code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module
// TODO: Basically translate what you did in the lab into Verilog
module DFlipFlop (clk, in, out, clr, pre, S);
parameter n = 4;
input clk;
input [n-1:0] in;
input [n-1:0] S;
//input clr;
//input pre;
output [n-1:0] out;
reg [n-1:0] out;
always @ (posedge clk)
out = in;
// Connecting the DFF back to the adder
wire [3:0] B;
wire [1:0] Cout;
Adder addThem (out, B, 1'b0, Cout, S);
endmodule
| 6.61756 |
module Adder(input [3:0] A, B, input carryIn, output carryOut, output [3:0] summation);
wire [3:0] t;
wire cin1, cin2, cin3, cin4;
// Adding the bits of A and B together
xor xorGateOne(t[0], carryIn, B[0]);
xor xorGateTwo(t[1], carryIn, B[1]);
xor xorGateThree(t[2], carryIn, B[2]);
xor xorGateFour(t[3], carryIn, B[3]);
Full_Adder S0 (.A(A[0]), .B(t[0]), .c_in(carryIn), .c_out(cin1), .sum(summation[0]));
Full_Adder S1 (.A(A[1]), .B(t[1]), .c_in(cin1), .c_out(cin2), .sum(summation[1]));
Full_Adder S2 (.A(A[2]), .B(t[2]), .c_in(cin2), .c_out(cin3), .sum(summation[2]));
Full_Adder S3 (.A(A[3]), .B(t[3]), .c_in(cin3), .c_out(carryOut), .sum(summation[3]));
// Connecting the adder to the D Flip Flop
wire [3:0] transfer;
transfer[0] = summation[0];
transfer[1] = summation[1];
transfer[2] = summation[2];
transfer[3] = summation[3];
wire [3:0] Q;
// FIXME:
DFlipFlop DFF (3'b001, transfer, Q, 1'b1, 1'b1, summation);
endmodule
| 7.973868 |
module ALU_add #(
parameter DATA_WIDTH = 4
) (
input [DATA_WIDTH -1 : 0] operand1,
input [DATA_WIDTH -1 : 0] operand2,
output signed_overflow,
output unsigned_overflow,
output [DATA_WIDTH -1 : 0] result
);
// overflow and result
wire carry;
assign {carry, result[DATA_WIDTH -1 : 0]} = operand1[DATA_WIDTH -1 : 0] + operand2[DATA_WIDTH -1 : 0];
// unsigned_overflow
assign unsigned_overflow = carry;
endmodule
| 9.199104 |
module alu_adder (
input [31:0] A,
input [31:0] B,
output reg [31:0] C,
output reg zero
);
always @(*) begin
C = A + B;
if (C == 32'b0) zero = 1'b1;
else zero = 1'b0;
end
endmodule
| 6.784883 |
module W0RM_ALU_AddSub #(
parameter SINGLE_CYCLE = 0,
parameter DATA_WIDTH = 8
) (
input wire clk,
input wire data_valid,
input wire [3:0] opcode,
input wire [DATA_WIDTH-1:0] data_a,
data_b,
output wire [DATA_WIDTH-1:0] result,
output wire result_valid,
output wire [ 3:0] result_flags
);
localparam MSB = DATA_WIDTH - 1;
localparam ALU_OPCODE_ADD = 4'h8;
localparam ALU_OPCODE_SUB = 4'h9;
localparam ALU_FLAG_ZERO = 4'h0;
localparam ALU_FLAG_NEG = 4'h1;
localparam ALU_FLAG_OVER = 4'h2;
localparam ALU_FLAG_CARRY = 4'h3;
reg [DATA_WIDTH-1:0] result_r = 0, data_a_r = 0, data_b_r = 0;
reg flag_carry_r = 0, result_valid_r = 0;
wire [DATA_WIDTH-1:0] result_i;
wire flag_carry_i;
assign result_flags[ALU_FLAG_ZERO] = result_r == 0;
assign result_flags[ALU_FLAG_NEG] = result_r[MSB];
assign result_flags[ALU_FLAG_OVER] = ((~result_r[MSB]) && data_a_r[MSB] && data_b_r[MSB]) ||
(result_r[MSB] && (~data_a_r[MSB]) && (~data_b_r[MSB]));
assign result_flags[ALU_FLAG_CARRY] = flag_carry_r; // Carry generated by IP core
assign result = result_r;
assign result_valid = result_valid_r;
W0RM_Int_AddSub dsp_addsub (
.a(data_a),
.b(data_b),
.add(opcode == ALU_OPCODE_ADD),
.c_out(flag_carry_i),
.s(result_i)
);
generate
if (SINGLE_CYCLE) begin
always @(result_i, data_valid, data_a, data_b, flag_carry_i) begin
result_r = result_i;
result_valid_r = data_valid;
data_a_r = data_a;
data_b_r = data_b;
flag_carry_r = flag_carry_i;
end
end else begin
always @(posedge clk) begin
result_valid_r <= data_valid;
if (data_valid) begin
data_a_r <= data_a;
data_b_r <= data_b;
result_r <= result_i;
flag_carry_r <= flag_carry_i;
end
end
end
endgenerate
endmodule
| 6.950982 |
module ALU_AddSub_1_tb (
output wire done,
error
);
ALU_AddSub_base_tb #(
.DATA_WIDTH (32),
.FILE_SOURCE ("../testbench/data/core/ALU_AddSub_1_tb_data.txt"),
.FILE_COMPARE("../testbench/data/core/ALU_AddSub_1_tb_compare.txt")
) dut (
.done (done),
.error(error)
);
endmodule
| 6.845873 |
module ALU_AddSub_base_tb #(
parameter DATA_WIDTH = 8,
parameter FILE_SOURCE = "",
parameter FILE_COMPARE = ""
) (
output wire done,
error
);
localparam FLAGS_WIDTH = 4;
localparam OPCODE_WIDTH = 4;
localparam FS_DATA_WIDTH = (2 * DATA_WIDTH) + OPCODE_WIDTH + 1;
localparam FC_DATA_WIDTH = FLAGS_WIDTH + DATA_WIDTH;
reg clk = 0;
reg fs_go = 0;
wire fs_done;
wire valid;
wire [DATA_WIDTH-1:0] data_a, data_b;
wire [ 3:0] opcode;
wire result_valid;
wire [ DATA_WIDTH-1:0] result;
wire [FLAGS_WIDTH-1:0] result_flags;
always #2.5 clk <= ~clk;
initial #50 fs_go <= 1'b1;
FileSource #(
.DATA_WIDTH(FS_DATA_WIDTH),
.FILE_PATH (FILE_SOURCE)
) source (
.clk (clk),
.ready(fs_go),
.valid(valid),
.empty(fs_done),
.data ({data_valid, opcode, data_a, data_b})
);
FileCompare #(
.DATA_WIDTH(FC_DATA_WIDTH),
.FILE_PATH (FILE_COMPARE)
) compare (
.clk (clk),
.valid(result_valid),
.data ({result_flags, result}),
.done (done),
.error(error)
);
W0RM_ALU_AddSub #(
.SINGLE_CYCLE(1),
.DATA_WIDTH (DATA_WIDTH)
) dut (
.clk(clk),
.data_valid(valid & data_valid),
.opcode(opcode),
.data_a(data_a),
.data_b(data_b),
.result(result),
.result_valid(result_valid),
.result_flags(result_flags)
);
endmodule
| 7.506481 |
module alu_add_1bit (
A,
B,
CI,
S,
CO
);
//port definitions
input wire A, B, CI;
output wire S, CO;
// instantiate module's hardware
assign S = (A & ~B & ~CI) | (~A & B & ~CI) | (~A & ~B & CI) | (A & B & CI);
assign CO = (B & CI) | (A & CI) | (A & B);
endmodule
| 7.60109 |
module alu_add_2bit (
A,
B,
CI,
S,
CO
);
//port definitions
input wire CI;
input wire [1:0] A, B;
output wire [1:0] S;
output wire CO;
// extra useful wires
wire carry_out_0, carry_in_1;
// instantiate module's hardware
assign carry_in_1 = carry_out_0;
alu_add_1bit ADD_0 (
.A (A[0]),
.B (B[0]),
.CI(CI),
.S (S[0]),
.CO(carry_out_0)
);
alu_add_1bit ADD_1 (
.A (A[1]),
.B (B[1]),
.CI(carry_in_1),
.S (S[1]),
.CO(CO)
);
endmodule
| 7.333868 |
module alu_add_4bit (
A,
B,
CI,
S,
CO
);
//port definitions
input wire CI;
input wire [3:0] A, B;
output wire [3:0] S;
output wire CO;
// extra useful wires
wire carry_out_01, carry_in_23;
// instantiate module's hardware
assign carry_in_23 = carry_out_01;
alu_add_2bit ADD_01 (
.A (A[1:0]),
.B (B[1:0]),
.CI(CI),
.S (S[1:0]),
.CO(carry_out_01)
);
alu_add_2bit ADD_23 (
.A (A[3:2]),
.B (B[3:2]),
.CI(carry_in_23),
.S (S[3:2]),
.CO(CO)
);
endmodule
| 7.185375 |
module alu_add_4bit_2 (
A,
B,
CI,
S,
CO
);
//port definitions
input wire CI;
input wire [3:0] A, B;
output wire [3:0] S;
output wire CO;
// extra useful wires
wire [3:0] g; // generate wires
wire [3:0] p; // propogate wires
wire [4:0] c; // carry wires
// instantiate module's hardware
// assign carry in and carry out
assign c[0] = CI;
assign CO = c[4];
// calculate generate and propogate signals
assign g = A & B;
assign p = A ^ B;
// calculate c
assign c[1] = g[0] | p[0] & c[0];
assign c[2] = g[1] | p[1] & g[0] | &p[1:0] & c[0];
assign c[3] = g[2] | p[2] & g[1] | &p[2:1] & g[0] | &p[2:0] & c[0];
assign c[4] = g[3] | p[3] & g[2] | &p[3:2] & g[1] | &p[3:1] & g[0] | &p[3:0] & c[0];
// calculate outputs
assign S = p ^ c[3:0];
endmodule
| 7.165054 |
module alu_add_4bit_2_test;
reg [3:0] A;
reg [3:0] B;
reg CI;
wire [3:0] S;
wire CO;
// testbench variables
reg [3:0] i;
reg [3:0] j;
reg [4:0] desired_sum;
wire [3:0] desired_output;
wire desired_carry_out;
alu_add_4bit_2 uut (
.A (A),
.B (B),
.CI(CI),
.S (S),
.CO(CO)
);
// Caculate the desired output and carry out
assign desired_output = desired_sum[3:0];
assign desired_carry_out = desired_sum[4];
initial begin
// Insert the dumps here
$dumpfile("alu_add_4bit_2_test.vcd");
$dumpvars(0, alu_add_4bit_2_test);
// Initialize Inputs
A = 4'b0000;
B = 4'b0000;
CI = 1'b0;
j = 4'h0;
i = 4'h0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for (i = 0; i < 16; i = i + 1) begin
// set A equal to i and B to j
A = i;
B = j;
// Calculate the desired sum
desired_sum = (i + j);
#1000; // gate delay time?
// Display the results
$display("CarryIn: %d; Inputs: %d, %d; Output: %d; CarryOut: %d", CI, A, B, S, CO);
$display("Sum: %d; Output should be %d; Carry should be: %d", desired_sum, desired_output,
desired_carry_out);
$display("\n");
// Increment j counter
j = j + 1;
end
$finish;
end
endmodule
| 7.165054 |
module alu_add_4bit_test;
reg [3:0] A;
reg [3:0] B;
reg CI;
wire [3:0] S;
wire CO;
// testbench variables
reg [3:0] i;
reg [3:0] j;
reg [4:0] desired_sum;
wire [3:0] desired_output;
wire desired_carry_out;
alu_add_4bit uut (
.A (A),
.B (B),
.CI(CI),
.S (S),
.CO(CO)
);
// Caculate the desired output and carry out
assign desired_output = desired_sum[3:0];
assign desired_carry_out = desired_sum[4];
initial begin
// Insert the dumps here
$dumpfile("alu_add_4bit_test.vcd");
$dumpvars(0, alu_add_4bit_test);
// Initialize Inputs
A = 4'b0000;
B = 4'b0000;
CI = 1'b0;
j = 4'h0;
i = 4'h0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for (i = 0; i < 16; i = i + 1) begin
// set A equal to i and B to j
A = i;
B = j;
// Calculate the desired sum
desired_sum = (i + j);
#100;
// Display the results
$display("CarryIn: %d; Inputs: %d, %d; Output: %d; CarryOut: %d", CI, A, B, S, CO);
$display("Sum: %d; Output should be %d; Carry should be: %d", desired_sum, desired_output,
desired_carry_out);
$display("\n");
// Increment j counter
j = j + 1;
end
$finish;
end
endmodule
| 7.165054 |
module alu_add_only (
in_a,
in_b,
add_out
);
input [31:0] in_a, in_b;
output [31:0] add_out;
assign add_out = in_a + in_b;
endmodule
| 8.733442 |
module alu_and (
A,
B,
Z
);
// parameter definitions
parameter WIDTH = 8;
//port definitions
input wire [WIDTH-1:0] A, B;
output wire [WIDTH-1:0] Z;
// instantiate module's hardware
assign Z = A & B;
endmodule
| 9.185003 |
module AndModule (
bigMuxIn3,
inA,
inB
);
output [15:0] bigMuxIn3;
input [15:0] inA;
input [15:0] inB;
and (bigMuxIn3[0], inA[0], inB[0]);
and (bigMuxIn3[1], inA[1], inB[1]);
and (bigMuxIn3[2], inA[2], inB[2]);
and (bigMuxIn3[3], inA[3], inB[3]);
and (bigMuxIn3[4], inA[4], inB[4]);
and (bigMuxIn3[5], inA[5], inB[5]);
and (bigMuxIn3[6], inA[6], inB[6]);
and (bigMuxIn3[7], inA[7], inB[7]);
and (bigMuxIn3[8], inA[8], inB[8]);
and (bigMuxIn3[9], inA[9], inB[9]);
and (bigMuxIn3[10], inA[10], inB[10]);
and (bigMuxIn3[11], inA[11], inB[11]);
and (bigMuxIn3[12], inA[12], inB[12]);
and (bigMuxIn3[13], inA[13], inB[13]);
and (bigMuxIn3[14], inA[14], inB[14]);
and (bigMuxIn3[15], inA[15], inB[15]);
endmodule
| 8.287566 |
module: alu_and_test
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_and_test;
// parameter
parameter WIDTH = 32;
// test module variables
reg [WIDTH-1:0] i;
// Inputs
reg [WIDTH-1:0] A;
reg [WIDTH-1:0] B;
// Outputs
wire [WIDTH-1:0] Z;
// Instantiate the Unit Under Test (UUT)
alu_and #(.N(WIDTH)) uut (
.A(A),
.B(B),
.Z(Z)
);
initial begin
// Insert the dumps here
$dumpfile("alu_and_test.vcd");
$dumpvars(0, alu_and_test);
// Initialize Inputs
i = 32'h0x0;
A = 32'h0x0;
B = 32'h0x0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for (i = 0; i < 16; i = i + 1) begin
#100;
A = i;
B = ~i;
$display("Inputs: %b, %b ; Output: %b", A, B, Z);
end
$finish;
end
endmodule
| 7.671632 |
module ALU_A_MUX (
input ALUSrcA,
input [31:0] Data1, //ԼĴ
input [ 4:0] Data2, //saֻ5λҪ0չ
output [31:0] result
);
assign result = (ALUSrcA == 0 ? Data1 : {{27{0}}, Data2[4:0]});
endmodule
| 6.848388 |
module ALU_B (
input wire [ `icodeBus] icode,
input wire [ `ifunBus] ifun,
input wire [`digitsBus] valB,
output reg [`digitsBus] ALUB
);
always @(*) begin
case ({
icode, 4'h0
})
`rrmovq: begin
ALUB <= 0;
end
`rmmovq: begin
ALUB <= valB;
end
`mrmovq: begin
ALUB <= valB;
end
`addq: begin
ALUB <= valB;
end
`ret: begin
ALUB <= valB;
end
`popq: begin
ALUB <= valB;
end
`pushq: begin
ALUB <= valB;
end
`call: begin
ALUB <= valB;
end
`irmovq: begin
if (ifun == 4'h0) begin
ALUB <= 0;
end else begin
ALUB <= valB;
end
end
endcase
end
endmodule
| 6.769681 |
module ALU_barrel (
input clk,
input S,
input [31:0] Shift_Data,
input [7:0] Shift_Num,
input [2:0] Shift_op,
input [31:0] A,
input [ 3:0] ALU_op,
output wire [31:0] F
);
wire [31:0] B;
wire Shift_carry_out;
wire [3:0] NZCV;
Barrel_Shift shift (
Shift_Data,
Shift_Num,
NZCV[1],
Shift_op,
B,
Shift_carry_out
);
ALU_Main ALU (
clk,
S,
B,
A,
ALU_op,
Shift_carry_out,
NZCV[1],
NZCV[0],
F,
NZCV
);
endmodule
| 8.218655 |
module alu_base (
input clock,
input alu_base_enable,
input [ 2:0] funct3,
input [31:0] rs1_value,
input [31:0] rs2_value,
output reg [31:0] rd_value
);
parameter [2:0] ADD = 3'h0;
parameter [2:0] SLL = 3'h1;
parameter [2:0] SLT = 3'h2;
parameter [2:0] SLTU = 3'h3;
parameter [2:0] XOR = 3'h4;
parameter [2:0] SRL = 3'h5;
parameter [2:0] OR = 3'h6;
parameter [2:0] AND = 3'h7;
always @(posedge clock & alu_base_enable) begin
case (funct3)
ADD: rd_value <= rs1_value + rs2_value;
SLL: rd_value <= rs1_value << rs2_value;
SLT: rd_value <= $signed(rs1_value) < $signed(rs2_value) ? `ONE : `ZERO;
SLTU: rd_value <= rs1_value < rs2_value ? `ONE : `ZERO;
XOR: rd_value <= rs1_value ^ rs2_value;
SRL: rd_value <= rs1_value >> rs2_value;
OR: rd_value <= rs1_value | rs2_value;
AND: rd_value <= rs1_value & rs2_value;
default: rd_value <= `ZERO;
endcase
end
always @(posedge clock & !alu_base_enable) begin
rd_value <= `HIGH_IMPEDANCE;
end
endmodule
| 8.207996 |
module ALU_basic (
input wire opA,
wire opB,
input wire [3:0] S ,
input wire M,
Cin,
output reg DO ,
output reg CO
);
reg p;
reg g;
always @(*) begin
p = ~(S[0] & (~opA) & (~opB) | S[1] & (~opA) & opB | S[2] & opA & (~opB) | S[3] & opA & opB);
DO = p ^ Cin;
g = S[3] & opA & opB | S[2] & opA & (~opB) | (~M);
CO = g | (p & Cin);
end
endmodule
| 7.459917 |
module ALU_basic_tb ();
reg clk_1Hz;
reg opA, opB;
reg [3:0] S ;
reg M;
reg Cin;
wire DO, CO;
ALU_basic u0 (
opA,
opB,
S,
M,
Cin,
DO,
CO
);
always #100 clk_1Hz = ~clk_1Hz;
initial begin
clk_1Hz = 0;
#200;
Cin = 1'b1;
M = 1'b0;
opA = 1'b1;
opB = 1'b0;
S = 4'b0000;
#200;
S = 4'b0001;
#200;
S = 4'b0010;
#200;
S = 4'b0011;
#200;
S = 4'b0100;
#200;
S = 4'b0101;
#200;
S = 4'b0110;
#200;
S = 4'b0111;
#200;
S = 4'b1000;
#200;
S = 4'b1001;
#200;
S = 4'b1010;
#200;
S = 4'b1011;
#200;
S = 4'b1100;
#200;
S = 4'b1101;
#200;
S = 4'b1110;
#200;
S = 4'b1111;
#200;
Cin = 1'b0;
M = 1'b1;
S = 4'b1001;
#200;
opA = 1'b1;
opB = 1'b1;
#200;
Cin = 1'b1;
S = 4'b0110;
#200;
opA = 1'b1;
opB = 1'b0;
#200;
opA = 1'b0;
opB = 1'b1;
end
endmodule
| 6.527365 |
module top_data_alu (
input [15:0] data,
//input push,
input reset,
input [2:0] load,
output [15:0] alu_out
//output zr,
//output ng
);
wire [5:0] opcode;
wire [15:0] x, y;
data my_data (
.data(data),
//.push(push), //BTND
.reset(reset),
.load(load),
.x(x),
.y(y),
.opcode(opcode)
);
ALU_case ALU (
.c (opcode),
.x (x),
.y (y),
.out(alu_out),
.zr (zr),
.ng (ng)
);
endmodule
| 7.34271 |
module alu_behav (
busOut,
zero,
overflow,
carry,
neg,
busA,
busB,
control
);
output reg [31:0] busOut;
output reg zero, overflow, carry, neg;
input [31:0] busA, busB;
input [2:0] control;
wire [31:0] adderBusB;
reg [31:0] sltBus; //For flags on SLT subtraction
// state encoding
parameter [2:0] NOP = 3'b000, ADD = 3'b001, SUB = 3'b010, AND = 3'b011,
OR = 3'b100, XOR = 3'b101, SLT = 3'b110, SLL = 3'b111;
// flip the bits input to the adder if in subtraction mode
assign adderBusB = control[1] ? ~busB : busB;
// 8 control modes
always @(*) begin
case (control)
NOP: begin
busOut <= 32'b0;
carry <= 1'b0;
overflow <= 1'b0;
end
ADD: begin
{carry, busOut} <= busA + adderBusB + control[1];
overflow <= (busA[31] & adderBusB[31] & ~busOut[31]) | (~busA[31] & ~adderBusB[31] & busOut[31]);
end
SUB: begin
{carry, busOut} <= busA + adderBusB + control[1];
overflow <= (busA[31] & adderBusB[31] & ~busOut[31]) | (~busA[31] & ~adderBusB[31] & busOut[31]);
end
AND: begin
busOut <= busA & busB;
carry <= 1'b0;
overflow <= 1'b0;
end
OR: begin
busOut <= busA | busB;
carry <= 1'b0;
overflow <= 1'b0;
end
XOR: begin
busOut <= busA ^ busB;
carry <= 1'b0;
overflow <= 1'b0;
end
SLT: begin
busOut <= (busA < busB) ? 32'b1 : 32'b0;
{carry, sltBus} <= busA + adderBusB + control[1];
overflow <= (busA[31] & adderBusB[31] & ~sltBus[31]) | (~busA[31] & ~adderBusB[31] & sltBus[31]);
end
SLL: begin
{carry, busOut} <= {1'b0, busA} << busB[1:0];
overflow <= busA[31] ^ busOut[31];
end
endcase
end
// zero and negative status flag
always @(*) begin
zero = ~|busOut;
neg = busOut[31];
end
endmodule
| 6.538166 |
module Alu (
Z,
A,
B,
INST,
SEL
);
output [31:0] Z;
input signed [31:0] A;
input signed [31:0] B;
input [3:0] INST;
input SEL;
reg [31:0] Z;
always @(A or B or INST or SEL) begin
case (INST)
4'b0000: Z = A + B;
4'b0001: Z = 32'h00000001 + ~A;
4'b0010: Z = A & B;
4'b0011: Z = A | B;
4'b0100: Z = A ^ B;
4'b0101: Z = ~A;
4'b0110: begin
if (SEL) Z = B;
else Z = A;
end
4'b0111: begin
if (SEL) Z = A;
else Z = B;
end
4'b1000: Z = A - B;
4'b1001: Z = {31'b0, A < B};
4'b1010: Z = {31'b0, A <= B};
4'b1011: Z = {31'b0, A > B};
4'b1100: Z = {31'b0, A >= B};
4'b1101: Z = {31'b0, A == B};
4'b1110: Z = {31'b0, A != B};
4'b1111: Z = {31'b0, SEL ^ B};
default: Z = 32'b0;
endcase
end
endmodule
| 7.167973 |
module: ALU_beh
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALU_beh_testbench;
// Inputs
reg [3:0] A_in;
reg [3:0] B_in;
reg [1:0] Sel_in;
// Outputs
wire [3:0] Y_out;
// Instantiate the Unit Under Test (UUT)
ALU_beh uut (
.A_in(A_in[3:0]),
.B_in(B_in[3:0]),
.Sel_in(Sel_in[1:0]),
.Y_out(Y_out[3:0])
);
initial begin
// Initialize Inputs
A_in = 5;
B_in = 4;
Sel_in = 0;
// Wait 100 ns for global reset to finish
#100;
Sel_in = 1;
#100;
Sel_in = 2;
#100;
Sel_in = 3;
#100;
// Add stimulus here
end
endmodule
| 6.656036 |
module ALU_behav (
ADin,
BDin,
ALU_ctr,
Result,
Overflow,
Carry_in,
Carry_out,
Zero
);
parameter n = 32, Ctr_size = 4;
input Carry_in;
input [Ctr_size-1:0] ALU_ctr;
input [n-1:0] ADin, BDin;
output [n-1:0] Result;
reg [n-1:0] Result, tmp;
output Carry_out, Overflow, Zero;
reg Carry_out, Overflow, Zero;
always @(ALU_ctr or ADin or BDin or Carry_in) begin
case (ALU_ctr)
`ADD: begin
{Carry_out, Result} = ADin + BDin + Carry_in;
Overflow = ADin[n-1] & BDin[n-1] & ~Result[n-1] | ~ADin[n-1] & ~BDin[n-1] & Result[n-1];
end
`ADDU: {Overflow, Result} = ADin + BDin + Carry_in;
`SUB: begin
{Carry_out, Result} = ADin - BDin;
Overflow = ADin[n-1] & ~BDin[n-1] & Result[n-1] | ~ADin[n-1] & BDin[n-1] & ~Result[n-1];
end
`SUBU: {Overflow, Result} = ADin - BDin;
`SLT: begin
{Carry_out, tmp} = ADin - BDin;
Overflow = ADin[n-1] & ~BDin[n-1] & ~tmp[n-1] | ~ADin[n-1] & BDin[n-1] & tmp[n-1];
$display("\nSLT:- [%d] tmp = %d [%b]; Cout=%b, Ovf=%b; A=%d, B=%d", $time, tmp, tmp,
Carry_out, Overflow, ADin, BDin);
Result = tmp[n-1] ^ Overflow;
$display("\nSLT:+R=%d [%b]", Result, Result);
end
`SLTU: begin
{Carry_out, tmp} = ADin - BDin;
$display("SLTU:- [%d] tmp = %d [%b]; Cout=%b, Ovf=%b; A=%d, B=%d", $time, tmp, tmp,
Carry_out, Overflow, ADin, BDin);
Result = Carry_out;
$display("SLTU:+R=%d [%b]", Result, Result);
end
`OR: Result = ADin | BDin;
`AND: Result = ADin & BDin;
`XOR: Result = ADin ^ BDin;
`NOP: Result = ADin;
`SLL: Result = ADin << BDin;
`SRL: Result = ADin >> BDin;
`SRA: Result = $signed(ADin) >>> BDin;
`BNE: if ((ADin - BDin) != 0) Result = 0; // Branch if not equal
`NOP: Result = 1'bZ;
endcase
Zero = ~|Result; // Result = 32'b0
end
/* always @ (Result)
begin
$display("%0d\t ADin = %0d BDin = %0d; Result = %0d; Cout = %b Ovfl = %b Zero = %b OP = %b", $time, ADin, BDin, Result, Carry_out, Overflow, Zero, ALU_ctr );
end
*/
endmodule
| 7.545058 |
module TestALU;
// parameter n = 32, Ctr_size = 4;
// reg [n-1:0] A, B, T;
// wire [n-1:0] R, tt;
// reg Carry_in;
// wire Carry_out, Overflow, Zero;
// reg [Ctr_size-1:0] ALU_ctr;
// integer num;
// ALU_behav ALU( A, B, ALU_ctr, R, Overflow, Carry_in, Carry_out, Zero );
// always @( R or Carry_out or Overflow or Zero )
// begin
// $display("%0d\tA = %0d B = %0d; R = %0d; Cout = %b Ovfl = %b Zero = %b OP = %b n = %d", $time, A, B, R, Carry_out, Overflow, Zero, ALU_ctr, num );
// num = num + 1;
// end
// initial begin
// #0 num = 0; Carry_in = 0;
// #1 A = 101; B = 0; ALU_ctr = `NOP;
// #10 A = 10; B = 10; ALU_ctr = `ADD;
// #10 A = 10; B = 20; ALU_ctr = `ADDU;
// #10 A = 10; B = 20; ALU_ctr = `SLT;
// #10 A = 10; B = 20; ALU_ctr = `SLTU;
// #10 A = 32'hffffffff; B = 1; ALU_ctr = `ADDU;
// #10 A = 10; B = 10; ALU_ctr = `ADDU;
// #10 A = 10; B = 10; ALU_ctr = `SUB;
// #10 A = 1; B = 1; ALU_ctr = `SUBU;
// #10 A = 10; B = 10; ALU_ctr = `SUB;
// #10 A = 10; B = 10; ALU_ctr = `SUBU;
// #10 A = -13; B = -12; ALU_ctr = `SLT;
// #100 $finish;
// end
// endmodule
| 6.634616 |
module mux32two (
i0,
i1,
sel,
out
);
input [31:0] i0, i1;
input sel;
output [31:0] out;
assign out = sel ? i1 : i0;
endmodule
| 8.056899 |
module add32 (
i0,
i1,
sum
);
input [31:0] i0, i1;
output [31:0] sum;
assign sum = i0 + i1;
endmodule
| 7.919421 |
module sub32 (
i0,
i1,
diff
);
input [31:0] i0, i1;
output [31:0] diff;
assign diff = i0 - i1;
endmodule
| 6.776614 |
module mul16 (
i0,
i1,
prod
);
input [15:0] i0, i1;
output [31:0] prod;
// this is a magnitude multiplier
// signed arithmetic later
assign prod = i0 * i1;
endmodule
| 7.398946 |
module mux32three (
i0,
i1,
i2,
sel,
out
);
input [31:0] i0, i1, i2;
input [1:0] sel;
output [31:0] out;
reg [31:0] out;
always @(i0 or i1 or i2 or sel) begin
case (sel)
2'b00: out = i0;
2'b01: out = i1;
2'b10: out = i2;
default: out = 32'bx;
endcase
end
endmodule
| 7.380275 |
module alu (
a,
b,
f,
r
);
input [31:0] a, b;
input [2:0] f;
output [31:0] r;
wire [31:0] addmux_out, submux_out;
wire [31:0] add_out, sub_out, mul_out;
mux32two adder_mux (
.i0 (b),
.i1 (32'd1),
.sel(f[0]),
.out(addmux_out)
);
mux32two sub_mux (
.i0 (b),
.i1 (32'd1),
.sel(f[0]),
.out(submux_out)
);
add32 our_adder (
.i0 (a),
.i1 (addmux_out),
.sum(add_out)
);
sub32 our_subtracter (
.i0 (a),
.i1 (submux_out),
.diff(sub_out)
);
mul16 our_multiplier (
.i0 (a[15:0]),
.i1 (b[15:0]),
.prod(mul_out)
);
mux32three output_mux (
.i0 (add_out),
.i1 (sub_out),
.i2 (mul_out),
.sel(f[2:1]),
.out(r)
);
endmodule
| 6.634214 |
module alu_bit_select (
bsel,
bs_out_high,
bs_out_low
);
input wire [2:0] bsel;
output wire [3:0] bs_out_high;
output wire [3:0] bs_out_low;
wire [3:0] bs_out_high_ALTERA_SYNTHESIZED;
wire [3:0] bs_out_low_ALTERA_SYNTHESIZED;
wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_13;
wire SYNTHESIZED_WIRE_14;
assign bs_out_low_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14;
assign bs_out_low_ALTERA_SYNTHESIZED[1] = bsel[0] & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14;
assign bs_out_low_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_12 & bsel[1] & SYNTHESIZED_WIRE_14;
assign bs_out_low_ALTERA_SYNTHESIZED[3] = bsel[0] & bsel[1] & SYNTHESIZED_WIRE_14;
assign bs_out_high_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & bsel[2];
assign bs_out_high_ALTERA_SYNTHESIZED[1] = bsel[0] & SYNTHESIZED_WIRE_13 & bsel[2];
assign bs_out_high_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_12 & bsel[1] & bsel[2];
assign bs_out_high_ALTERA_SYNTHESIZED[3] = bsel[0] & bsel[1] & bsel[2];
assign SYNTHESIZED_WIRE_12 = ~bsel[0];
assign SYNTHESIZED_WIRE_13 = ~bsel[1];
assign SYNTHESIZED_WIRE_14 = ~bsel[2];
assign bs_out_high = bs_out_high_ALTERA_SYNTHESIZED;
assign bs_out_low = bs_out_low_ALTERA_SYNTHESIZED;
endmodule
| 7.674859 |
module alu_blk (
input wire clk,
input wire reset,
input wire [15:0] reg16,
input wire [7:0] reg8,
input wire [7:0] mem8,
input wire [7:0] io8,
input wire [2:0] op,
input wire [1:0] latch_op,
input wire [7:0] flags_in,
output reg [7:0] flags_out,
output reg do_loop
);
parameter FLAG_S = 7; // sign flag
parameter FLAG_Z = 6; // zero flag
parameter FLAG_F5 = 5; // bit 5
parameter FLAG_H = 4; // half carry flag
parameter FLAG_F3 = 3; // bit 3
parameter FLAG_PV = 2; // parity/overflow
parameter FLAG_N = 1; // op was sub
parameter FLAG_C = 0; // carry
wire flag_s, flag_z, flag_f5, flag_h, flag_f3, flag_pv, flag_n, flag_c;
assign flag_s = flags_in[FLAG_S];
assign flag_z = flags_in[FLAG_Z];
assign flag_f5 = flags_in[FLAG_F5];
assign flag_h = flags_in[FLAG_H];
assign flag_f3 = flags_in[FLAG_F3];
assign flag_pv = flags_in[FLAG_PV];
assign flag_n = flags_in[FLAG_N];
assign flag_c = flags_in[FLAG_C];
reg [7:0] data;
reg [4:0] tmp5;
reg [7:0] tmp8;
reg [8:0] tmp9;
reg HF;
`include "ucode_consts.vh"
always @(posedge clk) begin
if (reset) begin
data <= 8'h00;
end else begin
case (latch_op)
VAL_BLK_LATCH_DATA: data <= mem8;
VAL_BLK_LATCH_IO: data <= io8;
endcase
end
end
reg [7:0] n;
reg [8:0] k;
reg p;
always @(*) begin
case (op)
VAL_BLK_OP_LD: begin
// inputs: latched data, live reg16 containing BC, live reg8 containing A
n = data + reg8;
flags_out = {flag_s, flag_z, n[1], 1'b0, n[3], reg16 != 0, 1'b0, flag_c};
do_loop = flags_out[FLAG_PV];
end
VAL_BLK_OP_CP: begin
// inputs: latched data, live reg16 containing BC, live reg8 containing A
tmp9 = reg8 - data;
tmp8 = reg8[6:0] - data[6:0];
tmp5 = reg8[3:0] - data[3:0];
HF = tmp5[4];
n = reg8 - data - HF;
// flag_s, flag_z, flag_f5, flag_h, flag_f3, flag_pv, flag_n, flag_c
flags_out = {tmp9[7], tmp9[7:0] == 0, n[1], HF, n[3], reg16 != 0, 1'b1, flag_c};
do_loop = flags_out[FLAG_PV] && !flags_out[FLAG_Z];
end
VAL_BLK_OP_OUT: begin
// inputs: latched data, live reg16 containing BC, live reg8 containing L
// tricky: flags from dec B already in flags
k = data + reg8;
p = !(^((k[7:0] & 8'b111) ^ reg16[15:8]));
// flag_s, flag_z, flag_f5, flag_h, flag_f3, flag_pv, flag_n, flag_c
flags_out = {flag_s, flag_z, flag_f5, k[8], flag_f3, p, data[7], k[8]};
do_loop = !flags_out[FLAG_Z];
end
VAL_BLK_OP_INI: begin
// inputs: latched data, live reg16 containing BC, live reg8 containing L
// tricky: flags from dec B already in flags
k = data + ((reg16[7:0] + 1) & 8'b11111111);
p = !(^((k[7:0] & 8'b111) ^ reg16[15:8]));
// flag_s, flag_z, flag_f5, flag_h, flag_f3, flag_pv, flag_n, flag_c
flags_out = {flag_s, flag_z, flag_f5, k[8], flag_f3, p, data[7], k[8]};
do_loop = !flags_out[FLAG_Z];
end
VAL_BLK_OP_IND: begin
// inputs: latched data, live reg16 containing BC, live reg8 containing L
// tricky: flags from dec B already in flags
k = data + ((reg16[7:0] - 1) & 8'b11111111);
p = !(^((k[7:0] & 8'b111) ^ reg16[15:8]));
// flag_s, flag_z, flag_f5, flag_h, flag_f3, flag_pv, flag_n, flag_c
flags_out = {flag_s, flag_z, flag_f5, k[8], flag_f3, p, data[7], k[8]};
do_loop = !flags_out[FLAG_Z];
end
default: begin
flags_out = 8'bX;
end
endcase
end
endmodule
| 7.526326 |
module alu_block (
reg_in1,
reg_in2,
sub_nadd,
alu_out
);
input [7:0] reg_in1;
input [7:0] reg_in2;
input sub_nadd;
output [8:0] alu_out;
//reg [8:0] alu_out;
wire [7:0] xor_out;
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : SUB_BLOCK
xor xor_u1 (xor_out[i], reg_in2[i], sub_nadd);
end
endgenerate
CLA8bit cla8bit_u1 (
.in1 (reg_in1),
.in2 (xor_out),
.sum (alu_out[7:0]),
.cin (sub_nadd),
.cout(alu_out[8])
);
endmodule
| 6.802042 |
module ALU_BLOCK_Test (
reset,
switch_val,
load_dest,
load_src,
load_op,
Disp1,
Disp2,
Disp3,
Disp4,
Flags
);
input wire reset;
input wire [9:0] switch_val;
reg [15:0] Dest;
reg [15:0] Src;
output wire [0:6] Disp1;
output wire [0:6] Disp2;
output wire [0:6] Disp3;
output wire [0:6] Disp4;
output wire [4:0] Flags;
input load_dest;
input load_src;
input load_op;
reg [ 7:0] opcode;
wire [15:0] result;
ALU b2v_ALU_BLOCK (
.Rdest(Dest),
.Rsrc(Src),
.op(opcode),
.flags(Flags),
.result(result),
.reset(reset)
);
bcd_to_sev_seg b2v_inst (
.bcd(result[3:0]),
.seven_seg(Disp1)
);
bcd_to_sev_seg b2v_inst3 (
.bcd(result[7:4]),
.seven_seg(Disp2)
);
bcd_to_sev_seg b2v_inst4 (
.bcd(result[11:8]),
.seven_seg(Disp3)
);
bcd_to_sev_seg b2v_inst5 (
.bcd(result[15:12]),
.seven_seg(Disp4)
);
always @(negedge load_dest) begin
Dest[9:0] = switch_val[9:0];
end
always @(negedge load_src) begin
Src[9:0] = switch_val[9:0];
end
always @(negedge load_op) begin
opcode[7:0] = switch_val[7:0];
end
endmodule
| 7.576463 |
module alu_boolean_20 (
input [15:0] a,
input [15:0] b,
input [3:0] alufn,
output reg [15:0] out
);
always @* begin
case (alufn[0+3-:4])
4'h8: begin
out = a & b;
end
4'he: begin
out = a | b;
end
4'h6: begin
out = a ^ b;
end
4'ha: begin
out = a;
end
4'h1: begin
out = ~(a & b);
end
4'hf: begin
out = ~(a | b);
end
4'h7: begin
out = ~(a ^ b);
end
4'h4: begin
out = {~a[15+0-:1], a[0+14-:15]};
end
4'hb: begin
out = {1'h0, a[0+14-:15]};
end
default: begin
out = 16'h0000;
end
endcase
end
endmodule
| 6.735649 |
module alu_branch (
input wire [5:0] alu_opcode,
input wire [31:0] in_s1,
input wire [31:0] in_s2,
input wire [15:0] offset,
input wire [31:0] pc,
input wire g_t,
input wire nop,
input wire enable,
output reg zero,
output reg [31:0] out_pc
);
wire [31:0] offset_ext;
sign_extender sign_extender (
.imm_val(offset),
.ctrl(1'b1),
.out_val(offset_ext)
);
always @(*) begin
if (enable == 1) begin
if (!nop) begin
case (alu_opcode)
6'b000001: begin
if (g_t == 1) begin
zero = (in_s1 >= 0) ? 1 : 0;
end else begin
zero = (in_s1 < 0) ? 1 : 0;
end
out_pc = pc + 4 + (offset_ext << 2);
end
6'b000100: begin
if (in_s1 == in_s2) begin
zero = 1;
end else begin
zero = 0;
end
out_pc = pc + 4 + (offset_ext << 2);
end
6'b000101: begin
if (in_s1 != in_s2) begin
zero = 1;
end else begin
zero = 0;
end
out_pc = pc + 4 + (offset_ext << 2);
end
`blez: begin
if (in_s1 <= 0) begin
zero = 1;
end else begin
zero = 0;
end
out_pc = pc + 4 + (offset_ext << 2);
end
`bgtz: begin
if (in_s1 > 0) begin
zero = 1;
end else begin
zero = 0;
end
out_pc = pc + 4 + (offset_ext << 2);
end
default: $display("not a branch");
endcase
//out_pc = pc + offset_ext;
end
end
end
endmodule
| 6.556047 |
module alu_B_mux (
input alub_sel,
input [31:0] rD2,
input [31:0] ext,
output reg [31:0] B
);
always @(*) begin
case (alub_sel)
'b0: B = rD2;
'b1: B = ext;
default: ;
endcase
end
endmodule
| 7.05293 |
module ALU_Cell_16bit (
A,
B,
FS,
Z,
C,
N,
V,
F
);
input wire [15:0] A;
input wire [15:0] B;
input wire [4:0] FS;
output wire Z;
output wire C;
output wire N;
output wire V;
output wire [15:0] F;
wire [15:0] F_ALTERA_SYNTHESIZED;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
assign V = 0;
assign SYNTHESIZED_WIRE_4 = 0;
ALU_Cell_4bit b2v_inst (
.C_in(SYNTHESIZED_WIRE_0),
.A_from_next_bit(A[4]),
.A(A[3:0]),
.B(B[3:0]),
.FS(FS),
.C_out(SYNTHESIZED_WIRE_1),
.F(F_ALTERA_SYNTHESIZED[3:0])
);
ALU_Cell_4bit b2v_inst1 (
.C_in(SYNTHESIZED_WIRE_1),
.A_from_next_bit(A[8]),
.A(A[7:4]),
.B(B[7:4]),
.FS(FS),
.C_out(SYNTHESIZED_WIRE_2),
.F(F_ALTERA_SYNTHESIZED[7:4])
);
ALU_Cell_4bit b2v_inst2 (
.C_in(SYNTHESIZED_WIRE_2),
.A_from_next_bit(A[12]),
.A(A[11:8]),
.B(B[11:8]),
.FS(FS),
.C_out(SYNTHESIZED_WIRE_3),
.F(F_ALTERA_SYNTHESIZED[11:8])
);
ALU_Cell_4bit b2v_inst3 (
.C_in(SYNTHESIZED_WIRE_3),
.A_from_next_bit(SYNTHESIZED_WIRE_4),
.A(A[15:12]),
.B(B[15:12]),
.FS(FS),
.C_out(C),
.F(F_ALTERA_SYNTHESIZED[15:12])
);
Zero_Check b2v_inst5 (
.F(F_ALTERA_SYNTHESIZED),
.Z(Z)
);
Cin_logic b2v_inst6 (
.FS0(FS[0]),
.FS1(FS[1]),
.FS2(FS[2]),
.FS3(FS[3]),
.C0 (SYNTHESIZED_WIRE_0)
);
assign N = F_ALTERA_SYNTHESIZED[15];
assign F = F_ALTERA_SYNTHESIZED;
endmodule
| 7.07117 |
module alu_cntl (
iInstFunct,
iALUOp,
oOp
);
input iInstFunct;
input iALUOp;
output oOp;
wire [ 5:0] iInstFunct;
wire [ 1:0] iALUOp;
reg [`ALU_CNTL_OP_W-1 : 0] oOp;
parameter ALUOP_ADD = 6'h22;
parameter ALUOP_SUB = 6'h26;
parameter ALUOP_AND = 6'h24;
parameter ALUOP_OR = 6'h25;
parameter ALUOP_SLT = 6'h2A;
parameter ALUOP_BEQ = 6'h16;
parameter ALUOP_LW = 6'h00;
parameter ALUOP_SW = 6'h10;
always @(iInstFunct or iALUOp) begin
casex ({
iALUOp, iInstFunct
})
8'b00??????: oOp = 6'h02; //Add operation
8'b01??????: oOp = 6'h06; //Substract operation
8'b10000000: oOp = 6'h02; //R-format Nop
8'b10100000: oOp = 6'h02; //R-format Add
8'b10100010: oOp = 6'h06; //R-format Sub
8'b10100100: oOp = 6'h00; //R-format And
8'b10100101: oOp = 6'h01; //R-format Or
8'b10101010: oOp = 6'h07; //R-format Slt
default: $display("%m Error encoding in alu_cntl", $time);
endcase
end
endmodule
| 6.545752 |
module ALU_come (
ALU_income,
ALU_outcome,
ALU_oppend,
ALU_funct,
ALU_sa,
ALU_HI,
ALU_LO
);
input [31:0] ALU_income;
input [1:0] ALU_oppend;
input [5:0] ALU_funct;
input [4:0] ALU_sa;
input [31:0] ALU_HI, ALU_LO;
output reg [31:0] ALU_outcome;
always @(*) begin
if (ALU_oppend == 2'b10) begin
case (ALU_funct[5:2])
4'b0000: begin
case (ALU_funct[1:0])
2'b00: ALU_outcome = ALU_income << ALU_sa;
2'b10: ALU_outcome = ALU_income >> ALU_sa;
2'b11:
ALU_outcome = ((ALU_income[31] * 32'hffffffff) & (~(32'hffffffff >> ALU_sa))) | (ALU_income >> ALU_sa);
default: ALU_outcome = ALU_income;
endcase
end
4'b0100: begin
case (ALU_funct[1:0])
2'b00: ALU_outcome = ALU_HI;
2'b10: ALU_outcome = ALU_LO;
default: ALU_outcome = ALU_income;
endcase
end
default: ALU_outcome = ALU_income;
endcase
end else ALU_outcome = ALU_income;
end
endmodule
| 6.956112 |
module alu_compare_20 (
input [1:0] alufn,
input z,
input v,
input n,
output reg [15:0] cmp
);
always @* begin
case (alufn)
2'h1: begin
cmp[0+0-:1] = z;
end
2'h2: begin
cmp[0+0-:1] = n ^ v;
end
2'h3: begin
cmp[0+0-:1] = z | (n ^ v);
end
endcase
cmp[1+14-:15] = 15'h0000;
end
endmodule
| 6.512678 |
module alu_compare_21 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
out = 16'h0000;
case (alufn)
6'h33: begin
out[0+0-:1] = (a == b);
end
6'h35: begin
out[0+0-:1] = (a < b);
end
6'h37: begin
out[0+0-:1] = (a <= b);
end
default: begin
out[0+0-:1] = 1'h0;
end
endcase
end
endmodule
| 6.512678 |
module ALU_CONT (
aluOp,
funCode,
aluFunc
);
input [3:0] funCode;
input [2:0] aluOp;
output reg [2:0] aluFunc;
always @(*) begin
case (aluOp)
3'b000: begin
if (funCode == 4'b0000) aluFunc = 3'b000;
if (funCode == 4'b0001) aluFunc = 3'b001;
if (funCode == 4'b0100) aluFunc = 3'b100;
if (funCode == 4'b0101) aluFunc = 3'b101;
end
3'b010: aluFunc = 3'b010;
3'b011: aluFunc = 3'b011;
3'b100: aluFunc = 3'b000;
default: aluFunc = 3'b000;
endcase
end
endmodule
| 7.446792 |
module ALU_control (
input [5:0] FunctCode,
input [2:0] ALUOpIn,
output reg [2:0] signal
);
always @* begin
case (ALUOpIn)
3'b111:
case (FunctCode)
6'b100000: signal = 3'b000;
6'b100010: signal = 3'b001;
6'b100100: signal = 3'b010;
6'b100101: signal = 3'b011;
6'b101010: signal = 3'b100;
6'b000000: signal = 3'b101;
default: signal = 3'b101;
endcase
3'b101: signal = 3'b000; //addi
3'b100: signal = 3'b101; //slti
3'b011: signal = 3'b100; //andi
3'b010: signal = 3'b011; //ori
3'b001: signal = 3'b000; //lw y sw
3'b000: signal = 3'b010; //beq
endcase
end
endmodule
| 7.483671 |
module alu_control_2 (
input [31:0] instruction,
input [ 1:0] alu_op,
output [ 3:0] ALU_select
);
wire [2:0] Func3 = instruction[14:12];
wire [6:0] Func7 = instruction[31:25];
wire [3:0] alu_select0 = {Func7[5], Func3};
wire [3:0] alu_select1 = {(~Func3[1] & Func3[0]) & Func7[5], Func3};
Mux_4 #(
.WORD_WIDTH(4)
) GPR_WriteData_Mux (
.a0(alu_select0),
.a1(alu_select1),
.a2(4'b0),
.a3(4'b0),
.select(alu_op),
.mux_out(ALU_select)
);
endmodule
| 7.641617 |
module: alu_control
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_control_tb;
// Inputs
reg [1:0] ALUOp;
reg [5:0] funct;
// Outputs
wire [2:0] operation;
// Instantiate the Unit Under Test (UUT)
alu_control uut (
.ALUOp(ALUOp),
.funct(funct),
.operation(operation)
);
initial begin
// Initialize Inputs
ALUOp = 2'b00;
funct = 4'b0000;
// Wait 100 ns for global reset to finish
#100;
ALUOp = 2'b01;
#100;
ALUOp[1] = 1'b1;
funct = 4'b0000;
#100;
ALUOp[1] = 1'b1;
funct[3:0] = 4'b0010;
#100;
ALUOp[1] = 1'b1;
funct[3:0] = 4'b0100;
#100;
ALUOp[1] = 1'b1;
funct[3:0] = 4'b0101;
#100;
ALUOp[1] = 1'b1;
funct[3:0] = 4'b1010;
#100;
// Add stimulus here
end
endmodule
| 6.672598 |
module ALU_control_unit_tb;
wire [3:0] ALUoperation; // output: ALU control signal
reg [5:0] func; // input: function
reg [1:0] ALUop; // input: ALUop
reg addi; // input: addi
reg clk; // clock
// instantiate DUT (device under test)
ALU_control_unit DUT (
ALUop,
addi,
func,
ALUoperation
);
// generate a clock pulse
always #10 clk = ~clk;
// set inputs
initial begin
$timeformat(-9, 1, " ns", 6);
clk = 1'b0;
addi = 1'b0; // switch function
func = 4'b0010; // sub
ALUop = 2'b01; // beq
// lw & sw
@(negedge clk) ALUop = 2'b00;
// R-type
@(negedge clk) ALUop = 2'b11;
end
// display inputs and outputs
always @(ALUop or func or addi)
#1
$display(
"At t=%t ALUop=%b func=%b addi=%b ALUoperation=%b", $time, ALUop, func, addi, ALUoperation
);
endmodule
| 7.040309 |
module alu_core (
cy_in,
S,
V,
R,
op1,
op2,
cy_out,
vf_out,
result
);
input wire cy_in;
input wire S;
input wire V;
input wire R;
input wire [3:0] op1;
input wire [3:0] op2;
output wire cy_out;
output wire vf_out;
output wire [3:0] result;
wire [3:0] result_ALTERA_SYNTHESIZED;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_5;
wire SYNTHESIZED_WIRE_3;
assign cy_out = SYNTHESIZED_WIRE_3;
alu_slice b2v_alu_slice_bit_0 (
.cy_in(cy_in),
.op1(op1[0]),
.op2(op2[0]),
.S(S),
.V(V),
.R(R),
.result(result_ALTERA_SYNTHESIZED[0]),
.cy_out(SYNTHESIZED_WIRE_0)
);
alu_slice b2v_alu_slice_bit_1 (
.cy_in(SYNTHESIZED_WIRE_0),
.op1(op1[1]),
.op2(op2[1]),
.S(S),
.V(V),
.R(R),
.result(result_ALTERA_SYNTHESIZED[1]),
.cy_out(SYNTHESIZED_WIRE_1)
);
alu_slice b2v_alu_slice_bit_2 (
.cy_in(SYNTHESIZED_WIRE_1),
.op1(op1[2]),
.op2(op2[2]),
.S(S),
.V(V),
.R(R),
.result(result_ALTERA_SYNTHESIZED[2]),
.cy_out(SYNTHESIZED_WIRE_5)
);
alu_slice b2v_alu_slice_bit_3 (
.cy_in(SYNTHESIZED_WIRE_5),
.op1(op1[3]),
.op2(op2[3]),
.S(S),
.V(V),
.R(R),
.result(result_ALTERA_SYNTHESIZED[3]),
.cy_out(SYNTHESIZED_WIRE_3)
);
assign vf_out = SYNTHESIZED_WIRE_3 ^ SYNTHESIZED_WIRE_5;
assign result = result_ALTERA_SYNTHESIZED;
endmodule
| 7.386554 |
module ALU_Core_1_tb (
output wire done,
error
);
ALU_Core_base_tb #(
.DATA_WIDTH (32),
.FILE_SOURCE ("../testbench/data/core/ALU_Core_1_tb_data.txt"),
.FILE_COMPARE("../testbench/data/core/ALU_Core_1_tb_compare.txt")
) dut (
.done (done),
.error(error)
);
endmodule
| 6.786737 |
module ALU_Core_base_tb #(
parameter DATA_WIDTH = 32,
parameter FILE_SOURCE = "",
parameter FILE_COMPARE = ""
) (
output wire done,
error
);
localparam FLAGS_WIDTH = 4;
localparam OPCODE_WIDTH = 4;
localparam FS_DATA_WIDTH = (2 * DATA_WIDTH) + OPCODE_WIDTH + 2;
localparam FC_DATA_WIDTH = DATA_WIDTH;
reg clk = 0;
reg fs_go = 0;
reg fs_pause = 1;
reg first_run = 1;
wire fs_done;
reg alu_ready_r = 0;
wire valid;
wire [DATA_WIDTH-1:0] data_a, data_b;
wire [ 3:0] opcode;
wire result_valid;
wire [ DATA_WIDTH-1:0] result;
wire [FLAGS_WIDTH-1:0] result_flags;
always #2.5 clk <= ~clk;
initial #50 fs_pause <= 1'b0;
/*
always @(posedge clk)
begin
if (fs_pause)
begin
fs_go <= 0;
end
else
begin
if (first_run)
begin
if (fs_go)
begin
fs_go <= 0;
first_run <= 0;
end
else
begin
fs_go <= 1;
end
end
else
begin
fs_go <= alu_ready;
end
end
end // */
always @(posedge clk) alu_ready_r <= alu_ready;
FileSource #(
.DATA_WIDTH(FS_DATA_WIDTH),
.FILE_PATH (FILE_SOURCE)
) source (
.clk (clk),
.ready(alu_ready && ~fs_pause),
.valid(fs_valid),
.empty(fs_done),
.data ({data_valid, ext_8_16, opcode, data_a, data_b})
);
FileCompare #(
.DATA_WIDTH(FC_DATA_WIDTH),
.FILE_PATH (FILE_COMPARE)
) compare (
.clk (clk),
.valid(result_valid),
.data (result),
.done (done),
.error(error)
);
W0RM_Core_ALU #(
.SINGLE_CYCLE(1),
.DATA_WIDTH (DATA_WIDTH)
) dut (
.clk(clk),
.flush(1'b0),
.mem_ready(1'b1),
.alu_ready(alu_ready),
.data_valid((fs_valid || ~alu_ready_r) && data_valid),
.opcode(opcode),
.store_flags_mask(4'h0),
.ext_bit_size(ext_8_16),
.data_a(data_a),
.data_b(data_b),
.result(result),
.result_valid(result_valid),
.flag_zero(flag_zero),
.flag_negative(flag_negative),
.flag_overflow(flag_overflow),
.flag_carry(flag_carry)
);
endmodule
| 7.579277 |
module ALU_CPU (
input clk_i,
input rst_i,
input inst_ack_i,
input [17:0] IR,
input int_req,
input int_en,
input data_ack_i,
input port_ack_i,
output reg [2:0] state_out,
next_state_out
);
localparam [2:0] misc_fn_wait = 3'b100;
localparam [2:0] misc_fn_stby = 3'b101;
localparam [1:0] mem_fn_ldm = 2'b00;
localparam [1:0] mem_fn_stm = 2'b01;
localparam [1:0] mem_fn_inp = 2'b10;
localparam [1:0] mem_fn_out = 2'b11;
parameter [2:0] fetch_state = 3'b000,
decode_state = 3'b001,
execute_state = 3'b010,
mem_state = 3'b011,
write_back_state = 3'b100,
int_state = 3'b101;
reg [2:0] state, next_state;
assign IR_decode_mem = IR[17:16] == 2'b10;
assign IR_decode_jump = IR[17:13] == 5'b11110;
assign IR_decode_branch = IR[17:12] == 6'b111110;
assign IR_decode_misc = IR[17:11] == 7'b1111110;
assign IR_misc_fn = IR[10:8];
assign IR_mem_fn = IR[15:14];
always @* begin
case (state)
fetch_state:
if (!inst_ack_i) next_state = fetch_state;
else next_state = decode_state;
decode_state:
if (IR_decode_branch || IR_decode_jump || IR_decode_misc) begin
if(IR_decode_misc && (IR_misc_fn == misc_fn_wait || IR_misc_fn == misc_fn_stby)
&& !(int_en && int_req))
next_state = decode_state;
else if (int_en && int_req) next_state = int_state;
else next_state = fetch_state;
end else next_state = execute_state;
execute_state:
if (IR_decode_mem) begin
if ((IR_mem_fn == mem_fn_ldm || IR_mem_fn == mem_fn_stm) && !data_ack_i)
next_state = mem_state;
else if ((IR_mem_fn == mem_fn_inp || IR_mem_fn == mem_fn_out) && !port_ack_i)
next_state = mem_state;
else if (IR_mem_fn == mem_fn_ldm || IR_mem_fn == mem_fn_inp) next_state = write_back_state;
else if (int_en && int_req) next_state = int_state;
else next_state = fetch_state;
end else next_state = write_back_state;
mem_state:
if ((IR_mem_fn == mem_fn_ldm || IR_mem_fn == mem_fn_stm) && !data_ack_i)
next_state = mem_state;
else if ((IR_mem_fn == mem_fn_inp || IR_mem_fn == mem_fn_out) && !port_ack_i)
next_state = mem_state;
else if (IR_mem_fn == mem_fn_ldm || IR_mem_fn == mem_fn_inp) next_state = write_back_state;
else if (int_en && int_req) next_state = int_state;
else next_state = fetch_state;
write_back_state:
if (int_en && int_req) next_state = int_state;
else next_state = fetch_state;
int_state: next_state = fetch_state;
endcase
state_out <= state;
next_state_out <= next_state;
end
always @(posedge clk_i or posedge rst_i) begin
if (rst_i) state <= fetch_state;
else state <= next_state;
end
endmodule
| 8.137589 |
module ALU_CPU_tb ();
reg clk_i;
reg rst_i;
reg inst_ack_i;
reg [17:0] IR;
reg int_req;
reg int_en;
reg data_ack_i;
reg port_ack_i;
wire [2:0] state_out, next_state_out;
ALU_CPU test (
.clk_i(clk_i),
.rst_i(rst_i),
.inst_ack_i(inst_ack_i),
.IR(IR),
.int_req(int_req),
.int_en(int_en),
.data_ack_i(data_ack_i),
.port_ack_i(port_ack_i),
.state_out(state_out),
.next_state_out(next_state_out)
);
initial begin
clk_i = 0;
forever #10 clk_i = ~clk_i;
end
initial begin
rst_i = 1;
#5 rst_i = 0;
inst_ack_i = 1;
IR = 18'b111000000010001100;
int_req = 1;
int_en = 1;
data_ack_i = 1;
port_ack_i = 1;
#100 $stop;
end
endmodule
| 6.633548 |
module alu_ctl (
ALUOp,
Funct,
ALUOperation
);
input [1:0] ALUOp;
input [5:0] Funct;
output [2:0] ALUOperation;
reg [2:0] ALUOperation;
// symbolic constants for instruction function code
parameter F_mfhi = 6'd16;
parameter F_mflo = 6'd18;
parameter F_add = 6'd32;
parameter F_sub = 6'd34;
parameter F_and = 6'd36;
parameter F_or = 6'd37;
parameter F_slt = 6'd42;
// symbolic constants for ALU Operations
parameter ALU_add = 3'b010;
parameter ALU_sub = 3'b110;
parameter ALU_and = 3'b000;
parameter ALU_or = 3'b001;
parameter ALU_slt = 3'b111;
always @(ALUOp or Funct) begin
case (ALUOp)
2'b00: ALUOperation = ALU_add;
2'b01: ALUOperation = ALU_sub;
2'b10:
case (Funct)
F_mfhi: ALUOperation = ALU_add;
F_mflo: ALUOperation = ALU_add;
F_add: ALUOperation = ALU_add;
F_sub: ALUOperation = ALU_sub;
F_and: ALUOperation = ALU_and;
F_or: ALUOperation = ALU_or;
F_slt: ALUOperation = ALU_slt;
default ALUOperation = 3'bxxx;
endcase
default ALUOperation = 3'bxxx;
endcase
end
endmodule
| 9.078723 |
module alu_ctrl (
input [2:0] funct3,
input [6:0] funct7,
input [1:0] aluCtrlOp,
// I 型指令类型的判断信号 itype。
// 如果是 itype 信号等于“1”，操作码直接由 funct3 和高位补“0”组成；
// 如果不是 I 型指令，ALU 操作码则要由 funct3 和 funct7 的第五位组成
input itype,
// 输出一个4位的ALU操作信号aluOp
output reg [3:0] aluOp
);
always @(*) begin
case (aluCtrlOp)
2'b00: aluOp <= `ALU_OP_ADD; // Load or Store
// 当 aluCtrlOp 等于（01）时，需要根据 funct3 和 funct7 产生 ALU 的操作码
2'b01: begin
if (itype & funct3[1:0] != 2'b01) aluOp <= {1'b0, funct3};
else aluOp <= {funct7[5], funct3}; // normal ALUI/ALUR
end
2'b10: begin
// $display("~~~aluCtrl bxx~~~%d", funct3);
case (funct3) // bxx
`BEQ_FUNCT3: aluOp <= `ALU_OP_EQ;
`BNE_FUNCT3: aluOp <= `ALU_OP_NEQ;
`BLT_FUNCT3: aluOp <= `ALU_OP_SLT;
`BGE_FUNCT3: aluOp <= `ALU_OP_GE;
`BLTU_FUNCT3: aluOp <= `ALU_OP_SLTU;
`BGEU_FUNCT3: aluOp <= `ALU_OP_GEU;
default: aluOp <= `ALU_OP_XXX;
endcase
end
default: aluOp <= `ALU_OP_XXX;
endcase
end
endmodule
| 9.229055 |
module alu_ctrler (
alu_op,
func,
alu_ctrl
); // 入出力ポート
input [2:0] alu_op; // 入力 3-bit メイン制御回路からの制御入力
input [5:0] func; // 入力 6-bit R 形式、function フィールド
output [3:0] alu_ctrl; // 出力 4-bit y
reg [3:0] y;
always @(alu_op or func) begin
case (alu_op)
3'b000: begin
y = `ALU_CTRL_ADD; // I 形式 LW, SW 用
end
3'b001: begin
y = `ALU_CTRL_LUI; // I 形式 LUI 用
end
3'b010: begin // R 形式
if (func == 6'b100000) begin // func=ADD
y = `ALU_CTRL_ADD;
end else if (func == 6'b100001) begin // func=ADDU
y = `ALU_CTRL_ADD;
end else if (func == 6'b100010) begin // func=SUB
y = `ALU_CTRL_SUB;
end else if (func == 6'b100011) begin // func=SUBU
y = `ALU_CTRL_SUB;
end else if (func == 6'b100100) begin // func=AND
y = `ALU_CTRL_AND;
end else if (func == 6'b100101) begin // func=OR
y = `ALU_CTRL_OR;
end else if (func == 6'b101010) begin // func=SLT
y = `ALU_CTRL_SLT;
end else if (func == 6'b001001) begin // func=JALR
y = `ALU_CTRL_ADD;
end else if (func == 6'b001000) begin // func=JR
y = `ALU_CTRL_ADD;
end else if (func == 6'b001000) begin // func=NOR
y = `ALU_CTRL_NOR;
end else if (func == 6'b001000) begin // func=XOR
y = `ALU_CTRL_XOR;
end else if (func == 6'b000000) begin // func=SLL
y = `ALU_CTRL_SLL;
end else if (func == 6'b000010) begin // func=SRL
y = `ALU_CTRL_SRL;
end else if (func == 6'b000100) begin // func=SLLV
y = `ALU_CTRL_SLL;
end else if (func == 6'b000110) begin // func=SRLV
y = `ALU_CTRL_SRL;
end else if (func == 6'b000011) begin // func=SRA
y = `ALU_CTRL_SRA;
end else if (func == 6'b000111) begin // func=SRAV
y = `ALU_CTRL_SRA;
end else if (func == 6'b101011) begin // func=SLTU
y = `ALU_CTRL_SLTU;
// 実験 9 のヒント（１２）：実行する命令が mult, mflo 命令のとき、mult, mflo 命令用の ALU 制御コードを生成する処理の記述
end else if (func == 6'b010010) begin // func=MFLO
y = `ALU_CTRL_MFLO;
end else if (func == 6'b011000) begin // func=MULT
y = `ALU_CTRL_MULT;
end else if (func == 6'b011011) begin // func=DIVU
y = `ALU_CTRL_DIVU;
end else if (func == 6'b010000) begin // func=MUHI
y = `ALU_CTRL_MFHI;
end else begin
y = 3'b000;
end
end
3'b011: begin
y = `ALU_CTRL_AND; // I 形式 ANDI 用
end
3'b100: begin
y = `ALU_CTRL_OR; // I 形式 ORI 用
end
3'b101: begin
y = `ALU_CTRL_XOR; // I 形式 XORI 用
end
3'b110: begin
y = `ALU_CTRL_SLT; // I 形式 SLTI 用
end
default: begin // 3'b111: begin
y = `ALU_CTRL_SLTU; // I 形式 SLTIU 用
end
endcase
end
assign alu_ctrl = y;
endmodule
| 7.911449 |
module ALU_CU (
ALUOp,
Func,
Operation
);
input [1:0] ALUOp;
input [3:0] Func;
output [3:0] Operation;
wire w1, w2, w3, w4, ALUOp0_inv, Func0_inv, Func2_inv;
not G0 (ALUOp0_inv, ALUOp[0]);
not G1 (Func0_inv, Func[0]);
not G2 (Func2_inv, Func[2]);
and G3 (Operation[0], ALUOp[1], ALUOp0_inv, Func[1], Func0_inv);
and G4 (w1, ALUOp[1], ALUOp0_inv, Func[1], Func[2]);
not G5 (Operation[1], w1);
and G6 (w2, Func2_inv, Func[1]);
or G7 (w3, Func[3], w2);
and G8 (w4, ALUOp[1], ALUOp0_inv, w3);
or G9 (Operation[2], w4, ALUOp[0]);
assign Operation[3] = 0;
endmodule
| 6.84921 |
module ALUData1Mux (
input [31:0] data_from_reg_i, // Data from the register.
input [31:0] data_from_shift_i, // Data from the shift amount.
input use_shift_ctrl_i, // Control flag:
// 0 -> data from register
// 1 -> data from shift amount.
output [31:0] data_o // The output data.
);
assign data_o = (use_shift_ctrl_i ? data_from_shift_i : data_from_reg_i);
endmodule
| 7.280684 |
module ALUData2Mux (
input [31:0] data_from_reg_i, // Data from the register.
input [31:0] data_from_sign_extend_i, // Data from the sign extend oper.
input use_sign_extend_ctrl_i, // Control flag:
// 0 -> data from register
// 1 -> data from sign extend
output [31:0] data_o // The output data.
);
assign data_o = (use_sign_extend_ctrl_i ? data_from_sign_extend_i : data_from_reg_i);
endmodule
| 7.176445 |
module alu_dec(
input wire [5:0] funct,
input wire [1:0] aluop,
output wire [2:0] alucontrol
);
// assign alucontrol = (aluop == 2'b00)? 3'b010:
// (aluop == 2'b01)? 3'b110:
// (aluop == 2'b10)?
// (funct == 6'b100000) ? 3'b010:
// (funct == 6'b100010) ? 3'b110:
// (funct == 6'b100100) ? 3'b000:
// (funct == 6'b100101) ? 3'b001:
// (funct == 6'b101010) ? 3'b111:
// 3'b000 : 3'b000;
//endmodule
| 7.639372 |
module ALU_Decoder #(
parameter Funct_width = 6,
ALU_OP_width = 2,
ALU_Control_width = 3
) (
input wire [ Funct_width-1:0] Funct,
input wire [ALU_OP_width-1:0] ALUOp,
output reg [ALU_Control_width-1:0] ALUControl
);
localparam [Funct_width-1:0] add = 'b10_0000;
localparam [Funct_width-1:0] sub = 'b10_0010;
localparam [Funct_width-1:0] slt = 'b10_1010;
localparam [Funct_width-1:0] mul = 'b01_1100;
//localparam [Funct_width-1:0] And = 'b10_0100;
//localparam [Funct_width-1:0] OR = 'b10_0101;
always @(*) begin
case (ALUOp)
2'b00: begin
ALUControl = 'b010;
end
2'b01: begin
ALUControl = 'b100;
end
2'b10: begin
case (Funct)
add: begin
ALUControl = 3'b010;
end
sub: begin
ALUControl = 3'b100;
end
slt: begin
ALUControl = 3'b110;
end
mul: begin
ALUControl = 3'b101;
end
default: begin
ALUControl = 3'b010;
end
endcase
end
2'b11: begin
ALUControl = 3'b010;
end
default: begin
ALUControl = 3'b010;
end
endcase
end
endmodule
| 7.842781 |
module: ALU_Decoder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALU_Decoder_Test;
// Inputs
reg [4:0] Funct40;
reg ALUOp;
// Outputs
wire [1:0] ALUControl;
wire [1:0] FlagW;
// Instantiate the Unit Under Test (UUT)
ALU_Decoder uut (
.Funct40(Funct40),
.ALUOp(ALUOp),
.ALUControl(ALUControl),
.FlagW(FlagW)
);
initial begin
// Initialize Inputs
Funct40 = 0;
ALUOp = 0;
#100;
Funct40 = 5'b01000;
ALUOp = 1;
#100;
Funct40 = 5'b01001;
#100;
Funct40 = 5'b00100;
#100;
Funct40 = 5'b00101;
#100;
Funct40 = 5'b00000;
#100;
Funct40 = 5'b00001;
#100;
Funct40 = 5'b11000;
#100;
Funct40 = 5'b11001;
end
endmodule
| 6.724468 |
module ALU_Design (
input [31:0] dina,
input [31:0] dinb,
input [ 3:0] aluc,
output reg [31:0] doutr,
output doutz, //0标志
output flag_of //flag overflow
);
//-------------------------------------------------------
wire [31:0] sum;
wire [31:0] sub;
wire [31:0] doutsh;
wire add_co;
wire sub_co;
wire right = (aluc == `ALUC_SRL) ? 1'b1 : 1'b0;
wire left = (aluc == `ALUC_SLL) ? 1'b1 : 1'b0;
//-------------------------------------------------------
//mux
always @(*) begin
case (aluc)
`ALUC_ADD: doutr = sum; //add
`ALUC_SUB: doutr = sub; //sub
`ALUC_AND: doutr = dina & dinb; //and
`ALUC_OR: doutr = dina | dinb; //or
`ALUC_XOR: doutr = dina ^ dinb; //xor
`ALUC_LUI: doutr = {dinb[15:0], 16'b0}; //lui 置高位立即数
`ALUC_SLL: doutr = doutsh; //sll 逻辑左移
`ALUC_SRL: doutr = doutsh; //srl 逻辑右移
`ALUC_SRA: doutr = doutsh; //sra 算术右移
default: doutr = 0;
endcase
end
assign doutz = (doutr == 32'b0) ? 1'b1 : 1'b0;
assign flag_of = add_co | sub_co;
//-------------------------------------------------------
//full_adder32
full_adder32 full_adder32_inst (
.dina(dina),
.dinb(dinb),
.cin (1'b0),
.sum (sum),
.cout(add_co) //溢出位
);
//-------------------------------------------------------
//full_sub32
full_adder32 full_sub32_inst (
.dina(dina),
.dinb(~dinb),
.cin (aluc[0]),
.sum (sub),
.cout(sub_co) //溢出位
);
//-------------------------------------------------------
//shift
shift shift_inst (
.dina (dina[4:0]),
.dinb (dinb),
.right (right),
.left (left),
.doutsh(doutsh)
);
endmodule
| 6.58604 |
module ALU_Design_Function (
input [`DATA_WIDTH-1:0] dina,
input [`DATA_WIDTH-1:0] dinb,
input [ 3:0] opcode,
output [`DATA_WIDTH-1:0] doutr,
output doutz, //0־
output flag_of //flag overflow
);
//------------------------------------------------------
assign {flag_of, doutr} = ALU_Design(dina, dinb, opcode);
assign doutz = (doutr == 'b0) ? 1'b1 : 1'b0;
function [`DATA_WIDTH:0] ALU_Design;
input [`DATA_WIDTH-1:0] dina;
input [`DATA_WIDTH-1:0] dinb;
input [3:0] opcode;
//-------------------------------------------------------
//mux
begin
case (opcode)
`ALUC_ADD: ALU_Design = dina + dinb + 1'b0; //add
`ALUC_SUB: ALU_Design = dina + ~dinb + 1'b1; //sub
`ALUC_AND: ALU_Design = dina & dinb; //and
`ALUC_OR: ALU_Design = dina | dinb; //or
`ALUC_XOR: ALU_Design = dina ^ dinb; //xor
//`ALUC_LUI: doutr = {dinb[3:0], 4'b0}; //lui øλ
`ALUC_LUI: ALU_Design = {dinb[1:0], 2'b0}; //lui øλ//س
`ALUC_SLL: ALU_Design = dinb << dina; //sll
`ALUC_SRL: ALU_Design = dinb >> dina; //srl
`ALUC_SRA: ALU_Design = $signed(dinb) >>> dina; //sra
default: ALU_Design = doutr;
endcase
end
endfunction
endmodule
| 7.410248 |
module ALU_Design_tb ();
reg [11:0] Datain;
reg reset;
reg clk;
wire [7:0] Y;
ALU_Design ALU (
Y,
Datain,
reset,
clk
);
initial begin
Datain = 12'b010001010010;
clk = 1;
reset = 0;
end
always #2 clk = ~clk;
initial begin
#50 Datain = 12'b010001010011;
#50 Datain = 12'b010001010001;
end
endmodule
| 6.560104 |
module alu_destination_decode (
instr,
rd,
we_reg
);
// Inputs
input [15:0] instr;
// Outputsn
output reg [2:0] rd;
output reg we_reg;
// Wires
wire [2:0] rd_imm, rd_reg, rd_ld_imm;
assign rd_imm = instr[7:5];
assign rd_reg = instr[4:2];
assign rd_ld_imm = instr[10:8];
// assigns
wire [6:0] op;
assign op = {instr[15:11], instr[1:0]};
always @(*) begin
casex (op)
/* Reg op */
7'b1101100: begin // ADD
rd = rd_reg;
we_reg = 1'b1;
end
7'b1101101: begin // SUB
rd = rd_reg;
we_reg = 1'b1;
end
7'b1101110: begin // OR
rd = rd_reg;
we_reg = 1'b1;
end
7'b1101111: begin // AND
rd = rd_reg;
we_reg = 1'b1;
end
7'b1101000: begin // ROL
rd = rd_reg;
we_reg = 1'b1;
end
7'b1101001: begin // SLL
rd = rd_reg;
we_reg = 1'b1;
end
7'b1101010: begin // ROR
rd = rd_reg;
we_reg = 1'b1;
end
7'b1101011: begin // SRA
rd = rd_reg;
we_reg = 1'b1;
end
7'b11100xx: begin // SEQ
rd = rd_reg;
we_reg = 1'b1;
end
7'b11101xx: begin // SLT
rd = rd_reg;
we_reg = 1'b1;
end
7'b11110xx: begin // SLE
rd = rd_reg;
we_reg = 1'b1;
end
7'b11111xx: begin // SCO
rd = rd_reg;
we_reg = 1'b1;
end
7'b11001xx: begin // BTR
rd = rd_reg;
we_reg = 1'b1;
end
/* Imm */
7'b01000xx: begin // ADDI
rd = rd_imm;
we_reg = 1'b1;
end
7'b01001xx: begin // SUBI
rd = rd_imm;
we_reg = 1'b1;
end
7'b01010xx: begin // ORI
rd = rd_imm;
we_reg = 1'b1;
end
7'b01011xx: begin // ANDI
rd = rd_imm;
we_reg = 1'b1;
end
7'b10100xx: begin // ROLI
rd = rd_imm;
we_reg = 1'b1;
end
7'b10101xx: begin // SLLI
rd = rd_imm;
we_reg = 1'b1;
end
7'b10110xx: begin // RORI
rd = rd_imm;
we_reg = 1'b1;
end
7'b10111xx: begin // SRAI
rd = rd_imm;
we_reg = 1'b1;
end
7'b10001xx: begin // LD
rd = rd_imm;
we_reg = 1'b1;
end
/* Load immediates (Rd is Rs here) */
7'b11000xx: begin // LBI
rd = rd_ld_imm;
we_reg = 1'b1;
end
7'b10010xx: begin // SLBI
rd = rd_ld_imm;
we_reg = 1'b1;
end
/* Write PC to R7 */
7'b00110xx: begin // JAL
rd = 3'd7;
we_reg = 1'b1;
end
7'b00111xx: begin // JALR
rd = 3'd7;
we_reg = 1'b1;
end
7'b10011xx: begin // STU
rd = rd_ld_imm;
we_reg = 1'b1;
end
/* No write */
7'b10000xx: begin // ST
rd = 3'd0;
we_reg = 1'b0;
end
7'b01100xx: begin // BEQZ
rd = 3'd0;
we_reg = 1'b0;
end
7'b01101xx: begin // BNEZ
rd = 3'd0;
we_reg = 1'b0;
end
7'b01111xx: begin // BLTZ
rd = 3'd0;
we_reg = 1'b0;
end
7'b00100xx: begin // JINST
rd = 3'd0;
we_reg = 1'b0;
end
7'b00101xx: begin // JR
rd = 3'd0;
we_reg = 1'b0;
end
7'b01110xx: begin // RET
rd = 3'd0;
we_reg = 1'b0;
end
7'b00010xx: begin // SIIC
rd = 3'd0;
we_reg = 1'b0;
end
7'b00011xx: begin // RTI
rd = 3'd0;
we_reg = 1'b0;
end
7'b00000xx: begin // HALT
rd = 3'd0;
we_reg = 1'b0;
end
7'b00001xx: begin // NOP;
rd = 3'd0;
we_reg = 1'b0;
end
default: begin
rd = 3'd0;
we_reg = 1'b0;
end
endcase
end
endmodule
| 6.739014 |
module ALU_display (
//entradas de la ALU
input [3:0] alu_in1,
alu_in2,
input [1:0] alu_selector,
input alu_switch1,
alu_switch2,
output [7:0] alu_out,
output [6:0] in1_units_display,
in1_decenas_display,
in2_units_display,
in2_decenas_display,
out_unit_display,
out_decenas_display,
out_centenas_display
);
ALU unidad_aritmetica_logica (
.num1(alu_in1),
.num2(alu_in2),
.operationSelect(alu_selector),
.shiftButton1(alu_switch1),
.shiftButton2(alu_switch2),
.result(alu_out)
);
wire [3:0] in1_unit = alu_in1 % 10;
wire [3:0] in1_decenas = alu_in1 / 10;
wire [3:0] in2_unit = alu_in2 % 10;
wire [3:0] in2_decenas = alu_in2 / 10;
wire [3:0] out_unit = alu_out % 10;
wire [3:0] out_decenas = (alu_out / 10) % 10;
wire [3:0] out_centenas = alu_out / 100;
BCD UNIDADES_ENTRADA1 (
.num(in1_unit),
.display7Segment(in1_units_display)
);
BCD DECENAS_ENTRADA1 (
.num(in1_decenas),
.display7Segment(in1_decenas_display)
);
BCD UNIDADES_ENTRADA2 (
.num(in2_unit),
.display7Segment(in2_units_display)
);
BCD DECENAS_ENTRADA2 (
.num(in2_decenas),
.display7Segment(in2_decenas_display)
);
BCD UNIDADES_SALIDA (
.num(out_unit),
.display7Segment(out_unit_display)
);
BCD DECENAS_SALIDA (
.num(out_decenas),
.display7Segment(out_decenas_display)
);
BCD CENTENAS_SALIDA (
.num(out_centenas),
.display7Segment(out_centenas_display)
);
endmodule
| 8.523294 |
module ALU_div #(
parameter DATA_WIDTH = 4
) (
input clk,
input enable,
output busy,
output divide_by_zero,
input [DATA_WIDTH - 1 : 0] operand1,
input [DATA_WIDTH - 1 : 0] operand2,
output [DATA_WIDTH - 1 : 0] result_div,
output [DATA_WIDTH - 1 : 0] result_mod
);
// divide by zero
assign divide_by_zero = enable & (operand2 == 0);
// remainder
reg [DATA_WIDTH - 1 : 0] remainder;
assign result_mod = remainder;
always @(posedge clk) begin
if (!enable || divide_by_zero) begin
remainder <= operand1;
end else begin
if (remainder >= operand2) begin
remainder <= remainder - operand2;
end else begin
remainder <= operand1;
end
end
end
// sum
// reg [DATA_WIDTH - 1 : 0] sum;
// assign result_mod = operand1 + operand2 - sum;
// always @(posedge clk) begin
// if (!enable || divide_by_zero) begin
// sum <= 0;
// end else begin
// if (sum < operand1) begin
// sum <= sum + operand2;
// end else begin
// sum <= 0;
// end
// end
// end
// quotient
reg [DATA_WIDTH - 1 : 0] quotient;
assign result_div = quotient;
always @(posedge clk) begin
if (!enable || divide_by_zero) begin
quotient <= 0;
end else begin
if (remainder >= operand2) begin
quotient <= quotient + 1'b1;
end else begin
quotient <= 0;
end
end
end
wire something;
assign something = remainder >= operand2;
// busy
assign busy = enable & (remainder >= operand2) & ~divide_by_zero;
endmodule
| 8.499804 |
module W0RM_ALU_DivRem #(
parameter SINGLE_CYCLE = 0,
parameter DATA_WIDTH = 8
) (
input wire clk,
input wire data_valid,
input wire [3:0] opcode,
input wire [DATA_WIDTH-1:0] data_a,
data_b,
output wire [DATA_WIDTH-1:0] result,
output wire result_valid,
output wire [ 3:0] result_flags
);
localparam MSB = DATA_WIDTH - 1;
localparam ALU_OPCODE_DIV = 4'h6;
localparam ALU_OPCODE_REM = 4'h7;
localparam ALU_FLAG_ZERO = 4'h0;
localparam ALU_FLAG_NEG = 4'h1;
localparam ALU_FLAG_OVER = 4'h2;
localparam ALU_FLAG_CARRY = 4'h3;
reg [DATA_WIDTH-1:0] result_r = 0, data_a_r = 0, data_b_r = 0;
reg [3:0] opcode_r = 0;
reg result_valid_r = 0;
wire result_valid_i;
wire [DATA_WIDTH-1:0] div_i, rem_i;
assign result_flags[ALU_FLAG_ZERO] = result_r == 0;
assign result_flags[ALU_FLAG_NEG] = result_r[MSB];
assign result_flags[ALU_FLAG_OVER] = ((~result_r[MSB]) && data_a_r[MSB] && data_b_r[MSB]) ||
(result_r[MSB] && (~data_a_r[MSB]) && (~data_b_r[MSB]));
assign result_flags[ALU_FLAG_CARRY] = 1'b0; // Carry not defined for DIV/REM
assign result = result_r;
assign result_valid = result_valid_r;
always @(posedge clk) begin
if (result_valid_i) begin
case (opcode_r)
ALU_OPCODE_DIV: begin
result_r <= div_i;
end
ALU_OPCODE_REM: begin
result_r <= rem_i;
end
default: begin
result_r <= 0;
end
endcase
end
if (data_valid) begin
data_a_r <= data_a;
data_b_r <= data_b;
opcode_r <= opcode;
end
result_valid_r <= result_valid_i;
end
W0RM_Static_Timer #(
.LOAD (0),
.LIMIT(47)
) valid_delay (
.clk(clk),
.start(data_valid),
.stop (result_valid_i)
);
W0RM_Int_Div div_rem (
.clk(clk),
.rfd(), // Ready-for-data
.dividend(data_a_r),
.divisor (data_b_r),
.quotient (div_i),
.fractional(rem_i)
);
endmodule
| 6.791546 |
module ALU_DivRem_1_tb (
output wire done,
error
);
ALU_DivRem_base_tb #(
.DATA_WIDTH (32),
.FILE_SOURCE ("../testbench/data/core/ALU_DivRem_1_tb_data.txt"),
.FILE_COMPARE("../testbench/data/core/ALU_DivRem_1_tb_compare.txt")
) dut (
.done (done),
.error(error)
);
endmodule
| 6.706171 |
module ALU_DivRem_base_tb #(
parameter DATA_WIDTH = 8,
parameter FILE_SOURCE = "",
parameter FILE_COMPARE = ""
) (
output wire done,
error
);
localparam FLAGS_WIDTH = 4;
localparam OPCODE_WIDTH = 4;
localparam FS_DATA_WIDTH = (2 * DATA_WIDTH) + OPCODE_WIDTH + 1;
localparam FC_DATA_WIDTH = (FLAGS_WIDTH - 1) + DATA_WIDTH;
reg clk = 0;
reg fs_go = 0;
reg fs_pause = 1;
reg first_run = 1;
wire fs_done;
wire valid;
wire [DATA_WIDTH-1:0] data_a, data_b;
wire [ 3:0] opcode;
wire result_valid;
wire [ DATA_WIDTH-1:0] result;
wire [FLAGS_WIDTH-1:0] result_flags;
always #2.5 clk <= ~clk;
//initial #50 fs_go <= 1'b1;
initial #50 fs_pause <= 1'b0;
always @(posedge clk) begin
if (fs_pause) begin
fs_go <= 0;
end else begin
if (first_run) begin
if (fs_go) begin
fs_go <= 0;
first_run <= 0;
end else begin
fs_go <= 1;
end
end else begin
fs_go <= result_valid;
end
end
end
FileSource #(
.DATA_WIDTH(FS_DATA_WIDTH),
.FILE_PATH (FILE_SOURCE)
) source (
.clk (clk),
.ready(fs_go),
.valid(valid),
.empty(fs_done),
.data ({data_valid, opcode, data_a, data_b})
);
FileCompare #(
.DATA_WIDTH(FC_DATA_WIDTH),
.FILE_PATH (FILE_COMPARE)
) compare (
.clk (clk),
.valid(result_valid),
.data ({result_flags[2:0], result}),
.done (done),
.error(error)
);
W0RM_ALU_DivRem #(
.SINGLE_CYCLE(0),
.DATA_WIDTH (DATA_WIDTH)
) dut (
.clk(clk),
.data_valid(valid & data_valid),
.opcode(opcode),
.data_a(data_a),
.data_b(data_b),
.result(result),
.result_valid(result_valid),
.result_flags(result_flags)
);
endmodule
| 6.831761 |
module alu_E (
input [31:0] SrcA,
input [31:0] SrcB,
input [4:0] Shift,
input [4:0] ALUop,
output [31:0] ALUresult,
output ov
);
`include "macros.v"
integer i;
reg [31:0] result;
reg [31:0] clz_temp;
reg V;
reg [32:0] ov_temp;
assign ALUresult = result;
assign ov = V;
initial begin
result = 0;
end
always @(*) begin
case (ALUop)
`alu_add: begin
ov_temp = {SrcA[31], SrcA} + {SrcB[31], SrcB};
V = ov_temp[32] ^ ov_temp[31];
result = ov_temp[31:0];
end
`alu_addu: begin
result = SrcA + SrcB;
end
`alu_sub: begin
ov_temp = {SrcA[31], SrcA} - {SrcB[31], SrcB};
V = ov_temp[32] ^ ov_temp[31];
result = ov_temp[31:0]; //˴Ӧòoverflow exception
end
`alu_subu: begin
result = SrcA - SrcB;
end
`alu_or: begin
result = SrcA | SrcB;
end
`alu_and: begin
result = SrcA & SrcB;
end
`alu_xor: begin
result = SrcA ^ SrcB;
end
`alu_nor: begin
result = ~(SrcA | SrcB);
end
`alu_sllv: begin
result = SrcB << SrcA[4:0];
end
`alu_sll: begin
result = SrcB << Shift;
end
`alu_srlv: begin
result = SrcB >> SrcA[4:0];
end
`alu_srl: begin
result = SrcB >> Shift;
end
`alu_srav: begin
result = $signed(SrcB) >>> SrcA[4:0];
end
`alu_sra: begin
result = $signed(SrcB) >>> Shift;
end
`alu_slt: begin
result = ($signed(SrcA) < $signed(SrcB)) ? 1 : 0;
end
`alu_sltu: begin
result = (SrcA < SrcB) ? 1 : 0;
end
`alu_clz: begin
i = 0;
clz_temp = SrcA;
while (clz_temp[31] == 0 && i <= 31) begin
i = i + 1;
clz_temp = SrcA << i;
end
result = i;
end
endcase
end
endmodule
| 6.873891 |
module ALU_ENCODER (
input wire [7:0] opcode,
output reg [3:0] encoded
);
parameter [7:0] ADD = 8'b00000101;
parameter [7:0] ADDU = 8'b00000110;
parameter [7:0] MUL = 8'b00001110;
parameter [7:0] SUB = 8'b00001001;
parameter [7:0] CMP = 8'b00001011;
parameter [7:0] AND = 8'b00000001;
parameter [7:0] OR = 8'b00000010;
parameter [7:0] XOR = 8'b00000011;
parameter [7:0] MOV = 8'b00001101;
parameter [7:0] LSH = 8'b10000100;
parameter [7:0] LOAD = 8'b01000000;
parameter [7:0] STOR = 8'b01000100;
parameter [7:0] JCOND = 8'b01001100;
parameter [7:0] JAL = 8'b01001000;
parameter [7:0] WAIT = 8'b00000000;
parameter [3:0] ADD_I = 4'b0101;
parameter [3:0] MUL_I = 4'b1110;
parameter [3:0] SUB_I = 4'b1001;
parameter [3:0] CMP_I = 4'b1011;
parameter [3:0] AND_I = 4'b0001;
parameter [3:0] OR_I = 4'b0010;
parameter [3:0] XOR_I = 4'b0011;
parameter [3:0] MOV_I = 4'b1101;
parameter [3:0] BCOND = 4'b1100;
parameter [6:0] LSH_I = 7'b1000000;
always @(opcode) begin
case (opcode)
ADD: encoded = 0;
ADDU: encoded = 1;
MUL: encoded = 2;
SUB: encoded = 3;
CMP: encoded = 4;
AND: encoded = 5;
OR: encoded = 6;
XOR: encoded = 7;
MOV: encoded = 8;
LSH: encoded = 9;
LOAD: encoded = 10;
STOR: encoded = 11;
JCOND: encoded = 13;
JAL: encoded = 14;
default: encoded = 15; // WAIT / NOP / Not Implemented
endcase
case (opcode[7:4])
ADD_I: encoded = 0;
MUL_I: encoded = 2;
SUB_I: encoded = 3;
CMP_I: encoded = 4;
AND_I: encoded = 5;
OR_I: encoded = 6;
XOR_I: encoded = 7;
MOV_I: encoded = 8;
BCOND: encoded = 12;
endcase
if (opcode[7:1] == LSH_I) encoded = 9;
end
endmodule
| 6.856935 |
module alu_engine #(
parameter M = 32,
parameter N = 32
) (
// --- clock and reset
input wire clk,
input wire rst,
// --- data interface
input wire ce,
input wire start,
input wire [M-1:0] a,
input wire [N-1:0] b,
input wire [ 3:0] op,
output wire valid,
output wire [M-1:0] q,
output wire [N-1:0] r
);
//*************************************************************//
// Variables declaration
//*************************************************************//
parameter OP_DIVIDER = 4'h0;
parameter OP_MUL = 4'h1;
wire divider_ce;
wire multiplier_ce;
wire div_valid;
wire mul_valid;
wire [31:0] div_q;
wire [31:0] div_r;
wire [31:0] mul_result;
//*************************************************************//
// Module instatiation
//*************************************************************//
divider #(
.M(M),
.N(N)
) divider_inst (
.clk (clk), //i
.rst (rst), //i
.ce (divider_ce), //i
.start(start), //i
.a (a), //i
.b (b), //i
.valid(div_valid), //o
.q (div_q), //o
.r (div_r) //o
);
multiplier #(
.M(M)
) multiplier_inst (
.clk (clk), //i
.rst (rst), //i
.ce (multiplier_ce), //i
.start (start), //i
.a (a), //i
.b (b), //i
.valid (mul_valid), //o
.result(mul_result) //o
);
//*************************************************************//
// Logics
//*************************************************************//
assign divider_ce = (op == OP_DIVIDER) ? ce : 1'b0;
assign multiplier_ce = (op == OP_MUL) ? ce : 1'b0;
assign valid = div_valid || mul_valid;
assign q = ({32{div_valid}} & div_q) | ({32{mul_valid}} & mul_result);
assign r = div_r;
endmodule
| 6.72792 |
module alu_eor (
input [15:0] operand1,
input [15:0] operand2,
output [15:0] dout
);
assign dout = operand1 ^ operand2;
endmodule
| 7.545037 |
module alu_eq (
S,
V,
Z
);
input wire [3:0] S;
input wire [3:0] V;
output wire Z;
wire [3:0] TEMP;
assign TEMP = S ^ V;
assign Z = ~(|TEMP[3:0]);
endmodule
| 7.005812 |
module ALU_ns_logic (
state,
next_state,
op_start,
opdone_clear,
rd_ack_inst,
rd_err_inst,
wr_err_inst,
rd_err_result,
wr_err_result,
opcode,
mul_done
);
input op_start, opdone_clear,
rd_ack_inst, rd_err_inst, wr_err_inst,
rd_err_result, wr_err_result,
mul_done;
input [3:0] opcode;
input [3:0] state;
output reg [3:0] next_state;
parameter IDLE = 4'h0;
parameter INST_POP1 = 4'h1;
parameter NOP = 4'h2;
parameter EXEC = 4'h3;
parameter MUL = 4'h4;
parameter RESULT_PUSH1 = 4'h5;
parameter RESULT_PUSH2 = 4'h6;
parameter INST_POP2 = 4'h7;
parameter EXEC_DONE = 4'h8;
parameter FAULT = 4'h9;
always @ (state, wr_err_inst, rd_err_result, rd_err_inst, rd_err_inst,
opcode, mul_done, wr_err_result, opdone_clear, op_start, rd_ack_inst) begin
if (wr_err_inst == 1'b1 || rd_err_result == 1'b1) next_state <= FAULT;
else begin
case (state)
IDLE: begin
if (op_start == 1'b1) next_state <= INST_POP1;
else next_state <= IDLE;
end
INST_POP1: begin
if (rd_err_inst == 1'b1) next_state <= FAULT;
else if (rd_ack_inst == 1'b1) begin
if (opcode == 4'h0) next_state <= NOP;
else if (opcode != 4'hf) next_state <= EXEC;
else if (opcode == 4'hf) next_state <= MUL;
else next_state <= FAULT;
end else next_state <= INST_POP1;
end
NOP: next_state <= INST_POP2;
EXEC: next_state <= RESULT_PUSH1;
MUL: begin
if (mul_done == 1'b1) next_state <= RESULT_PUSH1;
else next_state <= MUL;
end
RESULT_PUSH1: begin
if (wr_err_result == 1'b1) next_state <= FAULT;
else next_state <= RESULT_PUSH2;
end
RESULT_PUSH2: next_state <= INST_POP2;
INST_POP2: begin
if (rd_err_inst == 1'b1) next_state <= EXEC_DONE;
else if (rd_ack_inst == 1'b1) begin
if (opcode == 4'h0) next_state <= NOP;
else if (opcode != 4'hf) next_state <= EXEC;
else if (opcode == 4'hf) next_state <= MUL;
else next_state <= FAULT;
end else next_state <= INST_POP2;
end
EXEC_DONE: begin
if (opdone_clear == 1'b1) next_state <= IDLE;
else next_state <= EXEC_DONE;
end
FAULT: next_state <= FAULT;
default: next_state <= 4'bx;
endcase
end
end
endmodule
| 6.808735 |
module W0RM_ALU_Extend #(
parameter SINGLE_CYCLE = 0,
parameter DATA_WIDTH = 8
) (
input wire clk,
input wire data_valid,
input wire [3:0] opcode,
input wire ext_8_16, // High for 16-bit, low for 8-bit
input wire [DATA_WIDTH-1:0] data_a,
data_b,
output wire [DATA_WIDTH-1:0] result,
output wire result_valid,
output wire [ 3:0] result_flags
);
localparam MSB = DATA_WIDTH - 1;
localparam ALU_OPCODE_SEX = 4'ha;
localparam ALU_OPCODE_ZEX = 4'hb;
localparam ALU_FLAG_ZERO = 4'h0;
localparam ALU_FLAG_NEG = 4'h1;
localparam ALU_FLAG_OVER = 4'h2;
localparam ALU_FLAG_CARRY = 4'h3;
reg [DATA_WIDTH-1:0] result_r = 0;
reg result_valid_r = 0;
reg [DATA_WIDTH-1:0] result_i = 0;
reg result_valid_i = 0;
assign result_flags[ALU_FLAG_ZERO] = result_r == 0;
assign result_flags[ALU_FLAG_NEG] = result_r[MSB];
assign result_flags[ALU_FLAG_OVER] = 1'b0; // Overflow and carry are not
assign result_flags[ALU_FLAG_CARRY] = 1'b0; // defined for extend operations
assign result = result_r;
assign result_valid = result_valid_r;
always @(data_valid, opcode, ext_8_16, data_a) begin
result_valid_i = data_valid;
if (data_valid) begin
case (opcode)
ALU_OPCODE_SEX: begin
if (ext_8_16) begin
// 16-bit
result_i = {{16{data_a[15]}}, data_a[15:0]};
end else begin
// 8-bit
result_i = {{24{data_a[7]}}, data_a[7:0]};
end
end
ALU_OPCODE_ZEX: begin
if (ext_8_16) begin
// 16-bit
result_i = {16'd0, data_a[15:0]};
end else begin
// 8-bit
result_i = {24'd0, data_a[7:0]};
end
end
default: begin
result_i = 0;
end
endcase
end else begin
result_i = {DATA_WIDTH{1'b0}};
end
end
generate
if (SINGLE_CYCLE) begin
always @(result_i, result_valid_i) begin
result_r = result_i;
result_valid_r = result_valid_i;
end
end else begin
always @(posedge clk) begin
result_r <= result_i;
result_valid_r <= result_valid_i;
end
end
endgenerate
endmodule
| 7.452384 |
module alu_extra (
input clock,
input alu_extra_enable,
input [ 2:0] funct3,
input [31:0] rs1_value,
input [31:0] rs2_value,
output reg [31:0] rd_value
);
parameter [2:0] SUB = 3'h0; // bit select 31..25 = 32 -> means subtract
parameter [2:0] SRA = 3'h5; // bit select 31..25 = 32 -> means Shift Right Aritmethic which carries the MSB to the left
always @(posedge clock & alu_extra_enable) begin
case (funct3)
SUB: rd_value <= rs2_value - rs1_value;
SRA: rd_value <= rs1_value >>> rs2_value;
default: rd_value <= `ZERO;
endcase
end
always @(posedge clock & !alu_extra_enable) begin
rd_value <= `HIGH_IMPEDANCE;
end
endmodule
| 8.968897 |
module ALU_FIFO (
clk,
reset_n,
rd_en_inst,
wr_en_inst,
inst_in,
inst_out,
rd_ack_inst,
wr_err_inst,
rd_err_inst,
rd_en_result,
wr_en_result,
result_in,
result_out,
rd_ack_result,
wr_err_result,
rd_err_result
);
input clk, reset_n, rd_en_inst, wr_en_inst, rd_en_result, wr_en_result;
input [31:0] inst_in, result_in;
output rd_ack_inst, wr_err_inst, rd_err_inst, rd_ack_result, wr_err_result, rd_err_result;
output [31:0] inst_out, result_out;
////////// INSTRUCTION FIFO //////////////
FIFO8 U0_inst (
.clk(clk),
.reset_n(reset_n),
.rd_en(rd_en_inst),
.wr_en(wr_en_inst),
.din(inst_in),
.dout(inst_out),
.data_count(),
.rd_ack(rd_ack_inst),
.rd_err(rd_err_inst),
.wr_ack(),
.wr_err(wr_err_inst)
);
////////// RESULT FIFO //////////////
FIFO16 U1_result (
.clk(clk),
.reset_n(reset_n),
.rd_en(rd_en_result),
.wr_en(wr_en_result),
.din(result_in),
.dout(result_out),
.data_count(),
.rd_ack(rd_ack_result),
.rd_err(rd_err_result),
.wr_ack(),
.wr_err(wr_err_result)
);
endmodule
| 7.151648 |
module ALU (
Result,
zeroflag,
opcode,
A,
B
);
output [7:0] Result;
output zeroflag;
input [7:0] A, B;
input [1:0] opcode;
reg [7:0] Result;
assign zeroflag = ~|Result;
always @*
case (opcode)
2'b00: Result <= A + B;
2'b01: Result <= A - B;
2'b10: Result <= A & B;
2'b11: Result <= A ^ B;
default: Result <= 8'd0;
endcase
endmodule
| 7.343638 |
module tb_ALU ();
reg clk, reset;
reg [7:0] ResultExpected;
wire [7:0] Result;
wire zeroflag;
reg zeroflagExprected;
reg [7:0] A, B;
reg [1:0] opcode;
reg [31:0] vectornum, errors;
reg [26:0] testvectors[10000:0];
// instantiate device under test
ALU DUT (
Result,
zeroflag,
opcode,
A,
B
);
// generate clock
always begin
clk = 1;
#5;
clk = 0;
#5;
end
// at start of test, load vectors
// and pulse reset
initial begin
$readmemb("alu_example.tv", testvectors);
vectornum = 0;
errors = 0;
reset = 1;
#27;
reset = 0;
end
// apply test vectors on rising edge of clk
always @(posedge clk) begin
#1;
{ResultExpected, zeroflagExprected, opcode, A, B} = testvectors[vectornum];
end
// check results on falling edge of clk
always @(negedge clk)
if (~reset) begin // skip during reset
if (Result !== ResultExpected) begin
$display("Error: inputs = %b", {A, B});
$display("outputs = %b (%b expected), ZeroFlag = %b (%b expected)", Result, ResultExpected,
zeroflag, zeroflagExprected);
errors = errors + 1;
end
vectornum = vectornum + 1;
if (testvectors[vectornum] === 4'bx) begin
$display("%d tests completed with %d errors", vectornum, errors);
//$finish;
end
end
endmodule
| 7.04112 |
module ALU_FP (
S,
T,
FS,
shamt,
y_hi,
y_lo,
c,
v,
n,
z
);
input [31:0] S, T; //Inputs
input [4:0] FS, shamt; //Function Select
output [31:0] y_hi, y_lo; //Outputs
//Status Flag bits carry, overflow, negative and zero
output c, v, n, z;
wire c_w, v_w, n_w;
wire [63:0] prdct;
wire [31:0] quote, rem, Y;
integer int_S_int, int_T_int;
integer int_S_frac, int_T_frac;
wire S_sign;
wire T_sign;
wire [12:0] S_int;
wire [12:0] T_int;
wire [7:0] S_frac;
wire [7:0] T_frac;
//wire [9:0] S_exp; wire [9:0] T_exp;
wire [12:0] S_int_;
wire [12:0] T_int_;
wire [7:0] S_frac_;
wire [7:0] T_frac_;
//wire [9:0] S_exp_; wire [9:0] T_exp_;
wire Y_sign;
wire [12:0] Y_int;
wire [7:0] Y_frac;
wire [9:0] Y_exp;
wire c_frac;
assign S_sign = S[31];
assign T_sign = T[31];
assign S_int = S[30:14];
assign T_int = T[30:14];
assign S_frac = S[13:0];
assign T_frac = T[13:0];
//Arithmetic Operations
parameter PASS_S = 5'h00, PASS_T = 5'h01, ADD = 5'h02, ADDU = 5'h03,
SUB = 5'h04, SUBU = 5'h05, SLT = 5'h06, SLTU = 5'h07,
//Logical Operations
AND = 5'h08, OR = 5'h09, XOR = 5'h0a, NOR = 5'h0b,
SRL = 5'h0c, SRA = 5'h0d, SLL = 5'h0e, ANDI = 5'h16,
ORI = 5'h17, LUI = 5'h18, XORI = 5'h19,
//Other Operations
INC = 5'h0f, INC4 = 5'h10, DEC = 5'h11, DEC4= 5'h12,
ZEROS = 5'h13, ONES = 5'h14, SP_INIT = 5'h15,
//FP Operations
FADD = 5'h1A, FSUB = 5'h1B, FADDU = 5'h1C, FSBU = 5'h1D;
always @(S or T or FS) begin
int_S_frac = S_frac;
int_T_frac = T_frac;
int_S_int = S_int;
int_T_int = T_int;
case (FS)
FADD: begin
{c_fract, Y_fract} = S_frac + T_frac;
{c, Y_int} = S_int + T_int;
end
FSUB: begin
{c_fract, Y_fract} = S_frac - T_frac;
{c, Y_int} = S_int - T_int;
end
FADDU: begin
{c_fract, Y_fract} = frac_S_frac + frac_T_frac;
{c, Y_int} = int_S_int + int_T_int;
end
FSUBU: begin
{c_fract, Y_fract} = frac_S_frac - frac_T_frac;
{c, Y_int} = int_S_int - int_T_int;
end
endcase
end
endmodule
| 6.799427 |
module ALU (
a,
b,
sel,
y,
cout
);
input [15:0] a;
input [15:0] b;
input [2:0] sel;
output [15:0] y;
output cout;
wire [16:0] y0; //000
reg [16:0] y1; //001
reg [15:0] y2; //010
reg [15:0] y3; //011
reg [15:0] y4; //100
reg [15:0] y5; //101
reg [15:0] y6; //110
reg [15:0] y7; //111
reg [15:0] y; //output in module the output should be always reg, unless
reg cout; //output
reg c0 = 1'b0;
reg c1 = 1'b0;
//You SHOULD NOT USE ASSIGN in IF_ELSE
//A+B
assign y0 = a + b;
assign c0 = y0[16];
//A-B
assign y1 = a - b;
assign c1 = y1[16]; //Carry would be performed implicitly
//min{a,b}
assign y2 = (a - b) > 0 ? b : a;
//max{a,b}
assign y3 = (a - b) > 0 ? a : b;
//bitwise A & B
assign y4 = a & b;
//bitwise A OR B
assign y5 = a | b;
//A XOR B
assign y6 = a ^ b;
//A XNOR B
assign y7 = ~(a ^ b);
//MUX, output [15:0] y , 1 bit cout
always @(*) begin
case (sel) //OPCODE Selection for mux
3'b000: begin
y = y0;
cout = c0;
end
3'b001: begin
y = y1;
cout = c1;
end
3'b010: y = y2;
3'b011: y = y3;
3'b100: y = y4;
3'b101: y = y5;
3'b110: y = y6;
3'b111: y = y7;
default: y = 0;
endcase
end
endmodule
| 7.650109 |
module ALU_tb;
reg [15:0] a, b;
reg [2:0] op;
wire [15:0] y; //Specially note that wire used as the output is always changing
wire cout; //wire is used as something always flucuating,so in testbench, since the value
//Coming out is always fluctuating, you should use wire.
//Reg used to keep value, and the value you want to change
ALU u1 (
.a(a),
.b(b),
.sel(op),
.cout(cout),
.y(y)
);
initial begin
a <= 16'h8F54;
b <= 16'h79F8;
op <= 3'b000;
#40 a <= 16'b1001_0011_1101_0010;
b <= 16'b1110_1100_1001_0111;
end
always #10 begin //being_end should always be used to prevent errors
op = op + 3'b001;
end
endmodule
| 6.582016 |
module ALU (
a,
b,
sel,
y,
cout
);
input [15:0] a;
input [15:0] b;
input [2:0] sel;
output [15:0] y;
output cout;
reg [16:0] y0; //000
reg [16:0] y1; //001
reg [15:0] y2; //010
reg [15:0] y3; //011
reg [15:0] y4; //100
reg [15:0] y5; //101
reg [15:0] y6; //110
reg [15:0] y7; //111
reg [15:0] y; //output in module the output should be always reg, unless
reg cout; //output
reg c0 = 1'b0;
reg c1 = 1'b0;
//You SHOULD NOT USE ASSIGN in IF_ELSE
//A+B
assign y0 = a + b;
assign c0 = y0[16];
//A-B
assign y1 = a - b;
assign c1 = y1[16]; //Carry would be performed implicitly
//min{a,b}
assign y2 = (a - b) > 0 ? b : a;
//max{a,b}
assign y3 = (a - b) > 0 ? a : b;
//bitwise A & B
assign y4 = a & b;
//bitwise A OR B
assign y5 = a | b;
//A XOR B
assign y6 = a ^ b;
//A XNOR B
assign y7 = ~(a ^ b);
//MUX, output [15:0] y , 1 bit cout
always @(*) begin //Within the sensitivity block, reg is always used.
case (sel) //OPCODE Selection for mux
3'b000: begin
y = y0;
cout = c0;
end
3'b001: begin
y = y1;
cout = c1;
end
3'b010: y = y2;
3'b011: y = y3;
3'b100: y = y4;
3'b101: y = y5;
3'b110: y = y6;
3'b111: y = y7;
default: y = 0;
endcase
end
endmodule
| 7.650109 |
module structuralMultiplexer5 (
output out,
input [2:0] command,
input in0,
in1,
in2,
in3,
in4
);
wire [2:0] ncommand;
wire m0, m1, m2, m3, m4;
`NOT invA (
ncommand[0],
command[0]
);
`NOT invB (
ncommand[1],
command[1]
);
`NOT invC (
ncommand[2],
command[2]
);
`AND4 andgateA (
m0,
in0,
ncommand[0],
ncommand[1],
ncommand[2]
);
`AND4 andgateB (
m1,
in1,
command[0],
ncommand[1],
ncommand[2]
);
`AND4 andgateC (
m2,
in2,
ncommand[0],
command[1],
ncommand[2]
);
`AND4 andgateD (
m3,
in3,
command[0],
command[1],
ncommand[2]
);
`AND4 andgateE (
m4,
in4,
ncommand[0],
ncommand[1],
command[2]
);
`OR5 orgate (
out,
m0,
m1,
m2,
m3,
m4
);
endmodule
| 6.548452 |
module AddSubN (
output sum, // 2's complement sum of a and b
output carryout, // Carry out of the summation of a and b
output overflow, // True if the calculation resulted in an overflow
input a, // First operand in 2's complement format
input b, // Second operand in 2's complement format
input carryin,
input subtract
);
wire atest, btest;
wire bsub;
// allows for subtraction
`XOR subtest (
bsub,
b,
subtract
);
structuralFullAdder adder (
sum,
carryout,
a,
bsub,
carryin
);
endmodule
| 7.214139 |
module SLTmod #(
parameter n = 31
) (
output [n:0] slt,
output carryout,
output overflow,
input [n:0] a,
b
);
wire [n:0] sub;
wire carryout0, over;
wire subtract;
wire [32:0] carryin0;
assign subtract = 1'b1;
assign carryin0[0] = subtract;
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin
AddSubN adder (
.sum(sub[i]),
.carryout(carryin0[i+1]),
.a(a[i]),
.b(b[i]),
.carryin(carryin0[i]),
.subtract(subtract)
);
end
endgenerate
//calculate overflow for adder; overflow if final carryout is not equal to carryin of most significant bit
//used only to calculate SLT, not actual overflow output
`XOR OVERFLOW (
over,
carryin0[32],
carryin0[31]
);
// a larger than b if final bit of subraction if overflow != msb of subtraction
// in case where both are 0, both inputs were equal so SLT = 0 anyway
`XOR SLTXOR (
slt[0],
sub[n],
over
);
assign slt[31:1] = 0;
assign carryout = 0;
assign overflow = 0;
endmodule
| 6.628803 |
module XORmod (
output out,
output carryout,
output overflow,
input a,
b
);
`XOR xorgate (
out,
a,
b
);
assign carryout = 0;
assign overflow = 0;
endmodule
| 7.77765 |
module NORmod (
output out,
output carryout,
output overflow,
input a,
b,
input invert // if invert = 1 functions as an OR module
);
wire interim_out;
`NOR norgate (
interim_out,
a,
b
);
`XOR xorgate (
out,
interim_out,
invert
); // Will invert NAND output if meant to function as OR module
assign carryout = 0;
assign overflow = 0;
endmodule
| 6.784836 |
module alu_get_opposite (
input [3:0] alu_op,
input [31:0] B,
output reg [31:0] B_opposite
);
wire [30:0] tmp;
wire tmp31;
assign tmp = ~B[30:0] + 1;
assign tmp31 = (B == 0 || B == 32'h80000000) ? B[31] : ~B[31];
always @(*) begin
if (alu_op == `SUB) B_opposite = {tmp31, tmp};
else B_opposite = B;
end
endmodule
| 6.511538 |
module ALU_harvard_tb ();
logic clk;
logic ALUmux = 0;
logic [31:0] a;
logic [31:0] b;
logic [31:0] c = 0;
logic [31:0] ALUout;
logic [3:0] ALUop;
logic ALUzero;
initial begin
$dumpfile("test/modules/alu_harvard_tb.vcd");
$dumpvars(0, ALU_harvard_tb);
clk = 0;
#5;
forever begin
#5 clk = 1;
#5 clk = 0;
end
end
localparam integer STEPS = 10000;
initial begin
ALUop = 4'b0010; //alu control input for addition
a = 0;
b = 0;
@(posedge clk) #9;
repeat (STEPS) begin
a = a + 32'h23456789;
b = b + 32'h34567891;
@(posedge clk) #9;
end
a = 32'hffffffff;
b = 32'hffffffff;
@(posedge clk) #9;
ALUop = 4'b0011; //alu control input for subtraction
a = 0;
b = 0;
@(posedge clk) #9;
repeat (STEPS) begin
a = a + 32'h23456789;
b = b + 32'h34567891;
@(posedge clk) #9;
end
a = 32'hffffffff;
b = 32'hffffffff;
@(posedge clk) #9;
ALUop = 4'b0000; //alu control input for AND
a = 0;
b = 0;
@(posedge clk) #9;
repeat (STEPS) begin
a = a + 32'h23456789;
b = b + 32'h34567891;
@(posedge clk) #9;
end
a = 32'hffffffff;
b = 32'hffffffff;
@(posedge clk) #9;
ALUop = 4'b0001; //alu control input for OR
a = 0;
b = 0;
@(posedge clk) #9;
repeat (STEPS) begin
a = a + 32'h23456789;
b = b + 32'h34567891;
@(posedge clk) #9;
end
a = 32'hffffffff;
b = 32'hffffffff;
@(posedge clk) #9;
ALUop = 4'b0101; //alu control input for XOR
a = 0;
b = 0;
@(posedge clk) #9;
repeat (STEPS) begin
a = a + 32'h23456789;
b = b + 32'h34567891;
@(posedge clk) #9;
end
a = 32'hffffffff;
b = 32'hffffffff;
@(posedge clk) #9;
end
// check output of ALU
initial begin
$display("Testing addition");
repeat (STEPS + 2) begin
@(posedge clk) #1;
assert (ALUout == a + b)
else $fatal(2, "a=%d, b=%d, r=%d", a, b, ALUout);
end
$display("Testing subtraction");
repeat (STEPS + 2) begin
@(posedge clk) #1;
assert (ALUout == a - b)
else $fatal(2, "a=%d, b=%d, r=%d", a, b, ALUout);
end
$display("Testing AND");
repeat (STEPS + 2) begin
@(posedge clk) #1;
assert (ALUout == a & b)
else $fatal(2, "a=%d, b=%d, r=%d", a, b, ALUout);
end
$display("Testing OR");
repeat (STEPS + 2) begin
@(posedge clk) #1;
assert (ALUout == a | b)
else $fatal(2, "a=%d, b=%d, r=%d", a, b, ALUout);
end
$display("Testing XOR");
repeat (STEPS + 2) begin
@(posedge clk) #1;
assert (ALUout == a ^ b)
else $fatal(2, "a=%d, b=%d, r=%d", a, b, ALUout);
end
$display("Working as expected");
$finish;
end
mux_ALU test_unit (
.ALUmux(ALUmux),
.ALUop(ALUop),
.a(a),
.b(b),
.c(c), // ALU 32-bit Inputs
.ALUout(ALUout), // ALU 32-bit Output
.ALUzero(ALUzero)
);
endmodule
| 7.312833 |
module Alu_hazard_unit (
clk,
reset,
destination_address_mem_stage,
destination_address_alu_stage,
rs1_address_id_stage,
rs2_address_id_stage,
forward_enable_to_rs1_from_mem_stage_signal,
forward_enable_to_rs2_from_mem_stage_signal,
forward_enable_to_rs1_from_wb_stage_signal,
forward_enable_to_rs2_from_wb_stage_signal
);
input clk, reset;
input [4:0] destination_address_mem_stage,destination_address_alu_stage,rs1_address_id_stage,rs2_address_id_stage;
output reg forward_enable_to_rs1_from_mem_stage_signal,forward_enable_to_rs2_from_mem_stage_signal,forward_enable_to_rs1_from_wb_stage_signal,forward_enable_to_rs2_from_wb_stage_signal;
wire [4:0] alu_rs1_xnor_wire, alu_rs2_xnor_wire, mem_rs1_xnor_wire, mem_rs2_xnor_wire;
wire alu_rs_1comparing, alu_rs_2comparing, mem_rs1comparing, mem_rs2comparing;
// comparing destination address and sourse register address to identify hazards(alu stage with instruction decode stage)
assign #1 alu_rs1_xnor_wire=(destination_address_alu_stage~^rs1_address_id_stage); //bitwise xnoring
assign #1 alu_rs2_xnor_wire=(destination_address_alu_stage~^rs2_address_id_stage); //bit wise xnoring
assign #1 alu_rs_1comparing = (&alu_rs1_xnor_wire); //all bits are anding
assign #1 alu_rs_2comparing = (&alu_rs2_xnor_wire); //all bits anding
// comparing destination address and sourse register address to identify hazards(mem stage with instruction decode stage)
assign #1 mem_rs1_xnor_wire=(destination_address_mem_stage~^rs1_address_id_stage); //bitwise xnoring
assign #1 mem_rs2_xnor_wire=(destination_address_mem_stage~^rs2_address_id_stage); //bit wise xnoring
assign #1 mem_rs1comparing = (&mem_rs1_xnor_wire); //all bits are anding
assign #1 mem_rs2comparing = (&mem_rs2_xnor_wire); //all bits anding
always @(posedge clk) begin
#1 //delay occured by combinational logic
//setting relevent outputs
forward_enable_to_rs1_from_mem_stage_signal = alu_rs_1comparing;
forward_enable_to_rs2_from_mem_stage_signal = alu_rs_2comparing;
forward_enable_to_rs1_from_wb_stage_signal = mem_rs1comparing;
forward_enable_to_rs2_from_wb_stage_signal = mem_rs2comparing;
end
always @(reset) begin
if (reset == 1'b1) begin
#1 //reset delay
//when reset all outputs set to zero allowing normal functionality in the pipeline
forward_enable_to_rs1_from_mem_stage_signal = 1'b0;
forward_enable_to_rs2_from_mem_stage_signal = 1'b0;
forward_enable_to_rs1_from_wb_stage_signal = 1'b0;
forward_enable_to_rs2_from_wb_stage_signal = 1'b0;
end
end
endmodule
| 7.951827 |
module alu_helper (
input [31:0] a,
b,
input [63:0] hilo,
input [4:0] sa,
input [4:0] alu_control,
output reg [63:0] y,
output overflow,
output zero
);
always @(*) begin
case (alu_control)
`ALU_AND: y <= {{32{a[31]}}, a[31:0]} & {{32{b[31]}}, b[31:0]};
`ALU_ANDN: y <= {{32{a[31]}}, a[31:0]} & ~{{32{b[31]}}, b[31:0]};
`ALU_OR: y <= {{32{a[31]}}, a[31:0]} | {{32{b[31]}}, b[31:0]};
`ALU_ORN: y <= {{32{a[31]}}, a[31:0]} | ~{{32{b[31]}}, b[31:0]};
`ALU_NOR: y <= ~({{32{a[31]}}, a[31:0]} |{{32{b[31]}}, b[31:0]});
`ALU_XOR: y <= {{32{a[31]}}, a[31:0]} ^ {{32{b[31]}}, b[31:0]};
`ALU_ADD: y <= {{32{a[31]}}, a[31:0]} + {{32{b[31]}}, b[31:0]};
`ALU_ADDU: y <= {32'b0, a} + {32'b0, b};
`ALU_SUB: y <= {{32{a[31]}}, a[31:0]} - {{32{b[31]}}, b[31:0]};
`ALU_SUBU: y <= {32'b0, a} - {32'b0, b};
`ALU_SLT: y <= $signed(a) < $signed(b);
`ALU_SLTU: y <= {32'b0, a} < {32'b0, b};
`ALU_SLL: y <= {32'b0, b} << a[4:0];
`ALU_SRL: y <= {32'b0, b} >> a[4:0];
`ALU_SRA: y <= $signed(b) >>> a[4:0];
`ALU_SLL_SA: y <= {32'b0, b} << sa;
`ALU_SRL_SA: y <= {32'b0, b} >> sa;
`ALU_SRA_SA: y <= $signed(b) >>> sa;
`ALU_LUI: y <= {32'b0, b[15:0], 16'b0};
`ALU_MFHI: y <= {32'd0, hilo[63:32]};
`ALU_MFLO: y <= {32'd0, hilo[31:0]};
`ALU_MTHI: y <= {a[31:0], hilo[31:0]};
`ALU_MTLO: y <= {hilo[63:32], a[31:0]};
`ALU_PC_PLUS8: y <= {32'b0, a} + 64'd4;
default: y <= 64'd0;
endcase
end
assign overflow = (alu_control==`ALU_ADD || alu_control==`ALU_SUB) ? (y[32] != y[31]): 1'b0;//仅对于有符号数加减法需要判断溢出
assign zero = ~|y;
endmodule
| 7.094868 |
module combined with clkrst.
*/
module alu_hier(InA, InB, Cin, Op, invA, invB, sign, Out, Ofl, Zero);
// declare constant for size of inputs, outputs (N),
// and operations (O)
parameter N = 16;
parameter O = 3;
input [N-1:0] InA;
input [N-1:0] InB;
input Cin;
input [O-1:0] Op;
input invA;
input invB;
input sign;
output [N-1:0] Out;
output Ofl;
output Zero;
wire clk;
wire rst;
wire err;
assign err = 1'b0;
clkrst c0(
// Outputs
.clk (clk),
.rst (rst),
// Inputs
.err (err)
);
alu a0(
// Outputs
.Out (Out[15:0]),
.Ofl (Ofl),
.Zero (Zero),
// Inputs
.InA (InA[15:0]),
.InB (InB[15:0]),
.Cin (Cin),
.Op (Op[2:0]),
.invA (invA),
.invB (invB),
.sign (sign)
);
endmodule
| 7.45942 |
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