code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module
// TODO: Basically translate what you did in the lab into Verilog
module DFlipFlop (clk, in, out, clr, pre, S);
parameter n = 4;
input clk;
input [n-1:0] in;
input [n-1:0] S;
//input clr;
//input pre;
output [n-1:0] out;
reg [n-1:0] out;
always @ (posedge... | 6.61756 |
module Adder(input [3:0] A, B, input carryIn, output carryOut, output [3:0] summation);
wire [3:0] t;
wire cin1, cin2, cin3, cin4;
// Adding the bits of A and B together
xor xorGateOne(t[0], carryIn, B[0]);
xor xorGateTwo(t[1], carryIn, B[1]);
xor xorGateThree(t[2], carryIn, B[2]);
xor xo... | 7.973868 |
module ALU_add #(
parameter DATA_WIDTH = 4
) (
input [DATA_WIDTH -1 : 0] operand1,
input [DATA_WIDTH -1 : 0] operand2,
output signed_overflow,
output unsigned_overflow,
output [DATA_WIDTH -1 : 0] result
);
// overflow and result
wire carry;
assign {carry, result[DATA_WIDTH -1 : 0]} = opera... | 9.199104 |
module alu_adder (
input [31:0] A,
input [31:0] B,
output reg [31:0] C,
output reg zero
);
always @(*) begin
C = A + B;
if (C == 32'b0) zero = 1'b1;
else zero = 1'b0;
end
endmodule
| 6.784883 |
module W0RM_ALU_AddSub #(
parameter SINGLE_CYCLE = 0,
parameter DATA_WIDTH = 8
) (
input wire clk,
input wire data_valid,
input wire [3:0] opcode,
input wire [DATA_WIDTH-1:0] data_a,
data_b,
output wire [DATA_WIDTH-1:0] result,
output wire result_valid,
... | 6.950982 |
module ALU_AddSub_1_tb (
output wire done,
error
);
ALU_AddSub_base_tb #(
.DATA_WIDTH (32),
.FILE_SOURCE ("../testbench/data/core/ALU_AddSub_1_tb_data.txt"),
.FILE_COMPARE("../testbench/data/core/ALU_AddSub_1_tb_compare.txt")
) dut (
.done (done),
.error(error)
);
endmodule
... | 6.845873 |
module ALU_AddSub_base_tb #(
parameter DATA_WIDTH = 8,
parameter FILE_SOURCE = "",
parameter FILE_COMPARE = ""
) (
output wire done,
error
);
localparam FLAGS_WIDTH = 4;
localparam OPCODE_WIDTH = 4;
localparam FS_DATA_WIDTH = (2 * DATA_WIDTH) + OPCODE_WIDTH + 1;
localparam FC_DATA_WIDTH =... | 7.506481 |
module alu_add_1bit (
A,
B,
CI,
S,
CO
);
//port definitions
input wire A, B, CI;
output wire S, CO;
// instantiate module's hardware
assign S = (A & ~B & ~CI) | (~A & B & ~CI) | (~A & ~B & CI) | (A & B & CI);
assign CO = (B & CI) | (A & CI) | (A & B);
endmodule
| 7.60109 |
module alu_add_2bit (
A,
B,
CI,
S,
CO
);
//port definitions
input wire CI;
input wire [1:0] A, B;
output wire [1:0] S;
output wire CO;
// extra useful wires
wire carry_out_0, carry_in_1;
// instantiate module's hardware
assign carry_in_1 = carry_out_0;
alu_add_1bit ADD_0 (
... | 7.333868 |
module alu_add_4bit (
A,
B,
CI,
S,
CO
);
//port definitions
input wire CI;
input wire [3:0] A, B;
output wire [3:0] S;
output wire CO;
// extra useful wires
wire carry_out_01, carry_in_23;
// instantiate module's hardware
assign carry_in_23 = carry_out_01;
alu_add_2bit ADD_01... | 7.185375 |
module alu_add_4bit_2 (
A,
B,
CI,
S,
CO
);
//port definitions
input wire CI;
input wire [3:0] A, B;
output wire [3:0] S;
output wire CO;
// extra useful wires
wire [3:0] g; // generate wires
wire [3:0] p; // propogate wires
wire [4:0] c; // carry wires
// instantiate module... | 7.165054 |
module alu_add_4bit_2_test;
reg [3:0] A;
reg [3:0] B;
reg CI;
wire [3:0] S;
wire CO;
// testbench variables
reg [3:0] i;
reg [3:0] j;
reg [4:0] desired_sum;
wire [3:0] desired_output;
wire desired_carry_out;
alu_add_4bit_2 uut (
.A (A),
.B (B),
.CI(CI),
.S (S),
.... | 7.165054 |
module alu_add_4bit_test;
reg [3:0] A;
reg [3:0] B;
reg CI;
wire [3:0] S;
wire CO;
// testbench variables
reg [3:0] i;
reg [3:0] j;
reg [4:0] desired_sum;
wire [3:0] desired_output;
wire desired_carry_out;
alu_add_4bit uut (
.A (A),
.B (B),
.CI(CI),
.S (S),
.CO(C... | 7.165054 |
module alu_add_only (
in_a,
in_b,
add_out
);
input [31:0] in_a, in_b;
output [31:0] add_out;
assign add_out = in_a + in_b;
endmodule
| 8.733442 |
module alu_and (
A,
B,
Z
);
// parameter definitions
parameter WIDTH = 8;
//port definitions
input wire [WIDTH-1:0] A, B;
output wire [WIDTH-1:0] Z;
// instantiate module's hardware
assign Z = A & B;
endmodule
| 9.185003 |
module AndModule (
bigMuxIn3,
inA,
inB
);
output [15:0] bigMuxIn3;
input [15:0] inA;
input [15:0] inB;
and (bigMuxIn3[0], inA[0], inB[0]);
and (bigMuxIn3[1], inA[1], inB[1]);
and (bigMuxIn3[2], inA[2], inB[2]);
and (bigMuxIn3[3], inA[3], inB[3]);
and (bigMuxIn3[4], inA[4], inB[4]);
and (... | 8.287566 |
module: alu_and_test
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_and_test;
// parameter
parameter WIDTH = 32;
// test module variables
reg [WIDTH-1:0] i;
// Inputs
re... | 7.671632 |
module ALU_A_MUX (
input ALUSrcA,
input [31:0] Data1, //ԼĴ
input [ 4:0] Data2, //saֻ5λҪ0չ
output [31:0] result
);
assign result = (ALUSrcA == 0 ? Data1 : {{27{0}}, Data2[4:0]});
endmodule
| 6.848388 |
module ALU_B (
input wire [ `icodeBus] icode,
input wire [ `ifunBus] ifun,
input wire [`digitsBus] valB,
output reg [`digitsBus] ALUB
);
always @(*) begin
case ({
icode, 4'h0
})
`rrmovq: begin
ALUB <= 0;
end
`rmmovq: begin
ALUB <= valB;
end
... | 6.769681 |
module ALU_barrel (
input clk,
input S,
input [31:0] Shift_Data,
input [7:0] Shift_Num,
input [2:0] Shift_op,
input [31:0] A,
input [ 3:0] ALU_op,
output wire [31:0] F
);
wire [31:0] B;
wire Shift_carry_out;
wire [3:0] NZCV;
Barrel_Shift shift (
Shift_Data,
Shi... | 8.218655 |
module alu_base (
input clock,
input alu_base_enable,
input [ 2:0] funct3,
input [31:0] rs1_value,
input [31:0] rs2_value,
output reg [31:0] rd_value
);
parameter [2:0] ADD = 3'h0;
parameter [2:0] SLL = 3'h1;
parameter [2:0] SLT = 3'h2;
parameter [... | 8.207996 |
module ALU_basic (
input wire opA,
wire opB,
input wire [3:0] S ,
input wire M,
Cin,
output reg DO ,
output reg CO
);
reg p;
reg g;
always @(*) begin
p = ~(S[0] & (~opA) & (~opB) | S[1] & (~opA) & opB | S[2] & opA & (~opB) | S[3] & opA & opB);
DO = p ^ Cin;
g =... | 7.459917 |
module ALU_basic_tb ();
reg clk_1Hz;
reg opA, opB;
reg [3:0] S ;
reg M;
reg Cin;
wire DO, CO;
ALU_basic u0 (
opA,
opB,
S,
M,
Cin,
DO,
CO
);
always #100 clk_1Hz = ~clk_1Hz;
initial begin
clk_1Hz = 0;
#200;
Cin = 1'b1;
M = 1'b0;
opA = ... | 6.527365 |
module top_data_alu (
input [15:0] data,
//input push,
input reset,
input [2:0] load,
output [15:0] alu_out
//output zr,
//output ng
);
wire [5:0] opcode;
wire [15:0] x, y;
data my_data (
.data(data),
//.push(push), //BTND
.reset(reset),
.load(load),
.x(... | 7.34271 |
module alu_behav (
busOut,
zero,
overflow,
carry,
neg,
busA,
busB,
control
);
output reg [31:0] busOut;
output reg zero, overflow, carry, neg;
input [31:0] busA, busB;
input [2:0] control;
wire [31:0] adderBusB;
reg [31:0] sltBus; //For flags on SLT subtraction
// state... | 6.538166 |
module Alu (
Z,
A,
B,
INST,
SEL
);
output [31:0] Z;
input signed [31:0] A;
input signed [31:0] B;
input [3:0] INST;
input SEL;
reg [31:0] Z;
always @(A or B or INST or SEL) begin
case (INST)
4'b0000: Z = A + B;
4'b0001: Z = 32'h00000001 + ~A;
4'b0010: Z = A & B;... | 7.167973 |
module: ALU_beh
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALU_beh_testbench;
// Inputs
reg [3:0] A_in;
reg [3:0] B_in;
reg [1:0] Sel_in;
// Outputs
wire [3:0] Y_out;
... | 6.656036 |
module ALU_behav (
ADin,
BDin,
ALU_ctr,
Result,
Overflow,
Carry_in,
Carry_out,
Zero
);
parameter n = 32, Ctr_size = 4;
input Carry_in;
input [Ctr_size-1:0] ALU_ctr;
input [n-1:0] ADin, BDin;
output [n-1:0] Result;
reg [n-1:0] Result, tmp;
output Carry_out, Overflow, Zero;... | 7.545058 |
module TestALU;
// parameter n = 32, Ctr_size = 4;
// reg [n-1:0] A, B, T;
// wire [n-1:0] R, tt;
// reg Carry_in;
// wire Carry_out, Overflow, Zero;
// reg [Ctr_size-1:0] ALU_ctr;
// integer num;
// ALU_behav ALU( A, B, ALU_ctr, R, Overflow, Carry_in, Carry_out... | 6.634616 |
module mux32two (
i0,
i1,
sel,
out
);
input [31:0] i0, i1;
input sel;
output [31:0] out;
assign out = sel ? i1 : i0;
endmodule
| 8.056899 |
module add32 (
i0,
i1,
sum
);
input [31:0] i0, i1;
output [31:0] sum;
assign sum = i0 + i1;
endmodule
| 7.919421 |
module sub32 (
i0,
i1,
diff
);
input [31:0] i0, i1;
output [31:0] diff;
assign diff = i0 - i1;
endmodule
| 6.776614 |
module mul16 (
i0,
i1,
prod
);
input [15:0] i0, i1;
output [31:0] prod;
// this is a magnitude multiplier
// signed arithmetic later
assign prod = i0 * i1;
endmodule
| 7.398946 |
module mux32three (
i0,
i1,
i2,
sel,
out
);
input [31:0] i0, i1, i2;
input [1:0] sel;
output [31:0] out;
reg [31:0] out;
always @(i0 or i1 or i2 or sel) begin
case (sel)
2'b00: out = i0;
2'b01: out = i1;
2'b10: out = i2;
default: out = 32'bx;
endcase
... | 7.380275 |
module alu (
a,
b,
f,
r
);
input [31:0] a, b;
input [2:0] f;
output [31:0] r;
wire [31:0] addmux_out, submux_out;
wire [31:0] add_out, sub_out, mul_out;
mux32two adder_mux (
.i0 (b),
.i1 (32'd1),
.sel(f[0]),
.out(addmux_out)
);
mux32two sub_mux (
.i0 (b),
... | 6.634214 |
module alu_bit_select (
bsel,
bs_out_high,
bs_out_low
);
input wire [2:0] bsel;
output wire [3:0] bs_out_high;
output wire [3:0] bs_out_low;
wire [3:0] bs_out_high_ALTERA_SYNTHESIZED;
wire [3:0] bs_out_low_ALTERA_SYNTHESIZED;
wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_13;
wire SYNTHE... | 7.674859 |
module alu_blk (
input wire clk,
input wire reset,
input wire [15:0] reg16,
input wire [7:0] reg8,
input wire [7:0] mem8,
input wire [7:0] io8,
input wire [2:0] op,
input wire [1:0] latch_op,
input wire [7:0] flags_in,
output reg [7:0] flags_out,
output reg do_loop
);
para... | 7.526326 |
module alu_block (
reg_in1,
reg_in2,
sub_nadd,
alu_out
);
input [7:0] reg_in1;
input [7:0] reg_in2;
input sub_nadd;
output [8:0] alu_out;
//reg [8:0] alu_out;
wire [7:0] xor_out;
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : SUB_BLOCK
xor xor_u1 (xor_out[i], reg_i... | 6.802042 |
module ALU_BLOCK_Test (
reset,
switch_val,
load_dest,
load_src,
load_op,
Disp1,
Disp2,
Disp3,
Disp4,
Flags
);
input wire reset;
input wire [9:0] switch_val;
reg [15:0] Dest;
reg [15:0] Src;
output wire [0:6] Disp1;
output wire [0:6] Disp2;
output wire [0:6] Disp3;... | 7.576463 |
module alu_boolean_20 (
input [15:0] a,
input [15:0] b,
input [3:0] alufn,
output reg [15:0] out
);
always @* begin
case (alufn[0+3-:4])
4'h8: begin
out = a & b;
end
4'he: begin
out = a | b;
end
4'h6: begin
out = a ^ b;
end
4'ha... | 6.735649 |
module alu_branch (
input wire [5:0] alu_opcode,
input wire [31:0] in_s1,
input wire [31:0] in_s2,
input wire [15:0] offset,
input wire [31:0] pc,
input wire g_t,
input wire nop,
input wire enable,
output reg zero,
output reg [31:0] out_pc
);
wire [31:0] offset_ext;
sign... | 6.556047 |
module alu_B_mux (
input alub_sel,
input [31:0] rD2,
input [31:0] ext,
output reg [31:0] B
);
always @(*) begin
case (alub_sel)
'b0: B = rD2;
'b1: B = ext;
default: ;
endcase
end
endmodule
| 7.05293 |
module ALU_Cell_16bit (
A,
B,
FS,
Z,
C,
N,
V,
F
);
input wire [15:0] A;
input wire [15:0] B;
input wire [4:0] FS;
output wire Z;
output wire C;
output wire N;
output wire V;
output wire [15:0] F;
wire [15:0] F_ALTERA_SYNTHESIZED;
wire SYNTHESIZED_WIRE_0;
wire SYN... | 7.07117 |
module alu_cntl (
iInstFunct,
iALUOp,
oOp
);
input iInstFunct;
input iALUOp;
output oOp;
wire [ 5:0] iInstFunct;
wire [ 1:0] iALUOp;
reg [`ALU_CNTL_OP_W-1 : 0] oOp;
parameter ALUOP_ADD = 6'h22;
parameter ALUOP_SUB = 6'h26;
parameter ALUOP_AND = 6'h24;
pa... | 6.545752 |
module ALU_come (
ALU_income,
ALU_outcome,
ALU_oppend,
ALU_funct,
ALU_sa,
ALU_HI,
ALU_LO
);
input [31:0] ALU_income;
input [1:0] ALU_oppend;
input [5:0] ALU_funct;
input [4:0] ALU_sa;
input [31:0] ALU_HI, ALU_LO;
output reg [31:0] ALU_outcome;
always @(*) begin
if (ALU_opp... | 6.956112 |
module alu_compare_20 (
input [1:0] alufn,
input z,
input v,
input n,
output reg [15:0] cmp
);
always @* begin
case (alufn)
2'h1: begin
cmp[0+0-:1] = z;
end
2'h2: begin
cmp[0+0-:1] = n ^ v;
end
2'h3: begin
cmp[0+0-:1] = z | (n ^ v);
... | 6.512678 |
module alu_compare_21 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
out = 16'h0000;
case (alufn)
6'h33: begin
out[0+0-:1] = (a == b);
end
6'h35: begin
out[0+0-:1] = (a < b);
end
6'h37: begin
... | 6.512678 |
module ALU_CONT (
aluOp,
funCode,
aluFunc
);
input [3:0] funCode;
input [2:0] aluOp;
output reg [2:0] aluFunc;
always @(*) begin
case (aluOp)
3'b000: begin
if (funCode == 4'b0000) aluFunc = 3'b000;
if (funCode == 4'b0001) aluFunc = 3'b001;
if (funCode == 4'b0100)... | 7.446792 |
module ALU_control (
input [5:0] FunctCode,
input [2:0] ALUOpIn,
output reg [2:0] signal
);
always @* begin
case (ALUOpIn)
3'b111:
case (FunctCode)
6'b100000: signal = 3'b000;
6'b100010: signal = 3'b001;
6'b100100: signal = 3'b010;
6'b100101: signal = 3'b01... | 7.483671 |
module alu_control_2 (
input [31:0] instruction,
input [ 1:0] alu_op,
output [ 3:0] ALU_select
);
wire [2:0] Func3 = instruction[14:12];
wire [6:0] Func7 = instruction[31:25];
wire [3:0] alu_select0 = {Func7[5], Func3};
wire [3:0] alu_select1 = {(~Func3[1] & Func3[0]) & Func7[5], Func3};
Mux_4... | 7.641617 |
module: alu_control
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_control_tb;
// Inputs
reg [1:0] ALUOp;
reg [5:0] funct;
// Outputs
wire [2:0] operation;
// Instantia... | 6.672598 |
module ALU_control_unit_tb;
wire [3:0] ALUoperation; // output: ALU control signal
reg [5:0] func; // input: function
reg [1:0] ALUop; // input: ALUop
reg addi; // input: addi
reg clk; // clock
// instantiate DUT (device under test)
ALU_control_unit DUT (
ALUop,
addi,
... | 7.040309 |
module alu_core (
cy_in,
S,
V,
R,
op1,
op2,
cy_out,
vf_out,
result
);
input wire cy_in;
input wire S;
input wire V;
input wire R;
input wire [3:0] op1;
input wire [3:0] op2;
output wire cy_out;
output wire vf_out;
output wire [3:0] result;
wire [3:0] result_ALT... | 7.386554 |
module ALU_Core_1_tb (
output wire done,
error
);
ALU_Core_base_tb #(
.DATA_WIDTH (32),
.FILE_SOURCE ("../testbench/data/core/ALU_Core_1_tb_data.txt"),
.FILE_COMPARE("../testbench/data/core/ALU_Core_1_tb_compare.txt")
) dut (
.done (done),
.error(error)
);
endmodule
| 6.786737 |
module ALU_Core_base_tb #(
parameter DATA_WIDTH = 32,
parameter FILE_SOURCE = "",
parameter FILE_COMPARE = ""
) (
output wire done,
error
);
localparam FLAGS_WIDTH = 4;
localparam OPCODE_WIDTH = 4;
localparam FS_DATA_WIDTH = (2 * DATA_WIDTH) + OPCODE_WIDTH + 2;
localparam FC_DATA_WIDTH = ... | 7.579277 |
module ALU_CPU (
input clk_i,
input rst_i,
input inst_ack_i,
input [17:0] IR,
input int_req,
input int_en,
input data_ack_i,
input port_ack_i,
output reg [2:0] state_out,
next_state_out
);
localparam [2:0] misc_fn_wait = 3'b100;
localparam [2:0] misc_fn_stby = 3'b101;
l... | 8.137589 |
module ALU_CPU_tb ();
reg clk_i;
reg rst_i;
reg inst_ack_i;
reg [17:0] IR;
reg int_req;
reg int_en;
reg data_ack_i;
reg port_ack_i;
wire [2:0] state_out, next_state_out;
ALU_CPU test (
.clk_i(clk_i),
.rst_i(rst_i),
.inst_ack_i(inst_ack_i),
.IR(IR),
.int_req(int_req),... | 6.633548 |
module alu_ctl (
ALUOp,
Funct,
ALUOperation
);
input [1:0] ALUOp;
input [5:0] Funct;
output [2:0] ALUOperation;
reg [2:0] ALUOperation;
// symbolic constants for instruction function code
parameter F_mfhi = 6'd16;
parameter F_mflo = 6'd18;
parameter F_add = 6'd32;
parameter F_sub = 6'd34;... | 9.078723 |
module alu_ctrl (
input [2:0] funct3,
input [6:0] funct7,
input [1:0] aluCtrlOp,
// I 型指令类型的判断信号 itype。
// 如果是 itype 信号等于“1”，操作码直接由 funct3 和高位补“0”组成；
// 如果不是 I 型指令，ALU 操作码则要由 funct3 和 funct7 的第五位组成
input itype,
// 输出一个4位的ALU操作信号aluOp
output reg [3:0] aluOp
);
always @(*) beg... | 9.229055 |
module alu_ctrler (
alu_op,
func,
alu_ctrl
); // 入出力ポート
input [2:0] alu_op; // 入力 3-bit メイン制御回路からの制御入力
input [5:0] func; // 入力 6-bit R 形式、function フィールド
output [3:0] alu_ctrl; // 出力 4-bit y
reg [3:0] y;
always @(alu_op or func) begin
case (alu_op)
3'b000: begin
... | 7.911449 |
module ALU_CU (
ALUOp,
Func,
Operation
);
input [1:0] ALUOp;
input [3:0] Func;
output [3:0] Operation;
wire w1, w2, w3, w4, ALUOp0_inv, Func0_inv, Func2_inv;
not G0 (ALUOp0_inv, ALUOp[0]);
not G1 (Func0_inv, Func[0]);
not G2 (Func2_inv, Func[2]);
and G3 (Operation[0], ALUOp[1], ALUOp0_in... | 6.84921 |
module ALUData1Mux (
input [31:0] data_from_reg_i, // Data from the register.
input [31:0] data_from_shift_i, // Data from the shift amount.
input use_shift_ctrl_i, // Control flag:
// 0 -> data from register
// 1 -> data from shift amount... | 7.280684 |
module ALUData2Mux (
input [31:0] data_from_reg_i, // Data from the register.
input [31:0] data_from_sign_extend_i, // Data from the sign extend oper.
input use_sign_extend_ctrl_i, // Control flag:
// 0 -> data from register
// ... | 7.176445 |
module alu_dec(
input wire [5:0] funct,
input wire [1:0] aluop,
output wire [2:0] alucontrol
);
// assign alucontrol = (aluop == 2'b00)? 3'b010:
// (aluop == 2'b01)? 3'b110:
// (aluop == 2'b10)?
// (funct == 6'b10000... | 7.639372 |
module ALU_Decoder #(
parameter Funct_width = 6,
ALU_OP_width = 2,
ALU_Control_width = 3
) (
input wire [ Funct_width-1:0] Funct,
input wire [ALU_OP_width-1:0] ALUOp,
output reg [ALU_Control_width-1:0] ALUControl
);
localparam [Funct_width-1:0] add = 'b10_0000;
localparam [Funct_width-1:0]... | 7.842781 |
module: ALU_Decoder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALU_Decoder_Test;
// Inputs
reg [4:0] Funct40;
reg ALUOp;
// Outputs
wire [1:0] ALUControl;
wire [1:0] Fla... | 6.724468 |
module ALU_Design (
input [31:0] dina,
input [31:0] dinb,
input [ 3:0] aluc,
output reg [31:0] doutr,
output doutz, //0标志
output flag_of //flag overflow
);
//-------------------------------------------------------
wire [31:0] sum;
wire [31:0] sub;
... | 6.58604 |
module ALU_Design_Function (
input [`DATA_WIDTH-1:0] dina,
input [`DATA_WIDTH-1:0] dinb,
input [ 3:0] opcode,
output [`DATA_WIDTH-1:0] doutr,
output doutz, //0־
output flag_of //flag overflow
);
//-------------------------------------------... | 7.410248 |
module ALU_Design_tb ();
reg [11:0] Datain;
reg reset;
reg clk;
wire [7:0] Y;
ALU_Design ALU (
Y,
Datain,
reset,
clk
);
initial begin
Datain = 12'b010001010010;
clk = 1;
reset = 0;
end
always #2 clk = ~clk;
initial begin
#50 Datain = 12'b010001010011;
... | 6.560104 |
module alu_destination_decode (
instr,
rd,
we_reg
);
// Inputs
input [15:0] instr;
// Outputsn
output reg [2:0] rd;
output reg we_reg;
// Wires
wire [2:0] rd_imm, rd_reg, rd_ld_imm;
assign rd_imm = instr[7:5];
assign rd_reg = instr[4:2];
assign rd_ld_imm = instr[10:8];
// assigns
... | 6.739014 |
module ALU_display (
//entradas de la ALU
input [3:0] alu_in1,
alu_in2,
input [1:0] alu_selector,
input alu_switch1,
alu_switch2,
output [7:0] alu_out,
output [6:0] in1_units_display,
in1_decenas_display,
in2_units_display,
in2_decenas_display,
out_unit_display,... | 8.523294 |
module ALU_div #(
parameter DATA_WIDTH = 4
) (
input clk,
input enable,
output busy,
output divide_by_zero,
input [DATA_WIDTH - 1 : 0] operand1,
input [DATA_WIDTH - 1 : 0] operand2,
output [DATA_WIDTH - 1 : 0] result_div,
output [DATA_WIDTH - 1 : 0] result_mod
);
// divide by zero
... | 8.499804 |
module W0RM_ALU_DivRem #(
parameter SINGLE_CYCLE = 0,
parameter DATA_WIDTH = 8
) (
input wire clk,
input wire data_valid,
input wire [3:0] opcode,
input wire [DATA_WIDTH-1:0] data_a,
data_b,
output wire [DATA_WIDTH-1:0] result,
output wire result_valid,
... | 6.791546 |
module ALU_DivRem_1_tb (
output wire done,
error
);
ALU_DivRem_base_tb #(
.DATA_WIDTH (32),
.FILE_SOURCE ("../testbench/data/core/ALU_DivRem_1_tb_data.txt"),
.FILE_COMPARE("../testbench/data/core/ALU_DivRem_1_tb_compare.txt")
) dut (
.done (done),
.error(error)
);
endmodule
... | 6.706171 |
module ALU_DivRem_base_tb #(
parameter DATA_WIDTH = 8,
parameter FILE_SOURCE = "",
parameter FILE_COMPARE = ""
) (
output wire done,
error
);
localparam FLAGS_WIDTH = 4;
localparam OPCODE_WIDTH = 4;
localparam FS_DATA_WIDTH = (2 * DATA_WIDTH) + OPCODE_WIDTH + 1;
localparam FC_DATA_WIDTH =... | 6.831761 |
module alu_E (
input [31:0] SrcA,
input [31:0] SrcB,
input [4:0] Shift,
input [4:0] ALUop,
output [31:0] ALUresult,
output ov
);
`include "macros.v"
integer i;
reg [31:0] result;
reg [31:0] clz_temp;
reg V;
reg [32:0] ov_temp;
assign ALUresult = result;
assign ov = V;
initial ... | 6.873891 |
module ALU_ENCODER (
input wire [7:0] opcode,
output reg [3:0] encoded
);
parameter [7:0] ADD = 8'b00000101;
parameter [7:0] ADDU = 8'b00000110;
parameter [7:0] MUL = 8'b00001110;
parameter [7:0] SUB = 8'b00001001;
parameter [7:0] CMP = 8'b00001011;
parameter [7:0] AND = 8'b00000001;
parameter [... | 6.856935 |
module alu_engine #(
parameter M = 32,
parameter N = 32
) (
// --- clock and reset
input wire clk,
input wire rst,
// --- data interface
input wire ce,
input wire start,
input wire [M-1:0] a,
input wire [N-1:0] b,
input wire [ 3:0] op,
output wire ... | 6.72792 |
module alu_eor (
input [15:0] operand1,
input [15:0] operand2,
output [15:0] dout
);
assign dout = operand1 ^ operand2;
endmodule
| 7.545037 |
module alu_eq (
S,
V,
Z
);
input wire [3:0] S;
input wire [3:0] V;
output wire Z;
wire [3:0] TEMP;
assign TEMP = S ^ V;
assign Z = ~(|TEMP[3:0]);
endmodule
| 7.005812 |
module ALU_ns_logic (
state,
next_state,
op_start,
opdone_clear,
rd_ack_inst,
rd_err_inst,
wr_err_inst,
rd_err_result,
wr_err_result,
opcode,
mul_done
);
input op_start, opdone_clear,
rd_ack_inst, rd_err_inst, wr_err_inst,
rd_err_result, wr_err_result,
mul_done;
in... | 6.808735 |
module W0RM_ALU_Extend #(
parameter SINGLE_CYCLE = 0,
parameter DATA_WIDTH = 8
) (
input wire clk,
input wire data_valid,
input wire [3:0] opcode,
input wire ext_8_16, // High for 16-bit, low for 8-bit
input wire [DATA_WIDTH-1:0] data_a,
data_b,
output wire [DATA_... | 7.452384 |
module alu_extra (
input clock,
input alu_extra_enable,
input [ 2:0] funct3,
input [31:0] rs1_value,
input [31:0] rs2_value,
output reg [31:0] rd_value
);
parameter [2:0] SUB = 3'h0; // bit select 31..25 = 32 -> means subtract
parameter [2:0] SRA = 3... | 8.968897 |
module ALU_FIFO (
clk,
reset_n,
rd_en_inst,
wr_en_inst,
inst_in,
inst_out,
rd_ack_inst,
wr_err_inst,
rd_err_inst,
rd_en_result,
wr_en_result,
result_in,
result_out,
rd_ack_result,
wr_err_result,
rd_err_result
);
input clk, reset_n, rd_en_inst, wr_en_ins... | 7.151648 |
module ALU (
Result,
zeroflag,
opcode,
A,
B
);
output [7:0] Result;
output zeroflag;
input [7:0] A, B;
input [1:0] opcode;
reg [7:0] Result;
assign zeroflag = ~|Result;
always @*
case (opcode)
2'b00: Result <= A + B;
2'b01: Result <= A - B;
2'b10: Result <=... | 7.343638 |
module tb_ALU ();
reg clk, reset;
reg [7:0] ResultExpected;
wire [7:0] Result;
wire zeroflag;
reg zeroflagExprected;
reg [7:0] A, B;
reg [1:0] opcode;
reg [31:0] vectornum, errors;
reg [26:0] testvectors[10000:0];
// instantiate device under test
ALU DUT (
Result,
zeroflag,
opcod... | 7.04112 |
module ALU_FP (
S,
T,
FS,
shamt,
y_hi,
y_lo,
c,
v,
n,
z
);
input [31:0] S, T; //Inputs
input [4:0] FS, shamt; //Function Select
output [31:0] y_hi, y_lo; //Outputs
//Status Flag bits carry, overflow, negative and zero
output c, v, n, z;
wire c_w, v_w, n_w;
wir... | 6.799427 |
module ALU (
a,
b,
sel,
y,
cout
);
input [15:0] a;
input [15:0] b;
input [2:0] sel;
output [15:0] y;
output cout;
wire [16:0] y0; //000
reg [16:0] y1; //001
reg [15:0] y2; //010
reg [15:0] y3; //011
reg [15:0] y4; //100
reg [15:0] y5; //101
reg [15:0] y6; //110
re... | 7.650109 |
module ALU_tb;
reg [15:0] a, b;
reg [2:0] op;
wire [15:0] y; //Specially note that wire used as the output is always changing
wire cout; //wire is used as something always flucuating,so in testbench, since the value
//Coming out is always fluctuating, you should use wire.
//Reg used to keep value, and ... | 6.582016 |
module ALU (
a,
b,
sel,
y,
cout
);
input [15:0] a;
input [15:0] b;
input [2:0] sel;
output [15:0] y;
output cout;
reg [16:0] y0; //000
reg [16:0] y1; //001
reg [15:0] y2; //010
reg [15:0] y3; //011
reg [15:0] y4; //100
reg [15:0] y5; //101
reg [15:0] y6; //110
reg... | 7.650109 |
module structuralMultiplexer5 (
output out,
input [2:0] command,
input in0,
in1,
in2,
in3,
in4
);
wire [2:0] ncommand;
wire m0, m1, m2, m3, m4;
`NOT invA (
ncommand[0],
command[0]
);
`NOT invB (
ncommand[1],
command[1]
);
`NOT invC (
ncommand[2],
... | 6.548452 |
module AddSubN (
output sum, // 2's complement sum of a and b
output carryout, // Carry out of the summation of a and b
output overflow, // True if the calculation resulted in an overflow
input a, // First operand in 2's complement format
input b, // Second operand in 2's c... | 7.214139 |
module SLTmod #(
parameter n = 31
) (
output [n:0] slt,
output carryout,
output overflow,
input [n:0] a,
b
);
wire [n:0] sub;
wire carryout0, over;
wire subtract;
wire [32:0] carryin0;
assign subtract = 1'b1;
assign carryin0[0] = subtract;
genvar i;
generate
for (i = 0; i ... | 6.628803 |
module XORmod (
output out,
output carryout,
output overflow,
input a,
b
);
`XOR xorgate (
out,
a,
b
);
assign carryout = 0;
assign overflow = 0;
endmodule
| 7.77765 |
module NORmod (
output out,
output carryout,
output overflow,
input a,
b,
input invert // if invert = 1 functions as an OR module
);
wire interim_out;
`NOR norgate (
interim_out,
a,
b
);
`XOR xorgate (
out,
interim_out,
invert
); // Will invert NAN... | 6.784836 |
module alu_get_opposite (
input [3:0] alu_op,
input [31:0] B,
output reg [31:0] B_opposite
);
wire [30:0] tmp;
wire tmp31;
assign tmp = ~B[30:0] + 1;
assign tmp31 = (B == 0 || B == 32'h80000000) ? B[31] : ~B[31];
always @(*) begin
if (alu_op == `SUB) B_opposite = {tmp31, tmp};
els... | 6.511538 |
module ALU_harvard_tb ();
logic clk;
logic ALUmux = 0;
logic [31:0] a;
logic [31:0] b;
logic [31:0] c = 0;
logic [31:0] ALUout;
logic [3:0] ALUop;
logic ALUzero;
initial begin
$dumpfile("test/modules/alu_harvard_tb.vcd");
$dumpvars(0, ALU_harvard_tb);
clk = 0;
#5;
forever begin... | 7.312833 |
module Alu_hazard_unit (
clk,
reset,
destination_address_mem_stage,
destination_address_alu_stage,
rs1_address_id_stage,
rs2_address_id_stage,
forward_enable_to_rs1_from_mem_stage_signal,
forward_enable_to_rs2_from_mem_stage_signal,
forward_enable_to_rs1_from_wb_stage_signal,
for... | 7.951827 |
module alu_helper (
input [31:0] a,
b,
input [63:0] hilo,
input [4:0] sa,
input [4:0] alu_control,
output reg [63:0] y,
output overflow,
output zero
);
always @(*) begin
case (alu_control)
`ALU_AND: y <= {{32{a[31]}}, a[31:0]} & {{32{b[31]}}, b[31:0]};
`ALU_ANDN: y <... | 7.094868 |
module combined with clkrst.
*/
module alu_hier(InA, InB, Cin, Op, invA, invB, sign, Out, Ofl, Zero);
// declare constant for size of inputs, outputs (N),
// and operations (O)
parameter N = 16;
parameter O = 3;
input [N-1:0] InA;
input [N-1:0] InB;
input Cin;
input [O-1:0] Op;
input ... | 7.45942 |
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