code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module for alu
module alu(x,y,z,c_in,c_out,lt,eq,gt,overflow,ALUOp);
// Declare variables to be connected to inputs and outputs
input [15:0] x;
input [15:0] y;
output reg [15:0] z;
input c_in;
output reg c_out=0;
output reg lt,eq,gt;
output reg overflow;
input [2:0] ALUOp;
always @(x,y,ALUOp)
begin
case(ALUOp)
3'b000: z = x & y; // AND operation
3'b001: z = x | y; // OR operation
3'b010: {c_out,z} = x + y + c_in; // ADD operation
3'b011: {c_out,z} = x + ~y + 1'b1; // SUB operation
3'b111: z = x < y; // SLT operation
endcase
overflow = c_out;
// comparison indicator bits
lt <= x < y; // less than
eq <= x == y; // equals
gt <= x > y; // greater than
end
endmodule
| 8.189305 |
module ALU (
input [3:0] inA,
input [3:0] inB,
input [1:0] op,
output [3:0] ans
);
//Ŀ
assign ans = (op == 2'b00) ? inA & inB :
(op == 2'b01) ? inA | inB :
(op == 2'b10) ? inA ^ inB :
(op == 2'b11) ? inA + inB
: 4'b000 ; //error
endmodule
| 7.960621 |
module ALU (
input [3:0] inA,
input [3:0] inB,
input [1:0] inC,
input [1:0] op,
output [3:0] ans
);
assign ans = (op == 2'b00) ? $signed(
$signed(inA) >>> inC
) : (op == 2'b01) ? inA >> inC : (op == 2'b10) ? inA - inB : (op == 2'b11) ? inA + inB : 4'b0000;
endmodule
| 7.960621 |
module add (
input [31:0] a,
b,
input funct,
output reg [31:0] addres,
output reg cout
);
reg x;
always @(*) begin
case (funct)
2'b0: begin
{cout, addres} = a + b;
end
2'b1: begin
{x, addres} = a - b;
cout = 0;
end
endcase
end
endmodule
| 6.686118 |
module calc (
input [31:0] a,
b,
input funct,
output reg [31:0] calres,
output reg ovf
);
reg [31:0] cal;
always @(*) begin
case (funct)
1'b0: begin
{cal, calres} = a * b;
if (cal == 32'd0) ovf = 0;
else ovf = 1;
end
1'b1: begin
calres = a / b;
ovf = 0;
end
endcase
end
endmodule
| 6.573936 |
module ALU (
input clock,
input reset,
input [ 3:0] io_operation,
input [31:0] io_inputx,
input [31:0] io_inputy,
output [31:0] io_result
);
wire [31:0] _T_1 = io_inputx & io_inputy;
wire [31:0] _T_3 = io_inputx | io_inputy;
wire [31:0] _T_6 = io_inputx + io_inputy;
wire [31:0] _T_9 = io_inputx - io_inputy;
wire [31:0] _T_11 = io_inputx;
wire [31:0] _T_14 = $signed(io_inputx) >>> io_inputy[4:0];
wire [31:0] _T_18 = io_inputx ^ io_inputy;
wire [31:0] _T_21 = io_inputx >> io_inputy[4:0];
wire [31:0] _T_24 = io_inputy;
wire [62:0] _GEN_15 = {{31'd0}, io_inputx};
wire [62:0] _T_28 = _GEN_15 << io_inputy[4:0];
wire [31:0] _T_31 = ~_T_3;
wire _GEN_1 = io_operation == 4'hd ? io_inputx == io_inputy : io_operation == 4'he & io_inputx != io_inputy; // @[]
wire _GEN_2 = io_operation == 4'hc ? io_inputx >= io_inputy : _GEN_1; // @[]
wire _GEN_3 = io_operation == 4'hb ? $signed(io_inputx) >= $signed(io_inputy) : _GEN_2; // @[]
wire [31:0] _GEN_4 = io_operation == 4'ha ? _T_31 : {{31'd0}, _GEN_3}; // @[]
wire [62:0] _GEN_5 = io_operation == 4'h8 ? _T_28 : {{31'd0}, _GEN_4}; // @[]
wire [62:0] _GEN_6 = io_operation == 4'h9 ? {{62'd0}, $signed(
_T_11
) < $signed(
_T_24
)} : _GEN_5; // @[]
wire [62:0] _GEN_7 = io_operation == 4'h2 ? {{31'd0}, _T_21} : _GEN_6; // @[]
wire [62:0] _GEN_8 = io_operation == 4'h0 ? {{31'd0}, _T_18} : _GEN_7; // @[]
wire [62:0] _GEN_9 = io_operation == 4'h1 ? {{62'd0}, io_inputx < io_inputy} : _GEN_8; // @[]
wire [62:0] _GEN_10 = io_operation == 4'h3 ? {{31'd0}, _T_14} : _GEN_9; // @[]
wire [62:0] _GEN_11 = io_operation == 4'h4 ? {{31'd0}, _T_9} : _GEN_10; // @[]
wire [62:0] _GEN_12 = io_operation == 4'h7 ? {{31'd0}, _T_6} : _GEN_11; // @[]
wire [62:0] _GEN_13 = io_operation == 4'h5 ? {{31'd0}, _T_3} : _GEN_12; // @[]
wire [62:0] _GEN_14 = io_operation == 4'h6 ? {{31'd0}, _T_1} : _GEN_13; // @[]
assign io_result = _GEN_14[31:0];
endmodule
| 7.960621 |
module ALU( // @[:@3.2]
input clock, // @[:@4.4]
input reset, // @[:@5.4]
input [31:0] io_in1, // @[:@6.4]
input [31:0] io_in2, // @[:@6.4]
input [12:0] io_alu_opcode, // @[:@6.4]
output [31:0] io_out // @[:@6.4]
);
wire [31:0] _T_21 = io_in1 + io_in2; // @[ALUTester.scala 38:32:@13.4]
wire [31:0] _T_24 = io_in1 - io_in2; // @[ALUTester.scala 39:32:@16.4]
wire [31:0] _T_25 = io_in1 & io_in2; // @[ALUTester.scala 40:32:@17.4]
wire [31:0] _T_26 = io_in1 | io_in2; // @[ALUTester.scala 41:31:@18.4]
wire [31:0] _T_27 = io_in1 ^ io_in2; // @[ALUTester.scala 42:32:@19.4]
wire [31:0] _T_29 = ~_T_27; // @[ALUTester.scala 43:26:@21.4]
wire [62:0] _GEN_0 = {{31'd0}, io_in1}; // @[ALUTester.scala 44:38:@23.4]
wire [62:0] _T_31 = _GEN_0 << io_in2[4:0]; // @[ALUTester.scala 44:38:@23.4]
wire [31:0] _T_33 = io_in1 >> io_in2[4:0]; // @[ALUTester.scala 45:46:@25.4]
wire [31:0] _T_37 = $signed(io_in1) >>> io_in2[4:0]; // @[ALUTester.scala 48:73:@29.4]
wire _T_40 = $signed(io_in1) < $signed(io_in2); // @[ALUTester.scala 49:47:@32.4]
wire _T_41 = io_in1 < io_in2; // @[ALUTester.scala 50:48:@33.4]
wire _T_42 = 13'hd == io_alu_opcode; // @[Mux.scala 46:19:@34.4]
wire [31:0] _T_43 = _T_42 ? io_in2 : 32'hdeadf00d; // @[Mux.scala 46:16:@35.4]
wire _T_44 = 13'hc == io_alu_opcode; // @[Mux.scala 46:19:@36.4]
wire [31:0] _T_45 = _T_44 ? io_in1 : _T_43; // @[Mux.scala 46:16:@37.4]
wire _T_46 = 13'hb == io_alu_opcode; // @[Mux.scala 46:19:@38.4]
wire [31:0] _T_47 = _T_46 ? {{31'd0}, _T_41} : _T_45; // @[Mux.scala 46:16:@39.4]
wire _T_48 = 13'ha == io_alu_opcode; // @[Mux.scala 46:19:@40.4]
wire [31:0] _T_49 = _T_48 ? {{31'd0}, _T_40} : _T_47; // @[Mux.scala 46:16:@41.4]
wire _T_50 = 13'h9 == io_alu_opcode; // @[Mux.scala 46:19:@42.4]
wire [31:0] _T_51 = _T_50 ? _T_37 : _T_49; // @[Mux.scala 46:16:@43.4]
wire _T_52 = 13'h8 == io_alu_opcode; // @[Mux.scala 46:19:@44.4]
wire [31:0] _T_53 = _T_52 ? _T_33 : _T_51; // @[Mux.scala 46:16:@45.4]
wire _T_54 = 13'h7 == io_alu_opcode; // @[Mux.scala 46:19:@46.4]
wire [62:0] _T_55 = _T_54 ? _T_31 : {{31'd0}, _T_53}; // @[Mux.scala 46:16:@47.4]
wire _T_56 = 13'h6 == io_alu_opcode; // @[Mux.scala 46:19:@48.4]
wire [62:0] _T_57 = _T_56 ? {{31'd0}, _T_29} : _T_55; // @[Mux.scala 46:16:@49.4]
wire _T_58 = 13'h5 == io_alu_opcode; // @[Mux.scala 46:19:@50.4]
wire [62:0] _T_59 = _T_58 ? {{31'd0}, _T_27} : _T_57; // @[Mux.scala 46:16:@51.4]
wire _T_60 = 13'h4 == io_alu_opcode; // @[Mux.scala 46:19:@52.4]
wire [62:0] _T_61 = _T_60 ? {{31'd0}, _T_26} : _T_59; // @[Mux.scala 46:16:@53.4]
wire _T_62 = 13'h3 == io_alu_opcode; // @[Mux.scala 46:19:@54.4]
wire [62:0] _T_63 = _T_62 ? {{31'd0}, _T_25} : _T_61; // @[Mux.scala 46:16:@55.4]
wire _T_64 = 13'h2 == io_alu_opcode; // @[Mux.scala 46:19:@56.4]
wire [62:0] _T_65 = _T_64 ? {{31'd0}, _T_24} : _T_63; // @[Mux.scala 46:16:@57.4]
wire _T_66 = 13'h1 == io_alu_opcode; // @[Mux.scala 46:19:@58.4]
wire [62:0] _T_67 = _T_66 ? {{31'd0}, _T_21} : _T_65; // @[Mux.scala 46:16:@59.4]
wire _T_71 = ~reset; // @[ALUTester.scala 57:11:@63.6]
assign io_out = _T_67[31:0];
always @(posedge clock) begin
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_71) begin
$fwrite(32'h80000002,"io.alu_opcode = %d mux_alu_opcode = %d io.in1 = %x io.in2 = %x io.out = %x\n",
io_alu_opcode,io_alu_opcode,io_in1,io_in2,io_out); // @[ALUTester.scala 57:11:@65.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
| 6.800631 |
module ALU (
result,
zero,
A,
B,
control
);
`include "Parameters.vh"
input [XLEN - 1 : 0] A; // Operand A
input [XLEN - 1 : 0] B; // Operand B
input [2 : 0] control;
output zero;
output reg [XLEN - 1 : 0] result;
// ALU Operations
always @(*) begin
case (control)
ADD_OPCODE: result = A + B;
SUB_OPCODE: result = A - B;
AND_OPCODE: result = A & B;
OR_OPCODE: result = A | B;
SLT_OPCODE: result = A < B;
endcase
end
assign zero = (result == 32'b0) ? 1'b1 : 1'b0;
endmodule
| 8.31389 |
module alu1 (
out,
carryout,
A,
B,
carryin,
control
);
output out, carryout;
input A, B, carryin;
input [2:0] control;
wire xor_input, sum, logicout;
xor x1 (xor_input, B, control[0]);
full_adder f1 (
sum,
carryout,
A,
xor_input,
carryin
);
logicunit l1 (
logicout,
A,
B,
control[1:0]
);
mux2 m2 (
out,
logicout,
sum,
control[2]
);
endmodule
| 7.4996 |
module alu16 (
input wire [15:0] alu16_arg1,
input wire [15:0] alu16_arg2,
output reg [15:0] alu16_out,
input wire [ 2:0] alu16_op,
input wire [ 7:0] alu16_flags_in,
output reg [ 7:0] alu16_flags_out
);
`include "ucode_consts.vh"
parameter FLAG_S = 7; // sign flag
parameter FLAG_Z = 6; // zero flag
parameter FLAG_F5 = 5; // bit 5
parameter FLAG_H = 4; // half carry flag
parameter FLAG_F3 = 3; // bit 3
parameter FLAG_PV = 2; // parity/overflow
parameter FLAG_N = 1; // op was sub
parameter FLAG_C = 0; // carry
wire flag_s, flag_z, flag_f5, flag_h, flag_f3, flag_pv, flag_n, flag_c;
assign flag_s = alu16_flags_in[FLAG_S];
assign flag_z = alu16_flags_in[FLAG_Z];
assign flag_f5 = alu16_flags_in[FLAG_F5];
assign flag_h = alu16_flags_in[FLAG_H];
assign flag_f3 = alu16_flags_in[FLAG_F3];
assign flag_pv = alu16_flags_in[FLAG_PV];
assign flag_n = alu16_flags_in[FLAG_N];
assign flag_c = alu16_flags_in[FLAG_C];
reg [12:0] tmp13;
reg [16:0] tmp17;
always @(*) begin
case (alu16_op)
VAL_ALU16_OP_INC: // inc
begin
alu16_out = alu16_arg1 + 1;
alu16_flags_out = alu16_flags_in;
end
VAL_ALU16_OP_DEC: // dec
begin
alu16_out = alu16_arg1 - 1;
alu16_flags_out = alu16_flags_in;
end
VAL_ALU16_OP_ADD: // add
begin
tmp17 = alu16_arg1 + alu16_arg2;
tmp13 = alu16_arg1[11:0] + alu16_arg2[11:0];
alu16_out = tmp17[15:0];
alu16_flags_out = {
flag_s, flag_z, alu16_out[8+5], tmp13[12], alu16_out[8+3], flag_pv, 1'b0, tmp17[16]
};
end
VAL_ALU16_OP_DEC_LD: // dec as part of ldir etc
begin
alu16_out = alu16_arg1 - 1;
alu16_flags_out = {flag_s, flag_z, flag_f5, 1'b0, flag_f3, alu16_out != 0, 1'b0, flag_c};
end
VAL_ALU16_OP_SBC: // sbc
begin
tmp17 = alu16_arg1 - alu16_arg2 - flag_c;
tmp13 = alu16_arg1[11:0] - alu16_arg2[11:0] - flag_c;
alu16_out = tmp17[15:0];
alu16_flags_out = {
alu16_out[15],
alu16_out == 0,
alu16_out[13],
tmp13[12],
alu16_out[11],
(alu16_arg1[15] != alu16_arg2[15]) && (alu16_arg1[15] != alu16_out[15]),
1'b1,
tmp17[16]
};
end
VAL_ALU16_OP_ADC: // abc
begin
tmp17 = alu16_arg1 + alu16_arg2 + flag_c;
tmp13 = alu16_arg1[11:0] + alu16_arg2[11:0] + flag_c;
alu16_out = tmp17[15:0];
alu16_flags_out = {
alu16_out[15],
alu16_out == 0,
alu16_out[13],
tmp13[12],
alu16_out[11],
(alu16_arg1[15] == alu16_arg2[15]) && (alu16_arg1[15] != alu16_out[15]),
1'b0,
tmp17[16]
};
end
default: begin
alu16_out = 16'bX;
alu16_flags_out = 8'bX;
end
endcase
end
endmodule
| 7.135467 |
module ALU16B (
input logic [15:0] in1,
in2,
input logic [3:0] opCode,
output logic [15:0] out,
output negative,
zero
);
logic [15:0] in1Selector, in2Selector, outSelector;
assign in1Selector = opCode[3] ? ~in1 : in1;
assign in2Selector = opCode[2] ? ~in2 : in2;
assign outSelector = (opCode[1]) ? ~(in1Selector & in2Selector) : in1Selector + in2Selector;
assign out = opCode[0] ? ~outSelector : outSelector;
assign negative = out[15];
assign zero = ~|out;
endmodule
| 7.260804 |
module mux_16bit (
a,
b,
c,
d,
sel,
out
);
input [15:0] a, b, c, d;
input [1:0] sel;
output [15:0] out;
assign out = sel[1] ? (sel[0] ? a : b) : (sel[0] ? c : d);
endmodule
| 7.354098 |
module mux_1bit (
a,
b,
c,
d,
sel,
out
);
input a, b, c, d;
input [1:0] sel;
output out;
assign out = sel[1] ? (sel[0] ? a : b) : (sel[0] ? c : d);
endmodule
| 8.087151 |
module fa1 (
a,
b,
cin,
cout,
s
);
input a, b, cin;
output cout, s;
wire w1, w2, w3;
xor a1 (w1, a, b);
and a2 (w2, a, b);
and a3 (w3, cin, w1);
xor a4 (s, w1, cin);
or a5 (cout, w3, w2);
endmodule
| 7.927977 |
module fa4 (
a,
b,
cin,
cout,
s
);
input [3:0] a, b;
input cin;
output cout;
output [3:0] s;
wire c1, c2, c3;
fa1 a1 (
a[0],
b[0],
cin,
c1,
s[0]
);
fa1 a2 (
a[1],
b[1],
c1,
c2,
s[1]
);
fa1 a3 (
a[2],
b[2],
c2,
c3,
s[2]
);
fa1 a4 (
a[3],
b[3],
c3,
cout,
s[3]
);
endmodule
| 7.255881 |
module fa16 (
a,
b,
cin,
cout,
s
);
input [15:0] a, b;
input cin;
output cout;
output [15:0] s;
//cout = overflow
wire c1, c2, c3;
fa4 a41 (
a[3:0],
b[3:0],
cin,
c1,
s[3:0]
);
fa4 a42 (
a[7:4],
b[7:4],
c1,
c2,
s[7:4]
);
fa4 a43 (
a[11:8],
b[11:8],
c2,
c3,
s[11:8]
);
fa4 a44 (
a[15:12],
b[15:12],
c3,
cout,
s[15:12]
);
endmodule
| 6.682792 |
module sub4 (
a,
b,
cin,
sel,
cout,
ov,
s
);
input [3:0] a, b;
input cin, sel;
output cout, ov;
output [3:0] s;
wire c1, c2, c3;
fa1 sa1 (
a[0],
b[0] ^ sel,
cin,
c1,
s[0]
);
fa1 sa2 (
a[1],
b[1] ^ sel,
c1,
c2,
s[1]
);
fa1 sa3 (
a[2],
b[2] ^ sel,
c2,
c3,
s[2]
);
fa1 sa4 (
a[3],
b[3] ^ sel,
c3,
cout,
s[3]
);
xor ov2 (ov, cout, c3);
endmodule
| 7.03439 |
module sub16 (
a,
b,
ov,
s
);
input [15:0] a, b;
output ov;
output [15:0] s;
wire c1, c2, c3;
sub4 s1 (
a[3:0],
b[3:0],
1'b1,
1'b1,
c1
,,
s[3:0]
);
sub4 s2 (
a[7:4],
b[7:4],
c1,
1'b1,
c2
,,
s[7:4]
);
sub4 s3 (
a[11:8],
b[11:8],
c2,
1'b1,
c3
,,
s[11:8]
);
sub4 s4 (
a[15:12],
b[15:12],
c3,
1'b1
,,
ov,
s[15:12]
);
endmodule
| 7.317719 |
module divider (
a,
b,
out,
ov
);
input [15:0] a, b;
output [15:0] out;
output ov;
reg [31:0] temp;
reg [15:0] q;
reg [15:0] dividor;
always @(a, b) begin
q = a;
dividor = b;
temp = {16'b0, q};
//pdf에 제시된 방식이용 , 16bit -> 16번반복
repeat (16) begin
if (temp[31:16] < dividor) begin //상위 16bit가 dividor보다 작으면 <<1 적용
temp = temp << 1;
if (temp[31:16]>=dividor) begin //아닌경우 lsb =1 , 그리고 상위 16bit 값을 dividor만큼 제함
temp[0] = 1;
temp[31:16] = temp[31:16] - dividor;
end
end
end
end
//하위 16bit가 몫 , b==0 인 경우 , ov판정 on
assign out = temp[15:0];
assign ov = (b == 0) ? 1 : 0;
endmodule
| 7.389371 |
module ALU16bit (
a,
b,
sel,
ov,
out
);
input [15:0] a, b;
input [1:0] sel;
output ov;
output [15:0] out;
wire [15:0] add, sub, mul, div;
wire ov1, ov2, ov3, ov4;
fa16 alu_add (
a,
b,
1'b0,
ov1,
add
);
sub16 alu_sub (
a,
b,
ov2,
sub
);
multiplyer alu_mul (
a,
b,
1'b0,
ov3,
mul
);
divider alu_div (
a,
b,
div,
ov4
);
mux_16bit alu_mux16 (
div,
mul,
sub,
add,
sel,
out
);
mux_1bit alu_mux1 (
ov4,
ov3,
ov2,
ov1,
sel,
ov
);
endmodule
| 6.964646 |
module alu16_unit_24 (
input [5:0] alufn,
input [15:0] a,
input [15:0] b,
output reg [15:0] out
);
wire [16-1:0] M_compare_out;
reg [ 1-1:0] M_compare_z;
reg [ 1-1:0] M_compare_v;
reg [ 1-1:0] M_compare_n;
reg [ 6-1:0] M_compare_alufn;
compare_unit_27 compare (
.z(M_compare_z),
.v(M_compare_v),
.n(M_compare_n),
.alufn(M_compare_alufn),
.out(M_compare_out)
);
wire [16-1:0] M_shifter_out;
reg [16-1:0] M_shifter_a;
reg [16-1:0] M_shifter_b;
reg [ 6-1:0] M_shifter_alufn;
shifter_unit_28 shifter (
.a(M_shifter_a),
.b(M_shifter_b),
.alufn(M_shifter_alufn),
.out(M_shifter_out)
);
wire [16-1:0] M_adder_out;
wire [ 1-1:0] M_adder_z;
wire [ 1-1:0] M_adder_n;
wire [ 1-1:0] M_adder_v;
reg [16-1:0] M_adder_a;
reg [16-1:0] M_adder_b;
reg [ 6-1:0] M_adder_alufn;
adder_unit_29 adder (
.a(M_adder_a),
.b(M_adder_b),
.alufn(M_adder_alufn),
.out(M_adder_out),
.z(M_adder_z),
.n(M_adder_n),
.v(M_adder_v)
);
wire [16-1:0] M_boolean_out;
reg [ 6-1:0] M_boolean_alufn;
reg [16-1:0] M_boolean_a;
reg [16-1:0] M_boolean_b;
boolean_unit_30 boolean (
.alufn(M_boolean_alufn),
.a(M_boolean_a),
.b(M_boolean_b),
.out(M_boolean_out)
);
always @* begin
M_compare_alufn = alufn;
M_shifter_alufn = alufn;
M_adder_alufn = alufn;
M_boolean_alufn = alufn;
M_compare_z = M_adder_z;
M_compare_v = M_adder_v;
M_compare_n = M_adder_n;
M_shifter_a = a;
M_shifter_b = b;
M_adder_a = a;
M_adder_b = b;
M_boolean_a = a;
M_boolean_b = b;
case (alufn[4+1-:2])
2'h0: begin
out = M_adder_out;
end
2'h1: begin
out = M_boolean_out;
end
2'h2: begin
out = M_shifter_out;
end
2'h3: begin
out = M_compare_out;
end
default: begin
out = 1'h0;
end
endcase
end
endmodule
| 6.598123 |
module fulladder (
input wire a,
b,
c,
output wire sum,
c_out
);
wire x1, a1, a2;
xor xor1 (x1, a, b); // xor(out, in, in);
xor xor2 (sum, x1, c);
and and1 (a1, a, b); // and(out, in, in);
and and2 (a2, x1, c);
or or1 (c_out, a1, a2); // or(out, in, in);
endmodule
| 7.454465 |
module ALU_1bits (
input wire a_i,
input wire b_i,
input wire c_i,
input wire [1:0] op,
output wire r_o,
output wire c_o
);
wire and_o, or_o, add_o, zero;
assign and_o = a_i & b_i;
assign or_o = a_i | b_i;
assign zero = 1'b0;
fulladder adder (
a_i,
b_i,
c_i,
add_o,
c_o
);
mux_4x1 mux (
and_o,
or_o,
add_o,
zero,
op,
r_o
);
endmodule
| 7.548747 |
module alu2 (
Out,
A,
B
);
input signed [15:0] A, B;
output signed [15:0] Out;
assign Out = A + B;
endmodule
| 8.232598 |
module meiaSoma (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
xor XOR1 (s0, a, b);
and AND1 (s1, a, b);
endmodule
| 7.280431 |
module meiaSoma
//-----------------
//-- Soma Completa
//-----------------
module somaCompleta(s0, s1, a, b, c);
output s0, s1;
input a, b, c;
wire s2, s3, s4;
meiaSoma MS1 (s2, s3, a, b);
meiaSoma MS2 (s0, s4, s2, c);
or OR1 (s1, s3, s4);
endmodule
| 7.661006 |
module somaCompleta
// ----------------------
// -- Somador de 4 bits
// ----------------------
module somador4bits(s0, s1, s2, s3, carry, comparador, a0, a1, a2, a3, b0 ,b1, b2, b3);
output s0, s1, s2, s3, carry, comparador;
input a0, a1, a2, a3, b0 ,b1, b2, b3;
wire w1, w2, w3;
somaCompleta SM1(s0, w1, b0, a1, 0'b0);
somaCompleta SM2(s1, w2, b1, a1, w1);
somaCompleta SM3(s2, w3, b2, a2, w2);
somaCompleta SM4(s3, carry, b3, a3, w3);
not NOT1(comparador, w3);
endmodule
| 7.41852 |
module somador
//------------------
//-- Meia Diferena
//------------------
module meiaDiferenca(s0, s1, a ,b);
output s0, s1;
input a, b;
wire s2;
xor XOR1 (s0, a, b);
not NOT1 (s2, a);
and AND1 (s1, b, s2);
endmodule
| 7.81062 |
module Meia Diferena
//----------------------
//-- Diferena Completa
//----------------------
module diferencaCompleta(s0, s1, a, b, c);
output s0, s1;
input a, b, c;
wire s2, s3, s4;
meiaDiferenca MD1 (s2, s3, a, b);
meiaDiferenca MD2 (s0, s4, s2, c);
or OR1 (s1, s3, s4);
endmodule
| 7.055737 |
module Diferenca Completa
// ----------------------
// -- Subtrator de 4 bits
// ----------------------
module subtrator4bits(s0, s1, s2, s3, comparador, a0, a1, a2, a3, b0, b1, b2, b3);
output s0, s1, s2, s3, comparador;
input a0, a1, a2, a3, b0 ,b1, b2, b3;
wire w1, w2, w3;
diferencaCompleta DC1 (s0, w1, a0 ,b0, 0'b0);
diferencaCompleta DC2 (s1, w2, a1, b1, w1);
diferencaCompleta DC3 (s2, w3, a2, b2, w2);
diferencaCompleta DC4 (s3, comparador, a3, b3, w3);
endmodule
| 6.693215 |
module comparadorLogico
// ------------------------
// -- Incremento de 1 em a
// ------------------------
module incremento_de_1_em_a(s0, s1, s2, s3, s4, a0, a1, a2, a3);
output s0, s1, s2, s3, s4;
input a0 ,a1, a2, a3;
somador4bits S4B1(s0, s1, s2, s3, s4, s5, a0, a1, a2, a3, 1'b1, 0'b0, 0'b0, 0'b0);
endmodule
| 7.063838 |
module
// ------------------------
// -- Incremento de 1 em b
// ------------------------
module incremento_de_1_em_b(s0, s1, s2, s3, s4, b0, b1, b2, b3);
output s0, s1, s2, s3, s4;
input b0 ,b1, b2, b3;
somador4bits S4B2(s0, s1, s2, s3, s4, s5, b0, b1, b2, b3, 1'b1, 0'b0, 0'b0, 0'b0);
endmodule
| 7.103827 |
module
// ------------------------
// -- Decremento de 1 em a
// ------------------------
module decremento_de_1_em_a(s0, s1, s2, s3, s4, a0, a1, a2, a3);
output s0, s1, s2, s3, s4;
input a0 ,a1, a2, a3;
subtrator4bits Su4B1(s0, s1, s2, s3, s4, a0, a1, a2, a3, 1'b1, 0'b0, 0'b0, 0'b0);
endmodule
| 7.103827 |
module
// ------------------------
// -- Decremento de 1 em b
// ------------------------
module decremento_de_1_em_b(s0, s1, s2, s3, s4, b0, b1, b2, b3);
output s0, s1, s2, s3, s4;
input b0 ,b1, b2, b3;
subtrator4bits Su4B2(s0, s1, s2, s3, s4, b0, b1, b2, b3, 1'b1, 0'b0, 0'b0, 0'b0);
endmodule
| 7.103827 |
module
// -------------------------
// -- Complemento de 2 em a
// -------------------------
module complemento_de_2_em_a(s0, s1, s2, s3, s4, a0, a1, a2, a3);
output s0, s1, s2, s3, s4;
input a0 ,a1, a2, a3;
complementode1 C1_2(s00, s01, s02, s03, s10, s11, s12, s13, a0 ,a1, a2, a3, 1'b1, 0'b0, 0'b0, 0'b0);
somador4bits S4B3(s0, s1, s2, s3, s4, s5, s00, s01, s02, s03, 1'b1, 0'b0, 0'b0, 0'b0);
endmodule
| 7.103827 |
module
// ------------------------
// --Complemento de 2 em b
// ------------------------
module complemento_de_2_em_b(s0, s1, s2, s3, s4, b0, b1, b2, b3);
output s0, s1, s2, s3, s4;
input b0 ,b1, b2, b3;
complementode1 C1_2(s00, s01, s02, s03, s10, s11, s12, s13, b0 ,b1, b2, b3, 1'b1, 0'b0, 0'b0, 0'b0);
somador4bits S4B3(s0, s1, s2, s3, s4, s5, s10, s11, s12, s13, 1'b1, 0'b0, 0'b0, 0'b0);
endmodule
| 7.103827 |
module
// ----------------------
// -- Produto com 2 bits
// ----------------------
module produto_com_2_bits(s0, s1, s2, s3, a0, a1, b0, b1);
output s0, s1, s2, s3;
input a0, a1, b0, b1;
wire s4, s5, s6, s7, s8;
and AND1 (s4, a1, b1);
and AND2 (s5, a0, b0);
and AND3 (s6, a1, b0);
and AND4 (s7, a0, b1);
and AND5 (s3, s4, s5);
not NOT1 (s8, s5);
and AND6 (s2, s4, s8);
xor XOR1 (s1, s6, s7);
assign s0 = s5;
endmodule
| 7.103827 |
module ALU3 (
LEDR,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
KEY
);
input [9:0] SW;
input [2:0] KEY;
output [7:0] LEDR;
output [9:0] HEX0;
output [9:0] HEX1;
output [9:0] HEX2;
output [9:0] HEX3;
output [9:0] HEX4;
output [9:0] HEX5;
wire [7:0] ALUout;
wire [7:0] AaddOne;
wire [7:0] AaddB;
wire [7:0] AverilogB;
wire [7:0] AXORB;
wire [7:0] HighorLow;
wire [7:0] LeftShift;
wire [7:0] RightShift;
wire [7:0] Multiplication;
wire clock;
assign clock = KEY[0];
reg [7:0] q;
//A + 1
adderCircuit a1 (
.A(SW[3:0]),
.B(4'b0000),
.cin(1'b1),
.S(AaddOne[3:0]),
.cout(AaddOne[4])
);
assign AaddOne[5] = 1'b0;
assign AaddOne[6] = 1'b0;
assign AaddOne[7] = 1'b0;
//A + B
adderCircuit a2 (
.A(SW[3:0]),
.B(q[3:0]),
.cin(1'b0),
.S(AaddB[3:0]),
.cout(AaddB[4])
);
assign AaddB[5] = 1'b0;
assign AaddB[6] = 1'b0;
assign AaddB[7] = 1'b0;
//A + B
verilogCircuit v1 (
.A(SW[3:0]),
.B(q[3:0]),
.cin(1'b0),
.S(AverilogB[3:0]),
.cout(AverilogB[4])
);
assign AverilogB[5] = 1'b0;
assign AverilogB[6] = 1'b0;
assign AverilogB[7] = 1'b0;
//AXORB
xorAB x1 (
.A(SW[3:0]),
.B(q[3:0]),
.S(AXORB[7:0])
);
//1 or 0
highLow h1 (
.A(SW[3:0]),
.B(q[3:0]),
.S(HighorLow[7:0])
);
//Left shift B by A bits
assign LeftShift[7:0] = q << SW[3:0];
//Right shift B by A bits
assign RightShift[7:0] = q >> SW[3:0];
// A times B
assign Multiplication = SW[3:0] * q;
mux7to1 m1 (
.SW(SW[7:0]),
.KEY(KEY[2:0]),
.ALUout(ALUout[7:0]),
.AaddOne(AaddOne[7:0]),
.AaddB(AaddB[7:0]),
.AverilogB(AverilogB[7:0]),
.AXORB(AXORB[7:0]),
.HighorLow(HighorLow[7:0]),
.LeftShift(LeftShift[7:0]),
.RightShift(RightShift[7:0]),
.Multiplication(Multiplication[7:0])
);
display d0 (
.s0(SW[0]),
.s1(SW[1]),
.s2(SW[2]),
.s3(SW[3]),
.m0(HEX0[0]),
.m1(HEX0[1]),
.m2(HEX0[2]),
.m3(HEX0[3]),
.m4(HEX0[4]),
.m5(HEX0[5]),
.m6(HEX0[6])
);
assign HEX1[6:0] = 7'b0000000;
assign HEX2[6:0] = 7'b0000000;
assign HEX3[6:0] = 7'b0000000;
display d4 (
.s0(q[0]),
.s1(q[1]),
.s2(q[2]),
.s3(q[3]),
.m0(HEX4[0]),
.m1(HEX4[1]),
.m2(HEX4[2]),
.m3(HEX4[3]),
.m4(HEX4[4]),
.m5(HEX4[5]),
.m6(HEX4[6])
);
display d5 (
.s0(q[4]),
.s1(q[5]),
.s2(q[6]),
.s3(q[7]),
.m0(HEX5[0]),
.m1(HEX5[1]),
.m2(HEX5[2]),
.m3(HEX5[3]),
.m4(HEX5[4]),
.m5(HEX5[5]),
.m6(HEX5[6])
);
always @(posedge clock) begin
if (SW[9] == 1'b0) q <= 8'b0;
else q <= ALUout[7:0];
end
assign LEDR[7:0] = ALUout[7:0];
endmodule
| 6.981781 |
module mux7to1 (
SW,
KEY,
ALUout,
AaddOne,
AaddB,
AverilogB,
AXORB,
HighorLow,
LeftShift,
RightShift,
Multiplication
);
input [7:0] SW;
input [2:0] KEY;
output reg [7:0] ALUout;
input [7:0] AaddOne;
input [7:0] AaddB;
input [7:0] AverilogB;
input [7:0] AXORB;
input [7:0] HighorLow;
input [7:0] LeftShift;
input [7:0] RightShift;
input [7:0] Multiplication;
always @* begin
case (SW[7:5])
3'b000: ALUout[7:0] = AaddOne[7:0];
3'b001: ALUout[7:0] = AaddB[7:0];
3'b010: ALUout[7:0] = AverilogB[7:0];
3'b011: ALUout[7:0] = AXORB[7:0];
3'b100: ALUout[7:0] = HighorLow[7:0];
3'b101: ALUout[7:0] = LeftShift[7:0];
3'b110: ALUout[7:0] = RightShift[7:0];
3'b111: ALUout[7:0] = Multiplication[7:0];
default: ALUout[7:0] = 8'b00000000;
endcase
end
endmodule
| 9.111626 |
module verilogCircuit (
A,
B,
cin,
S,
cout
);
input [3:0] A;
input [3:0] B;
input cin;
output [7:0] S;
output cout;
wire c1;
wire c2;
wire c3;
verilogAdder v0 (
.A(A[0]),
.B(B[0]),
.cin(cin),
.S(S[0]),
.cout(c1)
);
verilogAdder v1 (
.A(A[1]),
.B(B[1]),
.cin(c1),
.S(S[1]),
.cout(c2)
);
verilogAdder v2 (
.A(A[2]),
.B(B[2]),
.cin(c2),
.S(S[2]),
.cout(c3)
);
verilogAdder v3 (
.A(A[3]),
.B(B[3]),
.cin(c3),
.S(S[3]),
.cout(cout)
);
endmodule
| 6.973848 |
module verilogAdder (
A,
B,
cin,
S,
cout
);
input A, B, cin;
output S, cout;
assign {cout, S} = A + B + cin;
endmodule
| 7.201902 |
module adderCircuit (
A,
B,
cin,
S,
cout
);
input [3:0] A;
input [3:0] B;
input cin;
output [7:0] S;
output cout;
wire c1;
wire c2;
wire c3;
fullAdder a0 (
.A(A[0]),
.B(B[0]),
.cin(cin),
.S(S[0]),
.cout(c1)
);
fullAdder a1 (
.A(A[1]),
.B(B[1]),
.cin(c1),
.S(S[1]),
.cout(c2)
);
fullAdder a2 (
.A(A[2]),
.B(B[2]),
.cin(c2),
.S(S[2]),
.cout(c3)
);
fullAdder a3 (
.A(A[3]),
.B(B[3]),
.cin(c3),
.S(S[3]),
.cout(cout)
);
endmodule
| 6.586857 |
module alu32 (
a,
b,
ALUControl,
result
);
input wire [31:0] a, b;
input wire [3:0] ALUControl;
output reg [31:0] result;
wire signed [31:0] a_signed, b_signed;
assign a_signed = a;
assign b_signed = b;
always @(*) begin
case (ALUControl)
4'b0000: result <= a + b;
4'b0001: result <= a - b;
4'b0010: result <= a & b;
4'b0011: result <= a | b;
4'b0100: result <= a ^ b;
4'b0101: result <= a << b[4:0]; // Unsigned Left shift
4'b0110: result <= a >> b[4:0]; // Unsigned Right shift
4'b0111: result <= a >>> b[4:0]; // Signed Right shift
4'b1000: result <= (a == b) ? 1 : 0; // Equal
4'b1001: result <= (a < b) ? 1 : 0; // Less Than Unsigned
4'b1010: result <= (a_signed < b_signed) ? 1 : 0; // Less Than Signed
4'b1011: result <= (a >= b) ? 1 : 0; // Greater Than or Equal Unsigned
4'b1100: result <= (a_signed >= b_signed) ? 1 : 0; // Greater Than or Equal Signed
4'b1101: result <= (a_signed + b_signed) & 32'hFFFFFFFE; // JALR
default: result <= 32'hXXXXXXXX;
endcase
end
endmodule
| 8.104213 |
module.
////////////////////////////////////////////////////////////////////////////////
module ALU32Bit_tb();
reg [3:0] ALUControl; // control bits for ALU operation
reg [31:0] A, B; // inputs
wire [31:0] ALUResult; // answer
wire Zero; // Zero=1 if ALUResult == 0
ALU32Bit u0(
.ALUControl(ALUControl),
.A(A),
.B(B),
.ALUResult(ALUResult),
.Zero(Zero)
);
initial begin
/* Please fill in the implementation here... */
//Use delay of 200 (#200) between the first operation and //second operation when simulating using post-sysnthesis //functional simulation.
//after that, at least 50 between each change.
end
endmodule
| 6.641851 |
module Alu32b_extended (
aluOp,
leftOperand,
rightOperand, // or shamt
aluResult
);
input wire [3:0] aluOp;
input wire [31:0] leftOperand;
input wire [31:0] rightOperand;
output reg [31:0] aluResult;
wire [31:0] aluSimpleResult;
wire [31:0] shiftRightLogically;
assign shiftRightLogically = leftOperand >> rightOperand;
Alu32b_simple alu32b_simple_inst (
.aluOp(aluOp),
.leftOperand(leftOperand),
.rightOperand(rightOperand),
.aluResult(aluSimpleResult)
);
always @(*) begin
case (aluOp)
`Alu32b_extended_aluOp_sll: begin
aluResult = leftOperand << rightOperand;
end
`Alu32b_extended_aluOp_srl: begin
aluResult = shiftRightLogically;
end
`Alu32b_extended_aluOp_sra: begin
aluResult = {shiftRightLogically[30], shiftRightLogically[30:0]};
end
`Alu32b_extended_aluOp_xor: begin
aluResult = leftOperand ^ rightOperand;
end
`Alu32b_extended_aluOp_sltu: begin
aluResult = leftOperand < rightOperand;
end
default: begin
aluResult = aluSimpleResult;
end
endcase
end
endmodule
| 6.86071 |
module ALU4 (
//////////// SW //////////
input [9:0] SW,
//////////// LED //////////
output [9:0] LEDR
);
//=======================================================
// REG/WIRE declarations
//=======================================================
s_ALU4 ALU1 (
SW[9],
SW[3:0],
SW[7:4],
LEDR[3:0],
LEDR[7],
LEDR[8],
LEDR[9]
);
//=======================================================
// Structural coding
//=======================================================
endmodule
| 6.658307 |
module ALU4B (
input logic [3:0] in1,
in2,
opCode,
output logic [3:0] out,
output negative,
zero
);
logic [3:0] in1Selector, in2Selector, outSelector;
assign in1Selector = opCode[3] ? ~in1 : in1;
assign in2Selector = opCode[2] ? ~in2 : in2;
assign outSelector = (opCode[1]) ? ~(in1Selector & in2Selector) : in1Selector + in2Selector;
assign out = opCode[0] ? ~outSelector : outSelector;
assign negative = out[3];
assign zero = ~|out;
endmodule
| 7.024057 |
module ALU_4bits (
input wire [3:0] a_i,
input wire [3:0] b_i,
input wire c_i,
input wire [1:0] op,
output wire [3:0] r_o,
output wire c_o
);
wire ALU_c[3:0];
wire ALU_r[3:0];
ALU_1bits ALU1 (
a_i[0],
b_i[0],
c_i,
op,
ALU_r[0],
ALU_c[0]
);
ALU_1bits ALU2 (
a_i[1],
b_i[1],
ALU_c[0],
op,
ALU_r[1],
ALU_c[1]
);
ALU_1bits ALU3 (
a_i[2],
b_i[2],
ALU_c[1],
op,
ALU_r[2],
ALU_c[2]
);
ALU_1bits ALU4 (
a_i[3],
b_i[3],
ALU_c[2],
op,
ALU_r[3],
ALU_c[3]
);
assign r_o = {ALU_r[3], ALU_r[2], ALU_r[1], ALU_r[0]};
assign c_o = ALU_c[3];
endmodule
| 8.318136 |
module ALU (
input CLK100MHZ,
input [3:0] Num1,
Num2,
input [1:0] Op,
output [3:0] LED1,
LED2,
output [1:0] LED_Op,
output reg [7:0] AN,
output reg [6:0] display
);
reg [ 7:0] result;
reg [ 3:0] digito;
reg [18:0] refresh;
wire [ 2:0] active_display;
assign LED1 = Num1;
assign LED2 = Num2;
assign LED_Op = Op;
always @(*) begin
case (Op)
2'b00: // Suma
result = Num1 + Num2;
2'b01: // Resta
result = (Num1 > Num2) ? (Num1 - Num2) : (Num2 - Num1);
2'b10: // Multiplicacion
result = Num1 * Num2;
2'b11: // Division
result = Num1 / Num2;
default: result = Num1 + Num2;
endcase
end
always @(posedge CLK100MHZ) begin
if (refresh >= 500000) refresh <= 0;
else refresh <= refresh + 1;
end
assign active_display = refresh[18:16];
always @(*) begin
case (active_display)
3'b000: begin
AN = 8'b11111110;
begin
if (Op == 3 & Num2 == 0) digito = 8;
else digito = result % 100 % 10;
end
end
3'b001: begin
AN = 8'b11111101;
begin
if (Op == 3 & Num2 == 0) digito = 8;
else digito = result % 100 / 10;
end
end
3'b010: begin
AN = 8'b11111011;
begin
if (Op == 1 & Num2 > Num1) digito = 10;
else digito = result / 100;
end
end
3'b011: begin
AN = 8'b11110111;
digito = Op;
end
3'b100: begin
AN = 8'b11101111;
digito = Num2 % 100 % 10;
end
3'b101: begin
AN = 8'b11011111;
digito = Num2 % 100 / 10;
end
3'b110: begin
AN = 8'b10111111;
digito = Num1 % 100 % 10;
end
3'b111: begin
AN = 8'b01111111;
digito = Num1 % 100 / 10;
end
endcase
end
always @(*) begin
case (digito)
4'b0000: display = 7'b0000001; // "0"
4'b0001: display = 7'b1001111; // "1"
4'b0010: display = 7'b0010010; // "2"
4'b0011: display = 7'b0000110; // "3"
4'b0100: display = 7'b1001100; // "4"
4'b0101: display = 7'b0100100; // "5"
4'b0110: display = 7'b0100000; // "6"
4'b0111: display = 7'b0001111; // "7"
4'b1000: display = 7'b0000000; // "8"
4'b1001: display = 7'b0000100; // "9"
4'b1010: display = 7'b1111110; // "-"
default: display = 7'b0000001; // "0"
endcase
end
endmodule
| 7.960621 |
module ALUunit (
alufun,
a,
b,
carryin,
result,
carryout
);
input a, b, alufun, carryin;
output reg result, carryout;
always @(*) begin
if(alufun == 1)//减法
begin
if (a == 1 && b == 0) begin
result = carryin;
carryout = 1;
end else if (a == 0 && b == 1) begin
result = carryin;
carryout = 0;
end else begin
if (carryin == 1) begin
result = 0;
carryout = 1;
end else begin
result = 1;
carryout = 0;
end
end
end else begin
if (a == 1 && b == 1) begin
result = carryin;
carryout = 1;
end else if (a == 0 && b == 0) begin
result = carryin;
carryout = 0;
end else begin
if (carryin == 1) begin
result = 0;
carryout = 1;
end else begin
result = 1;
carryout = 0;
end
end
end
end
endmodule
| 6.726604 |
module CMP (
sign,
zero,
overflow,
negative,
alufun,
result
);
input zero, overflow, negative, sign;
input [2:0] alufun;
output reg [31:0] result;
wire n_negative;
parameter EQ = 3'b001;
parameter NEQ = 3'b000;
parameter LT = 3'b010;
parameter LEZ = 3'b110;
parameter LTZ = 3'b101;
parameter GTZ = 3'b111;
assign n_negative = sign ? overflow ^ negative : negative;
always @(*) begin
case (alufun)
EQ: result = zero ? 32'd1 : 0;
NEQ: result = zero ? 0 : 32'd1;
LT: result = n_negative ? 32'd1 : 0;
LEZ: result = (zero || n_negative) ? 32'd1 : 0;
LTZ: result = n_negative ? 32'd1 : 0;
GTZ: result = ~(zero || n_negative) ? 32'd1 : 0;
default: result = 0;
endcase
end
endmodule
| 8.344089 |
module Shift (
A,
B,
alufun,
result
);
input [31:0] A, B;
input [1:0] alufun;
output reg [31:0] result;
parameter SLL = 2'b00;
parameter SRL = 2'b01;
parameter SRA = 2'b11;
always @(*) begin
if (A[4] == 1) begin
case (alufun)
SLL: result = B << 16;
SRL: result = B >> 16;
SRA: result = B >>> 16;
default: result = B << 16;
endcase
end else result = B;
if (A[3] == 1) begin
case (alufun)
SLL: result = result << 8;
SRL: result = result >> 8;
SRA: result = result >>> 8;
default: result = result << 8;
endcase
end else result = result;
if (A[2] == 1) begin
case (alufun)
SLL: result = result << 4;
SRL: result = result >> 4;
SRA: result = result >>> 4;
default: result = result << 4;
endcase
end else result = result;
if (A[1] == 1) begin
case (alufun)
SLL: result = result << 2;
SRL: result = result >> 2;
SRA: result = result >>> 2;
default: result = result << 2;
endcase
end else result = result;
if (A[0] == 1) begin
case (alufun)
SLL: result = result << 1;
SRL: result = result >> 1;
SRA: result = result >>> 1;
default: result = result << 1;
endcase
end else result = result;
end
endmodule
| 6.947224 |
module ALU4_2 (
//////////// KEY //////////
input [3:0] KEY,
//////////// SW //////////
input [9:0] SW,
//////////// LED //////////
output [9:0] LEDR
);
//=======================================================
// REG/WIRE declarations
//=======================================================
assign LEDR[7:4] = 0;
myALU4_2 myALU (
KEY[2:0],
SW[3:0],
SW[7:4],
LEDR[3:0],
LEDR[9],
LEDR[8]
);
//=======================================================
// Structural coding
//=======================================================
endmodule
| 7.712894 |
module ALU4_LA (
a,
b,
c_in,
c_out,
less,
sel,
out,
P,
G
);
input less;
input [3:0] a, b;
input [2:0] sel;
input c_in;
output [3:0] out;
output P, G;
output c_out;
wire [2:0] c;
wire [3:0] p, g;
alu_slice_LA a1 (
a[0],
b[0],
c_in,
less,
sel,
out[0],
p[0],
g[0]
);
alu_slice_LA a2 (
a[1],
b[1],
c[0],
1'b0,
sel,
out[1],
p[1],
g[1]
);
alu_slice_LA a3 (
a[2],
b[2],
c[1],
1'b0,
sel,
out[2],
p[2],
g[2]
);
alu_slice_LA a4 (
a[3],
b[3],
c[2],
1'b0,
sel,
out[3],
p[3],
g[3]
);
lookahead l1 (
c_in,
c_out,
c,
p,
g,
P,
G
);
endmodule
| 6.96335 |
module alu64 (
input [63:0] A,
input [63:0] B,
input [ 5:0] shamt,
// input [5:0] high, // used to set upper bound of string
// input [5:0] low, // used to set lower bound of string
input [ 3:0] aluctrl,
input CLK,
output reg [63:0] Z
// output reg overflow // used to detect overflow
);
reg [63:0] alu_out;
//reg alu_overflow;
//ALU COMBINATIONAL LOGIC
always @(*) begin
// alu_overflow = 1'b0; /**********Modified*********/
alu_out = 64'b0; /**********Modified*********/
case (aluctrl)
4'b0000: begin //add operation
alu_out = A + B;
// if( !A[63] && !B[63] && alu_out[63]) //two positive numbers became negative
// begin
// alu_overflow=1'b1;
// end
// else if ( A[63] && B[63] && !alu_out[63]) //two negative numbers became positive
// begin
// alu_overflow=1'b1;
// end
end
4'b0001: begin //subtract operation (signed
alu_out = A - B;
// if( A[63] && !B[63] && !alu_out[63]) //negative minus positive became positive /**********Modified*********/
// begin
// alu_overflow=1'b1;
// end
// else if ( !A[63] && B[63] && alu_out[63]) //positive minus negative became negative /**********Modified********/
// begin
// alu_overflow=1'b1;
// end
end
4'b0010: begin //bitwise AND
alu_out = A & B;
end
4'b0011: begin //bitwise OR
alu_out = A | B;
end
4'b0100: begin //bitwise XOR
alu_out = A ^ B;
end
// 4'b0101: begin //bitwise XNOR
// alu_out= A ^~ B;
// end
4'b0110: begin //Compare operation - alu_overflow goes high if equal
if (A == B) begin
alu_out[0] = 1'b1;
end
end
// 4'b0111: begin //greater than - alu_overflow goes high
// if (A > B) begin
// alu_out[0] = 1'b1;
// end
// end
// 4'b1000: begin //equal or greater than - alu_overflow goes high
// if (A >= B) begin
// alu_out[0] = 1'b1;
// end
// end
4'b1001: begin //less than - alu_overflow goes high
if (A < B) begin
alu_out[0] = 1'b1;
end
end
// 4'b1010: begin //equal or less than - alu_overflow goes high
// if (A <= B) begin
// alu_out[0] = 1'b1;
// end
// end
// 4'b1011: begin //Left logical shift operation
// alu_out = A << shamt;
// end
4'b1100: begin //Right logical shift operation
alu_out = A >> shamt;
end
4'b1101: begin //Not equal
if (A != B) begin
alu_out[0] = 1'b1;
end
end
// 4'b1110: begin // Bit Selection
// alu_out[0] = A[B[5:0]];
// end
// 4'b1111: begin // Expand
// alu_out = {66{A[B[5:0]]}};
// end
// 4'b1101: begin //Substring comparison
// if ((A << (63-high)) >> (63+low-high) == (B << (63-high)) >> (63+low-high)) begin
// alu_overflow = 1'b1;
// end
// end
// 4'b1110: begin //left shift and compare
// //reg A_temp = A << shamt;
// //reg B_temp = B << shamt;
// if ((A << shamt) == (B << shamt)) begin // not sure if this is best, or can we use just simple if ((A << shamt) == (B << shamt))
// alu_out[0] = 1'b1;
// end
// end
// 4'b1111: begin //right shift and compare
//
// if ((A >> shamt) == (B >> shamt)) begin
// alu_out[0] = 1'b1;
// end
// end
default: begin
//Unspecified behavior
alu_out = 64'bX; /********Modified*********/
// alu_overflow = 1'bX;
end
endcase
end
//REGISTERED OUTPUT OF ALU LOGIC
always @(posedge CLK) begin
Z <= alu_out;
// overflow <= alu_overflow;
end
endmodule
| 6.82162 |
module for ALU64bit
module ALU64bit(key,left,right,select);
output reg [63:0] key;
input [63:0] left, right;
input select;
always @(left,right,select)
begin
if(select) // Key 1 : add
key = left + right;
else // Key 2 : subtract
key = left - right;
end
endmodule
| 7.736513 |
module cla74182 (
input wire [3:0] g,
input wire [3:0] p,
input wire cin,
output wire pout,
output wire gout,
output wire coutx,
output wire couty,
output wire coutz
);
assign coutx = p[0] & (cin | g[0]);
assign couty = p[1] & (p[0] | g[1]) & (cin | g[0] | g[1]);
assign coutz = p[2] & (p[1] | g[2]) & (p[0] | g[1] | g[2]) & (cin | g[0] | g[1] | g[2]);
assign gout = g[0] | g[1] | g[2] | g[3];
assign pout = p[3] & (p[2] | g[3]) & (p[1] | g[2] | g[3]) & (p[0] | g[1] | g[2] | g[3]);
endmodule
| 7.244733 |
module alu8b (
output [7:0] bus,
output reg carry,
output reg zero,
input [7:0] a,
input [7:0] b,
input sub,
input out,
input clr,
input clk,
input fi
);
wire [7:0] int_reg;
wire int_carry, int_zero;
assign {int_carry, int_reg} = a + (b ^ {8{sub}}) + sub;
assign int_zero = ~|(int_reg);
assign bus = out ? int_reg : 8'Bzzzzzzzz;
always @(posedge clk, posedge clr) begin
carry <= (clr) ? 1'b0 : (fi) ? int_carry : carry;
zero <= (clr) ? 1'b0 : (fi) ? int_zero : zero;
end
endmodule
| 7.372182 |
module ALU8bit (
input [3:0] Opcode,
input [7:0] Operand1,
input [7:0] Operand2,
output reg [15:0] Result,
output reg flagC,
output reg flagZ
);
parameter [3:0] ADD = 4'b0000;
parameter [3:0] SUB = 4'b0001;
parameter [3:0] MUL = 4'b0010;
parameter [3:0] DIV = 4'b0011;
parameter [3:0] AND = 4'b0100;
parameter [3:0] OR = 4'b0101;
parameter [3:0] NAND = 4'b0110;
parameter [3:0] NOR = 4'b0111;
parameter [3:0] XOR = 4'b1000;
always @(Opcode or Operand1 or Operand2) begin
case (Opcode)
ADD: begin
Result = Operand1 + Operand2;
flagC = Result[8];
flagZ = (Result == 16'b0);
end
SUB: begin
Result = Operand1 - Operand2;
flagC = Result[8];
flagZ = (Result == 16'b0);
end
MUL: begin
Result = Operand1 * Operand2;
flagZ = (Result == 16'b0);
end
DIV: begin
Result = Operand1 / Operand2;
flagZ = (Result == 16'b0);
end
AND: begin
Result = Operand1 & Operand2;
flagZ = (Result == 16'b0);
end
OR: begin
Result = Operand1 | Operand2;
flagZ = (Result == 16'b0);
end
NAND: begin
Result = ~(Operand1 & Operand2);
flagZ = (Result == 16'b0);
end
NOR: begin
Result = ~(Operand1 | Operand2);
flagZ = (Result == 16'b0);
end
XOR: begin
Result = Operand1 ^ Operand2;
flagZ = (Result == 16'b0);
end
default: begin
Result = 16'b0;
flagC = 1'b0;
flagZ = 1'b0;
end
endcase
end
endmodule
| 7.016761 |
module to test how to port VHDL code to verilog
// in a little smaller units.
// This module is purely combinatorial logic.
module alu9900(
input [16:0] arg1, // 17-bit input to support DIV steps
input [15:0] arg2,
input [3:0] ope,
input compare, // for compare, set this to 1 and ope to sub.
output [15:0] alu_result,
output alu_logical_gt,
output alu_arithmetic_gt,
output alu_flag_zero,
output alu_flag_carry,
output alu_flag_overflow,
output alu_flag_parity,
output alu_flag_parity_source
);
localparam load1=4'h0, load2=4'h1, add =4'h2, sub =4'h3,
abs =4'h4, aor =4'h5, aand=4'h6, axor=4'h7,
andn =4'h8, coc =4'h9, czc =4'ha, swpb=4'hb,
sla =4'hc, sra =4'hd, src =4'he, srl =4'hf;
wire [16:0] alu_out;
// arg1 is DA, arg2 is SA when ALU used for instruction execute
assign alu_out =
(ope == load1) ? arg1 :
(ope == load2) ? { 1'b0, arg2 } :
(ope == add) ? arg1 + { 1'b0, arg2 } :
(ope == sub) ? arg1 - { 1'b0, arg2 } :
(ope == aor) ? arg1 | { 1'b0, arg2 } :
(ope == aand) ? arg1 & { 1'b0, arg2 } :
(ope == axor) ? arg1 ^ { 1'b0, arg2 } :
(ope == andn) ? arg1 & { 1'b0, ~arg2 } :
(ope == coc) ? (arg1 ^ { 1'b0, arg2 }) & arg1 : // compare ones corresponding
(ope == czc) ? (arg1 ^ { 1'b0, ~arg2 }) & arg1 : // compare zeros corresponding
(ope == swpb) ? { 1'b0, arg2[7:0], arg2[15:8] }: // swap bytes of arg2
(ope == abs) ? (arg2[15] ? arg1 - { 1'b0, arg2 } : { 1'b0, arg2 }) :
(ope == sla) ? { arg2, 1'b0 } :
(ope == sra) ? { arg2[0], arg2[15], arg2[15:1] } :
(ope == src) ? { arg2[0], arg2[0], arg2[15:1] } :
{ arg2[0], 1'b0, arg2[15:1] }; // srl
assign alu_result = alu_out[15:0];
// ST0 ST1 ST2 ST3 ST4 ST5
// L> A> = C O P
// ST0 - when looking at data sheet arg1 is (DA) and arg2 is (SA), sub is (DA)-(SA).
assign alu_logical_gt = compare ? (arg2[15] && !arg1[15]) || (arg1[15]==arg2[15] && alu_result[15])
: alu_result != 16'd0;
// ST1
assign alu_arithmetic_gt = compare ? (!arg2[15] && arg1[15]) || (arg1[15]==arg2[15] && alu_result[15])
: (ope == abs) ? arg2[15] == 1'b0 && arg2 != 16'd0
: alu_result[15]==1'b0 && alu_result != 16'd0;
// ST2
assign alu_flag_zero = !(|alu_result);
// ST3
assign alu_flag_carry = (ope == sub) ? !alu_out[16] : alu_out[16]; // for sub carry out is inverted
// ST4 overflow
assign alu_flag_overflow = (ope == sla) ? alu_result[15] != arg2[15] : // sla condition: if MSB changes during shift
(compare || ope==sub || ope==abs) ? (arg1[15] != arg2[15] && alu_result[15] != arg1[15]) :
(arg1[15] == arg2[15] && alu_result[15] != arg1[15]);
// ST5 parity
assign alu_flag_parity = ^alu_result[15:8];
// source parity used with CB and MOVB instructions
assign alu_flag_parity_source = ^arg2[15:8];
endmodule
| 7.771489 |
module ALUAdd (
input [31:0] a,
input [31:0] b,
output reg [31:0] result
);
always @(*) begin
result <= a + b;
end
endmodule
| 7.227614 |
module aluAdder (
result,
pcFour,
relaAddress
);
input [31:0] pcFour, relaAddress;
output [31:0] result;
assign result = pcFour + relaAddress;
// for branch, if branch, new pc = result.
endmodule
| 7.10724 |
module contains 1 control signal, ALUALtSrc, if it is deasserted, it will
* take data from register file as the operand; if it is asserted, it will
* take data from immediate number as the operand.
*/
module alualtsrcmux( input wire [31:0] regsrc,
input wire [31:0] immsrc,
input wire alualtsrc,
output reg [31:0] operand);
always @(*) begin
if (alualtsrc) begin
operand = immsrc;
end else begin
operand = regsrc;
end
end
endmodule
| 6.799318 |
module ALU (
in1,
in2,
shamt,
aluop,
out,
zeroflag
);
input signed [31:0] in1, in2; //edited to signed
reg unsigned [31:0] in1u, in2u;
input [3:0] aluop;
input [4:0] shamt;
output reg [31:0] out;
output reg zeroflag;
always @(in1, in2, aluop) begin
if (in1 == in2) zeroflag = 1;
else zeroflag = 0;
//if(aluop==7)
in1u = in1;
in2u = in2;
case (aluop)
0: out = in1 + in2;
1: out = in1 - in2;
2: out = in1 & in2;
3: out = in1 | in2;
4: out = in1 < in2;
5: out = in2 * (2 ** shamt);
6: out = in2 / (2 ** shamt);
7: out = in1u < in2u;
endcase
end
endmodule
| 7.37871 |
module ALUAMuxTest ();
reg [31:0] PC, A, MDR;
reg [ 1:0] ALUSrcA;
wire [31:0] out;
ALUAMux dut (
.ALUSrcA(ALUSrcA),
.PC(PC),
.A(A),
.MDR(MDR),
.Data_out(out)
);
initial begin
$dumpfile("memAddrMuxTest.vcd");
$dumpvars;
end
initial begin
ALUSrcA = 0;
PC = 5;
A = 0;
MDR = 0;
#5 ALUSrcA = 1;
PC = 0;
A = 5;
MDR = 0;
#5 ALUSrcA = 2;
PC = 0;
A = 0;
MDR = 5;
#5 $finish();
end
endmodule
| 7.213011 |
module ALUB (
input [7:0] A,
B, // ALU 8-bit Inputs
input [3:0] ALU_Sel, // ALU Selection
output [7:0] ALU_Out, // ALU 8-bit Output
output CarryOut // Carry Out Flag
);
reg [7:0] ALU_Result;
wire [8:0] tmp;
assign ALU_Out = ALU_Result; // ALU out
assign tmp = {1'b0, A} + {1'b0, B};
assign CarryOut = tmp[8]; // Carryout flag
always @(*) begin
case (ALU_Sel)
4'b0000: // Addition
ALU_Result = A + B;
4'b0001: // Subtraction
ALU_Result = A - B;
4'b0010: // Multiplication
ALU_Result = A * B;
4'b0011: // Division
ALU_Result = A / B;
4'b0100: // Logical shift left
ALU_Result = A << 1;
4'b0101: // Logical shift right
ALU_Result = A >> 1;
4'b0110: // Rotate left
ALU_Result = {A[6:0], A[7]};
4'b0111: // Rotate right
ALU_Result = {A[0], A[7:1]};
4'b1000: // Logical and
ALU_Result = A & B;
4'b1001: // Logical or
ALU_Result = A | B;
4'b1010: // Logical xor
ALU_Result = A ^ B;
4'b1011: // Logical nor
ALU_Result = ~(A | B);
4'b1100: // Logical nand
ALU_Result = ~(A & B);
4'b1101: // Logical xnor
ALU_Result = ~(A ^ B);
4'b1110: // Greater comparison
ALU_Result = (A > B) ? 8'd1 : 8'd0;
4'b1111: // Equal comparison
ALU_Result = (A == B) ? 8'd1 : 8'd0;
default: ALU_Result = A + B;
endcase
end
endmodule
| 8.227322 |
module ALUbasic (
output [7:0] Out, // Output 8 bit
output [3:0] flagArray, // not holding only driving EDI
input Cin, // Carry input bit
input [7:0] A_IN_0,
input [7:0] B_IN_0, // 8-bit data input
input [7:0] OR2,
input [3:0] S_AF, // Most significant 4 bits of the op code
input S30,
input S40
);
wire [7:0] B_IN;
wire [7:0] A_IN;
//legacy def
//Unary Operations
parameter [3:0] ZERO = 4'h0; //Output 0(ZERO)
parameter [3:0] A = 4'h1; //Output A
parameter [3:0] NOT = 4'h2; //~A
parameter [3:0] B = 4'h3; //Output B
parameter [3:0] INC_A = 4'h4; //A + 1
parameter [3:0] DCR_A = 4'h5; //A - 1
parameter [3:0] SLC_A = 4'h6; //Shift Left & C <- MSB
parameter [3:0] SRC_A = 4'h7; //Shift Right & C <- LSB
//Binary and ternary operations - Arithmetic
parameter [3:0] ADD_AB = 4'h8; //A + B
parameter [3:0] SUB_AB = 4'h9; //A - B
parameter [3:0] ADD_ABC = 4'hA; //A + B + C
parameter [3:0] SUB_ABC = 4'hB; //A - B - C
//Binary and ternary operations - Logical
parameter [3:0] AND_AB = 4'hC; //A AND B
parameter [3:0] OR_AB = 4'hD; //A OR B
parameter [3:0] XOR_AB = 4'hE; //A XOR B
parameter [3:0] XNA_AB = 4'hF; //A' XOR B
// end legacy def
wire Cout;
wire Zero;
wire OddParity;
wire Positive;
assign B_IN = (S40 == 1'b0) ? B_IN_0 : OR2;
assign A_IN = (S30 == 1'b0) ? A_IN_0 : B_IN_0;
assign {Cout,Out} = (S_AF== ZERO )? 9'h00 : (
(S_AF== A )? A_IN : (
(S_AF== NOT )? ~A_IN : (
(S_AF== B )? B_IN : (
(S_AF== INC_A )? A_IN+1 : (
(S_AF== DCR_A )? A_IN - 1 : (
(S_AF== SLC_A )? {A_IN,Cin} : ( //Rotate
(S_AF == SRC_A) ? {A_IN[0], Cin, A_IN[7:1]} : ( //Rotate
(S_AF== ADD_AB )? A_IN+B_IN : (
(S_AF== SUB_AB )? A_IN-B_IN : (
(S_AF== ADD_ABC )? A_IN+B_IN+Cin : (
(S_AF== SUB_ABC )? A_IN-B_IN-Cin : (
(S_AF== AND_AB )? A_IN&B_IN : (
(S_AF== OR_AB )? A_IN|B_IN : (
(S_AF== XOR_AB )? A_IN^B_IN : (
(S_AF== XNA_AB )? ~(A_IN^B_IN) : 9'hzz )))))))))))))));
assign OddParity = ^Out;
assign Zero = ~(|Out);
assign Positive = ~(Out[7]);
assign flagArray = {OddParity, Positive, Cout, Zero};
endmodule
| 7.565516 |
module alu (
RESULT,
DATA1,
DATA2,
SELECT
);
output reg [7:0] RESULT;
input [7:0] DATA1, DATA2;
input [2:0] SELECT;
always @(*) begin
case (SELECT)
3'b000: begin
RESULT = DATA1; //FORWARD
end
3'b001: begin
RESULT = DATA1 + DATA2; //ADD
end
3'b010: begin
RESULT = DATA1 & DATA2; //AND
end
3'b011: begin
RESULT = DATA1 | DATA2; //OR
end
default: RESULT = 8'b00000000;
endcase
end
endmodule
| 6.796395 |
module alub_mux (
input wire alub_sel,
input wire [31:0] rdata2,
input wire [31:0] imm,
output wire [31:0] alub
);
assign alub = (alub_sel == 1) ? rdata2 : imm;
endmodule
| 6.888262 |
module ALUcard_top (
input [2:0] opcode,
input [3:0] data,
input GO,
input clk,
input reset,
output [3:0] result,
output cout,
output borrow,
output led_idle,
output led_wait,
output led_rdy,
output led_done
);
wire [3:0] A_w;
wire [3:0] B_w;
ALU_State U1 (
.clk(clk),
.GO(GO),
.reset(reset),
.led_idle(led_idle),
.led_wait(led_wait),
.led_rdy(led_rdy),
.led_done(led_done)
);
Shift_in U2 (
.data(data),
.load(GO),
.A(A_w),
.B(B_w)
);
ALU U3 (
.opcode(opcode),
.A(A_w),
.B(B_w),
.result(result),
.cout(cout),
.borrow(borrow)
);
endmodule
| 7.246696 |
module ALU_State (
input clk,
input GO,
input reset,
output reg led_idle,
output reg led_wait,
output reg led_rdy,
output reg led_done
);
reg [3:0] state;
initial begin
led_idle = 0;
led_wait = 0;
led_rdy = 0;
led_done = 0;
state = 0;
end
parameter IDLE = 0;
parameter LOAD = 1;
parameter DONE = 2;
parameter READY = 3;
always @(posedge clk or posedge reset) begin
if (reset) state = IDLE;
else
case (state)
IDLE: begin
if (GO) state = LOAD;
else state = state;
end
LOAD: begin
if (!GO) state = READY;
else state = state;
end
READY: begin
state = DONE;
end
DONE: begin
if (GO) state = LOAD;
else state = state;
end
default: begin
state = state;
end
endcase
end
always @(*) begin
case (state)
IDLE: begin
led_idle = 1;
led_wait = 0;
led_rdy = 0;
led_done = 0;
end
LOAD: begin
led_idle = 0;
led_wait = 1;
led_rdy = 0;
led_done = 0;
end
DONE: begin
led_idle = 0;
led_wait = 0;
led_rdy = 0;
led_done = 1;
end
READY: begin
led_idle = 0;
led_wait = 0;
led_rdy = 1;
led_done = 0;
end
default: begin
led_idle = 0;
led_wait = 0;
led_rdy = 0;
led_done = 0;
end
endcase
end
endmodule
| 7.374085 |
module Shift_in (
input [3:0] data,
input load,
output reg [3:0] A,
output reg [3:0] B
);
initial begin
A = 0;
B = 0;
end
always @(posedge load) begin
A = data;
end
always @(negedge load) begin
B = data;
end
endmodule
| 7.292331 |
module ALU (
input [2:0] opcode,
input [3:0] A,
input [3:0] B,
output reg [3:0] result,
output reg cout,
output reg borrow
);
initial begin
result = 0;
cout = 0;
borrow = 0;
end
parameter ADD = 0;
parameter SUBTRACT = 1;
parameter NOTa = 2;
parameter NOTb = 3;
parameter AND = 4;
parameter OR = 5;
parameter XOR = 6;
parameter XNOR = 7;
always @(*) begin
case (opcode)
ADD: begin
{cout, result} = A + B;
borrow = 0;
end
SUBTRACT: begin
{borrow, result} = A - B;
cout = 0;
end
NOTa: begin
result = ~A;
{cout, borrow} = 0;
end
NOTb: begin
result = ~B;
{cout, borrow} = 0;
end
AND: begin
result = A & B;
{cout, borrow} = 0;
end
OR: begin
result = A | B;
{cout, borrow} = 0;
end
XOR: begin
result = A ^ B;
{cout, borrow} = 0;
end
XNOR: begin
result = ~(A ^ B);
{cout, borrow} = 0;
end
default: begin
result = result;
{cout, borrow} = {cout, borrow};
end
endcase
end
endmodule
| 7.960621 |
module alucell (
ai,
gi,
bi,
pih,
piv,
pi,
ti,
ao,
go,
poh,
pov,
po
);
input [8:1] ai, gi, bi;
input [1:8] ti;
input pi;
input [1:7] pih, piv;
output [8:1] ao, go;
output po;
output [1:7] poh, pov;
wire [1:7] po1, po2, po3, po4, po5, po6, po7;
firstrow pe1 (
ai,
gi,
pih,
{piv, pi},
bi[8],
ti[1],
po1,
pov[1]
);
generalrow pe2 (
ai,
gi,
po1,
bi[7],
ti[2],
po2,
pov[2]
);
generalrow pe3 (
ai,
gi,
po2,
bi[6],
ti[3],
po3,
pov[3]
);
generalrow pe4 (
ai,
gi,
po3,
bi[5],
ti[4],
po4,
pov[4]
);
generalrow pe5 (
ai,
gi,
po4,
bi[4],
ti[5],
po5,
pov[5]
);
generalrow pe6 (
ai,
gi,
po5,
bi[3],
ti[6],
po6,
pov[6]
);
generalrow pe7 (
ai,
gi,
po6,
bi[2],
ti[7],
po7,
pov[7]
);
generalrow pe8 (
ai,
gi,
po7,
bi[1],
ti[8],
poh,
po
);
assign ao = ai;
assign go = gi;
endmodule
| 6.686049 |
module ALUControl (
input [1:0] ALUOp,
input [5:0] Function,
output reg [2:0] ALU_Control
);
wire [7:0] ALUControlIn;
assign ALUControlIn = {ALUOp, Function};
always @(ALUControlIn) begin
casex (ALUControlIn)
8'b01xxxxxx: ALU_Control <= 3'b010; //lw, sw
8'b10xxxxxx: ALU_Control <= 3'b011; //control flow
8'b11xxxxxx: ALU_Control <= 3'b100; //set less than i
8'b00100100: ALU_Control <= 3'b000; //r_type(and)
8'b00101100: ALU_Control <= 3'b001; //r_type(or)
8'b00000100: ALU_Control <= 3'b010; //r_type(add)
8'b00010100: ALU_Control <= 3'b011; //r_type(sub)
8'b00010101: ALU_Control <= 3'b100; //r_type(slt)
default: ALU_Control <= 3'b000;
endcase
end
endmodule
| 8.639118 |
module JR_Control (
input [1:0] alu_op,
input [5:0] funct,
output pcsrc3
);
assign pcsrc3 = ({alu_op, funct} == 8'b00000001) ? 1'b0 : 1'b1;
endmodule
| 6.633219 |
module ALU (
input [15:0] A,
input [15:0] B,
input Cin,
input [3:0] OP,
output [15:0] C,
output Cout
);
wire [15:0] Arithmetic;
wire Overflow;
// activate Cout on arithmetic opertion +/-
// implemented using the fact that OP_add is 0000 and OP_sub is 0001
assign {Overflow,Arithmetic} = ( OP==`OP_ADD ? {1'b0,A[15:0]}+({1'b0,B[15:0]}+Cin) :
OP==`OP_SUB ? {1'b0,A[15:0]}-({1'b0,B[15:0]}+Cin) :
/* else */ 0);
assign Cout = Overflow;
// implemented the main stream of ALU by a long chain of ternary opertor
assign C = OP==`OP_ADD ? Arithmetic :
OP==`OP_SUB ? Arithmetic :
OP==`OP_ID ? A :
OP==`OP_NAND ? ~(A&B) :
OP==`OP_NOR ? ~(A|B) :
OP==`OP_XNOR ? (A~^B) :
OP==`OP_NOT ? ~A :
OP==`OP_AND ? (A&B) :
OP==`OP_OR ? (A|B) :
OP==`OP_XOR ? (A^B) :
OP==`OP_LRS ? {1'b0,A[15:1]} : // used concatenation opertor
OP == `OP_ARS ? {A[15], A[15:1]} : // for immediate provision of values with mixed order
OP==`OP_RR ? {A[0],A[15:1]} :
OP==`OP_LHI ? {B[7:0],8'h00} :
OP==`OP_ALS ? {A[14:0],1'b0} :
{A[14:0],A[15]} ;
endmodule
| 7.960621 |
module alucont (
aluop1,
aluop0,
f5,
f4,
f3,
f2,
f1,
f0,
gout,
brnout
); //Figure 4.12
input aluop1, aluop0, f5, f4, f3, f2, f1, f0;
output [2:0] gout;
output brnout;
reg [2:0] gout;
reg brnout;
always @(aluop1 or aluop0 or f5 or f4 or f3 or f2 or f1 or f0) begin
if (~(aluop1 | aluop0)) gout = 3'b010;
if (aluop0) gout = 3'b110;
if(aluop1)//R-type
begin
if (f5 & ~f4 & ~f3 & ~f2 & ~f1 & ~f0)
gout = 3'b010; //function code=100000,ALU control=010 (2)(add)
if (f5 & ~f4 & f3 & ~f2 & f1 & ~f0)
gout = 3'b111; //function code=101010,ALU control=111 (7)(set on less than)
if (f5 & ~f4 & ~f3 & ~f2 & f1 & ~f0)
gout = 3'b110; //function code=100010,ALU control=110 (6)(sub)
if (f5 & ~f4 & ~f3 & f2 & ~f1 & f0)
gout = 3'b001; //function code=100101,ALU control=001 (1)(or)
if (f5 & ~f4 & ~f3 & f2 & ~f1 & ~f0)
gout = 3'b000; //function code=100100,ALU control=000 (0)(and)
if (~f5 & f4 & ~f3 & f2 & ~f1 & f0)
gout=3'b010; //function code=010101,ALU control=010 (2)(brn), same as add since it will only add 0
brnout = (~f5 & f4 & ~f3 & f2 & ~f1 & f0);
if (~f5 & ~f4 & ~f3 & f2 & ~f1 & ~f0)
gout=3'b011; //function code=000100, ALU control=011 (3)(sllv), since this is a brand new instruction with shift operation
end
end
endmodule
| 6.74583 |
module ALUControl (
input clock,
input reset,
input io_aluop,
input io_itype,
input [6:0] io_funct7,
input [2:0] io_funct3,
output [3:0] io_operation
);
wire [2:0] _GEN_0 = io_itype | io_funct7 == 7'h0 ? 3'h7 : 3'h4; // @[]
wire [1:0] _GEN_1 = io_funct7 == 7'h0 ? 2'h2 : 2'h3; // @[]
wire [2:0] _GEN_2 = io_funct3 == 3'h6 ? 3'h5 : 3'h6; // @[]
wire [2:0] _GEN_3 = io_funct3 == 3'h5 ? {{1'd0}, _GEN_1} : _GEN_2; // @[]
wire [2:0] _GEN_4 = io_funct3 == 3'h4 ? 3'h0 : _GEN_3; // @[]
wire [2:0] _GEN_5 = io_funct3 == 3'h3 ? 3'h1 : _GEN_4; // @[]
wire [3:0] _GEN_6 = io_funct3 == 3'h2 ? 4'h9 : {{1'd0}, _GEN_5}; // @[]
wire [3:0] _GEN_7 = io_funct3 == 3'h1 ? 4'h8 : _GEN_6; // @[]
wire [3:0] _GEN_8 = io_funct3 == 3'h0 ? {{1'd0}, _GEN_0} : _GEN_7; // @[]
assign io_operation = io_aluop ? _GEN_8 : 4'h7; // @[]
endmodule
| 8.639118 |
module ALUControl (
OpCode,
Funct,
ALUCtrl,
Sign
);
input [5:0] OpCode;
input [5:0] Funct;
output reg [4:0] ALUCtrl;
output Sign;
// Your code below
parameter aluADD = 5'b00000;
parameter aluOR = 5'b00001;
parameter aluAND = 5'b00010;
parameter aluSUB = 5'b00110;
parameter aluSLT = 5'b00111;
parameter aluNOR = 5'b01100;
parameter aluXOR = 5'b01101;
parameter aluSRL = 5'b10000;
parameter aluSRA = 5'b11000;
parameter aluSLL = 5'b11001;
reg Sign;
always @(*) begin
if (OpCode == 6'h00) Sign = ~Funct[0];
else Sign = ~OpCode[0];
end
reg [4:0] aluFunct;
always @(*) begin
case (Funct)
6'b00_0000: aluFunct <= aluSLL;
6'b00_0010: aluFunct <= aluSRL;
6'b00_0011: aluFunct <= aluSRA;
6'b10_0000: aluFunct <= aluADD;
6'b10_0001: aluFunct <= aluADD;
6'b10_0010: aluFunct <= aluSUB;
6'b10_0011: aluFunct <= aluSUB;
6'b10_0100: aluFunct <= aluAND;
6'b10_0101: aluFunct <= aluOR;
6'b10_0110: aluFunct <= aluXOR;
6'b10_0111: aluFunct <= aluNOR;
6'b10_1010: aluFunct <= aluSLT;
6'b10_1011: aluFunct <= aluSLT;
default: aluFunct <= aluADD;
endcase
end
always @(*) begin
case (OpCode)
6'h04: ALUCtrl <= aluSUB;
6'h0c: ALUCtrl <= aluAND;
6'h0a: ALUCtrl <= aluSLT;
6'h0b: ALUCtrl <= aluSLT;
6'h00: ALUCtrl <= aluFunct;
default: ALUCtrl <= aluADD;
endcase
end
// Your code above
endmodule
| 8.639118 |
module ALUControl_MyTest_v;
task passTest;
input [5:0] actualOut, expectedOut;
input [`STRLEN*8:0] testType;
inout [7:0] passed;
if (actualOut == expectedOut) begin
$display("%s passed", testType);
passed = passed + 1;
end else $display("%s failed: %d should be %d", testType, actualOut, expectedOut);
endtask
task allPassed;
input [7:0] passed;
input [7:0] numTests;
if (passed == numTests) $display("All tests passed"); //Display if all the tests have passed
else $display("Some tests failed");
endtask
// Inputs
reg [3:0] ALUop;
reg [5:0] FuncCode;
reg [7:0] passed;
// Outputs
wire [3:0] ALUCtrl;
// Instantiate the Unit Under Test (UUT)
ALUControl uut (
.ALUCtrl(ALUCtrl),
.ALUop(ALUop),
.FuncCode(FuncCode)
);
initial begin
// Initialize Inputs
passed = 0;
ALUop = 0;
FuncCode = 0;
//1: Checks for OverWrite ADD
{FuncCode, ALUop} = {6'bXXXXXX, 4'b0010};
#40;
passTest(ALUCtrl, 4'b0010, "(OverWrite ADD)", passed);
$display("ALUop == %b, FuncCode == %b, ALUCtrl == %b\n", ALUop, FuncCode, ALUCtrl);
//2: Checks for OverWrite SUB
{FuncCode, ALUop} = {6'bXXXXXX, 4'b0110};
#40;
passTest(ALUCtrl, 4'b0110, "(OverWrite SUB)", passed);
$display("ALUop == %b, FuncCode == %b, ALUCtrl == %b\n", ALUop, FuncCode, ALUCtrl);
//3: Checks SLL
{FuncCode, ALUop} = {`SLLFunc, 4'b1111};
#40;
passTest(ALUCtrl, 4'b0011, "(SLL)", passed);
$display("ALUop == %b, FuncCode == %b, ALUCtrl == %b\n", ALUop, FuncCode, ALUCtrl);
//4: Checks SRL
{FuncCode, ALUop} = {`SRLFunc, 4'b1111};
#40;
passTest(ALUCtrl, 4'b0100, "(SRL)", passed);
$display("ALUop == %b, FuncCode == %b, ALUCtrl == %b\n", ALUop, FuncCode, ALUCtrl);
//5: Checks ADD
{FuncCode, ALUop} = {`ADDFunc, 4'b1111};
#40;
passTest(ALUCtrl, 4'b0010, "(ADD)", passed);
$display("ALUop == %b, FuncCode == %b, ALUCtrl == %b\n", ALUop, FuncCode, ALUCtrl);
//6: Checks SUB
{FuncCode, ALUop} = {`SUBFunc, 4'b1111};
#40;
passTest(ALUCtrl, 4'b0110, "(SUB)", passed);
$display("ALUop == %b, FuncCode == %b, ALUCtrl == %b\n", ALUop, FuncCode, ALUCtrl);
//7: Checks AND
{FuncCode, ALUop} = {`ANDFunc, 4'b1111};
#40;
passTest(ALUCtrl, 4'b0000, "(AND)", passed);
$display("ALUop == %b, FuncCode == %b, ALUCtrl == %b\n", ALUop, FuncCode, ALUCtrl);
//8: Checks OR
{FuncCode, ALUop} = {`ORFunc, 4'b1111};
#40;
passTest(ALUCtrl, 4'b0001, "(OR)", passed);
$display("ALUop == %b, FuncCode == %b, ALUCtrl == %b\n", ALUop, FuncCode, ALUCtrl);
//9: Checks SLT
{FuncCode, ALUop} = {`SLTFunc, 4'b1111};
#40;
passTest(ALUCtrl, 4'b0111, "(SLT)", passed);
$display("ALUop == %b, FuncCode == %b, ALUCtrl == %b\n", ALUop, FuncCode, ALUCtrl);
allPassed(passed, 9);
end
endmodule
| 7.301268 |
module: ALU_Control
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALUControlTest;
// Inputs
reg [1:0] ALUOp;
reg [5:0] function_field;
// Outputs
wire [3:0] ALUCtrl;
// Instantiate the Unit Under Test (UUT)
ALU_Control uut (
.ALUOp(ALUOp),
.function_field(function_field),
.ALUCtrl(ALUCtrl)
);
initial begin
// Initialize Inputs
ALUOp = 0;
function_field = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.194599 |
module: ALUControlUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALUControlUnit_TEST;
// Inputs
reg [2:0] ALUOp;
reg [5:0] funct;
// Outputs
wire [3:0] ALUCnt;
// Instantiate the Unit Under Test (UUT)
ALUControlUnit uut (
.ALUOp(ALUOp),
.funct(funct),
.ALUCnt(ALUCnt)
);
always #20 funct = funct + 1;
initial begin
// Initialize Inputs
ALUOp = 0;
funct = 0;
#200 ALUOp = 3'b001;
#250 ALUOp = 3'b010;
#300 ALUOp = 3'b011;
// Wait 100 ns for global reset to finish
#1000 $finish;
// Add stimulus here
end
endmodule
| 8.370485 |
module ALUControl_Block (
ALUControl,
ALUOp,
Function
);
output [1:0] ALUControl;
reg [1:0] ALUControl;
input [1:0] ALUOp;
input [5:0] Function;
wire [7:0] ALUControlIn;
assign ALUControlIn = {ALUOp, Function};
always @(ALUControlIn)
casex (ALUControlIn)
8'b11xxxxxx: ALUControl = 2'b01;
8'b00xxxxxx: ALUControl = 2'b00;
8'b01xxxxxx: ALUControl = 2'b10;
8'b10100000: ALUControl = 2'b00;
8'b10100010: ALUControl = 2'b10;
8'b10101010: ALUControl = 2'b11;
default: ALUControl = 2'b00;
endcase
endmodule
| 7.200402 |
module ALUControl_tb;
// Inputs
reg [5:0] funct;
reg [2:0] ALUOp;
// Outputs
wire [3:0] ALUCnt;
// Instantiate the Unit Under Test (UUT)
ALUControl uut (
.funct (funct),
.ALUOp (ALUOp),
.ALUCnt(ALUCnt)
);
initial begin
// Initialize Inputs
funct = 0;
ALUOp = 0;
// Wait 100 ns for global reset to finish
#100;
funct = 1;
#100;
funct = 2;
#100;
funct = 3;
#100;
funct = 4;
#100;
funct = 5;
#100;
funct = 6;
#100;
funct = 7;
#100;
funct = 8;
#100;
ALUOp = 1;
#100;
ALUOp = 2;
#100;
ALUOp = 3;
#100;
ALUOp = 4;
// Add stimulus here
end
endmodule
| 6.689514 |
module ALUControl_tb2;
// Inputs
reg [5:0] funct;
reg [2:0] ALUOp;
// Outputs
wire [3:0] ALUCnt;
// Instantiate the Unit Under Test (UUT)
ALUControl uut (
.funct (funct),
.ALUOp (ALUOp),
.ALUCnt(ALUCnt)
);
initial begin
// Initialize Inputs
funct = 0;
ALUOp = 0;
// Wait 100 ns for global reset to finish
#100;
funct = 1;
#100;
funct = 2;
#100;
funct = 3;
#100;
funct = 4;
#100;
funct = 5;
#100;
funct = 6;
#100;
funct = 7;
#100;
funct = 8;
#100;
ALUOp = 1;
#100;
ALUOp = 2;
#100;
ALUOp = 3;
#100;
ALUOp = 4;
// Add stimulus here
end
endmodule
| 6.689514 |
module alucontrol_stimulus;
reg [1:0] aluop;
reg [5:0] fun;
wire [3:0] aluctrl;
reg [1:0] aluop_in[0:7];
reg [5:0] fun_in[0:7];
reg [3:0] aluctrl_in[0:7];
reg [3:0] aluctrl_cmp;
alucontrol_v2 myAlucontrol (
.aluop(aluop),
.fun(fun),
.aluctrl(aluctrl)
);
integer i;
initial begin
$readmemb("aluop_test.txt", aluop_in);
$readmemb("function_test.txt", fun_in);
$readmemb("output_test.txt", aluctrl_in);
#2
for (i = 0; i < 8; i = i + 1) begin
aluop = aluop_in[i];
fun = fun_in[i];
aluctrl_cmp = aluctrl_in[i];
$display("Op: %b, Fun: %b, Output: %b.", aluop, fun, aluctrl_cmp);
#2 $display("Ouput is -> %b", aluctrl);
if (aluctrl == aluctrl_cmp) begin
$display("Passed ALU testvector %d", i);
end else begin
$display("Failed ALU testvector %d", i);
end
end
end
endmodule
| 7.947841 |
module: ALUControl
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALUControl_tf;
// Inputs
reg [1:0] ALUOp;
reg [5:0] FuncCode;
// Outputs
wire [3:0] ALUCtl;
// Instantiate the Unit Under Test (UUT)
ALUControl uut (
.ALUOp(ALUOp),
.FuncCode(FuncCode),
.ALUCtl(ALUCtl)
);
initial begin
// Initialize Inputs
ALUOp = 0;
FuncCode = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#10 ALUOp=2'b00;
#10 ALUOp=2'b01;
#10 ALUOp=2'b10;
#10 FuncCode = 6'h20; //add
#10 FuncCode = 6'h22; //substract
#10 FuncCode = 6'h24; //and
#10 FuncCode = 6'h25; //or
#10 FuncCode = 6'h27; //nor
#10 FuncCode = 6'h2a; //slt
end
endmodule
| 7.099352 |
module alucontrol_v2 (
aluOp0,
aluOp1,
fun,
aluctrl
);
input wire aluOp0, aluOp1;
input wire [5:0] fun;
output reg [3:0] aluctrl;
//Evaluate when any input changes.
always @(aluOp0 or aluOp1 or fun) begin
casex ({
aluOp1, aluOp0, fun
}) //For casex a ? represents a don't care. Simply set aluctrl to the case that matches.
8'b00??????: begin
aluctrl = 4'b0010;
end
8'b01??????: begin
aluctrl = 4'b0110;
end
8'b10100000: begin
aluctrl = 4'b0010;
end
8'b10100010: begin
aluctrl = 4'b0110;
end
8'b10100100: begin
aluctrl = 4'b0000;
end
8'b10100101: begin
aluctrl = 4'b0001;
end
8'b10101010: begin
aluctrl = 4'b0111;
end
default: begin
//In case that its not possible to match
//printout an error and set the aluctrl
//to an invalid value.
$display("Error in ALU Control.");
aluctrl = 4'b1111;
end
endcase
end
endmodule
| 7.287868 |
module alucont (
aluop1,
aluop0,
f5,
f4,
f3,
f2,
f1,
f0,
gout
); //Figure 4.12
input aluop1, aluop0, f5, f4, f3, f2, f1, f0;
output [2:0] gout;
reg [2:0] gout;
always @(aluop1 or aluop0 or f5 or f4 or f3 or f2 or f1 or f0) begin
if (~(aluop1 | aluop0)) gout = 3'b010; //(add - 00) => sw - lw - jm
if (aluop0 & ~(aluop1)) gout = 3'b110; //(sub - 01) => bez - bgez
if (aluop0 & aluop1) gout = 3'b000; //(andi - 11) => andi
if(aluop1&~(aluop0)) //R-type (10)
begin
if (~(f3 | f2 | f1 | f0)) gout = 3'b010; //function code=0000,ALU control=010 (add)
if (f1 & f3 & ~(f0) & ~(f2))
gout = 3'b111; //function code=1010,ALU control=111 (set on less than)
if (f1 & ~(f3) & ~(f0) & ~(f2)) gout = 3'b110; //function code=0010,ALU control=110 (sub)
if (f2 & f0 & ~(f3) & ~(f1)) gout = 3'b001; //function code=0101,ALU control=001 (or)
if (f2 & ~(f0) & ~(f1) & ~(f3) & f5)
gout = 3'b000; //function code=100100,ALU control=000 (and)
if (f2 & ~(f0) & ~(f1) & ~(f3) & ~(f4) & ~(f5))
gout = 3'b100; //function code=000100,ALU control=100 (sllv) ----
end
end
endmodule
| 6.74583 |
module ALUCt (
input rst,
input [5:0] funct,
input [1:0] alu_ct_op,
output reg [3:0] alu_ct
);
always @(*) begin
if (!rst) alu_ct = 0;
else
case (alu_ct_op)
2'b00: alu_ct = 4'b0010; //加法
2'b01: alu_ct = 4'b0110; //减法
2'b11: alu_ct = 4'b0000; //作比较<
2'b10: begin
case (funct) //R型指令
6'b100001: alu_ct = 4'b0010;
default: alu_ct = 0;
endcase
end
default: alu_ct = 0;
endcase
end
endmodule
| 6.617956 |
module ALUctrl (
Clk,
op,
func,
ALUctr
);
input Clk;
input [5:0] op;
input [5:0] func;
output reg [3:0] ALUctr;
parameter R = 6'b000000;
always @(posedge Clk) begin
case (op)
R: begin
//P168
ALUctr[3]=(!func[4]&!func[3]&func[2]&func[1])+(!func[5]&!func[4]&!func[3]&!func[2]&!func[0])+(!func[5]&!func[4]&!func[3]&func[2]&!func[1]&!func[0])+(!func[5]&!func[4]&!func[3]&!func[2]&func[1]&func[0]);
ALUctr[2]=(func[5]&!func[4]&!func[3]&!func[2]&func[1])+(func[5]&!func[4]&func[3]&!func[2]&func[1])+(!func[5]&!func[4]&!func[3]&func[1]&func[0])+(!func[5]&!func[4]&!func[3]&func[2]&!func[0]);
ALUctr[1]=(func[5]&!func[4]&func[3]&!func[2]&func[1])+(func[5]&!func[4]&!func[3]&func[2]&!func[1])+(!func[5]&!func[4]&!func[3]&!func[2]&!func[0])+(!func[5]&!func[4]&!func[3]&func[2]&func[1]);
ALUctr[0]=(func[5]&!func[4]&!func[3]&func[2]&!func[0])+(!func[5]&!func[4]&!func[3]&!func[2]&func[1])+(func[5]&!func[4]&!func[3]&!func[2]&!func[0])+(func[5]&!func[4]&func[3]&!func[2]&func[1]&!func[0])+(!func[5]&!func[4]&!func[3]&func[2]&func[1]&!func[0]);
//{!func[2]&func[1],(func[3]&!func[2]&func[1])+(!func[3]&func[2]&!func[1]),(!func[3]&!func[1]&!func[0])+(!func[2]&func[1]&!func[0])};
end
default: begin
//P167
ALUctr[3] = !op[5] & !op[4] & op[3] & op[2] & op[1] & !op[0];
ALUctr[2]=(!op[5]&!op[4]&!op[3]&op[2]&!op[1])+(!op[5]&!op[4]&op[3]&!op[2]&op[1]);
ALUctr[1]=(!op[5]&!op[4]&op[3]&!op[2]&op[1])+(!op[5]&!op[4]&op[3]&op[2]&!op[1]);
ALUctr[0]=(!op[5]&!op[4]&op[3]&!op[2]&!op[0])+(!op[5]&!op[4]&op[3]&op[2]&!op[0])+(op[5]&!op[4]&!op[3]&!op[2]&!op[1]&!op[0])+(op[5]&!op[4]&op[3]&!op[2]&!op[1]&!op[0]);
/*(!op[5]&!op[4]&op[3]&!op[2]&!op[0])+(!op[5]&!op[4]&op[3]&!op[2]&!op[0])
+(op[5]&!op[4]&!op[3]&!op[2]&!op[1]&!op[0])
+(op[5]&!op[4]&!op[3]&op[2]&!op[1]&!op[0])
+(op[5]&!op[4]&op[3]&!op[2]&!op[1]&!op[0])
+(!op[5]&!op[4]&op[3]&op[2]&op[1]&!op[0]);*/
//ALUctr[3:0] = {1'b0,!op[5]&!op[4]&!op[3]&op[2]&!op[1]&!op[0],!op[5]&!op[4]&op[3]&op[2]&!op[1]&op[0],(!op[5]&!op[4]&!op[3]&!op[2]&!op[1]&!op[0])+(!op[5]&!op[4]&op[3]&!op[2]&!op[1]&!op[0])};
end
endcase
end
endmodule
| 6.533673 |
module aluctrl_testbench;
reg [3:0] func;
reg [1:0] op;
wire [3:0] ctrl_out;
ALUCtrl uut (
.func(func),
.alu_op(op),
.alu_ctrl(ctrl_out)
);
task check_alu_ctrl;
input [3:0] test_num;
input [3:0] expected_ctrl;
input [3:0] got_ctrl;
begin
if (expected_ctrl !== got_ctrl) begin
$display("FAIL - test %d, expected: %b, got: %b", test_num, expected_ctrl, got_ctrl);
$finish;
end else begin
$display("PASS - test %d, got: %b", test_num, got_ctrl);
end
end
endtask
task check_add_op;
begin
$display("====Check Add Operation====");
op = 2'b00;
func = 4'b0000;
#1 check_alu_ctrl(1, 4'b0010, ctrl_out);
op = 2'b10;
func = 4'b0000;
#1 check_alu_ctrl(2, 4'b0010, ctrl_out);
end
endtask
task check_subtract_op;
begin
$display("====Check Subtract Operation====");
op = 2'b01;
func = 4'b0000;
#1 check_alu_ctrl(1, 4'b0110, ctrl_out);
op = 2'b10;
func = 4'b1000;
#1 check_alu_ctrl(2, 4'b0110, ctrl_out);
end
endtask
task check_AND_op;
begin
$display("====Check AND Operation====");
op = 2'b10;
func = 4'b0111;
#1 check_alu_ctrl(1, 4'b0000, ctrl_out);
end
endtask
task check_OR_op;
begin
$display("====Check OR Operation====");
op = 2'b10;
func = 4'b0110;
#1 check_alu_ctrl(1, 4'b0001, ctrl_out);
end
endtask
initial begin
check_add_op();
check_subtract_op();
check_AND_op();
check_OR_op();
$display("ALL ALUCTRL TESTS PASSED!");
$finish;
end
endmodule
| 6.666479 |
module aluCU (
oper,
aluOp,
funcfield
);
input [1:0] aluOp;
input [3:0] funcfield;
output [2:0] oper;
assign oper[0] = (funcfield[0] | funcfield[3]) & aluOp[1];
assign oper[1] = ((~aluOp[1]) | (~funcfield[2]));
assign oper[2] = (aluOp[0] | (aluOp[1] & funcfield[1]));
endmodule
| 7.119252 |
module ALUDecoder (
ALUControl,
ALUOpcode,
funct3,
funct7,
opcode5
);
`include "Parameters.vh"
input [1 : 0] ALUOpcode;
input [2 : 0] funct3;
// The ALU decoder use funct7 and opcode[5] to determine ALU control
input funct7;
input opcode5;
output reg [2 : 0] ALUControl;
reg [1 : 0] subOpcode;
// This always block is the implementation of ALU decoder's truth table
always @(*) begin
case (ALUOpcode)
2'b00: ALUControl <= ADD_OPCODE; // lw, sw
2'b01: ALUControl <= SUB_OPCODE; // beq
2'b10: begin
case (funct3)
3'b000: begin
subOpcode = {opcode5, funct7};
ALUControl = (subOpcode == 2'b11) ? SUB_OPCODE : ADD_OPCODE; // add or sub
end
3'b010: ALUControl <= SLT_OPCODE; // slt
3'b110: ALUControl <= OR_OPCODE; // or
3'b111: ALUControl <= AND_OPCODE; // and
endcase
end
endcase
end
endmodule
| 6.68279 |
module aluDemo (
LEDR,
HEX5,
HEX3,
HEX2,
HEX1,
HEX0,
SW,
KEY,
CLOCK_50
);
//DE1-SoC wire interface for driving hardware
output [9:0] LEDR;
output [6:0] HEX5, HEX3, HEX2, HEX1, HEX0;
input CLOCK_50;
input [9:0] SW;
input [3:0] KEY;
wire clk; // choosing from 32 different clock speeds
wire [3:0] operand;
wire [2:0] control;
wire [1:0] modeSel;
wire [31:0] result;
wire cFlag, nFlag, vFlag, zFlag;
wire enter;
wire run;
reg [15:0] resultDisp;
reg [3:0] flagReg;
reg [15:0] opA;
reg [15:0] opB;
reg [1:0] digitSel;
reg [15:0] display;
assign LEDR = {6'b0, flagReg}; //Disable LEDs
assign operand = SW[3:0];
assign control = SW[6:4];
assign modeSel = SW[9:8];
// Press detect for the enter and run keys
pressDetectDelay myEnterToggle (
.outToggle(enter),
.inPress(~KEY[0]),
.clk(clk)
);
pressDetectDelay myRunToggle (
.outToggle(run),
.inPress(~KEY[1]),
.clk(clk)
);
// instantiate clock_divider module
clock_divider cdiv (
.clk_out (clk),
.clk_in (CLOCK_50),
.slowDown(SW[7])
);
// instantiate the ALU module, either alu_behav or alu
alu myALU (
.busOut(result),
.zero(zFlag),
.overflow(vFlag),
.carry(cFlag),
.neg(nFlag),
.busA({{16{opA[15]}}, opA}),
.busB({{16{opB[15]}}, opB}),
.control(control)
);
// Drivers for the 7-segment 4 hex displays
hexDriver myHex3 (
HEX3,
display[15:12]
);
hexDriver myHex2 (
HEX2,
display[11:8]
);
hexDriver myHex1 (
HEX1,
display[7:4]
);
hexDriver myHex0 (
HEX0,
display[3:0]
);
//Display which digit is being editted with HEX5
hexDriver myHex5 (
HEX5,
{2'b0, digitSel[1:0]}
);
parameter [1:0] modifyA = 2'b00, modifyB = 2'b01;
always @(posedge clk) begin
// Store the results of the ALU when run is toggled
if (run) begin
resultDisp <= result[15:0];
flagReg <= {cFlag, nFlag, vFlag, zFlag};
end else begin //Explicit latching
resultDisp <= resultDisp;
flagReg <= flagReg;
end
// Set the display dependent on switches 9 and 8
case (modeSel)
modifyA: begin
if (enter) begin
digitSel <= digitSel + 2'b1;
case (digitSel)
2'b00: opA[3:0] <= operand;
2'b01: opA[7:4] <= operand;
2'b10: opA[11:8] <= operand;
2'b11: opA[15:12] <= operand;
default: opA <= opA;
endcase
end
display <= opA;
end
modifyB: begin
if (enter) begin
digitSel <= digitSel + 2'b1;
case (digitSel)
2'b00: opB[3:0] <= operand;
2'b01: opB[7:4] <= operand;
2'b10: opB[11:8] <= operand;
2'b11: opB[15:12] <= operand;
default: opB <= opB;
endcase
end
display <= opB;
end
default: begin //display result
digitSel <= 2'b0;
display <= resultDisp;
end
endcase
end
endmodule
| 9.663607 |
module clock_divider (
clk_out,
clk_in,
slowDown
);
output clk_out;
reg [31:0] divided_clocks;
input clk_in, slowDown;
//Choose clock frequency for signal tap display or LED display
assign clk_out = slowDown ? divided_clocks[23] : clk_in;
initial divided_clocks = 0;
always @(posedge clk_in) divided_clocks = divided_clocks + 1;
endmodule
| 6.818038 |
module ALU (
in1,
in2,
c,
aluout
);
input [2:0] in1, in2;
input [1:0] c;
output reg [2:0] aluout;
always @(in1, in2, c) begin
if (c == 2'b11) //Add
aluout = in1 + in2;
else if (c == 2'b10) //Subtract
aluout = in1 - in2;
else if (c == 2'b01) //And
aluout = in1 & in2;
else //Xor
aluout = in1 ^ in2;
end
endmodule
| 7.37871 |
module aluFile_testbench ();
reg [63:0] a, b;
reg Cin;
reg [4:0] sel;
wire [63:0] out;
wire cOut;
wire [3:0] status;
aluFile dut (
a,
b,
Cin,
sel,
out,
cOut,
status
);
initial begin
$monitor("sel=%d a=%d b=%d out=%d Cin=%d cOut=%d status=%d", sel, a, b, out, Cin, cOut, status);
a = 64'd3;
b = 64'd1;
sel = 5'b10000;
Cin = 1'd0; //A+1
#50;
a = 64'd2;
b = 64'd2;
sel = 5'b10000;
Cin = 1'd0; //A + B
#50;
a = 64'd3;
b = 64'd2;
sel = 5'b10010;
Cin = 1'd1; //A - B
#50;
a = 64'd3;
b = 64'd1;
sel = 5'b10010;
Cin = 1'd1; //A -1
#50;
a = 64'd2;
b = 64'd4;
sel = 5'b10010;
Cin = 1'd1; //-A
#50;
a = 64'd0;
b = 64'd0;
sel = 5'b10000;
Cin = 1'd0; // F = 0, also the zero flag
#50;
a = 64'd1;
b = 64'd0;
sel = 5'b10000;
Cin = 1'd0; // A
#50;
a = 64'd11;
b = 64'd0;
sel = 5'b10001;
Cin = 1'd0; //A~
#50;
a = 64'd11;
b = 64'd14;
sel = 5'b10100;
Cin = 1'd0; // A&B
#50;
a = 64'd3;
b = 64'd4;
sel = 5'b00100;
Cin = 1'd0; //A|B
#50;
a = 64'd2;
b = 64'd5;
sel = 5'b01100;
Cin = 1'd0; //A^B
#50;
a = 64'd23;
b = 5'd3;
sel = 5'b10100;
Cin = 1'd0; //shift right
#50;
a = 64'd23;
b = 5'd3;
sel = 5'b11000;
Cin = 1'd0; //shift left
#50;
a = 64'd2;
b = 64'd4;
sel = 5'b10010;
Cin = 1'd1; //Negative flag
#50;
a = 64'd4;
b = 64'd6;
sel = 5'b10000;
Cin = 1'd1; //carry out
#50;
a = 64'd7;
b = 64'd2;
sel = 5'b10010;
Cin = 1'd1; //overflow
#50;
a = 64'd3;
b = 64'd4;
sel = 5'b10000;
Cin = 1'd0;
#50;
a = 64'b1000000000000000000000000000000000000000000000000000000000000000;
b = 64'b1000000000000000000000000000000000000000000000000000000000000000;
Cin = 1'd1;
#50;
end
endmodule
| 6.802639 |
module aluforwardingmux (
aluforward,
regdata,
aluresult,
dmresult,
out
);
parameter DWIDTH = 32;
input wire [1:0] aluforward;
input wire [DWIDTH-1:0] regdata;
input wire [DWIDTH-1:0] aluresult;
input wire [DWIDTH-1:0] dmresult;
output reg [DWIDTH-1:0] out;
always @(aluforward, regdata, aluresult, dmresult) begin
case (aluforward)
2'b00: out = regdata;
2'b10: out = aluresult;
2'b01: out = dmresult;
default: out = regdata;
endcase
end
endmodule
| 8.576114 |
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