code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module aluGTK;
wire [31:0] busOut;
wire zero, overflow, carry, neg;
wire [31:0] busA, busB;
wire [2:0] control;
//declare instances of dut and tester modules
alu_behav myalu (
busOut,
zero,
overflow,
carry,
neg,
busA,
busB,
control
);
Tester aTester (
busA,
busB,
control,
busOut,
zero,
overflow,
carry,
neg
);
// file for gtkwave
initial begin
$dumpfile("aluGTK.vcd");
$dumpvars(1, myalu);
end
endmodule
| 6.614873 |
module ALUInputAdapter #(
parameter DATA_BITS = 32
) (
// data lines in
input wire [DATA_BITS - 1:0] RegOut1,
input wire [DATA_BITS - 1:0] RegOut2,
input wire [ 15:0] Immediate,
input wire [ 4:0] ShamtIn,
// signals in
input wire AluSrcB, // Note: probably needs more than 1 bit
input wire [ 1:0] ShamtSel,
input wire SignedExt,
// real data out to ~ALU~
output wire [DATA_BITS - 1:0] AluA,
output reg [DATA_BITS - 1:0] AluB,
output reg [ 4:0] ShamtOut
);
assign AluA = RegOut1;
wire [DATA_BITS - 1:0] immediate_extended;
assign immediate_extended = SignedExt ? {{16{Immediate[15]}}, Immediate} : Immediate;
always @* begin
case (AluSrcB)
0: AluB <= RegOut2;
1: AluB <= immediate_extended;
endcase
end
always @* begin
case (ShamtSel)
0: ShamtOut <= ShamtIn;
1: ShamtOut <= RegOut1[4:0];
2: ShamtOut <= 16;
3: ShamtOut <= 0; // undefined
endcase
end
endmodule
| 7.146599 |
module ALUio (
output [31:0] result,
output N,
Zero,
C,
V,
input [31:0] A,
B,
input MuxD0,
Clk,
Load,
carry,
input [4:0] sel_alu,
sel_cu
);
wire [4:0] sel;
MUX2x1_5bits2 MuxD (
MuxD0,
sel_alu,
sel_cu,
sel
);
ALU alu (
result,
N_,
Zero_,
C_,
V_,
A,
B,
carry,
sel
);
// PSR psr (flags, N, Zero, C, V, N_, Zero_, C_, V_, Clk, Load);
PSR2 psr (
N,
Zero,
C,
V,
N_,
Zero_,
C_,
V_,
Clk,
Load
);
endmodule
| 7.014327 |
module ALUJump_tb;
reg [7:0] inPc;
reg [7:0] ini;
wire [7:0] out;
ALUJump pcALU (
inPc,
ini,
out
);
initial begin
//$dumpfile ("testbench/acOut_tb.vcd");
//$dumpvars(0, acOut_tb);
$monitor("PC = %d, Imediate = %d, Final Addr = %d", inPc, ini, out);
inPc = 8'b00000001;
ini = 8'b10000000;
#20;
inPc = 8'b00001111;
ini = 8'b00000100;
#20;
inPc = 8'b01100001;
ini = 8'b10001100;
#20;
inPc = 8'b00000011;
ini = 8'b10000100;
#20;
$monitor("test completed");
end
endmodule
| 7.077617 |
module ALUM2DR (
clk,
DataIn,
DataOut
);
input clk;
input [31:0] DataIn;
output reg [31:0] DataOut;
always @(posedge clk) begin
#0.002;
DataOut = DataIn;
end
endmodule
| 6.94159 |
module ALUMatrixTop (
clk,
reset,
eleSel,
sel,
eleIn,
eleOut,
LED
);
input clk, reset;
input [4:0] eleSel;
input [5:0] sel;
input [31:0] eleIn;
output [31:0] eleOut;
output [15:0] LED;
ALUCalc zero (
.clk(clk),
.reset(reset),
.eleSel(eleSel),
.sel(sel),
.eleIn(eleIn),
.eleOut(eleOut),
.LED(LED)
);
endmodule
| 6.562062 |
module clock_divider (
clk_out,
clk_in,
slowDown
);
output clk_out;
reg [31:0] divided_clocks;
input clk_in, slowDown;
//Choose clock frequency for signal tap display or LED display
assign clk_out = slowDown ? divided_clocks[1] : clk_in;
initial divided_clocks = 0;
always @(posedge clk_in) divided_clocks = divided_clocks + 1;
endmodule
| 6.818038 |
module AluMisc (
////////////
// INPUTS //
////////////
input clock,
input reset,
input iss_am_oper, // Enables this funcional unit (mutually exclusive
// regarding the other two main functional units'
// signals)
// Whether to save the ALU's or the Shifter's output
input iss_am_selalushift,
// Whether to use an immediate value or a register as the second operand
input iss_am_selimregb,
// ALU operation to be performed
input [2:0] iss_am_aluop,
// Whether or not to perform an unsigned operation
input iss_am_unsig,
// Shifter operation to be performed
input [1:0] iss_am_shiftop,
// Amount to be shifted
input [4:0] iss_am_shiftamt,
// First register (always an operand)
input [31:0] iss_am_rega,
// Second register (not necessarily an operand, an immediate value may be
// used instead)
input [31:0] iss_am_regb,
// Immediate value (may be used as operand)
input [31:0] iss_am_imedext,
// Destination register
input [4:0] iss_am_regdest,
// Whether or not the instruction writes to the ARF
input iss_am_writereg,
// If true, the instruction will write to the ARF even if an overflow
// happens.
input iss_am_writeov,
/////////////
// OUTPUTS //
/////////////
// Register to be written
output reg [4:0] am_wb_regdest,
// Whether or not a write should be performed (takes overflows into account
// or not, depending on iss_am_writeov)
output reg am_wb_writereg,
// Value to be written
output reg [31:0] am_wb_wbvalue,
output reg am_wb_oper
);
wire [31:0] aluout;
wire aluov;
wire [31:0] result;
wire [31:0] mux_imregb;
// wire to which the second operand (register or immediate) is assigned
assign mux_imregb = (iss_am_selimregb) ? iss_am_imedext : iss_am_regb;
Alu ALU (
.a(iss_am_rega),
.b(mux_imregb),
.aluout(aluout),
.op(iss_am_aluop),
.unsig(iss_am_unsig),
.overflow(aluov)
);
Shifter SHIFTER (
.in(iss_am_regb),
.shiftop(iss_am_shiftop),
.shiftamt(iss_am_shiftamt),
.result(result)
);
always @(posedge clock or negedge reset) begin
if (~reset) begin
am_wb_oper <= 1'b0;
am_wb_regdest <= 5'b00000;
am_wb_writereg <= 1'b0;
am_wb_wbvalue <= 32'h0000_0000;
end else if (~iss_am_oper) begin
am_wb_oper <= 1'b0;
am_wb_regdest <= 5'b00000;
am_wb_writereg <= 1'b0;
am_wb_wbvalue <= 32'h0000_0000;
end else begin
am_wb_oper <= 1'b1;
am_wb_regdest <= iss_am_regdest;
am_wb_writereg <= (!aluov | iss_am_writeov) & iss_am_writereg;
am_wb_wbvalue <= (iss_am_selalushift) ? result : aluout;
end
end
endmodule
| 8.256437 |
module AluMisc_TB0;
reg clock;
reg reset;
reg oper;
reg [31:0] op_a;
reg [31:0] op_b;
reg [31:0] imm;
reg [2:0] aluop;
reg imm_or_reg;
wire [4:0] am_wb_regdest;
wire am_wb_writereg;
wire [31:0] res;
wire oper_out;
AluMisc ALUMISC (
.clock(clock),
.reset(reset),
.iss_am_oper(oper),
.iss_am_selalushift(1'b0), // possível bug
.iss_am_selimregb(imm_or_reg),
.iss_am_aluop(aluop),
.iss_am_unsig(1'b0),
.iss_am_shiftop(2'b00),
.iss_am_shiftamt(5'b00000),
.iss_am_rega(op_a),
.iss_am_regb(op_b),
.iss_am_imedext(imm),
.iss_am_writereg(1'b1),
.iss_am_writeov(1'b1),
.am_wb_regdest (am_wb_regdest),
.am_wb_writereg(am_wb_writereg),
.am_wb_wbvalue (res),
.am_wb_oper(oper_out)
);
initial begin
$dumpfile("alumisc_tb0.vcd");
$dumpvars;
$display("Clock\t\tOper\tA\tB\tRes");
$monitor("%d\t%d\t%d\t%d\t%d", clock, oper, op_a, op_b, res);
#500 $finish;
end
initial begin
oper = 1'b0;
imm_or_reg = 1'b0;
imm = 32'h0001_0000;
aluop = 3'b010;
#2 op_a = 32'h0000_0002;
op_b = 32'hFFFF_FFFD;
#2 oper = 1'b1;
#8 oper = 1'b0;
#3 aluop = 3'b110;
#3 oper = 1'b1;
#6 oper = 1'b0;
#500 $finish;
end
initial begin
clock <= 0;
reset <= 1;
#1 reset <= 0;
#2 reset <= 1;
end
always begin
#3 clock <= ~clock;
end
endmodule
| 6.764446 |
module ALUMux (
input [63:0] registerData,
input [63:0] signExtendedData,
input ALUsrc,
output reg [63:0] ALUMUXout
);
always @(*)
case (ALUsrc)
0: ALUMUXout = registerData;
1: ALUMUXout = signExtendedData;
default: ALUMUXout = registerData;
endcase
endmodule
| 7.766766 |
module ALUmux4to1 (
input logic [31:0] register_b,
input logic [15:0] immediate,
input logic [ 5:0] opcode,
input logic [ 1:0] ALUSrcB,
output logic [31:0] ALUB
);
logic [31:0] sign_extended;
logic [31:0] shift_2;
typedef enum logic [5:0] {
LUI = 6'b001111,
ANDI = 6'b001100,
ORI = 6'b001101,
XORI = 6'b001110
} Zero_extend_opcode;
always @(*) begin
//sign extend
if (opcode == ANDI || opcode == ORI || opcode == XORI) begin
sign_extended = 32'b0000 + immediate;
end else if (opcode == LUI) begin
sign_extended = {immediate, 16'b0};
end else begin
if (immediate[15] == 1) begin
sign_extended = 32'hFFFF0000 + immediate;
end else begin
sign_extended = 32'h00000000 + immediate;
end
end
//shift by 2
shift_2 = sign_extended << 2;
//mux
case (ALUSrcB)
0: ALUB = register_b;
1: ALUB = 32'h00000004;
2: ALUB = sign_extended;
3: ALUB = shift_2;
endcase
end
endmodule
| 6.652348 |
module ALU (
Out,
A,
B,
ALUFun,
Sign
);
input [31:0] A, B;
input [5:0] ALUFun;
input Sign;
output reg [31:0] Out;
wire Z, V, N;
wire [31:0] Out1, Out2, Out3, Out4;
ARITH ari (
ALUFun[0],
A,
B,
Sign,
Z,
V,
N,
Out1
);
LOGIC log (
ALUFun[3:0],
A,
B,
Out2
);
SHIFT shi (
ALUFun[1:0],
A,
B,
Out3
);
CMP cmp (
ALUFun[3:1],
Z,
V,
N,
Out4
);
always @* begin
case (ALUFun[5:4])
2'b00: Out <= Out1;
2'b01: Out <= Out2;
2'b10: Out <= Out3;
2'b11: Out <= Out4;
default: Out <= 32'h00000000;
endcase
end
endmodule
| 8.102762 |
module CMP (
FUNC,
Z,
V,
N,
Out
);
input [2:0] FUNC;
input Z, V, N;
output reg [31:0] Out;
always @* begin
Out[31:0] = 32'h00000000;
case (FUNC)
3'b001: Out[0] <= Z;
3'b000: Out[0] <= ~Z;
3'b010: Out[0] <= N;
3'b110: Out[0] <= (Z || N);
3'b101: Out[0] <= N;
3'b111: Out[0] <= ~N;
default: Out <= 32'h00000000;
endcase
end
endmodule
| 9.397321 |
module ARITH (
FUNC,
A,
B,
S,
Z,
V,
N,
Out
);
input [31:0] A, B;
input FUNC;
input S;
output Z;
output reg V, N;
output reg [31:0] Out;
reg [31:0] C;
assign Z = (Out == 0);
always @* begin
if (FUNC == 0) begin
if (S == 1) begin
Out = A + B;
if (A[31] == 0 && B[31] == 0 && Out[31] == 1 || A[31] == 1 && B[31] == 1 && Out[31] == 0)
V = 1;
else V = 0;
if (A[31] == 1 && B[31] == 1) N = 1;
else if (A[31] == 0 && B[31] == 0) N = 0;
else N = Out[31];
end
if (S == 0) begin
Out = A + B;
V = 0;
N = 0;
end
end
if (FUNC == 1) begin
C = ~B + 1'b1;
if (S == 1) begin
Out = A + C;
if (A[31] == 0 && C[31] == 0 && Out[31] == 1 || A[31] == 1 && C[31] == 1 && Out[31] == 0)
V = 1;
else V <= 0;
if (A[31] == 1 && C[31] == 1) N = 1;
else if (A[31] == 0 && C[31] == 0) N = 0;
else N = Out[31];
end
if (S == 0) begin
Out = A + C;
V = 0;
if (A[31] == 1 && B[31] == 0) N = 0;
else if (A[31] == 0 && B[31] == 1) N = 1;
else N = Out[31];
end
end
end
endmodule
| 6.664095 |
module LOGIC (
FUNC,
A,
B,
Z
);
input [3:0] FUNC;
input [31:0] A, B;
output reg [31:0] Z;
always @* begin
case (FUNC)
4'b1000: Z = A & B;
4'b1110: Z = A | B;
4'b0110: Z = A ^ B;
4'b0001: Z = ~(A | B);
4'b1010: Z = A;
default: Z = 32'h00000000;
endcase
end
endmodule
| 7.902914 |
module ALUnFlag (
input [15:0] A,
B,
input [2:0] op,
input [3:0] imm,
input clk,
rst,
modify,
output [2:0] outFlag
); //Z V N
wire [2:0] ALUFlag;
ALU alu (
.A(A),
.B(B),
.op(op),
.imm(imm),
.Flag(ALUFlag)
);
FlagRegister FR (
.clk(clk),
.rst(rst),
.modify(modify),
.inFlag(ALUFlag),
.outFlag(outFlag)
);
endmodule
| 7.045403 |
module aluop_selector #(
parameter CURRENTPC = 1'b0,
parameter RD1 = 1'b1,
parameter EXT = 1'b0,
parameter RD2 = 1'b1
) (
input op_A_sel_i,
input op_B_sel_i,
input [31:0] current_pc_i,
input [31:0] rD1_i,
input [31:0] rD2_i,
input [31:0] ext_i,
output reg [31:0] alu_op_a_o,
output reg [31:0] alu_op_b_o
);
// alu_a选择
always @(*) begin
case (op_A_sel_i)
CURRENTPC: alu_op_a_o = current_pc_i;
RD1: alu_op_a_o = rD1_i;
default: alu_op_a_o = 32'h0;
endcase
end
// alu_b选择
always @(*) begin
case (op_B_sel_i)
EXT: alu_op_b_o = ext_i;
RD2: alu_op_b_o = rD2_i;
default: alu_op_b_o = 32'h0;
endcase
end
endmodule
| 7.915518 |
module ALUoutDR (
input CLK,
input [31:0] DataIn,
output reg [31:0] DataOut
);
always @(negedge CLK) DataOut <= DataIn;
endmodule
| 6.750416 |
module ALUOut_module (
clk,
ALUOut_in,
ALUOut_out
);
input clk;
input [31:0] ALUOut_in;
output [31:0] ALUOut_out;
reg [31:0] ALUOut_out;
always @(clk) ALUOut_out <= ALUOut_in;
endmodule
| 6.830488 |
module ALUOut_reg (
ALUOut_in,
ALUOut_reg,
reset,
clk
);
input [31:0] ALUOut_in;
input reset, clk;
output reg [31:0] ALUOut_reg;
always @(posedge clk) begin
if (reset) begin
ALUOut_reg <= 32'd0;
end else begin
ALUOut_reg <= ALUOut_in;
end
end
endmodule
| 7.157747 |
module ALUPC ( //Summation of PC and 1
clock,
inPC,
out
);
input clock;
input [7:0] inPC;
output reg [7:0] out;
always @(posedge clock) out = inPC + 1;
endmodule
| 6.502121 |
module ALUPC_tb;
reg [7:0] currAddr;
wire [7:0] nextAddr;
ALUPC pcALU (
currAddr,
nextAddr
);
initial begin
//$dumpfile ("testbench/acOut_tb.vcd");
//$dumpvars(0, acOut_tb);
$monitor("New Address = %d, Current Address = %d", nextAddr, currAddr);
currAddr = 8'b00000001;
#20;
currAddr = 8'b00000100;
#20;
currAddr = 8'b00100001;
#20;
currAddr = 8'b00001111;
#20;
$monitor("test completed");
end
endmodule
| 6.53211 |
module ALUposk (
CLK,
RST,
frac,
exp,
nguyen,
le,
lt
);
input CLK, RST;
input [22:0] frac;
input [8:0] exp;
output [19:0] le;
output [4:0] nguyen;
output [8:0] lt;
wire [31:0] number1, temp_result, number2;
wire [27:0] frac1;
wire [8:0] _2k, _3k, exp_temp, exp_out, temp_lt;
wire [7:0] exp1;
wire [1:0] rst_1;
wire ena1, CLK2, ena2, CLK3;
reg [1:0] count_rst;
reg RST2, ena3;
assign number1 = {1'b0, 8'b01111111, frac};
assign _2k = {exp[7:0], 1'b0};
adder_9bit tinh3k (
.in1(_2k),
.in2(exp),
.S(_3k),
.Cout()
);
power tinhmu3k (
.A(32'h3E00E9F9),
.B({15'b0, _3k}),
.CLK(CLK),
.RST(RST),
.result(temp_result),
.overflow(),
.underflow(),
.enable(ena1)
); //ok
assign CLK2 = CLK & ena1;
mult mult1 (
.A(number1),
.B(temp_result),
.CLK(CLK2),
.RST(RST),
.result(number2),
.overflow(),
.underflow(),
.enable(ena2)
);
assign CLK3 = CLK2 & ena2;
assign exp1 = number2[30:23];
assign frac1 = {5'b00001, number2[22:0]};
adder_9bit tinh_exp (
.in1({1'b0, exp1}),
.in2(-9'd127),
.S(exp_temp),
.Cout()
);
compliment2_9bit dao_exp (
.in (exp_temp),
.out(exp_out)
);
//////// RESET for neg
adder_2bit RST_SECOND (
.in1(count_rst),
.in2(-2'd1),
.S(rst_1),
.Cout()
);
always @(posedge CLK3 or negedge RST) begin
if (~RST) begin
count_rst <= 2'b10;
RST2 <= 1'b1;
end else begin
count_rst <= ena3 ? (rst_1) : (count_rst);
RST2 <= |rst_1;
end
end
always @(*) begin
ena3 = ~(&(count_rst));
end
///////////////////////////////////////
ALUnegk ALU1 (
.CLK(CLK3),
.RST(RST2),
.frac(frac1),
.exp(exp_out),
.nguyen(nguyen),
.le(le),
.lt(temp_lt)
);
adder_9bit tinhlt (
.in1(temp_lt),
.in2(_3k),
.S(lt),
.Cout()
);
endmodule
| 6.561404 |
module RegisterFile (
rd1,
rd2,
rr1,
rr2,
wr,
wd,
we,
clk
);
output reg [31:0] rd1, rd2;
input [4:0] rr1, rr2, wr;
input we, clk;
input [31:0] wd;
reg [31:0] rf[7:0];
always @(posedge clk) begin
if (we) begin
rf[wr] <= wd;
end
rd1 = rf[rr1];
rd2 = rf[rr2];
end
endmodule
| 8.108491 |
module alureg(input wire clk, reset, wr, opmux2, cin, input wire[3:0]op, input wire[2:0] rd_addr_a, rd_addr_b, wr_addr,op1, input wire[1:0]op2, input wire[15:0] d, output wire[15:0] o, ouput wire coutf);
wire[15:0] d_out_a;
wire[15:0] d_out_b;
reg_file f1(clk, reset, wr, opmux2, rd_addr_a, rd_addr_b, wr_addr, d, d_out_a, d_out_b);
alu_16 f2(op,op1, op, d_out_a, d_out_b, cin, opmux2, o, coutf);
endmodule
| 7.406026 |
module alu_rf_32 (
input wire clock,
// Register File Knobs
input wire write_enabled,
input wire [4:0] read_addr_s,
input wire [4:0] read_addr_t,
input wire [4:0] write_addr,
// ALU Knob
input wire [3:0] control,
// ALU Outputs
output wire cout,
output wire zero,
output wire err_overflow,
output wire err_invalid_control
);
// The nets interconnecting our alu and rf
wire [31:0] regfile_to_alu_s;
wire [31:0] regfile_to_alu_t;
wire [31:0] alu_result_write_data; // It is a register for laziness
// Connect our ALU to our Register File (rf)
alu_32 alu (
.clock (clock),
.input_a (regfile_to_alu_s),
.input_b (regfile_to_alu_t),
.result (alu_result_write_data),
.control (control),
.cout (cout),
.zero (zero),
.err_overflow (err_overflow),
.err_invalid_control(err_invalid_control)
);
rf_32 regfile (
.clock (clock),
.write_data (alu_result_write_data),
.outA (regfile_to_alu_s),
.outB (regfile_to_alu_t),
.read_addr_s (read_addr_s),
.read_addr_t (read_addr_t),
.write_addr (write_addr),
.write_enabled(write_enabled)
);
endmodule
| 6.93197 |
module aluReg (
clk,
alu_res,
aluReg_out,
overflow,
overflowReg
);
input clk;
input [31:0] alu_res;
input overflow;
output reg [31:0] aluReg_out;
output reg overflowReg;
always @(posedge clk) begin
aluReg_out <= alu_res;
overflowReg <= overflow;
end
endmodule
| 6.947866 |
module nxtPosCal (
input wire enWrtO,
input wire [`TagBus] WrtTagO,
input wire [`DataBus] WrtDataO,
input wire enWrtT,
input wire [`TagBus] WrtTagT,
input wire [`DataBus] WrtDataT,
input wire [`DataBus] dataNow,
input wire [ `TagBus] tagNow,
output wire [`DataBus] dataNxtPos,
output wire [ `TagBus] tagNxtPos
);
assign dataNxtPos = (enWrtO & (tagNow == WrtTagO)) ? WrtDataO :
(enWrtT & (tagNow == WrtTagT)) ? WrtDataT :
dataNow;
assign tagNxtPos = (enWrtO & (tagNow == WrtTagO)) ? `tagFree :
(enWrtT & (tagNow == WrtTagT)) ? `tagFree :
tagNow;
endmodule
| 8.272042 |
module RsLine (
input clk,
input rst,
input rdy,
//
input wire enWrtO,
input wire [ `TagBus] WrtTagO,
input wire [ `DataBus] WrtDataO,
input wire enWrtT,
input wire [ `TagBus] WrtTagT,
input wire [ `DataBus] WrtDataT,
//
input wire allocEn,
input wire [ `DataBus] allocOperandO,
input wire [ `DataBus] allocOperandT,
input wire [ `TagBus] allocTagO,
input wire [ `TagBus] allocTagT,
input wire [ `TagBus] allocTagW,
input wire [ `OpBus] allocOp,
input wire [ `InstAddrBus] allocImm,
input wire [`BranchTagBus] allocBranchTag,
//
input wire empty,
output wire ready,
output wire [ `DataBus] issueOperandO,
output wire [ `DataBus] issueOperandT,
output reg [ `OpBus] issueOp,
output reg [ `TagBus] issueTagW,
output reg [ `DataBus] issueImm,
output wire [`BranchTagBus] issueBranchTag,
//the imm is pc in alu, is imm in ls; so bucket branchRS for it contains both
input wire bFreeEn,
input wire [ 1:0] bFreeNum,
input wire misTaken,
output wire nxtPosEmpty
);
reg [`TagBus] rsTagO, rsTagT;
reg [`DataBus] rsDataO, rsDataT;
reg [`BranchTagBus] BranchTag;
wire [`TagBus] nxtPosTagO, nxtPosTagT;
wire [`DataBus] nxtPosDataO, nxtPosDataT;
wire discard;
assign discard = ~empty & misTaken & BranchTag[bFreeNum];
assign nxtPosEmpty = (~allocEn & empty) | discard;
assign ready = ~empty & (nxtPosTagO == `tagFree) & (nxtPosTagT == `tagFree) & ~discard;
assign issueOperandO = (nxtPosTagO == `tagFree) ? nxtPosDataO : rsDataO;
assign issueOperandT = (nxtPosTagT == `tagFree) ? nxtPosDataT : rsDataT;
assign issueBranchTag = (bFreeEn & BranchTag[bFreeNum]) ? (BranchTag ^ (1 << bFreeNum)) : BranchTag;
nxtPosCal nxtPosCalO (
.enWrtO(enWrtO),
.WrtTagO(WrtTagO),
.WrtDataO(WrtDataO),
.enWrtT(enWrtT),
.WrtTagT(WrtTagT),
.WrtDataT(WrtDataT),
.dataNow(rsDataO),
.tagNow(rsTagO),
.dataNxtPos(nxtPosDataO),
.tagNxtPos(nxtPosTagO)
);
nxtPosCal nxtPosCalT (
.enWrtO(enWrtO),
.WrtTagO(WrtTagO),
.WrtDataO(WrtDataO),
.enWrtT(enWrtT),
.WrtTagT(WrtTagT),
.WrtDataT(WrtDataT),
.dataNow(rsDataT),
.tagNow(rsTagT),
.dataNxtPos(nxtPosDataT),
.tagNxtPos(nxtPosTagT)
);
always @(posedge clk) begin
if (rst | discard) begin
rsTagO <= `tagFree;
rsTagT <= `tagFree;
rsDataO <= `dataFree;
rsDataT <= `dataFree;
issueTagW <= `tagFree;
issueImm <= `dataFree;
issueOp <= `NOP;
BranchTag <= 0;
end else if (rdy) begin
if (allocEn) begin
rsTagO <= allocTagO;
rsTagT <= allocTagT;
rsDataO <= allocOperandO;
rsDataT <= allocOperandT;
issueTagW <= allocTagW;
issueImm <= allocImm;
issueOp <= allocOp;
BranchTag <= allocBranchTag;
end else begin
rsTagO <= nxtPosTagO;
rsTagT <= nxtPosTagT;
rsDataO <= nxtPosDataO;
rsDataT <= nxtPosDataT;
BranchTag <= issueBranchTag;
end
end
end
endmodule
| 7.818872 |
module ALUSelA (
code,
alu_sel_a,
insn
);
input [9:0] code;
input [31:0] insn;
output alu_sel_a;
wire W1;
// Assign com expressão derivada da função
assign W1 = (~code[9] & ~code[8] & ~code[7] & ~code[6] & ~code[5] & ~code[4] & ~code[3] & ~code[2] & ~code[1] & code[0]) | (~code[9] & ~code[8] & ~code[7] & ~code[6] & ~code[5] & ~code[4] & code[3] & ~code[2] & ~code[1] & ~code[0]) ;
/* Se a função acima de devolveu 1, apenas passar o sinal
Caso contrário, devolver 0 para todos os codes != 1000000000 e 1 somente quando o bit 20 de insn for 1 (diferenciador entre ecall e ebreak) */
assign alu_sel_a = W1 | (code[9] & insn[20]);
endmodule
| 6.944147 |
module ALUSelector (
input ALUSrcB,
input [31:0] out2,
input [31:0] extendOut,
output wire [31:0] ALUSelectorOut
);
// ALUSrcBΪ0ʱʾALUB˿ڽԼĴdata2Ϊ1ʱʾsignzeroչ
assign ALUSelectorOut = ALUSrcB ? extendOut : out2;
endmodule
| 6.652188 |
module ALUSimple (
input clock,
input reset,
input [ 3:0] io_operation,
input [31:0] io_inputx,
input [31:0] io_inputy,
output [31:0] io_result
);
wire [31:0] _T_1 = io_inputx & io_inputy;
wire [31:0] _T_3 = io_inputx | io_inputy;
wire [31:0] _T_6 = io_inputx + io_inputy;
wire [31:0] _T_9 = io_inputx - io_inputy;
wire [31:0] _T_11 = io_inputx;
wire [31:0] _T_14 = $signed(io_inputx) >>> io_inputy[4:0];
wire [31:0] _T_18 = io_inputx ^ io_inputy;
wire [31:0] _T_21 = io_inputx >> io_inputy[4:0];
wire [31:0] _T_24 = io_inputy;
wire [62:0] _GEN_14 = {{31'd0}, io_inputx};
wire [62:0] _T_28 = _GEN_14 << io_inputy[4:0];
wire [31:0] _T_31 = ~_T_3;
wire _GEN_1 = io_operation == 4'hc ? io_inputx >= io_inputy : io_operation == 4'hd & io_inputx == io_inputy; // @[]
wire _GEN_2 = io_operation == 4'hb ? $signed(io_inputx) >= $signed(io_inputy) : _GEN_1; // @[]
wire [31:0] _GEN_3 = io_operation == 4'ha ? _T_31 : {{31'd0}, _GEN_2}; // @[]
wire [62:0] _GEN_4 = io_operation == 4'h8 ? _T_28 : {{31'd0}, _GEN_3}; // @[]
wire [62:0] _GEN_5 = io_operation == 4'h9 ? {{62'd0}, $signed(
_T_11
) < $signed(
_T_24
)} : _GEN_4; // @[]
wire [62:0] _GEN_6 = io_operation == 4'h2 ? {{31'd0}, _T_21} : _GEN_5; // @[]
wire [62:0] _GEN_7 = io_operation == 4'h0 ? {{31'd0}, _T_18} : _GEN_6; // @[]
wire [62:0] _GEN_8 = io_operation == 4'h1 ? {{62'd0}, io_inputx < io_inputy} : _GEN_7; // @[]
wire [62:0] _GEN_9 = io_operation == 4'h3 ? {{31'd0}, _T_14} : _GEN_8; // @[]
wire [62:0] _GEN_10 = io_operation == 4'h4 ? {{31'd0}, _T_9} : _GEN_9; // @[]
wire [62:0] _GEN_11 = io_operation == 4'h7 ? {{31'd0}, _T_6} : _GEN_10; // @[]
wire [62:0] _GEN_12 = io_operation == 4'h5 ? {{31'd0}, _T_3} : _GEN_11; // @[]
wire [62:0] _GEN_13 = io_operation == 4'h6 ? {{31'd0}, _T_1} : _GEN_12; // @[]
assign io_result = _GEN_13[31:0];
endmodule
| 7.00578 |
module ALUSrc (
PR2,
ALUSrc_Out
);
input [499:0] PR2;
wire [63:0] Data2_3;
wire [63:0] SEout3;
reg [63:0] In0;
reg [63:0] In1;
wire ALUSrc3;
output reg [63:0] ALUSrc_Out;
assign ALUSrc3 = PR2[96];
assign SEout3 = PR2[295:232];
assign Data2_3 = PR2[231:168];
always @* begin
case (ALUSrc3)
0: begin
assign In0 = Data2_3;
ALUSrc_Out <= In0;
end
1: begin
assign In1 = SEout3;
ALUSrc_Out <= In1;
end
endcase
end
endmodule
| 7.574005 |
module contains 1 control signal, ALUSrc, if it is deasserted, it will
* take data from register file as the operand; if it is asserted, it will
* take data from immediate number as the operand.
* code | meaning
* 00 | takes operand from register
* 01 | takes operand from immediate number
* 10 | takes operand from constant 16
*/
module alusrcmux( input wire [31:0] regsrc,
input wire [31:0] immsrc,
input wire [1:0] alusrc,
output reg [31:0] operand);
always @(*) begin
case (alusrc)
2'b00: operand = regsrc;
2'b01: operand = immsrc;
2'b10: operand = 32'd16;
default: operand = 32'bx;
endcase
end
endmodule
| 6.799318 |
module alusrc_mux (
rd_data2,
sd_imm,
addi_imm,
ALUSrc,
sd,
alu_in2
);
input [63:0] rd_data2, sd_imm, addi_imm;
input ALUSrc, sd;
output [63:0] alu_in2;
assign alu_in2 = ALUSrc ? ((sd) ? sd_imm : addi_imm) : rd_data2;
endmodule
| 7.460633 |
module ALUSrc_selector #(
parameter W = 32
) (
input [W-1:0] i_instruction,
input [W-1:0] i_rs,
input [W-1:0] i_rt,
input [W-1:0] i_forwarded_data,
input i_rs_forward_signal,
input i_rt_forward_signal,
output reg [W-1:0] o_alu_oprand1,
output reg [W-1:0] o_alu_oprand2
);
wire [ `op] opcode = `get_op(i_instruction);
wire [ `fun] fun = `get_fun(i_instruction);
wire [ `sa] sa = `get_sa(i_instruction);
wire [ `imm] imm = `get_imm(i_instruction);
wire [W-1:0] imm_signext;
sign_extender #(
.from(16),
.to (32)
) ALUSrc_sign_extender (
.inst(imm),
.data(imm_signext)
);
wire [W-1:0] imm_zeroext = {{16{0}}, imm};
//op1
always @(*) begin
case (opcode)
`OP_R: begin
case (fun)
`FUN_SLL, `FUN_SRL, `FUN_SRA: o_alu_oprand1 = {{27{1'b0}}, sa};
default: o_alu_oprand1 = i_rs_forward_signal ? i_forwarded_data : i_rs;
endcase
end
default: o_alu_oprand1 = i_rs_forward_signal ? i_forwarded_data : i_rs;
endcase
end
//op2
always @(*) begin
case (opcode)
`OP_R, `OP_BEQ, `OP_BNE: o_alu_oprand2 = i_rt_forward_signal ? i_forwarded_data : i_rt;
`OP_REGIMM, `OP_BGTZ, `OP_BLEZ: o_alu_oprand2 = 0;
`OP_ADDI, `OP_ADDIU, `OP_SLTI, `OP_SLTIU, `OP_LB, `OP_LBU, `OP_LH, `OP_LHU, `OP_LW, `OP_SB, `OP_SH, `OP_SW:
o_alu_oprand2 = imm_signext;
`OP_ANDI, `OP_ORI, `OP_XORI, `OP_LUI: o_alu_oprand2 = imm_zeroext;
default: o_alu_oprand2 = {32{1'bx}};
endcase
end
endmodule
| 8.650255 |
module mux2to1 (
input [31:0] A,
B,
input sel,
output [31:0] out
);
assign out = (sel == 0) ? A : B;
endmodule
| 7.107199 |
module ALU_main (
input [31:0] RF_A,
input [31:0] RF_B,
input [31:0] Immed,
input ALU_Bin_sel,
input [3:0] ALU_func,
output [31:0] ALU_out,
output Zero
);
wire [31:0] mux_out;
mux2to1 mux (
.A (RF_B),
.B (Immed),
.sel(ALU_Bin_sel),
.out(mux_out)
);
ALU alu (
.out(ALU_out),
.Op(ALU_func),
.A(RF_A),
.B(mux_out),
.Zero(Zero)
);
endmodule
| 8.028381 |
module: alu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALUtb;
// Inputs
reg [31:0] A;
reg [31:0] B;
reg [2:0] ALUOp;
// Outputs
wire [31:0] C;
// Instantiate the Unit Under Test (UUT)
alu uut (
.A(A),
.B(B),
.ALUOp(ALUOp),
.C(C)
);
initial begin
// Initialize Inputs
A = 32'hfffffffe;
B = 2;
ALUOp = 3'b100;
// Wait 10 ns for global reset to finish
#10;
// Add stimulus here
end
endmodule
| 7.023594 |
module ALUTestVectorTestbench ();
parameter Halfcycle = 5; //half period is 5ns
localparam Cycle = 2 * Halfcycle;
reg Clock;
// Clock Signal generation:
initial Clock = 0;
always #(Halfcycle) Clock = ~Clock;
// Wires to test the ALU
// These are read from the input vector
reg [6:0] opcode;
reg [2:0] funct;
reg add_rshift_type;
reg [31:0] A, B;
reg [31:0] REFout;
wire [31:0] DUTout;
wire [ 3:0] ALUop;
// Task for checking output
task checkOutput;
input [6:0] opcode;
input [2:0] funct;
input add_rshift_type;
if (REFout !== DUTout) begin
$display("FAIL: Incorrect result for opcode %b, funct: %b, add_rshift_type: %b", opcode,
funct, add_rshift_type);
$display("\tA: 0x%h, B: 0x%h, DUTout: 0x%h, REFout: 0x%h", A, B, DUTout, REFout);
$finish();
end else begin
$display("PASS: opcode %b, funct %b, add_rshift_type %b", opcode, funct, add_rshift_type);
$display("\tA: 0x%h, B: 0x%h, DUTout: 0x%h, REFout: 0x%h", A, B, DUTout, REFout);
end
endtask
// This is where the modules being tested are instantiated.
ALUdec DUT1 (
.opcode(opcode),
.funct(funct),
.add_rshift_type(add_rshift_type),
.ALUop(ALUop)
);
ALU DUT2 (
.A(A),
.B(B),
.ALUop(ALUop),
.Out(DUTout)
);
/////////////////////////////////////////////////////////////////
// Change this number to reflect the number of testcases in your
// testvector input file, which you can find with the command:
// % wc -l ../sim/tests/testvectors.input
// //////////////////////////////////////////////////////////////
localparam testcases = 314;
reg [106:0] testvector[0:testcases-1]; // Each testcase has 107 bits:
// 64 for A and B, 32 for REFout, 6 for
// opcode, 6 for funct
integer i; // integer used for looping in non-generate statement
initial begin
$readmemb("testvectors.input", testvector);
for (i = 0; i < testcases; i = i + 1) begin
opcode = testvector[i][106:100];
funct = testvector[i][99:97];
add_rshift_type = testvector[i][96];
A = testvector[i][95:64];
B = testvector[i][63:32];
REFout = testvector[i][31:0];
#1;
checkOutput(opcode, funct, add_rshift_type);
end
$display("\n\nALL TESTS PASSED!");
$finish();
end
endmodule
| 6.646929 |
module: alu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alutest;
// Inputs
reg [3:0] A;
reg [3:0] B;
reg [1:0] Opcode;
// Outputs
wire [3:0] C;
wire [4:0] Flags;
integer i;
// Instantiate the Unit Under Test (UUT)
alu uut (
.A(A),
.B(B),
.C(C),
.Opcode(Opcode),
.Flags(Flags)
);
initial begin
// $monitor("A: %0d, B: %0d, C: %0d, Flags[1:0]:
%b, time:%0d", A, B, C, Flags[1:0], $time );
//Instead of the $display stmt in the loop, you could use just this
//monitor statement which is executed everytime there is an event on any
//signal in the argument list.
// Initialize Inputs
A = 0;
B = 0;
Opcode = 2'b11;
// Wait 100 ns for global reset to finish
/*****
// One vector-by-vector case simulation
#10;
Opcode = 2'b11;
A = 4'b0010; B = 4'b0011;
#10
A = 4'b1111; B = 4'b 1110;
//$display("A: %b, B: %b, C:%b, Flags[1:0]: %b, time:%d", A, B, C, Flags[1:0], $time);
****/
//Random simulation
for( i = 0; i< 10; i = i+ 1)
begin
#10
A = $random % 16;
B = $random %16;
$display("A: %0d, B: %0d, C: %0d, Flags[1:0]: %b, time:%0d", A, B, C, Flags[1:0], $time );
end
$finish(2);
// Add stimulus here
end
endmodule
| 7.023594 |
module ALUtoDM_addr (
ALUout,
addr
);
input [31:0] ALUout;
output [13:0] addr;
assign addr = {ALUout[13:0]};
endmodule
| 7.177681 |
module ALUtoMEM_REG (
input clk,
input rstn,
input [31:0] i_ALUResult_32,
output [31:0] o_ALUResult_32,
input i_Load_1,
input i_Store_1,
input i_LoadUnsigned_1,
input [ 1:0] i_LoadStoreWidth_2,
input [31:0] i_StoreData_32,
input [ 4:0] i_GRFWriteAddr_5,
input i_GRFWen_1,
output o_Load_1,
output o_Store_1,
output o_LoadUnsigned_1,
output[ 1:0] o_LoadStoreWidth_2,
output[31:0] o_StoreData_32,
output[ 4:0] o_GRFWriteAddr_5,
output o_GRFWen_1
);
reg [31:0] ALUResult;
reg Load;
reg Store;
reg LoadUnsigned;
reg [ 1:0] LoadStoreWidth;
reg [31:0] StoreData;
reg [ 4:0] GRFWriteAddr;
reg GRFWen;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
ALUResult <= 32'b0;
Load <= 1'b0;
Store <= 1'b0;
LoadUnsigned <= 1'b0;
LoadStoreWidth <= 2'b0;
StoreData <= 32'b0;
GRFWriteAddr <= 5'b0;
GRFWen <= 1'b0;
end else begin
ALUResult <= i_ALUResult_32;
Load <= i_Load_1;
Store <= i_Store_1;
LoadUnsigned <= i_LoadUnsigned_1;
LoadStoreWidth <= i_LoadStoreWidth_2;
StoreData <= i_StoreData_32;
GRFWriteAddr <= i_GRFWriteAddr_5;
GRFWen <= i_GRFWen_1;
end
end
assign o_ALUResult_32 = ALUResult;
assign o_Load_1 = Load;
assign o_Store_1 = Store;
assign o_LoadUnsigned_1 = LoadUnsigned;
assign o_LoadStoreWidth_2 = LoadStoreWidth;
assign o_StoreData_32 = StoreData;
assign o_GRFWriteAddr_5 = GRFWriteAddr;
assign o_GRFWen_1 = GRFWen;
endmodule
| 7.832463 |
module alut_mem (
// Inputs
pclk,
mem_addr_add,
mem_write_add,
mem_write_data_add,
mem_addr_age,
mem_write_age,
mem_write_data_age,
mem_read_data_add,
mem_read_data_age
);
parameter DW = 83; // width of data busses
parameter DD = 256; // depth of RAM
input pclk; // APB clock
input [7:0] mem_addr_add; // hash address for R/W to memory
input mem_write_add; // R/W flag (write = high)
input [DW-1:0] mem_write_data_add; // write data for memory
input [7:0] mem_addr_age; // hash address for R/W to memory
input mem_write_age; // R/W flag (write = high)
input [DW-1:0] mem_write_data_age; // write data for memory
output [DW-1:0] mem_read_data_add; // read data from mem
output [DW-1:0] mem_read_data_age; // read data from mem
reg [DW-1:0] mem_core_array[DD-1:0]; // memory array
reg [DW-1:0] mem_read_data_add; // read data from mem
reg [DW-1:0] mem_read_data_age; // read data from mem
// -----------------------------------------------------------------------------
// read and write control for address checker access
// -----------------------------------------------------------------------------
always @(posedge pclk) begin
if (~mem_write_add) // read array
mem_read_data_add <= mem_core_array[mem_addr_add];
else mem_core_array[mem_addr_add] <= mem_write_data_add;
end
// -----------------------------------------------------------------------------
// read and write control for age checker access
// -----------------------------------------------------------------------------
always @(posedge pclk) begin
if (~mem_write_age) // read array
mem_read_data_age <= mem_core_array[mem_addr_age];
else mem_core_array[mem_addr_age] <= mem_write_data_age;
end
endmodule
| 6.936293 |
module alut_veneer (
// Inputs
pclk,
n_p_reset,
psel,
penable,
pwrite,
paddr,
pwdata,
// Outputs
prdata
);
// APB Inputs
input pclk; // APB clock
input n_p_reset; // Reset
input psel; // Module select signal
input penable; // Enable signal
input pwrite; // Write when HIGH and read when LOW
input [6:0] paddr; // Address bus for read write
input [31:0] pwdata; // APB write bus
output [31:0] prdata; // APB read bus
//-----------------------------------------------------------------------
//##############################################################################
// if the ALUT is NOT black boxed
//##############################################################################
`ifndef FV_KIT_BLACK_BOX_LUT
alut i_alut (
//inputs
.n_p_reset(n_p_reset),
.pclk(pclk),
.psel(psel),
.penable(penable),
.pwrite(pwrite),
.paddr(paddr[6:0]),
.pwdata(pwdata),
//outputs
.prdata(prdata)
);
`else
//##############################################################################
// if the <module> is black boxed
//##############################################################################
// APB Inputs
wire pclk; // APB clock
wire n_p_reset; // Reset
wire psel; // Module select signal
wire penable; // Enable signal
wire pwrite; // Write when HIGH and read when LOW
wire [ 6:0] paddr; // Address bus for read write
wire [31:0] pwdata; // APB write bus
reg [31:0] prdata; // APB read bus
`endif
endmodule
| 7.24936 |
module ALUusr (
input wire [15:0] x, // input x (16 bit)
input wire [15:0] y, // input y (16 bit)
input wire zx, // zero the x input?
input wire nx, // negate the x input?
input wire zy, // zero the y input?
input wire ny, // negate the y input?
input wire f, // compute out = x + y (if 1) or x & y (if 0)
input wire no, // negate the out output?
output wire [15:0] out, // 16-bit output
output wire zr, // 1 if (out == 0), 0 otherwise
output wire ng // 1 if (out < 0), 0 otherwise
);
// your implementation comes here:
// Mux16(a=x ,b=false ,sel=zx ,out=x1 );
// Not16(in=x1, out=notx1);
// Mux16(a=x1,b=notx1,sel=nx ,out=x2 );
// Mux16(a=y ,b=false ,sel=zy ,out=y1 );
// Not16(in=y1,out=noty1);
// Mux16(a=y1,b=noty1,sel=ny ,out=y2 );
// And16(a=x2 ,b=y2 ,out=andxy );
// Add16(a=x2 ,b=y2 ,out=addxy );
// Mux16(a=andxy,b=addxy,sel=f,out=xy);
// Not16(in=xy,out=notxy);
// Mux16(a=xy,b=notxy,sel=no,out[15]=tmp,out[0..7]=out07,out[8..15]=out815,out=out);
// And(a=tmp,b=true,out=ng);
// Or8Way(in=out07,out=tmp1);
// Or8Way(in=out815,out=tmp2);
// Or(a=tmp1,b=tmp2,out=tmp3);
// Not(in=tmp3,out=zr);
wire [15:0] x1;
wire [15:0] x2;
wire [15:0] notx1;
Mux16 MUX16x (
.a (x),
.b (16'b0000000000000000),
.sel(zx),
.out(x1)
);
Not16 NOT16x (
.in (x1),
.out(notx1)
);
Mux16 MUX16x1 (
.a (x1),
.b (notx1),
.sel(nx),
.out(x2)
);
wire [15:0] y1;
wire [15:0] y2;
wire [15:0] noty1;
Mux16 MUX16y (
.a (y),
.b (16'b0000000000000000),
.sel(zy),
.out(y1)
);
Not16 NOT16y (
.in (y1),
.out(noty1)
);
Mux16 MUX16y1 (
.a (y1),
.b (noty1),
.sel(ny),
.out(y2)
);
wire [15:0] andxy;
wire [15:0] addxy;
wire [15:0] xy;
And16 AND16xy (
.a (x2),
.b (y2),
.out(andxy)
);
Add16 ADD16xy (
.a (x2),
.b (y2),
.out(addxy)
);
Mux16 MUX16andadd (
.a (andxy),
.b (addxy),
.sel(f),
.out(xy)
);
wire [15:0] notxy;
Not16 NOT16xy (
.in (xy),
.out(notxy)
);
Mux16 MUX16xy (
.a (xy),
.b (notxy),
.sel(no),
.out(out)
);
wire tmp = out[15];
wire [7:0] out07 = out[7:0];
wire [7:0] out815 = out[15:8];
wire tmp1;
wire tmp2;
wire tmp3;
And AND (
.a (tmp),
.b (1'b1),
.out(ng)
);
Or8Way OR8WAY07 (
.in (out07),
.out(tmp1)
);
Or8Way OR8WAY815 (
.in (out815),
.out(tmp2)
);
Or OR (
.a (tmp1),
.b (tmp2),
.out(tmp3)
);
Not NOT (
.in (tmp3),
.out(zr)
);
endmodule
| 7.655842 |
module ALUV (
a,
b,
sel,
c
);
input [15:0] a, b;
input [3:0] sel;
output [15:0] c;
reg [15:0] c;
parameter alupass = 0,
andOp = 1,
orOp = 2,
notOp = 3,
xorOp = 4,
plus = 5,
alusub = 6,
inc = 7,
dec = 8,
zero = 9;
always @(a or b or sel) begin
case (sel)
alupass: c <= a; //总线数据直通ALU
andOp: c <= a & b; //逻辑与操作
orOp: c <= a | b; //逻辑或操作
notOp: c <= a ^ b; //逻辑异或操作
xorOp: c <= ~a; //取反操作
plus: c <= a + b; //算数加操作
alusub: c <= a - b; //算数减操作
inc: c <= a + 1; //加1操作
dec: c <= a - 1; //减1操作
zero: c <= 0; //输出清0
default: c <= 0;
endcase
end
endmodule
| 7.814237 |
module alu (
a,
b,
s,
y
);
input [3:0] a;
input [3:0] b;
input [2:0] s;
output [7:0] y;
reg [7:0] y;
always @(a, b, s) begin
case (s)
3'b000: y = a + b;
3'b001: y = a - b;
3'b010: y = a & b;
3'b011: y = a | b;
3'b100: y = 4'b1111 ^ a;
3'b101: y = (4'b1111 ^ a) + 1'b1;
3'b110: y = a * b;
3'b111: begin
y = a;
y = y >> 1'b1;
end
endcase
end
endmodule
| 6.634214 |
module: ALUwithControl
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALUwithControlTester;
// Inputs
reg [1:0] ALUOp;
reg [10:0] OpcodeField;
reg ALUoperation;
// Instantiate the Unit Under Test (UUT)
ALUwithControl uut (
.ALUOp(ALUOp),
.OpcodeField(OpcodeField),
.ALUoperation(ALUoperation)
);
initial begin
// Initialize Inputs
ALUOp = 0;
OpcodeField = 0;
ALUoperation = 0;
// Wait 100 ns for global reset to finish
#100;
// Testing AND OpcodeField
A = 64'h5555555555555555;
B = 64'haaaaaaaaaaaaaaaa;
ALUOp = 2'b10;
OpcodeField = 11'b10_10001010000;
#100;
// Testing OR OpcodeField
OpcodeField = 11'b10_10101010000;
#100;
// Testing ADD OpcodeField
OpcodeField = 11'b10_10001011000;
#100
// Testing Sub OpcodeField
OpcodeField = 11'b10_11001011000;
#100
// Testing Pass B OpcodeField
OpcodeField = 11'b10_11111000010;
#100
// Testing NOR OpcodeField
OpcodeField = 11'b10_11101010000;
end
endmodule
| 6.625934 |
module alux64 (
input [63:0] a,
input [63:0] b,
input [3:0] aluop,
output reg Zero,
output reg [63:0] aluout
);
always @(*) begin
case (aluop)
4'b0000: aluout = a & b;
4'b0001: aluout = a | b;
4'b0010: aluout = a + b;
4'b0110: aluout = a - b;
4'b1100: aluout = ~(a | b);
endcase
if (aluout == 64'd0) assign Zero = 1'b1;
else assign Zero = 1'b0;
end
endmodule
| 6.645124 |
module alu_11 (
input [5:0] alufn,
input [15:0] a,
input [15:0] b,
output reg [15:0] out,
output reg z,
output reg v,
output reg n
);
wire [16-1:0] M_adder__out;
wire [ 1-1:0] M_adder__z;
wire [ 1-1:0] M_adder__v;
wire [ 1-1:0] M_adder__n;
reg [ 6-1:0] M_adder__alufn;
reg [16-1:0] M_adder__a;
reg [16-1:0] M_adder__b;
adder_14 adder_ (
.alufn(M_adder__alufn),
.a(M_adder__a),
.b(M_adder__b),
.out(M_adder__out),
.z(M_adder__z),
.v(M_adder__v),
.n(M_adder__n)
);
wire [16-1:0] M_boolean__s;
reg [16-1:0] M_boolean__a;
reg [16-1:0] M_boolean__b;
reg [ 6-1:0] M_boolean__alufn;
boolean_15 boolean_ (
.a(M_boolean__a),
.b(M_boolean__b),
.alufn(M_boolean__alufn),
.s(M_boolean__s)
);
wire [16-1:0] M_shifter__s;
reg [ 6-1:0] M_shifter__alufn;
reg [16-1:0] M_shifter__a;
reg [16-1:0] M_shifter__b;
shifter_16 shifter_ (
.alufn(M_shifter__alufn),
.a(M_shifter__a),
.b(M_shifter__b),
.s(M_shifter__s)
);
wire [16-1:0] M_compare__s;
reg [ 1-1:0] M_compare__z;
reg [ 1-1:0] M_compare__v;
reg [ 1-1:0] M_compare__n;
reg [ 6-1:0] M_compare__alufn;
compare_17 compare_ (
.z(M_compare__z),
.v(M_compare__v),
.n(M_compare__n),
.alufn(M_compare__alufn),
.s(M_compare__s)
);
reg xz;
reg xv;
reg xn;
always @* begin
M_adder__alufn = alufn;
M_adder__a = a;
M_adder__b = b;
xz = M_adder__z;
xv = M_adder__v;
xn = M_adder__n;
z = xz;
v = xv;
n = xn;
M_compare__alufn = alufn;
M_compare__z = xz;
M_compare__v = xv;
M_compare__n = xn;
M_boolean__alufn = alufn;
M_boolean__a = a;
M_boolean__b = b;
M_shifter__alufn = alufn;
M_shifter__a = a;
M_shifter__b = b;
case (alufn[4+1-:2])
2'h0: begin
out = M_adder__out;
end
2'h1: begin
out = M_boolean__s;
end
2'h2: begin
out = M_shifter__s;
end
2'h3: begin
out = M_compare__s;
end
default: begin
out = 16'h0000;
end
endcase
end
endmodule
| 6.804463 |
module alu_13 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn_signal,
output reg [15:0] alu,
output reg z,
output reg v,
output reg n
);
wire [16-1:0] M_adder1_out;
wire [ 1-1:0] M_adder1_z;
wire [ 1-1:0] M_adder1_v;
wire [ 1-1:0] M_adder1_n;
reg [16-1:0] M_adder1_a;
reg [16-1:0] M_adder1_b;
reg [ 6-1:0] M_adder1_alufn_signal;
adder_17 adder1 (
.a(M_adder1_a),
.b(M_adder1_b),
.alufn_signal(M_adder1_alufn_signal),
.out(M_adder1_out),
.z(M_adder1_z),
.v(M_adder1_v),
.n(M_adder1_n)
);
wire [16-1:0] M_comp1_out;
reg [ 1-1:0] M_comp1_z;
reg [ 1-1:0] M_comp1_v;
reg [ 1-1:0] M_comp1_n;
reg [ 6-1:0] M_comp1_alufn_signal;
compare_18 comp1 (
.z(M_comp1_z),
.v(M_comp1_v),
.n(M_comp1_n),
.alufn_signal(M_comp1_alufn_signal),
.out(M_comp1_out)
);
wire [16-1:0] M_boole1_out;
reg [16-1:0] M_boole1_a;
reg [16-1:0] M_boole1_b;
reg [ 6-1:0] M_boole1_alufn_signal;
boolean_19 boole1 (
.a(M_boole1_a),
.b(M_boole1_b),
.alufn_signal(M_boole1_alufn_signal),
.out(M_boole1_out)
);
wire [16-1:0] M_shifter1_out;
reg [16-1:0] M_shifter1_a;
reg [ 4-1:0] M_shifter1_b;
reg [ 6-1:0] M_shifter1_alufn_signal;
shifter_20 shifter1 (
.a(M_shifter1_a),
.b(M_shifter1_b),
.alufn_signal(M_shifter1_alufn_signal),
.out(M_shifter1_out)
);
wire [16-1:0] M_mult_out;
reg [16-1:0] M_mult_a;
reg [16-1:0] M_mult_b;
reg [ 6-1:0] M_mult_alufn_signal;
multiplier_21 mult (
.a(M_mult_a),
.b(M_mult_b),
.alufn_signal(M_mult_alufn_signal),
.out(M_mult_out)
);
always @* begin
M_adder1_a = a;
M_adder1_b = b;
M_adder1_alufn_signal = alufn_signal;
M_comp1_v = M_adder1_v;
M_comp1_n = M_adder1_n;
M_comp1_z = M_adder1_z;
M_comp1_alufn_signal = alufn_signal;
M_boole1_a = a;
M_boole1_b = b;
M_boole1_alufn_signal = alufn_signal;
M_shifter1_a = a;
M_shifter1_b = b[0+3-:4];
M_shifter1_alufn_signal = alufn_signal;
M_mult_a = a;
M_mult_b = b;
M_mult_alufn_signal = alufn_signal;
case (alufn_signal[4+1-:2])
2'h0: begin
case (alufn_signal[0+1-:2])
2'h2: begin
alu = M_mult_out;
end
default: begin
alu = M_adder1_out;
end
endcase
end
2'h1: begin
alu = M_boole1_out;
end
2'h2: begin
alu = M_shifter1_out;
end
2'h3: begin
alu = M_comp1_out;
end
default: begin
alu = 8'h00;
end
endcase
z = M_adder1_z;
v = M_adder1_v;
n = M_adder1_n;
end
endmodule
| 6.727174 |
module add (
in1,
in2,
out
);
input [15:0] in1, in2;
output [15:0] out;
assign out = in1 + in2;
endmodule
| 7.493514 |
module sub (
in1,
in2,
out
);
input [15:0] in1, in2;
output [15:0] out;
assign out = in1 - in2;
endmodule
| 7.353783 |
module mul (
in1,
in2,
out
);
input [15:0] in1, in2;
output [15:0] out;
assign out = in1 * in2;
endmodule
| 7.969753 |
module div (
in1,
in2,
out
);
input [15:0] in1, in2;
output [15:0] out;
assign out = in1 / in2;
endmodule
| 8.452409 |
module mux41 (
in1,
in2,
in3,
in4,
sel,
out
);
input [15:0] in1, in2, in3, in4;
input [1:0] sel;
output [15:0] out;
assign out = sel[1] ? (sel[0] ? in4 : in3) : (sel[0] ? in2 : in1);
endmodule
| 7.514523 |
module alu_16 (
inp1,
inp2,
sel,
out
);
input [15:0] inp1, inp2;
input [1:0] sel;
output [15:0] out;
wire [15:0] out1, out2, out3, out4;
add n1 (
inp1,
inp2,
out1
);
sub n2 (
inp1,
inp2,
out2
);
mul n3 (
inp1,
inp2,
out3
);
div n4 (
inp1,
inp2,
out4
);
mux41 n5 (
out1,
out2,
out3,
out4,
sel,
out
);
endmodule
| 6.735691 |
module ALU_16bit_t;
reg Cin_t;
reg [15:0] A_t, B_t;
reg [4:0] FS_t;
wire Cout_t;
wire [15:0] F_t;
integer i;
integer FE; //F expected
ALU_16bit_v dut (
.Cin(Cin_t),
.A(A_t),
.B(B_t),
.FS(FS_t),
.Cout(Cout_t),
.F(F_t)
);
initial begin
repeat (10) begin
Cin_t <= $random;
A_t <= $random;
B_t <= $random;
for (i = 0; i < 32; i = i + 1) begin
FS_t <= i;
#10;
end
end
end
initial begin
casex (FS_t)
5'b00000: FE = 0;
5'b00001: FE = ~(A_t | B_t);
5'b00010: FE = ~A_t & B_t;
5'b00011: FE = ~A_t;
5'b00100: FE = A_t & ~B_t;
5'b00101: FE = ~B_t;
5'b00110: FE = A_t ^ B_t;
5'b00111: FE = ~(A_t & B_t);
5'b01000: FE = A_t & B_t;
5'b01001: FE = ~(A_t ^ B_t);
5'b01010: FE = B_t;
5'b01011: FE = ~A_t | B_t;
5'b01100: FE = A_t;
5'b01101: FE = A_t | ~B_t;
5'b01110: FE = A_t | B_t;
5'b01111: FE = 131071;
5'b10000: FE = A_t + Cin_t;
5'b10001: FE = ~A_t + 1;
5'b10010: FE = A_t + 1 + Cin_t;
5'b10011: FE = Cin_t - A_t;
5'b10100: FE = A_t + B_t + Cin_t;
5'b10101: FE = ~A_t + B_t + Cin_t;
5'b10110: FE = A_t + ~B_t + Cin_t;
5'b10111: FE = ~A_t + ~B_t + Cin_t;
5'b11xx0: FE = (A_t << 1) + Cin_t;
5'b11xx1: FE = A_t >> 1; //Change this to (A>>1)+Cin by looping back to cin in the block file
endcase
if (F_t != FE) begin
$display("FAILED %b", FS_t);
end
end
initial begin
#3300 $stop;
end
endmodule
| 7.282368 |
module alu_16bit_tb;
//Inputs
reg [15:0] A, B;
reg [3:0] ALU_Sel;
reg M, cin;
//outputs
wire Cn4, equality_check, P, G;
wire [15:0] F;
// Verilog code for ALU
alu_16bit test_unit (
A,
B, // ALU 8-bit Inputs
ALU_Sel, // ALU Selection
M,
cin,
Cn4,
equality_check,
P,
G,
F
);
integer k = 0;
//finding answer for all possible values of select and M
initial begin
A = 16'd1200;
B = 16'd343;
cin = 1'b1;
for (k = 0; k < 32; k = k + 1) #10{ALU_Sel, M} = k;
#10 $finish;
end
endmodule
| 7.277312 |
module alu_16_6 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out,
output reg [0:0] z,
output reg [0:0] v,
output reg [0:0] n
);
wire [16-1:0] M_adder_out;
wire [ 1-1:0] M_adder_z;
wire [ 1-1:0] M_adder_v;
wire [ 1-1:0] M_adder_n;
reg [16-1:0] M_adder_a;
reg [16-1:0] M_adder_b;
reg [ 6-1:0] M_adder_alufn;
adder_16_9 adder (
.a(M_adder_a),
.b(M_adder_b),
.alufn(M_adder_alufn),
.out(M_adder_out),
.z(M_adder_z),
.v(M_adder_v),
.n(M_adder_n)
);
wire [16-1:0] M_boolean_out;
reg [16-1:0] M_boolean_a;
reg [16-1:0] M_boolean_b;
reg [ 6-1:0] M_boolean_alufn;
boolean_16_10 boolean (
.a(M_boolean_a),
.b(M_boolean_b),
.alufn(M_boolean_alufn),
.out(M_boolean_out)
);
wire [16-1:0] M_shifter_out;
reg [16-1:0] M_shifter_a;
reg [16-1:0] M_shifter_b;
reg [ 6-1:0] M_shifter_alufn;
shifter_16_11 shifter (
.a(M_shifter_a),
.b(M_shifter_b),
.alufn(M_shifter_alufn),
.out(M_shifter_out)
);
wire [16-1:0] M_comparator_out;
reg [ 1-1:0] M_comparator_z;
reg [ 1-1:0] M_comparator_v;
reg [ 1-1:0] M_comparator_n;
reg [ 6-1:0] M_comparator_alufn;
compare_16_12 comparator (
.z(M_comparator_z),
.v(M_comparator_v),
.n(M_comparator_n),
.alufn(M_comparator_alufn),
.out(M_comparator_out)
);
always @* begin
M_adder_alufn = alufn;
M_adder_a = a;
M_adder_b = b;
z = M_adder_z;
v = M_adder_v;
n = M_adder_n;
M_comparator_alufn = alufn;
M_comparator_z = M_adder_z;
M_comparator_v = M_adder_v;
M_comparator_n = M_adder_n;
M_boolean_alufn = alufn;
M_boolean_a = a;
M_boolean_b = b;
M_shifter_alufn = alufn;
M_shifter_a = a;
M_shifter_b = b[0+3-:4];
case (alufn[4+1-:2])
2'h0: begin
out = M_adder_out;
end
2'h1: begin
out = M_boolean_out;
z = 1'h0;
v = 1'h0;
n = 1'h0;
end
2'h2: begin
out = M_shifter_out;
z = 1'h0;
v = 1'h0;
n = 1'h0;
end
2'h3: begin
out = M_comparator_out;
end
default: begin
out = 16'h0000;
end
endcase
end
endmodule
| 6.619657 |
module alu_16_7 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out,
output reg [0:0] z,
output reg [0:0] v,
output reg [0:0] n
);
wire [16-1:0] M_adder_out;
wire [ 1-1:0] M_adder_z;
wire [ 1-1:0] M_adder_v;
wire [ 1-1:0] M_adder_n;
reg [16-1:0] M_adder_a;
reg [16-1:0] M_adder_b;
reg [ 6-1:0] M_adder_alufn;
adder_16_11 adder (
.a(M_adder_a),
.b(M_adder_b),
.alufn(M_adder_alufn),
.out(M_adder_out),
.z(M_adder_z),
.v(M_adder_v),
.n(M_adder_n)
);
wire [16-1:0] M_boolean_out;
reg [16-1:0] M_boolean_a;
reg [16-1:0] M_boolean_b;
reg [ 6-1:0] M_boolean_alufn;
boolean_16_12 boolean (
.a(M_boolean_a),
.b(M_boolean_b),
.alufn(M_boolean_alufn),
.out(M_boolean_out)
);
wire [16-1:0] M_shifter_out;
reg [16-1:0] M_shifter_a;
reg [16-1:0] M_shifter_b;
reg [ 6-1:0] M_shifter_alufn;
shifter_16_13 shifter (
.a(M_shifter_a),
.b(M_shifter_b),
.alufn(M_shifter_alufn),
.out(M_shifter_out)
);
wire [16-1:0] M_comparator_out;
reg [ 1-1:0] M_comparator_z;
reg [ 1-1:0] M_comparator_v;
reg [ 1-1:0] M_comparator_n;
reg [ 6-1:0] M_comparator_alufn;
compare_16_14 comparator (
.z(M_comparator_z),
.v(M_comparator_v),
.n(M_comparator_n),
.alufn(M_comparator_alufn),
.out(M_comparator_out)
);
always @* begin
M_adder_alufn = alufn;
M_adder_a = a;
M_adder_b = b;
z = M_adder_z;
v = M_adder_v;
n = M_adder_n;
M_comparator_alufn = alufn;
M_comparator_z = M_adder_z;
M_comparator_v = M_adder_v;
M_comparator_n = M_adder_n;
M_boolean_alufn = alufn;
M_boolean_a = a;
M_boolean_b = b;
M_shifter_alufn = alufn;
M_shifter_a = a;
M_shifter_b = b[0+3-:4];
case (alufn[4+1-:2])
2'h0: begin
out = M_adder_out;
end
2'h1: begin
out = M_boolean_out;
z = 1'h0;
v = 1'h0;
n = 1'h0;
end
2'h2: begin
out = M_shifter_out;
z = 1'h0;
v = 1'h0;
n = 1'h0;
end
2'h3: begin
out = M_comparator_out;
end
default: begin
out = 16'h0000;
end
endcase
end
endmodule
| 6.964163 |
module alu_16_9 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out,
output reg [0:0] z,
output reg [0:0] v,
output reg [0:0] n
);
wire [16-1:0] M_adder_out;
wire [ 1-1:0] M_adder_z;
wire [ 1-1:0] M_adder_v;
wire [ 1-1:0] M_adder_n;
reg [16-1:0] M_adder_a;
reg [16-1:0] M_adder_b;
reg [ 6-1:0] M_adder_alufn;
adder_16_16 adder (
.a(M_adder_a),
.b(M_adder_b),
.alufn(M_adder_alufn),
.out(M_adder_out),
.z(M_adder_z),
.v(M_adder_v),
.n(M_adder_n)
);
wire [16-1:0] M_boolean_out;
reg [16-1:0] M_boolean_a;
reg [16-1:0] M_boolean_b;
reg [ 6-1:0] M_boolean_alufn;
boolean_16_17 boolean (
.a(M_boolean_a),
.b(M_boolean_b),
.alufn(M_boolean_alufn),
.out(M_boolean_out)
);
wire [16-1:0] M_shifter_out;
reg [16-1:0] M_shifter_a;
reg [16-1:0] M_shifter_b;
reg [ 6-1:0] M_shifter_alufn;
shifter_16_18 shifter (
.a(M_shifter_a),
.b(M_shifter_b),
.alufn(M_shifter_alufn),
.out(M_shifter_out)
);
wire [16-1:0] M_comparator_out;
reg [ 1-1:0] M_comparator_z;
reg [ 1-1:0] M_comparator_v;
reg [ 1-1:0] M_comparator_n;
reg [ 6-1:0] M_comparator_alufn;
compare_16_19 comparator (
.z(M_comparator_z),
.v(M_comparator_v),
.n(M_comparator_n),
.alufn(M_comparator_alufn),
.out(M_comparator_out)
);
always @* begin
M_adder_alufn = alufn;
M_adder_a = a;
M_adder_b = b;
z = M_adder_z;
v = M_adder_v;
n = M_adder_n;
M_comparator_alufn = alufn;
M_comparator_z = M_adder_z;
M_comparator_v = M_adder_v;
M_comparator_n = M_adder_n;
M_boolean_alufn = alufn;
M_boolean_a = a;
M_boolean_b = b;
M_shifter_alufn = alufn;
M_shifter_a = a;
M_shifter_b = b[0+3-:4];
case (alufn[4+1-:2])
2'h0: begin
out = M_adder_out;
end
2'h1: begin
out = M_boolean_out;
z = 1'h0;
v = 1'h0;
n = 1'h0;
end
2'h2: begin
out = M_shifter_out;
z = 1'h0;
v = 1'h0;
n = 1'h0;
end
2'h3: begin
out = M_comparator_out;
end
default: begin
out = 16'h0000;
end
endcase
end
endmodule
| 6.556797 |
module alu_16_bit (
input [15:0] A,
input [15:0] B,
input [2:0] op,
output reg [15:0] R,
output reg AltB
);
always @* begin
case (op)
0: R = A & B; // And
1: R = A | B; // Or
2: R = A + B; // Add
3: R = B - A; // Sub
4:
if ($signed(B) < 0) begin // shift
R = (A >> (~B)) >> 1;
end else if (B == 0) begin
R = A;
end else begin
R = A << B;
end
5: begin // slt
AltB = (A < B);
R = A + B;
end
default: R = A + B;
endcase
end
endmodule
| 8.001301 |
module alu_16_bit_11 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out
);
wire [ 1-1:0] M_arithmeticUnit_z;
wire [ 1-1:0] M_arithmeticUnit_v;
wire [ 1-1:0] M_arithmeticUnit_n;
wire [16-1:0] M_arithmeticUnit_out;
reg [16-1:0] M_arithmeticUnit_a;
reg [16-1:0] M_arithmeticUnit_b;
reg [ 4-1:0] M_arithmeticUnit_alufn;
alu_arithmetic_19 arithmeticUnit (
.a(M_arithmeticUnit_a),
.b(M_arithmeticUnit_b),
.alufn(M_arithmeticUnit_alufn),
.z(M_arithmeticUnit_z),
.v(M_arithmeticUnit_v),
.n(M_arithmeticUnit_n),
.out(M_arithmeticUnit_out)
);
wire [16-1:0] M_booleanUnit_out;
reg [16-1:0] M_booleanUnit_a;
reg [16-1:0] M_booleanUnit_b;
reg [ 4-1:0] M_booleanUnit_alufn;
alu_boolean_20 booleanUnit (
.a(M_booleanUnit_a),
.b(M_booleanUnit_b),
.alufn(M_booleanUnit_alufn),
.out(M_booleanUnit_out)
);
wire [16-1:0] M_compareUnit_out;
reg [16-1:0] M_compareUnit_a;
reg [16-1:0] M_compareUnit_b;
reg [ 6-1:0] M_compareUnit_alufn;
alu_compare_21 compareUnit (
.a(M_compareUnit_a),
.b(M_compareUnit_b),
.alufn(M_compareUnit_alufn),
.out(M_compareUnit_out)
);
wire [16-1:0] M_shifterUnit_out;
reg [16-1:0] M_shifterUnit_a;
reg [ 4-1:0] M_shifterUnit_b;
reg [ 2-1:0] M_shifterUnit_alufn;
alu_shifter_22 shifterUnit (
.a(M_shifterUnit_a),
.b(M_shifterUnit_b),
.alufn(M_shifterUnit_alufn),
.out(M_shifterUnit_out)
);
reg int_z;
reg int_v;
reg int_n;
always @* begin
int_z = 1'h0;
int_v = 1'h0;
int_n = 1'h0;
M_arithmeticUnit_alufn = alufn[0+3-:4];
M_arithmeticUnit_a = a;
M_arithmeticUnit_b = b;
int_z = M_arithmeticUnit_z;
int_v = M_arithmeticUnit_v;
int_n = M_arithmeticUnit_n;
M_compareUnit_alufn = alufn;
M_compareUnit_a = a;
M_compareUnit_b = b;
M_booleanUnit_alufn = alufn[0+3-:4];
M_booleanUnit_a = a;
M_booleanUnit_b = b;
M_shifterUnit_alufn = alufn[0+1-:2];
M_shifterUnit_a = a;
M_shifterUnit_b = b[0+3-:4];
case (alufn[4+1-:2])
2'h0: begin
out = M_arithmeticUnit_out;
end
2'h1: begin
out = M_booleanUnit_out;
end
2'h2: begin
out = M_shifterUnit_out;
end
2'h3: begin
out = M_compareUnit_out;
end
default: begin
out = 16'h0000;
end
endcase
end
endmodule
| 6.813687 |
module alu_16_bit_tb;
// Inputs
reg [15:0] A;
reg [15:0] B;
reg [2:0] op;
// Outputs
wire [15:0] R;
wire AltB;
// Instantiate the Unit Under Test (UUT)
alu_16_bit uut (
.A(A),
.B(B),
.op(op),
.R(R),
.AltB(AltB)
);
initial begin
// Initialize Inputs
A = 0;
B = 0;
op = 0;
// Wait 100 ns for global reset to finish
#100;
// And
$display("AND:");
op = 0;
A = -10;
B = -10;
#1;
repeat (20) begin
repeat (20) begin
A = A + 1;
#5;
if ((A & B) == R) begin
$display("PASS AND");
end else begin
$display("FAIL: %b & %b = %b", A, B, R);
end
end
A = -10;
B = B + 1;
#5;
end
// Or
$display("OR:");
op = 1;
A = -10;
B = -10;
#1;
repeat (20) begin
repeat (20) begin
A = A + 1;
#5;
if ((A | B) == R) begin
$display("PASS OR");
end else begin
$display("FAIL: %b | %b = %b", A, B, R);
end
end
A = -10;
B = B + 1;
#5;
end
// Add
$display("Add:");
op = 2;
A = -10;
B = -10;
#1;
repeat (20) begin
repeat (20) begin
A = A + 1;
#5;
if (A + B == R) begin
$display("PASS Add");
end else begin
$display("FAIL: %d + %d = %d", A, B, R);
end
end
A = -10;
B = B + 1;
#5;
end
// Sub
$display("Sub:");
op = 3;
A = -10;
B = -10;
#1;
repeat (20) begin
repeat (20) begin
A = A + 1;
#5;
if (A - B == R) begin
$display("PASS Sub");
end else begin
$display("FAIL: %d - %d = %d", A, B, R);
end
end
A = -10;
B = B + 1;
#5;
end
// Shift
$display("Shift:");
op = 4;
A = -10;
B = -10;
#1;
repeat (20) begin
repeat (20) begin
A = A + 1;
#5;
if ($signed(B) < 0) begin // right shift test
if ((A >> (~B)) >> 1 == R) begin
$display("PASS: Shift right");
end else begin
$display("FAIL: Shift right");
end
end else begin // left shift test
if ((A << B) == R) begin
$display("PASS: Shift left");
end else begin
$display("FAIL: Shift right");
end
end
end
A = -10;
B = B + 1;
#5;
end
// Set on Less than
$display("SLT:");
op = 5;
A = -10;
B = -10;
#1;
repeat (20) begin
repeat (20) begin
A = A + 1;
#5;
if (((A < B) && AltB) || (~(A < B) && ~AltB)) begin
$display("PASS Slt");
end else begin
$display("FAIL: %d < %d = %d", A, B, AltB);
end
end
A = -10;
B = B + 1;
#5;
end
end
endmodule
| 7.169615 |
module alu_181 #(
parameter WIDTH = 16
) (
input [WIDTH-1:0] A_in,
input [WIDTH-1:0] B_in,
output [WIDTH-1:0] out,
input mode, // alu or logical
input [3:0] op_in, // alu op on the 181s
input carry_in,
output carry_out,
output reg equal_out
);
localparam NUM181 = WIDTH / 4; // a 181 for every 4 bits
wire [NUM181-1:0] equals; // equals on the 181s
wire [NUM181-1:0] CP_bar; // P outs on the 181s
wire [NUM181-1:0] CG_bar; // G outs on the 181s
wire [NUM181-2:0] carries; // carry lookaheads from the 182
// set equal_out to true only if all the bits in equal are set.
// use a fancy loop to deal with variable WIDTH
always_comb begin
int count = 0;
for (int i = 0; i < NUM181; i++) begin
if (equals[i]) count++;
end
equal_out = count == NUM181;
end
// stamp out 4 181s and a 182
// NOTE: assumes WIDTH=16.
// TODO: use generate to stamp out a variable number of 181s
// first 181, bits [3:0]
TopLevel74181b ALU0 (
.S (op_in),
.M (mode),
.CNb(carry_in), // carry in from the outside
.A (A_in[3:0]),
.B (B_in[3:0]),
.X(CP_bar[0]),
.Y(CG_bar[0]),
.AEB(equals[0]),
.CN4b(),
.F(out[3:0])
);
// second 181, bits [7:4]
TopLevel74181b ALU1 (
.S (op_in),
.M (mode),
.CNb(carries[0]),
.A (A_in[7:4]),
.B (B_in[7:4]),
.X(CP_bar[1]),
.Y(CG_bar[1]),
.AEB(equals[1]),
.CN4b(),
.F(out[7:4])
);
// third 181, bits [11:8]
TopLevel74181b ALU2 (
.S (op_in),
.M (mode),
.CNb(carries[1]),
.A (A_in[11:8]),
.B (B_in[11:8]),
.X(CP_bar[2]),
.Y(CG_bar[2]),
.AEB(equals[2]),
.CN4b(),
.F(out[11:8])
);
// fourth 181, bits [15:12]
TopLevel74181b ALU3 (
.S (op_in),
.M (mode),
.CNb(carries[2]),
.A (A_in[15:12]),
.B (B_in[15:12]),
.X(CP_bar[3]),
.Y(CG_bar[3]),
.AEB(equals[3]),
.CN4b(carry_out), // carry out of the module
.F(out[15:12])
);
// a 182 carry look ahead
TopLevel74182b CLA (
.CN(carry_in),
.PB(CP_bar),
.GB(CG_bar),
.PBo(),
.GBo(),
.CNX(carries[0]),
.CNY(carries[1]),
.CNZ(carries[2])
);
endmodule
| 9.24349 |
module Circuit74182 (
CN,
PB,
GB,
PBo,
GBo,
CNX,
CNY,
CNZ
);
input [3:0] PB, GB;
input CN;
output PBo, GBo, CNX, CNY, CNZ;
TopLevel74182b Ckt74182b (
CN,
PB,
GB,
PBo,
GBo,
CNX,
CNY,
CNZ
);
endmodule
| 6.993964 |
module TopLevel74181b (
S,
A,
B,
M,
CNb,
F,
X,
Y,
CN4b,
AEB
);
input [3:0] A, B, S;
input CNb, M;
output [3:0] F;
output AEB, X, Y, CN4b;
wire [3:0] E, D, C, Bb;
Emodule Emod1 (
A,
B,
S,
E
);
Dmodule Dmod2 (
A,
B,
S,
D
);
CLAmodule CLAmod3 (
E,
D,
CNb,
C,
X,
Y,
CN4b
);
Summodule Summod4 (
E,
D,
C,
M,
F,
AEB
);
endmodule
| 6.940936 |
module testbench (
input clk
);
localparam trace = 1;
/// test of our ALU module
reg [15:0] A = 0;
reg [15:0] B = 1;
reg C_in = 1; // carry in
reg [3:0] select = 'b1001; // add
reg mode = 0; // alu ops
wire [15:0] out;
wire C_out;
wire Equal;
alu_181 alu (
.A_in(A),
.B_in(B),
.out(out),
.mode(mode),
.op_in(select),
.carry_in(C_in),
.carry_out(C_out),
.equal_out(Equal)
);
always_ff @(posedge clk) begin
A <= A + 1;
//A <= $random;
//B <= $random;
//A <= out;
if (trace) $display("A 0x%x, B 0x%x, out 0x%x, carry_out %d", A, B, out, C_out);
end
endmodule
| 6.751666 |
module ALU_1B (
Y,
CarryOut,
A,
B,
Less,
CarryIn,
A_invert,
B_invert,
Op
);
input A, B, CarryIn, Less;
input A_invert, B_invert;
input [1:0] Op;
output Y;
output CarryOut;
wire T1, T2;
wire Y1;
ALU_adder Adder (
Y1,
CarryOut,
T1,
T2,
CarryIn
);
assign Y = (Op == 2'b00) ? (T1 & T2) : ((Op == 2'b01) ? (T1 | T2) : ((Op == 2'b10) ? Y1 : Less));
assign T1 = (A_invert) ? (~A) : A;
assign T2 = (B_invert) ? (~B) : B;
endmodule
| 7.049592 |
module ALU_adder (
Sum,
Carry,
A,
B,
C
);
input A, B, C;
output Sum, Carry;
assign {Carry, Sum} = A + B + C;
endmodule
| 8.504694 |
module ALU_1B_MSB (
Set,
Overflow,
Y,
CarryOut,
A,
B,
Less,
CarryIn,
A_invert,
B_invert,
Op
);
input A, B, CarryIn, Less;
input A_invert, B_invert;
input [1:0] Op;
output Y;
output Set, Overflow, CarryOut;
wire T1, T2;
wire Y1;
ALU_adder Adder (
Y1,
CarryOut,
T1,
T2,
CarryIn
);
assign Set = Y1;
assign Y = (Op == 2'b00) ? (T1 & T2) : ((Op == 2'b01) ? (T1 | T2) : ((Op == 2'b10) ? Y1 : Less));
assign T1 = (A_invert) ? (~A) : A;
assign T2 = (B_invert) ? (~B) : B;
/*
always@(Op,T1,T2,Y1)
begin
if(Op==2'b00)
Y=T1 & T2;
else
begin
if(Op==2'b01)
Y=T1 | T2;
else
begin if(Op==2'b10)
Y=Y1;
else
Y=Less;
end
end
end
*/
/*always@(A_invert,A)
begin
if(A_invert)
T1=~A;
else
T1=A;
end
always@(B_invert,B)
begin
if (B_invert)
T2=~B;
else
T2=B;
end
*/
always @(T1, T2, B_invert, CarryOut, Y1) begin
end
endmodule
| 6.746766 |
module ALU_1bit_tb;
reg a, b, Ainvert, Binvert, Cin;
reg [1:0] operation;
wire sum, carry;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
ALU_1bit UUT (
a,
b,
Ainvert,
Binvert,
Cin,
operation,
sum,
carry
);
initial begin
$dumpfile("alu.vcd");
$dumpvars(0, ALU_1bit_tb);
end
initial // initial block executes only once
begin
// values for a and b
a = 1;
b = 1;
Ainvert = 0;
Binvert = 0;
Cin = 0;
operation = 2'b00;
#1 $display("sum %d", sum);
$display("carry %d", carry);
$display("===============");
#period; // wait for period
a = 1;
b = 1;
Ainvert = 0;
Binvert = 0;
Cin = 0;
operation = 2'b01;
#1 $display("sum %d", sum);
$display("carry %d", carry);
$display("===============");
#period;
a = 1;
b = 1;
Ainvert = 0;
Binvert = 0;
Cin = 0;
operation = 2'b11;
#1 $display("sum %d", sum);
$display("carry %d", carry);
$display("===============");
#period;
end
endmodule
| 6.509043 |
module ALU_1_bit (
input a,
b,
CarryIn,
input [3:0] ALUOp,
output reg Result,
output reg CarryOut
);
always @(ALUOp or a or b or CarryIn) begin
if (ALUOp[1:0] == 2'b00) begin
if (ALUOp[3:2] == 2'b00) Result <= a & b;
else begin
if (ALUOp[3:2] == 2'b11) assign Result = ~(a | b);
end
end
if (ALUOp[1:0] == 2'b01) begin
if (ALUOp[3:2] == 2'b00) assign Result = a | b;
end
if (ALUOp[1:0] == 2'b10) begin
if (ALUOp[3:2] == 2'b00) begin
assign Result = (a & ~b & ~CarryIn) | (~a & b & ~CarryIn) | (~a & ~b & CarryIn) | (a & b & CarryIn);
assign CarryOut = (a & CarryIn) | (b & CarryIn) | (a & b);
end else begin
if (ALUOp[3:2] == 2'b01) begin
assign Result = (a & ~b & ~CarryIn) | (~a & b & ~CarryIn) | (~a & ~b & CarryIn) | (a & b & CarryIn);
assign CarryOut = (a & CarryIn) | (b & CarryIn) | (a & b);
end
end
end
end
endmodule
| 6.504433 |
module for use as the most-significant bit
// of the 16-bit ALU.
module alu_1_bit_msb(result, overflow, set, c_out, a, b, less, c_in, op);
input a, b;
input less;
input c_in;
input [2:0] op;
output result, overflow, set, c_out;
wire m, n, p, q;
not g1(m, b);
mux_2_to_1 mux1(n, b, m, op[2]);
and g2(p, a, n);
or g3(q, a, n);
full_adder fa(set, c_out, a, n, c_in);
mux_4_to_1 mux2(result, p, q, set, less, op[1:0]);
xor g4(overflow, c_out, c_in);
endmodule
| 7.198888 |
module ALU_1_tb ();
reg [15:0] op1, op2;
reg [ 1:0] func;
wire [15:0] result;
wire [ 5:0] flags;
reg [15:0] inputTests1[0:15];
reg [15:0] inputTests2[0:15];
reg [15:0] resultTests[0:15];
reg [ 5:0] flagsTests [0:15];
reg [ 1:0] funcTests [0:15];
ALU_1 alu (
.op1(op1),
.op2(op2),
.func(func),
.result(result),
.outFlags(flags)
);
integer i;
initial begin
// hold reset state for 100 ns.
inputTests1[0] = 16'b0000_0000_0000_0001;
inputTests2[0] = 16'b0000_0000_0000_0001;
funcTests[0] = 2'b11; // ADD
resultTests[0] = 16'b0000_0000_0000_0010;
inputTests1[1] = 16'b1111_1111_1111_1111;
inputTests2[1] = 16'b0000_0000_0000_0001;
funcTests[1] = 2'b11; // ADD
resultTests[1] = 16'b0000_0000_0000_0000;
inputTests1[2] = 16'b0000_0000_1111_1111;
inputTests2[2] = 16'b0000_0000_0000_0101;
funcTests[2] = 2'b10; // MOV
resultTests[2] = 16'b0000_0000_1111_1111;
inputTests1[3] = 16'b0000_1111_0000_1111;
inputTests2[3] = 16'b0000_0000_0000_0001;
funcTests[3] = 2'b01; // NOT
resultTests[3] = 16'b1111_0000_1111_0000;
inputTests1[4] = 16'b1111_0000_0000_1111;
inputTests2[4] = 16'b1111_0000_0000_1111;
funcTests[4] = 2'b01; // NOT
resultTests[4] = 16'b0000_1111_1111_0000;
// op1 = 16'b0000_0000_0000_0001;
// op2 = 116'b0000_0000_0000_0001;
// func = 4'b0111;
// #10;
for (i = 0; i <= 4; i = i + 1) begin
op1 = inputTests1[i];
op2 = inputTests2[i];
func = funcTests[i];
#10;
if (result == resultTests[i]) begin
$display("success");
end else begin
$display("fail in %b,ouput: %b ,expected result: %b", i, result, resultTests[i]);
end
end
$finish;
end
endmodule
| 6.660444 |
module alu (
dataOut_1,
dataOut_2,
ext32,
ALUSrc,
ALUOp,
zero,
overflow,
alu_res,
write_30
);
input [31:0] dataOut_1, dataOut_2, ext32;
input [1:0] ALUOp;
input ALUSrc;
input write_30;
output zero, overflow;
output reg [31:0] alu_res;
wire [31:0] a, b;
wire [32:0] tmp;
wire overflow_0;
assign a = dataOut_1;
assign b = (ALUSrc == 1'b0) ? dataOut_2 : ext32;
assign tmp = {a[31], a} + b;
assign overflow_0 = (ALUOp == 2'b00) ? ((tmp[32] != tmp[31]) ? 1 : 0) : 0;
assign zero = (alu_res == 32'b0) ? 1 : 0;
assign overflow = (write_30 == 1) ? overflow_0 : 0;
/*
00 +
01 -
10 |
11 slt
*/
always @(*) begin
case (ALUOp)
2'b00: begin
alu_res = a + b;
end
2'b01: begin
alu_res = a - b;
end
2'b10: begin
alu_res = a | b;
end
2'b11: begin
alu_res = ($signed(a) < $signed(b)) ? 32'd1 : 32'd0;
end
default: begin
$display("invalid ALUOp!");
end
endcase
end
endmodule
| 6.813467 |
module Alu_2_Operations (
input [3:0] A,
B,
input c,
output [3:0] Out
);
assign Out = c != 1 ? A + B : A - B;
endmodule
| 7.849354 |
module alu_3 #(
parameter STAGE_ID = 0,
parameter ACTION_LEN = 25,
parameter META_LEN = 256,
parameter COMP_LEN = 100
) (
input clk,
input rst_n,
//the input data shall be metadata & com_ins
input [META_LEN+COMP_LEN-1:0] comp_meta_data_in,
input comp_meta_data_valid_in,
input [ ACTION_LEN-1:0] action_in,
input action_valid_in,
//output is the modified metadata plus comp_ins
output reg [META_LEN+COMP_LEN-1:0] comp_meta_data_out,
output reg comp_meta_data_valid_out
);
//need delay for one cycle before the result pushed out
/*
action format:
[24:20]: opcode;
[19:12]: dst_port;
[11]: discard_flag;
[10:5]: next_table_id;
[4:0]: reserverd_bit;
*/
/*
metadata fields that are related:
TODO: next table id is not supported yet.
[255:250]: next_table_id;
[249:129]: reservered for other use;
[128]: discard_field;
[127:0]: copied from NetFPGA's md;
*/
localparam IDLE = 0, OP_1 = 1, OP_2 = 2;
reg [1:0] state, state_next;
reg [META_LEN+COMP_LEN-1:0] comp_meta_data_out_r;
reg comp_meta_data_valid_next;
always @(*) begin
state_next = state;
comp_meta_data_out_r = comp_meta_data_out;
comp_meta_data_valid_next = 0;
case (state)
IDLE: begin
if (action_valid_in) begin
state_next = OP_1;
case (action_in[24:21])
4'b1100: begin
comp_meta_data_out_r[355:32] = {action_in[10:5], comp_meta_data_in[349:32]};
comp_meta_data_out_r[31:24] = action_in[20:13];
comp_meta_data_out_r[23:0] = comp_meta_data_in[23:0];
end
4'b1101: begin
comp_meta_data_out_r[355:129] = {action_in[10:5], comp_meta_data_in[349:129]};
comp_meta_data_out_r[128] = action_in[12];
comp_meta_data_out_r[127:0] = comp_meta_data_in[127:0];
end
default: begin
comp_meta_data_out_r = comp_meta_data_in;
end
endcase
end
end
OP_1: begin
// empty cycle
state_next = OP_2;
end
OP_2: begin
comp_meta_data_valid_next = 1;
state_next = IDLE;
end
endcase
end
always @(posedge clk) begin
if (~rst_n) begin
comp_meta_data_out <= 0;
comp_meta_data_valid_out <= 0;
state <= IDLE;
end else begin
state <= state_next;
comp_meta_data_out <= comp_meta_data_out_r;
comp_meta_data_valid_out <= comp_meta_data_valid_next;
end
end
endmodule
| 7.687102 |
module alu_32 #(
parameter WIDTH = 32
) (
input [WIDTH - 1 : 0] a,
b,
input [2:0] f,
output reg [WIDTH -1 : 0] y,
output reg z
);
parameter ADD_32 = 3'b000;
parameter SUB_32 = 3'b001;
parameter AND_32 = 3'b010;
parameter OR_32 = 3'b011;
parameter XOR_32 = 3'b100;
always @(*) begin
case (f)
ADD_32: y = a + b;
SUB_32: y = a - b;
AND_32: y = a & b;
OR_32: y = a | b;
XOR_32: y = a ^ b;
default: y = 32'b0;
endcase
end
always @(*) begin
if (y == 32'b0) z = 1'b0;
else z = 1'b1;
end
endmodule
| 8.332004 |
module ALU_32bit (
SW1,
SW2,
SW4,
clock_100Mhz,
//reset,
a_to_g,
an,
LED1,
LED2,
LED4,
aluout
);
input SW1; // Represents S0
input SW2; // Represents S1
input SW4; // Represents Reset
input clock_100Mhz;
//input reset;
output reg [7:0] a_to_g;
output reg [7:0] an;
output LED1, LED2, LED4;
output [31:0] aluout;
parameter [15:0] a = 16'h8089;
parameter [15:0] b = 16'h3000;
parameter cin = 1'b0;
parameter bin = 1'b0;
reg [31:0] aluout;
wire cout;
wire bout;
wire [31:0] sum;
wire [31:0] diff;
wire [31:0] shift;
wire [31:0] product;
reg [3:0] LED_BCD;
wire [3:0] LED_activating_counter;
reg [19:0] refresh_counter;
FA_16bit U1 (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cFlag(cout)
);
FS_16bit U2 (
.a(a),
.b(b),
.bin(bin),
.diff(diff),
.bout(bout)
);
mult_16bit U3 (
.a(a),
.b(b),
.mult(product)
);
Shift_RightA U4 (
.a(a),
.shift_a(shift)
);
assign LED1 = (~SW4 & SW1);
assign LED2 = (~SW4 & SW2);
assign LED4 = SW4;
always @(posedge clock_100Mhz) begin
if (SW4) //Switch 4 is reset
refresh_counter <= 0;
else refresh_counter <= refresh_counter + 1;
end
assign LED_activating_counter = refresh_counter[19:17];
always @(*) begin
casex ({
SW4, SW1, SW2
})
3'b000: begin
aluout <= sum;
end
3'b001: begin
aluout <= diff;
end
3'b010: aluout <= product;
3'b011: aluout <= shift;
3'b1xx: aluout <= 16'h0000;
default: aluout <= 16'h0000;
endcase
case (LED_activating_counter)
3'b000: begin
an = 8'b01111111;
LED_BCD = aluout[31:28];
end
3'b001: begin
an = 8'b10111111;
LED_BCD = aluout[27:24];
end
3'b010: begin
an = 8'b11011111;
LED_BCD = aluout[23:20];
end
3'b011: begin
an = 8'b11101111;
LED_BCD = aluout[19:16];
end
3'b100: begin
an = 8'b11110111;
LED_BCD = aluout[15:12];
end
3'b101: begin
an = 8'b11111011;
LED_BCD = aluout[11:8];
end
3'b110: begin
an = 8'b11111101;
LED_BCD = aluout[7:4];
end
3'b111: begin
an = 8'b11111110;
LED_BCD = aluout[3:0];
end
endcase
end
always @(LED_BCD) begin
casex (LED_BCD)
4'b0000: a_to_g = 8'b1_000_0001;
4'b0001: a_to_g = 8'b1_100_1111;
4'b0010: a_to_g = 8'b1_001_0010;
4'b0011: a_to_g = 8'b1_000_0110;
4'b0100: a_to_g = 8'b1_100_1100;
4'b0101: a_to_g = 8'b1_010_0100;
4'b0110: a_to_g = 8'b1_010_0000;
4'b0111: a_to_g = 8'b1_000_1111;
4'b1000: a_to_g = 8'b1_000_0000;
4'b1001: a_to_g = 8'b1_000_1100;
4'b1010: a_to_g = 8'b1_000_1000;
4'b1011: a_to_g = 8'b0_110_0000;
4'b1100: a_to_g = 8'b1_011_0001;
4'b1101: a_to_g = 8'b1_100_0010;
4'b1110: a_to_g = 8'b1_011_0000;
4'b1111: a_to_g = 8'b1_011_1000;
default: a_to_g = 8'bX0000000;
endcase
end
endmodule
| 7.299764 |
module FA_16bit (
a,
b,
cin,
sum,
cFlag
);
input [15:0] a;
input [15:0] b;
input cin;
output [15:0] sum;
output cFlag;
assign sum = a + b + cin;
assign cFlag = (a & b | (a ^ b) & cin);
endmodule
| 6.642525 |
module FS (
a,
b,
bin,
diff,
bout
);
input a;
input b;
input bin;
output diff;
output bout;
wire an;
wire w0;
wire w0not;
wire w1;
wire w2;
// Design implementation of a single bit full subtractor
not n1 (an, a);
not n2 (w0not, w0);
xor x1 (w0, a, b);
and a1 (w1, an, b);
xor x2 (diff, w0, bin);
and a2 (w2, w0not, bin);
or o1 (bout, w2, w1);
endmodule
| 7.619808 |
module FS_16bit (
a,
b,
bin,
diff,
bout
);
input [15:0] a;
input [15:0] b;
input bin;
output [15:0] diff;
output bout;
wire w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12, w13, w14, w15;
// Design implementation
// Using the previous module of a single bit full subtractor
// this 16-bit subtractor can be created by instantiating
// the FS module and adding wires to connect each block together to
// form a 16-bit subtractor.
FS F0 (
a[0],
b[0],
bin,
diff[0],
w0
);
FS F1 (
a[1],
b[1],
w0,
diff[1],
w1
);
FS F2 (
a[2],
b[2],
w1,
diff[2],
w2
);
FS F3 (
a[3],
b[3],
w2,
diff[3],
w3
);
FS F4 (
a[4],
b[4],
w3,
diff[4],
w4
);
FS F5 (
a[5],
b[5],
w4,
diff[5],
w5
);
FS F6 (
a[6],
b[6],
w5,
diff[6],
w6
);
FS F7 (
a[7],
b[7],
w6,
diff[7],
w7
);
FS F8 (
a[8],
b[8],
w7,
diff[8],
w8
);
FS F9 (
a[9],
b[9],
w8,
diff[9],
w9
);
FS F10 (
a[10],
b[10],
w9,
diff[10],
w10
);
FS F11 (
a[11],
b[11],
w10,
diff[11],
w11
);
FS F12 (
a[12],
b[12],
w11,
diff[12],
w12
);
FS F13 (
a[13],
b[13],
w12,
diff[13],
w13
);
FS F14 (
a[14],
b[14],
w13,
diff[14],
w14
);
FS F15 (
a[15],
b[15],
w14,
diff[15],
bout
);
endmodule
| 8.163367 |
module mult_16bit (
a,
b,
mult
);
input [15:0] a;
input [15:0] b;
output [31:0] mult;
assign mult = a * b;
endmodule
| 7.498629 |
module Shift_RightA (
a,
shift_a
);
input [15:0] a;
output [15:0] shift_a;
assign shift_a = a >> 1;
endmodule
| 7.399126 |
module ALU_32_bit (
a,
b,
Binvert,
Carryin,
Operation,
Result,
CarryOut
);
input Binvert, Carryin;
input [1:0] Operation;
input [31:0] a, b;
output [31:0] Result;
output CarryOut;
wire [31:0] out, notB, in0, in1, in2;
assign {notB} = ~b;
AND_32_Bit AND (
in0,
a,
b
);
OR_32_Bit OR (
in1,
a,
b
);
MUX_32_bit_2_ip ADDORSUB (
out,
Binvert,
b,
notB
);
FADDER32BIT FA (
in2,
CarryOut,
a,
out,
Carryin
);
MUX_32_bit_3_ip FINAL (
Result,
Operation,
in0,
in1,
in2
);
endmodule
| 7.226228 |
module ALU_4B (
Y,
CarryOut,
A,
B,
Less,
CarryIn,
A_invert,
B_invert,
Op
);
output [3:0] Y;
output CarryOut;
input [3:0] A, B, Less;
input CarryIn;
input A_invert, B_invert;
input [1:0] Op;
wire [3:0] GC;
wire [3:0] C, G, P;
assign CarryOut = C[3];
ALU_1B ALU0 (
Y[0],
C[0],
A[0],
B[0],
Less[0],
CarryIn,
A_invert,
B_invert,
Op
);
ALU_1B ALU1 (
Y[1],
C[1],
A[1],
B[1],
Less[1],
C[0],
A_invert,
B_invert,
Op
);
ALU_1B ALU2 (
Y[2],
C[2],
A[2],
B[2],
Less[2],
C[1],
A_invert,
B_invert,
Op
);
ALU_1B ALU3 (
Y[3],
C[3],
A[3],
B[3],
Less[3],
C[2],
A_invert,
B_invert,
Op
);
/*
PG PG1(G[0],P[0],A[0],B[0]);
PG PG2(G[1],P[1],A[1],B[1]);
PG PG3(G[2],P[2],A[2],B[2]);
PG PG4(G[3],P[3],A[3],B[3]);
assign GC[1] = G[0] + P[0]*CarryIn;
assign GC[2] = G[1] + P[1]*GC[1];
assign GC[3] = G[2] + P[2]*GC[2];
assign CarryOut = G[3] + P[3]*GC[3];
*/
endmodule
| 6.760633 |
module or5_0 (
IN1,
IN3,
IN2,
IN5,
IN4,
OUT
);
/* synthesis black_box */
input IN1;
input IN3;
input IN2;
input IN5;
input IN4;
output OUT;
endmodule
| 6.514611 |
module or5_0 (
IN1,
IN3,
IN2,
IN5,
IN4,
OUT
);
/* synthesis black_box */
input IN1;
input IN3;
input IN2;
input IN5;
input IN4;
output OUT;
or (OUT, IN1, IN2, IN3, IN4, IN5);
endmodule
| 6.514611 |
modules:
// 1. a 1-bit ALU building block (based on figure C.5.9 of the 4th edition of
// the textbook, which is same as figure B.5.9 of the 3rd edition), and
// 2. a 4-bit ALU built by instantiating 4 of the above building blocks and
// adding needed glue logic for SLT implementation (based on figure C.5.12 of the
// 4th edition of our textbook, which is same as figure B.5.12 of the 3rd edition)
//-------------------------------------------------------------------------------
// 1-bit ALU building block alu_1_bit
`timescale 1 ns / 100 ps
module alu_1_bit (A, B, CIN, LESS, AINV, BINV, Opr, RESULT, COUT, ADD_R);
input A, B, CIN, LESS, AINV, BINV;
input [1:0] Opr;
output RESULT, ADD_R, COUT;
reg RESULT, COUT, ADD_R;
always @(*) // same as always @(A, B, Ainv, Binv, CIN, Opr, LESS)
begin : combinational_logic // named procedural block
// local declarations in the named procedural block
reg RESULT_AND, RESULT_OR, RESULT_ADD_SUB, RESULT_SLT;
reg Am, Bm; // Am is the A at the output of the mux controlled by AINV; Similarly Bm
Am = AINV ? ~A : A; // fill-in ~A : A or A : ~A
Bm = BINV ? ~B : B; // fill-in ~B : B or B : ~B
// fill-in the following lines using Am, Bm, CIN
RESULT_AND = Am & Bm;
RESULT_OR = Am | Bm;
ADD_R = Am ^ Bm ^ CIN;
RESULT_ADD_SUB = ADD_R;
RESULT_SLT = LESS;
COUT = (Am & Bm) | (Am & CIN) | (Bm & CIN);
case (Opr)
0 : // 2'b00 Logical AND Function
begin
RESULT = RESULT_AND;
end
1 : // 2'b01 Logical OR Function
begin
RESULT = RESULT_OR;
end
2 : // 2'b10 Arithmatic addition or subtract depending on the value of BINV
begin
RESULT = RESULT_ADD_SUB;
end
3 : // 2'b11 for the SLT A, B instruction ( if A < B, RESULT =1)
begin
RESULT = RESULT_SLT;
end
endcase
end
endmodule
| 8.772217 |
module alu_4_bit (
A,
B,
AINV,
BNEG,
Opr,
RESULT,
OVERFLOW,
ZERO,
COUT
);
input [3:0] A, B;
input AINV, BNEG;
input [1:0] Opr;
output [3:0] RESULT;
output OVERFLOW, ZERO, COUT;
//LOCAL SIGNALS;
wire COUT1, COUT2, COUT3, COUT4;
wire BINV, SET, LESS_0;
wire [3:0] ADD_R;
assign BINV = BNEG;
assign CIN = BNEG;
assign COUT = COUT4;
assign OVERFLOW = COUT3 ^ COUT4; // fill-in this line
assign SET = ADD_R[3];
assign LESS_0 = OVERFLOW ? ~SET : SET; // fill-in this line
assign ZERO = ~( (RESULT[0]) | (RESULT[1]) | (RESULT[2]) | (RESULT[3]) ); // correct this line !!!! *****
// instantiate the alu_1_bit. Follow the order carefully if you are using positional association (positional mapping)
// module alu_1_bit (A, B, CIN, LESS, AINV, BINV, Opr, RESULT, COUT, ADD_R);
alu_1_bit alu0 (
A[0],
B[0],
CIN,
LESS_0,
AINV,
BINV,
Opr,
RESULT[0],
COUT1,
ADD_R[1]
); // fill-in this line
alu_1_bit alu1 (
A[1],
B[1],
COUT1,
1'b0,
AINV,
BINV,
Opr,
RESULT[1],
COUT2,
ADD_R[1]
);
alu_1_bit alu2 (
A[2],
B[2],
COUT2,
1'b0,
AINV,
BINV,
Opr,
RESULT[2],
COUT3,
ADD_R[2]
);
alu_1_bit alu3 (
A[3],
B[3],
COUT3,
1'b0,
AINV,
BINV,
Opr,
RESULT[3],
COUT4,
ADD_R[3]
);
endmodule
| 7.806442 |
module for use as the most-significant
// 4 bits of the 16-bit ALU.
module alu_4_bit_last(result, overflow, set, zero, c_out, a, b, c_in, op);
input [3:0] a;
input [3:0] b;
input c_in;
input [2:0] op;
output [3:0] result;
output overflow, set, zero, c_out;
wire p, q, r, s, t;
alu_1_bit alu_0(result[0], p, a[0], b[0], 0, c_in, op),
alu_1(result[1], q, a[1], b[1], 0, p, op),
alu_2(result[2], r, a[2], b[2], 0, q, op);
alu_1_bit_msb alu_3(result[3], overflow, set, c_out, a[3], b[3], 0, r, op);
or g1(s, result[0], result[1]),
g2(t, result[2], result[3]);
nor g3(zero, s, t);
endmodule
| 7.198888 |
module alu_4_bit_tb;
reg [3:0] A_tb, B_tb;
reg AINV_tb, BNEG_tb;
reg [1:0] Opr_tb;
wire [3:0] RESULT_tb;
wire OVERFLOW_tb, ZERO_tb, COUT_tb;
integer test_num;
integer file_results; // file_results is a logical name for the physical file alu_output_results.txt here.
// module alu_4_bit (A, B, AINV, BNEG, Opr, RESULT, OVERFLOW, ZERO, COUT);
alu_4_bit alu_4 (
A_tb,
B_tb,
AINV_tb,
BNEG_tb,
Opr_tb, // CIN_tb, LESS_tb,
RESULT_tb,
OVERFLOW_tb,
ZERO_tb,
COUT_tb
);
task TEST_ALU;
input [3:0] A_value, B_value;
input AINV_value, BNEG_value;
input [1:0] Opr_value;
reg [16*8:1] Opr_string_tb;
begin
A_tb = A_value;
B_tb = B_value;
AINV_tb = AINV_value;
BNEG_tb = BNEG_value;
Opr_tb = Opr_value;
test_num = test_num + 1;
case (Opr_value)
0:
if (AINV_value && BNEG_value) Opr_string_tb = "NOR operation";
else if (!(AINV_value || BNEG_value)) Opr_string_tb = "AND operation";
else Opr_string_tb = "UNK operation"; // unknown operation
1:
if (AINV_value && BNEG_value) Opr_string_tb = "NAND operation";
else if (!(AINV_value || BNEG_value)) Opr_string_tb = " OR operation";
else Opr_string_tb = "UNK operation"; // unknown operation
2:
if ((~AINV_value) && BNEG_value) Opr_string_tb = "SUB operation";
else if (!(AINV_value || BNEG_value)) Opr_string_tb = "ADD operation";
else Opr_string_tb = "UNK operation"; // unknown operation
3:
if ((~AINV_value) && BNEG_value) Opr_string_tb = "SLT operation";
else Opr_string_tb = "UNK operation"; // unknown operation
endcase
#1; // wait for a little while for all delta_T delays to pass before reporting the results
// output to console
$display("Test # = %0d ", test_num);
$display("Inputs: A = %b and B = %b AINV = %b BNEG = %b", A_tb, B_tb, AINV_tb, BNEG_tb);
$display("Opr = %h %s RESULT = %b ", Opr_tb, Opr_string_tb, RESULT_tb);
$display(" COUT = %b OVERFLOW = %b ZERO = %b ", COUT_tb, OVERFLOW_tb,
ZERO_tb);
$display(" ");
// output to file
$fdisplay(file_results, "Test # = %0d ", test_num);
$fdisplay(file_results, "Inputs: A = %b and B = %b AINV = %b BNEG = %b", A_tb, B_tb,
AINV_tb, BNEG_tb);
$fdisplay(file_results, "Opr = %h %s RESULT = %b ", Opr_tb, Opr_string_tb, RESULT_tb);
$fdisplay(file_results, " COUT = %b OVERFLOW = %b ZERO = %b ", COUT_tb,
OVERFLOW_tb, ZERO_tb);
$fdisplay(file_results, " ");
#19; // wait for a total of 20 ns (1 + 19 = 20ns) before applying next set of stimulai to the combinational logic
end
endtask
initial begin : STIMULUS
file_results = $fopen("alu_output_results.txt", "w");
test_num = 0;
// test #1 begin
TEST_ALU(11, 7, 0, 0, 0); // (A,B,AINV,BNEG,Opr) AND
// test #1 end
// test #2 begin
TEST_ALU(11, 7, 0, 0, 1); // (A,B,AINV,BNEG,Opr) OR
// test #2 end
// test #3 begin
TEST_ALU(11, 7, 0, 0, 2); // (A,B,AINV,BNEG,Opr) ADD
// test #3 end
// test #4 begin
TEST_ALU(11, 7, 0, 1, 2); // (A,B,AINV,BNEG,Opr) SUB
// test #4 end
// test #5 begin
TEST_ALU(11, 7, 0, 1, 3); // (A,B,AINV,BNEG,Opr) SLT
// test #5 end
// test #6 begin
TEST_ALU(4, 7, 0, 1, 3); // (A,B,AINV,BNEG,Opr) SLT
// test #6 end
// test #7 begin
TEST_ALU(7, 4, 0, 1, 3); // (A,B,AINV,BNEG,Opr) SLT
// test #7 end
// test #8 begin
TEST_ALU(11, 12, 0, 1, 3); // (A,B,AINV,BNEG,Opr) SLT
// test #8 end
// test #9 begin
TEST_ALU(11, 10, 0, 1, 3); // (A,B,AINV,BNEG,Opr) SLT
// test #9 end
// test #10 begin
TEST_ALU(11, 7, 1, 1, 0); // (A,B,AINV,BNEG,Opr) NOR
// test #10 end
$display("All tests concluded!");
$fdisplay(file_results, "All tests concluded!");
$fclose(file_results);
end // STIMULUS
endmodule
| 7.342503 |
module decoder (
input en,
input [1:0] sel,
output reg ea,
eb,
ef
);
always @(*) begin
if (en) begin
case (sel)
2'b00: begin
ea = 1'b1;
eb = 1'b0;
ef = 1'b0;
end
2'b01: begin
ea = 1'b0;
eb = 1'b1;
ef = 1'b0;
end
2'b10: begin
ea = 1'b0;
eb = 1'b0;
ef = 1'b1;
end
default: begin
ea = 1'b0;
eb = 1'b0;
ef = 1'b0;
end
endcase
end else begin
ea = 1'b0;
eb = 1'b0;
ef = 1'b0;
end
end
endmodule
| 7.018254 |
module alu_6 #(
parameter ADD_6 = 3'b000,
parameter SUB_6 = 3'b001,
parameter AND_6 = 3'b010,
parameter OR_6 = 3'b011,
parameter XOR_6 = 3'b100
) (
input clk,
input en,
input [1:0] sel,
input [5:0] x,
output reg [5:0] y,
output reg z
);
reg [2:0] fr;
reg [5:0] ar;
reg [5:0] br;
wire ea;
wire eb;
wire ef;
reg [5:0] yout;
reg zout;
decoder decoder (
en,
sel,
ea,
eb,
ef
);
always @(posedge clk) begin
if (ea) ar <= x;
else if (eb) br <= x;
else if (ef) fr <= x[2:0];
else begin
ar <= ar;
br <= br;
fr <= fr;
end
end
always @(*) begin
case (fr)
ADD_6: y = ar + br;
SUB_6: y = ar - br;
AND_6: y = ar & br;
OR_6: y = ar | br;
XOR_6: y = ar ^ br;
default: y = 6'b0;
endcase
end
always @(*) begin
if (y == 6'b0) z = 1'b1;
else z = 1'b0;
end
always @(posedge clk) begin
yout <= y;
zout <= z;
end
endmodule
| 6.762562 |
module ALU_64 (
A,
B,
ALU_Opcode,
ALU_Out,
Z
);
parameter BITSIZE = 32;
parameter REGSIZE = 64;
input [REGSIZE-1:0] A, B; // ALU 64-bit Inputs
input [2:0] ALU_Opcode; // ALU Selection
output reg [REGSIZE-1:0] ALU_Out; // ALU 64-bit Output
output Z;
/*wire ReadData2;
Register_File uut4( .ReadData1(A),
.ReadData2(ReadData2));
MUX_2_1 uut5(.in0(ReadData2),
.in1(SignExtendOut), ///from sign extend
.s0(ALUSrc), /////from control signal
.out(B)
);
*/
always @(*) begin
case (ALU_Opcode)
3'b000: begin
ALU_Out <= A & B;
end
3'b001: // Logical or
begin
ALU_Out <= A | B;
end
3'b010: begin
ALU_Out <= ~A;
end
3'b011: //move A
begin
ALU_Out <= A;
end
3'b100: // move B
begin
ALU_Out <= B;
end
3'b101: //add
begin
ALU_Out <= A + B;
end
3'b110: //subtract
begin
ALU_Out <= A - B;
end
3'b111: // MOVK
begin
ALU_Out <= {A[63:16], B[15:0]}; //a b exchange
end
endcase
end
assign Z = (ALU_Out == 0) ? 0 : 1;
endmodule
| 8.750207 |
module ALU_64_bit (
a,
b,
ALUOp,
Zero,
Result,
Pos
);
input [63:0] a;
input [63:0] b;
input [3:0] ALUOp;
output reg Zero;
output reg [63:0] Result;
output reg Pos;
always @(*) begin
if (ALUOp == 4'b0000) begin
Result = a & b;
end else if (ALUOp == 4'b0001) begin
Result = a | b;
end else if (ALUOp == 4'b0010) begin
Result = a + b;
end else if (ALUOp == 4'b0110) begin
Result = a - b;
end else if (ALUOp == 4'b1100) begin
Result = ~(a | b);
end
if (Result == 0) Zero = 1;
else Zero = 0;
Pos <= ~Result[63];
end
endmodule
| 6.840274 |
module alu_8 (
input clk,
input rst,
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out
);
reg [ 15:0] actual_output;
reg [ 15:0] temp_a;
reg [ 15:0] temp_b;
wire [16-1:0] M_alu_adder_s;
wire [ 1-1:0] M_alu_adder_cout;
wire [ 1-1:0] M_alu_adder_z;
wire [ 1-1:0] M_alu_adder_n;
wire [ 1-1:0] M_alu_adder_v;
reg [16-1:0] M_alu_adder_x;
reg [16-1:0] M_alu_adder_y;
reg [ 1-1:0] M_alu_adder_cin;
sixteen_bit_adder_23 alu_adder (
.x(M_alu_adder_x),
.y(M_alu_adder_y),
.cin(M_alu_adder_cin),
.s(M_alu_adder_s),
.cout(M_alu_adder_cout),
.z(M_alu_adder_z),
.n(M_alu_adder_n),
.v(M_alu_adder_v)
);
wire [16-1:0] M_alu_boole_out;
reg [16-1:0] M_alu_boole_a;
reg [16-1:0] M_alu_boole_b;
reg [ 4-1:0] M_alu_boole_alufn;
sixteen_bit_boolean_24 alu_boole (
.a(M_alu_boole_a),
.b(M_alu_boole_b),
.alufn(M_alu_boole_alufn),
.out(M_alu_boole_out)
);
wire [1-1:0] M_alu_cmp_out;
reg [1-1:0] M_alu_cmp_z;
reg [1-1:0] M_alu_cmp_n;
reg [1-1:0] M_alu_cmp_v;
reg [2-1:0] M_alu_cmp_alufn;
comparator_25 alu_cmp (
.z(M_alu_cmp_z),
.n(M_alu_cmp_n),
.v(M_alu_cmp_v),
.alufn(M_alu_cmp_alufn),
.out(M_alu_cmp_out)
);
wire [16-1:0] M_alu_shift_s;
reg [ 6-1:0] M_alu_shift_alufn;
reg [16-1:0] M_alu_shift_a;
reg [16-1:0] M_alu_shift_b;
shifter_26 alu_shift (
.alufn(M_alu_shift_alufn),
.a(M_alu_shift_a),
.b(M_alu_shift_b),
.s(M_alu_shift_s)
);
wire [16-1:0] M_alu_mul_out;
reg [16-1:0] M_alu_mul_a;
reg [16-1:0] M_alu_mul_b;
multiplier_27 alu_mul (
.a (M_alu_mul_a),
.b (M_alu_mul_b),
.out(M_alu_mul_out)
);
always @* begin
M_alu_adder_x = 1'h0;
M_alu_adder_y = 1'h0;
M_alu_adder_cin = 1'h0;
M_alu_boole_a = 1'h0;
M_alu_boole_b = 1'h0;
M_alu_boole_alufn = 1'h0;
M_alu_cmp_v = 1'h0;
M_alu_cmp_z = 1'h0;
M_alu_cmp_n = 1'h0;
M_alu_cmp_alufn = 1'h0;
M_alu_shift_a = 1'h0;
M_alu_shift_b = 1'h0;
M_alu_shift_alufn = 1'h0;
M_alu_mul_a = 1'h0;
M_alu_mul_b = 1'h0;
actual_output = 16'h0000;
case (alufn[4+1-:2])
2'h0: begin
if (alufn[1+2-:3] == 3'h0) begin
M_alu_adder_x = a;
M_alu_adder_y = b;
M_alu_adder_cin = alufn[0+0-:1];
actual_output = M_alu_adder_s;
end else begin
if (alufn[0+3-:4] == 4'h2) begin
M_alu_mul_a = a;
M_alu_mul_b = b;
actual_output = M_alu_mul_out;
end else begin
if (alufn[0+3-:4] == 4'h3) begin
temp_a = a ^ b;
temp_b = a & b;
actual_output = temp_a <= temp_b && a != 1'h0;
end
end
end
end
2'h1: begin
if (alufn[0+3-:4] == 4'ha || alufn[0+3-:4] == 4'h6 || alufn[0+3-:4] == 4'he || alufn[0+3-:4] == 4'h8 || alufn[0+3-:4] == 4'h5 || alufn[0+3-:4] == 4'hc || alufn[0+3-:4] == 4'h3 || alufn[0+3-:4] == 4'h7 || alufn[0+3-:4] == 4'h1 || alufn[0+3-:4] == 4'h9) begin
M_alu_boole_a = a;
M_alu_boole_b = b;
M_alu_boole_alufn = alufn[0+3-:4];
actual_output = M_alu_boole_out;
end
end
2'h2: begin
if (alufn[2+1-:2] == 2'h0 && alufn[0+1-:2] != 2'h2) begin
M_alu_shift_a = a;
M_alu_shift_b = b;
M_alu_shift_alufn = alufn;
actual_output = M_alu_shift_s;
end
end
2'h3: begin
if (alufn[0+3-:4] == 4'h3 || alufn[0+3-:4] == 4'h5 || alufn[0+3-:4] == 4'h7) begin
M_alu_adder_x = a;
M_alu_adder_y = b;
M_alu_adder_cin = alufn[0+0-:1];
M_alu_cmp_z = M_alu_adder_z;
M_alu_cmp_v = M_alu_adder_v;
M_alu_cmp_n = M_alu_adder_n;
M_alu_cmp_alufn = alufn[1+1-:2];
actual_output = M_alu_cmp_out;
end
end
endcase
out = actual_output;
end
endmodule
| 6.508885 |
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