code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module aluGTK;
wire [31:0] busOut;
wire zero, overflow, carry, neg;
wire [31:0] busA, busB;
wire [2:0] control;
//declare instances of dut and tester modules
alu_behav myalu (
busOut,
zero,
overflow,
carry,
neg,
busA,
busB,
control
);
Tester aTester (
... | 6.614873 |
module ALUInputAdapter #(
parameter DATA_BITS = 32
) (
// data lines in
input wire [DATA_BITS - 1:0] RegOut1,
input wire [DATA_BITS - 1:0] RegOut2,
input wire [ 15:0] Immediate,
input wire [ 4:0] ShamtIn,
// signals in
input wire AluSrcB, //... | 7.146599 |
module ALUio (
output [31:0] result,
output N,
Zero,
C,
V,
input [31:0] A,
B,
input MuxD0,
Clk,
Load,
carry,
input [4:0] sel_alu,
sel_cu
);
wire [4:0] sel;
MUX2x1_5bits2 MuxD (
MuxD0,
sel_alu,
sel_cu,
sel
);
ALU alu (
result,
... | 7.014327 |
module ALUJump_tb;
reg [7:0] inPc;
reg [7:0] ini;
wire [7:0] out;
ALUJump pcALU (
inPc,
ini,
out
);
initial begin
//$dumpfile ("testbench/acOut_tb.vcd");
//$dumpvars(0, acOut_tb);
$monitor("PC = %d, Imediate = %d, Final Addr = %d", inPc, ini, out);
inPc = 8'b00000... | 7.077617 |
module ALUM2DR (
clk,
DataIn,
DataOut
);
input clk;
input [31:0] DataIn;
output reg [31:0] DataOut;
always @(posedge clk) begin
#0.002;
DataOut = DataIn;
end
endmodule
| 6.94159 |
module ALUMatrixTop (
clk,
reset,
eleSel,
sel,
eleIn,
eleOut,
LED
);
input clk, reset;
input [4:0] eleSel;
input [5:0] sel;
input [31:0] eleIn;
output [31:0] eleOut;
output [15:0] LED;
ALUCalc zero (
.clk(clk),
.reset(reset),
.eleSel(eleSel),
.sel(sel)... | 6.562062 |
module clock_divider (
clk_out,
clk_in,
slowDown
);
output clk_out;
reg [31:0] divided_clocks;
input clk_in, slowDown;
//Choose clock frequency for signal tap display or LED display
assign clk_out = slowDown ? divided_clocks[1] : clk_in;
initial divided_clocks = 0;
always @(posedge clk_in) ... | 6.818038 |
module AluMisc (
////////////
// INPUTS //
////////////
input clock,
input reset,
input iss_am_oper, // Enables this funcional unit (mutually exclusive
// regarding the other two main functional units'
// signals)
// Whether to save the AL... | 8.256437 |
module AluMisc_TB0;
reg clock;
reg reset;
reg oper;
reg [31:0] op_a;
reg [31:0] op_b;
reg [31:0] imm;
reg [2:0] aluop;
reg imm_or_reg;
wire [4:0] am_wb_regdest;
wire am_wb_writereg;
wire [31:0] res;
wire oper_out;
AluMisc ALUMISC (
.clock(clock),
.reset(reset),
.iss_am_... | 6.764446 |
module ALUMux (
input [63:0] registerData,
input [63:0] signExtendedData,
input ALUsrc,
output reg [63:0] ALUMUXout
);
always @(*)
case (ALUsrc)
0: ALUMUXout = registerData;
1: ALUMUXout = signExtendedData;
default: ALUMUXout = registerData;
endcase
endmodule
| 7.766766 |
module ALUmux4to1 (
input logic [31:0] register_b,
input logic [15:0] immediate,
input logic [ 5:0] opcode,
input logic [ 1:0] ALUSrcB,
output logic [31:0] ALUB
);
logic [31:0] sign_extended;
logic [31:0] shift_2;
typedef enum logic [5:0] {
LUI = 6'b001111,
ANDI = 6'b001100,
... | 6.652348 |
module ALU (
Out,
A,
B,
ALUFun,
Sign
);
input [31:0] A, B;
input [5:0] ALUFun;
input Sign;
output reg [31:0] Out;
wire Z, V, N;
wire [31:0] Out1, Out2, Out3, Out4;
ARITH ari (
ALUFun[0],
A,
B,
Sign,
Z,
V,
N,
Out1
);
LOGIC log (
... | 8.102762 |
module CMP (
FUNC,
Z,
V,
N,
Out
);
input [2:0] FUNC;
input Z, V, N;
output reg [31:0] Out;
always @* begin
Out[31:0] = 32'h00000000;
case (FUNC)
3'b001: Out[0] <= Z;
3'b000: Out[0] <= ~Z;
3'b010: Out[0] <= N;
3'b110: Out[0] <= (Z || N);
3'b101: Out[... | 9.397321 |
module ARITH (
FUNC,
A,
B,
S,
Z,
V,
N,
Out
);
input [31:0] A, B;
input FUNC;
input S;
output Z;
output reg V, N;
output reg [31:0] Out;
reg [31:0] C;
assign Z = (Out == 0);
always @* begin
if (FUNC == 0) begin
if (S == 1) begin
Out = A + B;
if ... | 6.664095 |
module LOGIC (
FUNC,
A,
B,
Z
);
input [3:0] FUNC;
input [31:0] A, B;
output reg [31:0] Z;
always @* begin
case (FUNC)
4'b1000: Z = A & B;
4'b1110: Z = A | B;
4'b0110: Z = A ^ B;
4'b0001: Z = ~(A | B);
4'b1010: Z = A;
default: Z = 32'h00000000;
endcase
... | 7.902914 |
module ALUnFlag (
input [15:0] A,
B,
input [2:0] op,
input [3:0] imm,
input clk,
rst,
modify,
output [2:0] outFlag
); //Z V N
wire [2:0] ALUFlag;
ALU alu (
.A(A),
.B(B),
.op(op),
.imm(imm),
.Flag(ALUFlag)
);
FlagRegister FR (
.clk(clk),
... | 7.045403 |
module aluop_selector #(
parameter CURRENTPC = 1'b0,
parameter RD1 = 1'b1,
parameter EXT = 1'b0,
parameter RD2 = 1'b1
) (
input op_A_sel_i,
input op_B_sel_i,
input [31:0] current_pc_i,
input [31:0] rD1_i,
input [31:0] rD2_i,
... | 7.915518 |
module ALUoutDR (
input CLK,
input [31:0] DataIn,
output reg [31:0] DataOut
);
always @(negedge CLK) DataOut <= DataIn;
endmodule
| 6.750416 |
module ALUOut_module (
clk,
ALUOut_in,
ALUOut_out
);
input clk;
input [31:0] ALUOut_in;
output [31:0] ALUOut_out;
reg [31:0] ALUOut_out;
always @(clk) ALUOut_out <= ALUOut_in;
endmodule
| 6.830488 |
module ALUOut_reg (
ALUOut_in,
ALUOut_reg,
reset,
clk
);
input [31:0] ALUOut_in;
input reset, clk;
output reg [31:0] ALUOut_reg;
always @(posedge clk) begin
if (reset) begin
ALUOut_reg <= 32'd0;
end else begin
ALUOut_reg <= ALUOut_in;
end
end
endmodule
| 7.157747 |
module ALUPC ( //Summation of PC and 1
clock,
inPC,
out
);
input clock;
input [7:0] inPC;
output reg [7:0] out;
always @(posedge clock) out = inPC + 1;
endmodule
| 6.502121 |
module ALUPC_tb;
reg [7:0] currAddr;
wire [7:0] nextAddr;
ALUPC pcALU (
currAddr,
nextAddr
);
initial begin
//$dumpfile ("testbench/acOut_tb.vcd");
//$dumpvars(0, acOut_tb);
$monitor("New Address = %d, Current Address = %d", nextAddr, currAddr);
currAddr = 8'b00000001;
... | 6.53211 |
module ALUposk (
CLK,
RST,
frac,
exp,
nguyen,
le,
lt
);
input CLK, RST;
input [22:0] frac;
input [8:0] exp;
output [19:0] le;
output [4:0] nguyen;
output [8:0] lt;
wire [31:0] number1, temp_result, number2;
wire [27:0] frac1;
wire [8:0] _2k, _3k, exp_temp, exp_out, temp_... | 6.561404 |
module RegisterFile (
rd1,
rd2,
rr1,
rr2,
wr,
wd,
we,
clk
);
output reg [31:0] rd1, rd2;
input [4:0] rr1, rr2, wr;
input we, clk;
input [31:0] wd;
reg [31:0] rf[7:0];
always @(posedge clk) begin
if (we) begin
rf[wr] <= wd;
end
rd1 = rf[rr1];
rd2 = rf[... | 8.108491 |
module alureg(input wire clk, reset, wr, opmux2, cin, input wire[3:0]op, input wire[2:0] rd_addr_a, rd_addr_b, wr_addr,op1, input wire[1:0]op2, input wire[15:0] d, output wire[15:0] o, ouput wire coutf);
wire[15:0] d_out_a;
wire[15:0] d_out_b;
reg_file f1(clk, reset, wr, opmux2, rd_addr_a, rd_addr_b, wr_addr, d, d_o... | 7.406026 |
module alu_rf_32 (
input wire clock,
// Register File Knobs
input wire write_enabled,
input wire [4:0] read_addr_s,
input wire [4:0] read_addr_t,
input wire [4:0] write_addr,
// ALU Knob
input wire [3:0] control,
// ALU Outputs
output wire cout,
output... | 6.93197 |
module aluReg (
clk,
alu_res,
aluReg_out,
overflow,
overflowReg
);
input clk;
input [31:0] alu_res;
input overflow;
output reg [31:0] aluReg_out;
output reg overflowReg;
always @(posedge clk) begin
aluReg_out <= alu_res;
overflowReg <= overflow;
end
endmodule
| 6.947866 |
module nxtPosCal (
input wire enWrtO,
input wire [`TagBus] WrtTagO,
input wire [`DataBus] WrtDataO,
input wire enWrtT,
input wire [`TagBus] WrtTagT,
input wire [`DataBus] WrtDataT,
input wire [`DataBus] dataNow,
input wire [ `TagBus] tagNow,
output wire [`DataBus] dataNxtPos,
o... | 8.272042 |
module RsLine (
input clk,
input rst,
input rdy,
//
input wire enWrtO,
input wire [ `TagBus] WrtTagO,
input wire [ `DataBus] WrtDataO,
input wire enWrtT,
input wire [ ... | 7.818872 |
module ALUSelA (
code,
alu_sel_a,
insn
);
input [9:0] code;
input [31:0] insn;
output alu_sel_a;
wire W1;
// Assign com expressão derivada da função
assign W1 = (~code[9] & ~code[8] & ~code[7] & ~code[6] & ~code[5] & ~code[4] & ~code[3] & ~code[2] & ~code[1] & code[0]) | (~code[9] & ~code[8] & ... | 6.944147 |
module ALUSelector (
input ALUSrcB,
input [31:0] out2,
input [31:0] extendOut,
output wire [31:0] ALUSelectorOut
);
// ALUSrcBΪ0ʱʾALUB˿ڽԼĴdata2Ϊ1ʱʾsignzeroչ
assign ALUSelectorOut = ALUSrcB ? extendOut : out2;
endmodule
| 6.652188 |
module ALUSimple (
input clock,
input reset,
input [ 3:0] io_operation,
input [31:0] io_inputx,
input [31:0] io_inputy,
output [31:0] io_result
);
wire [31:0] _T_1 = io_inputx & io_inputy;
wire [31:0] _T_3 = io_inputx | io_inputy;
wire [31:0] _T_6 = io_inputx + io_inputy... | 7.00578 |
module ALUSrc (
PR2,
ALUSrc_Out
);
input [499:0] PR2;
wire [63:0] Data2_3;
wire [63:0] SEout3;
reg [63:0] In0;
reg [63:0] In1;
wire ALUSrc3;
output reg [63:0] ALUSrc_Out;
assign ALUSrc3 = PR2[96];
assign SEout3 = PR2[295:232];
assign Data2_3 = PR2[231:168];
always @* begin
case (ALU... | 7.574005 |
module contains 1 control signal, ALUSrc, if it is deasserted, it will
* take data from register file as the operand; if it is asserted, it will
* take data from immediate number as the operand.
* code | meaning
* 00 | takes operand from register
* 01 | takes operand from immediate number
* 10 | takes operand fro... | 6.799318 |
module alusrc_mux (
rd_data2,
sd_imm,
addi_imm,
ALUSrc,
sd,
alu_in2
);
input [63:0] rd_data2, sd_imm, addi_imm;
input ALUSrc, sd;
output [63:0] alu_in2;
assign alu_in2 = ALUSrc ? ((sd) ? sd_imm : addi_imm) : rd_data2;
endmodule
| 7.460633 |
module ALUSrc_selector #(
parameter W = 32
) (
input [W-1:0] i_instruction,
input [W-1:0] i_rs,
input [W-1:0] i_rt,
input [W-1:0] i_forwarded_data,
input i_rs_forward_signal,
input i_rt_forward_signal,
output reg [W-1:0] o_alu_oprand1,
ou... | 8.650255 |
module mux2to1 (
input [31:0] A,
B,
input sel,
output [31:0] out
);
assign out = (sel == 0) ? A : B;
endmodule
| 7.107199 |
module ALU_main (
input [31:0] RF_A,
input [31:0] RF_B,
input [31:0] Immed,
input ALU_Bin_sel,
input [3:0] ALU_func,
output [31:0] ALU_out,
output Zero
);
wire [31:0] mux_out;
mux2to1 mux (
.A (RF_B),
.B (Immed),
.sel(ALU_Bin_sel),
.out(mux_out)
);
ALU alu ... | 8.028381 |
module: alu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALUtb;
// Inputs
reg [31:0] A;
reg [31:0] B;
reg [2:0] ALUOp;
// Outputs
wire [31:0] C;
// Instantiate the Unit ... | 7.023594 |
module ALUTestVectorTestbench ();
parameter Halfcycle = 5; //half period is 5ns
localparam Cycle = 2 * Halfcycle;
reg Clock;
// Clock Signal generation:
initial Clock = 0;
always #(Halfcycle) Clock = ~Clock;
// Wires to test the ALU
// These are read from the input vector
reg [6:0] opcode;
reg... | 6.646929 |
module: alu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alutest;
// Inputs
reg [3:0] A;
reg [3:0] B;
reg [1:0] Opcode;
// Outputs
wire [3:0] C;
wire [4:0] Flags;
integ... | 7.023594 |
module ALUtoDM_addr (
ALUout,
addr
);
input [31:0] ALUout;
output [13:0] addr;
assign addr = {ALUout[13:0]};
endmodule
| 7.177681 |
module ALUtoMEM_REG (
input clk,
input rstn,
input [31:0] i_ALUResult_32,
output [31:0] o_ALUResult_32,
input i_Load_1,
input i_Store_1,
input i_LoadUnsigned_1,
input [ 1:0] i_LoadStoreWidth_2,
input [31:0] i_StoreData_32,
input [ 4:0] i_GRFWriteAddr_5,
... | 7.832463 |
module alut_mem (
// Inputs
pclk,
mem_addr_add,
mem_write_add,
mem_write_data_add,
mem_addr_age,
mem_write_age,
mem_write_data_age,
mem_read_data_add,
mem_read_data_age
);
parameter DW = 83; // width of data busses
parameter DD = 256; // depth of RAM
input pclk; // AP... | 6.936293 |
module alut_veneer (
// Inputs
pclk,
n_p_reset,
psel,
penable,
pwrite,
paddr,
pwdata,
// Outputs
prdata
);
// APB Inputs
input pclk; // APB clock
input n_p_reset; // Reset
input psel; // Module select signal ... | 7.24936 |
module ALUusr (
input wire [15:0] x, // input x (16 bit)
input wire [15:0] y, // input y (16 bit)
input wire zx, // zero the x input?
input wire nx, // negate the x input?
input wire zy, // zero the y input?
input wire ny, // negate the y input?
... | 7.655842 |
module ALUV (
a,
b,
sel,
c
);
input [15:0] a, b;
input [3:0] sel;
output [15:0] c;
reg [15:0] c;
parameter alupass = 0,
andOp = 1,
orOp = 2,
notOp = 3,
xorOp = 4,
plus = 5,
alusub = 6,
inc = 7,
dec = 8,
zero = 9;
alway... | 7.814237 |
module alu (
a,
b,
s,
y
);
input [3:0] a;
input [3:0] b;
input [2:0] s;
output [7:0] y;
reg [7:0] y;
always @(a, b, s) begin
case (s)
3'b000: y = a + b;
3'b001: y = a - b;
3'b010: y = a & b;
3'b011: y = a | b;
3'b100: y = 4'b1111 ^ a;
3'b101: y = (4'b... | 6.634214 |
module: ALUwithControl
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALUwithControlTester;
// Inputs
reg [1:0] ALUOp;
reg [10:0] OpcodeField;
reg ALUoperation;
// Instantiat... | 6.625934 |
module alux64 (
input [63:0] a,
input [63:0] b,
input [3:0] aluop,
output reg Zero,
output reg [63:0] aluout
);
always @(*) begin
case (aluop)
4'b0000: aluout = a & b;
4'b0001: aluout = a | b;
4'b0010: aluout = a + b;
4'b0110: aluout = a - b;
4'b1100: aluout =... | 6.645124 |
module alu_11 (
input [5:0] alufn,
input [15:0] a,
input [15:0] b,
output reg [15:0] out,
output reg z,
output reg v,
output reg n
);
wire [16-1:0] M_adder__out;
wire [ 1-1:0] M_adder__z;
wire [ 1-1:0] M_adder__v;
wire [ 1-1:0] M_adder__n;
reg [ 6-1:0] M_adder__alufn;
reg [1... | 6.804463 |
module alu_13 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn_signal,
output reg [15:0] alu,
output reg z,
output reg v,
output reg n
);
wire [16-1:0] M_adder1_out;
wire [ 1-1:0] M_adder1_z;
wire [ 1-1:0] M_adder1_v;
wire [ 1-1:0] M_adder1_n;
reg [16-1:0] M_adder1_a;
reg ... | 6.727174 |
module add (
in1,
in2,
out
);
input [15:0] in1, in2;
output [15:0] out;
assign out = in1 + in2;
endmodule
| 7.493514 |
module sub (
in1,
in2,
out
);
input [15:0] in1, in2;
output [15:0] out;
assign out = in1 - in2;
endmodule
| 7.353783 |
module mul (
in1,
in2,
out
);
input [15:0] in1, in2;
output [15:0] out;
assign out = in1 * in2;
endmodule
| 7.969753 |
module div (
in1,
in2,
out
);
input [15:0] in1, in2;
output [15:0] out;
assign out = in1 / in2;
endmodule
| 8.452409 |
module mux41 (
in1,
in2,
in3,
in4,
sel,
out
);
input [15:0] in1, in2, in3, in4;
input [1:0] sel;
output [15:0] out;
assign out = sel[1] ? (sel[0] ? in4 : in3) : (sel[0] ? in2 : in1);
endmodule
| 7.514523 |
module alu_16 (
inp1,
inp2,
sel,
out
);
input [15:0] inp1, inp2;
input [1:0] sel;
output [15:0] out;
wire [15:0] out1, out2, out3, out4;
add n1 (
inp1,
inp2,
out1
);
sub n2 (
inp1,
inp2,
out2
);
mul n3 (
inp1,
inp2,
out3
);
di... | 6.735691 |
module ALU_16bit_t;
reg Cin_t;
reg [15:0] A_t, B_t;
reg [4:0] FS_t;
wire Cout_t;
wire [15:0] F_t;
integer i;
integer FE; //F expected
ALU_16bit_v dut (
.Cin(Cin_t),
.A(A_t),
.B(B_t),
.FS(FS_t),
.Cout(Cout_t),
.F(F_t)
);
initial begin
repeat (10) begin
... | 7.282368 |
module alu_16bit_tb;
//Inputs
reg [15:0] A, B;
reg [3:0] ALU_Sel;
reg M, cin;
//outputs
wire Cn4, equality_check, P, G;
wire [15:0] F;
// Verilog code for ALU
alu_16bit test_unit (
A,
B, // ALU 8-bit Inputs
ALU_Sel, // ALU Selection
M,
cin,
Cn4,
... | 7.277312 |
module alu_16_6 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out,
output reg [0:0] z,
output reg [0:0] v,
output reg [0:0] n
);
wire [16-1:0] M_adder_out;
wire [ 1-1:0] M_adder_z;
wire [ 1-1:0] M_adder_v;
wire [ 1-1:0] M_adder_n;
reg [16-1:0] M_adder_a... | 6.619657 |
module alu_16_7 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out,
output reg [0:0] z,
output reg [0:0] v,
output reg [0:0] n
);
wire [16-1:0] M_adder_out;
wire [ 1-1:0] M_adder_z;
wire [ 1-1:0] M_adder_v;
wire [ 1-1:0] M_adder_n;
reg [16-1:0] M_adder_a... | 6.964163 |
module alu_16_9 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out,
output reg [0:0] z,
output reg [0:0] v,
output reg [0:0] n
);
wire [16-1:0] M_adder_out;
wire [ 1-1:0] M_adder_z;
wire [ 1-1:0] M_adder_v;
wire [ 1-1:0] M_adder_n;
reg [16-1:0] M_adder_a... | 6.556797 |
module alu_16_bit (
input [15:0] A,
input [15:0] B,
input [2:0] op,
output reg [15:0] R,
output reg AltB
);
always @* begin
case (op)
0: R = A & B; // And
1: R = A | B; // Or
2: R = A + B; // Add
3: R = B - A; // Sub
4:
if ($signed(B) < 0) begin // sh... | 8.001301 |
module alu_16_bit_11 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out
);
wire [ 1-1:0] M_arithmeticUnit_z;
wire [ 1-1:0] M_arithmeticUnit_v;
wire [ 1-1:0] M_arithmeticUnit_n;
wire [16-1:0] M_arithmeticUnit_out;
reg [16-1:0] M_arithmeticUnit_a;
reg [16-1:0] M_ar... | 6.813687 |
module alu_16_bit_tb;
// Inputs
reg [15:0] A;
reg [15:0] B;
reg [2:0] op;
// Outputs
wire [15:0] R;
wire AltB;
// Instantiate the Unit Under Test (UUT)
alu_16_bit uut (
.A(A),
.B(B),
.op(op),
.R(R),
.AltB(AltB)
);
initial begin
// Initialize Inputs
A = 0;... | 7.169615 |
module alu_181 #(
parameter WIDTH = 16
) (
input [WIDTH-1:0] A_in,
input [WIDTH-1:0] B_in,
output [WIDTH-1:0] out,
input mode, // alu or logical
input [3:0] op_in, // alu op on the 181s
input carry_in,
output carry_out,
output reg equal_out
);
localparam NUM181 = WIDTH / 4; // ... | 9.24349 |
module Circuit74182 (
CN,
PB,
GB,
PBo,
GBo,
CNX,
CNY,
CNZ
);
input [3:0] PB, GB;
input CN;
output PBo, GBo, CNX, CNY, CNZ;
TopLevel74182b Ckt74182b (
CN,
PB,
GB,
PBo,
GBo,
CNX,
CNY,
CNZ
);
endmodule
| 6.993964 |
module TopLevel74181b (
S,
A,
B,
M,
CNb,
F,
X,
Y,
CN4b,
AEB
);
input [3:0] A, B, S;
input CNb, M;
output [3:0] F;
output AEB, X, Y, CN4b;
wire [3:0] E, D, C, Bb;
Emodule Emod1 (
A,
B,
S,
E
);
Dmodule Dmod2 (
A,
B,
S,
... | 6.940936 |
module testbench (
input clk
);
localparam trace = 1;
/// test of our ALU module
reg [15:0] A = 0;
reg [15:0] B = 1;
reg C_in = 1; // carry in
reg [3:0] select = 'b1001; // add
reg mode = 0; // alu ops
wire [15:0] out;
wire C_out;
wire Equal;
alu_181 alu (
.A_in(A),
.B_in(B)... | 6.751666 |
module ALU_1B (
Y,
CarryOut,
A,
B,
Less,
CarryIn,
A_invert,
B_invert,
Op
);
input A, B, CarryIn, Less;
input A_invert, B_invert;
input [1:0] Op;
output Y;
output CarryOut;
wire T1, T2;
wire Y1;
ALU_adder Adder (
Y1,
CarryOut,
T1,
T2,
Ca... | 7.049592 |
module ALU_adder (
Sum,
Carry,
A,
B,
C
);
input A, B, C;
output Sum, Carry;
assign {Carry, Sum} = A + B + C;
endmodule
| 8.504694 |
module ALU_1B_MSB (
Set,
Overflow,
Y,
CarryOut,
A,
B,
Less,
CarryIn,
A_invert,
B_invert,
Op
);
input A, B, CarryIn, Less;
input A_invert, B_invert;
input [1:0] Op;
output Y;
output Set, Overflow, CarryOut;
wire T1, T2;
wire Y1;
ALU_adder Adder (
Y1,
... | 6.746766 |
module ALU_1bit_tb;
reg a, b, Ainvert, Binvert, Cin;
reg [1:0] operation;
wire sum, carry;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
ALU_1bit UUT (
a,
b,
Ainvert,
Binvert,
Cin,
operation,
sum,
carry
);
initial... | 6.509043 |
module ALU_1_bit (
input a,
b,
CarryIn,
input [3:0] ALUOp,
output reg Result,
output reg CarryOut
);
always @(ALUOp or a or b or CarryIn) begin
if (ALUOp[1:0] == 2'b00) begin
if (ALUOp[3:2] == 2'b00) Result <= a & b;
else begin
if (ALUOp[3:2] == 2'b11) assign Result = ~... | 6.504433 |
module for use as the most-significant bit
// of the 16-bit ALU.
module alu_1_bit_msb(result, overflow, set, c_out, a, b, less, c_in, op);
input a, b;
input less;
input c_in;
input [2:0] op;
output result, overflow, set, c_out;
wire m, n, p, q;
not g1(m, b);
mux_2_to_1 mux1(n, b, m, o... | 7.198888 |
module ALU_1_tb ();
reg [15:0] op1, op2;
reg [ 1:0] func;
wire [15:0] result;
wire [ 5:0] flags;
reg [15:0] inputTests1[0:15];
reg [15:0] inputTests2[0:15];
reg [15:0] resultTests[0:15];
reg [ 5:0] flagsTests [0:15];
reg [ 1:0] funcTests [0:15];
ALU_1 alu (
.op1(op1),
.op2(op2),... | 6.660444 |
module alu (
dataOut_1,
dataOut_2,
ext32,
ALUSrc,
ALUOp,
zero,
overflow,
alu_res,
write_30
);
input [31:0] dataOut_1, dataOut_2, ext32;
input [1:0] ALUOp;
input ALUSrc;
input write_30;
output zero, overflow;
output reg [31:0] alu_res;
wire [31:0] a, b;
wire [32:0] tm... | 6.813467 |
module Alu_2_Operations (
input [3:0] A,
B,
input c,
output [3:0] Out
);
assign Out = c != 1 ? A + B : A - B;
endmodule
| 7.849354 |
module alu_3 #(
parameter STAGE_ID = 0,
parameter ACTION_LEN = 25,
parameter META_LEN = 256,
parameter COMP_LEN = 100
) (
input clk,
input rst_n,
//the input data shall be metadata & com_ins
input [META_LEN+COMP_LEN-1:0] comp_meta_dat... | 7.687102 |
module alu_32 #(
parameter WIDTH = 32
) (
input [WIDTH - 1 : 0] a,
b,
input [2:0] f,
output reg [WIDTH -1 : 0] y,
output reg z
);
parameter ADD_32 = 3'b000;
parameter SUB_32 = 3'b001;
parameter AND_32 = 3'b010;
parameter OR_32 = 3'b011;
parameter XOR_32 = 3'b100;
always @(*) begin
... | 8.332004 |
module ALU_32bit (
SW1,
SW2,
SW4,
clock_100Mhz,
//reset,
a_to_g,
an,
LED1,
LED2,
LED4,
aluout
);
input SW1; // Represents S0
input SW2; // Represents S1
input SW4; // Represents Reset
input clock_100Mhz;
//input reset;
output reg [7:0] a_to_g;
output re... | 7.299764 |
module FA_16bit (
a,
b,
cin,
sum,
cFlag
);
input [15:0] a;
input [15:0] b;
input cin;
output [15:0] sum;
output cFlag;
assign sum = a + b + cin;
assign cFlag = (a & b | (a ^ b) & cin);
endmodule
| 6.642525 |
module FS (
a,
b,
bin,
diff,
bout
);
input a;
input b;
input bin;
output diff;
output bout;
wire an;
wire w0;
wire w0not;
wire w1;
wire w2;
// Design implementation of a single bit full subtractor
not n1 (an, a);
not n2 (w0not, w0);
xor x1 (w0, a, b);
and a1 (w1,... | 7.619808 |
module FS_16bit (
a,
b,
bin,
diff,
bout
);
input [15:0] a;
input [15:0] b;
input bin;
output [15:0] diff;
output bout;
wire w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12, w13, w14, w15;
// Design implementation
// Using the previous module of a single bit full subtractor
... | 8.163367 |
module mult_16bit (
a,
b,
mult
);
input [15:0] a;
input [15:0] b;
output [31:0] mult;
assign mult = a * b;
endmodule
| 7.498629 |
module Shift_RightA (
a,
shift_a
);
input [15:0] a;
output [15:0] shift_a;
assign shift_a = a >> 1;
endmodule
| 7.399126 |
module ALU_32_bit (
a,
b,
Binvert,
Carryin,
Operation,
Result,
CarryOut
);
input Binvert, Carryin;
input [1:0] Operation;
input [31:0] a, b;
output [31:0] Result;
output CarryOut;
wire [31:0] out, notB, in0, in1, in2;
assign {notB} = ~b;
AND_32_Bit AND (
in0,
a,... | 7.226228 |
module ALU_4B (
Y,
CarryOut,
A,
B,
Less,
CarryIn,
A_invert,
B_invert,
Op
);
output [3:0] Y;
output CarryOut;
input [3:0] A, B, Less;
input CarryIn;
input A_invert, B_invert;
input [1:0] Op;
wire [3:0] GC;
wire [3:0] C, G, P;
assign CarryOut = C[3];
ALU_1B ALU0 (... | 6.760633 |
module or5_0 (
IN1,
IN3,
IN2,
IN5,
IN4,
OUT
);
/* synthesis black_box */
input IN1;
input IN3;
input IN2;
input IN5;
input IN4;
output OUT;
endmodule
| 6.514611 |
module or5_0 (
IN1,
IN3,
IN2,
IN5,
IN4,
OUT
);
/* synthesis black_box */
input IN1;
input IN3;
input IN2;
input IN5;
input IN4;
output OUT;
or (OUT, IN1, IN2, IN3, IN4, IN5);
endmodule
| 6.514611 |
modules:
// 1. a 1-bit ALU building block (based on figure C.5.9 of the 4th edition of
// the textbook, which is same as figure B.5.9 of the 3rd edition), and
// 2. a 4-bit ALU built by instantiating 4 of the above building blocks and
// adding needed glue logic for SLT implementation (based on figure C.5.12 o... | 8.772217 |
module alu_4_bit (
A,
B,
AINV,
BNEG,
Opr,
RESULT,
OVERFLOW,
ZERO,
COUT
);
input [3:0] A, B;
input AINV, BNEG;
input [1:0] Opr;
output [3:0] RESULT;
output OVERFLOW, ZERO, COUT;
//LOCAL SIGNALS;
wire COUT1, COUT2, COUT3, COUT4;
wire BINV, SET, LESS_0;
wire [3:0] A... | 7.806442 |
module for use as the most-significant
// 4 bits of the 16-bit ALU.
module alu_4_bit_last(result, overflow, set, zero, c_out, a, b, c_in, op);
input [3:0] a;
input [3:0] b;
input c_in;
input [2:0] op;
output [3:0] result;
output overflow, set, zero, c_out;
wire p, q, r, s, t;
alu_1_bit... | 7.198888 |
module alu_4_bit_tb;
reg [3:0] A_tb, B_tb;
reg AINV_tb, BNEG_tb;
reg [1:0] Opr_tb;
wire [3:0] RESULT_tb;
wire OVERFLOW_tb, ZERO_tb, COUT_tb;
integer test_num;
integer file_results; // file_results is a logical name for the physical file alu_output_results.txt here.
// module alu_4_bit (A, B, AINV, B... | 7.342503 |
module decoder (
input en,
input [1:0] sel,
output reg ea,
eb,
ef
);
always @(*) begin
if (en) begin
case (sel)
2'b00: begin
ea = 1'b1;
eb = 1'b0;
ef = 1'b0;
end
2'b01: begin
ea = 1'b0;
eb = 1'b1;
ef = 1'... | 7.018254 |
module alu_6 #(
parameter ADD_6 = 3'b000,
parameter SUB_6 = 3'b001,
parameter AND_6 = 3'b010,
parameter OR_6 = 3'b011,
parameter XOR_6 = 3'b100
) (
input clk,
input en,
input [1:0] sel,
input [5:0] x,
output reg [5:0] y,
output reg z
);
reg [2:0] fr;
reg [5:0] ar;
reg... | 6.762562 |
module ALU_64 (
A,
B,
ALU_Opcode,
ALU_Out,
Z
);
parameter BITSIZE = 32;
parameter REGSIZE = 64;
input [REGSIZE-1:0] A, B; // ALU 64-bit Inputs
input [2:0] ALU_Opcode; // ALU Selection
output reg [REGSIZE-1:0] ALU_Out; // ALU 64-bit Output
output Z;
/*wire ReadD... | 8.750207 |
module ALU_64_bit (
a,
b,
ALUOp,
Zero,
Result,
Pos
);
input [63:0] a;
input [63:0] b;
input [3:0] ALUOp;
output reg Zero;
output reg [63:0] Result;
output reg Pos;
always @(*) begin
if (ALUOp == 4'b0000) begin
Result = a & b;
end else if (ALUOp == 4'b0001) begin
... | 6.840274 |
module alu_8 (
input clk,
input rst,
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out
);
reg [ 15:0] actual_output;
reg [ 15:0] temp_a;
reg [ 15:0] temp_b;
wire [16-1:0] M_alu_adder_s;
wire [ 1-1:0] M_alu_adder_cout;
wire [ 1-1:0] M_alu_adder_z;
... | 6.508885 |
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