code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module altr_hps_cyc_dly (
input wire clk,
input wire i_rst_n,
output reg dly_rst_n
);
parameter DLY = 'd8;
// counter size:
// counter counts from 0 to DLY-1, then saturates. minimum size should cover DLY-1.
// To be safe, counter size can cover DLY in case there is one run-over.
// e.g.: DLY... | 8.608872 |
module altr_hps_eccsync (
input wire rst_n, // Reset (active low)
input wire clk, // Clock
input wire err, // Error interrupt (from ECC RAM, serr/derr)
input wire err_ack, // Error interrupt request (from System Manager)
output reg err_req // Error interrupt acknowledge (to GIC... | 7.162844 |
module altr_hps_gltchfltr
#(parameter RESET_VAL = 'd0) ( // Reset value
// src_clk domain signals.
input clk,
input rst_n,
input wire din, // Async. input
output reg dout_clean // Synchronous outpu... | 7.629592 |
module altr_hps_gltchfltr_vec #(
parameter RESET_VAL = 'd0, // Reset value
parameter DWIDTH = 'd2,
parameter COUNT = 'd8,
parameter RELOAD = 'd1
) (
// src_clk domain signals.
input clk,
input rst_n,
input wire [DWIDTH-1:0] din, // Async. input
output reg [DWIDTH-1:0] dou... | 7.629592 |
module altr_hps_gtieh (
output wire z_out // output
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign z_out = 1'b1;
`else
`endif
endmodule
| 7.255927 |
module altr_hps_gtiel (
output wire z_out // output
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign z_out = 1'b0;
`else
`endif
endmodule
| 7.255927 |
module altr_hps_gtie_generator #(
parameter TIE_WIDTH = 1,
parameter [TIE_WIDTH-1:0] TIE_VALUE = 'd0
) (
output wire [TIE_WIDTH-1 : 0] z_out // output
);
genvar i;
generate
for (i = 0; i < TIE_WIDTH; i = i + 1) begin : gtie
if (TIE_VALUE[i] == 1'b1) begin
// tie high
altr_hps... | 7.255927 |
module altr_hps_mux21 (
input wire mux_in0, // mux in 0
input wire mux_in1, // mux in 1
input wire mux_sel, // mux selector
output wire mux_out // mux out
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign mux_out = mux_sel ? mux_in1 : mux_in0;
`else
`endif
endmodule
| 7.182512 |
module altr_hps_mux41 (
input wire mux_in0, // mux in 0
input wire mux_in1, // mux in 1
input wire mux_in2, // mux in 1
input wire mux_in3, // mux in 1
input wire [1:0] mux_sel, // mux selector
output wire mux_out // mux out
);
`ifdef ALTR_HPS_INTEL_MAC... | 7.006293 |
module altr_hps_nand3 (
input wire nand_in1, // and input 1
input wire nand_in2, // and input 2
input wire nand_in3, // and input 3
output wire nand_out // and output
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign nand_out = ~(nand_in1 & nand_in2 & nand_in3);
`else
`endif
endmodule
| 7.093856 |
module altr_hps_nand4 (
input wire nand_in1, // and input 1
input wire nand_in2, // and input 2
input wire nand_in3, // and input 3
input wire nand_in4, // and input 4
output wire nand_out // and output
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign nand_out = ~(nand_in1 & nand_in2 & nand_i... | 7.093856 |
module altr_hps_nor2 (
input wire nor_in1, // and input 1
input wire nor_in2, // and input 2
output wire nor_out // and output
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign nor_out = ~(nor_in1 | nor_in2);
`else
`endif
endmodule
| 7.668215 |
module altr_hps_nor3 (
input wire nor_in1, // and input 1
input wire nor_in2, // and input 2
input wire nor_in3, // and input 3
output wire nor_out // and output
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign nor_out = ~(nor_in1 | nor_in2 | nor_in3);
`else
`endif
endmodule
| 7.517618 |
module altr_hps_or (
input wire or_in1, // and input 1
input wire or_in2, // and input 2
output wire or_out // or output
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign or_out = or_in1 | or_in2;
`else
`endif
endmodule
| 7.650365 |
module altr_hps_rstnsync (
input wire clk, // Destination clock of reset to be synced
input wire i_rst_n, // Asynchronous reset input
input wire scan_mode, // Scan bypass for reset
output wire sync_rst_n // Synchronized reset output
);
reg first_stg_rst_n;
wire prescan_sync_rst_n;
... | 7.959119 |
module altr_hps_rstnsync4 (
input wire clk,
input wire i_rst_n,
input wire scan_mode,
output wire sync_rst_n
);
reg first_stg_rst_n;
wire prescan_sync_rst_n;
always @(posedge clk or negedge i_rst_n)
if (!i_rst_n) first_stg_rst_n <= 1'b0;
else first_stg_rst_n <= 1'b1;
altr_hps_bit... | 7.959119 |
module altr_hps_sync_clr #(
parameter DWIDTH = 'd1
) (
input clk, //main clk signal
input rst_n, //main reset signal
input clr, //active high clear signal (expected this clear signal to be quasi-static)
input [DWIDTH-1:0] data_in, //data in
output [DWIDTH-1:0] data_out //data out
);
`ifdef... | 7.152398 |
module altr_i2c_databuffer #(
parameter DSIZE = 8
) (
input clk,
input rst_n,
input s_rst, //Sync Reset - when Mode is disabled
input put,
input get,
output reg empty,
input [DSIZE-1:0] wdata,
output reg [DSIZE-1:0] rdata
);
//BUFFER storage
always @(posedge clk or negedge rst_... | 8.145772 |
module altr_i2c_spksupp (
input i2c_clk,
input i2c_rst_n,
input [7:0] ic_fs_spklen,
input sda_in,
input scl_in,
output sda_int,
output scl_int
);
// Status Register bit definition
// wires & registers declaration
reg [7:0] scl_spike_cnt;
r... | 7.569367 |
module altr_i2c_txout (
input i2c_clk,
input i2c_rst_n,
input [15:0] ic_sda_hold,
input start_sda_out,
input restart_sda_out,
input stop_sda_out,
input mst_tx_sda_out,
input mst_rx_sda_out,
input slv_tx_sda_out,
input ... | 6.612108 |
module contains altsource_probe megafunction body
//************************************************************
///////////////////////////////////////////////////////////////////////////////
// Description : IP for Interactive Probe. Capture internal signals using the
// probe input, drive internal signa... | 7.039347 |
module altsource_probe_top #(
parameter lpm_type = "altsource_probe", // required by the coding standard
parameter lpm_hint = "UNUSED", // required by the coding standard
parameter sld_auto_instance_index = "YES", // Yes, if the instance index should be automatically assigned.
parameter sl... | 8.012029 |
module is a parametrized dual port ram with a registered output port
It is optional to define it's input address and output address and it's
depth.
REVISION HISTORY
05FEB03 First Created -ac-
*******************************************************************************/
module altsyncram3... | 7.877064 |
module alt_a10_temp_sense (
input clk,
output reg [7:0] degrees_c,
output reg [7:0] degrees_f
);
// WYS connection to sense diode ADC
wire [9:0] tsd_out;
// make sure it actually routes, out of caution for flakey new port connections
wire trst = 1'b0 /* synthesis keep */;
wire corectl = 1'b1 /... | 7.233031 |
module alt_and3t1 #(
parameter SIM_EMULATE = 1'b0
) (
input clk,
input [2:0] din,
output dout
);
wire dout_w;
alt_and3t0 c0 (
.din (din),
.dout(dout_w)
);
defparam c0.SIM_EMULATE = SIM_EMULATE;
reg dout_r = 1'b0;
always @(posedge clk) dout_r <= dout_w;
assign dout = dout_r;
... | 6.673592 |
module alt_bcd_counter (
input clk,
rst_n,
input go,
output reg [3:0] s1,
s0,
ms0
);
reg [22:0] counter_reg = 0;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
s1 <= 0;
s0 <= 0;
ms0 <= 0;
counter_reg <= 0;
end else if (go) begin //nested-if for ... | 6.52275 |
module alt_db_fsm (
input wire clk,
reset,
input wire sw,
output reg db
);
// symbolic state declaration
localparam[2:0]
zero = 3'b000,
wait1_1 = 3'b001,
wait1_2 = 3'b010,
wait1_3 = 3'b011,
one = 3'b100,
wait0_1 = 3'b101,
wait0_2 = 3... | 7.057655 |
module alt_db_fsm_tb;
// signal declaration
localparam T = 10; // clk period
reg clk, reset;
reg sw;
wire db;
// instance of uut
alt_db_fsm uut (
.clk(clk),
.reset(reset),
.sw(sw),
.db(db)
);
// clock
always begin
clk = 1'b0;
#(T / 2);
clk = 1'b1;
#(T / 2... | 7.462 |
module alt_ddr (
input wire outclock, // outclock.export
input wire [1:0] din, // din.export
output wire [0:0] pad_out // pad_out.export
);
altera_gpio_lite #(
.PIN_TYPE ("output"),
.SIZE (1),
.REG... | 6.520382 |
module (RAM) is not used anymore, this will be commented for future reference
// which will instantiate ram modules
module alt_ddrx_bank_mem #
( parameter
MEM_IF_CS_WIDTH = 4,
MEM_IF_CHIP_BITS = 2,
MEM_IF_BA_WIDTH = 3,
MEM_IF_ROW_WIDTH = 16
)
(
ctl_clk,
ctl_... | 6.91058 |
module alt_ddrx_clock_and_reset #(
parameter DWIDTH_RATIO = "2"
) (
// Inputs
ctl_full_clk,
ctl_half_clk,
ctl_quater_clk,
//csr_clk,
reset_phy_clk_n,
// Outputs
ctl_clk,
ctl_reset_n
);
input ctl_full_clk;
input ctl_half_clk;
input ctl_quater_clk;
//input csr_clk;
inpu... | 6.957515 |
module alt_ddrx_ddr3_odt_gen #(
parameter DWIDTH_RATIO = 2,
TCL_BUS_WIDTH = 4,
CAS_WR_LAT_BUS_WIDTH = 4
) (
ctl_clk,
ctl_reset_n,
mem_tcl,
mem_cas_wr_lat,
do_write,
do_read,
int_odt_l,
int_odt_h
);
input ctl_clk;
input ctl_reset_n;
in... | 7.472813 |
module alt_debounce (
input wire clk,
reset,
input wire sw,
output reg db_level,
db_tick
);
// symbolic state declaration
localparam [1:0] zero = 2'b00, wait0 = 2'b01, one = 2'b10, wait1 = 2'b11;
// number of counter bits (2^N * 10 ns = 40 ms)
localparam N = 22;
// signal declaration... | 7.211802 |
module alt_debounce_fsmd_test (
input wire clk,
reset,
input wire [1:0] btn,
output wire [3:0] an,
output wire [7:0] sseg
);
// signal declaration
reg [7:0] b_reg, d_reg;
wire [7:0] b_next, d_next;
reg btn_reg;
wire db_tick, btn_tick, clr;
// instantiate display circuit
disp_... | 8.656287 |
module alt_delay_dynamic_m20k #(
parameter WIDTH = 16,
parameter ADDR_WIDTH = 10
)(
input clk,
input [ADDR_WIDTH-1:0] delta,
input din_valid,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout
);
reg [ADDR_WIDTH-1:0] waddr = {ADDR_WIDTH{1'b0}};
reg [ADDR_WIDTH-1:0] raddr = {ADDR_WIDTH{1'b0}};
always @(p... | 6.752459 |
module alt_descrambler #(
parameter WIDTH = 512,
parameter OFS = 0 // debug shift
) (
input clk,
srst,
ena,
input [WIDTH-1:0] din, // bit 0 is used first
output reg [WIDTH-1:0] dout
);
reg [2*WIDTH-1:0] lag_din = 0;
always @(posedge clk) begin
if (srst) lag_din <= {2 * WIDTH{1'b0}... | 7.495298 |
module alt_fmon8 #(
parameter SIM_HURRY = 1'b0,
parameter SIM_EMULATE = 1'b0
) (
input clk,
input [7:0] din,
input [2:0] din_sel,
output [15:0] dout,
output dout_fresh
);
////////////////////////////
// divide down and cross domain
wire [7:0] prescale;
wire [7:0] prescale_s;
g... | 8.11264 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module alt_invert (
inA,
A
);
parameter n = 8;
// Assigning ports as in/out
input [n-1 : 0] inA;
output [n-1 : 0] A;
genvar i;
generate
for (i = 0; i < n; i = i + 1) begin : l1
if (i % 2 == 0) assign A[i] = ~inA[i];
else assign A[i] = inA[i];
end
endgenerate
endmodule
| 8.024698 |
module alt_iobuf
(
`IOB_INPUT(i, 1),
`IOB_INPUT(oe, 1),
`IOB_OUTPUT(o, 1),
`IOB_INOUT(io, 1)
);
assign io = oe? i : 1'bz;
assign o = io;
endmodule
| 6.918813 |
module alt_lfsr_client_40b #(
parameter SEED = 32'h12345678
) (
input clk_tx,
input srst_tx,
output [39:0] tx_sample, // lsbit first
input clk_rx,
input srst_rx,
input [39:0] rx_sample, // lsbit first
output [3:0] err_cnt
);
localparam WIDTH = 40;
// send scrambled 0's
alt_scr... | 7.043769 |
module alt_mem_asym #(
parameter A_ADDRESS_WIDTH = 0,
parameter A_DATA_WIDTH = 128,
parameter B_ADDRESS_WIDTH = 10,
parameter B_DATA_WIDTH = 128
) (
input wire [127:0] data_datain, // data.datain
output wire [127:0] mem_o_dataout, // mem_o.dataout
input wire ... | 7.029251 |
module alt_mem_asym_bypass #(
parameter A_ADDRESS_WIDTH = 10,
parameter A_DATA_WIDTH = 128,
parameter B_ADDRESS_WIDTH = 10,
parameter B_DATA_WIDTH = 128
) (
input wire [127:0] mem_i_datain, // mem_i.datain
input wire [ 9:0] mem_i_wraddress, // .wraddress
input wire [ 9:0... | 7.157808 |
module alt_mem_asym_rd #(
parameter A_ADDRESS_WIDTH = 0,
parameter A_DATA_WIDTH = 512,
parameter B_ADDRESS_WIDTH = 12,
parameter B_DATA_WIDTH = 128
) (
input wire [511:0] mem_i_datain, // mem_i.datain
input wire [ 9:0] mem_i_wraddress, // .wraddress
input wire [ 11:0] mem... | 7.157808 |
module alt_mem_asym_wr #(
parameter A_ADDRESS_WIDTH = 12,
parameter A_DATA_WIDTH = 128,
parameter B_ADDRESS_WIDTH = 8,
parameter B_DATA_WIDTH = 512
) (
input wire [127:0] mem_i_datain, // mem_i.datain
input wire [ 11:0] mem_i_wraddress, // .wraddress
input wire [ 9:0] mem... | 7.157808 |
module alt_mlab #(
parameter WIDTH = 20,
parameter ADDR_WIDTH = 5,
parameter SIM_EMULATE = 1'b0 // this may not be exactly the same at the fine grain timing level
) (
input wclk,
input wena,
input [ADDR_WIDTH-1:0] waddr_reg,
input [WIDTH-1:0] wdata_reg,
input [ADDR_WIDTH-1:0] raddr,
... | 7.833195 |
module alt_or_r #(
parameter WIDTH = 8
) (
input clk,
input [WIDTH-1:0] din,
output dout
);
genvar i;
generate
if (WIDTH <= 6) begin
reg dout_r = 1'b0;
always @(posedge clk) dout_r <= |din;
assign dout = dout_r;
end else if ((WIDTH % 6) == 0) begin
localparam NUM_HEX... | 8.522536 |
module alt_reset_delay #(
parameter CNTR_BITS = 16
) (
input clk,
input ready_in,
output ready_out
);
reg [2:0]
rs_meta = 3'b0 /* synthesis preserve dont_replicate */
/* synthesis ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \"set_false_path -from [get_fanins -async *reset_delay*rs_meta\[*\]] -to... | 6.932559 |
module alt_scfifo (
aclr,
clock,
data,
rdreq,
sclr,
wrreq,
almost_empty,
almost_full,
empty,
full,
q,
usedw,
fifo_ovf,
fifo_unf
);
parameter FIFO_WIDTH = 144;
parameter FIFO_DEPTH = 7;
parameter FIFO_TYPE = "AUTO";
parameter FIFO_SHOW = "OFF";
parameter... | 6.630776 |
module alt_scrambler #(
parameter WIDTH = 512,
parameter SCRAM_INIT = 58'h3ff_ffff_ffff_ffff,
parameter DEBUG_DONT_SCRAMBLE = 1'b0
) (
input clk,
srst,
ena,
input [WIDTH-1:0] din, // bit 0 is to be sent first
output reg [WIDTH-1:0] dout
);
reg [57:0] scram_state = SCRAM_INIT;
wire ... | 7.298221 |
module alt_sld_fab_altera_a10_xcvr_reset_sequencer_181_ivi4soy (
input wire clk_in_0, // Unused (this is part of a reset ep configured which isn't configured as a clock input)
input wire reset_req_0,
output wire reset_out_0,
input wire clk_in_1, // Unused (this is part of a reset ep configured which i... | 7.327296 |
module alt_sld_fab_alt_sld_fab_trfabric_mem (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
output [31:0] readdata;
input [12:0] address;
input [3:0] byteenable;
input chipselect;
... | 7.327296 |
module alt_sync_regs_m2 #(
parameter WIDTH = 32,
parameter DEPTH = 2 // minimum of 2
) (
input clk,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout
);
reg [WIDTH-1:0]
din_meta = 0 /* synthesis preserve dont_replicate */
/* synthesis ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \"set_multicycl... | 6.712928 |
module alt_times_1pt8 #(
parameter WIDTH = 8
) (
input clk,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout
);
reg [WIDTH+8-1:0] scratch = {(WIDTH + 8) {1'b0}};
reg [WIDTH+1-1:0] p0 = {(WIDTH + 1) {1'b0}};
reg [WIDTH+3-1:0] p1 = {(WIDTH + 3) {1'b0}};
reg [WIDTH+2-1:0] p2 = {(WIDTH + 2) {1'b0}};... | 6.880969 |
module alt_top (
input OSCCLK,
output hsync,
output vsync,
output [2:0] red,
output [2:0] green,
output [1:0] blue,
output [7:0] sseg,
output [3:0] an,
input ps2_clk,
input ps2_data
);
wire [7:0] wr;
wire [7:0] wg;
wire [7:0] wb;
assign red = wr[7:5];
assign green... | 8.721 |
module alt_vipcti130_common_fifo (
wrclk,
rdreq,
aclr,
rdclk,
wrreq,
data,
rdusedw,
rdempty,
wrusedw,
wrfull,
q
);
function integer alt_clogb2;
input [31:0] value;
integer i;
begin
alt_clogb2 = 32;
for (i = 31; i > 0; i = i - 1) begin
if (2 ... | 6.83539 |
module alt_vipcti130_common_frame_counter #(
parameter NUMBER_OF_COLOUR_PLANES = 0,
COLOUR_PLANES_ARE_IN_PARALLEL = 0,
LOG2_NUMBER_OF_COLOUR_PLANES = 0,
CONVERT_SEQ_TO_PAR = 0,
TOTALS_MINUS_ONE = 0
) (
input wire rst,
input wire clk,
input wire sclr,
// control signals
input wir... | 6.83539 |
module alt_vipcti130_common_sample_counter #(
parameter NUMBER_OF_COLOUR_PLANES = 0,
COLOUR_PLANES_ARE_IN_PARALLEL = 0,
LOG2_NUMBER_OF_COLOUR_PLANES = 0
) (
input wire rst,
input wire clk,
input wire sclr,
input wire count_cycle,
input wire hd_sdn,
output wire count_sample,
out... | 6.83539 |
module alt_vipcti130_common_sync #(
parameter CLOCKS_ARE_SAME = 0,
WIDTH = 1
) (
input wire rst,
input wire sync_clock,
input wire [WIDTH-1:0] data_in,
output wire [WIDTH-1:0] data_out
);
(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name SDC_STATEMENT \"... | 6.83539 |
module alt_vipcti130_Vid2IS_sync_polarity_convertor (
input rst,
input clk,
input sync_in,
input datavalid,
output sync_out
);
wire datavalid_negedge;
reg datavalid_reg;
wire needs_invert_nxt;
reg needs_invert;
wire invert_sync_nxt;
reg invert_sync;
assign datavalid_negedge = d... | 6.83539 |
module alt_vipcti130_Vid2IS_write_buffer #(
parameter DATA_WIDTH = 20,
NUMBER_OF_COLOUR_PLANES = 2,
BPS = 10
) (
input wire rst,
input wire clk,
input wire convert,
input wire hd_sdn,
input wire early_eop,
input wire wrreq_in,
input wire [DATA_WIDTH-1:0] data_in,
input wire... | 6.83539 |
module alt_vipcti131_common_fifo (
wrclk,
rdreq,
aclr,
rdclk,
wrreq,
data,
rdusedw,
rdempty,
wrusedw,
wrfull,
q
);
function integer alt_clogb2;
input [31:0] value;
integer i;
begin
alt_clogb2 = 32;
for (i = 31; i > 0; i = i - 1) begin
if (2 ... | 6.875537 |
module alt_vipcti131_common_frame_counter #(
parameter NUMBER_OF_COLOUR_PLANES = 0,
COLOUR_PLANES_ARE_IN_PARALLEL = 0,
LOG2_NUMBER_OF_COLOUR_PLANES = 0,
CONVERT_SEQ_TO_PAR = 0,
TOTALS_MINUS_ONE = 0
) (
input wire rst,
input wire clk,
input wire sclr,
// control signals
input wir... | 6.875537 |
module alt_vipcti131_common_sample_counter #(
parameter NUMBER_OF_COLOUR_PLANES = 0,
COLOUR_PLANES_ARE_IN_PARALLEL = 0,
LOG2_NUMBER_OF_COLOUR_PLANES = 0
) (
input wire rst,
input wire clk,
input wire sclr,
input wire count_cycle,
input wire hd_sdn,
output wire count_sample,
out... | 6.875537 |
module alt_vipcti131_common_sync #(
parameter CLOCKS_ARE_SAME = 0,
WIDTH = 1
) (
input wire rst,
input wire sync_clock,
input wire [WIDTH-1:0] data_in,
output wire [WIDTH-1:0] data_out
);
(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name SDC_STATEMENT \"... | 6.875537 |
module alt_vipcti131_Vid2IS_sync_polarity_convertor (
input rst,
input clk,
input sync_in,
input datavalid,
output sync_out
);
wire datavalid_negedge;
reg datavalid_reg;
wire needs_invert_nxt;
reg needs_invert;
wire invert_sync_nxt;
reg invert_sync;
assign datavalid_negedge = d... | 6.875537 |
module alt_vipcti131_Vid2IS_write_buffer #(
parameter DATA_WIDTH = 20,
NUMBER_OF_COLOUR_PLANES = 2,
BPS = 10
) (
input wire rst,
input wire clk,
input wire convert,
input wire hd_sdn,
input wire early_eop,
input wire wrreq_in,
input wire [DATA_WIDTH-1:0] data_in,
input wire... | 6.875537 |
module alt_vipitc130_common_fifo (
wrclk,
rdreq,
aclr,
rdclk,
wrreq,
data,
rdusedw,
rdempty,
wrusedw,
wrfull,
q
);
function integer alt_clogb2;
input [31:0] value;
integer i;
begin
alt_clogb2 = 32;
for (i = 31; i > 0; i = i - 1) begin
if (2 ... | 7.568016 |
module alt_vipitc130_common_frame_counter #(
parameter NUMBER_OF_COLOUR_PLANES = 0,
COLOUR_PLANES_ARE_IN_PARALLEL = 0,
LOG2_NUMBER_OF_COLOUR_PLANES = 0,
CONVERT_SEQ_TO_PAR = 0,
TOTALS_MINUS_ONE = 0
) (
input wire rst,
input wire clk,
input wire sclr,
// control signals
input wir... | 7.568016 |
module alt_vipitc130_common_generic_count #(
parameter WORD_LENGTH = 12,
parameter MAX_COUNT = 1280,
parameter RESET_VALUE = 0,
parameter TICKS_WORD_LENGTH = 1,
parameter TICKS_PER_COUNT = 1
) (
input wire clk,
input wire reset_n,
input wire enable,
input wire enable_ticks,
inpu... | 7.568016 |
module alt_vipitc130_common_sample_counter #(
parameter NUMBER_OF_COLOUR_PLANES = 0,
COLOUR_PLANES_ARE_IN_PARALLEL = 0,
LOG2_NUMBER_OF_COLOUR_PLANES = 0
) (
input wire rst,
input wire clk,
input wire sclr,
input wire count_cycle,
input wire hd_sdn,
output wire count_sample,
out... | 7.568016 |
module alt_vipitc130_common_sync #(
parameter CLOCKS_ARE_SAME = 0,
WIDTH = 1
) (
input wire rst,
input wire sync_clock,
input wire [WIDTH-1:0] data_in,
output wire [WIDTH-1:0] data_out
);
(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name SDC_STATEMENT \"... | 7.568016 |
module alt_vipitc130_common_to_binary (
one_hot,
binary
);
parameter NO_OF_MODES = 3;
parameter LOG2_NO_OF_MODES = 2;
input [NO_OF_MODES-1:0] one_hot;
output [LOG2_NO_OF_MODES-1:0] binary;
generate
genvar binary_pos, one_hot_pos;
wire [(NO_OF_MODES*LOG2_NO_OF_MODES)-1:0] binary_values;
... | 7.568016 |
module alt_vipitc130_common_trigger_sync (
input wire input_rst,
input wire input_clock,
input wire rst,
input wire sync_clock,
input wire trigger_in,
input wire ack_in,
output wire trigger_out
);
parameter CLOCKS_ARE_SAME = 0;
generate
if (CLOCKS_ARE_SAME) assign trigger_out = ... | 7.568016 |
module alt_vipitc130_IS2Vid_calculate_mode (
input [3:0] trs,
input is_interlaced,
input is_serial_output,
input [15:0] is_sample_count_f0,
input [15:0] is_line_count_f0,
input [15:0] is_sample_count_f1,
input [15:0] is_line_count_f1,
input [15:0] is_h_front_porch,
input [15:0] is_h_... | 7.568016 |
module alt_vipitc131_common_fifo (
wrclk,
rdreq,
aclr,
rdclk,
wrreq,
data,
rdusedw,
rdempty,
wrusedw,
wrfull,
q
);
function integer alt_clogb2;
input [31:0] value;
integer i;
begin
alt_clogb2 = 32;
for (i = 31; i > 0; i = i - 1) begin
if (2 ... | 7.512576 |
module alt_vipitc131_common_frame_counter #(
parameter NUMBER_OF_COLOUR_PLANES = 0,
COLOUR_PLANES_ARE_IN_PARALLEL = 0,
LOG2_NUMBER_OF_COLOUR_PLANES = 0,
CONVERT_SEQ_TO_PAR = 0,
TOTALS_MINUS_ONE = 0
) (
input wire rst,
input wire clk,
input wire sclr,
// control signals
input wir... | 7.512576 |
module alt_vipitc131_common_generic_count #(
parameter WORD_LENGTH = 12,
parameter MAX_COUNT = 1280,
parameter RESET_VALUE = 0,
parameter TICKS_WORD_LENGTH = 1,
parameter TICKS_PER_COUNT = 1
) (
input wire clk,
input wire reset_n,
input wire enable,
input wire enable_ticks,
inpu... | 7.512576 |
module alt_vipitc131_common_sample_counter #(
parameter NUMBER_OF_COLOUR_PLANES = 0,
COLOUR_PLANES_ARE_IN_PARALLEL = 0,
LOG2_NUMBER_OF_COLOUR_PLANES = 0
) (
input wire rst,
input wire clk,
input wire sclr,
input wire count_cycle,
input wire hd_sdn,
output wire count_sample,
out... | 7.512576 |
module alt_vipitc131_common_sync #(
parameter CLOCKS_ARE_SAME = 0,
WIDTH = 1
) (
input wire rst,
input wire sync_clock,
input wire [WIDTH-1:0] data_in,
output wire [WIDTH-1:0] data_out
);
(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name SDC_STATEMENT \"... | 7.512576 |
module alt_vipitc131_common_to_binary (
one_hot,
binary
);
parameter NO_OF_MODES = 3;
parameter LOG2_NO_OF_MODES = 2;
input [NO_OF_MODES-1:0] one_hot;
output [LOG2_NO_OF_MODES-1:0] binary;
generate
genvar binary_pos, one_hot_pos;
wire [(NO_OF_MODES*LOG2_NO_OF_MODES)-1:0] binary_values;
... | 7.512576 |
module alt_vipitc131_common_trigger_sync (
input wire input_rst,
input wire input_clock,
input wire rst,
input wire sync_clock,
input wire trigger_in,
input wire ack_in,
output wire trigger_out
);
parameter CLOCKS_ARE_SAME = 0;
generate
if (CLOCKS_ARE_SAME) assign trigger_out = ... | 7.512576 |
module alt_vipitc131_IS2Vid_calculate_mode (
input [3:0] trs,
input is_interlaced,
input is_serial_output,
input [15:0] is_sample_count_f0,
input [15:0] is_line_count_f0,
input [15:0] is_sample_count_f1,
input [15:0] is_line_count_f1,
input [15:0] is_h_front_porch,
input [15:0] is_h_... | 7.512576 |
module alt_vipswi130_common_stream_output #(
parameter DATA_WIDTH = 10
) (
input wire rst,
input wire clk,
// dout
input wire dout_ready,
output wire dout_valid,
output reg [DATA_WIDTH-1:0] dout_data,
output reg dout_sop,
output ... | 8.849096 |
module alt_vipswi130_switch_control #(
parameter AV_ADDRESS_WIDTH = 5,
AV_DATA_WIDTH = 16,
NO_INPUTS = 4,
NO_OUTPUTS = 4,
NO_SYNCS = 4
) (
input wire rst,
input wire clk,
// control
input wire [AV_ADDRESS_WIDTH-1:0] av_address,
input wire av_read,
ou... | 8.849096 |
module alt_vipvfr130_common_avalon_mm_master (
clock,
reset,
// Avalon-MM master interface
av_clock,
av_reset,
av_address,
av_burstcount,
av_writedata,
av_readdata,
av_write,
av_read,
av_readdatavalid,
av_waitrequest,
// user algorithm interface
addr,
co... | 8.0499 |
module alt_vipvfr130_common_stream_output #(
parameter DATA_WIDTH = 10
) (
input wire rst,
input wire clk,
// dout
input wire dout_ready,
output wire dout_valid,
output reg [DATA_WIDTH-1:0] dout_data,
output reg dout_sop,
output ... | 8.0499 |
module alt_vipvfr130_common_unpack_data (
clock,
reset,
// read interface (memory side)
data_in,
read,
stall_in,
// write interface (user side)
data_out,
write,
stall_out,
// clear buffer
clear
);
// DATA_WIDTH_IN must not be smaller than DATA_WIDTH_OUT!
parame... | 8.0499 |
module alt_vipvfr131_common_avalon_mm_master (
clock,
reset,
// Avalon-MM master interface
av_clock,
av_reset,
av_address,
av_burstcount,
av_writedata,
av_readdata,
av_write,
av_read,
av_readdatavalid,
av_waitrequest,
// user algorithm interface
addr,
co... | 8.433874 |
module alt_vipvfr131_common_stream_output #(
parameter DATA_WIDTH = 10
) (
input wire rst,
input wire clk,
// dout
input wire dout_ready,
output wire dout_valid,
output reg [DATA_WIDTH-1:0] dout_data,
output reg dout_sop,
output ... | 8.433874 |
module alt_vipvfr131_common_unpack_data (
clock,
reset,
// read interface (memory side)
data_in,
read,
stall_in,
// write interface (user side)
data_out,
write,
stall_out,
// clear buffer
clear
);
// DATA_WIDTH_IN must not be smaller than DATA_WIDTH_OUT!
parame... | 8.433874 |
module alt_vip_common_flow_control_wrapper #(
parameter BITS_PER_SYMBOL = 8,
parameter SYMBOLS_PER_BEAT = 3
) (
input clk,
input rst,
// interface to decoder
output din_ready,
input din_valid,
input [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 1:0] din_data,
input [15:0] decoder_width,
... | 7.933786 |
module alt_vip_common_stream_output #(
parameter DATA_WIDTH = 10
) (
input wire rst,
input wire clk,
// dout
input wire dout_ready,
output wire dout_valid,
output reg [DATA_WIDTH-1:0] dout_data,
output reg dout_sop,
output reg ... | 7.933786 |
module alt_vram (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [14:0] address_a;
input [14:0] address_b;
input clock_a;
input clock_b;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b... | 6.562369 |
module ALU (
Reg_A,
Reg_B,
ALUOp,
Reset,
BorN,
Branch_Flag,
ALU_Out
);
input [31:0] Reg_A, Reg_B;
input [2:0] ALUOp;
input [1:0] BorN;
input Reset;
output reg Branch_Flag;
output reg [31:0] ALU_Out;
reg [31:0] MOV, NOT, ADD, SUB, OR, AND, XOR, SLT;
always @(*) begin
if (... | 6.708595 |
module ALUCtrl (
ALUSel,
ALUOp,
Funct
);
input [5:0] Funct;
input [1:0] ALUOp;
output reg [3:0] ALUSel;
parameter add = 0, sub = 1, sll = 2, slv = 3, srav = 4;
always @(ALUSel, ALUOp, Funct) begin
if (ALUOp == 0) ALUSel <= 0;
else if (ALUOp == 1) ALUSel <= 1;
else
case (Funct)
... | 6.86253 |
module ALU_decoder (
input [1:0] ALU_OP,
input [5:0] funct,
output reg [2:0] ALU_control
);
always @(*) begin
case (ALU_OP)
2'b00: begin
ALU_control = 3'b010;
end
2'b01: begin
ALU_control = 3'b100;
end
2'b10: begin
case (funct)
6'b10_0000... | 6.956019 |
module ALU_mod (
input [31:0] SRC_A,
input [31:0] SRC_B,
input [2:0] ALU_control,
output reg [31:0] ALU_result,
output reg zero_flag
);
always @(*) begin
case (ALU_control)
3'b000: begin
ALU_result = SRC_A & SRC_B;
end
3'b001: begin
ALU_result = SRC_A | SRC_B;... | 6.855121 |
module ALU (
input1,
input2,
aluCtr,
zero,
aluRes
);
input [31:0] input1;
input [31:0] input2;
input [3:0] aluCtr;
output zero;
output [31:0] aluRes;
reg Zero;
reg [31:0] AluRes;
always @(input1 or input2 or aluCtr) begin
case (aluCtr)
4'b0010: AluRes = input1 + input2; ... | 7.960621 |
module for test bench
module test_alu;
// Declare variables to be connected to inputs and outputs
reg [15:0] x;
reg [15:0] y;
wire [15:0] z;
reg c_in;
wire c_out;
wire lt,eq,gt;
wire overflow;
reg [2:0] ALUOp;
alu test(x,y,z,c_in,c_out,lt,eq,gt,overflow,ALUOp);
initial
begin
// check AND operation
x=16'h1; y=16'... | 7.417889 |
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