code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module altr_hps_cyc_dly (
input wire clk,
input wire i_rst_n,
output reg dly_rst_n
);
parameter DLY = 'd8;
// counter size:
// counter counts from 0 to DLY-1, then saturates. minimum size should cover DLY-1.
// To be safe, counter size can cover DLY in case there is one run-over.
// e.g.: DLY = 2, counter size = 2 (instead of 1). DLY = 3, size = 3 (instead of 2) ;
// DLY =3~6, size =3. DLY=7~14, size=4...
//
parameter CNT_WIDTH = DLY > 'd1022 ? 'd11 :
DLY > 'd510 ? 'd10 :
DLY > 'd254 ? 'd9 :
DLY > 'd126 ? 'd8 :
DLY > 'd62 ? 'd7 :
DLY > 'd30 ? 'd6 :
DLY > 'd14 ? 'd5 :
DLY > 'd6 ? 'd4 :
DLY > 'd2 ? 'd3 :
DLY > 'd1 ? 'd2 :
'd1;
`ifdef ALTR_HPS_SIMULATION
initial // check parameters
begin
if (DLY > 'd2046) begin
$display("ERROR : %m : DELAY parameter is too big , MAX Value is 2046.");
$finish;
end
if (DLY == 'd0) begin
$display("ERROR : %m : DELAY parameter is 0, no need to instantiate this cell.");
$finish;
end
end
`endif
reg [CNT_WIDTH-1:0] dly_cntr;
wire cntr_reached = (dly_cntr >= (DLY - 'd1));
always @(posedge clk or negedge i_rst_n)
if (!i_rst_n) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
dly_cntr <= {(1 + (CNT_WIDTH - 1)) {1'b0}};
dly_rst_n <= 1'h0;
// End of automatics
end else begin
dly_cntr <= cntr_reached ? dly_cntr : dly_cntr + {{CNT_WIDTH - 1{1'b0}}, 1'b1};
dly_rst_n <= cntr_reached;
end
endmodule
| 8.608872 |
module altr_hps_eccsync (
input wire rst_n, // Reset (active low)
input wire clk, // Clock
input wire err, // Error interrupt (from ECC RAM, serr/derr)
input wire err_ack, // Error interrupt request (from System Manager)
output reg err_req // Error interrupt acknowledge (to GIC)
);
// Declaration
localparam IDLE = 1'b0, REQ = 1'b1;
reg err_d, ack_d;
wire err_p, ack_p;
// Positive edge detection
assign err_p = err & ~err_d;
assign ack_p = err_ack & ~ack_d;
always @(posedge clk, negedge rst_n) begin
if (~rst_n) begin
err_d <= 1'b0;
ack_d <= 1'b0;
end else begin
err_d <= err;
ack_d <= err_ack;
end
end
// Hand-shake states
always @(posedge clk, negedge rst_n) begin
if (~rst_n) err_req <= 1'b0;
else
case (err_req)
IDLE: err_req <= err_p & ~err_ack;
REQ: err_req <= ~ack_p;
default: err_req <= 1'bx; // simulation purpose
endcase
end
endmodule
| 7.162844 |
module altr_hps_gltchfltr
#(parameter RESET_VAL = 'd0) ( // Reset value
// src_clk domain signals.
input clk,
input rst_n,
input wire din, // Async. input
output reg dout_clean // Synchronous output to clk.
// Glitch free output signal.
);
// signals
wire din_sync;
reg din_sync_r;
wire detect_transition;
wire dout_enable;
reg [ 2: 0] cntr;
altr_hps_bitsync #(.DWIDTH(1), .RESET_VAL(RESET_VAL)) gltchfltr_sync (
.clk(clk),
.rst_n(rst_n),
.data_in(din),
.data_out(din_sync)
);
// 2 extra flops
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
din_sync_r <= RESET_VAL;
dout_clean <= RESET_VAL;
end else begin
din_sync_r <= din_sync;
if (dout_enable) begin
dout_clean <= din_sync_r;
end
end
end
// Transition when bits are not equal (xor)
assign detect_transition = din_sync ^ din_sync_r;
// Enable output flop only when count is equal to 3'b111 and not transition.
assign dout_enable = (cntr == 3'b111) & ~detect_transition;
// 3 bit counter for 8 stable clocks without a transition.
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
cntr <= 3'd0;
end else begin
cntr <= detect_transition ? 3'd0: cntr + 3'd1;
end
end
endmodule
| 7.629592 |
module altr_hps_gltchfltr_vec #(
parameter RESET_VAL = 'd0, // Reset value
parameter DWIDTH = 'd2,
parameter COUNT = 'd8,
parameter RELOAD = 'd1
) (
// src_clk domain signals.
input clk,
input rst_n,
input wire [DWIDTH-1:0] din, // Async. input
output reg [DWIDTH-1:0] dout_clean // Synchronous output to clk.
// Glitch free output signal.
);
function integer clog2;
input [31:0] value; // Input variable
for (clog2 = 0; value > 0; clog2 = clog2 + 1) value = value >> 'd1;
endfunction
localparam FULL = COUNT - 'd1;
localparam CWIDTH = clog2(FULL);
// The reset methodology will follow altr_hps_bitsync
localparam RESET_VAL_1B = (RESET_VAL == 'd0) ? 1'b0 : 1'b1;
// signals
wire [DWIDTH-1:0] din_sync;
reg [DWIDTH-1:0] din_sync_r;
wire detect_transition;
wire dout_enable;
wire deglitching;
reg [CWIDTH-1:0] cntr;
altr_hps_bitsync #(
.DWIDTH(DWIDTH),
.RESET_VAL(RESET_VAL)
) gltchfltr_sync (
.clk(clk),
.rst_n(rst_n),
.data_in(din),
.data_out(din_sync)
);
// 2 extra flops per bit
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
din_sync_r <= {DWIDTH{RESET_VAL_1B}};
dout_clean <= {DWIDTH{RESET_VAL_1B}};
end else begin
din_sync_r <= din_sync;
if (dout_enable) begin
dout_clean <= din_sync_r;
end
end
end
// Transition when bits are not equal (xor)
assign detect_transition = |(din_sync ^ din_sync_r);
// RELOAD == 1 causes it's behavior to match with altr_hps_gltchfltr
assign deglitching = (RELOAD == 'd1) ? 1'b1 : (|(din_sync ^ dout_clean));
// Enable output flop only when count is equal to 3'b111 and not transition.
assign dout_enable = (cntr == FULL) & ~detect_transition;
// 3 bit counter for 8 stable clocks without a transition.
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
cntr <= {CWIDTH{1'b0}};
end else begin
// Some seriously long cascaded muxes
cntr <= deglitching ? ( detect_transition ? {CWIDTH{1'b0}} : (cntr == FULL) ? {CWIDTH{1'b0}} : cntr + {{CWIDTH-1{1'b0}}, 1'b1} ) : {CWIDTH{1'b0}};
// Here's what it means
// if (deglitching) -- it means a new input is sampled and is different from current output
// if (detect_transition) -- 1 pulse signal indicating a change in the synchronized input
// -- detect_transition pulses when a new input is sampled and will also pulse if the input changes again while deglitching
// reset counter to zero
// else if (counter == FULL) -- has the counter his FULL count yet?
// reset counter to zero
// else
// increment the counter
// else -- this "else" matches with "if (deglitching)"
// -- when deglitching is no longer required - reset the counter to zero
// reset counter to zero
end
end
endmodule
| 7.629592 |
module altr_hps_gtieh (
output wire z_out // output
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign z_out = 1'b1;
`else
`endif
endmodule
| 7.255927 |
module altr_hps_gtiel (
output wire z_out // output
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign z_out = 1'b0;
`else
`endif
endmodule
| 7.255927 |
module altr_hps_gtie_generator #(
parameter TIE_WIDTH = 1,
parameter [TIE_WIDTH-1:0] TIE_VALUE = 'd0
) (
output wire [TIE_WIDTH-1 : 0] z_out // output
);
genvar i;
generate
for (i = 0; i < TIE_WIDTH; i = i + 1) begin : gtie
if (TIE_VALUE[i] == 1'b1) begin
// tie high
altr_hps_gtieh u_gtieh (.z_out(z_out[i]));
end else begin
// tie low
altr_hps_gtiel u_gtiel (.z_out(z_out[i]));
end // if
end // for
endgenerate // generate
endmodule
| 7.255927 |
module altr_hps_mux21 (
input wire mux_in0, // mux in 0
input wire mux_in1, // mux in 1
input wire mux_sel, // mux selector
output wire mux_out // mux out
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign mux_out = mux_sel ? mux_in1 : mux_in0;
`else
`endif
endmodule
| 7.182512 |
module altr_hps_mux41 (
input wire mux_in0, // mux in 0
input wire mux_in1, // mux in 1
input wire mux_in2, // mux in 1
input wire mux_in3, // mux in 1
input wire [1:0] mux_sel, // mux selector
output wire mux_out // mux out
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign mux_out = mux_sel[1] ? mux_sel[0] ? mux_in3 : mux_in2 : mux_sel[0] ? mux_in1 : mux_in0;
`else
`endif
endmodule
| 7.006293 |
module altr_hps_nand3 (
input wire nand_in1, // and input 1
input wire nand_in2, // and input 2
input wire nand_in3, // and input 3
output wire nand_out // and output
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign nand_out = ~(nand_in1 & nand_in2 & nand_in3);
`else
`endif
endmodule
| 7.093856 |
module altr_hps_nand4 (
input wire nand_in1, // and input 1
input wire nand_in2, // and input 2
input wire nand_in3, // and input 3
input wire nand_in4, // and input 4
output wire nand_out // and output
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign nand_out = ~(nand_in1 & nand_in2 & nand_in3 & nand_in4);
`else
`endif
endmodule
| 7.093856 |
module altr_hps_nor2 (
input wire nor_in1, // and input 1
input wire nor_in2, // and input 2
output wire nor_out // and output
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign nor_out = ~(nor_in1 | nor_in2);
`else
`endif
endmodule
| 7.668215 |
module altr_hps_nor3 (
input wire nor_in1, // and input 1
input wire nor_in2, // and input 2
input wire nor_in3, // and input 3
output wire nor_out // and output
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign nor_out = ~(nor_in1 | nor_in2 | nor_in3);
`else
`endif
endmodule
| 7.517618 |
module altr_hps_or (
input wire or_in1, // and input 1
input wire or_in2, // and input 2
output wire or_out // or output
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign or_out = or_in1 | or_in2;
`else
`endif
endmodule
| 7.650365 |
module altr_hps_rstnsync (
input wire clk, // Destination clock of reset to be synced
input wire i_rst_n, // Asynchronous reset input
input wire scan_mode, // Scan bypass for reset
output wire sync_rst_n // Synchronized reset output
);
reg first_stg_rst_n;
wire prescan_sync_rst_n;
always @(posedge clk or negedge i_rst_n)
if (!i_rst_n) first_stg_rst_n <= 1'b0;
else first_stg_rst_n <= 1'b1;
altr_hps_bitsync #(
.DWIDTH(1),
.RESET_VAL(0)
) i_sync_rst_n (
.clk (clk),
.rst_n (i_rst_n),
.data_in (first_stg_rst_n),
.data_out(prescan_sync_rst_n)
);
// Added scan bypass mux (Fogbugz #26486)
altr_hps_mux21 i_rstsync_mux (
.mux_in0(prescan_sync_rst_n),
.mux_in1(i_rst_n),
.mux_sel(scan_mode),
.mux_out(sync_rst_n)
);
endmodule
| 7.959119 |
module altr_hps_rstnsync4 (
input wire clk,
input wire i_rst_n,
input wire scan_mode,
output wire sync_rst_n
);
reg first_stg_rst_n;
wire prescan_sync_rst_n;
always @(posedge clk or negedge i_rst_n)
if (!i_rst_n) first_stg_rst_n <= 1'b0;
else first_stg_rst_n <= 1'b1;
altr_hps_bitsync4 #(
.DWIDTH(1),
.RESET_VAL(0)
) i_sync_rst_n (
.clk (clk),
.rst_n (i_rst_n),
.data_in (first_stg_rst_n),
.data_out(prescan_sync_rst_n)
);
// Added scan bypass mux (Fogbugz #26486)
altr_hps_mux21 i_rstsync_mux (
.mux_in0(prescan_sync_rst_n),
.mux_in1(i_rst_n),
.mux_sel(scan_mode),
.mux_out(sync_rst_n)
);
endmodule
| 7.959119 |
module altr_hps_sync_clr #(
parameter DWIDTH = 'd1
) (
input clk, //main clk signal
input rst_n, //main reset signal
input clr, //active high clear signal (expected this clear signal to be quasi-static)
input [DWIDTH-1:0] data_in, //data in
output [DWIDTH-1:0] data_out //data out
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
reg [DWIDTH-1:0] dff1;
reg [DWIDTH-1:0] dff2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
dff1 <= {DWIDTH{1'b0}};
dff2 <= {DWIDTH{1'b0}};
end else begin
dff1 <= data_in & ~clr;
dff2 <= dff1 & ~clr;
end
end
assign data_out = dff2;
`else
`endif
endmodule
| 7.152398 |
module altr_i2c_databuffer #(
parameter DSIZE = 8
) (
input clk,
input rst_n,
input s_rst, //Sync Reset - when Mode is disabled
input put,
input get,
output reg empty,
input [DSIZE-1:0] wdata,
output reg [DSIZE-1:0] rdata
);
//BUFFER storage
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rdata <= {DSIZE{1'b0}};
end else if (put) begin
rdata <= wdata;
end
end
//EMPTY Indicator
always @(posedge clk or negedge rst_n) begin
if (!rst_n) empty <= 1;
else begin
empty <= s_rst ? 1 : put ? 0 : get ? 1 : empty;
end
end
endmodule
| 8.145772 |
module altr_i2c_spksupp (
input i2c_clk,
input i2c_rst_n,
input [7:0] ic_fs_spklen,
input sda_in,
input scl_in,
output sda_int,
output scl_int
);
// Status Register bit definition
// wires & registers declaration
reg [7:0] scl_spike_cnt;
reg scl_int_reg;
reg scl_doublesync_a;
reg [7:0] sda_spike_cnt;
reg sda_int_reg;
reg sda_doublesync_a;
reg scl_in_synced;
reg sda_in_synced;
wire scl_clear_cnt;
wire scl_cnt_limit;
wire scl_int_next;
wire sda_clear_cnt;
wire sda_cnt_limit;
wire sda_int_next;
// double sync flops for scl
always @(posedge i2c_clk or negedge i2c_rst_n) begin
if (!i2c_rst_n) begin
scl_doublesync_a <= 1'b1;
scl_in_synced <= 1'b1;
end else begin
scl_doublesync_a <= scl_in;
scl_in_synced <= scl_doublesync_a;
end
end
//assign scl_in_synced = scl_doublesync_b;
// XOR: return 1 to increase counter ; return 0 to reset counter
assign scl_clear_cnt = ~(scl_in_synced ^ scl_int_next);
// scl counter
always @(posedge i2c_clk or negedge i2c_rst_n) begin
if (!i2c_rst_n) scl_spike_cnt <= 8'h0;
else if (scl_clear_cnt) scl_spike_cnt <= 8'h0;
else scl_spike_cnt <= scl_spike_cnt + 8'h1;
end
// to allow scl_in pass through to scl_int when the comparator returns 1
// if disallow to pass through, scl_int returns the prev value
// to make the scl_in pass through at the same clock as the counter reaching the limit value of suppression length
assign scl_cnt_limit = (scl_spike_cnt >= ic_fs_spklen);
always @(posedge i2c_clk or negedge i2c_rst_n) begin
if (!i2c_rst_n) scl_int_reg <= 1'b1;
else scl_int_reg <= scl_int_next;
end
assign scl_int_next = scl_cnt_limit ? scl_in_synced : scl_int_reg;
//assign scl_int = scl_cnt_limit ? scl_in_synced : scl_int_reg ;
assign scl_int = scl_int_reg; // Using the registered version to improve timing
// double sync flops for sda
always @(posedge i2c_clk or negedge i2c_rst_n) begin
if (!i2c_rst_n) begin
sda_doublesync_a <= 1'b1;
sda_in_synced <= 1'b1;
end else begin
sda_doublesync_a <= sda_in;
sda_in_synced <= sda_doublesync_a;
end
end
// assign sda_in_synced = sda_doublesync_b;
// XOR: return 1 to increase counter ; return 0 to reset counter
assign sda_clear_cnt = ~(sda_in_synced ^ sda_int_next);
// sda counter
always @(posedge i2c_clk or negedge i2c_rst_n) begin
if (!i2c_rst_n) sda_spike_cnt <= 8'h0;
else if (sda_clear_cnt) sda_spike_cnt <= 8'h0;
else sda_spike_cnt <= sda_spike_cnt + 8'h1;
end
// to allow scl_in pass through to scl_int when the comparator returns 1
// if disallow to pass through, scl_int returns the prev value
// to make the scl_in pass through at the same clock as the counter reaching the limit value of suppression length
assign sda_cnt_limit = (sda_spike_cnt >= ic_fs_spklen);
always @(posedge i2c_clk or negedge i2c_rst_n) begin
if (!i2c_rst_n) sda_int_reg <= 1'b1;
else sda_int_reg <= sda_int_next;
end
assign sda_int_next = sda_cnt_limit ? sda_in_synced : sda_int_reg;
//assign sda_int = sda_cnt_limit ? sda_in_synced : sda_int_reg ;
assign sda_int = sda_int_reg; // Using the registered version to improve timing
endmodule
| 7.569367 |
module altr_i2c_txout (
input i2c_clk,
input i2c_rst_n,
input [15:0] ic_sda_hold,
input start_sda_out,
input restart_sda_out,
input stop_sda_out,
input mst_tx_sda_out,
input mst_rx_sda_out,
input slv_tx_sda_out,
input slv_rx_sda_out,
input restart_scl_out,
input stop_scl_out,
input mst_tx_scl_out,
input mst_rx_scl_out,
input slv_tx_scl_out,
input pop_tx_fifo_state,
input pop_tx_fifo_state_dly,
input ic_slv_en,
input scl_edge_hl,
output i2c_data_oe,
output i2c_clk_oe
);
reg data_oe;
reg clk_oe;
reg clk_oe_nxt_dly;
reg [15:0] sda_hold_cnt;
reg [15:0] sda_hold_cnt_nxt;
wire data_oe_nxt;
wire clk_oe_nxt;
wire clk_oe_nxt_hl;
wire load_sda_hold_cnt;
wire sda_hold_en;
assign data_oe_nxt = ~start_sda_out |
~restart_sda_out |
~stop_sda_out |
~mst_tx_sda_out |
~mst_rx_sda_out |
~slv_tx_sda_out |
~slv_rx_sda_out;
assign clk_oe_nxt = ~restart_scl_out |
~stop_scl_out |
~mst_tx_scl_out |
~mst_rx_scl_out |
~slv_tx_scl_out;
assign clk_oe_nxt_hl = clk_oe_nxt & ~clk_oe_nxt_dly;
assign load_sda_hold_cnt = ic_slv_en ? scl_edge_hl : clk_oe_nxt_hl;
assign sda_hold_en = (sda_hold_cnt_nxt != 16'h0) | pop_tx_fifo_state | pop_tx_fifo_state_dly;
assign i2c_data_oe = data_oe;
assign i2c_clk_oe = clk_oe;
always @(posedge i2c_clk or negedge i2c_rst_n) begin
if (!i2c_rst_n) clk_oe_nxt_dly <= 1'b0;
else clk_oe_nxt_dly <= clk_oe_nxt;
end
always @(posedge i2c_clk or negedge i2c_rst_n) begin
if (!i2c_rst_n) data_oe <= 1'b0;
else if (sda_hold_en) data_oe <= data_oe;
else data_oe <= data_oe_nxt;
end
always @(posedge i2c_clk or negedge i2c_rst_n) begin
if (!i2c_rst_n) clk_oe <= 1'b0;
else if (pop_tx_fifo_state_dly) clk_oe <= clk_oe;
else clk_oe <= clk_oe_nxt;
end
always @(posedge i2c_clk or negedge i2c_rst_n) begin
if (!i2c_rst_n) sda_hold_cnt <= 16'h0;
else sda_hold_cnt <= sda_hold_cnt_nxt;
end
always @* begin
if (load_sda_hold_cnt) sda_hold_cnt_nxt = (ic_sda_hold - 16'h1);
else if (sda_hold_cnt != 16'h0) sda_hold_cnt_nxt = sda_hold_cnt - 16'h1;
else sda_hold_cnt_nxt = sda_hold_cnt;
end
endmodule
| 6.612108 |
module contains altsource_probe megafunction body
//************************************************************
///////////////////////////////////////////////////////////////////////////////
// Description : IP for Interactive Probe. Capture internal signals using the
// probe input, drive internal signals using the source output.
// The captured value and the input source value generated are
// transmitted through the JTAG interface.
///////////////////////////////////////////////////////////////////////////////
module altsource_probe
(
probe,
source,
source_clk,
source_ena,
raw_tck,
tdi,
usr1,
jtag_state_cdr,
jtag_state_sdr,
jtag_state_e1dr,
jtag_state_udr,
jtag_state_cir,
jtag_state_uir,
jtag_state_tlr,
clr,
ena,
ir_in,
ir_out,
tdo
);
parameter lpm_type = "altsource_probe"; // required by the coding standard
parameter lpm_hint = "UNUSED"; // required by the coding standard
parameter sld_auto_instance_index = "YES"; // Yes, if the instance index should be automatically assigned.
parameter sld_instance_index = 0; // unique identifier for the altsource_probe instance.
parameter SLD_NODE_INFO = 4746752 + sld_instance_index; // The NODE ID to uniquely identify this node on the hub. Type ID: 9 Version: 0 Inst: 0 MFG ID 110 @no_decl
parameter sld_ir_width = 4; // @no_decl
parameter instance_id = "UNUSED"; // optional name for the instance.
parameter probe_width = 1; // probe port width
parameter source_width= 1; // source port width
parameter source_initial_value = "0"; // initial source port value
parameter enable_metastability = "NO"; // yes to add two registe
input [probe_width - 1 : 0] probe; // probe inputs
output [source_width - 1 : 0] source; // source outputs
input source_clk; // clock of the registers used to metastabilize the source output
input tri1 source_ena; // enable of the registers used to metastabilize the source output
input raw_tck; // Real TCK from the JTAG HUB. @no_decl
input tdi; // TDI from the JTAG HUB. It gets the data from JTAG TDI. @no_decl
input usr1; // USR1 from the JTAG HUB. Indicate whether it is in USER1 or USER0 @no_decl
input jtag_state_cdr; // CDR from the JTAG HUB. Indicate whether it is in Capture_DR state. @no_decl
input jtag_state_sdr; // SDR from the JTAG HUB. Indicate whether it is in Shift_DR state. @no_decl
input jtag_state_e1dr; // EDR from the JTAG HUB. Indicate whether it is in Exit1_DR state. @no_decl
input jtag_state_udr; // UDR from the JTAG HUB. Indicate whether it is in Update_DR state. @no_decl
input jtag_state_cir; // CIR from the JTAG HUB. Indicate whether it is in Capture_IR state. @no_decl
input jtag_state_uir; // UIR from the JTAG HUB. Indicate whether it is in Update_IR state. @no_decl
input jtag_state_tlr; // UIR from the JTAG HUB. Indicate whether it is in Test_Logic_Reset state. @no_decl
input clr; // CLR from the JTAG HUB. Indicate whether hub requests global reset. @no_decl
input ena; // ENA from the JTAG HUB. Indicate whether this node should establish JTAG chain. @no_decl
input [sld_ir_width - 1 : 0] ir_in; // IR_OUT from the JTAG HUB. It hold the current instruction for the node. @no_decl
output [sld_ir_width - 1 : 0] ir_out; // IR_IN to the JTAG HUB. It supplies the updated value for IR_IN. @no_decl
output tdo; //TDO to the JTAG HUB. It supplies the data to JTAG TDO. @no_decl
assign tdo = 1'b0;
assign ir_out = 1'b0;
assign source = 1'b0;
endmodule
| 7.039347 |
module altsource_probe_top #(
parameter lpm_type = "altsource_probe", // required by the coding standard
parameter lpm_hint = "UNUSED", // required by the coding standard
parameter sld_auto_instance_index = "YES", // Yes, if the instance index should be automatically assigned.
parameter sld_instance_index = 0, // unique identifier for the altsource_probe instance.
parameter sld_node_info_parameter = 4746752 + sld_instance_index, // The NODE ID to uniquely identify this node on the hub. Type ID: 9 Version: 0 Inst: 0 MFG ID 110 -- ***NOTE*** this parameter cannot be called SLD_NODE_INFO or Quartus Standard will think it's an ISSP impl.
parameter sld_ir_width = 4,
parameter instance_id = "UNUSED", // optional name for the instance.
parameter probe_width = 1, // probe port width
parameter source_width = 1, // source port width
parameter source_initial_value = "0", // initial source port value
parameter enable_metastability = "NO" // yes to add two register
) (
input [probe_width - 1 : 0] probe, // probe inputs
output [source_width - 1 : 0] source, // source outputs
input source_clk, // clock of the registers used to metastabilize the source output
input tri1 source_ena // enable of the registers used to metastabilize the source output
);
altsource_probe #(
.lpm_type(lpm_type),
.lpm_hint(lpm_hint),
.sld_auto_instance_index(sld_auto_instance_index),
.sld_instance_index(sld_instance_index),
.SLD_NODE_INFO(sld_node_info_parameter),
.sld_ir_width(sld_ir_width),
.instance_id(instance_id),
.probe_width(probe_width),
.source_width(source_width),
.source_initial_value(source_initial_value),
.enable_metastability(enable_metastability)
) issp_impl (
.probe(probe),
.source(source),
.source_clk(source_clk),
.source_ena(source_ena)
);
endmodule
| 8.012029 |
module is a parametrized dual port ram with a registered output port
It is optional to define it's input address and output address and it's
depth.
REVISION HISTORY
05FEB03 First Created -ac-
*******************************************************************************/
module altsyncram3
(
data,
byteena,
rd_aclr,
rdaddress,
rdclock,
rdclocken,
rden,
wraddress,
wrclock,
wrclocken,
wren,
q);
parameter A_WIDTH = 288;
parameter A_WIDTHAD = 9;
parameter B_WIDTH = A_WIDTH;
parameter B_WIDTHAD = A_WIDTHAD;
parameter A_NUMWORDS = 1<<A_WIDTHAD;
parameter B_NUMWORDS = 1<<B_WIDTHAD;
parameter RAM_TYPE = "AUTO";
parameter BYTE_ENA = 1;
parameter USE_RDEN = 1;
parameter TYPE = RAM_TYPE == "M4K" | RAM_TYPE == "M9K"? "M9K":
RAM_TYPE == "M512" | RAM_TYPE == "MLAB"? "MLAB":
RAM_TYPE == "M-RAM" | RAM_TYPE == "M144K"? "M144K":
"AUTO";
parameter REG_B = "CLOCK1";
input [A_WIDTH-1:0] data;
input [BYTE_ENA-1 :0] byteena;
input rd_aclr;
input [B_WIDTHAD-1:0] rdaddress;
input rdclock;
input rdclocken;
input rden;
input [A_WIDTHAD-1:0] wraddress;
input wrclock;
input wrclocken;
input wren;
output [B_WIDTH-1:0] q;
wire [B_WIDTH-1:0] sub_wire0;
wire [B_WIDTH-1:0] q = sub_wire0[B_WIDTH-1:0];
wire [BYTE_ENA-1 :0] byteena_wire = BYTE_ENA==1 ? 1'b1 : byteena;
wire rden_wire = USE_RDEN ? rden : 1'b1;
altsyncram altsyncram_component (
.clocken0(wrclocken),
.clocken1(rdclocken),
.wren_a(wren),
.clock0(wrclock),
.aclr1 (rd_aclr),
.clock1(rdclock),
.address_a(wraddress),
.address_b(rdaddress),
.rden_b(rden_wire),
.data_a(data),
.q_b(sub_wire0),
.aclr0 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (byteena_wire),
.byteena_b (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({B_WIDTH{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "CLEAR1",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_input_b = "NORMAL",
altsyncram_component.clock_enable_output_b = "NORMAL",
altsyncram_component.intended_device_family = "Stratix III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = A_NUMWORDS,
altsyncram_component.numwords_b = B_NUMWORDS,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "CLEAR1",
altsyncram_component.outdata_reg_b = REG_B,
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = TYPE,
altsyncram_component.rdcontrol_reg_b = "CLOCK1",
altsyncram_component.widthad_a = A_WIDTHAD,
altsyncram_component.widthad_b = B_WIDTHAD,
altsyncram_component.width_a = A_WIDTH,
altsyncram_component.width_b = B_WIDTH,
altsyncram_component.width_byteena_a = BYTE_ENA;
endmodule
| 7.877064 |
module alt_a10_temp_sense (
input clk,
output reg [7:0] degrees_c,
output reg [7:0] degrees_f
);
// WYS connection to sense diode ADC
wire [9:0] tsd_out;
// make sure it actually routes, out of caution for flakey new port connections
wire trst = 1'b0 /* synthesis keep */;
wire corectl = 1'b1 /* synthesis keep */;
twentynm_tsdblock tsd (
.corectl(corectl),
.reset(trst),
.tempout(tsd_out),
.eoc()
);
wire [9:0] tsd_out_s;
alt_sync_regs_m2 sr0 (
.clk (clk),
.din (tsd_out),
.dout(tsd_out_s)
);
defparam sr0.WIDTH = 10;
// convert valid samples to better format
reg [12:0] p0 = 13'h0;
reg [10:0] p1 = 11'h0;
reg [14:0] scaled_tsd = 15'h0;
always @(posedge clk) begin
// NPP says Temp = val * (706 / 1024) - 275
// that fraction is 1/2 + 1/8 + 1/16 + 1/512
p0 <= {1'b0, tsd_out_s, 2'b0} + {3'b0, tsd_out_s};
p1 <= {1'b0, tsd_out_s} + {6'b0, tsd_out_s[9:5]};
scaled_tsd <= {1'b0, p0, 1'b0} + {4'b0, p1};
end
reg [14:0] scaled_ofs_tsd = 15'h0;
always @(posedge clk) begin
scaled_ofs_tsd <= scaled_tsd - {9'd275, 4'b0};
end
initial degrees_c = 0;
always @(posedge clk) begin
degrees_c <= scaled_ofs_tsd[11:4];
end
// F = C * 1.8 + 32
wire [9:0] fscaled;
alt_times_1pt8 at0 (
.clk (clk),
.din (scaled_ofs_tsd[11:2]),
.dout(fscaled)
);
defparam at0.WIDTH = 10;
initial degrees_f = 0;
always @(posedge clk) begin
degrees_f <= fscaled[9:2] + 8'd32;
end
endmodule
| 7.233031 |
module alt_and3t1 #(
parameter SIM_EMULATE = 1'b0
) (
input clk,
input [2:0] din,
output dout
);
wire dout_w;
alt_and3t0 c0 (
.din (din),
.dout(dout_w)
);
defparam c0.SIM_EMULATE = SIM_EMULATE;
reg dout_r = 1'b0;
always @(posedge clk) dout_r <= dout_w;
assign dout = dout_r;
endmodule
| 6.673592 |
module alt_bcd_counter (
input clk,
rst_n,
input go,
output reg [3:0] s1,
s0,
ms0
);
reg [22:0] counter_reg = 0;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
s1 <= 0;
s0 <= 0;
ms0 <= 0;
counter_reg <= 0;
end else if (go) begin //nested-if for describing the BCD-counter
if (counter_reg != 4_999_999) counter_reg <= counter_reg + 1;
else begin
counter_reg <= 0;
if (ms0 != 9) ms0 <= ms0 + 1;
else begin
ms0 <= 0;
if (s0 != 9) s0 <= s0 + 1;
else begin
s0 <= 0;
if (s1 != 9) s1 <= s1 + 1;
else s1 <= 0;
end
end
end
end
end
endmodule
| 6.52275 |
module alt_db_fsm (
input wire clk,
reset,
input wire sw,
output reg db
);
// symbolic state declaration
localparam[2:0]
zero = 3'b000,
wait1_1 = 3'b001,
wait1_2 = 3'b010,
wait1_3 = 3'b011,
one = 3'b100,
wait0_1 = 3'b101,
wait0_2 = 3'b110,
wait0_3 = 3'b111;
// number of counter bits (2^N * 10 ns = 10 ms tick
localparam N = 20;
// signal declaration
reg [N-1:0] q_reg = 0;
wire [N-1:0] q_next;
wire m_tick;
reg [2:0] state_reg, state_next;
// body
//=================================
// counter to generate 10 ms tick
//=================================
always @(posedge clk) q_reg <= q_next;
// next state logic
assign q_next = q_reg + 1;
// output logic
assign m_tick = (q_reg == 0) ? 1'b1 : 1'b0;
//=================================
// counter to generate 10 ms tick
//=================================
// state register
always @(posedge clk, posedge reset)
if (reset) state_reg <= zero;
else state_reg <= state_next;
// next-state logic and output logic
always @* begin
state_next = state_reg; // default state: the same
db = 1'b0; // default output: 0
case (state_reg)
zero:
if (sw) begin
db = 1'b1; // output is set with first rising edge
state_next = wait1_1;
end
wait1_1: begin
db = 1'b1;
if (m_tick) state_next = wait1_2;
end
wait1_2: begin
db = 1'b1;
if (m_tick) state_next = wait1_3;
end
wait1_3: begin
db = 1'b1;
// confirm press or go back to state zero
if (m_tick)
if (sw) state_next = one;
else state_next = zero;
end
one: begin
db = 1'b1;
if (~sw) begin
db = 1'b0;
state_next = wait0_1;
end
end
wait0_1: if (m_tick) state_next = wait0_2;
wait0_2: if (m_tick) state_next = wait0_3;
wait0_3:
// confirm depress or go back to state one
if (m_tick)
if (~sw) state_next = zero;
else state_next = one;
endcase
end
endmodule
| 7.057655 |
module alt_db_fsm_tb;
// signal declaration
localparam T = 10; // clk period
reg clk, reset;
reg sw;
wire db;
// instance of uut
alt_db_fsm uut (
.clk(clk),
.reset(reset),
.sw(sw),
.db(db)
);
// clock
always begin
clk = 1'b0;
#(T / 2);
clk = 1'b1;
#(T / 2);
end
// reset
initial begin
reset = 1'b1;
#(T / 2);
reset = 1'b0;
end
// test vector
initial begin
sw = 1'b0;
repeat (3) @(negedge clk);
#(T / 4); // sw changes outside of clock edge
sw = 1'b1;
// simulate bouncing on rising
#(1000 * T);
sw = 1'b0;
#(1000 * T);
sw = 1'b1;
#(1000 * T);
sw = 1'b0;
#(1000 * T);
sw = 1'b1;
// wait for 100 ms
#100000000;
#(T / 4); // sw changes outside of clock edge
sw = 1'b0;
// simulate bouncing on falling
#(1000 * T);
sw = 1'b1;
#(1000 * T);
sw = 1'b0;
#(1000 * T);
sw = 1'b1;
#(1000 * T);
sw = 1'b0;
// wait for 20 + 10 ms
#30000000;
$stop;
end
endmodule
| 7.462 |
module alt_ddr (
input wire outclock, // outclock.export
input wire [1:0] din, // din.export
output wire [0:0] pad_out // pad_out.export
);
altera_gpio_lite #(
.PIN_TYPE ("output"),
.SIZE (1),
.REGISTER_MODE ("ddr"),
.BUFFER_TYPE ("single-ended"),
.ASYNC_MODE ("none"),
.SYNC_MODE ("none"),
.BUS_HOLD ("false"),
.OPEN_DRAIN_OUTPUT ("false"),
.ENABLE_OE_PORT ("false"),
.ENABLE_NSLEEP_PORT ("false"),
.ENABLE_CLOCK_ENA_PORT ("false"),
.SET_REGISTER_OUTPUTS_HIGH ("false"),
.INVERT_OUTPUT ("false"),
.INVERT_INPUT_CLOCK ("false"),
.USE_ONE_REG_TO_DRIVE_OE ("false"),
.USE_DDIO_REG_TO_DRIVE_OE ("false"),
.USE_ADVANCED_DDR_FEATURES ("false"),
.USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY("false"),
.ENABLE_OE_HALF_CYCLE_DELAY ("true"),
.INVERT_CLKDIV_INPUT_CLOCK ("false"),
.ENABLE_PHASE_INVERT_CTRL_PORT ("false"),
.ENABLE_HR_CLOCK ("false"),
.INVERT_OUTPUT_CLOCK ("false"),
.INVERT_OE_INCLOCK ("false"),
.ENABLE_PHASE_DETECTOR_FOR_CK ("false")
) alt_ddr_inst (
.outclock (outclock), // outclock.export
.din (din), // din.export
.pad_out (pad_out), // pad_out.export
.outclocken (1'b1), // (terminated)
.inclock (1'b0), // (terminated)
.inclocken (1'b0), // (terminated)
.fr_clock (), // (terminated)
.hr_clock (), // (terminated)
.invert_hr_clock(1'b0), // (terminated)
.phy_mem_clock (1'b0), // (terminated)
.mimic_clock (), // (terminated)
.dout (), // (terminated)
.pad_io (), // (terminated)
.pad_io_b (), // (terminated)
.pad_in (1'b0), // (terminated)
.pad_in_b (1'b0), // (terminated)
.pad_out_b (), // (terminated)
.aset (1'b0), // (terminated)
.aclr (1'b0), // (terminated)
.sclr (1'b0), // (terminated)
.nsleep (1'b0), // (terminated)
.oe (1'b0) // (terminated)
);
endmodule
| 6.520382 |
module (RAM) is not used anymore, this will be commented for future reference
// which will instantiate ram modules
module alt_ddrx_bank_mem #
( parameter
MEM_IF_CS_WIDTH = 4,
MEM_IF_CHIP_BITS = 2,
MEM_IF_BA_WIDTH = 3,
MEM_IF_ROW_WIDTH = 16
)
(
ctl_clk,
ctl_reset_n,
// Write Interface
write_req,
write_addr,
write_data,
// Read Interface
read_addr,
read_data
);
localparam RAM_ADDR_WIDTH = 5;
input ctl_clk;
input ctl_reset_n;
input [MEM_IF_CS_WIDTH - 1 : 0] write_req;
input [MEM_IF_BA_WIDTH - 1 : 0] write_addr;
input [MEM_IF_ROW_WIDTH - 1 : 0] write_data;
input [MEM_IF_BA_WIDTH - 1 : 0] read_addr;
output [(MEM_IF_CS_WIDTH * MEM_IF_ROW_WIDTH) - 1 : 0] read_data;
wire [(MEM_IF_CS_WIDTH * MEM_IF_ROW_WIDTH) - 1 : 0] read_data;
generate
genvar z;
for (z = 0;z < MEM_IF_CS_WIDTH;z = z + 1)
begin : ram_inst_per_chip
ram ram_inst
(
.clock (ctl_clk),
.wren (write_req [z]),
.wraddress ({{(RAM_ADDR_WIDTH - MEM_IF_BA_WIDTH){1'b0}}, write_addr}),
.data (write_data),
.rdaddress ({{(RAM_ADDR_WIDTH - MEM_IF_BA_WIDTH){1'b0}}, read_addr [MEM_IF_BA_WIDTH - 1 : 0]}),
.q (read_data [(z + 1) * MEM_IF_ROW_WIDTH - 1 : z * MEM_IF_ROW_WIDTH])
);
end
endgenerate
endmodule
| 6.91058 |
module alt_ddrx_clock_and_reset #(
parameter DWIDTH_RATIO = "2"
) (
// Inputs
ctl_full_clk,
ctl_half_clk,
ctl_quater_clk,
//csr_clk,
reset_phy_clk_n,
// Outputs
ctl_clk,
ctl_reset_n
);
input ctl_full_clk;
input ctl_half_clk;
input ctl_quater_clk;
//input csr_clk;
input reset_phy_clk_n;
output ctl_clk;
output ctl_reset_n;
wire ctl_clk;
wire ctl_reset_n = reset_phy_clk_n;
generate
if (DWIDTH_RATIO == 2) // fullrate
assign ctl_clk = ctl_full_clk;
else if (DWIDTH_RATIO == 4) // halfrate
assign ctl_clk = ctl_half_clk;
endgenerate
endmodule
| 6.957515 |
module alt_ddrx_ddr3_odt_gen #(
parameter DWIDTH_RATIO = 2,
TCL_BUS_WIDTH = 4,
CAS_WR_LAT_BUS_WIDTH = 4
) (
ctl_clk,
ctl_reset_n,
mem_tcl,
mem_cas_wr_lat,
do_write,
do_read,
int_odt_l,
int_odt_h
);
input ctl_clk;
input ctl_reset_n;
input [TCL_BUS_WIDTH-1:0] mem_tcl;
input [CAS_WR_LAT_BUS_WIDTH-1:0] mem_cas_wr_lat;
input do_write;
input do_read;
output int_odt_l;
output int_odt_h;
wire do_write;
wire int_do_read;
reg do_read_r;
wire [3:0] diff_unreg; // difference between CL and CWL
reg [3:0] diff;
reg int_odt_l_int;
reg int_odt_l_int_r;
wire int_odt_l;
wire int_odt_h;
reg [2:0] doing_write_count;
reg [2:0] doing_read_count;
// AL also applies to ODT signal so ODT logic is AL agnostic
// also regdimm because ODT is registered too
// ODTLon = CWL + AL - 2
// ODTLoff = CWL + AL - 2
assign diff_unreg = mem_tcl - mem_cas_wr_lat;
assign int_do_read = (diff > 1) ? do_read_r : do_read;
generate
if (DWIDTH_RATIO == 2) // full rate
begin
assign int_odt_h = int_odt_l_int;
assign int_odt_l = int_odt_l_int;
end else // half rate
begin
assign int_odt_h = int_odt_l_int | do_write | (int_do_read & ~|diff);
assign int_odt_l = int_odt_l_int | int_odt_l_int_r;
end
endgenerate
always @(posedge ctl_clk, negedge ctl_reset_n) begin
if (!ctl_reset_n) diff <= 0;
else diff <= diff_unreg;
end
always @(posedge ctl_clk, negedge ctl_reset_n) begin
if (!ctl_reset_n) do_read_r <= 0;
else do_read_r <= do_read;
end
always @(posedge ctl_clk, negedge ctl_reset_n) begin
if (!ctl_reset_n) doing_write_count <= 0;
else if (do_write) doing_write_count <= 1;
else if ((DWIDTH_RATIO == 2 && doing_write_count == 4) || (DWIDTH_RATIO != 2 && doing_write_count == 1))
doing_write_count <= 0;
else if (doing_write_count > 0) doing_write_count <= doing_write_count + 1'b1;
end
always @(posedge ctl_clk, negedge ctl_reset_n) begin
if (!ctl_reset_n) doing_read_count <= 0;
else if (int_do_read) doing_read_count <= 1;
else if ((DWIDTH_RATIO == 2 && doing_read_count == 4) || (DWIDTH_RATIO != 2 && doing_read_count == 1))
doing_read_count <= 0;
else if (doing_read_count > 0) doing_read_count <= doing_read_count + 1'b1;
end
always @(posedge ctl_clk, negedge ctl_reset_n) begin
if (!ctl_reset_n) int_odt_l_int <= 1'b0;
else if (do_write || int_do_read) int_odt_l_int <= 1'b1;
else if (doing_write_count > 0 || doing_read_count > 0) int_odt_l_int <= 1'b1;
else int_odt_l_int <= 1'b0;
end
always @(posedge ctl_clk, negedge ctl_reset_n) begin
if (!ctl_reset_n) int_odt_l_int_r <= 1'b0;
else int_odt_l_int_r <= int_odt_l_int;
end
endmodule
| 7.472813 |
module alt_debounce (
input wire clk,
reset,
input wire sw,
output reg db_level,
db_tick
);
// symbolic state declaration
localparam [1:0] zero = 2'b00, wait0 = 2'b01, one = 2'b10, wait1 = 2'b11;
// number of counter bits (2^N * 10 ns = 40 ms)
localparam N = 22;
// signal declaration
reg [N-1:0] q_reg, q_next;
reg [1:0] state_reg, state_next;
// body
// fsmd state and data registers
always @(posedge clk, posedge reset)
if (reset) begin
state_reg <= zero;
q_reg <= 0;
end else begin
state_reg <= state_next;
q_reg <= q_next;
end
// next-state logic and data path functional units/routing
always @* begin
state_next = state_reg;
q_next = q_reg;
db_tick = 1'b0;
db_level = 1'b0;
case (state_reg)
zero: begin
if (sw) begin
state_next = wait1;
q_next = {N{1'b1}}; // load 1..1
db_level = 1'b1;
end
end
wait1: begin
db_level = 1'b1;
if (sw) begin
q_next = q_reg - 1;
if (q_next == 0) begin
state_next = one;
db_tick = 1'b1;
end
end else // sw == 0
state_next = zero;
end
one: begin
if (~sw) begin
state_next = wait0;
q_next = {N{1'b1}}; // load 1..1
db_level = 1'b0;
end else db_level = 1'b1;
end
wait0: begin
if (~sw) begin
q_next = q_reg - 1;
if (q_next == 0) state_next = zero;
end else // sw == 1
state_next = one;
end
default: state_next = zero;
endcase
end
endmodule
| 7.211802 |
module alt_debounce_fsmd_test (
input wire clk,
reset,
input wire [1:0] btn,
output wire [3:0] an,
output wire [7:0] sseg
);
// signal declaration
reg [7:0] b_reg, d_reg;
wire [7:0] b_next, d_next;
reg btn_reg;
wire db_tick, btn_tick, clr;
// instantiate display circuit
disp_hex_mux disp_unit (
.clk(clk),
.reset(reset),
.hex3(b_reg[7:4]),
.hex2(b_reg[3:0]),
.hex1(d_reg[7:4]),
.hex0(d_reg[3:0]),
.dp_in(4'b1011),
.an(an),
.sseg(sseg)
);
// instantiate debouncing circuit
alt_debounce db_unit (
.clk(clk),
.reset(reset),
.sw(btn[1]),
.db_level(),
.db_tick(db_tick)
);
// edge detection circuit for un-debounced input
always @(posedge clk) btn_reg <= btn[1];
assign btn_tick = ~btn_reg & btn[1];
// two counters
assign clr = btn[0];
always @(posedge clk) begin
d_reg <= d_next;
b_reg <= b_next;
end
// next-state logic for the counter
assign b_next = (clr) ? 0 : (btn_tick) ? b_reg + 1 : b_reg;
assign d_next = (clr) ? 0 : (db_tick) ? d_reg + 1 : d_reg;
endmodule
| 8.656287 |
module alt_delay_dynamic_m20k #(
parameter WIDTH = 16,
parameter ADDR_WIDTH = 10
)(
input clk,
input [ADDR_WIDTH-1:0] delta,
input din_valid,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout
);
reg [ADDR_WIDTH-1:0] waddr = {ADDR_WIDTH{1'b0}};
reg [ADDR_WIDTH-1:0] raddr = {ADDR_WIDTH{1'b0}};
always @(posedge clk) begin
if (din_valid) begin
raddr <= raddr + 1'b1;
waddr <= raddr + delta;
end
end
wire [WIDTH-1:0] q;
altsyncram altsyncram_component (
.address_a (waddr[ADDR_WIDTH-1:0]),
.clock0 (clk),
.data_a (din),
.wren_a (1'b1),
.address_b (raddr[ADDR_WIDTH-1:0]),
.q_b (q),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({WIDTH{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.enable_ecc = "FALSE",
altsyncram_component.intended_device_family = "Stratix V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = (1 << ADDR_WIDTH),
altsyncram_component.numwords_b = (1 << ADDR_WIDTH),
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M20K",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = ADDR_WIDTH,
altsyncram_component.widthad_b = ADDR_WIDTH,
altsyncram_component.width_a = WIDTH,
altsyncram_component.width_b = WIDTH,
altsyncram_component.width_byteena_a = 1;
reg [WIDTH-1:0] dout_r = {WIDTH{1'b0}};
reg din_valid_r;
always @(posedge clk) din_valid_r <= din_valid;
always @(posedge clk) begin
if (din_valid_r) dout_r <= q;
end
assign dout = dout_r;
endmodule
| 6.752459 |
module alt_descrambler #(
parameter WIDTH = 512,
parameter OFS = 0 // debug shift
) (
input clk,
srst,
ena,
input [WIDTH-1:0] din, // bit 0 is used first
output reg [WIDTH-1:0] dout
);
reg [2*WIDTH-1:0] lag_din = 0;
always @(posedge clk) begin
if (srst) lag_din <= {2 * WIDTH{1'b0}};
else if (ena) lag_din <= {din, lag_din[2*WIDTH-1:WIDTH]};
end
reg [57:0] scram_state;
wire [WIDTH+58-1:0] history;
wire [WIDTH-1:0] dout_w;
assign history = {lag_din[OFS+WIDTH-1:OFS], scram_state};
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : lp
assign dout_w[i] = history[58+i-58] ^ history[58+i-39] ^ history[58+i];
end
endgenerate
always @(posedge clk) begin
if (srst) begin
dout <= 0;
scram_state <= 58'h3ff_ffff_ffff_ffff;
end else if (ena) begin
dout <= dout_w;
scram_state <= history[WIDTH+58-1:WIDTH];
end
end
endmodule
| 7.495298 |
module alt_fmon8 #(
parameter SIM_HURRY = 1'b0,
parameter SIM_EMULATE = 1'b0
) (
input clk,
input [7:0] din,
input [2:0] din_sel,
output [15:0] dout,
output dout_fresh
);
////////////////////////////
// divide down and cross domain
wire [7:0] prescale;
wire [7:0] prescale_s;
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : lp0
wire [5:0] local_cnt;
alt_cnt6 ct0 (
.clk (din[i]),
.dout(local_cnt)
);
defparam ct0.SIM_EMULATE = SIM_EMULATE;
assign prescale[i] = local_cnt[5];
alt_sync1r1 sn0 (
.din_clk(din[i]),
.din(prescale[i]),
.dout_clk(clk),
.dout(prescale_s[i])
);
defparam sn0.SIM_EMULATE = SIM_EMULATE;
end
endgenerate
////////////////////////////
// select signal to watch
wire sel_prescale;
alt_mux8w1t2s1 mx0 (
.clk (clk),
.din (prescale_s),
.sel (din_sel),
.dout(sel_prescale)
);
defparam mx0.SIM_EMULATE = SIM_EMULATE;
reg last_sel_prescale = 1'b0;
always @(posedge clk) last_sel_prescale <= sel_prescale;
reg ping = 1'b0;
always @(posedge clk) ping <= sel_prescale ^ last_sel_prescale;
////////////////////////////
// count selected signal
wire sclr;
alt_ripple16 rp0 (
.clk (clk),
.sclr(sclr),
.inc (ping),
.dout(dout)
);
defparam rp0.SIM_EMULATE = SIM_EMULATE;
////////////////////////////
// regular measuring interval
generate
if (SIM_HURRY) begin
// times 100 KHz
alt_metronome32000 mt0 (
.clk (clk),
.sclr(1'b0),
.dout(sclr)
);
defparam mt0.SIM_EMULATE = SIM_EMULATE;
end else begin
// times 10 KHz
alt_metronome320000 mt0 (
.clk (clk),
.sclr(1'b0),
.dout(sclr)
);
defparam mt0.SIM_EMULATE = SIM_EMULATE;
end
endgenerate
assign dout_fresh = sclr;
endmodule
| 8.11264 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module alt_ifconv #(
// parameters
parameter WIDTH = 1,
parameter INTERFACE_NAME_IN = "input-interface-name",
parameter INTERFACE_NAME_OUT = "output-interface-name",
parameter SIGNAL_NAME_IN = "input-signal-name",
parameter SIGNAL_NAME_OUT = "output-signal-name") (
// bad tools - ugly stuff
input [(WIDTH-1):0] din,
output [(WIDTH-1):0] dout);
// avoiding qsys signal conflicts
assign dout = din;
endmodule
| 8.180735 |
module alt_invert (
inA,
A
);
parameter n = 8;
// Assigning ports as in/out
input [n-1 : 0] inA;
output [n-1 : 0] A;
genvar i;
generate
for (i = 0; i < n; i = i + 1) begin : l1
if (i % 2 == 0) assign A[i] = ~inA[i];
else assign A[i] = inA[i];
end
endgenerate
endmodule
| 8.024698 |
module alt_iobuf
(
`IOB_INPUT(i, 1),
`IOB_INPUT(oe, 1),
`IOB_OUTPUT(o, 1),
`IOB_INOUT(io, 1)
);
assign io = oe? i : 1'bz;
assign o = io;
endmodule
| 6.918813 |
module alt_lfsr_client_40b #(
parameter SEED = 32'h12345678
) (
input clk_tx,
input srst_tx,
output [39:0] tx_sample, // lsbit first
input clk_rx,
input srst_rx,
input [39:0] rx_sample, // lsbit first
output [3:0] err_cnt
);
localparam WIDTH = 40;
// send scrambled 0's
alt_scrambler sc (
.clk (clk_tx),
.srst(srst_tx),
.ena (1'b1),
.din ({WIDTH{1'b0}}), // bit 0 is to be sent first
.dout(tx_sample)
);
defparam sc.WIDTH = WIDTH;
defparam sc.SCRAM_INIT = 58'h3ff_ffff_ffff_ffff ^ {SEED[15:0], SEED[31:0]};
wire [WIDTH-1:0] rx_dsc;
alt_descrambler ds (
.clk (clk_rx),
.srst(srst_rx),
.ena (1'b1),
.din (rx_sample), // bit 0 is used first
.dout(rx_dsc)
);
defparam ds.WIDTH = WIDTH;
// when working properly it should descramble to all 0's
wire rx_err;
alt_or_r oo (
.clk (clk_rx),
.din (rx_dsc),
.dout(rx_err)
);
defparam oo.WIDTH = WIDTH;
reg [3:0] err_cnt_r = 4'b0;
always @(posedge clk_rx) begin
if (srst_rx) err_cnt_r <= 4'b0;
else err_cnt_r <= err_cnt_r + rx_err;
end
assign err_cnt = err_cnt_r;
endmodule
| 7.043769 |
module alt_mem_asym #(
parameter A_ADDRESS_WIDTH = 0,
parameter A_DATA_WIDTH = 128,
parameter B_ADDRESS_WIDTH = 10,
parameter B_DATA_WIDTH = 128
) (
input wire [127:0] data_datain, // data.datain
output wire [127:0] mem_o_dataout, // mem_o.dataout
input wire [ 9:0] wraddress_wraddress, // wraddress.wraddress
input wire [ 9:0] rdaddress_rdaddress, // rdaddress.rdaddress
input wire wren_wren, // wren.wren
input wire wrclock_clk, // wrclock.clk
input wire rdclock_clk // rdclock.clk
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (A_ADDRESS_WIDTH != 0) begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above a_address_width_check (
.error(1'b1)
);
end
if (A_DATA_WIDTH != 128) begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above a_data_width_check (.error(1'b1));
end
if (B_ADDRESS_WIDTH != 10) begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above b_address_width_check (
.error(1'b1)
);
end
if (B_DATA_WIDTH != 128) begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above b_data_width_check (.error(1'b1));
end
endgenerate
ad9680_fifo_alt_mem_asym_10_ngt5uda #(
.A_ADDRESS_WIDTH(0),
.A_DATA_WIDTH (128),
.B_ADDRESS_WIDTH(10),
.B_DATA_WIDTH (128)
) alt_mem_asym (
.data_datain (data_datain), // input, width = 128, data.datain
.mem_o_dataout (mem_o_dataout), // output, width = 128, mem_o.dataout
.wraddress_wraddress(wraddress_wraddress), // input, width = 10, wraddress.wraddress
.rdaddress_rdaddress(rdaddress_rdaddress), // input, width = 10, rdaddress.rdaddress
.wren_wren (wren_wren), // input, width = 1, wren.wren
.wrclock_clk (wrclock_clk), // input, width = 1, wrclock.clk
.rdclock_clk (rdclock_clk) // input, width = 1, rdclock.clk
);
endmodule
| 7.029251 |
module alt_mem_asym_bypass #(
parameter A_ADDRESS_WIDTH = 10,
parameter A_DATA_WIDTH = 128,
parameter B_ADDRESS_WIDTH = 10,
parameter B_DATA_WIDTH = 128
) (
input wire [127:0] mem_i_datain, // mem_i.datain
input wire [ 9:0] mem_i_wraddress, // .wraddress
input wire [ 9:0] mem_i_rdaddress, // .rdaddress
input wire mem_i_wren, // .wren
input wire mem_i_wrclock, // .wrclock
input wire mem_i_rdclock, // .rdclock
output wire [127:0] mem_o_dataout // mem_o.dataout
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (A_ADDRESS_WIDTH != 10) begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above a_address_width_check (
.error(1'b1)
);
end
if (A_DATA_WIDTH != 128) begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above a_data_width_check (.error(1'b1));
end
if (B_ADDRESS_WIDTH != 10) begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above b_address_width_check (
.error(1'b1)
);
end
if (B_DATA_WIDTH != 128) begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above b_data_width_check (.error(1'b1));
end
endgenerate
system_bd_alt_mem_asym_10_wryanuq #(
.A_ADDRESS_WIDTH(10),
.A_DATA_WIDTH (128),
.B_ADDRESS_WIDTH(10),
.B_DATA_WIDTH (128)
) alt_mem_asym_bypass (
.mem_i_datain (mem_i_datain), // mem_i.datain
.mem_i_wraddress(mem_i_wraddress), // .wraddress
.mem_i_rdaddress(mem_i_rdaddress), // .rdaddress
.mem_i_wren (mem_i_wren), // .wren
.mem_i_wrclock (mem_i_wrclock), // .wrclock
.mem_i_rdclock (mem_i_rdclock), // .rdclock
.mem_o_dataout (mem_o_dataout) // mem_o.dataout
);
endmodule
| 7.157808 |
module alt_mem_asym_rd #(
parameter A_ADDRESS_WIDTH = 0,
parameter A_DATA_WIDTH = 512,
parameter B_ADDRESS_WIDTH = 12,
parameter B_DATA_WIDTH = 128
) (
input wire [511:0] mem_i_datain, // mem_i.datain
input wire [ 9:0] mem_i_wraddress, // .wraddress
input wire [ 11:0] mem_i_rdaddress, // .rdaddress
input wire mem_i_wren, // .wren
input wire mem_i_wrclock, // .wrclock
input wire mem_i_rdclock, // .rdclock
output wire [127:0] mem_o_dataout // mem_o.dataout
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (A_ADDRESS_WIDTH != 0) begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above a_address_width_check (
.error(1'b1)
);
end
if (A_DATA_WIDTH != 512) begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above a_data_width_check (.error(1'b1));
end
if (B_ADDRESS_WIDTH != 12) begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above b_address_width_check (
.error(1'b1)
);
end
if (B_DATA_WIDTH != 128) begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above b_data_width_check (.error(1'b1));
end
endgenerate
system_bd_alt_mem_asym_10_ommashy #(
.A_ADDRESS_WIDTH(0),
.A_DATA_WIDTH (512),
.B_ADDRESS_WIDTH(12),
.B_DATA_WIDTH (128)
) alt_mem_asym_rd (
.mem_i_datain (mem_i_datain), // mem_i.datain
.mem_i_wraddress(mem_i_wraddress), // .wraddress
.mem_i_rdaddress(mem_i_rdaddress), // .rdaddress
.mem_i_wren (mem_i_wren), // .wren
.mem_i_wrclock (mem_i_wrclock), // .wrclock
.mem_i_rdclock (mem_i_rdclock), // .rdclock
.mem_o_dataout (mem_o_dataout) // mem_o.dataout
);
endmodule
| 7.157808 |
module alt_mem_asym_wr #(
parameter A_ADDRESS_WIDTH = 12,
parameter A_DATA_WIDTH = 128,
parameter B_ADDRESS_WIDTH = 8,
parameter B_DATA_WIDTH = 512
) (
input wire [127:0] mem_i_datain, // mem_i.datain
input wire [ 11:0] mem_i_wraddress, // .wraddress
input wire [ 9:0] mem_i_rdaddress, // .rdaddress
input wire mem_i_wren, // .wren
input wire mem_i_wrclock, // .wrclock
input wire mem_i_rdclock, // .rdclock
output wire [511:0] mem_o_dataout // mem_o.dataout
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (A_ADDRESS_WIDTH != 12) begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above a_address_width_check (
.error(1'b1)
);
end
if (A_DATA_WIDTH != 128) begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above a_data_width_check (.error(1'b1));
end
if (B_ADDRESS_WIDTH != 8) begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above b_address_width_check (
.error(1'b1)
);
end
if (B_DATA_WIDTH != 512) begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above b_data_width_check (.error(1'b1));
end
endgenerate
system_bd_alt_mem_asym_10_7c4hvii #(
.A_ADDRESS_WIDTH(12),
.A_DATA_WIDTH (128),
.B_ADDRESS_WIDTH(8),
.B_DATA_WIDTH (512)
) alt_mem_asym_wr (
.mem_i_datain (mem_i_datain), // mem_i.datain
.mem_i_wraddress(mem_i_wraddress), // .wraddress
.mem_i_rdaddress(mem_i_rdaddress), // .rdaddress
.mem_i_wren (mem_i_wren), // .wren
.mem_i_wrclock (mem_i_wrclock), // .wrclock
.mem_i_rdclock (mem_i_rdclock), // .rdclock
.mem_o_dataout (mem_o_dataout) // mem_o.dataout
);
endmodule
| 7.157808 |
module alt_mlab #(
parameter WIDTH = 20,
parameter ADDR_WIDTH = 5,
parameter SIM_EMULATE = 1'b0 // this may not be exactly the same at the fine grain timing level
) (
input wclk,
input wena,
input [ADDR_WIDTH-1:0] waddr_reg,
input [WIDTH-1:0] wdata_reg,
input [ADDR_WIDTH-1:0] raddr,
output [WIDTH-1:0] rdata
);
genvar i;
generate
if (!SIM_EMULATE) begin
/////////////////////////////////////////////
// hardware cells
for (i = 0; i < WIDTH; i = i + 1) begin : ml
wire wclk_w = wclk; // workaround strange modelsim warning due to cell model tristate
// Note: the stratix 5 cell is the same other than timing
//stratixv_mlab_cell lrm (
twentynm_mlab_cell lrm (
.clk0(wclk_w),
.ena0(wena),
// synthesis translate off
.clk1(1'b0),
.ena1(1'b1),
.ena2(1'b1),
.clr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
// synthesis translate on
.portabyteenamasks(1'b1),
.portadatain(wdata_reg[i]),
.portaaddr(waddr_reg),
.portbaddr(raddr),
.portbdataout(rdata[i])
);
defparam lrm.mixed_port_feed_through_mode = "dont_care";
defparam lrm.logical_ram_name = "lrm"; defparam lrm.logical_ram_depth = 1 << ADDR_WIDTH;
defparam lrm.logical_ram_width = WIDTH; defparam lrm.first_address = 0;
defparam lrm.last_address = (1 << ADDR_WIDTH) - 1; defparam lrm.first_bit_number = i;
defparam lrm.data_width = 1; defparam lrm.address_width = ADDR_WIDTH;
end
end else begin
/////////////////////////////////////////////
// sim equivalent
localparam NUM_WORDS = (1 << ADDR_WIDTH);
reg [WIDTH-1:0] storage[0:NUM_WORDS-1];
integer k = 0;
initial begin
for (k = 0; k < NUM_WORDS; k = k + 1) begin
storage[k] = 0;
end
end
always @(posedge wclk) begin
if (wena) storage[waddr_reg] <= wdata_reg;
end
reg [WIDTH-1:0] rdata_b = 0;
always @(*) begin
rdata_b = storage[raddr];
end
assign rdata = rdata_b;
end
endgenerate
endmodule
| 7.833195 |
module alt_or_r #(
parameter WIDTH = 8
) (
input clk,
input [WIDTH-1:0] din,
output dout
);
genvar i;
generate
if (WIDTH <= 6) begin
reg dout_r = 1'b0;
always @(posedge clk) dout_r <= |din;
assign dout = dout_r;
end else if ((WIDTH % 6) == 0) begin
localparam NUM_HEXES = WIDTH / 6;
wire [NUM_HEXES-1:0] tmp;
for (i = 0; i < NUM_HEXES; i = i + 1) begin : lp
alt_or_r a (
.clk (clk),
.din (din[(i+1)*6-1:i*6]),
.dout(tmp[i])
);
defparam a.WIDTH = 6;
end
alt_or_r h (
.clk (clk),
.din (tmp),
.dout(dout)
);
defparam h.WIDTH = NUM_HEXES;
end else if ((WIDTH % 5) == 0) begin
localparam NUM_QUINTS = WIDTH / 5;
wire [NUM_QUINTS-1:0] tmp;
for (i = 0; i < NUM_QUINTS; i = i + 1) begin : lp
alt_or_r a (
.clk (clk),
.din (din[(i+1)*5-1:i*5]),
.dout(tmp[i])
);
defparam a.WIDTH = 5;
end
alt_or_r h (
.clk (clk),
.din (tmp),
.dout(dout)
);
defparam h.WIDTH = NUM_QUINTS;
end else if ((WIDTH % 4) == 0) begin
localparam NUM_QUADS = WIDTH / 4;
wire [NUM_QUADS-1:0] tmp;
for (i = 0; i < NUM_QUADS; i = i + 1) begin : lp
alt_or_r a (
.clk (clk),
.din (din[(i+1)*4-1:i*4]),
.dout(tmp[i])
);
defparam a.WIDTH = 4;
end
alt_or_r h (
.clk (clk),
.din (tmp),
.dout(dout)
);
defparam h.WIDTH = NUM_QUADS;
end else begin
initial begin
$display("Oops - no pipelined gate pattern available for width %d", WIDTH);
$display("Please add");
$stop();
end
end
endgenerate
endmodule
| 8.522536 |
module alt_reset_delay #(
parameter CNTR_BITS = 16
) (
input clk,
input ready_in,
output ready_out
);
reg [2:0]
rs_meta = 3'b0 /* synthesis preserve dont_replicate */
/* synthesis ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \"set_false_path -from [get_fanins -async *reset_delay*rs_meta\[*\]] -to [get_keepers *reset_delay*rs_meta\[*\]]\" " */;
always @(posedge clk or negedge ready_in) begin
if (!ready_in) rs_meta <= 3'b000;
else rs_meta <= {rs_meta[1:0], 1'b1};
end
wire ready_sync = rs_meta[2];
reg [CNTR_BITS-1:0] cntr = {CNTR_BITS{1'b0}} /* synthesis preserve */;
assign ready_out = cntr[CNTR_BITS-1];
always @(posedge clk or negedge ready_sync) begin
if (!ready_sync) cntr <= {CNTR_BITS{1'b0}};
else if (!ready_out) cntr <= cntr + 1'b1;
end
endmodule
| 6.932559 |
module alt_scfifo (
aclr,
clock,
data,
rdreq,
sclr,
wrreq,
almost_empty,
almost_full,
empty,
full,
q,
usedw,
fifo_ovf,
fifo_unf
);
parameter FIFO_WIDTH = 144;
parameter FIFO_DEPTH = 7;
parameter FIFO_TYPE = "AUTO";
parameter FIFO_SHOW = "OFF";
parameter USE_EAB = "ON";
parameter FIFO_NUMWORDS = 1 << FIFO_DEPTH;
parameter FIFO_AEMPTY = 0;
parameter FIFO_AFULL = FIFO_NUMWORDS;
parameter FIFO_UNF = "TRUE";
parameter TYPE = FIFO_TYPE == "M4K" | FIFO_TYPE == "M9K" ? "RAM_BLOCK_TYPE=M9K":
FIFO_TYPE == "M512" | FIFO_TYPE == "MLAB" ? "RAM_BLOCK_TYPE=MLAB":
FIFO_TYPE == "M-RAM" | FIFO_TYPE == "M144K"? "RAM_BLOCK_TYPE=M144K":
"RAM_BLOCK_TYPE=AUTO";
input aclr;
input clock;
input [FIFO_WIDTH-1:0] data;
input rdreq;
input sclr;
input wrreq;
output almost_empty;
output almost_full;
output empty;
output full;
output [FIFO_WIDTH-1:0] q;
output [FIFO_DEPTH-1:0] usedw;
output fifo_ovf;
output fifo_unf;
reg fifo_ovf;
reg fifo_unf;
always @(posedge clock or posedge aclr)
if (aclr) begin
fifo_ovf <= 1'b0;
fifo_unf <= 1'b0;
end else begin
// synthesis translate_off
if (fifo_ovf) begin
$display("%m: ERROR!!! %m alt_scfifo FIFO overflow, simulation stop");
$stop;
end
if (fifo_unf & (FIFO_UNF == "TRUE")) begin
$display("%m: ERROR!!! alt_dcfifo FIFO underflow, simulation stop");
$stop;
end
// synthesis translate_on
fifo_ovf <= (full & wrreq) | fifo_ovf;
fifo_unf <= ((empty & rdreq) | fifo_unf) & (FIFO_UNF == "TRUE");
end
scfifo scfifo_component (
.rdreq (rdreq),
.sclr (sclr),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.almost_full (almost_full),
.usedw (usedw),
.empty (empty),
.almost_empty(almost_empty),
.q (q),
.full (full)
);
defparam scfifo_component.add_ram_output_register = "ON", scfifo_component.almost_empty_value =
FIFO_AEMPTY, scfifo_component.almost_full_value = FIFO_AFULL,
scfifo_component.intended_device_family = "Stratix III", scfifo_component.lpm_hint = TYPE,
scfifo_component.lpm_numwords = FIFO_NUMWORDS, scfifo_component.lpm_showahead = FIFO_SHOW,
scfifo_component.lpm_type = "scfifo", scfifo_component.lpm_width = FIFO_WIDTH,
scfifo_component.lpm_widthu = FIFO_DEPTH, scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON", scfifo_component.use_eab = USE_EAB;
endmodule
| 6.630776 |
module alt_scrambler #(
parameter WIDTH = 512,
parameter SCRAM_INIT = 58'h3ff_ffff_ffff_ffff,
parameter DEBUG_DONT_SCRAMBLE = 1'b0
) (
input clk,
srst,
ena,
input [WIDTH-1:0] din, // bit 0 is to be sent first
output reg [WIDTH-1:0] dout
);
reg [57:0] scram_state = SCRAM_INIT;
wire [WIDTH+58-1:0] history;
assign history[57:0] = scram_state;
genvar i;
generate
for (i = 58; i < WIDTH + 58; i = i + 1) begin : lp
assign history[i] =
(DEBUG_DONT_SCRAMBLE ? 1'b0 : (history[i-58] ^ history[i-39])) ^ din[i-58];
end
endgenerate
// suppress secondary signal inference
wire [WIDTH-1:0] dout_w /* synthesis keep */;
assign dout_w = srst ? {WIDTH{1'b0}} : (ena ? history[WIDTH+58-1:58] : dout);
always @(posedge clk) dout <= dout_w;
wire [57:0] scram_state_w /* synthesis keep */;
assign scram_state_w = srst ? SCRAM_INIT : (ena ? history[WIDTH+58-1:WIDTH] : scram_state);
always @(posedge clk) scram_state <= scram_state_w;
/*
always @(posedge clk) begin
if (srst) begin
dout <= 0;
scram_state <= SCRAM_INIT;
end
else if (ena) begin
dout <= history[WIDTH+58-1:58];
scram_state <= history[WIDTH+58-1:WIDTH];
end
end
*/
endmodule
| 7.298221 |
module alt_sld_fab_altera_a10_xcvr_reset_sequencer_181_ivi4soy (
input wire clk_in_0, // Unused (this is part of a reset ep configured which isn't configured as a clock input)
input wire reset_req_0,
output wire reset_out_0,
input wire clk_in_1, // Unused (this is part of a reset ep configured which isn't configured as a clock input)
input wire reset_req_1,
output wire reset_out_1,
input wire clk_in_2, // Unused (this is part of a reset ep configured which isn't configured as a clock input)
input wire reset_req_2,
output wire reset_out_2,
input wire clk_in_3, // Unused (this is part of a reset ep configured which isn't configured as a clock input)
input wire reset_req_3,
output wire reset_out_3,
input wire clk_in_4, // Unused (this is part of a reset ep configured which isn't configured as a clock input)
input wire reset_req_4,
output wire reset_out_4,
input wire clk_in_5, // Unused (this is part of a reset ep configured which isn't configured as a clock input)
input wire reset_req_5,
output wire reset_out_5,
input wire clk_in_6, // Unused (this is part of a reset ep configured which isn't configured as a clock input)
input wire reset_req_6,
output wire reset_out_6,
input wire clk_in_7, // Unused (this is part of a reset ep configured which isn't configured as a clock input)
input wire reset_req_7,
output wire reset_out_7
);
wire [8-1:0] reset_req;
wire [8-1:0] reset_out;
// Assgnments to break apart the bus
assign reset_req[0] = reset_req_0;
assign reset_out_0 = reset_out[0];
assign reset_req[1] = reset_req_1;
assign reset_out_1 = reset_out[1];
assign reset_req[2] = reset_req_2;
assign reset_out_2 = reset_out[2];
assign reset_req[3] = reset_req_3;
assign reset_out_3 = reset_out[3];
assign reset_req[4] = reset_req_4;
assign reset_out_4 = reset_out[4];
assign reset_req[5] = reset_req_5;
assign reset_out_5 = reset_out[5];
assign reset_req[6] = reset_req_6;
assign reset_out_6 = reset_out[6];
assign reset_req[7] = reset_req_7;
assign reset_out_7 = reset_out[7];
wire altera_clk_user_int;
twentynm_oscillator ALTERA_INSERTED_INTOSC_FOR_TRS (
.clkout (altera_clk_user_int),
.clkout1(),
.oscena (1'b1)
);
altera_xcvr_reset_sequencer #(
.CLK_FREQ_IN_HZ (125000000),
.RESET_SEPARATION_NS(200),
.NUM_RESETS (8) // total number of resets to sequence
// rx/tx_analog, pll_powerdown
) altera_reset_sequencer (
// Input clock
.altera_clk_user(altera_clk_user_int), // Connect to CLKUSR
// Reset requests and acknowledgements
.reset_req (reset_req),
.reset_out (reset_out)
);
endmodule
| 7.327296 |
module alt_sld_fab_alt_sld_fab_trfabric_mem (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
output [31:0] readdata;
input [12:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input freeze;
input reset;
input reset_req;
input write;
input [31:0] writedata;
wire clocken0;
reg [31:0] readdata;
wire [31:0] readdata_ram;
wire wren;
always @(posedge clk) begin
if (clken) readdata <= readdata_ram;
end
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clk),
.clocken0(clocken0),
.data_a(writedata),
.q_a(readdata_ram),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram", the_altsyncram.maximum_depth = 8192,
the_altsyncram.numwords_a = 8192, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 13;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 7.327296 |
module alt_sync_regs_m2 #(
parameter WIDTH = 32,
parameter DEPTH = 2 // minimum of 2
) (
input clk,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout
);
reg [WIDTH-1:0]
din_meta = 0 /* synthesis preserve dont_replicate */
/* synthesis ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \"set_multicycle_path -to [get_keepers *sync_regs_m*din_meta\[*\]] 2\" " */ ;
reg [WIDTH*(DEPTH-1)-1:0]
sync_sr = 0 /* synthesis preserve dont_replicate */
/* synthesis ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \"set_false_path -hold -to [get_keepers *sync_regs_m*din_meta\[*\]]\" " */ ;
always @(posedge clk) begin
din_meta <= din;
sync_sr <= (sync_sr << WIDTH) | din_meta;
end
assign dout = sync_sr[WIDTH*(DEPTH-1)-1:WIDTH*(DEPTH-2)];
endmodule
| 6.712928 |
module alt_times_1pt8 #(
parameter WIDTH = 8
) (
input clk,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout
);
reg [WIDTH+8-1:0] scratch = {(WIDTH + 8) {1'b0}};
reg [WIDTH+1-1:0] p0 = {(WIDTH + 1) {1'b0}};
reg [WIDTH+3-1:0] p1 = {(WIDTH + 3) {1'b0}};
reg [WIDTH+2-1:0] p2 = {(WIDTH + 2) {1'b0}};
always @(posedge clk) begin
p0 <= {din, 1'b0} + din; // 256,128
p1 <= {din, 3'b0} + din; // 64 8
p2 <= {din, 2'b0} + din; // 4 1
scratch <= {p0, 7'b0} + {p1, 3'b0} + p2;
end
assign dout = scratch[WIDTH+8-1:8];
endmodule
| 6.880969 |
module alt_top (
input OSCCLK,
output hsync,
output vsync,
output [2:0] red,
output [2:0] green,
output [1:0] blue,
output [7:0] sseg,
output [3:0] an,
input ps2_clk,
input ps2_data
);
wire [7:0] wr;
wire [7:0] wg;
wire [7:0] wb;
assign red = wr[7:5];
assign green = wg[7:5];
assign blue = wb[7:6];
demo_root alt_map (
.OSCCLK(OSCCLK),
.hsync(hsync),
.vsync(vsync),
.red(wr),
.green(wg),
.blue(wb),
.sseg(sseg),
.an(an),
.ps2_clk(ps2_clk),
.ps2_data(ps2_data)
);
endmodule
| 8.721 |
module alt_vipcti130_common_fifo (
wrclk,
rdreq,
aclr,
rdclk,
wrreq,
data,
rdusedw,
rdempty,
wrusedw,
wrfull,
q
);
function integer alt_clogb2;
input [31:0] value;
integer i;
begin
alt_clogb2 = 32;
for (i = 31; i > 0; i = i - 1) begin
if (2 ** i >= value) alt_clogb2 = i;
end
end
endfunction
parameter DATA_WIDTH = 20;
parameter FIFO_DEPTH = 1920;
parameter CLOCKS_ARE_SAME = 0;
parameter DATA_WIDTHU = alt_clogb2(FIFO_DEPTH);
input wrclk;
input rdreq;
input aclr;
input rdclk;
input wrreq;
input [DATA_WIDTH-1:0] data;
output [DATA_WIDTHU-1:0] rdusedw;
output rdempty;
output [DATA_WIDTHU-1:0] wrusedw;
output wrfull;
output [DATA_WIDTH-1:0] q;
generate
if (CLOCKS_ARE_SAME) begin
assign rdusedw = wrusedw;
scfifo input_fifo (
.rdreq(rdreq),
.aclr(aclr),
.clock(wrclk),
.wrreq(wrreq),
.data(data),
.empty(rdempty),
.full(wrfull),
.usedw(wrusedw),
.q(q)
);
defparam input_fifo.add_ram_output_register = "OFF",
input_fifo.lpm_hint = "MAXIMIZE_SPEED=7,", input_fifo.lpm_numwords = FIFO_DEPTH,
input_fifo.lpm_showahead = "OFF", input_fifo.lpm_type = "scfifo", input_fifo.lpm_width =
DATA_WIDTH, input_fifo.lpm_widthu = DATA_WIDTHU, input_fifo.overflow_checking = "OFF",
input_fifo.underflow_checking = "OFF", input_fifo.use_eab = "ON";
end else begin
dcfifo input_fifo (
.wrclk(wrclk),
.rdreq(rdreq),
.aclr(aclr),
.rdclk(rdclk),
.wrreq(wrreq),
.data(data),
.rdusedw(rdusedw),
.rdempty(rdempty),
.wrfull(wrfull),
.wrusedw(wrusedw),
.q(q)
);
defparam input_fifo.lpm_hint = "MAXIMIZE_SPEED=7,", input_fifo.lpm_numwords = FIFO_DEPTH,
input_fifo.lpm_showahead = "OFF", input_fifo.lpm_type = "dcfifo", input_fifo.lpm_width =
DATA_WIDTH, input_fifo.lpm_widthu = DATA_WIDTHU, input_fifo.overflow_checking = "OFF",
input_fifo.rdsync_delaypipe = 5, input_fifo.underflow_checking = "OFF", input_fifo.use_eab
= "ON", input_fifo.wrsync_delaypipe = 5, input_fifo.read_aclr_synch = "ON";
end
endgenerate
endmodule
| 6.83539 |
module alt_vipcti130_common_frame_counter #(
parameter NUMBER_OF_COLOUR_PLANES = 0,
COLOUR_PLANES_ARE_IN_PARALLEL = 0,
LOG2_NUMBER_OF_COLOUR_PLANES = 0,
CONVERT_SEQ_TO_PAR = 0,
TOTALS_MINUS_ONE = 0
) (
input wire rst,
input wire clk,
input wire sclr,
// control signals
input wire enable,
input wire hd_sdn,
// frame sizes
input wire [13:0] h_total,
input wire [12:0] v_total,
// reset values
input wire [13:0] h_reset,
input wire [12:0] v_reset,
// outputs
output wire new_line,
output wire start_of_sample,
output wire [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] sample_ticks,
output reg [13:0] h_count,
output reg [12:0] v_count
);
wire count_sample;
alt_vipcti130_common_sample_counter sample_counter (
.rst(rst),
.clk(clk),
.sclr(sclr),
.hd_sdn(hd_sdn),
.count_cycle(enable),
.count_sample(count_sample),
.start_of_sample(start_of_sample),
.sample_ticks(sample_ticks)
);
defparam sample_counter.NUMBER_OF_COLOUR_PLANES = NUMBER_OF_COLOUR_PLANES,
sample_counter.COLOUR_PLANES_ARE_IN_PARALLEL = COLOUR_PLANES_ARE_IN_PARALLEL,
sample_counter.LOG2_NUMBER_OF_COLOUR_PLANES = LOG2_NUMBER_OF_COLOUR_PLANES;
wire [13:0] h_total_int;
wire [12:0] v_total_int;
generate
if (TOTALS_MINUS_ONE) begin : totals_minus_one_generate
assign h_total_int = h_total;
assign v_total_int = v_total;
end else begin
assign h_total_int = h_total - 14'd1;
assign v_total_int = v_total - 13'd1;
end
endgenerate
always @(posedge rst or posedge clk) begin
if (rst) begin
h_count <= 14'd0;
v_count <= 13'd0;
end else begin
if (sclr) begin
h_count <= h_reset + {{13{1'b0}}, count_sample & hd_sdn};
v_count <= v_reset;
end else if (enable) begin
if (new_line) begin
h_count <= 14'd0;
if (v_count >= v_total_int) v_count <= 13'd0;
else v_count <= v_count + 13'd1;
end else if (count_sample) h_count <= h_count + 14'd1;
end
end
end
assign new_line = (h_count >= h_total_int) && count_sample;
endmodule
| 6.83539 |
module alt_vipcti130_common_sample_counter #(
parameter NUMBER_OF_COLOUR_PLANES = 0,
COLOUR_PLANES_ARE_IN_PARALLEL = 0,
LOG2_NUMBER_OF_COLOUR_PLANES = 0
) (
input wire rst,
input wire clk,
input wire sclr,
input wire count_cycle,
input wire hd_sdn,
output wire count_sample,
output wire start_of_sample,
output wire [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] sample_ticks
);
generate
if (NUMBER_OF_COLOUR_PLANES == 1) begin
assign count_sample = count_cycle;
assign start_of_sample = 1'b1;
assign sample_ticks = 1'b0;
end else begin
reg [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] count_valids;
wire new_sample;
assign new_sample = count_valids == (NUMBER_OF_COLOUR_PLANES - 1);
always @(posedge rst or posedge clk) begin
if (rst) begin
count_valids <= {LOG2_NUMBER_OF_COLOUR_PLANES{1'b0}};
end else begin
if (sclr) count_valids <= {{LOG2_NUMBER_OF_COLOUR_PLANES - 1{1'b0}}, count_cycle};
else
count_valids <= (count_cycle) ? (new_sample) ? {LOG2_NUMBER_OF_COLOUR_PLANES{1'b0}} : count_valids + 1 : count_valids;
end
end
assign count_sample = (hd_sdn) ? count_cycle : count_cycle & new_sample;
assign start_of_sample = (hd_sdn) ? 1'b1 : (count_valids == {LOG2_NUMBER_OF_COLOUR_PLANES{1'b0}});
assign sample_ticks = count_valids;
end
endgenerate
endmodule
| 6.83539 |
module alt_vipcti130_common_sync #(
parameter CLOCKS_ARE_SAME = 0,
WIDTH = 1
) (
input wire rst,
input wire sync_clock,
input wire [WIDTH-1:0] data_in,
output wire [WIDTH-1:0] data_out
);
(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name SDC_STATEMENT \"set_false_path -to [get_keepers *data_out_sync0*]\"" *)reg [WIDTH-1:0] data_out_sync0;
(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS" *)reg [WIDTH-1:0] data_out_sync1;
generate
if (CLOCKS_ARE_SAME) assign data_out = data_in;
else begin
always @(posedge rst or posedge sync_clock) begin
if (rst) begin
data_out_sync0 <= {WIDTH{1'b0}};
data_out_sync1 <= {WIDTH{1'b0}};
end else begin
data_out_sync0 <= data_in;
data_out_sync1 <= data_out_sync0;
end
end
assign data_out = data_out_sync1;
end
endgenerate
endmodule
| 6.83539 |
module alt_vipcti130_Vid2IS_sync_polarity_convertor (
input rst,
input clk,
input sync_in,
input datavalid,
output sync_out
);
wire datavalid_negedge;
reg datavalid_reg;
wire needs_invert_nxt;
reg needs_invert;
wire invert_sync_nxt;
reg invert_sync;
assign datavalid_negedge = datavalid_reg & ~datavalid;
assign needs_invert_nxt = (datavalid & sync_in) | needs_invert;
assign invert_sync_nxt = (datavalid_negedge) ? needs_invert_nxt : invert_sync;
always @(posedge rst or posedge clk) begin
if (rst) begin
datavalid_reg <= 1'b0;
needs_invert <= 1'b0;
invert_sync <= 1'b0;
end else begin
datavalid_reg <= datavalid;
needs_invert <= needs_invert_nxt & ~datavalid_negedge;
invert_sync <= invert_sync_nxt;
end
end
assign sync_out = sync_in ^ invert_sync_nxt;
endmodule
| 6.83539 |
module alt_vipcti130_Vid2IS_write_buffer #(
parameter DATA_WIDTH = 20,
NUMBER_OF_COLOUR_PLANES = 2,
BPS = 10
) (
input wire rst,
input wire clk,
input wire convert,
input wire hd_sdn,
input wire early_eop,
input wire wrreq_in,
input wire [DATA_WIDTH-1:0] data_in,
input wire packet_in,
output wire wrreq_out,
output wire [DATA_WIDTH-1:0] data_out,
output wire packet_out
);
reg [BPS-1:0] write_buffer_data[NUMBER_OF_COLOUR_PLANES-1:0];
reg [NUMBER_OF_COLOUR_PLANES-1:0] write_buffer_valid;
reg write_buffer_packet;
generate
begin : write_buffer_generation
genvar i;
for (i = 0; i < NUMBER_OF_COLOUR_PLANES; i = i + 1) begin : write_buffer_generation_for_loop
always @(posedge rst or posedge clk) begin
if (rst) begin
write_buffer_data[i] <= {BPS{1'b0}};
write_buffer_valid[i] <= 1'b0;
end else begin
if (wrreq_in && !early_eop) begin
if (!hd_sdn) begin
if (!convert) begin
// copy the ancilliary data into the Y (control packet copied as well
// but that won't affect anything)
write_buffer_data[i] <= data_in[BPS-1:0];
write_buffer_valid[i] <= 1'b1;
end else begin
if((i == 0) ? write_buffer_valid[i] == 0 || wrreq_out : write_buffer_valid[i] == 0 && write_buffer_valid[i-1] == 1) begin // decide which part of the buffer to insert the sample
write_buffer_data[i] <= data_in[BPS-1:0];
write_buffer_valid[i] <= 1'b1;
end else begin
if (wrreq_out) begin
write_buffer_valid[i] <= 1'b0; // clear the buffer
end
end
end
end else begin
write_buffer_data[i] <= data_in[(i*BPS)+(BPS-1):(i*BPS)];
write_buffer_valid[i] <= 1'b1;
end
end else begin
if (wrreq_out) begin
write_buffer_valid[i] <= 1'b0; // clear the buffer
end
end
end
end
assign data_out[(i*BPS)+(BPS-1):(i*BPS)] = write_buffer_data[i];
end
end
endgenerate
always @(posedge rst or posedge clk) begin
if (rst) begin
write_buffer_packet <= 1'b0;
end else begin
if (wrreq_in && !early_eop) begin
if (!hd_sdn) begin
if (packet_in) begin
write_buffer_packet <= 1'b1;
end else if (wrreq_out) begin
write_buffer_packet <= 1'b0;
end
end else begin
write_buffer_packet <= packet_in;
end
end else begin
if (wrreq_out) begin
write_buffer_packet <= 1'b0;
end
end
end
end
assign wrreq_out = (&write_buffer_valid) | early_eop;
assign packet_out = write_buffer_packet | early_eop;
endmodule
| 6.83539 |
module alt_vipcti131_common_fifo (
wrclk,
rdreq,
aclr,
rdclk,
wrreq,
data,
rdusedw,
rdempty,
wrusedw,
wrfull,
q
);
function integer alt_clogb2;
input [31:0] value;
integer i;
begin
alt_clogb2 = 32;
for (i = 31; i > 0; i = i - 1) begin
if (2 ** i >= value) alt_clogb2 = i;
end
end
endfunction
parameter DATA_WIDTH = 20;
parameter FIFO_DEPTH = 1920;
parameter CLOCKS_ARE_SAME = 0;
parameter DATA_WIDTHU = alt_clogb2(FIFO_DEPTH);
input wrclk;
input rdreq;
input aclr;
input rdclk;
input wrreq;
input [DATA_WIDTH-1:0] data;
output [DATA_WIDTHU-1:0] rdusedw;
output rdempty;
output [DATA_WIDTHU-1:0] wrusedw;
output wrfull;
output [DATA_WIDTH-1:0] q;
generate
if (CLOCKS_ARE_SAME) begin
assign rdusedw = wrusedw;
scfifo input_fifo (
.rdreq(rdreq),
.aclr(aclr),
.clock(wrclk),
.wrreq(wrreq),
.data(data),
.empty(rdempty),
.full(wrfull),
.usedw(wrusedw),
.q(q)
);
defparam input_fifo.add_ram_output_register = "OFF",
input_fifo.lpm_hint = "MAXIMIZE_SPEED=7,", input_fifo.lpm_numwords = FIFO_DEPTH,
input_fifo.lpm_showahead = "OFF", input_fifo.lpm_type = "scfifo", input_fifo.lpm_width =
DATA_WIDTH, input_fifo.lpm_widthu = DATA_WIDTHU, input_fifo.overflow_checking = "OFF",
input_fifo.underflow_checking = "OFF", input_fifo.use_eab = "ON";
end else begin
dcfifo input_fifo (
.wrclk(wrclk),
.rdreq(rdreq),
.aclr(aclr),
.rdclk(rdclk),
.wrreq(wrreq),
.data(data),
.rdusedw(rdusedw),
.rdempty(rdempty),
.wrfull(wrfull),
.wrusedw(wrusedw),
.q(q)
);
defparam input_fifo.lpm_hint = "MAXIMIZE_SPEED=7,", input_fifo.lpm_numwords = FIFO_DEPTH,
input_fifo.lpm_showahead = "OFF", input_fifo.lpm_type = "dcfifo", input_fifo.lpm_width =
DATA_WIDTH, input_fifo.lpm_widthu = DATA_WIDTHU, input_fifo.overflow_checking = "OFF",
input_fifo.rdsync_delaypipe = 5, input_fifo.underflow_checking = "OFF", input_fifo.use_eab
= "ON", input_fifo.wrsync_delaypipe = 5, input_fifo.read_aclr_synch = "ON";
end
endgenerate
endmodule
| 6.875537 |
module alt_vipcti131_common_frame_counter #(
parameter NUMBER_OF_COLOUR_PLANES = 0,
COLOUR_PLANES_ARE_IN_PARALLEL = 0,
LOG2_NUMBER_OF_COLOUR_PLANES = 0,
CONVERT_SEQ_TO_PAR = 0,
TOTALS_MINUS_ONE = 0
) (
input wire rst,
input wire clk,
input wire sclr,
// control signals
input wire enable,
input wire hd_sdn,
// frame sizes
input wire [13:0] h_total,
input wire [12:0] v_total,
// reset values
input wire [13:0] h_reset,
input wire [12:0] v_reset,
// outputs
output wire new_line,
output wire start_of_sample,
output wire [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] sample_ticks,
output reg [13:0] h_count,
output reg [12:0] v_count
);
wire count_sample;
alt_vipcti131_common_sample_counter sample_counter (
.rst(rst),
.clk(clk),
.sclr(sclr),
.hd_sdn(hd_sdn),
.count_cycle(enable),
.count_sample(count_sample),
.start_of_sample(start_of_sample),
.sample_ticks(sample_ticks)
);
defparam sample_counter.NUMBER_OF_COLOUR_PLANES = NUMBER_OF_COLOUR_PLANES,
sample_counter.COLOUR_PLANES_ARE_IN_PARALLEL = COLOUR_PLANES_ARE_IN_PARALLEL,
sample_counter.LOG2_NUMBER_OF_COLOUR_PLANES = LOG2_NUMBER_OF_COLOUR_PLANES;
wire [13:0] h_total_int;
wire [12:0] v_total_int;
generate
if (TOTALS_MINUS_ONE) begin : totals_minus_one_generate
assign h_total_int = h_total;
assign v_total_int = v_total;
end else begin
assign h_total_int = h_total - 14'd1;
assign v_total_int = v_total - 13'd1;
end
endgenerate
always @(posedge rst or posedge clk) begin
if (rst) begin
h_count <= 14'd0;
v_count <= 13'd0;
end else begin
if (sclr) begin
h_count <= h_reset + {{13{1'b0}}, count_sample & hd_sdn};
v_count <= v_reset;
end else if (enable) begin
if (new_line) begin
h_count <= 14'd0;
if (v_count >= v_total_int) v_count <= 13'd0;
else v_count <= v_count + 13'd1;
end else if (count_sample) h_count <= h_count + 14'd1;
end
end
end
assign new_line = (h_count >= h_total_int) && count_sample;
endmodule
| 6.875537 |
module alt_vipcti131_common_sample_counter #(
parameter NUMBER_OF_COLOUR_PLANES = 0,
COLOUR_PLANES_ARE_IN_PARALLEL = 0,
LOG2_NUMBER_OF_COLOUR_PLANES = 0
) (
input wire rst,
input wire clk,
input wire sclr,
input wire count_cycle,
input wire hd_sdn,
output wire count_sample,
output wire start_of_sample,
output wire [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] sample_ticks
);
generate
if (NUMBER_OF_COLOUR_PLANES == 1) begin
assign count_sample = count_cycle;
assign start_of_sample = 1'b1;
assign sample_ticks = 1'b0;
end else begin
reg [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] count_valids;
wire new_sample;
assign new_sample = count_valids == (NUMBER_OF_COLOUR_PLANES - 1);
always @(posedge rst or posedge clk) begin
if (rst) begin
count_valids <= {LOG2_NUMBER_OF_COLOUR_PLANES{1'b0}};
end else begin
if (sclr) count_valids <= {{LOG2_NUMBER_OF_COLOUR_PLANES - 1{1'b0}}, count_cycle};
else
count_valids <= (count_cycle) ? (new_sample) ? {LOG2_NUMBER_OF_COLOUR_PLANES{1'b0}} : count_valids + 1 : count_valids;
end
end
assign count_sample = (hd_sdn) ? count_cycle : count_cycle & new_sample;
assign start_of_sample = (hd_sdn) ? 1'b1 : (count_valids == {LOG2_NUMBER_OF_COLOUR_PLANES{1'b0}});
assign sample_ticks = count_valids;
end
endgenerate
endmodule
| 6.875537 |
module alt_vipcti131_common_sync #(
parameter CLOCKS_ARE_SAME = 0,
WIDTH = 1
) (
input wire rst,
input wire sync_clock,
input wire [WIDTH-1:0] data_in,
output wire [WIDTH-1:0] data_out
);
(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name SDC_STATEMENT \"set_false_path -to [get_keepers *data_out_sync0*]\"" *)reg [WIDTH-1:0] data_out_sync0;
(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS" *)reg [WIDTH-1:0] data_out_sync1;
generate
if (CLOCKS_ARE_SAME) assign data_out = data_in;
else begin
always @(posedge rst or posedge sync_clock) begin
if (rst) begin
data_out_sync0 <= {WIDTH{1'b0}};
data_out_sync1 <= {WIDTH{1'b0}};
end else begin
data_out_sync0 <= data_in;
data_out_sync1 <= data_out_sync0;
end
end
assign data_out = data_out_sync1;
end
endgenerate
endmodule
| 6.875537 |
module alt_vipcti131_Vid2IS_sync_polarity_convertor (
input rst,
input clk,
input sync_in,
input datavalid,
output sync_out
);
wire datavalid_negedge;
reg datavalid_reg;
wire needs_invert_nxt;
reg needs_invert;
wire invert_sync_nxt;
reg invert_sync;
assign datavalid_negedge = datavalid_reg & ~datavalid;
assign needs_invert_nxt = (datavalid & sync_in) | needs_invert;
assign invert_sync_nxt = (datavalid_negedge) ? needs_invert_nxt : invert_sync;
always @(posedge rst or posedge clk) begin
if (rst) begin
datavalid_reg <= 1'b0;
needs_invert <= 1'b0;
invert_sync <= 1'b0;
end else begin
datavalid_reg <= datavalid;
needs_invert <= needs_invert_nxt & ~datavalid_negedge;
invert_sync <= invert_sync_nxt;
end
end
assign sync_out = sync_in ^ invert_sync_nxt;
endmodule
| 6.875537 |
module alt_vipcti131_Vid2IS_write_buffer #(
parameter DATA_WIDTH = 20,
NUMBER_OF_COLOUR_PLANES = 2,
BPS = 10
) (
input wire rst,
input wire clk,
input wire convert,
input wire hd_sdn,
input wire early_eop,
input wire wrreq_in,
input wire [DATA_WIDTH-1:0] data_in,
input wire packet_in,
output wire wrreq_out,
output wire [DATA_WIDTH-1:0] data_out,
output wire packet_out
);
reg [BPS-1:0] write_buffer_data[NUMBER_OF_COLOUR_PLANES-1:0];
reg [NUMBER_OF_COLOUR_PLANES-1:0] write_buffer_valid;
reg write_buffer_packet;
generate
begin : write_buffer_generation
genvar i;
for (i = 0; i < NUMBER_OF_COLOUR_PLANES; i = i + 1) begin : write_buffer_generation_for_loop
always @(posedge rst or posedge clk) begin
if (rst) begin
write_buffer_data[i] <= {BPS{1'b0}};
write_buffer_valid[i] <= 1'b0;
end else begin
if (wrreq_in && !early_eop) begin
if (!hd_sdn) begin
if (!convert) begin
// copy the ancilliary data into the Y (control packet copied as well
// but that won't affect anything)
write_buffer_data[i] <= data_in[BPS-1:0];
write_buffer_valid[i] <= 1'b1;
end else begin
if((i == 0) ? write_buffer_valid[i] == 0 || wrreq_out : write_buffer_valid[i] == 0 && write_buffer_valid[i-1] == 1) begin // decide which part of the buffer to insert the sample
write_buffer_data[i] <= data_in[BPS-1:0];
write_buffer_valid[i] <= 1'b1;
end else begin
if (wrreq_out) begin
write_buffer_valid[i] <= 1'b0; // clear the buffer
end
end
end
end else begin
write_buffer_data[i] <= data_in[(i*BPS)+(BPS-1):(i*BPS)];
write_buffer_valid[i] <= 1'b1;
end
end else begin
if (wrreq_out) begin
write_buffer_valid[i] <= 1'b0; // clear the buffer
end
end
end
end
assign data_out[(i*BPS)+(BPS-1):(i*BPS)] = write_buffer_data[i];
end
end
endgenerate
always @(posedge rst or posedge clk) begin
if (rst) begin
write_buffer_packet <= 1'b0;
end else begin
if (wrreq_in && !early_eop) begin
if (!hd_sdn) begin
if (packet_in) begin
write_buffer_packet <= 1'b1;
end else if (wrreq_out) begin
write_buffer_packet <= 1'b0;
end
end else begin
write_buffer_packet <= packet_in;
end
end else begin
if (wrreq_out) begin
write_buffer_packet <= 1'b0;
end
end
end
end
assign wrreq_out = (&write_buffer_valid) | early_eop;
assign packet_out = write_buffer_packet | early_eop;
endmodule
| 6.875537 |
module alt_vipitc130_common_fifo (
wrclk,
rdreq,
aclr,
rdclk,
wrreq,
data,
rdusedw,
rdempty,
wrusedw,
wrfull,
q
);
function integer alt_clogb2;
input [31:0] value;
integer i;
begin
alt_clogb2 = 32;
for (i = 31; i > 0; i = i - 1) begin
if (2 ** i >= value) alt_clogb2 = i;
end
end
endfunction
parameter DATA_WIDTH = 20;
parameter FIFO_DEPTH = 1920;
parameter CLOCKS_ARE_SAME = 0;
parameter DATA_WIDTHU = alt_clogb2(FIFO_DEPTH);
input wrclk;
input rdreq;
input aclr;
input rdclk;
input wrreq;
input [DATA_WIDTH-1:0] data;
output [DATA_WIDTHU-1:0] rdusedw;
output rdempty;
output [DATA_WIDTHU-1:0] wrusedw;
output wrfull;
output [DATA_WIDTH-1:0] q;
generate
if (CLOCKS_ARE_SAME) begin
assign rdusedw = wrusedw;
scfifo input_fifo (
.rdreq(rdreq),
.aclr(aclr),
.clock(wrclk),
.wrreq(wrreq),
.data(data),
.empty(rdempty),
.full(wrfull),
.usedw(wrusedw),
.q(q)
);
defparam input_fifo.add_ram_output_register = "OFF",
input_fifo.lpm_hint = "MAXIMIZE_SPEED=7,", input_fifo.lpm_numwords = FIFO_DEPTH,
input_fifo.lpm_showahead = "OFF", input_fifo.lpm_type = "scfifo", input_fifo.lpm_width =
DATA_WIDTH, input_fifo.lpm_widthu = DATA_WIDTHU, input_fifo.overflow_checking = "OFF",
input_fifo.underflow_checking = "OFF", input_fifo.use_eab = "ON";
end else begin
dcfifo input_fifo (
.wrclk(wrclk),
.rdreq(rdreq),
.aclr(aclr),
.rdclk(rdclk),
.wrreq(wrreq),
.data(data),
.rdusedw(rdusedw),
.rdempty(rdempty),
.wrfull(wrfull),
.wrusedw(wrusedw),
.q(q)
);
defparam input_fifo.lpm_hint = "MAXIMIZE_SPEED=7,", input_fifo.lpm_numwords = FIFO_DEPTH,
input_fifo.lpm_showahead = "OFF", input_fifo.lpm_type = "dcfifo", input_fifo.lpm_width =
DATA_WIDTH, input_fifo.lpm_widthu = DATA_WIDTHU, input_fifo.overflow_checking = "OFF",
input_fifo.rdsync_delaypipe = 5, input_fifo.underflow_checking = "OFF", input_fifo.use_eab
= "ON", input_fifo.wrsync_delaypipe = 5, input_fifo.read_aclr_synch = "ON";
end
endgenerate
endmodule
| 7.568016 |
module alt_vipitc130_common_frame_counter #(
parameter NUMBER_OF_COLOUR_PLANES = 0,
COLOUR_PLANES_ARE_IN_PARALLEL = 0,
LOG2_NUMBER_OF_COLOUR_PLANES = 0,
CONVERT_SEQ_TO_PAR = 0,
TOTALS_MINUS_ONE = 0
) (
input wire rst,
input wire clk,
input wire sclr,
// control signals
input wire enable,
input wire hd_sdn,
// frame sizes
input wire [13:0] h_total,
input wire [12:0] v_total,
// reset values
input wire [13:0] h_reset,
input wire [12:0] v_reset,
// outputs
output wire new_line,
output wire start_of_sample,
output wire [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] sample_ticks,
output reg [13:0] h_count,
output reg [12:0] v_count
);
wire count_sample;
alt_vipitc130_common_sample_counter sample_counter (
.rst(rst),
.clk(clk),
.sclr(sclr),
.hd_sdn(hd_sdn),
.count_cycle(enable),
.count_sample(count_sample),
.start_of_sample(start_of_sample),
.sample_ticks(sample_ticks)
);
defparam sample_counter.NUMBER_OF_COLOUR_PLANES = NUMBER_OF_COLOUR_PLANES,
sample_counter.COLOUR_PLANES_ARE_IN_PARALLEL = COLOUR_PLANES_ARE_IN_PARALLEL,
sample_counter.LOG2_NUMBER_OF_COLOUR_PLANES = LOG2_NUMBER_OF_COLOUR_PLANES;
wire [13:0] h_total_int;
wire [12:0] v_total_int;
generate
if (TOTALS_MINUS_ONE) begin : totals_minus_one_generate
assign h_total_int = h_total;
assign v_total_int = v_total;
end else begin
assign h_total_int = h_total - 14'd1;
assign v_total_int = v_total - 13'd1;
end
endgenerate
always @(posedge rst or posedge clk) begin
if (rst) begin
h_count <= 14'd0;
v_count <= 13'd0;
end else begin
if (sclr) begin
h_count <= h_reset + {{13{1'b0}}, count_sample & hd_sdn};
v_count <= v_reset;
end else if (enable) begin
if (new_line) begin
h_count <= 14'd0;
if (v_count >= v_total_int) v_count <= 13'd0;
else v_count <= v_count + 13'd1;
end else if (count_sample) h_count <= h_count + 14'd1;
end
end
end
assign new_line = (h_count >= h_total_int) && count_sample;
endmodule
| 7.568016 |
module alt_vipitc130_common_generic_count #(
parameter WORD_LENGTH = 12,
parameter MAX_COUNT = 1280,
parameter RESET_VALUE = 0,
parameter TICKS_WORD_LENGTH = 1,
parameter TICKS_PER_COUNT = 1
) (
input wire clk,
input wire reset_n,
input wire enable,
input wire enable_ticks,
input wire [WORD_LENGTH-1:0] max_count, // -1
output reg [WORD_LENGTH-1:0] count,
input wire restart_count,
input wire [WORD_LENGTH-1:0] reset_value,
output wire enable_count,
output wire start_count,
output wire [TICKS_WORD_LENGTH-1:0] cp_ticks
);
generate
if (TICKS_PER_COUNT == 1) begin
assign start_count = 1'b1;
assign enable_count = enable;
assign cp_ticks = 1'b0;
end else begin
reg [TICKS_WORD_LENGTH-1:0] ticks;
always @(posedge clk or negedge reset_n)
if (!reset_n) ticks <= {TICKS_WORD_LENGTH{1'b0}};
else
ticks <= (restart_count) ? {TICKS_WORD_LENGTH{1'b0}} :
(enable) ? (ticks >= TICKS_PER_COUNT - 1) ? {TICKS_WORD_LENGTH{1'b0}} : ticks + 1'b1 : ticks;
assign start_count = ticks == {TICKS_WORD_LENGTH{1'b0}} || !enable_ticks;
assign enable_count = enable && ((ticks >= TICKS_PER_COUNT - 1) || !enable_ticks);
assign cp_ticks = ticks & {TICKS_WORD_LENGTH{enable_ticks}};
end
endgenerate
always @(posedge clk or negedge reset_n)
if (!reset_n) count <= RESET_VALUE[WORD_LENGTH-1:0];
else
count <= (restart_count) ? reset_value :
(enable_count) ? (count < max_count) ? count + 1'b1 : {(WORD_LENGTH){1'b0}} : count;
endmodule
| 7.568016 |
module alt_vipitc130_common_sample_counter #(
parameter NUMBER_OF_COLOUR_PLANES = 0,
COLOUR_PLANES_ARE_IN_PARALLEL = 0,
LOG2_NUMBER_OF_COLOUR_PLANES = 0
) (
input wire rst,
input wire clk,
input wire sclr,
input wire count_cycle,
input wire hd_sdn,
output wire count_sample,
output wire start_of_sample,
output wire [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] sample_ticks
);
generate
if (NUMBER_OF_COLOUR_PLANES == 1) begin
assign count_sample = count_cycle;
assign start_of_sample = 1'b1;
assign sample_ticks = 1'b0;
end else begin
reg [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] count_valids;
wire new_sample;
assign new_sample = count_valids == (NUMBER_OF_COLOUR_PLANES - 1);
always @(posedge rst or posedge clk) begin
if (rst) begin
count_valids <= {LOG2_NUMBER_OF_COLOUR_PLANES{1'b0}};
end else begin
if (sclr) count_valids <= {{LOG2_NUMBER_OF_COLOUR_PLANES - 1{1'b0}}, count_cycle};
else
count_valids <= (count_cycle) ? (new_sample) ? {LOG2_NUMBER_OF_COLOUR_PLANES{1'b0}} : count_valids + 1 : count_valids;
end
end
assign count_sample = (hd_sdn) ? count_cycle : count_cycle & new_sample;
assign start_of_sample = (hd_sdn) ? 1'b1 : (count_valids == {LOG2_NUMBER_OF_COLOUR_PLANES{1'b0}});
assign sample_ticks = count_valids;
end
endgenerate
endmodule
| 7.568016 |
module alt_vipitc130_common_sync #(
parameter CLOCKS_ARE_SAME = 0,
WIDTH = 1
) (
input wire rst,
input wire sync_clock,
input wire [WIDTH-1:0] data_in,
output wire [WIDTH-1:0] data_out
);
(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name SDC_STATEMENT \"set_false_path -to [get_keepers *data_out_sync0*]\"" *)reg [WIDTH-1:0] data_out_sync0;
(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS" *)reg [WIDTH-1:0] data_out_sync1;
generate
if (CLOCKS_ARE_SAME) assign data_out = data_in;
else begin
always @(posedge rst or posedge sync_clock) begin
if (rst) begin
data_out_sync0 <= {WIDTH{1'b0}};
data_out_sync1 <= {WIDTH{1'b0}};
end else begin
data_out_sync0 <= data_in;
data_out_sync1 <= data_out_sync0;
end
end
assign data_out = data_out_sync1;
end
endgenerate
endmodule
| 7.568016 |
module alt_vipitc130_common_to_binary (
one_hot,
binary
);
parameter NO_OF_MODES = 3;
parameter LOG2_NO_OF_MODES = 2;
input [NO_OF_MODES-1:0] one_hot;
output [LOG2_NO_OF_MODES-1:0] binary;
generate
genvar binary_pos, one_hot_pos;
wire [(NO_OF_MODES*LOG2_NO_OF_MODES)-1:0] binary_values;
wire [(NO_OF_MODES*LOG2_NO_OF_MODES)-1:0] binary_values_by_bit;
for (
one_hot_pos = 0; one_hot_pos < NO_OF_MODES; one_hot_pos = one_hot_pos + 1
) begin : to_binary_one_hot_pos
assign binary_values[(one_hot_pos*LOG2_NO_OF_MODES)+(LOG2_NO_OF_MODES-1):(one_hot_pos*LOG2_NO_OF_MODES)] = (one_hot[one_hot_pos]) ? one_hot_pos + 1 : 0;
end
for (
binary_pos = 0; binary_pos < LOG2_NO_OF_MODES; binary_pos = binary_pos + 1
) begin : to_binary_binary_pos
for (
one_hot_pos = 0; one_hot_pos < NO_OF_MODES; one_hot_pos = one_hot_pos + 1
) begin : to_binary_one_hot_pos
assign binary_values_by_bit[(binary_pos*NO_OF_MODES)+one_hot_pos] = binary_values[(one_hot_pos*LOG2_NO_OF_MODES)+binary_pos];
end
assign binary[binary_pos] = |binary_values_by_bit[(binary_pos*NO_OF_MODES)+NO_OF_MODES-1:binary_pos*NO_OF_MODES];
end
endgenerate
endmodule
| 7.568016 |
module alt_vipitc130_common_trigger_sync (
input wire input_rst,
input wire input_clock,
input wire rst,
input wire sync_clock,
input wire trigger_in,
input wire ack_in,
output wire trigger_out
);
parameter CLOCKS_ARE_SAME = 0;
generate
if (CLOCKS_ARE_SAME) assign trigger_out = trigger_in;
else begin
reg trigger_in_reg;
reg toggle;
reg toggle_synched_reg;
wire toggle_synched;
always @(posedge input_rst or posedge input_clock) begin
if (input_rst) begin
trigger_in_reg <= 1'b0;
toggle <= 1'b0;
end else begin
trigger_in_reg <= trigger_in;
toggle <= toggle ^ (trigger_in & (~trigger_in_reg | ack_in));
end
end
alt_vipitc130_common_sync #(CLOCKS_ARE_SAME) toggle_sync (
.rst(rst),
.sync_clock(sync_clock),
.data_in(toggle),
.data_out(toggle_synched)
);
always @(posedge rst or posedge sync_clock) begin
if (rst) begin
toggle_synched_reg <= 1'b0;
end else begin
toggle_synched_reg <= toggle_synched;
end
end
assign trigger_out = toggle_synched ^ toggle_synched_reg;
end
endgenerate
endmodule
| 7.568016 |
module alt_vipitc130_IS2Vid_calculate_mode (
input [3:0] trs,
input is_interlaced,
input is_serial_output,
input [15:0] is_sample_count_f0,
input [15:0] is_line_count_f0,
input [15:0] is_sample_count_f1,
input [15:0] is_line_count_f1,
input [15:0] is_h_front_porch,
input [15:0] is_h_sync_length,
input [15:0] is_h_blank,
input [15:0] is_v_front_porch,
input [15:0] is_v_sync_length,
input [15:0] is_v_blank,
input [15:0] is_v1_front_porch,
input [15:0] is_v1_sync_length,
input [15:0] is_v1_blank,
input [15:0] is_ap_line,
input [15:0] is_v1_rising_edge,
input [15:0] is_f_rising_edge,
input [15:0] is_f_falling_edge,
input [15:0] is_anc_line,
input [15:0] is_v1_anc_line,
output interlaced_nxt,
output serial_output_nxt,
output [15:0] h_total_minus_one_nxt,
output [15:0] v_total_minus_one_nxt,
output [15:0] ap_line_nxt,
output [15:0] ap_line_end_nxt,
output [15:0] h_blank_nxt,
output [15:0] sav_nxt,
output [15:0] h_sync_start_nxt,
output [15:0] h_sync_end_nxt,
output [15:0] f2_v_start_nxt,
output [15:0] f1_v_start_nxt,
output [15:0] f1_v_end_nxt,
output [15:0] f2_v_sync_start_nxt,
output [15:0] f2_v_sync_end_nxt,
output [15:0] f1_v_sync_start_nxt,
output [15:0] f1_v_sync_end_nxt,
output [15:0] f_rising_edge_nxt,
output [15:0] f_falling_edge_nxt,
output [12:0] total_line_count_f0_nxt,
output [12:0] total_line_count_f1_nxt,
output [15:0] f2_anc_v_start_nxt,
output [15:0] f1_anc_v_start_nxt
);
wire [15:0] v_active_lines;
wire [15:0] v_total;
wire [15:0] v1_rising_edge;
wire [15:0] v2_rising_edge;
wire [15:0] f1_v_sync;
wire [15:0] f2_v_sync;
wire [15:0] total_line_count_f0_nxt_full;
wire [15:0] total_line_count_f1_nxt_full;
assign v_active_lines = (is_interlaced ? is_line_count_f1 : 16'd0) + is_line_count_f0;
assign v_total = v_active_lines + (is_interlaced ? is_v1_blank : 16'd0) + is_v_blank;
assign v1_rising_edge = is_v1_rising_edge - is_ap_line;
assign v2_rising_edge = v_active_lines + (is_interlaced ? is_v1_blank : 16'd0);
assign f1_v_sync = v1_rising_edge + is_v1_front_porch;
assign f2_v_sync = v2_rising_edge + is_v_front_porch;
assign interlaced_nxt = is_interlaced;
assign serial_output_nxt = is_serial_output;
// counter wrapping
assign h_total_minus_one_nxt = is_sample_count_f0 + is_h_blank - 16'd1;
assign v_total_minus_one_nxt = v_total - 16'd1;
// line numbering
assign ap_line_nxt = is_ap_line;
assign ap_line_end_nxt = v_total - is_ap_line;
// horizontal blanking end
assign h_blank_nxt = is_h_blank;
assign sav_nxt = is_h_blank - trs;
// horizontal sync start & end
assign h_sync_start_nxt = is_h_front_porch;
assign h_sync_end_nxt = is_h_front_porch + is_h_sync_length;
// f2 vertical blanking start
assign f2_v_start_nxt = v2_rising_edge;
// f1 vertical blanking start & end
assign f1_v_start_nxt = v1_rising_edge;
assign f1_v_end_nxt = v1_rising_edge + is_v1_blank;
// f2 vertical sync start & end
assign f2_v_sync_start_nxt = f2_v_sync;
assign f2_v_sync_end_nxt = f2_v_sync + is_v_sync_length;
// f1 vertical sync start and end
assign f1_v_sync_start_nxt = f1_v_sync;
assign f1_v_sync_end_nxt = f1_v_sync + is_v1_sync_length;
// f rising edge
assign f_rising_edge_nxt = is_f_rising_edge - is_ap_line;
assign f_falling_edge_nxt = v_total - (is_ap_line - is_f_falling_edge);
// sync generation
assign total_line_count_f0_nxt_full = is_line_count_f0 + (is_v_blank - is_v_front_porch + is_v1_front_porch) - 16'd1;
assign total_line_count_f1_nxt_full = is_line_count_f1 + (is_v1_blank - is_v1_front_porch + is_v_front_porch) - 16'd1;
assign total_line_count_f0_nxt = total_line_count_f0_nxt_full[12:0];
assign total_line_count_f1_nxt = total_line_count_f1_nxt_full[12:0];
// ancilliary data position
assign f2_anc_v_start_nxt = v_total - (is_ap_line - is_anc_line);
assign f1_anc_v_start_nxt = is_v1_anc_line - is_ap_line;
endmodule
| 7.568016 |
module alt_vipitc131_common_fifo (
wrclk,
rdreq,
aclr,
rdclk,
wrreq,
data,
rdusedw,
rdempty,
wrusedw,
wrfull,
q
);
function integer alt_clogb2;
input [31:0] value;
integer i;
begin
alt_clogb2 = 32;
for (i = 31; i > 0; i = i - 1) begin
if (2 ** i >= value) alt_clogb2 = i;
end
end
endfunction
parameter DATA_WIDTH = 20;
parameter FIFO_DEPTH = 1920;
parameter CLOCKS_ARE_SAME = 0;
parameter DATA_WIDTHU = alt_clogb2(FIFO_DEPTH);
input wrclk;
input rdreq;
input aclr;
input rdclk;
input wrreq;
input [DATA_WIDTH-1:0] data;
output [DATA_WIDTHU-1:0] rdusedw;
output rdempty;
output [DATA_WIDTHU-1:0] wrusedw;
output wrfull;
output [DATA_WIDTH-1:0] q;
generate
if (CLOCKS_ARE_SAME) begin
assign rdusedw = wrusedw;
scfifo input_fifo (
.rdreq(rdreq),
.aclr(aclr),
.clock(wrclk),
.wrreq(wrreq),
.data(data),
.empty(rdempty),
.full(wrfull),
.usedw(wrusedw),
.q(q)
);
defparam input_fifo.add_ram_output_register = "OFF",
input_fifo.lpm_hint = "MAXIMIZE_SPEED=7,", input_fifo.lpm_numwords = FIFO_DEPTH,
input_fifo.lpm_showahead = "OFF", input_fifo.lpm_type = "scfifo", input_fifo.lpm_width =
DATA_WIDTH, input_fifo.lpm_widthu = DATA_WIDTHU, input_fifo.overflow_checking = "OFF",
input_fifo.underflow_checking = "OFF", input_fifo.use_eab = "ON";
end else begin
dcfifo input_fifo (
.wrclk(wrclk),
.rdreq(rdreq),
.aclr(aclr),
.rdclk(rdclk),
.wrreq(wrreq),
.data(data),
.rdusedw(rdusedw),
.rdempty(rdempty),
.wrfull(wrfull),
.wrusedw(wrusedw),
.q(q)
);
defparam input_fifo.lpm_hint = "MAXIMIZE_SPEED=7,", input_fifo.lpm_numwords = FIFO_DEPTH,
input_fifo.lpm_showahead = "OFF", input_fifo.lpm_type = "dcfifo", input_fifo.lpm_width =
DATA_WIDTH, input_fifo.lpm_widthu = DATA_WIDTHU, input_fifo.overflow_checking = "OFF",
input_fifo.rdsync_delaypipe = 5, input_fifo.underflow_checking = "OFF", input_fifo.use_eab
= "ON", input_fifo.wrsync_delaypipe = 5, input_fifo.read_aclr_synch = "ON";
end
endgenerate
endmodule
| 7.512576 |
module alt_vipitc131_common_frame_counter #(
parameter NUMBER_OF_COLOUR_PLANES = 0,
COLOUR_PLANES_ARE_IN_PARALLEL = 0,
LOG2_NUMBER_OF_COLOUR_PLANES = 0,
CONVERT_SEQ_TO_PAR = 0,
TOTALS_MINUS_ONE = 0
) (
input wire rst,
input wire clk,
input wire sclr,
// control signals
input wire enable,
input wire hd_sdn,
// frame sizes
input wire [13:0] h_total,
input wire [12:0] v_total,
// reset values
input wire [13:0] h_reset,
input wire [12:0] v_reset,
// outputs
output wire new_line,
output wire start_of_sample,
output wire [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] sample_ticks,
output reg [13:0] h_count,
output reg [12:0] v_count
);
wire count_sample;
alt_vipitc131_common_sample_counter sample_counter (
.rst(rst),
.clk(clk),
.sclr(sclr),
.hd_sdn(hd_sdn),
.count_cycle(enable),
.count_sample(count_sample),
.start_of_sample(start_of_sample),
.sample_ticks(sample_ticks)
);
defparam sample_counter.NUMBER_OF_COLOUR_PLANES = NUMBER_OF_COLOUR_PLANES,
sample_counter.COLOUR_PLANES_ARE_IN_PARALLEL = COLOUR_PLANES_ARE_IN_PARALLEL,
sample_counter.LOG2_NUMBER_OF_COLOUR_PLANES = LOG2_NUMBER_OF_COLOUR_PLANES;
wire [13:0] h_total_int;
wire [12:0] v_total_int;
generate
if (TOTALS_MINUS_ONE) begin : totals_minus_one_generate
assign h_total_int = h_total;
assign v_total_int = v_total;
end else begin
assign h_total_int = h_total - 14'd1;
assign v_total_int = v_total - 13'd1;
end
endgenerate
always @(posedge rst or posedge clk) begin
if (rst) begin
h_count <= 14'd0;
v_count <= 13'd0;
end else begin
if (sclr) begin
h_count <= h_reset + {{13{1'b0}}, count_sample & hd_sdn};
v_count <= v_reset;
end else if (enable) begin
if (new_line) begin
h_count <= 14'd0;
if (v_count >= v_total_int) v_count <= 13'd0;
else v_count <= v_count + 13'd1;
end else if (count_sample) h_count <= h_count + 14'd1;
end
end
end
assign new_line = (h_count >= h_total_int) && count_sample;
endmodule
| 7.512576 |
module alt_vipitc131_common_generic_count #(
parameter WORD_LENGTH = 12,
parameter MAX_COUNT = 1280,
parameter RESET_VALUE = 0,
parameter TICKS_WORD_LENGTH = 1,
parameter TICKS_PER_COUNT = 1
) (
input wire clk,
input wire reset_n,
input wire enable,
input wire enable_ticks,
input wire [WORD_LENGTH-1:0] max_count, // -1
output reg [WORD_LENGTH-1:0] count,
input wire restart_count,
input wire [WORD_LENGTH-1:0] reset_value,
output wire enable_count,
output wire start_count,
output wire [TICKS_WORD_LENGTH-1:0] cp_ticks
);
generate
if (TICKS_PER_COUNT == 1) begin
assign start_count = 1'b1;
assign enable_count = enable;
assign cp_ticks = 1'b0;
end else begin
reg [TICKS_WORD_LENGTH-1:0] ticks;
always @(posedge clk or negedge reset_n)
if (!reset_n) ticks <= {TICKS_WORD_LENGTH{1'b0}};
else
ticks <= (restart_count) ? {TICKS_WORD_LENGTH{1'b0}} :
(enable) ? (ticks >= TICKS_PER_COUNT - 1) ? {TICKS_WORD_LENGTH{1'b0}} : ticks + 1'b1 : ticks;
assign start_count = ticks == {TICKS_WORD_LENGTH{1'b0}} || !enable_ticks;
assign enable_count = enable && ((ticks >= TICKS_PER_COUNT - 1) || !enable_ticks);
assign cp_ticks = ticks & {TICKS_WORD_LENGTH{enable_ticks}};
end
endgenerate
always @(posedge clk or negedge reset_n)
if (!reset_n) count <= RESET_VALUE[WORD_LENGTH-1:0];
else
count <= (restart_count) ? reset_value :
(enable_count) ? (count < max_count) ? count + 1'b1 : {(WORD_LENGTH){1'b0}} : count;
endmodule
| 7.512576 |
module alt_vipitc131_common_sample_counter #(
parameter NUMBER_OF_COLOUR_PLANES = 0,
COLOUR_PLANES_ARE_IN_PARALLEL = 0,
LOG2_NUMBER_OF_COLOUR_PLANES = 0
) (
input wire rst,
input wire clk,
input wire sclr,
input wire count_cycle,
input wire hd_sdn,
output wire count_sample,
output wire start_of_sample,
output wire [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] sample_ticks
);
generate
if (NUMBER_OF_COLOUR_PLANES == 1) begin
assign count_sample = count_cycle;
assign start_of_sample = 1'b1;
assign sample_ticks = 1'b0;
end else begin
reg [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] count_valids;
wire new_sample;
assign new_sample = count_valids == (NUMBER_OF_COLOUR_PLANES - 1);
always @(posedge rst or posedge clk) begin
if (rst) begin
count_valids <= {LOG2_NUMBER_OF_COLOUR_PLANES{1'b0}};
end else begin
if (sclr) count_valids <= {{LOG2_NUMBER_OF_COLOUR_PLANES - 1{1'b0}}, count_cycle};
else
count_valids <= (count_cycle) ? (new_sample) ? {LOG2_NUMBER_OF_COLOUR_PLANES{1'b0}} : count_valids + 1 : count_valids;
end
end
assign count_sample = (hd_sdn) ? count_cycle : count_cycle & new_sample;
assign start_of_sample = (hd_sdn) ? 1'b1 : (count_valids == {LOG2_NUMBER_OF_COLOUR_PLANES{1'b0}});
assign sample_ticks = count_valids;
end
endgenerate
endmodule
| 7.512576 |
module alt_vipitc131_common_sync #(
parameter CLOCKS_ARE_SAME = 0,
WIDTH = 1
) (
input wire rst,
input wire sync_clock,
input wire [WIDTH-1:0] data_in,
output wire [WIDTH-1:0] data_out
);
(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name SDC_STATEMENT \"set_false_path -to [get_keepers *data_out_sync0*]\"" *)reg [WIDTH-1:0] data_out_sync0;
(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS" *)reg [WIDTH-1:0] data_out_sync1;
generate
if (CLOCKS_ARE_SAME) assign data_out = data_in;
else begin
always @(posedge rst or posedge sync_clock) begin
if (rst) begin
data_out_sync0 <= {WIDTH{1'b0}};
data_out_sync1 <= {WIDTH{1'b0}};
end else begin
data_out_sync0 <= data_in;
data_out_sync1 <= data_out_sync0;
end
end
assign data_out = data_out_sync1;
end
endgenerate
endmodule
| 7.512576 |
module alt_vipitc131_common_to_binary (
one_hot,
binary
);
parameter NO_OF_MODES = 3;
parameter LOG2_NO_OF_MODES = 2;
input [NO_OF_MODES-1:0] one_hot;
output [LOG2_NO_OF_MODES-1:0] binary;
generate
genvar binary_pos, one_hot_pos;
wire [(NO_OF_MODES*LOG2_NO_OF_MODES)-1:0] binary_values;
wire [(NO_OF_MODES*LOG2_NO_OF_MODES)-1:0] binary_values_by_bit;
for (
one_hot_pos = 0; one_hot_pos < NO_OF_MODES; one_hot_pos = one_hot_pos + 1
) begin : to_binary_one_hot_pos
assign binary_values[(one_hot_pos*LOG2_NO_OF_MODES)+(LOG2_NO_OF_MODES-1):(one_hot_pos*LOG2_NO_OF_MODES)] = (one_hot[one_hot_pos]) ? one_hot_pos + 1 : 0;
end
for (
binary_pos = 0; binary_pos < LOG2_NO_OF_MODES; binary_pos = binary_pos + 1
) begin : to_binary_binary_pos
for (
one_hot_pos = 0; one_hot_pos < NO_OF_MODES; one_hot_pos = one_hot_pos + 1
) begin : to_binary_one_hot_pos
assign binary_values_by_bit[(binary_pos*NO_OF_MODES)+one_hot_pos] = binary_values[(one_hot_pos*LOG2_NO_OF_MODES)+binary_pos];
end
assign binary[binary_pos] = |binary_values_by_bit[(binary_pos*NO_OF_MODES)+NO_OF_MODES-1:binary_pos*NO_OF_MODES];
end
endgenerate
endmodule
| 7.512576 |
module alt_vipitc131_common_trigger_sync (
input wire input_rst,
input wire input_clock,
input wire rst,
input wire sync_clock,
input wire trigger_in,
input wire ack_in,
output wire trigger_out
);
parameter CLOCKS_ARE_SAME = 0;
generate
if (CLOCKS_ARE_SAME) assign trigger_out = trigger_in;
else begin
reg trigger_in_reg;
reg toggle;
reg toggle_synched_reg;
wire toggle_synched;
always @(posedge input_rst or posedge input_clock) begin
if (input_rst) begin
trigger_in_reg <= 1'b0;
toggle <= 1'b0;
end else begin
trigger_in_reg <= trigger_in;
toggle <= toggle ^ (trigger_in & (~trigger_in_reg | ack_in));
end
end
alt_vipitc131_common_sync #(CLOCKS_ARE_SAME) toggle_sync (
.rst(rst),
.sync_clock(sync_clock),
.data_in(toggle),
.data_out(toggle_synched)
);
always @(posedge rst or posedge sync_clock) begin
if (rst) begin
toggle_synched_reg <= 1'b0;
end else begin
toggle_synched_reg <= toggle_synched;
end
end
assign trigger_out = toggle_synched ^ toggle_synched_reg;
end
endgenerate
endmodule
| 7.512576 |
module alt_vipitc131_IS2Vid_calculate_mode (
input [3:0] trs,
input is_interlaced,
input is_serial_output,
input [15:0] is_sample_count_f0,
input [15:0] is_line_count_f0,
input [15:0] is_sample_count_f1,
input [15:0] is_line_count_f1,
input [15:0] is_h_front_porch,
input [15:0] is_h_sync_length,
input [15:0] is_h_blank,
input [15:0] is_v_front_porch,
input [15:0] is_v_sync_length,
input [15:0] is_v_blank,
input [15:0] is_v1_front_porch,
input [15:0] is_v1_sync_length,
input [15:0] is_v1_blank,
input [15:0] is_ap_line,
input [15:0] is_v1_rising_edge,
input [15:0] is_f_rising_edge,
input [15:0] is_f_falling_edge,
input [15:0] is_anc_line,
input [15:0] is_v1_anc_line,
output interlaced_nxt,
output serial_output_nxt,
output [15:0] h_total_minus_one_nxt,
output [15:0] v_total_minus_one_nxt,
output [15:0] ap_line_nxt,
output [15:0] ap_line_end_nxt,
output [15:0] h_blank_nxt,
output [15:0] sav_nxt,
output [15:0] h_sync_start_nxt,
output [15:0] h_sync_end_nxt,
output [15:0] f2_v_start_nxt,
output [15:0] f1_v_start_nxt,
output [15:0] f1_v_end_nxt,
output [15:0] f2_v_sync_start_nxt,
output [15:0] f2_v_sync_end_nxt,
output [15:0] f1_v_sync_start_nxt,
output [15:0] f1_v_sync_end_nxt,
output [15:0] f_rising_edge_nxt,
output [15:0] f_falling_edge_nxt,
output [12:0] total_line_count_f0_nxt,
output [12:0] total_line_count_f1_nxt,
output [15:0] f2_anc_v_start_nxt,
output [15:0] f1_anc_v_start_nxt
);
wire [15:0] v_active_lines;
wire [15:0] v_total;
wire [15:0] v1_rising_edge;
wire [15:0] v2_rising_edge;
wire [15:0] f1_v_sync;
wire [15:0] f2_v_sync;
wire [15:0] total_line_count_f0_nxt_full;
wire [15:0] total_line_count_f1_nxt_full;
assign v_active_lines = (is_interlaced ? is_line_count_f1 : 16'd0) + is_line_count_f0;
assign v_total = v_active_lines + (is_interlaced ? is_v1_blank : 16'd0) + is_v_blank;
assign v1_rising_edge = is_v1_rising_edge - is_ap_line;
assign v2_rising_edge = v_active_lines + (is_interlaced ? is_v1_blank : 16'd0);
assign f1_v_sync = v1_rising_edge + is_v1_front_porch;
assign f2_v_sync = v2_rising_edge + is_v_front_porch;
assign interlaced_nxt = is_interlaced;
assign serial_output_nxt = is_serial_output;
// counter wrapping
assign h_total_minus_one_nxt = is_sample_count_f0 + is_h_blank - 16'd1;
assign v_total_minus_one_nxt = v_total - 16'd1;
// line numbering
assign ap_line_nxt = is_ap_line;
assign ap_line_end_nxt = v_total - is_ap_line;
// horizontal blanking end
assign h_blank_nxt = is_h_blank;
assign sav_nxt = is_h_blank - trs;
// horizontal sync start & end
assign h_sync_start_nxt = is_h_front_porch;
assign h_sync_end_nxt = is_h_front_porch + is_h_sync_length;
// f2 vertical blanking start
assign f2_v_start_nxt = v2_rising_edge;
// f1 vertical blanking start & end
assign f1_v_start_nxt = v1_rising_edge;
assign f1_v_end_nxt = v1_rising_edge + is_v1_blank;
// f2 vertical sync start & end
assign f2_v_sync_start_nxt = f2_v_sync;
assign f2_v_sync_end_nxt = f2_v_sync + is_v_sync_length;
// f1 vertical sync start and end
assign f1_v_sync_start_nxt = f1_v_sync;
assign f1_v_sync_end_nxt = f1_v_sync + is_v1_sync_length;
// f rising edge
assign f_rising_edge_nxt = is_f_rising_edge - is_ap_line;
assign f_falling_edge_nxt = v_total - (is_ap_line - is_f_falling_edge);
// sync generation
assign total_line_count_f0_nxt_full = is_line_count_f0 + (is_v_blank - is_v_front_porch + is_v1_front_porch) - 16'd1;
assign total_line_count_f1_nxt_full = is_line_count_f1 + (is_v1_blank - is_v1_front_porch + is_v_front_porch) - 16'd1;
assign total_line_count_f0_nxt = total_line_count_f0_nxt_full[12:0];
assign total_line_count_f1_nxt = total_line_count_f1_nxt_full[12:0];
// ancilliary data position
assign f2_anc_v_start_nxt = v_total - (is_ap_line - is_anc_line);
assign f1_anc_v_start_nxt = is_v1_anc_line - is_ap_line;
endmodule
| 7.512576 |
module alt_vipswi130_common_stream_output #(
parameter DATA_WIDTH = 10
) (
input wire rst,
input wire clk,
// dout
input wire dout_ready,
output wire dout_valid,
output reg [DATA_WIDTH-1:0] dout_data,
output reg dout_sop,
output reg dout_eop,
// internal
output wire int_ready,
input wire int_valid,
input wire [DATA_WIDTH-1:0] int_data,
input wire int_sop,
input wire int_eop,
// control signals
input wire enable,
output wire synced
);
// Simple decode to detect the end of image packets. This allows us to
// synch multiple inputs.
reg image_packet;
reg synced_int;
reg enable_synced_reg;
wire image_packet_nxt;
wire synced_int_nxt;
wire enable_synced;
wire eop;
wire sop;
always @(posedge clk or posedge rst) begin
if (rst) begin
image_packet <= 1'b0;
synced_int <= 1'b1;
enable_synced_reg <= 1'b0;
end else begin
image_packet <= image_packet_nxt;
synced_int <= synced_int_nxt;
enable_synced_reg <= enable_synced;
end
end
assign sop = dout_valid & dout_sop;
assign eop = dout_valid & dout_eop;
assign image_packet_nxt = (sop && dout_data == 0) || (image_packet && ~eop);
assign synced_int_nxt = (image_packet & eop) | (synced_int & ~sop);
assign enable_synced = (synced_int_nxt) ? enable : enable_synced_reg;
assign synced = ~enable_synced;
// Register outputs and ready input
reg int_valid_reg;
reg int_ready_reg;
always @(posedge clk or posedge rst) begin
if (rst) begin
int_valid_reg <= 1'b0;
dout_data <= {DATA_WIDTH{1'b0}};
dout_sop <= 1'b0;
dout_eop <= 1'b0;
int_ready_reg <= 1'b0;
end else begin
if (int_ready_reg) begin
if (enable_synced) begin
int_valid_reg <= int_valid;
dout_data <= int_data;
dout_sop <= int_sop;
dout_eop <= int_eop;
end else begin
int_valid_reg <= 1'b0;
end
end
int_ready_reg <= dout_ready;
end
end
assign dout_valid = int_valid_reg & int_ready_reg;
assign int_ready = int_ready_reg & enable_synced;
endmodule
| 8.849096 |
module alt_vipswi130_switch_control #(
parameter AV_ADDRESS_WIDTH = 5,
AV_DATA_WIDTH = 16,
NO_INPUTS = 4,
NO_OUTPUTS = 4,
NO_SYNCS = 4
) (
input wire rst,
input wire clk,
// control
input wire [AV_ADDRESS_WIDTH-1:0] av_address,
input wire av_read,
output reg [ AV_DATA_WIDTH-1:0] av_readdata,
input wire av_write,
input wire [ AV_DATA_WIDTH-1:0] av_writedata,
// internal
output wire enable,
output reg [(NO_INPUTS*NO_OUTPUTS)-1:0] select,
input wire [ NO_SYNCS-1:0] synced
);
reg master_enable;
reg output_switch;
reg [NO_INPUTS-1:0] output_control[NO_OUTPUTS-1:0];
wire global_synced;
always @(posedge clk or posedge rst) begin
if (rst) begin
master_enable <= 1'b0;
output_switch <= 1'b0;
av_readdata <= {AV_DATA_WIDTH{1'b0}};
end else begin
if (av_write) begin
master_enable <= (av_address == 0) ? av_writedata[0] : master_enable;
end
output_switch <= (av_write && av_address == 2) ? av_writedata[0] : output_switch & ~global_synced;
if (av_read) begin
case (av_address)
0: av_readdata <= {{AV_DATA_WIDTH - 1{1'b0}}, master_enable};
2: av_readdata <= {{AV_DATA_WIDTH - 1{1'b0}}, output_switch};
default: av_readdata <= {{AV_DATA_WIDTH - 1{1'b0}}, !global_synced};
endcase
end
end
end
generate
genvar i;
for (i = 0; i < NO_OUTPUTS; i = i + 1) begin : control_loop
always @(posedge clk or posedge rst) begin
if (rst) begin
output_control[i] <= {NO_INPUTS{1'b0}};
select[(i*NO_INPUTS)+NO_INPUTS-1:(i*NO_INPUTS)] <= {NO_INPUTS{1'b0}};
end else begin
if (av_write && av_address == i + 3) begin
output_control[i] <= av_writedata[NO_INPUTS-1:0];
end
if (global_synced) begin
select[(i*NO_INPUTS)+NO_INPUTS-1:(i*NO_INPUTS)] <= output_control[i];
end
end
end
end
endgenerate
assign global_synced = &synced;
assign enable = master_enable & ~output_switch;
endmodule
| 8.849096 |
module alt_vipvfr130_common_avalon_mm_master (
clock,
reset,
// Avalon-MM master interface
av_clock,
av_reset,
av_address,
av_burstcount,
av_writedata,
av_readdata,
av_write,
av_read,
av_readdatavalid,
av_waitrequest,
// user algorithm interface
addr,
command,
is_burst,
is_write_not_read,
burst_length,
writedata,
write,
readdata,
read,
stall
);
parameter ADDR_WIDTH = 16;
parameter DATA_WIDTH = 16;
parameter MAX_BURST_LENGTH_REQUIREDWIDTH = 11;
parameter READ_USED = 1;
parameter WRITE_USED = 1;
parameter READ_FIFO_DEPTH = 8;
parameter WRITE_FIFO_DEPTH = 8;
parameter COMMAND_FIFO_DEPTH = 8;
parameter WRITE_TARGET_BURST_SIZE = 5;
parameter READ_TARGET_BURST_SIZE = 5;
parameter CLOCKS_ARE_SAME = 1;
parameter BURST_WIDTH = 6;
input clock;
input reset;
// Avalon-MM master interface
input av_clock;
input av_reset;
output [ADDR_WIDTH-1 : 0] av_address;
output [BURST_WIDTH-1 : 0] av_burstcount;
output [DATA_WIDTH-1 : 0] av_writedata;
input [DATA_WIDTH-1 : 0] av_readdata;
output av_write;
output av_read;
input av_readdatavalid;
input av_waitrequest;
// user algorithm interface
input [ADDR_WIDTH-1 : 0] addr;
input command;
input is_burst;
input is_write_not_read;
input [MAX_BURST_LENGTH_REQUIREDWIDTH-1 : 0] burst_length;
input [DATA_WIDTH-1 : 0] writedata;
input write;
output [DATA_WIDTH-1 : 0] readdata;
input read;
output stall;
// instantiate FU
alt_vipvfr130_common_avalon_mm_bursting_master_fifo #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.READ_USED(READ_USED),
.WRITE_USED(WRITE_USED),
.CMD_FIFO_DEPTH(COMMAND_FIFO_DEPTH),
.RDATA_FIFO_DEPTH(READ_FIFO_DEPTH),
.WDATA_FIFO_DEPTH(WRITE_FIFO_DEPTH),
.WDATA_TARGET_BURST_SIZE(WRITE_TARGET_BURST_SIZE),
.RDATA_TARGET_BURST_SIZE(READ_TARGET_BURST_SIZE),
.CLOCKS_ARE_SYNC(CLOCKS_ARE_SAME),
.BYTEENABLE_USED(0), // not used
.LEN_BE_WIDTH(MAX_BURST_LENGTH_REQUIREDWIDTH),
.BURST_WIDTH(BURST_WIDTH),
.INTERRUPT_USED(0), // not used
.INTERRUPT_WIDTH(8)
) fu_inst (
.clock(clock),
.reset(reset),
// ena must go low when dependencies of this functional unit stall.
// right now it's only dependent is itself as no other stalls affect it.
.ena (!stall),
.ready(),
.stall(stall),
//These stalls dont work with the single ena signal. So they aren't any use right now
//.stall_read (stall_in), // new FU output
//.stall_write (stall_out), // new FU output
//.stall_command (stall_command), // new FU output
.addr(addr),
.write(is_write_not_read),
.burst(is_burst),
.len_be(burst_length),
.cenable(1'b1),
.cenable_en(command),
.wdata(writedata),
.wenable(1'b1),
.wenable_en(write),
.rdata(readdata),
.renable(1'b1),
.renable_en(read),
.activeirqs(), // not used
.av_address(av_address),
.av_burstcount(av_burstcount),
.av_writedata(av_writedata),
.av_byteenable(), // not used
.av_write(av_write),
.av_read(av_read),
.av_clock(av_clock), // not used if CLOCKS_ARE_SAME = 1
.av_reset(av_reset), // not used inside FU
.av_readdata(av_readdata),
.av_readdatavalid(av_readdatavalid),
.av_waitrequest(av_waitrequest),
.av_interrupt(8'd0)
); // not used
endmodule
| 8.0499 |
module alt_vipvfr130_common_stream_output #(
parameter DATA_WIDTH = 10
) (
input wire rst,
input wire clk,
// dout
input wire dout_ready,
output wire dout_valid,
output reg [DATA_WIDTH-1:0] dout_data,
output reg dout_sop,
output reg dout_eop,
// internal
output wire int_ready,
input wire int_valid,
input wire [DATA_WIDTH-1:0] int_data,
input wire int_sop,
input wire int_eop,
// control signals
input wire enable,
output wire synced
);
// Simple decode to detect the end of image packets. This allows us to
// synch multiple inputs.
reg image_packet;
reg synced_int;
reg enable_synced_reg;
wire image_packet_nxt;
wire synced_int_nxt;
wire enable_synced;
wire eop;
wire sop;
always @(posedge clk or posedge rst) begin
if (rst) begin
image_packet <= 1'b0;
synced_int <= 1'b1;
enable_synced_reg <= 1'b0;
end else begin
image_packet <= image_packet_nxt;
synced_int <= synced_int_nxt;
enable_synced_reg <= enable_synced;
end
end
assign sop = dout_valid & dout_sop;
assign eop = dout_valid & dout_eop;
assign image_packet_nxt = (sop && dout_data == 0) || (image_packet && ~eop);
assign synced_int_nxt = (image_packet & eop) | (synced_int & ~sop);
assign enable_synced = (synced_int_nxt) ? enable : enable_synced_reg;
assign synced = ~enable_synced;
// Register outputs and ready input
reg int_valid_reg;
reg int_ready_reg;
always @(posedge clk or posedge rst) begin
if (rst) begin
int_valid_reg <= 1'b0;
dout_data <= {DATA_WIDTH{1'b0}};
dout_sop <= 1'b0;
dout_eop <= 1'b0;
int_ready_reg <= 1'b0;
end else begin
if (int_ready_reg) begin
if (enable_synced) begin
int_valid_reg <= int_valid;
dout_data <= int_data;
dout_sop <= int_sop;
dout_eop <= int_eop;
end else begin
int_valid_reg <= 1'b0;
end
end
int_ready_reg <= dout_ready;
end
end
assign dout_valid = int_valid_reg & int_ready_reg;
assign int_ready = int_ready_reg & enable_synced;
endmodule
| 8.0499 |
module alt_vipvfr130_common_unpack_data (
clock,
reset,
// read interface (memory side)
data_in,
read,
stall_in,
// write interface (user side)
data_out,
write,
stall_out,
// clear buffer
clear
);
// DATA_WIDTH_IN must not be smaller than DATA_WIDTH_OUT!
parameter DATA_WIDTH_IN = 128;
parameter DATA_WIDTH_OUT = 24;
input clock;
input reset;
// read interface
input [DATA_WIDTH_IN - 1 : 0] data_in;
//output reg read;
output read;
input stall_in;
// write interface
input stall_out;
output reg write;
output [DATA_WIDTH_OUT - 1:0] data_out;
input clear;
wire need_input;
wire ena;
assign ena = ~stall_in;
/*always @(posedge clock or posedge reset)
if (reset)
read <= 1'b0;
else
read <= need_input;
*/
assign read = need_input;
// Cusp FU instantiation
alt_vipvfr130_common_pulling_width_adapter #(
.IN_WIDTH (DATA_WIDTH_IN),
.OUT_WIDTH(DATA_WIDTH_OUT)
) fu_inst (
.clock(clock),
.reset(reset),
.input_data(data_in),
.need_input(need_input),
.output_data(data_out),
.pull(1'b1), // not explicitely needed
.pull_en(~stall_out),
.discard(1'b1), // not explicitely needed
.discard_en(clear),
.ena(ena)
);
always @(posedge clock or posedge reset)
if (reset) begin
write <= 1'b0;
end else if (~stall_out) begin
write <= ena;
end
endmodule
| 8.0499 |
module alt_vipvfr131_common_avalon_mm_master (
clock,
reset,
// Avalon-MM master interface
av_clock,
av_reset,
av_address,
av_burstcount,
av_writedata,
av_readdata,
av_write,
av_read,
av_readdatavalid,
av_waitrequest,
// user algorithm interface
addr,
command,
is_burst,
is_write_not_read,
burst_length,
writedata,
write,
readdata,
read,
stall
);
parameter ADDR_WIDTH = 16;
parameter DATA_WIDTH = 16;
parameter MAX_BURST_LENGTH_REQUIREDWIDTH = 11;
parameter READ_USED = 1;
parameter WRITE_USED = 1;
parameter READ_FIFO_DEPTH = 8;
parameter WRITE_FIFO_DEPTH = 8;
parameter COMMAND_FIFO_DEPTH = 8;
parameter WRITE_TARGET_BURST_SIZE = 5;
parameter READ_TARGET_BURST_SIZE = 5;
parameter CLOCKS_ARE_SAME = 1;
parameter BURST_WIDTH = 6;
input clock;
input reset;
// Avalon-MM master interface
input av_clock;
input av_reset;
output [ADDR_WIDTH-1 : 0] av_address;
output [BURST_WIDTH-1 : 0] av_burstcount;
output [DATA_WIDTH-1 : 0] av_writedata;
input [DATA_WIDTH-1 : 0] av_readdata;
output av_write;
output av_read;
input av_readdatavalid;
input av_waitrequest;
// user algorithm interface
input [ADDR_WIDTH-1 : 0] addr;
input command;
input is_burst;
input is_write_not_read;
input [MAX_BURST_LENGTH_REQUIREDWIDTH-1 : 0] burst_length;
input [DATA_WIDTH-1 : 0] writedata;
input write;
output [DATA_WIDTH-1 : 0] readdata;
input read;
output stall;
// instantiate FU
alt_vipvfr131_common_avalon_mm_bursting_master_fifo #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.READ_USED(READ_USED),
.WRITE_USED(WRITE_USED),
.CMD_FIFO_DEPTH(COMMAND_FIFO_DEPTH),
.RDATA_FIFO_DEPTH(READ_FIFO_DEPTH),
.WDATA_FIFO_DEPTH(WRITE_FIFO_DEPTH),
.WDATA_TARGET_BURST_SIZE(WRITE_TARGET_BURST_SIZE),
.RDATA_TARGET_BURST_SIZE(READ_TARGET_BURST_SIZE),
.CLOCKS_ARE_SYNC(CLOCKS_ARE_SAME),
.BYTEENABLE_USED(0), // not used
.LEN_BE_WIDTH(MAX_BURST_LENGTH_REQUIREDWIDTH),
.BURST_WIDTH(BURST_WIDTH),
.INTERRUPT_USED(0), // not used
.INTERRUPT_WIDTH(8)
) fu_inst (
.clock(clock),
.reset(reset),
// ena must go low when dependencies of this functional unit stall.
// right now it's only dependent is itself as no other stalls affect it.
.ena (!stall),
.ready(),
.stall(stall),
//These stalls dont work with the single ena signal. So they aren't any use right now
//.stall_read (stall_in), // new FU output
//.stall_write (stall_out), // new FU output
//.stall_command (stall_command), // new FU output
.addr(addr),
.write(is_write_not_read),
.burst(is_burst),
.len_be(burst_length),
.cenable(1'b1),
.cenable_en(command),
.wdata(writedata),
.wenable(1'b1),
.wenable_en(write),
.rdata(readdata),
.renable(1'b1),
.renable_en(read),
.activeirqs(), // not used
.av_address(av_address),
.av_burstcount(av_burstcount),
.av_writedata(av_writedata),
.av_byteenable(), // not used
.av_write(av_write),
.av_read(av_read),
.av_clock(av_clock), // not used if CLOCKS_ARE_SAME = 1
.av_reset(av_reset), // not used inside FU
.av_readdata(av_readdata),
.av_readdatavalid(av_readdatavalid),
.av_waitrequest(av_waitrequest),
.av_interrupt(8'd0)
); // not used
endmodule
| 8.433874 |
module alt_vipvfr131_common_stream_output #(
parameter DATA_WIDTH = 10
) (
input wire rst,
input wire clk,
// dout
input wire dout_ready,
output wire dout_valid,
output reg [DATA_WIDTH-1:0] dout_data,
output reg dout_sop,
output reg dout_eop,
// internal
output wire int_ready,
input wire int_valid,
input wire [DATA_WIDTH-1:0] int_data,
input wire int_sop,
input wire int_eop,
// control signals
input wire enable,
output wire synced
);
// Simple decode to detect the end of image packets. This allows us to
// synch multiple inputs.
reg image_packet;
reg synced_int;
reg enable_synced_reg;
wire image_packet_nxt;
wire synced_int_nxt;
wire enable_synced;
wire eop;
wire sop;
always @(posedge clk or posedge rst) begin
if (rst) begin
image_packet <= 1'b0;
synced_int <= 1'b1;
enable_synced_reg <= 1'b0;
end else begin
image_packet <= image_packet_nxt;
synced_int <= synced_int_nxt;
enable_synced_reg <= enable_synced;
end
end
assign sop = dout_valid & dout_sop;
assign eop = dout_valid & dout_eop;
assign image_packet_nxt = (sop && dout_data == 0) || (image_packet && ~eop);
assign synced_int_nxt = (image_packet & eop) | (synced_int & ~sop);
assign enable_synced = (synced_int_nxt) ? enable : enable_synced_reg;
assign synced = ~enable_synced;
// Register outputs and ready input
reg int_valid_reg;
reg int_ready_reg;
always @(posedge clk or posedge rst) begin
if (rst) begin
int_valid_reg <= 1'b0;
dout_data <= {DATA_WIDTH{1'b0}};
dout_sop <= 1'b0;
dout_eop <= 1'b0;
int_ready_reg <= 1'b0;
end else begin
if (int_ready_reg) begin
if (enable_synced) begin
int_valid_reg <= int_valid;
dout_data <= int_data;
dout_sop <= int_sop;
dout_eop <= int_eop;
end else begin
int_valid_reg <= 1'b0;
end
end
int_ready_reg <= dout_ready;
end
end
assign dout_valid = int_valid_reg & int_ready_reg;
assign int_ready = int_ready_reg & enable_synced;
endmodule
| 8.433874 |
module alt_vipvfr131_common_unpack_data (
clock,
reset,
// read interface (memory side)
data_in,
read,
stall_in,
// write interface (user side)
data_out,
write,
stall_out,
// clear buffer
clear
);
// DATA_WIDTH_IN must not be smaller than DATA_WIDTH_OUT!
parameter DATA_WIDTH_IN = 128;
parameter DATA_WIDTH_OUT = 24;
input clock;
input reset;
// read interface
input [DATA_WIDTH_IN - 1 : 0] data_in;
//output reg read;
output read;
input stall_in;
// write interface
input stall_out;
output reg write;
output [DATA_WIDTH_OUT - 1:0] data_out;
input clear;
wire need_input;
wire ena;
assign ena = ~stall_in;
/*always @(posedge clock or posedge reset)
if (reset)
read <= 1'b0;
else
read <= need_input;
*/
assign read = need_input;
// Cusp FU instantiation
alt_vipvfr131_common_pulling_width_adapter #(
.IN_WIDTH (DATA_WIDTH_IN),
.OUT_WIDTH(DATA_WIDTH_OUT)
) fu_inst (
.clock(clock),
.reset(reset),
.input_data(data_in),
.need_input(need_input),
.output_data(data_out),
.pull(1'b1), // not explicitely needed
.pull_en(~stall_out),
.discard(1'b1), // not explicitely needed
.discard_en(clear),
.ena(ena)
);
always @(posedge clock or posedge reset)
if (reset) begin
write <= 1'b0;
end else if (~stall_out) begin
write <= ena;
end
endmodule
| 8.433874 |
module alt_vip_common_flow_control_wrapper #(
parameter BITS_PER_SYMBOL = 8,
parameter SYMBOLS_PER_BEAT = 3
) (
input clk,
input rst,
// interface to decoder
output din_ready,
input din_valid,
input [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 1:0] din_data,
input [15:0] decoder_width,
input [15:0] decoder_height,
input [3:0] decoder_interlaced,
input decoder_end_of_video,
input decoder_is_video,
input decoder_vip_ctrl_valid,
// algorithm inputs from decoder
output [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 1:0] data_in,
output [15:0] width_in,
output [15:0] height_in,
output [3:0] interlaced_in,
output end_of_video_in,
output vip_ctrl_valid_in,
// algorithm outputs to encoder
input [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 1:0] data_out,
input [15:0] width_out,
input [15:0] height_out,
input [3:0] interlaced_out,
input vip_ctrl_valid_out,
input end_of_video_out,
// interface to encoder
input dout_ready,
output dout_valid,
output [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 1:0] dout_data,
output [15:0] encoder_width,
output [15:0] encoder_height,
output [3:0] encoder_interlaced,
output encoder_vip_ctrl_send,
input encoder_vip_ctrl_busy,
output encoder_end_of_video,
// flow control signals
input read,
input write,
output stall_in,
output stall_out
);
// conversion ready/valid to stall/read interface and filtering of active video
assign data_in = din_data;
assign end_of_video_in = decoder_end_of_video;
assign din_ready = ~decoder_is_video | read;
assign stall_in = ~(din_valid & decoder_is_video);
// conversion stall/write to ready/valid interface
assign dout_data = data_out;
assign encoder_end_of_video = end_of_video_out;
assign dout_valid = write;
assign stall_out = ~dout_ready;
// decoder control signals
assign width_in = decoder_width;
assign height_in = decoder_height;
assign interlaced_in = decoder_interlaced;
assign vip_ctrl_valid_in = decoder_vip_ctrl_valid;
reg [15:0] width_reg, height_reg;
reg [3:0] interlaced_reg;
reg vip_ctrl_valid_reg;
wire vip_ctrl_send_internal;
// encoder control signals
assign encoder_vip_ctrl_send = (vip_ctrl_valid_reg || vip_ctrl_valid_out) & ~encoder_vip_ctrl_busy;
assign encoder_width = vip_ctrl_valid_out ? width_out : width_reg;
assign encoder_height = vip_ctrl_valid_out ? height_out : height_reg;
assign encoder_interlaced = vip_ctrl_valid_out ? interlaced_out : interlaced_reg;
// connect control signals
always @(posedge clk or posedge rst)
if (rst) begin
width_reg <= 16'd640;
height_reg <= 16'd480;
interlaced_reg <= 4'd0;
vip_ctrl_valid_reg <= 1'b0;
end else begin
width_reg <= encoder_width;
height_reg <= encoder_height;
interlaced_reg <= encoder_interlaced;
if (vip_ctrl_valid_out || !encoder_vip_ctrl_busy) begin
vip_ctrl_valid_reg <= vip_ctrl_valid_out && encoder_vip_ctrl_busy;
end
end
endmodule
| 7.933786 |
module alt_vip_common_stream_output #(
parameter DATA_WIDTH = 10
) (
input wire rst,
input wire clk,
// dout
input wire dout_ready,
output wire dout_valid,
output reg [DATA_WIDTH-1:0] dout_data,
output reg dout_sop,
output reg dout_eop,
// internal
output wire int_ready,
input wire int_valid,
input wire [DATA_WIDTH-1:0] int_data,
input wire int_sop,
input wire int_eop,
// control signals
input wire enable,
output wire synced
);
// Simple decode to detect the end of image packets. This allows us to
// synch multiple inputs.
reg image_packet;
reg synced_int;
reg enable_synced_reg;
wire image_packet_nxt;
wire synced_int_nxt;
wire enable_synced;
wire eop;
always @(posedge clk or posedge rst) begin
if (rst) begin
image_packet <= 1'b0;
synced_int <= 1'b1;
enable_synced_reg <= 1'b0;
end else begin
image_packet <= image_packet_nxt;
synced_int <= synced_int_nxt;
enable_synced_reg <= enable_synced;
end
end
assign eop = dout_valid & dout_eop;
assign image_packet_nxt = (dout_sop && dout_data == 0) || (image_packet && ~eop);
assign synced_int_nxt = (image_packet & eop) | (synced_int & ~dout_sop);
assign enable_synced = (synced_int_nxt) ? enable : enable_synced_reg;
assign synced = ~enable_synced;
// Register outputs and ready input
reg int_valid_reg;
reg int_ready_reg;
always @(posedge clk or posedge rst) begin
if (rst) begin
int_valid_reg <= 1'b0;
dout_data <= {DATA_WIDTH{1'b0}};
dout_sop <= 1'b0;
dout_eop <= 1'b0;
int_ready_reg <= 1'b0;
end else begin
if (int_ready_reg) begin
if (enable_synced) begin
int_valid_reg <= int_valid;
dout_data <= int_data;
dout_sop <= int_sop;
dout_eop <= int_eop;
end else begin
int_valid_reg <= 1'b0;
end
end
int_ready_reg <= dout_ready;
end
end
assign dout_valid = int_valid_reg & int_ready_reg;
assign int_ready = int_ready_reg & enable_synced;
endmodule
| 7.933786 |
module alt_vram (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [14:0] address_a;
input [14:0] address_b;
input clock_a;
input clock_b;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire [31:0] q_a = sub_wire0[31:0];
wire [31:0] q_b = sub_wire1[31:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock_a),
.clock1 (clock_b),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 21504,
altsyncram_component.numwords_b = 21504,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 15,
altsyncram_component.widthad_b = 15,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
| 6.562369 |
module ALU (
Reg_A,
Reg_B,
ALUOp,
Reset,
BorN,
Branch_Flag,
ALU_Out
);
input [31:0] Reg_A, Reg_B;
input [2:0] ALUOp;
input [1:0] BorN;
input Reset;
output reg Branch_Flag;
output reg [31:0] ALU_Out;
reg [31:0] MOV, NOT, ADD, SUB, OR, AND, XOR, SLT;
always @(*) begin
if (Reset == 1) ALU_Out <= 32'b0;
else begin
MOV = Reg_B;
NOT = ~Reg_B;
ADD = Reg_B + Reg_A;
SUB = Reg_B - Reg_A;
OR = (Reg_A | Reg_B);
AND = (Reg_A & Reg_B);
XOR = Reg_A ^ Reg_B;
if (Reg_A >= Reg_B) SLT = 32'b1;
else SLT = 32'b0;
if (BorN == 2'b00) begin
if (Reg_A == Reg_B) Branch_Flag <= 1'b1;
else Branch_Flag <= 1'b0;
end
if (BorN == 2'b01) begin
if (Reg_A != Reg_B) Branch_Flag <= 1'b1;
else Branch_Flag <= 1'b0;
end
if (BorN == 2'b10) begin
if (Reg_A < Reg_B) Branch_Flag <= 1'b1;
else Branch_Flag <= 1'b0;
end
if (BorN == 2'b11) begin
if (Reg_A <= Reg_B) Branch_Flag <= 1'b1;
else Branch_Flag <= 1'b0;
end
case (ALUOp)
0: ALU_Out <= MOV;
1: ALU_Out <= NOT;
2: ALU_Out <= ADD;
3: ALU_Out <= SUB;
4: ALU_Out <= OR;
5: ALU_Out <= AND;
6: ALU_Out <= XOR;
7: ALU_Out <= SLT;
endcase
end
end
endmodule
| 6.708595 |
module ALUCtrl (
ALUSel,
ALUOp,
Funct
);
input [5:0] Funct;
input [1:0] ALUOp;
output reg [3:0] ALUSel;
parameter add = 0, sub = 1, sll = 2, slv = 3, srav = 4;
always @(ALUSel, ALUOp, Funct) begin
if (ALUOp == 0) ALUSel <= 0;
else if (ALUOp == 1) ALUSel <= 1;
else
case (Funct)
add: ALUSel = 0;
sub: ALUSel = 1;
sll: ALUSel = 2;
slv: ALUSel = 3;
srav: ALUSel = 4;
endcase
end
endmodule
| 6.86253 |
module ALU_decoder (
input [1:0] ALU_OP,
input [5:0] funct,
output reg [2:0] ALU_control
);
always @(*) begin
case (ALU_OP)
2'b00: begin
ALU_control = 3'b010;
end
2'b01: begin
ALU_control = 3'b100;
end
2'b10: begin
case (funct)
6'b10_0000: begin
ALU_control = 3'b010;
end
6'b10_0010: begin
ALU_control = 3'b100;
end
6'b10_1010: begin
ALU_control = 3'b110;
end
6'b01_1100: begin
ALU_control = 3'b101;
end
endcase
end
default: begin
ALU_control = 3'b010;
end
endcase
end
endmodule
| 6.956019 |
module ALU_mod (
input [31:0] SRC_A,
input [31:0] SRC_B,
input [2:0] ALU_control,
output reg [31:0] ALU_result,
output reg zero_flag
);
always @(*) begin
case (ALU_control)
3'b000: begin
ALU_result = SRC_A & SRC_B;
end
3'b001: begin
ALU_result = SRC_A | SRC_B;
end
3'b010: begin
ALU_result = SRC_A + SRC_B;
end
3'b011: begin
ALU_result = 'b0;
end
3'b100: begin
ALU_result = SRC_A - SRC_B;
end
3'b101: begin
ALU_result = SRC_A * SRC_B;
end
3'b110: begin
ALU_result = (SRC_A < SRC_B) ? 32'h0000_0001 : 32'h0000_0000;
end
3'b111: begin
ALU_result = 'b0;
end
default: begin
ALU_result = 'b0;
end
endcase
end
always @(*) begin
if (!ALU_result) zero_flag = 1'b1;
else zero_flag = 1'b0;
end
endmodule
| 6.855121 |
module ALU (
input1,
input2,
aluCtr,
zero,
aluRes
);
input [31:0] input1;
input [31:0] input2;
input [3:0] aluCtr;
output zero;
output [31:0] aluRes;
reg Zero;
reg [31:0] AluRes;
always @(input1 or input2 or aluCtr) begin
case (aluCtr)
4'b0010: AluRes = input1 + input2; //add
4'b0110: AluRes = input1 - input2; //subtract
4'b0000: AluRes = input1 & input2; //and
4'b0001: AluRes = input1 | input2; //or
//4'b0011: AluRes = input2 << input1; //sll
//4'b0100: AluRes = input2 >> input1; //srl
4'b0111: //slt
begin
if (input1 < input2) AluRes = 1;
else AluRes = 0;
end
4'b1100: begin
AluRes = ~(input1 | input2); //nor
end
4'b1101: begin
AluRes = input1 ^ input2; //xor
end
endcase
if (AluRes == 0) Zero = 1;
else Zero = 0;
end
assign zero = Zero;
assign aluRes = AluRes;
endmodule
| 7.960621 |
module for test bench
module test_alu;
// Declare variables to be connected to inputs and outputs
reg [15:0] x;
reg [15:0] y;
wire [15:0] z;
reg c_in;
wire c_out;
wire lt,eq,gt;
wire overflow;
reg [2:0] ALUOp;
alu test(x,y,z,c_in,c_out,lt,eq,gt,overflow,ALUOp);
initial
begin
// check AND operation
x=16'h1; y=16'h1; ALUOp=3'b000; c_in=0;
#1 $display("x=%b y=%b ALUOp=%b z=%b lt=%b eq=%b gt=%b",x,y,ALUOp,z,lt,eq,gt);
// check ORR operation
x=16'h1; y=16'h2; ALUOp=3'b001; c_in=0;
#1 $display("x=%b y=%b ALUOp=%b z=%b lt=%b eq=%b gt=%b",x,y,ALUOp,z,lt,eq,gt);
// check ADD operation without c_out
x=16'h1; y=16'h2; ALUOp=3'b010; c_in=0;
#1 $display("x=%b y=%b ALUOp=%b z=%b lt=%b eq=%b gt=%b c_out=%b overflow=%b",x,y,ALUOp,z,lt,eq,gt,c_out,overflow);
// check ADD operation with c_out
x=16'hAAAA; y=16'hAAAA; ALUOp=3'b010; c_in=0;
#1 $display("x=%b y=%b ALUOp=%b z=%b lt=%b eq=%b gt=%b c_out=%b overflow=%b",x,y,ALUOp,z,lt,eq,gt,c_out,overflow);
// check ADD operation with c_in
x=16'hAAAA; y=16'hAAAA; ALUOp=3'b010; c_in=1;
#1 $display("x=%b y=%b ALUOp=%b z=%b lt=%b eq=%b gt=%b c_out=%b overflow=%b",x,y,ALUOp,z,lt,eq,gt,c_out,overflow);
// check SUB operation
x=16'h2; y=16'h1; ALUOp=3'b011; c_in=0;
#1 $display("x=%b y=%b ALUOp=%b z=%b lt=%b eq=%b gt=%b c_out=%b overflow=%b",x,y,ALUOp,z,lt,eq,gt,c_out,overflow);
x=16'hAAAA; y=16'hAAAA; ALUOp=3'b011; c_in=0;
#1 $display("x=%b y=%b ALUOp=%b z=%b lt=%b eq=%b gt=%b c_out=%b overflow=%b",x,y,ALUOp,z,lt,eq,gt,c_out,overflow);
// check SLT operation (x>y)
x=16'h4; y=16'h2; ALUOp=3'b111; c_in=0;
#1 $display("x=%b y=%b ALUOp=%b z=%b lt=%b eq=%b gt=%b",x,y,ALUOp,z,lt,eq,gt);
// check SLT operation (x<y)
x=16'h2; y=16'h4; ALUOp=3'b111; c_in=0;
#1 $display("x=%b y=%b ALUOp=%b z=%b lt=%b eq=%b gt=%b",x,y,ALUOp,z,lt,eq,gt);
// check SLT operation (x=y)
x=16'h2; y=16'h2; ALUOp=3'b111; c_in=0;
#1 $display("x=%b y=%b ALUOp=%b z=%b lt=%b eq=%b gt=%b",x,y,ALUOp,z,lt,eq,gt);
end
endmodule
| 7.417889 |
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