code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module altmemddr_mem_model_ram_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [127:0] q;
input [127:0] data;
input [23:0] rdaddress;
input rdclken;
input [23:0] wraddress;
input wrclock;
input wren;
//PETES CHANGE - ... | 6.564346 |
module altmemddr_phy_alt_mem_phy_delay (
s_in,
s_out
);
//parameters
parameter WIDTH = 1;
parameter DELAY_PS = 10;
//ports
input wire [WIDTH - 1 : 0] s_in;
output wire [WIDTH - 1 : 0] s_out;
//model the transport delay
assign #(DELAY_PS) s_out = s_in;
endmodule
| 7.636203 |
module altmemddr_phy_alt_mem_phy_reset_pipe (
input wire clock,
input wire pre_clear,
output wire reset_out
);
parameter PIPE_DEPTH = 4;
// Declare pipeline registers.
reg [PIPE_DEPTH - 1 : 0] ams_pipe;
integer i;
// begin : RESET_PIPE
always @(posedge clock or n... | 7.636203 |
module altor32_alu (
input_a,
input_b,
func,
result
);
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input [31:0] input_a /*verilator public*/;
input [31:0] input_b /*verilator public*/;
input... | 8.984213 |
module altor32_lfu (
// Opcode
input [7:0] opcode_i /*verilator public*/,
// Memory load result
input [31:0] mem_result_i /*verilator public*/,
input [ 1:0] mem_offset_i /*verilator public*/,
// Result
output reg [31:0] load_result_o /*verilator public*/,
output reg load_ins... | 7.227236 |
module altor32_lsu (
// Current instruction
input opcode_valid_i /*verilator public*/,
input [7:0] opcode_i /*verilator public*/,
// Load / Store pending
input load_pending_i /*verilator public*/,
input store_pending_i /*verilator public*/,
// Load dest register
input [4:0] r... | 7.837467 |
module altor32_noicache (
input clk_i /*verilator public*/,
input rst_i /*verilator public*/,
// Processor interface
input rd_i /*verilator public*/,
input [31:0] pc_i /*verilator public*/,
output [31:0] instruction_o /*verilator public*/,
output valid_o /*verilator pu... | 8.370186 |
module altor32_ram_dp #(
parameter WIDTH = 8,
parameter SIZE = 14
) (
input aclk_i /*verilator public*/,
output [(WIDTH - 1):0] adat_o /*verilator public*/,
input [(WIDTH - 1):0] adat_i /*verilator public*/,
input [ (SIZE - 1):0] aadr_i /*verilator public*/,
input ... | 8.212447 |
module altor32_ram_sp #(
parameter [31:0] WIDTH = 8,
parameter [31:0] SIZE = 14
) (
input clk_i /*verilator public*/,
output [(WIDTH - 1):0] dat_o /*verilator public*/,
input [(WIDTH - 1):0] dat_i /*verilator public*/,
input [ (SIZE - 1):0] adr_i /*verilator public*/,
... | 8.348214 |
module altor32_regfile_alt (
input clk_i /*verilator public*/,
input rst_i /*verilator public*/,
input wr_i /*verilator public*/,
input [ 4:0] ra_i /*verilator public*/,
input [ 4:0] rb_i /*verilator public*/,
input [ 4:0] rd_i /*verilator... | 7.549143 |
module altor32_regfile_xil (
input clk_i /*verilator public*/,
input rst_i /*verilator public*/,
input wr_i /*verilator public*/,
input [ 4:0] ra_i /*verilator public*/,
input [ 4:0] rb_i /*verilator public*/,
input [ 4:0] rd_i /*verilator... | 7.549143 |
module altor32_writeback (
// General
input clk_i /*verilator public*/,
input rst_i /*verilator public*/,
// Opcode
input [31:0] opcode_i /*verilator public*/,
// Register target
input [4:0] rd_i /*verilator public*/,
// ALU result
input [31:0] alu_result_i /*verilator public... | 8.02051 |
module construct of the Avalon Streaming receive port for the
// chaining DMA application MSI signals.
//-----------------------------------------------------------------------------
// Copyright (c) 2009 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents,... | 6.967781 |
module altpcierd_cdma_ecrc_gen_calc #(
parameter AVALON_ST_128 = 0
) (
clk,
rstn,
crc_data,
crc_valid,
crc_empty,
crc_eop,
crc_sop,
ecrc,
crc_ack
);
input clk;
input rstn;
input [127:0] crc_data;
input crc_valid;
input [3:0] crc_empty;
input crc_eop;
input crc_sop;... | 6.83792 |
module altpcierd_cdma_ecrc_gen_datapath (
clk,
rstn,
data_in,
data_valid,
rdreq,
data_out,
data_out_valid,
full
);
input clk;
input rstn;
input [135:0] data_in;
input data_valid;
input rdreq;
output [135:0] data_out;
output data_out_valid;
output full;
wire emp... | 6.83792 |
module altpcierd_compliance_test (
input local_rstn, // Local board reset
input pcie_rstn, // PCIe reset
input refclk, // 100 Mhz clock
input req_compliance_push_button_n,// Push button to cycle through compliance mode, gen1, gen2 - Active low
input req_compliance_soft_ctrl , // Register to cyc... | 7.948987 |
module altpcierd_icm_fifo #(
parameter RAMTYPE = "RAM_BLOCK_TYPE=M512",
parameter USEEAB = "ON"
) (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
almost_full,
empty,
full,
q
);
input aclr;
input clock;
input [107:0] data;
input rdreq;
input wrreq;
output a... | 7.142683 |
module altpcierd_icm_fifo_lkahd #(
parameter RAMTYPE = "RAM_BLOCK_TYPE=M512",
parameter USEEAB = "ON",
parameter ALMOST_FULL = 10,
parameter NUMWORDS = 16,
parameter WIDTHU = 4
) (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
almost_full,
empty,
full,
q,
... | 7.142683 |
module altpcierd_icm_msibridge (
clk,
rstn,
data_valid,
data_in,
data_ack,
msi_ack,
msi_req,
msi_num,
msi_tc
);
input clk;
input rstn;
input data_valid;
input [107:0] data_in;
input msi_ack;
output data_ack;
output msi_req;
output [4:0] msi_num;
output [2:0] ms... | 7.142683 |
module altpcierd_icm_sideband (
clk,
rstn,
cfg_busdev,
cfg_devcsr,
cfg_linkcsr,
cfg_msicsr,
cfg_prmcsr,
cfg_tcvcmap,
app_int_sts,
app_int_sts_ack,
pex_msi_num,
cpl_err,
cpl_pending,
cfg_busdev_del,
cfg_devcsr_del,
cfg_linkcsr_del,
cfg_msicsr_del,
c... | 7.142683 |
module stratixiv_pciehip_dprio_bit (
reset,
clk,
sig_in,
ext_in,
serial_mode,
si,
shift,
mdio_dis,
sig_out,
so
);
input reset; // reset
input clk; // clock
input sig_in; // signal input
input ext_in; // external input port
input serial_mode; // serial shift mode e... | 6.746782 |
module stratixiv_pciehip_compute_bit (
input wire [63:0] datain,
input wire s,
output wire r
);
// begin
assign r = datain[0] ^ datain[1] ^ datain[2] ^ datain[3] ^ datain[4] ^ datain[5] ^ datain[6] ^ datain[7] ^ datain[10] ^ datain[13] ^ datain[14] ^ datain[17] ^
datain[2... | 6.746782 |
module stratixiv_pciehip_ecc_gen (
input wire [63:0] datain, // Data on which ECC is required
input wire [ 7:0] syndrome, // Syndrome uses 8'h00 while generating
output wire [ 7:0] result // Result
);
//-----------------------------------------------------------------------------
// Instan... | 6.746782 |
module stratixiv_pciehip_ecc_decoder (
flag,
derr,
derr_cor
);
input [2:0] flag;
output derr;
output derr_cor;
assign derr = flag[2] & ~(flag[1]) & flag[0];
assign derr_cor = ~(flag[2]) & flag[1] & flag[0];
endmodule
| 6.746782 |
module stratixiv_pciehip_pulse_ext (
core_clk,
rstn,
srst,
derr_cor,
derr_cor_ext
);
input core_clk;
input rstn;
input srst;
input derr_cor;
output derr_cor_ext;
reg n1, derr_cor_ext;
wire n2;
// Pulse width extender
always @(negedge rstn or posedge core_clk) begin
if (rstn... | 6.746782 |
module stratixiv_pciehip_pciexp_dcfiforam (
data,
wren,
wraddress,
rdaddress,
wrclock,
rdclock,
q
);
parameter addr_width = 4;
parameter data_width = 32;
input [data_width - 1:0] data;
input wren;
input [addr_width - 1:0] wraddress;
input [addr_width - 1:0] rdaddress;
input wr... | 6.746782 |
module stratixiv_pciehip_pciexp_dcram_rtry (
wrclock,
wren,
wraddress,
data,
rdclock,
rdaddress,
q
);
parameter addr_width = 'd4;
parameter data_width = 'd32;
input wrclock;
input wren;
input [data_width - 1:0] data;
input [addr_width - 1:0] wraddress;
input rdclock;
input ... | 6.746782 |
module stratixiv_pciehip_pciexp_dcram_rxvc (
wrclock,
wren,
wraddress,
data,
rdclock,
rdaddress,
q
);
parameter addr_width = 'd4;
parameter data_width = 'd32;
input wrclock;
input wren;
input [data_width - 1:0] data;
input [addr_width - 1:0] wraddress;
input rdclock;
input ... | 6.746782 |
module cycloneiv_hssi_tx_pma_sub_reg (
input wire clk,
input tri1 ena,
input wire d,
input tri1 clrn,
input tri1 prn,
output wire q
);
// BUFFER INPUTS
// INTERNAL VARIABLES
reg q_tmp;
wire q_wire;
// TIMING PATHS
specify
$setuphold(posedge clk, d, 0, 0);
(posedge cl... | 8.011405 |
module cycloneiv_hssi_tx_pma_sub_out_block #(
parameter bypass_serializer = "false",
parameter invert_clock = "false",
parameter use_falling_clock_edge = "false"
) (
input wire clk,
input wire datain,
input wire devclrn,
input wire devpor,
output wire dataout
);
// INTERNAL VARIAB... | 8.011405 |
module cycloneiv_hssi_tx_pma_sub_parallel_register #(
parameter channel_width = 4
) (
input wire clk,
input wire enable,
input wire [channel_width - 1:0] datain,
input wire devclrn,
input wire devpor,
output wire [channel_width - 1:0] dataout
);
// INTERNAL VARIABLES AND NETS
reg clk_la... | 8.011405 |
module cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2 (
input wire clk,
input wire reset_n,
output reg clkout
);
wire next_val;
// SPR:328849 - initialize clkout because reset_n is optional
initial clkout = 1'b0;
// state definition
always @(posedge clk or negedge reset_n) begin
if (!reset... | 8.011405 |
module cycloneiv_hssi_tx_pma_sub_tx_rx_det_clk_gen (
input wire clk,
input wire reset_n,
output wire clkout
);
wire clk8m, clk4m, clk2m;
cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2 div_1 (
.clk(clk),
.reset_n(reset_n),
.clkout(clk8m)
);
cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_... | 8.011405 |
module cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_sync (
input wire clk,
input wire reset_n,
input wire rcv_det,
output reg rcv_det_out
); // synthesis syn_black_box
reg rcv_det_mid;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
rcv_det_out <= 1'b0;
rcv_d... | 8.011405 |
module cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_fsm (
input wire clk,
input wire reset_n,
input wire com_pass,
input wire probe_pass,
output reg det_on,
output reg detect_valid,
output reg rcv_found
); // synthesis syn_black_box
reg [2:0] STATE;
reg [2:0] NEXTSTATE;
reg... | 8.011405 |
module cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_control (
input wire clk,
input wire rcv_det_en,
input wire rcv_det_pdb,
input wire com_pass,
input wire probe_pass,
output wire det_on,
output wire detect_valid,
output wire rcv_found
);
wire rcv_det_syn;
cycloneiv_hssi_tx_pm... | 8.011405 |
module cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_digital (
input wire oscclk,
input wire rcv_det_pdb,
input wire rcv_det_en,
input wire com_pass,
input wire probe_pass,
output wire det_on,
output wire detect_valid,
output wire rcv_found
);
wire clk;
cycloneiv_hssi_tx_pma_sub... | 8.011405 |
module is the behavior model for rx_det block
// If there is rx - set parameter RX_EXIST to 1, set to 0 otherwise
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneiv_hssi_tx_pma_sub_tx_rx_det
//
// Description : Receiver detect
//
////////////////////////////... | 7.595207 |
module receives serial data and outputs
// parallel data word of width = channel_width
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cycloneiv_hssi_rx_pma_sub_deser
#(
parameter channel_width = 8
)
(
input wire fclk,
input wire... | 6.910834 |
module cycloneiv_hssi_rx_pma_sub_clkdiv (
input wire rxfclk,
input wire clr,
input wire [3:0] deser_fact,
output reg loaden,
output reg clkdivrx
);
integer clk_count;
reg first_clkcount;
reg clkdivrx_prev;
reg rxloaden;
initial begin
first_clkcount = 1'b0;
clkdivrx_prev = 1'b0;
... | 8.011405 |
module cycloneiv_hssi_pcs_reset (
hard_reset,
clk_2_b,
refclk_b_in,
scan_mode,
rxpcs_rst,
txpcs_rst,
rxrst_int,
txrst_int
);
input hard_reset;
input clk_2_b;
input refclk_b_in;
input scan_mode;
input rxpcs_rst;
input txpcs_rst;
output rxrst_int;
output txrst_int;
reg... | 8.011405 |
module cycloneiv_hssi_tx_digis_txclk_gating (
select_n,
clk1,
clk2,
clk1out_n,
clk2out_n
);
input select_n;
input clk1;
input clk2;
output clk1out_n;
output clk2out_n;
assign clk1out_n = ~(select_n | clk1);
assign clk2out_n = ~(~select_n | clk2);
endmodule
| 8.011405 |
module cycloneiv_hssi_rx_digis_rxclk_gating (
select_n,
clk1,
clk2,
clk1out_n,
clk2out_n
);
input select_n;
input clk1;
input clk2;
output clk1out_n;
output clk2out_n;
assign clk1out_n = ~(select_n | clk1);
assign clk2out_n = ~(~select_n | clk2);
endmodule
| 8.011405 |
module cycloneiv_hssi_cmu_clk_gating (
select_n,
clk1,
clk2,
clk1out_n,
clk2out_n
);
input select_n;
input clk1;
input clk2;
output clk1out_n;
output clk2out_n;
assign clk1out_n = ~(select_n | clk1);
assign clk2out_n = ~(~select_n | clk2);
endmodule
| 8.011405 |
module cycloneiv_hssi_cmu_clk_ctl (
pclk_pma,
refclk_dig,
mdc,
ser_clk,
ser_mode,
scan_mode,
scan_clk,
rfreerun_centrl,
rcentrl_clk_sel,
rrefclk_out_div2,
hard_reset,
txrst,
refclk_pma_out,
mdc_b,
refclk_out,
rauto_speed_ena,
rfreq_sel,
gen2ngen1_b... | 8.011405 |
module cycloneiv_hssi_cmu_rxclk_gating (
select_n,
clk1,
clk2,
clk1out_n,
clk2out_n
);
input select_n;
input clk1;
input clk2;
output clk1out_n;
output clk2out_n;
assign clk1out_n = ~(select_n | clk1);
assign clk2out_n = ~(~select_n | clk2);
endmodule
| 8.011405 |
module cycloneiv_hssi_cmu_txclk_gating (
select_n,
clk1,
clk2,
clk1out_n,
clk2out_n
);
input select_n;
input clk1;
input clk2;
output clk1out_n;
output clk2out_n;
assign clk1out_n = ~(select_n | clk1);
assign clk2out_n = ~(~select_n | clk2);
endmodule
| 8.011405 |
module cycloneiv_hssi_cmu_dprio_bit (
reset,
clk,
sig_in,
ext_in,
serial_mode,
si,
shift,
mdio_dis,
sig_out,
so
);
input reset; // reset
input clk; // clock
input sig_in; // signal input
input ext_in; // external input port
input serial_mode; // serial shift mode ... | 8.011405 |
module cycloneiv_hssi_cmu_dprio_bit_pma (
reset,
clk,
sig_in,
ext_in,
serial_mode,
si,
shift,
mdio_dis,
pma_cram_test,
sig_out,
so
);
input reset; // reset
input clk; // clock
input sig_in; // signal input
input ext_in; // external input port
input serial_mode;... | 8.011405 |
module cycloneiv_hssi_calibration_block (
clk,
powerdn,
testctrl,
calibrationstatus,
nonusertocmu
);
// *** End of Section 3 ***
// *** Section 4 -- Parameter declarations and default values ***
parameter lpm_type = "cycloneiv_hssi_calibration_block";
parameter cont_cal_mode = "false";
... | 8.011405 |
module cycloneiv_pciehip_dprio_bit (
reset,
clk,
sig_in,
ext_in,
serial_mode,
si,
shift,
mdio_dis,
sig_out,
so
);
input reset; // reset
input clk; // clock
input sig_in; // signal input
input ext_in; // external input port
input serial_mode; // serial shift mode e... | 7.364512 |
module cycloneiv_pciehip_compute_bit (
input wire [63:0] datain,
input wire s,
output wire r
);
// begin
assign r = datain[0] ^ datain[1] ^ datain[2] ^ datain[3] ^ datain[4] ^ datain[5] ^ datain[6] ^ datain[7] ^ datain[10] ^ datain[13] ^ datain[14] ^ datain[17] ^
datain[2... | 7.364512 |
module cycloneiv_pciehip_ecc_gen (
input wire [63:0] datain, // Data on which ECC is required
input wire [ 7:0] syndrome, // Syndrome uses 8'h00 while generating
output wire [ 7:0] result // Result
);
//-----------------------------------------------------------------------------
// Instan... | 7.364512 |
module cycloneiv_pciehip_ecc_decoder (
flag,
derr,
derr_cor
);
input [2:0] flag;
output derr;
output derr_cor;
assign derr = flag[2] & ~(flag[1]) & flag[0];
assign derr_cor = ~(flag[2]) & flag[1] & flag[0];
endmodule
| 7.364512 |
module cycloneiv_pciehip_pulse_ext (
core_clk,
rstn,
srst,
derr_cor,
derr_cor_ext
);
input core_clk;
input rstn;
input srst;
input derr_cor;
output derr_cor_ext;
reg n1, derr_cor_ext;
wire n2;
// Pulse width extender
always @(negedge rstn or posedge core_clk) begin
if (rstn... | 7.364512 |
module cycloneiv_pciehip_pciexp_dcfiforam (
data,
wren,
wraddress,
rdaddress,
wrclock,
rdclock,
q
);
parameter addr_width = 4;
parameter data_width = 32;
input [data_width - 1:0] data;
input wren;
input [addr_width - 1:0] wraddress;
input [addr_width - 1:0] rdaddress;
input wr... | 7.364512 |
module cycloneiv_pciehip_pciexp_dcram_rtry (
wrclock,
wren,
wraddress,
data,
rdclock,
rdaddress,
q
);
parameter addr_width = 'd4;
parameter data_width = 'd32;
input wrclock;
input wren;
input [data_width - 1:0] data;
input [addr_width - 1:0] wraddress;
input rdclock;
input ... | 7.364512 |
module cycloneiv_pciehip_pciexp_dcram_rxvc (
wrclock,
wren,
wraddress,
data,
rdclock,
rdaddress,
q
);
parameter addr_width = 'd4;
parameter data_width = 'd32;
input wrclock;
input wren;
input [data_width - 1:0] data;
input [addr_width - 1:0] wraddress;
input rdclock;
input ... | 7.364512 |
module is not intended to be instantiated by rather referenced by an
// absolute path from the altpcietb_bfm_log.v include file. This allows all
// users of altpcietb_bfm_log.v to see a common set of values.
//-----------------------------------------------------------------------------
// Copyright (c) 2005 Altera Co... | 8.44882 |
module altpcietb_bfm_shmem_common (
dummy_out
);
`include "altpcietb_bfm_constants.v"
`include "altpcietb_bfm_log.v"
`include "altpcietb_bfm_shmem.v"
output dummy_out;
reg [7:0] shmem[0:SHMEM_SIZE-1];
// Protection Bit for the Shared Memory
// This bit protects critical data in Shared Memory from be... | 6.756527 |
module altpcietb_ltssm_mon (
rp_clk,
rstn,
rp_ltssm,
ep_ltssm,
dummy_out
);
`include "altpcietb_bfm_constants.v"
`include "altpcietb_bfm_log.v"
`include "altpcietb_bfm_shmem.v"
`include "altpcietb_bfm_rdwr.v"
input rp_clk;
input rstn;
input [4:0] rp_ltssm;
input [4:0] ep_ltssm;
o... | 6.629067 |
module contains the clock synchronization logic for a signal from clock
// domain 1 to clock domain 2.
// if the cg_common_clock_mode_i is active, signal1 will be passed through to
// signal 2 with a direct connection
module altpciexpav128_clksync ( cg_common_clock_mode_i,
Clk1_i,
... | 7.358377 |
module altpciexpav128_fifo #(
parameter FIFO_DEPTH = 3,
parameter DATA_WIDTH = 144
) (
// global signals
input clk,
input rstn,
input srst,
input wrreq,
input rdreq,
input ... | 8.703434 |
module altpciexpav128_p2a_addrtrans (
k_bar_i,
cb_p2a_avalon_addr_b0_i,
cb_p2a_avalon_addr_b1_i,
cb_p2a_avalon_addr_b2_i,
cb_p2a_avalon_addr_b3_i,
cb_p2a_avalon_addr_b4_i,
cb_p2a_avalon_addr_b5_i,
cb_p2a_avalon_addr_b6_i,
PCIeAddr_i,
BarHit_i,
AvlAddr_o
);
input [223:0] k_... | 8.703434 |
module contains the clock synchronization logic for a signal from clock
// domain 1 to clock domain 2.
// if the cg_common_clock_mode_i is active, signal1 will be passed through to
// signal 2 with a direct connection
module altpciexpav_clksync ( cg_common_clock_mode_i,
Clk1_i,
... | 7.358377 |
module altpciexpav_stif_p2a_addrtrans (
k_bar_i,
cb_p2a_avalon_addr_b0_i,
cb_p2a_avalon_addr_b1_i,
cb_p2a_avalon_addr_b2_i,
cb_p2a_avalon_addr_b3_i,
cb_p2a_avalon_addr_b4_i,
cb_p2a_avalon_addr_b5_i,
cb_p2a_avalon_addr_b6_i,
PCIeAddr_i,
BarHit_i,
AvlAddr_o
);
input [227:0] ... | 7.929651 |
module altpciexpav_stif_reg_fifo #(
parameter FIFO_DEPTH = 5,
parameter DATA_WIDTH = 304
) (
// global signals
input clk,
input rstn,
input srst,
input wrreq,
input rdreq,
in... | 7.929651 |
module altpcie_a10mlab #(
parameter WIDTH = 20,
parameter ADDR_WIDTH = 5,
parameter SIM_EMULATE = 1'b0 // this may not be exactly the same at the fine grain timing level
) (
input wclk,
input wena,
input [ADDR_WIDTH-1:0] waddr_reg,
input [WIDTH-1:0] wdata_reg,
input [ADDR_WIDTH-1:0] rad... | 7.233059 |
module altpcie_avl_stub ( /*AUTOARG*/
// Outputs
m_ChipSelect,
m_Read,
m_Write,
m_BurstCount,
m_ByteEnable,
m_Address,
m_WriteData,
s_WaitRequest,
s_ReadData,
s_ReadDataValid,
// Inputs
m_WaitRequest,
m_ReadData,
m_ReadDataValid,
s_Read,
s_Write,
... | 7.00397 |
modules used in PTC CV
module altpcie_hip_bitsync2
#(
parameter DWIDTH = 1, // Sync Data input
parameter RESET_VAL = 0 // Reset value
)
(
input wire clk, // clock
input wire rst_n, // async reset
input wire [DWIDTH-1:0] data_in, // data in
... | 7.161353 |
module altpcie_hip_bitsync #(
parameter DWIDTH = 1, // Sync Data input
parameter SYNCSTAGE = 2, // Sync stages
parameter RESET_VAL = 0 // Reset value
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire [DWIDTH-1:0] data_in, // data in... | 7.8011 |
module is to assist timing closure on TL_CFG bus
//-----------------------------------------------------------------------------
module altpcie_tl_cfg_pipe
(
input clk,
input srst,
output reg [ 3:0] o_tl_cfg_add,
output reg [31:0] o_tl_cfg_ctl,
output reg o_... | 6.759612 |
module altpcie_reset_delay_sync #(
parameter ACTIVE_RESET = 0,
parameter WIDTH_RST = 1,
parameter NODENAME = "altpcie_reset_delay_sync", // Expecting Instance name
parameter LOCK_TIME_CNT_WIDTH = 1
) (
input clk,
input async_rst,
output reg [WIDTH_RST-1:0] sync_r... | 7.866151 |
module altpcie_rs_a10_hip (
input pld_clk,
input dlup_exit,
input hotrst_exit,
input l2_exit,
input npor_core,
input [4:0] ltssm,
output reg hiprst
);
localparam [4:0] LTSSM_POL = 5'b00010;
localparam [4:0] LTSSM_CPL = 5'b00011;
localparam [4:0] LTSSM_DE... | 6.599681 |
module altpcie_sc_bitsync_node #(
parameter DWIDTH = 1, // Sync Data input
parameter NODENAME = "altpcie_sc_bitsync_node", // Instance name
parameter SYNCSTAGE = 2, // Sync stages
parameter SDC_TYPE = 0, // 0: Multi Cycle=3, 1:Multi Cycle=2, 2: Set False Path
parameter RESET_VAL = 0 // Reset va... | 6.984807 |
module dffp (
q,
clk,
ena,
d,
clrn,
prn
);
input d;
input clk;
input clrn;
input prn;
input ena;
output q;
tri1 prn, clrn, ena;
reg q;
always @(posedge clk or negedge clrn or negedge prn)
if (prn == 1'b0) q <= 1;
else if (clrn == 1'b0) q <= 0;
else begin
i... | 6.992594 |
module pll_iobuf (
i,
oe,
io,
o
);
input i;
input oe;
inout io;
output o;
reg o;
always @(io) begin
o = io;
end
assign io = (oe == 1) ? i : 1'bz;
endmodule
| 6.54618 |
module MF_pll_reg (
q,
clk,
ena,
d,
clrn,
prn
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q = 0;
always @(posedge clk ... | 6.578739 |
module arm_m_cntr (
clk,
reset,
cout,
initial_value,
modulus,
time_delay
);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tm... | 6.684371 |
module arm_scale_cntr (
clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap
);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// IN... | 6.900873 |
module ttn_m_cntr (
clk,
reset,
cout,
initial_value,
modulus,
time_delay
);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tm... | 6.735089 |
module ttn_n_cntr (
clk,
reset,
cout,
modulus
);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial begin
... | 6.545063 |
module ttn_scale_cntr (
clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap
);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// IN... | 6.82995 |
module cda_m_cntr (
clk,
reset,
cout,
initial_value,
modulus,
time_delay
);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tm... | 6.852977 |
module cda_n_cntr (
clk,
reset,
cout,
modulus
);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial begin
... | 6.89266 |
module cda_scale_cntr (
clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap
);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// IN... | 6.742481 |
module cycloneiiigl_post_divider (
clk,
reset,
cout
);
// PARAMETER
parameter dpa_divider = 1;
// INPUT PORTS
input clk;
input reset;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp... | 7.203778 |
module altpll_wb_clkgen #(
parameter DEVICE_FAMILY = "",
parameter INPUT_FREQUENCY = 50,
parameter WB_DIVIDE_BY = 1,
parameter WB_MULTIPLY_BY = 1,
parameter SDRAM_DIVIDE_BY = 1,
parameter SDRAM_MULTIPLY_BY = 1
) (
// Main clocks in, depending on board
input sys_clk_pad_i,
// Asynchro... | 7.787885 |
module of the DDL links
//* Author/Designer : Zhang.Fan (fanzhang.ccnu@gmail.com)
//*
//* Revision history:
//* 06-03-2013 : Add ALTRO command handshaking (acmd_ack)
//* 02-25-04-2013 : Add ALTRO command handshaking (acmd_ack)
//*******************************************************************************
//`tim... | 7.294035 |
module altr_hps_and (
input wire and_in1, // and input 1
input wire and_in2, // and input 2
output wire and_out // and output
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign and_out = and_in1 & and_in2;
`else
`endif
endmodule
| 7.049869 |
module altr_hps_bin2gray (
bin_in,
gray_out
);
input [2:0] bin_in;
output [2:0] gray_out;
reg [2:0] gray_out;
always @(*) begin // 3 bit gray code
case (bin_in)
3'b000: gray_out = 3'b000;
3'b001: gray_out = 3'b001;
3'b010: gray_out = 3'b011;
3'b011: gray_out = 3'b010;... | 6.592632 |
module altr_hps_bitsync #(
parameter DWIDTH = 1'b1, // Sync Data input
//parameter SYNCSTAGE = 2, // Sync stages
parameter RESET_VAL = 1'b0 // Reset value
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire [DWIDTH-1:0] data_in, // dat... | 10.098234 |
module altr_hps_bitsync4 #(
parameter DWIDTH = 1'b1, // Sync Data input
//parameter SYNCSTAGE = 4, // Sync stages
parameter RESET_VAL = 1'b0 // Reset value
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire [DWIDTH-1:0] data_in, // da... | 10.098234 |
module altr_hps_bitsync_generator #(
parameter DWIDTH = 1,
parameter [DWIDTH-1:0] RESET_VAL = 'd0
) (
input wire clk, //clock
input wire rst_n, //async reset
input wire [DWIDTH-1:0] data_in, //data in
output wire [DWIDTH-1:0] data_out //data out
);
genvar i;
generate
for (i = 0; i ... | 10.098234 |
module altr_hps_ckand (
input wire and_in1, // and input 1
input wire and_in2, // and input 2
output wire and_out // and output
);
// -------------------
// Port declarations
// -------------------
wire and_out_n;
// -----
// RTL
// -----
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign and... | 7.068816 |
module altr_hps_ckand_gate (
input wire and_clk, // and input 1
input wire and_en, // and input 2
output wire and_out // and output
);
// -------------------
// Port declarations
// -------------------
// -----
// RTL
// -----
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign and_out = and_clk... | 7.068816 |
module altr_hps_cknand (
input wire nand_in1, // and input 1
input wire nand_in2, // and input 2
output wire nand_out // and output
);
// -------------------
// Port declarations
// -------------------
// -----
// RTL
// -----
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign nand_out = ~(nand_... | 7.060948 |
module altr_hps_cknor (
input wire nor_in1, // or input 1
input wire nor_in2, // or input 2
output wire nor_out // or output
);
// -------------------
// Port declarations
// -------------------
// -----
// RTL
// -----
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign nor_out = ~(nor_in1 | nor... | 7.549032 |
module altr_hps_ckor (
input wire or_in1, // or input 1
input wire or_in2, // or input 2
output wire or_out // or output
);
// -------------------
// Port declarations
// -------------------
// -----
// RTL
// -----
wire or_out_n;
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign or_out = or... | 7.916579 |
module altr_hps_ckor_gate (
input wire or_clk, // or input 1
input wire or_en, // or input 2
output wire or_out // or output
);
// -------------------
// Port declarations
// -------------------
// -----
// RTL
// -----
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign or_out = or_clk | or_en;... | 7.916579 |
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