code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module altmemddr_mem_model_ram_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [127:0] q;
input [127:0] data;
input [23:0] rdaddress;
input rdclken;
input [23:0] wraddress;
input wrclock;
input wren;
//PETES CHANGE - make memory 32 bits to match instr.dat/data.dat
//reg [127: 0] mem_array [16777215: 0];
reg [ 31:0] mem_array [67108863 : 0];
wire [127:0] q;
reg [ 23:0] read_address;
//PETES CHANGE
initial begin
//This is TOO big for 256 MB RAM! We right shift data by 1
$readmemh("instr.dat", mem_array, 'h100_0000);
$readmemh("data.dat", mem_array, 'h400_0000 >> 1);
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(rdaddress) begin
read_address = rdaddress;
end
// Data read is asynchronous.
//PETES CHANGE - make memory 32 bits to match instr.dat/data.dat
//assign q = mem_array[read_address];
assign q = {
mem_array[{read_address, 2'd3}],
mem_array[{read_address, 2'd2}],
mem_array[{read_address, 2'd1}],
mem_array[{read_address, 2'd0}]
};
always @(posedge wrclock) begin
// Write data
if (wren)
//PETES CHANGE - make memory 32 bits to match instr.dat/data.dat
//mem_array[wraddress] <= data;
{mem_array[{
wraddress, 2'd3
}], mem_array[{
wraddress, 2'd2
}], mem_array[{
wraddress, 2'd1
}], mem_array[{
wraddress, 2'd0
}]} <= data;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// always @(rdaddress)
// begin
// read_address = rdaddress;
// end
//
//
// lpm_ram_dp lpm_ram_dp_component
// (
// .data (data),
// .q (q),
// .rdaddress (read_address),
// .rdclken (rdclken),
// .wraddress (wraddress),
// .wrclock (wrclock),
// .wren (wren)
// );
//
// defparam lpm_ram_dp_component.lpm_file = "UNUSED",
// lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
// lpm_ram_dp_component.lpm_indata = "REGISTERED",
// lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
// lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",
// lpm_ram_dp_component.lpm_width = 128,
// lpm_ram_dp_component.lpm_widthad = 24,
// lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
// lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 6.564346 |
module altmemddr_phy_alt_mem_phy_delay (
s_in,
s_out
);
//parameters
parameter WIDTH = 1;
parameter DELAY_PS = 10;
//ports
input wire [WIDTH - 1 : 0] s_in;
output wire [WIDTH - 1 : 0] s_out;
//model the transport delay
assign #(DELAY_PS) s_out = s_in;
endmodule
| 7.636203 |
module altmemddr_phy_alt_mem_phy_reset_pipe (
input wire clock,
input wire pre_clear,
output wire reset_out
);
parameter PIPE_DEPTH = 4;
// Declare pipeline registers.
reg [PIPE_DEPTH - 1 : 0] ams_pipe;
integer i;
// begin : RESET_PIPE
always @(posedge clock or negedge pre_clear) begin
if (pre_clear == 1'b0) begin
ams_pipe <= 0;
end else begin
for (i = 0; i < PIPE_DEPTH; i = i + 1) begin
if (i == 0) ams_pipe[i] <= 1'b1;
else ams_pipe[i] <= ams_pipe[i-1];
end
end // if-else
end // always
// end
assign reset_out = ams_pipe[PIPE_DEPTH-1];
endmodule
| 7.636203 |
module altor32_alu (
input_a,
input_b,
func,
result
);
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input [31:0] input_a /*verilator public*/;
input [31:0] input_b /*verilator public*/;
input [3:0] func /*verilator public*/;
output [31:0] result /*verilator public*/;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [31:0] result;
//-----------------------------------------------------------------
// ALU
//-----------------------------------------------------------------
always @(func or input_a or input_b) begin
case (func)
`ALU_SHIFTL: result = shift_left(input_a, input_b);
`ALU_SHIFTR: result = shift_right(input_a, input_b);
`ALU_SHIRTR_ARITH: result = shift_right_arith(input_a, input_b);
`ALU_ADD: result = (input_a + input_b);
`ALU_SUB: result = (input_a - input_b);
`ALU_AND: result = (input_a & input_b);
`ALU_OR: result = (input_a | input_b);
`ALU_XOR: result = (input_a ^ input_b);
default: result = 32'h00000000;
endcase
end
`include "altor32_funcs.v"
endmodule
| 8.984213 |
module altor32_lfu (
// Opcode
input [7:0] opcode_i /*verilator public*/,
// Memory load result
input [31:0] mem_result_i /*verilator public*/,
input [ 1:0] mem_offset_i /*verilator public*/,
// Result
output reg [31:0] load_result_o /*verilator public*/,
output reg load_insn_o /*verilator public*/
);
//-------------------------------------------------------------------
// Load forwarding unit
//-------------------------------------------------------------------
always @* begin
load_result_o = 32'h00000000;
load_insn_o = 1'b0;
case (opcode_i)
`INST_OR32_LBS: // l.lbs
begin
case (mem_offset_i)
2'b00: load_result_o[7:0] = mem_result_i[31:24];
2'b01: load_result_o[7:0] = mem_result_i[23:16];
2'b10: load_result_o[7:0] = mem_result_i[15:8];
2'b11: load_result_o[7:0] = mem_result_i[7:0];
default: ;
endcase
// Sign extend LB
if (load_result_o[7] == 1'b1) load_result_o[31:8] = 24'hFFFFFF;
load_insn_o = 1'b1;
end
`INST_OR32_LBZ: // l.lbz
begin
case (mem_offset_i)
2'b00: load_result_o[7:0] = mem_result_i[31:24];
2'b01: load_result_o[7:0] = mem_result_i[23:16];
2'b10: load_result_o[7:0] = mem_result_i[15:8];
2'b11: load_result_o[7:0] = mem_result_i[7:0];
default: ;
endcase
load_insn_o = 1'b1;
end
`INST_OR32_LHS: // l.lhs
begin
case (mem_offset_i)
2'b00: load_result_o[15:0] = mem_result_i[31:16];
2'b10: load_result_o[15:0] = mem_result_i[15:0];
default: ;
endcase
// Sign extend LH
if (load_result_o[15] == 1'b1) load_result_o[31:16] = 16'hFFFF;
load_insn_o = 1'b1;
end
`INST_OR32_LHZ: // l.lhz
begin
case (mem_offset_i)
2'b00: load_result_o[15:0] = mem_result_i[31:16];
2'b10: load_result_o[15:0] = mem_result_i[15:0];
default: ;
endcase
load_insn_o = 1'b1;
end
`INST_OR32_LWZ, `INST_OR32_LWS: // l.lwz l.lws
begin
load_result_o = mem_result_i;
load_insn_o = 1'b1;
end
default: ;
endcase
end
endmodule
| 7.227236 |
module altor32_lsu (
// Current instruction
input opcode_valid_i /*verilator public*/,
input [7:0] opcode_i /*verilator public*/,
// Load / Store pending
input load_pending_i /*verilator public*/,
input store_pending_i /*verilator public*/,
// Load dest register
input [4:0] rd_load_i /*verilator public*/,
// Load insn in WB stage
input load_wb_i /*verilator public*/,
// Memory status
input mem_access_i /*verilator public*/,
input mem_ack_i /*verilator public*/,
// Load / store still pending
output reg load_pending_o /*verilator public*/,
output reg store_pending_o /*verilator public*/,
// Insert load result into pipeline
output reg write_result_o /*verilator public*/,
// Stall pipeline due load / store / insert
output reg stall_o /*verilator public*/
);
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "altor32_defs.v"
`include "altor32_funcs.v"
//-------------------------------------------------------------------
// Outstanding memory access logic
//-------------------------------------------------------------------
reg inst_load_r;
reg inst_store_r;
always @* begin
load_pending_o = load_pending_i;
store_pending_o = store_pending_i;
stall_o = 1'b0;
write_result_o = 1'b0;
// Is this instruction a load or store?
inst_load_r = is_load_operation(opcode_i);
inst_store_r = is_store_operation(opcode_i);
// Store operation just completed?
if (store_pending_o & mem_ack_i & ~mem_access_i) begin
`ifdef CONF_CORE_DEBUG
$display(" Store operation now completed");
`endif
store_pending_o = 1'b0;
end
// Load just completed (and result ready in-time for writeback stage)?
if (load_pending_o & mem_ack_i & ~mem_access_i & load_wb_i) begin
// Load complete
load_pending_o = 1'b0;
`ifdef CONF_CORE_DEBUG
$display(" Load operation completed in writeback stage");
`endif
end // Load just completed (later than writeback stage)?
else if (load_pending_o & mem_ack_i & ~mem_access_i) begin
`ifdef CONF_CORE_DEBUG
$display(" Load operation completed later than writeback stage");
`endif
// Valid target register?
if (rd_load_i != 5'b00000) begin
`ifdef CONF_CORE_DEBUG
$display(" Load result now ready for R%d", rd_load_i);
`endif
// Stall instruction and write load result to pipeline
stall_o = opcode_valid_i;
write_result_o = 1'b1;
end else begin
`ifdef CONF_CORE_DEBUG
$display(" Load result ready but not needed");
`endif
end
// Load complete
load_pending_o = 1'b0;
end
// If load or store in progress (and this instruction is valid)
if ((load_pending_o | store_pending_o) & opcode_valid_i) begin
// Load or store whilst memory bus busy
if (inst_load_r | inst_store_r) begin
`ifdef CONF_CORE_DEBUG
$display(" Data bus already busy, stall (load_pending_o=%d, store_pending_o=%d)",
load_pending_o, store_pending_o);
`endif
// Stall!
stall_o = 1'b1;
end
end
end
endmodule
| 7.837467 |
module altor32_noicache (
input clk_i /*verilator public*/,
input rst_i /*verilator public*/,
// Processor interface
input rd_i /*verilator public*/,
input [31:0] pc_i /*verilator public*/,
output [31:0] instruction_o /*verilator public*/,
output valid_o /*verilator public*/,
// Invalidate (not used)
input invalidate_i /*verilator public*/,
// Memory interface
output [31:0] wbm_addr_o /*verilator public*/,
input [31:0] wbm_dat_i /*verilator public*/,
output [ 2:0] wbm_cti_o /*verilator public*/,
output wbm_cyc_o /*verilator public*/,
output wbm_stb_o /*verilator public*/,
input wbm_stall_i /*verilator public*/,
input wbm_ack_i /*verilator public*/
);
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
// Current state
parameter STATE_CHECK = 0;
parameter STATE_FETCH = 1;
reg state_q;
reg drop_resp_q;
wire mem_fetch_w = (state_q == STATE_CHECK);
wire mem_valid_w;
wire mem_final_w;
//-----------------------------------------------------------------
// Fetch unit
//-----------------------------------------------------------------
altor32_wb_fetch u_wb (
.clk_i(clk_i),
.rst_i(rst_i),
.fetch_i (mem_fetch_w),
.burst_i (1'b0),
.address_i(pc_i),
.resp_addr_o( /* not used */),
.data_o(instruction_o),
.valid_o(mem_valid_w),
.final_o(mem_final_w),
.wbm_addr_o (wbm_addr_o),
.wbm_dat_i (wbm_dat_i),
.wbm_cti_o (wbm_cti_o),
.wbm_cyc_o (wbm_cyc_o),
.wbm_stb_o (wbm_stb_o),
.wbm_stall_i(wbm_stall_i),
.wbm_ack_i (wbm_ack_i)
);
//-----------------------------------------------------------------
// Control logic
//-----------------------------------------------------------------
always @(posedge rst_i or posedge clk_i) begin
if (rst_i == 1'b1) begin
drop_resp_q <= 1'b0;
state_q <= STATE_CHECK;
end else begin
case (state_q)
//-----------------------------------------
// CHECK - Accept read request
//-----------------------------------------
STATE_CHECK: begin
drop_resp_q <= 1'b0;
state_q <= STATE_FETCH;
end
//-----------------------------------------
// FETCH - Wait for read response
//-----------------------------------------
STATE_FETCH: begin
// Read whilst waiting for previous response?
if (rd_i) drop_resp_q <= 1'b1;
// Data ready from memory?
if (mem_final_w) state_q <= STATE_CHECK;
end
default: ;
endcase
end
end
assign valid_o = mem_valid_w & ~drop_resp_q & ~rd_i;
assign instruction_o = wbm_dat_i;
endmodule
| 8.370186 |
module altor32_ram_dp #(
parameter WIDTH = 8,
parameter SIZE = 14
) (
input aclk_i /*verilator public*/,
output [(WIDTH - 1):0] adat_o /*verilator public*/,
input [(WIDTH - 1):0] adat_i /*verilator public*/,
input [ (SIZE - 1):0] aadr_i /*verilator public*/,
input awr_i /*verilator public*/,
input bclk_i /*verilator public*/,
output [(WIDTH - 1):0] bdat_o /*verilator public*/,
input [(WIDTH - 1):0] bdat_i /*verilator public*/,
input [ (SIZE - 1):0] badr_i /*verilator public*/,
input bwr_i /*verilator public*/
);
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
/* verilator lint_off MULTIDRIVEN */
reg [(WIDTH - 1):0] ram [((2<< (SIZE-1)) - 1):0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */
reg [ (SIZE - 1):0] rd_addr_a_q;
reg [ (SIZE - 1):0] rd_addr_b_q;
//-----------------------------------------------------------------
// Processes
//-----------------------------------------------------------------
always @(posedge aclk_i) begin
if (awr_i == 1'b1) ram[aadr_i] <= adat_i;
rd_addr_a_q <= aadr_i;
end
always @(posedge bclk_i) begin
if (bwr_i == 1'b1) ram[badr_i] <= bdat_i;
rd_addr_b_q <= badr_i;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
assign adat_o = ram[rd_addr_a_q];
assign bdat_o = ram[rd_addr_b_q];
//-----------------------------------------------------------------
// Init Memory
//-----------------------------------------------------------------
`ifdef ALTOR32_CLEAR_RAM
integer i;
initial begin
for (i = 0; i < ((2 << (SIZE - 1)) - 1); i = i + 1) begin
ram[i] = 0;
end
end
`endif
endmodule
| 8.212447 |
module altor32_ram_sp #(
parameter [31:0] WIDTH = 8,
parameter [31:0] SIZE = 14
) (
input clk_i /*verilator public*/,
output [(WIDTH - 1):0] dat_o /*verilator public*/,
input [(WIDTH - 1):0] dat_i /*verilator public*/,
input [ (SIZE - 1):0] adr_i /*verilator public*/,
input wr_i /*verilator public*/
);
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [(WIDTH - 1):0] ram [((2<< (SIZE-1)) - 1):0] /*verilator public*/;
reg [ (SIZE - 1):0] rd_addr_q;
//-----------------------------------------------------------------
// Processes
//-----------------------------------------------------------------
always @(posedge clk_i) begin
if (wr_i == 1'b1) ram[adr_i] <= dat_i;
rd_addr_q <= adr_i;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
assign dat_o = ram[rd_addr_q];
//-----------------------------------------------------------------
// Init Memory
//-----------------------------------------------------------------
`ifdef ALTOR32_CLEAR_RAM
integer i;
initial begin
for (i = 0; i < ((2 << (SIZE - 1)) - 1); i = i + 1) begin
ram[i] = 0;
end
end
`endif
endmodule
| 8.348214 |
module altor32_regfile_alt (
input clk_i /*verilator public*/,
input rst_i /*verilator public*/,
input wr_i /*verilator public*/,
input [ 4:0] ra_i /*verilator public*/,
input [ 4:0] rb_i /*verilator public*/,
input [ 4:0] rd_i /*verilator public*/,
output reg [31:0] reg_ra_o /*verilator public*/,
output reg [31:0] reg_rb_o /*verilator public*/,
input [31:0] reg_rd_i /*verilator public*/
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter SUPPORT_32REGS = "ENABLED";
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
wire clk_delayed_w;
wire [31:0] reg_ra_w;
wire [31:0] reg_rb_w;
wire write_enable_w;
reg [ 4:0] addr_q;
reg [31:0] data_q;
wire [31:0] ra_w;
wire [31:0] rb_w;
//-----------------------------------------------------------------
// Sync addr & data
//-----------------------------------------------------------------
always @(posedge clk_i or posedge rst_i) begin
if (rst_i) begin
addr_q <= 5'b00000;
data_q <= 32'h00000000;
end else begin
addr_q <= rd_i;
data_q <= reg_rd_i;
end
end
//-----------------------------------------------------------------
// Register File (using lpm_ram_dp)
// Unfortunatly, LPM_RAM_DP primitives have synchronous read ports.
// As this core requires asynchronous/non-registered read ports,
// we have to invert the readclock edge to get close to what we
// require.
// This will have negative timing implications!
//-----------------------------------------------------------------
lpm_ram_dp #(
.lpm_width(32),
.lpm_widthad(5),
.lpm_indata("REGISTERED"),
.lpm_outdata("UNREGISTERED"),
.lpm_rdaddress_control("REGISTERED"),
.lpm_wraddress_control("REGISTERED"),
.lpm_file("UNUSED"),
.lpm_type("lpm_ram_dp"),
.lpm_hint("UNUSED")
) lpm1 (
.rdclock(clk_delayed_w),
.rdclken(1'b1),
.rdaddress(ra_i),
.rden(1'b1),
.data(reg_rd_i),
.wraddress(rd_i),
.wren(write_enable_w),
.wrclock(clk_i),
.wrclken(1'b1),
.q(ra_w)
);
lpm_ram_dp #(
.lpm_width(32),
.lpm_widthad(5),
.lpm_indata("REGISTERED"),
.lpm_outdata("UNREGISTERED"),
.lpm_rdaddress_control("REGISTERED"),
.lpm_wraddress_control("REGISTERED"),
.lpm_file("UNUSED"),
.lpm_type("lpm_ram_dp"),
.lpm_hint("UNUSED")
) lpm2 (
.rdclock(clk_delayed_w),
.rdclken(1'b1),
.rdaddress(rb_i),
.rden(1'b1),
.data(reg_rd_i),
.wraddress(rd_i),
.wren(write_enable_w),
.wrclock(clk_i),
.wrclken(1'b1),
.q(rb_w)
);
//-----------------------------------------------------------------
// Combinatorial Assignments
//-----------------------------------------------------------------
// Delayed clock
assign clk_delayed_w = !clk_i;
// Register read ports
always @* begin
if (ra_i == 5'b00000) reg_ra_o = 32'h00000000;
else reg_ra_o = reg_ra_w;
if (rb_i == 5'b00000) reg_rb_o = 32'h00000000;
else reg_rb_o = reg_rb_w;
end
assign write_enable_w = (rd_i != 5'b00000) & wr_i;
// Reads are bypassed during write-back
assign reg_ra_w = (ra_i != addr_q) ? ra_w : data_q;
assign reg_rb_w = (rb_i != addr_q) ? rb_w : data_q;
endmodule
| 7.549143 |
module altor32_regfile_xil (
input clk_i /*verilator public*/,
input rst_i /*verilator public*/,
input wr_i /*verilator public*/,
input [ 4:0] ra_i /*verilator public*/,
input [ 4:0] rb_i /*verilator public*/,
input [ 4:0] rd_i /*verilator public*/,
output reg [31:0] reg_ra_o /*verilator public*/,
output reg [31:0] reg_rb_o /*verilator public*/,
input [31:0] reg_rd_i /*verilator public*/
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter SUPPORT_32REGS = "ENABLED";
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
wire [31:0] reg_ra_w;
wire [31:0] reg_rb_w;
wire [31:0] ra_0_15_w;
wire [31:0] ra_16_31_w;
wire [31:0] rb_0_15_w;
wire [31:0] rb_16_31_w;
wire write_enable_w;
wire write_banka_w;
wire write_bankb_w;
//-----------------------------------------------------------------
// Register File (using RAM16X1D )
//-----------------------------------------------------------------
// Registers 0 - 15
generate
begin
genvar i;
for (i = 0; i < 32; i = i + 1) begin : reg_loop1
RAM16X1D reg_bit1a (
.WCLK(clk_i),
.WE(write_banka_w),
.A0(rd_i[0]),
.A1(rd_i[1]),
.A2(rd_i[2]),
.A3(rd_i[3]),
.D(reg_rd_i[i]),
.DPRA0(ra_i[0]),
.DPRA1(ra_i[1]),
.DPRA2(ra_i[2]),
.DPRA3(ra_i[3]),
.DPO(ra_0_15_w[i]),
.SPO( /* open */)
);
RAM16X1D reg_bit2a (
.WCLK(clk_i),
.WE(write_banka_w),
.A0(rd_i[0]),
.A1(rd_i[1]),
.A2(rd_i[2]),
.A3(rd_i[3]),
.D(reg_rd_i[i]),
.DPRA0(rb_i[0]),
.DPRA1(rb_i[1]),
.DPRA2(rb_i[2]),
.DPRA3(rb_i[3]),
.DPO(rb_0_15_w[i]),
.SPO( /* open */)
);
end
end
endgenerate
// Registers 16 - 31
generate
if (SUPPORT_32REGS == "ENABLED") begin
genvar i;
for (i = 0; i < 32; i = i + 1) begin : reg_loop2
RAM16X1D reg_bit1b (
.WCLK(clk_i),
.WE(write_bankb_w),
.A0(rd_i[0]),
.A1(rd_i[1]),
.A2(rd_i[2]),
.A3(rd_i[3]),
.D(reg_rd_i[i]),
.DPRA0(ra_i[0]),
.DPRA1(ra_i[1]),
.DPRA2(ra_i[2]),
.DPRA3(ra_i[3]),
.DPO(ra_16_31_w[i]),
.SPO( /* open */)
);
RAM16X1D reg_bit2b (
.WCLK(clk_i),
.WE(write_bankb_w),
.A0(rd_i[0]),
.A1(rd_i[1]),
.A2(rd_i[2]),
.A3(rd_i[3]),
.D(reg_rd_i[i]),
.DPRA0(rb_i[0]),
.DPRA1(rb_i[1]),
.DPRA2(rb_i[2]),
.DPRA3(rb_i[3]),
.DPO(rb_16_31_w[i]),
.SPO( /* open */)
);
end
end else begin
assign ra_16_31_w = 32'h00000000;
assign rb_16_31_w = 32'h00000000;
end
endgenerate
//-----------------------------------------------------------------
// Combinatorial Assignments
//-----------------------------------------------------------------
assign reg_ra_w = (ra_i[4] == 1'b0) ? ra_0_15_w : ra_16_31_w;
assign reg_rb_w = (rb_i[4] == 1'b0) ? rb_0_15_w : rb_16_31_w;
assign write_enable_w = (rd_i != 5'b00000) & wr_i;
assign write_banka_w = (write_enable_w & (~rd_i[4]));
assign write_bankb_w = (write_enable_w & rd_i[4]);
// Register read ports
always @* begin
if (ra_i == 5'b00000) reg_ra_o = 32'h00000000;
else reg_ra_o = reg_ra_w;
if (rb_i == 5'b00000) reg_rb_o = 32'h00000000;
else reg_rb_o = reg_rb_w;
end
endmodule
| 7.549143 |
module altor32_writeback (
// General
input clk_i /*verilator public*/,
input rst_i /*verilator public*/,
// Opcode
input [31:0] opcode_i /*verilator public*/,
// Register target
input [4:0] rd_i /*verilator public*/,
// ALU result
input [31:0] alu_result_i /*verilator public*/,
// Memory load result
input [31:0] mem_result_i /*verilator public*/,
input [ 1:0] mem_offset_i /*verilator public*/,
input mem_ready_i /*verilator public*/,
// Multiplier result
input [63:0] mult_result_i /*verilator public*/,
// Outputs
output reg write_enable_o /*verilator public*/,
output reg [ 4:0] write_addr_o /*verilator public*/,
output reg [31:0] write_data_o /*verilator public*/
);
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
// Register address
reg [ 4:0] rd_q;
// Register writeback value
reg [31:0] result_q;
reg [ 7:0] opcode_q;
// Register writeback enable
reg write_rd_q;
reg [ 1:0] mem_offset_q;
//-------------------------------------------------------------------
// Pipeline Registers
//-------------------------------------------------------------------
always @(posedge clk_i or posedge rst_i) begin
if (rst_i == 1'b1) begin
write_rd_q <= 1'b1;
result_q <= 32'h00000000;
rd_q <= 5'b00000;
opcode_q <= 8'b0;
mem_offset_q <= 2'b0;
end else begin
rd_q <= rd_i;
result_q <= alu_result_i;
opcode_q <= {2'b00, opcode_i[31:26]};
mem_offset_q <= mem_offset_i;
// Register writeback required?
if (rd_i != 5'b00000) write_rd_q <= 1'b1;
else write_rd_q <= 1'b0;
end
end
//-------------------------------------------------------------------
// Load result resolve
//-------------------------------------------------------------------
wire load_inst_w;
wire [31:0] load_result_w;
altor32_lfu u_lfu (
// Opcode
.opcode_i(opcode_q),
// Memory load result
.mem_result_i(mem_result_i),
.mem_offset_i(mem_offset_q),
// Result
.load_result_o(load_result_w),
.load_insn_o (load_inst_w)
);
//-------------------------------------------------------------------
// Writeback
//-------------------------------------------------------------------
always @* begin
write_addr_o = rd_q;
// Load result
if (load_inst_w) begin
write_enable_o = write_rd_q & mem_ready_i;
write_data_o = load_result_w;
end // Normal ALU instruction
else begin
write_enable_o = write_rd_q;
write_data_o = result_q;
end
end
endmodule
| 8.02051 |
module construct of the Avalon Streaming receive port for the
// chaining DMA application MSI signals.
//-----------------------------------------------------------------------------
// Copyright (c) 2009 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
module altpcierd_cdma_ast_msi (
input clk_in,
input rstn,
input app_msi_req,
output reg app_msi_ack,
input[2:0] app_msi_tc,
input[4:0] app_msi_num,
input stream_ready,
output reg [7:0] stream_data,
output reg stream_valid);
reg stream_ready_del;
reg app_msi_req_r;
wire [7:0] m_data;
assign m_data[7:5] = app_msi_tc[2:0];
assign m_data[4:0] = app_msi_num[4:0];
//------------------------------------------------------------
// Input register boundary
//------------------------------------------------------------
always @(negedge rstn or posedge clk_in) begin
if (rstn == 1'b0)
stream_ready_del <= 1'b0;
else
stream_ready_del <= stream_ready;
end
//------------------------------------------------------------
// Arbitration between master and target for transmission
//------------------------------------------------------------
// tx_state SM states
always @(negedge rstn or posedge clk_in) begin
if (rstn == 1'b0) begin
app_msi_ack <= 1'b0;
stream_valid <= 1'b0;
stream_data <= 8'h0;
app_msi_req_r <= 1'b0;
end
else begin
app_msi_ack <= stream_ready_del & app_msi_req;
stream_valid <= stream_ready_del & app_msi_req & ~app_msi_req_r;
stream_data <= m_data;
app_msi_req_r <= stream_ready_del ? app_msi_req : app_msi_req_r;
end
end
endmodule
| 6.967781 |
module altpcierd_cdma_ecrc_gen_calc #(
parameter AVALON_ST_128 = 0
) (
clk,
rstn,
crc_data,
crc_valid,
crc_empty,
crc_eop,
crc_sop,
ecrc,
crc_ack
);
input clk;
input rstn;
input [127:0] crc_data;
input crc_valid;
input [3:0] crc_empty;
input crc_eop;
input crc_sop;
output [31:0] ecrc;
input crc_ack;
wire [31:0] crc_int;
wire crc_valid_int;
wire open_empty;
wire open_full;
generate
begin
if (AVALON_ST_128 == 1) begin
altpcierd_tx_ecrc_128 tx_ecrc_128 (
.clk(clk),
.reset_n(rstn),
.data(crc_data),
.datavalid(crc_valid),
.empty(crc_empty),
.endofpacket(crc_eop),
.startofpacket(crc_sop),
.checksum(crc_int),
.crcvalid(crc_valid_int)
);
end
end
endgenerate
generate
begin
if (AVALON_ST_128 == 0) begin
altpcierd_tx_ecrc_64 tx_ecrc_64 (
.clk(clk),
.reset_n(rstn),
.data(crc_data[127:64]),
.datavalid(crc_valid),
.empty(crc_empty[2:0]),
.endofpacket(crc_eop),
.startofpacket(crc_sop),
.checksum(crc_int),
.crcvalid(crc_valid_int)
);
end
end
endgenerate
altpcierd_tx_ecrc_fifo tx_ecrc_fifo (
.aclr (~rstn),
.clock(clk),
.data (crc_int),
.rdreq(crc_ack),
.wrreq(crc_valid_int),
.empty(open_empty),
.full (open_full),
.q (ecrc)
);
endmodule
| 6.83792 |
module altpcierd_cdma_ecrc_gen_datapath (
clk,
rstn,
data_in,
data_valid,
rdreq,
data_out,
data_out_valid,
full
);
input clk;
input rstn;
input [135:0] data_in;
input data_valid;
input rdreq;
output [135:0] data_out;
output data_out_valid;
output full;
wire empty;
reg [6:0] ctl_shift_reg;
wire rdreq_int;
wire open_data_fifo_empty;
wire open_data_fifo_almost_full;
wire open_data_fifo_full;
wire open_ctl_fifo_full;
wire open_ctl_fifo_data;
wire data_bit;
assign data_bit = 1'b1;
// lookahead
altpcierd_tx_ecrc_data_fifo tx_ecrc_data_fifo (
.aclr (~rstn),
.clock (clk),
.data (data_in),
.rdreq (rdreq_int),
.wrreq (data_valid),
.almost_full(open_data_fifo_almost_full),
.empty (open_data_fifo_empty),
.full (open_data_fifo_full),
.q (data_out)
);
// push data_valid thru a shift register to
// wait a minimum time before allowing data fifo
// to be popped. when shifted data_valid is put
// into the control fifo, it is okay to pop data
// fifo whenever avalon ST is ready
always @(posedge clk or negedge rstn) begin
if (rstn == 1'b0) begin
ctl_shift_reg <= 7'h0;
end else begin
ctl_shift_reg <= {
data_valid, ctl_shift_reg[6:1]
}; // always shifting. no throttling because crc module is not throttled.
end
end
assign rdreq_int = (rdreq == 1'b1) & (empty == 1'b0);
assign data_out_valid = (rdreq == 1'b1) & (empty == 1'b0);
// this fifo only serves as an up/down counter for number of
// tx_data_fifo entries which have met the minimum
// required delay time before being popped
// lookahead
altpcierd_tx_ecrc_ctl_fifo tx_ecrc_ctl_fifo (
.aclr (~rstn),
.clock (clk),
.data (data_bit), // data does not matter
.rdreq (rdreq_int),
.wrreq (ctl_shift_reg[0]),
.almost_full(full),
.empty (empty),
.full (open_ctl_fifo_full),
.q (open_ctl_fifo_data)
);
endmodule
| 6.83792 |
module altpcierd_compliance_test (
input local_rstn, // Local board reset
input pcie_rstn, // PCIe reset
input refclk, // 100 Mhz clock
input req_compliance_push_button_n,// Push button to cycle through compliance mode, gen1, gen2 - Active low
input req_compliance_soft_ctrl , // Register to cycle trough compliance mode (monitor rising edge on this register - Active on 0 to 1 transition
input set_compliance_mode, // Set compliance mode (test_in[32])
output test_in_5_hip,
output test_in_32_hip
);
wire rstn; // async rstn synchronized on refclk
wire exit_ltssm_compliance; // when 1 : force exit LTSSM COMPLIANCE state
// When 0 : if board plugged on compliance based board, LTSSM returns to COMPLIANCE state
wire new_edge_for_compliance;
reg [ 2:0] ltssm_cnt_cycles;
reg [15:0] dbc_cnt;
assign test_in_5_hip = (set_compliance_mode == 1'b0) ? 1'b1 : exit_ltssm_compliance;
assign test_in_32_hip = set_compliance_mode;
//
// LTSSM Compliance forcing in/out
//
assign exit_ltssm_compliance = ltssm_cnt_cycles[2];
always @(posedge refclk or negedge rstn) begin
if (rstn == 1'b0) begin
ltssm_cnt_cycles <= 3'b000;
end else begin
if (new_edge_for_compliance == 1'b1) begin
ltssm_cnt_cycles <= 3'b111;
end else if (ltssm_cnt_cycles != 3'b000) begin
ltssm_cnt_cycles <= ltssm_cnt_cycles - 3'b001;
end
end
end
reg req_compliance_cycle, req_compliance_cycle_r, req_compliance_soft_ctrl_r;
always @(posedge refclk or negedge rstn) begin
if (rstn == 1'b0) begin
req_compliance_cycle <= 1'b1;
req_compliance_cycle_r <= 1'b1;
req_compliance_soft_ctrl_r <= 1'b1;
end else begin
req_compliance_cycle <= (dbc_cnt == 16'h0000) ? 1'b0 : 1'b1;
req_compliance_cycle_r <= req_compliance_cycle;
req_compliance_soft_ctrl_r <= req_compliance_soft_ctrl;
end
end
assign new_edge_for_compliance = (((req_compliance_cycle_r == 1'b1)&(req_compliance_cycle == 1'b0))||
((req_compliance_soft_ctrl_r == 1'b0)&(req_compliance_soft_ctrl == 1'b1))) ?1'b1:1'b0;
//De bouncer for push button
always @(posedge refclk or negedge rstn) begin
if (rstn == 1'b0) begin
dbc_cnt <= 16'hFFFF;
end else begin
if (req_compliance_push_button_n == 0) begin
dbc_cnt <= 16'hFFFF;
end else if (dbc_cnt != 16'h0000) begin
dbc_cnt <= dbc_cnt - 16'h1;
end
end
end
// Sync async reset
wire npor;
reg [2:0] rstn_sync;
assign npor = pcie_rstn & local_rstn;
always @(posedge refclk or negedge npor) begin
if (npor == 1'b0) begin
rstn_sync[2:0] <= 3'b000;
end else begin
rstn_sync[0] <= 1'b1;
rstn_sync[1] <= rstn_sync[0];
rstn_sync[2] <= rstn_sync[1];
end
end
assign rstn = rstn_sync[2];
endmodule
| 7.948987 |
module altpcierd_icm_fifo #(
parameter RAMTYPE = "RAM_BLOCK_TYPE=M512",
parameter USEEAB = "ON"
) (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
almost_full,
empty,
full,
q
);
input aclr;
input clock;
input [107:0] data;
input rdreq;
input wrreq;
output almost_empty;
output almost_full;
output empty;
output full;
output [107:0] q;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [107:0] sub_wire3;
wire sub_wire4;
wire almost_full = sub_wire0;
wire empty = sub_wire1;
wire almost_empty = sub_wire2;
wire [107:0] q = sub_wire3[107:0];
wire full = sub_wire4;
scfifo #(
.add_ram_output_register("ON"),
.almost_empty_value (5),
.almost_full_value (10),
.intended_device_family ("Stratix II GX"),
.lpm_hint (RAMTYPE),
.lpm_numwords (16),
.lpm_showahead ("OFF"),
.lpm_type ("scfifo"),
.lpm_width (108),
.lpm_widthu (4),
.overflow_checking ("OFF"),
.underflow_checking ("OFF"),
.use_eab (USEEAB)
) scfifo_component (
.rdreq(rdreq),
.aclr(aclr),
.clock(clock),
.wrreq(wrreq),
.data(data),
.almost_full(sub_wire0),
.empty(sub_wire1),
.almost_empty(sub_wire2),
.q(sub_wire3),
.full(sub_wire4)
// synopsys translate_off
, .sclr(),
.usedw()
// synopsys translate_on
);
endmodule
| 7.142683 |
module altpcierd_icm_fifo_lkahd #(
parameter RAMTYPE = "RAM_BLOCK_TYPE=M512",
parameter USEEAB = "ON",
parameter ALMOST_FULL = 10,
parameter NUMWORDS = 16,
parameter WIDTHU = 4
) (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
almost_full,
empty,
full,
q,
usedw
);
input aclr;
input clock;
input [107:0] data;
input rdreq;
input wrreq;
output almost_empty;
output almost_full;
output empty;
output full;
output [107:0] q;
output [WIDTHU-1:0] usedw;
wire sub_wire0;
wire [WIDTHU-1:0] sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire [107:0] sub_wire4;
wire sub_wire5;
wire almost_full = sub_wire0;
wire [WIDTHU-1:0] usedw = sub_wire1[WIDTHU-1:0];
wire empty = sub_wire2;
wire almost_empty = sub_wire3;
wire [107:0] q = sub_wire4[107:0];
wire full = sub_wire5;
scfifo #(
.add_ram_output_register("ON"),
.almost_empty_value (3),
.almost_full_value (ALMOST_FULL),
.intended_device_family ("Stratix II GX"),
.lpm_hint (RAMTYPE),
.lpm_numwords (NUMWORDS),
.lpm_showahead ("ON"),
.lpm_type ("scfifo"),
.lpm_width (108),
.lpm_widthu (WIDTHU),
.overflow_checking ("OFF"),
.underflow_checking ("OFF"),
.use_eab (USEEAB)
) scfifo_component (
.rdreq(rdreq),
.aclr(aclr),
.clock(clock),
.wrreq(wrreq),
.data(data),
.almost_full(sub_wire0),
.usedw(sub_wire1),
.empty(sub_wire2),
.almost_empty(sub_wire3),
.q(sub_wire4),
.full(sub_wire5)
// synopsys translate_off
, .sclr()
// synopsys translate_on
);
endmodule
| 7.142683 |
module altpcierd_icm_msibridge (
clk,
rstn,
data_valid,
data_in,
data_ack,
msi_ack,
msi_req,
msi_num,
msi_tc
);
input clk;
input rstn;
input data_valid;
input [107:0] data_in;
input msi_ack;
output data_ack;
output msi_req;
output [4:0] msi_num;
output [2:0] msi_tc;
reg msi_req;
reg [4:0] msi_num;
reg [2:0] msi_tc;
reg msi_req_r;
wire throttle_data;
//--------------------------------
// legacy output signals
//--------------------------------
//--------------------------------
// avalon ready
//--------------------------------
assign data_ack = ~(~msi_ack & (msi_req | (data_valid & data_in[`STREAM_MSI_VALID])));
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
msi_num <= 5'h0;
msi_tc <= 3'h0;
msi_req <= 1'b0;
end else begin
msi_num <= (data_in[`STREAM_MSI_VALID]) ? data_in[`STREAM_APP_MSI_NUM] : msi_num;
msi_tc <= (data_in[`STREAM_MSI_VALID]) ? data_in[`STREAM_MSI_TC] : msi_tc;
msi_req <= msi_ack ? 1'b0 : (data_valid & data_in[`STREAM_MSI_VALID]) ? 1'b1 : msi_req;
end
end
/*
wire msi_req;
wire [4:0] msi_num;
wire [2:0] msi_tc;
reg msi_req_r;
wire throttle_data;
reg [4:0] msi_num_r;
reg [2:0] msi_tc_r;
reg msi_ack_r;
//--------------------------------
// legacy output signals
//--------------------------------
assign msi_req = msi_ack_r ? 1'b0 : (data_valid & data_in[`STREAM_MSI_VALID]) ? 1'b1 : msi_req_r;
assign msi_tc = (data_in[`STREAM_MSI_VALID]) ? data_in[`STREAM_MSI_TC] : msi_tc_r;
assign msi_num = (data_in[`STREAM_MSI_VALID]) ? data_in[`STREAM_APP_MSI_NUM] : msi_num_r;
//--------------------------------
// avalon ready
//--------------------------------
assign data_ack = ~msi_req;
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
msi_num_r <= 5'h0;
msi_tc_r <= 3'h0;
msi_req_r <= 1'b0;
msi_ack_r <= 1'b0;
end
else begin
msi_num_r <= msi_num;
msi_tc_r <= msi_tc;
msi_req_r <= msi_req;
msi_ack_r <= msi_ack;
end
end
*/
endmodule
| 7.142683 |
module altpcierd_icm_sideband (
clk,
rstn,
cfg_busdev,
cfg_devcsr,
cfg_linkcsr,
cfg_msicsr,
cfg_prmcsr,
cfg_tcvcmap,
app_int_sts,
app_int_sts_ack,
pex_msi_num,
cpl_err,
cpl_pending,
cfg_busdev_del,
cfg_devcsr_del,
cfg_linkcsr_del,
cfg_msicsr_del,
cfg_prmcsr_del,
cfg_tcvcmap_del,
app_int_sts_del,
app_int_sts_ack_del,
pex_msi_num_del,
cpl_err_del,
cpl_pending_del
);
input clk;
input rstn;
input [12:0] cfg_busdev; // From core to app
input [31:0] cfg_devcsr; // From core to app
input [31:0] cfg_linkcsr; // From core to app
input [31:0] cfg_prmcsr; // From core to app
input [23:0] cfg_tcvcmap; // From core to app
input [15:0] cfg_msicsr; // From core to app
input [4:0] pex_msi_num; // From app to core
input app_int_sts; // From app to core
input app_int_sts_ack; // From core to app
input [2:0] cpl_err;
input cpl_pending;
output [12:0] cfg_busdev_del;
output [31:0] cfg_devcsr_del;
output [31:0] cfg_linkcsr_del;
output [31:0] cfg_prmcsr_del;
output [23:0] cfg_tcvcmap_del;
output [15:0] cfg_msicsr_del;
output app_int_sts_del;
output app_int_sts_ack_del; // To app
output [4:0] pex_msi_num_del;
output [2:0] cpl_err_del;
output cpl_pending_del;
reg [12:0] cfg_busdev_del;
reg [31:0] cfg_devcsr_del;
reg [31:0] cfg_linkcsr_del;
reg [31:0] cfg_prmcsr_del;
reg [23:0] cfg_tcvcmap_del;
reg app_int_sts_del;
reg app_int_sts_ack_del;
reg [ 4:0] pex_msi_num_del;
reg [ 2:0] cpl_err_del;
reg [15:0] cfg_msicsr_del;
reg cpl_pending_del;
//---------------------------------------------
// Incremental Compile Boundary registers
//---------------------------------------------
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
cfg_busdev_del <= 13'h0;
cfg_devcsr_del <= 32'h0;
cfg_linkcsr_del <= 32'h0;
cfg_prmcsr_del <= 32'h0;
cfg_tcvcmap_del <= 24'h0;
cfg_msicsr_del <= 16'h0;
app_int_sts_del <= 1'b0;
app_int_sts_ack_del <= 1'b0;
pex_msi_num_del <= 5'h0;
cpl_err_del <= 3'h0;
cpl_pending_del <= 1'b0;
end else begin
cfg_busdev_del <= cfg_busdev;
cfg_devcsr_del <= cfg_devcsr;
cfg_linkcsr_del <= cfg_linkcsr;
cfg_prmcsr_del <= cfg_prmcsr;
cfg_tcvcmap_del <= cfg_tcvcmap;
cfg_msicsr_del <= cfg_msicsr;
app_int_sts_del <= app_int_sts; // From app to core. NO COMBINATIONAL allowed on input
app_int_sts_ack_del <= app_int_sts_ack;
pex_msi_num_del <= pex_msi_num; // From app to core. NO COMBINATIONAL allowed on input
cpl_err_del <= cpl_err; // From app to core. NO COMBINATIONAL allowed on input
cpl_pending_del <= cpl_pending; // From app to core. NO COMBINATIONAL allowed on input
end
end
endmodule
| 7.142683 |
module stratixiv_pciehip_dprio_bit (
reset,
clk,
sig_in,
ext_in,
serial_mode,
si,
shift,
mdio_dis,
sig_out,
so
);
input reset; // reset
input clk; // clock
input sig_in; // signal input
input ext_in; // external input port
input serial_mode; // serial shift mode enable
input si; // scan input
input shift; // 1'b1=shift in data from si into scan flop
// 1'b0=load data from sig_in into scan flop
input mdio_dis; // 1'b1=choose ext_in to the sig_out mux
// 1'b0=choose so to the sign_out mux
output sig_out; // signal output
output so; // scan output
wire sig_out;
wire cram_int;
wire set_int;
reg so;
// select signal output
assign sig_out = (serial_mode) ? (so & ~shift) : (cram_int);
assign cram_int = (mdio_dis) ? (ext_in) : (so);
// Set signal for the flop
assign set_int = (shift | reset) ? 1'b0 : ext_in;
// scan flop
always @(posedge reset or posedge set_int or posedge clk)
if (reset) so <= 1'b0;
else if (set_int) so <= 1'b1;
else if (shift && serial_mode) so <= si;
else so <= sig_in;
endmodule
| 6.746782 |
module stratixiv_pciehip_compute_bit (
input wire [63:0] datain,
input wire s,
output wire r
);
// begin
assign r = datain[0] ^ datain[1] ^ datain[2] ^ datain[3] ^ datain[4] ^ datain[5] ^ datain[6] ^ datain[7] ^ datain[10] ^ datain[13] ^ datain[14] ^ datain[17] ^
datain[20] ^ datain[23] ^ datain[24] ^ datain[27] ^ datain[35] ^ datain[43] ^ datain[46] ^ datain[47] ^ datain[51] ^ datain[52] ^ datain[53] ^
datain[56] ^ datain[57] ^ datain[58] ^ s;
// end
endmodule
| 6.746782 |
module stratixiv_pciehip_ecc_gen (
input wire [63:0] datain, // Data on which ECC is required
input wire [ 7:0] syndrome, // Syndrome uses 8'h00 while generating
output wire [ 7:0] result // Result
);
//-----------------------------------------------------------------------------
// Instantiate Result Compute block for 8 bits
//-----------------------------------------------------------------------------
stratixiv_pciehip_compute_bit cb_0 (
.datain(datain),
.s (syndrome[0]),
.r (result[0])
);
stratixiv_pciehip_compute_bit cb_1 (
.datain({datain[7:0], datain[63:8]}),
.s(syndrome[1]),
.r(result[1])
);
stratixiv_pciehip_compute_bit cb_2 (
.datain({datain[15:0], datain[63:16]}),
.s(syndrome[2]),
.r(result[2])
);
stratixiv_pciehip_compute_bit cb_3 (
.datain({datain[23:0], datain[63:24]}),
.s(syndrome[3]),
.r(result[3])
);
stratixiv_pciehip_compute_bit cb_4 (
.datain({datain[31:0], datain[63:32]}),
.s(syndrome[4]),
.r(result[4])
);
stratixiv_pciehip_compute_bit cb_5 (
.datain({datain[39:0], datain[63:40]}),
.s(syndrome[5]),
.r(result[5])
);
stratixiv_pciehip_compute_bit cb_6 (
.datain({datain[47:0], datain[63:48]}),
.s(syndrome[6]),
.r(result[6])
);
stratixiv_pciehip_compute_bit cb_7 (
.datain({datain[55:0], datain[63:56]}),
.s(syndrome[7]),
.r(result[7])
);
endmodule
| 6.746782 |
module stratixiv_pciehip_ecc_decoder (
flag,
derr,
derr_cor
);
input [2:0] flag;
output derr;
output derr_cor;
assign derr = flag[2] & ~(flag[1]) & flag[0];
assign derr_cor = ~(flag[2]) & flag[1] & flag[0];
endmodule
| 6.746782 |
module stratixiv_pciehip_pulse_ext (
core_clk,
rstn,
srst,
derr_cor,
derr_cor_ext
);
input core_clk;
input rstn;
input srst;
input derr_cor;
output derr_cor_ext;
reg n1, derr_cor_ext;
wire n2;
// Pulse width extender
always @(negedge rstn or posedge core_clk) begin
if (rstn == 1'b0) begin
n1 <= 1'b0;
end else begin
if (srst == 1'b1) begin
n1 <= 1'b0;
end else begin
n1 <= derr_cor;
end
end
end
assign n2 = n1 | derr_cor;
always @(negedge rstn or posedge core_clk) begin
if (rstn == 1'b0) begin
derr_cor_ext <= 1'b0;
end else begin
if (srst == 1'b1) begin
derr_cor_ext <= 1'b0;
end else begin
derr_cor_ext <= n2;
end
end
end
endmodule
| 6.746782 |
module stratixiv_pciehip_pciexp_dcfiforam (
data,
wren,
wraddress,
rdaddress,
wrclock,
rdclock,
q
);
parameter addr_width = 4;
parameter data_width = 32;
input [data_width - 1:0] data;
input wren;
input [addr_width - 1:0] wraddress;
input [addr_width - 1:0] rdaddress;
input wrclock;
input rdclock;
output [data_width - 1:0] q;
wire [data_width - 1:0] q;
reg [data_width - 1:0] ram_block[0:2 ** addr_width - 1];
reg [addr_width - 1:0] rdaddr_r;
reg [addr_width - 1:0] wraddr_r;
reg wren_r;
reg [data_width - 1:0] wrdata_r;
// Write process
always @(posedge wrclock) begin
wren_r <= wren;
wraddr_r <= wraddress;
wrdata_r <= data;
if (wren_r == 1'b1) begin
ram_block[wraddr_r] <= wrdata_r;
end
end
// Read process
always @(posedge rdclock) begin
rdaddr_r <= rdaddress;
end
assign q = ram_block[rdaddr_r];
endmodule
| 6.746782 |
module stratixiv_pciehip_pciexp_dcram_rtry (
wrclock,
wren,
wraddress,
data,
rdclock,
rdaddress,
q
);
parameter addr_width = 'd4;
parameter data_width = 'd32;
input wrclock;
input wren;
input [data_width - 1:0] data;
input [addr_width - 1:0] wraddress;
input rdclock;
input [addr_width - 1:0] rdaddress;
output [data_width - 1:0] q;
wire [data_width - 1:0] q;
// -------------------------------------------------------------
reg [data_width - 1:0] ram_block [(1<<addr_width)-1:0];
reg [addr_width - 1:0] read_addr_r;
reg [addr_width - 1:0] wraddr_r;
reg wren_r;
reg [data_width - 1:0] wrdata_r;
// Write process
always @(posedge wrclock) begin : process_1
wren_r <= wren;
wraddr_r <= wraddress;
wrdata_r <= data;
if (wren_r == 1'b1) begin
ram_block[wraddr_r] <= wrdata_r;
end
end
// Read process
always @(posedge rdclock) begin : process_3
read_addr_r <= rdaddress;
end
assign q = ram_block[read_addr_r];
endmodule
| 6.746782 |
module stratixiv_pciehip_pciexp_dcram_rxvc (
wrclock,
wren,
wraddress,
data,
rdclock,
rdaddress,
q
);
parameter addr_width = 'd4;
parameter data_width = 'd32;
input wrclock;
input wren;
input [data_width - 1:0] data;
input [addr_width - 1:0] wraddress;
input rdclock;
input [addr_width - 1:0] rdaddress;
output [data_width - 1:0] q;
wire [data_width - 1:0] q;
// -------------------------------------------------------------
reg [data_width - 1:0] ram_block [(1<<addr_width)-1:0];
reg [addr_width - 1:0] read_addr_r;
reg [addr_width - 1:0] wraddr_r;
reg wren_r;
reg [data_width - 1:0] wrdata_r;
// Write process
always @(posedge wrclock) begin : process_1
wren_r <= wren;
wraddr_r <= wraddress;
wrdata_r <= data;
if (wren_r == 1'b1) begin
ram_block[wraddr_r] <= wrdata_r;
end
end
// Read process
always @(posedge rdclock) begin : process_3
read_addr_r <= rdaddress;
end
assign q = ram_block[read_addr_r];
endmodule
| 6.746782 |
module cycloneiv_hssi_tx_pma_sub_reg (
input wire clk,
input tri1 ena,
input wire d,
input tri1 clrn,
input tri1 prn,
output wire q
);
// BUFFER INPUTS
// INTERNAL VARIABLES
reg q_tmp;
wire q_wire;
// TIMING PATHS
specify
$setuphold(posedge clk, d, 0, 0);
(posedge clk => (q +: q_tmp)) = (0, 0);
(negedge clrn => (q +: q_tmp)) = (0, 0);
(negedge prn => (q +: q_tmp)) = (0, 0);
endspecify
initial q_tmp = 0;
always @(posedge clk or negedge clrn or negedge prn) begin
if (prn == 1'b0) q_tmp <= 1;
else if (clrn == 1'b0) q_tmp <= 0;
else if ((clk == 1) & (ena == 1'b1)) q_tmp <= d;
end
assign q_wire = q_tmp;
and (q, q_wire, 1'b1);
endmodule
| 8.011405 |
module cycloneiv_hssi_tx_pma_sub_out_block #(
parameter bypass_serializer = "false",
parameter invert_clock = "false",
parameter use_falling_clock_edge = "false"
) (
input wire clk,
input wire datain,
input wire devclrn,
input wire devpor,
output wire dataout
);
// INTERNAL VARIABLES AND NETS
reg dataout_tmp;
reg clk_last_value;
reg bypass_mode;
reg invert_mode;
reg falling_clk_out;
// BUFFER INPUTS
// TEST PARAMETER VALUES
initial begin
falling_clk_out = (use_falling_clock_edge == "true") ? 1'b1 : 1'b0;
bypass_mode = (bypass_serializer == "true") ? 1'b1 : 1'b0;
invert_mode = (invert_clock == "true") ? 1'b1 : 1'b0;
end
// TIMING PATHS
specify
if (bypass_mode == 1'b1) (clk => dataout) = (0, 0);
if (bypass_mode == 1'b0 && falling_clk_out == 1'b1)
(negedge clk => (dataout +: dataout_tmp)) = (0, 0);
if (bypass_mode == 1'b0 && falling_clk_out == 1'b0)
(datain => (dataout +: dataout_tmp)) = (0, 0);
endspecify
initial begin
clk_last_value = 0;
dataout_tmp = 0;
end
always @(clk or datain or devclrn or devpor) begin
if ((devpor === 1'b0) || (devclrn === 1'b0)) begin
dataout_tmp <= 0;
end else begin
if (bypass_serializer == "false") begin
if (use_falling_clock_edge == "false") dataout_tmp <= datain;
if ((clk === 1'b0) && (clk_last_value !== clk)) begin
if (use_falling_clock_edge == "true") dataout_tmp <= datain;
end
end // bypass is off
else
begin
// generate clk_out
if (invert_clock == "false") dataout_tmp <= clk;
else dataout_tmp <= !clk;
end // clk output
end
clk_last_value <= clk;
end // always
and (dataout, dataout_tmp, 1'b1);
endmodule
| 8.011405 |
module cycloneiv_hssi_tx_pma_sub_parallel_register #(
parameter channel_width = 4
) (
input wire clk,
input wire enable,
input wire [channel_width - 1:0] datain,
input wire devclrn,
input wire devpor,
output wire [channel_width - 1:0] dataout
);
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [channel_width - 1:0] dataout_tmp;
// TIMING PATHS
specify
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
$setuphold(posedge clk, datain, 0, 0);
endspecify
initial begin
clk_last_value = 0;
dataout_tmp = 'b0;
end
always @(clk or enable or devpor or devclrn) begin
if ((devpor === 1'b0) || (devclrn === 1'b0)) begin
dataout_tmp <= 'b0;
end else begin
if ((clk === 1'b1) && (clk_last_value !== clk)) begin
if (enable === 1'b1) begin
dataout_tmp <= datain;
end
end
end
clk_last_value <= clk;
end // always
assign dataout = dataout_tmp;
endmodule
| 8.011405 |
module cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2 (
input wire clk,
input wire reset_n,
output reg clkout
);
wire next_val;
// SPR:328849 - initialize clkout because reset_n is optional
initial clkout = 1'b0;
// state definition
always @(posedge clk or negedge reset_n) begin
if (!reset_n) clkout <= 1'b0;
else clkout <= next_val;
end
assign next_val = ~clkout;
endmodule
| 8.011405 |
module cycloneiv_hssi_tx_pma_sub_tx_rx_det_clk_gen (
input wire clk,
input wire reset_n,
output wire clkout
);
wire clk8m, clk4m, clk2m;
cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2 div_1 (
.clk(clk),
.reset_n(reset_n),
.clkout(clk8m)
);
cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2 div_2 (
.clk(clk8m),
.reset_n(reset_n),
.clkout(clk4m)
);
cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2 div_3 (
.clk(clk4m),
.reset_n(reset_n),
.clkout(clk2m)
);
cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2 div_4 (
.clk(clk2m),
.reset_n(reset_n),
.clkout(clkout)
);
endmodule
| 8.011405 |
module cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_sync (
input wire clk,
input wire reset_n,
input wire rcv_det,
output reg rcv_det_out
); // synthesis syn_black_box
reg rcv_det_mid;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
rcv_det_out <= 1'b0;
rcv_det_mid <= 1'b0;
end else begin
rcv_det_out <= rcv_det_mid;
rcv_det_mid <= rcv_det;
end
end
endmodule
| 8.011405 |
module cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_fsm (
input wire clk,
input wire reset_n,
input wire com_pass,
input wire probe_pass,
output reg det_on,
output reg detect_valid,
output reg rcv_found
); // synthesis syn_black_box
reg [2:0] STATE;
reg [2:0] NEXTSTATE;
reg next_rcv_found;
reg fake_rcv_present;
// state definition
parameter RESET = 3'b000;
parameter WAKE = 3'b001;
parameter STATE_1 = 3'b011;
parameter STATE_2 = 3'b101;
parameter HOLD = 3'b100;
initial begin
fake_rcv_present = 1'b1;
NEXTSTATE = 3'b001;
end
// State logic and FSM
always @(posedge clk or negedge reset_n) begin
if (!reset_n) STATE <= RESET;
else STATE <= NEXTSTATE;
end
always @(STATE or com_pass) begin
case (STATE)
RESET: NEXTSTATE = WAKE; // after reset; then next state is wake
WAKE: begin
if (com_pass)
NEXTSTATE = STATE_1; // if com_pass is true; go to state_1 else stay at wake state
else NEXTSTATE = WAKE;
end
STATE_1: NEXTSTATE = STATE_2; // state_1; next state is state_2
STATE_2: NEXTSTATE = HOLD; // state_2; next state is hold
HOLD: NEXTSTATE = HOLD; // hold; stays at hold state
default: NEXTSTATE = RESET;
endcase // case(state)
end // always @ (state or com_pass)
// Output logic
always @(posedge clk or negedge reset_n) begin
if (!reset_n) rcv_found <= 1'b0;
else rcv_found <= next_rcv_found;
end
always @(NEXTSTATE or probe_pass or fake_rcv_present) begin
if ((NEXTSTATE == STATE_2) && (!probe_pass) && fake_rcv_present) // probe pass goes up slow -> there is rx
next_rcv_found = 1'b1;
else if ((NEXTSTATE == HOLD) && fake_rcv_present) next_rcv_found = rcv_found;
else // probe pass goes up fast -> no rx
next_rcv_found = 1'b0;
end
// there is no rcv_det_syn
always @(STATE) begin
if (STATE == RESET) det_on = 1'b0;
else det_on = 1'b1;
end
always @(STATE) begin
if (STATE == HOLD) detect_valid = 1'b1;
else detect_valid = 1'b0;
end
endmodule
| 8.011405 |
module cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_control (
input wire clk,
input wire rcv_det_en,
input wire rcv_det_pdb,
input wire com_pass,
input wire probe_pass,
output wire det_on,
output wire detect_valid,
output wire rcv_found
);
wire rcv_det_syn;
cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_sync xrcv_det_sync (
clk,
rcv_det_pdb,
rcv_det_en,
rcv_det_syn
);
cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_fsm xrcv_det_fsm (
clk,
rcv_det_syn,
com_pass,
probe_pass,
det_on,
detect_valid,
rcv_found
);
endmodule
| 8.011405 |
module cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_digital (
input wire oscclk,
input wire rcv_det_pdb,
input wire rcv_det_en,
input wire com_pass,
input wire probe_pass,
output wire det_on,
output wire detect_valid,
output wire rcv_found
);
wire clk;
cycloneiv_hssi_tx_pma_sub_tx_rx_det_clk_gen xclk_gen (
oscclk,
rcv_det_pdb,
clk
);
cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_control xrcv_det_ctrl (
clk,
rcv_det_en,
rcv_det_pdb,
com_pass,
probe_pass,
det_on,
detect_valid,
rcv_found
);
endmodule
| 8.011405 |
module is the behavior model for rx_det block
// If there is rx - set parameter RX_EXIST to 1, set to 0 otherwise
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneiv_hssi_tx_pma_sub_tx_rx_det
//
// Description : Receiver detect
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
module cycloneiv_hssi_tx_pma_sub_tx_rx_det (
input wire rx_det_pdb,
input wire clk15m,
input wire tx_det_rx,
output wire rx_found,
output wire rx_det_valid
);
wire com_pass, probe_pass, det_on;
parameter RX_EXIST = 1'b1;
assign #100000 com_pass = det_on;
assign #100000 probe_pass = ~RX_EXIST;
cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_digital xrcv_det_digital (
.oscclk (clk15m),
.rcv_det_pdb (rx_det_pdb),
.rcv_det_en (tx_det_rx),
.com_pass (com_pass),
.probe_pass (probe_pass),
.det_on (det_on),
.detect_valid (rx_det_valid),
.rcv_found (rx_found)
);
endmodule
| 7.595207 |
module receives serial data and outputs
// parallel data word of width = channel_width
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cycloneiv_hssi_rx_pma_sub_deser
#(
parameter channel_width = 8
)
(
input wire fclk,
input wire deven,
input wire dodd,
input wire loaden,
input wire clr,
output reg [9:0] rxdat
);
// INTERNAL VARIABLES AND NETS
reg [9:0] rxdat_tmp;
reg [9:0] rxdat_output;
reg [3:0] i;
reg clr_edge;
initial
begin
i = 4'b0;
clr_edge = 1'b0;
rxdat_tmp = 10'b0;
rxdat_output = 10'b0;
end
always @(loaden or clr)
begin
if (clr == 1'b1)
begin
rxdat_output <= 1'b0;
rxdat <= 1'b0;
end
else
if (loaden == 1'b1)
rxdat_output <= rxdat_tmp;
else if (loaden == 1'b0)
rxdat <= rxdat_output;
end
always @(fclk or clr)
begin
if (clr == 1'b1)
begin
rxdat_tmp <= 10'b0;
i <= 4'b0;
clr_edge <= 1'b1;
end
else
begin
if (clr_edge == 1'b1)
clr_edge <= 1'b0;
else if (fclk == 1'b1)
begin
rxdat_tmp[7:0] <= rxdat_tmp[9:2];
rxdat_tmp[8] <= deven;
rxdat_tmp[9] <= dodd;
end
end
end
endmodule
| 6.910834 |
module cycloneiv_hssi_rx_pma_sub_clkdiv (
input wire rxfclk,
input wire clr,
input wire [3:0] deser_fact,
output reg loaden,
output reg clkdivrx
);
integer clk_count;
reg first_clkcount;
reg clkdivrx_prev;
reg rxloaden;
initial begin
first_clkcount = 1'b0;
clkdivrx_prev = 1'b0;
clkdivrx = 1'b1;
clk_count = 1;
rxloaden = 1'b0;
loaden = 1'b0;
end
always @(negedge rxfclk) begin
if (clkdivrx == 1'b0 || first_clkcount == 1'b0) begin
rxloaden <= 1'b0;
end else if (rxfclk === 1'b0 && clkdivrx == 1'b1) begin
begin
rxloaden <= ~rxloaden;
end
end
end
always @(rxfclk or clr) begin
if (clr === 1'b1) begin
clkdivrx <= 1'b1;
loaden <= 1'b0;
clkdivrx_prev = 1'b1;
clk_count <= 1;
first_clkcount <= 1'b0;
end else if (clr === 1'b0) begin
// clockout
if (first_clkcount === 1'b0 && rxfclk === 1'b1) begin
first_clkcount <= 1'b1;
clk_count <= 1;
clkdivrx <= 1'b0;
end else if (clk_count === deser_fact) begin
clk_count <= 1;
clkdivrx <= ~clkdivrx_prev;
end else begin
clk_count <= clk_count + 1;
end
clkdivrx_prev <= clkdivrx;
// loaden
if (rxfclk == 1'b1) begin
if (rxloaden == 1'b1) begin
loaden <= 1'b1;
end else if (rxloaden == 1'b0) begin
loaden <= 1'b0;
end
end
end
end
endmodule
| 8.011405 |
module cycloneiv_hssi_pcs_reset (
hard_reset,
clk_2_b,
refclk_b_in,
scan_mode,
rxpcs_rst,
txpcs_rst,
rxrst_int,
txrst_int
);
input hard_reset;
input clk_2_b;
input refclk_b_in;
input scan_mode;
input rxpcs_rst;
input txpcs_rst;
output rxrst_int;
output txrst_int;
reg txrst_sync1, txrst_sync2;
reg rxrst_sync1, rxrst_sync2;
wire txrst_int, rxrst_int;
initial begin
txrst_sync1 = 1'b0;
txrst_sync2 = 1'b0;
rxrst_sync1 = 1'b0;
rxrst_sync2 = 1'b0;
end
always @(posedge hard_reset or posedge clk_2_b) begin
if (hard_reset) begin
rxrst_sync2 <= 1'b1;
rxrst_sync1 <= 1'b1;
end else begin
rxrst_sync2 <= #1 rxrst_sync1;
rxrst_sync1 <= rxpcs_rst;
end
end
always @(posedge hard_reset or posedge refclk_b_in) begin
if (hard_reset) begin
txrst_sync2 <= 1'b1;
txrst_sync1 <= 1'b1;
end else begin
txrst_sync2 <= #1 txrst_sync1;
txrst_sync1 <= txpcs_rst;
end
end
// 06-14-02 BT Changed SCAN_SHIFT signal to SCAN_MODE
//assign rxrst_int = !SCAN_SHIFT & rxrst_sync2;
//assign txrst_int = !SCAN_SHIFT & txrst_sync2;
assign rxrst_int = !scan_mode & rxrst_sync2;
assign txrst_int = !scan_mode & txrst_sync2;
endmodule
| 8.011405 |
module cycloneiv_hssi_tx_digis_txclk_gating (
select_n,
clk1,
clk2,
clk1out_n,
clk2out_n
);
input select_n;
input clk1;
input clk2;
output clk1out_n;
output clk2out_n;
assign clk1out_n = ~(select_n | clk1);
assign clk2out_n = ~(~select_n | clk2);
endmodule
| 8.011405 |
module cycloneiv_hssi_rx_digis_rxclk_gating (
select_n,
clk1,
clk2,
clk1out_n,
clk2out_n
);
input select_n;
input clk1;
input clk2;
output clk1out_n;
output clk2out_n;
assign clk1out_n = ~(select_n | clk1);
assign clk2out_n = ~(~select_n | clk2);
endmodule
| 8.011405 |
module cycloneiv_hssi_cmu_clk_gating (
select_n,
clk1,
clk2,
clk1out_n,
clk2out_n
);
input select_n;
input clk1;
input clk2;
output clk1out_n;
output clk2out_n;
assign clk1out_n = ~(select_n | clk1);
assign clk2out_n = ~(~select_n | clk2);
endmodule
| 8.011405 |
module cycloneiv_hssi_cmu_clk_ctl (
pclk_pma,
refclk_dig,
mdc,
ser_clk,
ser_mode,
scan_mode,
scan_clk,
rfreerun_centrl,
rcentrl_clk_sel,
rrefclk_out_div2,
hard_reset,
txrst,
refclk_pma_out,
mdc_b,
refclk_out,
rauto_speed_ena,
rfreq_sel,
gen2ngen1_bundle
);
input pclk_pma; // x4 PCLK from PMA CMU
input refclk_dig; // External digital clock
input mdc; // MDIO input clock
input ser_clk; // Serial clock
input ser_mode; // Serial shift configuration mode
input scan_mode; // Scan mode
input scan_clk; // Scan mode
input rfreerun_centrl; // REFCLK_OUT free running enable CRAM
input rcentrl_clk_sel; // REFCLK_PMA global clock selection CRAM
input rrefclk_out_div2; // REFCLK_OUT divide by 2 enable CRAM
input hard_reset; // Hard reset input
input txrst;
input rauto_speed_ena;
input rfreq_sel;
input gen2ngen1_bundle;
output refclk_pma_out; // Global TX PCS clock
output mdc_b; // Configuration output clock
output refclk_out; // REFCLK_OUT output clk
wire refclk_pma_int, refclk_out_div2_inv, hard_reset_n;
reg refclk_out_div2;
reg gen2ngen1_local_sync;
wire dynamic_div2ndiv1;
wire clk1out_n;
wire clk2out_n;
// shawn initial begin ------
initial begin
refclk_out_div2 = 1'b1;
end
// shawn initial end ------
// The following assignments need to be replaced with clock buffers
// instantiation when the technology is identified later
// refclk_pma clock selection
assign refclk_pma_int = (rcentrl_clk_sel) ? refclk_dig : pclk_pma;
assign refclk_pma_out = (scan_mode) ? scan_clk : refclk_pma_int;
// refclk_out logic
// This register is used to generate divided by two clock. Div by 2 clock starts off high after reset
assign refclk_out_div2_inv = (rauto_speed_ena & ~rfreq_sel) ? (~refclk_out_div2 | ~gen2ngen1_local_sync) : ~refclk_out_div2;
assign hard_reset_n = rfreerun_centrl ? 1'b1 : ~hard_reset;
always @(negedge hard_reset_n or posedge refclk_pma_out) begin
if (~hard_reset_n) refclk_out_div2 <= 1'b1;
else refclk_out_div2 <= refclk_out_div2_inv;
end
always @(posedge txrst or posedge refclk_pma_out) begin
if (txrst) gen2ngen1_local_sync <= #1 1'b0;
else gen2ngen1_local_sync <= #1 gen2ngen1_bundle;
end
assign dynamic_div2ndiv1 = rrefclk_out_div2 | (gen2ngen1_local_sync & rauto_speed_ena & ~rfreq_sel);
cycloneiv_hssi_cmu_clk_gating centrl_clk_gating (
.select_n(dynamic_div2ndiv1),
.clk1(refclk_pma_out),
.clk2(refclk_out_div2),
.clk1out_n(clk1out_n),
.clk2out_n(clk2out_n)
);
assign refclk_out = ~(clk1out_n | clk2out_n);
// mdc_b clock logic
assign mdc_b = ({scan_mode, ser_mode} == 2'b11) ? refclk_pma_out :
({scan_mode, ser_mode} == 2'b10) ? refclk_pma_out :
({scan_mode, ser_mode} == 2'b01) ? ser_clk :
({scan_mode, ser_mode} == 2'b00) ? mdc :
mdc;
endmodule
| 8.011405 |
module cycloneiv_hssi_cmu_rxclk_gating (
select_n,
clk1,
clk2,
clk1out_n,
clk2out_n
);
input select_n;
input clk1;
input clk2;
output clk1out_n;
output clk2out_n;
assign clk1out_n = ~(select_n | clk1);
assign clk2out_n = ~(~select_n | clk2);
endmodule
| 8.011405 |
module cycloneiv_hssi_cmu_txclk_gating (
select_n,
clk1,
clk2,
clk1out_n,
clk2out_n
);
input select_n;
input clk1;
input clk2;
output clk1out_n;
output clk2out_n;
assign clk1out_n = ~(select_n | clk1);
assign clk2out_n = ~(~select_n | clk2);
endmodule
| 8.011405 |
module cycloneiv_hssi_cmu_dprio_bit (
reset,
clk,
sig_in,
ext_in,
serial_mode,
si,
shift,
mdio_dis,
sig_out,
so
);
input reset; // reset
input clk; // clock
input sig_in; // signal input
input ext_in; // external input port
input serial_mode; // serial shift mode enable
input si; // scan input
input shift; // 1'b1=shift in data from si into scan flop
// 1'b0=load data from sig_in into scan flop
input mdio_dis; // 1'b1=choose ext_in to the sig_out mux
// 1'b0=choose so to the sign_out mux
output sig_out; // signal output
output so; // scan output
wire sig_out;
wire cram_int;
wire set_int;
reg so;
// select signal output
assign sig_out = (serial_mode) ? (so & ~shift) : (cram_int);
assign cram_int = (mdio_dis) ? (ext_in) : (so);
// Set signal for the flop
assign set_int = (shift | reset) ? 1'b0 : ext_in;
// scan flop
always @(posedge reset or posedge set_int or posedge clk)
if (reset) so <= 1'b0;
else if (set_int) so <= 1'b1;
else if (shift && serial_mode) so <= si;
else so <= sig_in;
endmodule
| 8.011405 |
module cycloneiv_hssi_cmu_dprio_bit_pma (
reset,
clk,
sig_in,
ext_in,
serial_mode,
si,
shift,
mdio_dis,
pma_cram_test,
sig_out,
so
);
input reset; // reset
input clk; // clock
input sig_in; // signal input
input ext_in; // external input port
input serial_mode; // serial shift mode enable
input si; // scan input
input shift; // 1'b1=shift in data from si into scan flop
// 1'b0=load data from sig_in into scan flop
input mdio_dis; // 1'b1=choose ext_in to the sig_out mux
// 1'b0=choose so to the sign_out mux
input pma_cram_test; //1'b1: choose the previous output of this register
//1'b0: choose either si or input from DPRIO SM (sig_in)
output sig_out; // signal output
output so; // scan output
wire sig_out;
wire cram_int;
wire set_int;
reg so;
// select signal output
assign sig_out = (serial_mode) ? (so & ~shift) : (cram_int);
assign cram_int = (mdio_dis) ? (ext_in) : (so);
// Set signal for the flop
assign set_int = (shift | reset) ? 1'b0 : ext_in;
// scan flop
always @(posedge reset or posedge set_int or posedge clk)
if (reset) so <= 1'b0;
else if (set_int) so <= 1'b1;
else if (pma_cram_test) so <= sig_out;
else if (shift && serial_mode) so <= si;
else so <= sig_in;
endmodule
| 8.011405 |
module cycloneiv_hssi_calibration_block (
clk,
powerdn,
testctrl,
calibrationstatus,
nonusertocmu
);
// *** End of Section 3 ***
// *** Section 4 -- Parameter declarations and default values ***
parameter lpm_type = "cycloneiv_hssi_calibration_block";
parameter cont_cal_mode = "false";
parameter enable_rx_cal_tw = "false";
parameter enable_tx_cal_tw = "false";
parameter rtest = "false";
parameter rx_cal_wt_value = 0;
parameter send_rx_cal_status = "false";
parameter tx_cal_wt_value = 1;
// *** End of Section 4 ***
// *** Section 5 -- Port declarations ***
input clk;
input powerdn;
input testctrl;
output [4 : 0] calibrationstatus;
output nonusertocmu;
// *** End of Section 5 ***
// *** Section 6 -- Port declarations with defaults, if any ***
// This section will always be empty for WYSIWYG atoms
// tri1 devclrn; //sample
// *** End of Section 6 ***
endmodule
| 8.011405 |
module cycloneiv_pciehip_dprio_bit (
reset,
clk,
sig_in,
ext_in,
serial_mode,
si,
shift,
mdio_dis,
sig_out,
so
);
input reset; // reset
input clk; // clock
input sig_in; // signal input
input ext_in; // external input port
input serial_mode; // serial shift mode enable
input si; // scan input
input shift; // 1'b1=shift in data from si into scan flop
// 1'b0=load data from sig_in into scan flop
input mdio_dis; // 1'b1=choose ext_in to the sig_out mux
// 1'b0=choose so to the sign_out mux
output sig_out; // signal output
output so; // scan output
wire sig_out;
wire cram_int;
wire set_int;
reg so;
// select signal output
assign sig_out = (serial_mode) ? (so & ~shift) : (cram_int);
assign cram_int = (mdio_dis) ? (ext_in) : (so);
// Set signal for the flop
assign set_int = (shift | reset) ? 1'b0 : ext_in;
// scan flop
always @(posedge reset or posedge set_int or posedge clk)
if (reset) so <= 1'b0;
else if (set_int) so <= 1'b1;
else if (shift && serial_mode) so <= si;
else so <= sig_in;
endmodule
| 7.364512 |
module cycloneiv_pciehip_compute_bit (
input wire [63:0] datain,
input wire s,
output wire r
);
// begin
assign r = datain[0] ^ datain[1] ^ datain[2] ^ datain[3] ^ datain[4] ^ datain[5] ^ datain[6] ^ datain[7] ^ datain[10] ^ datain[13] ^ datain[14] ^ datain[17] ^
datain[20] ^ datain[23] ^ datain[24] ^ datain[27] ^ datain[35] ^ datain[43] ^ datain[46] ^ datain[47] ^ datain[51] ^ datain[52] ^ datain[53] ^
datain[56] ^ datain[57] ^ datain[58] ^ s;
// end
endmodule
| 7.364512 |
module cycloneiv_pciehip_ecc_gen (
input wire [63:0] datain, // Data on which ECC is required
input wire [ 7:0] syndrome, // Syndrome uses 8'h00 while generating
output wire [ 7:0] result // Result
);
//-----------------------------------------------------------------------------
// Instantiate Result Compute block for 8 bits
//-----------------------------------------------------------------------------
cycloneiv_pciehip_compute_bit cb_0 (
.datain(datain),
.s (syndrome[0]),
.r (result[0])
);
cycloneiv_pciehip_compute_bit cb_1 (
.datain({datain[7:0], datain[63:8]}),
.s(syndrome[1]),
.r(result[1])
);
cycloneiv_pciehip_compute_bit cb_2 (
.datain({datain[15:0], datain[63:16]}),
.s(syndrome[2]),
.r(result[2])
);
cycloneiv_pciehip_compute_bit cb_3 (
.datain({datain[23:0], datain[63:24]}),
.s(syndrome[3]),
.r(result[3])
);
cycloneiv_pciehip_compute_bit cb_4 (
.datain({datain[31:0], datain[63:32]}),
.s(syndrome[4]),
.r(result[4])
);
cycloneiv_pciehip_compute_bit cb_5 (
.datain({datain[39:0], datain[63:40]}),
.s(syndrome[5]),
.r(result[5])
);
cycloneiv_pciehip_compute_bit cb_6 (
.datain({datain[47:0], datain[63:48]}),
.s(syndrome[6]),
.r(result[6])
);
cycloneiv_pciehip_compute_bit cb_7 (
.datain({datain[55:0], datain[63:56]}),
.s(syndrome[7]),
.r(result[7])
);
endmodule
| 7.364512 |
module cycloneiv_pciehip_ecc_decoder (
flag,
derr,
derr_cor
);
input [2:0] flag;
output derr;
output derr_cor;
assign derr = flag[2] & ~(flag[1]) & flag[0];
assign derr_cor = ~(flag[2]) & flag[1] & flag[0];
endmodule
| 7.364512 |
module cycloneiv_pciehip_pulse_ext (
core_clk,
rstn,
srst,
derr_cor,
derr_cor_ext
);
input core_clk;
input rstn;
input srst;
input derr_cor;
output derr_cor_ext;
reg n1, derr_cor_ext;
wire n2;
// Pulse width extender
always @(negedge rstn or posedge core_clk) begin
if (rstn == 1'b0) begin
n1 <= 1'b0;
end else begin
if (srst == 1'b1) begin
n1 <= 1'b0;
end else begin
n1 <= derr_cor;
end
end
end
assign n2 = n1 | derr_cor;
always @(negedge rstn or posedge core_clk) begin
if (rstn == 1'b0) begin
derr_cor_ext <= 1'b0;
end else begin
if (srst == 1'b1) begin
derr_cor_ext <= 1'b0;
end else begin
derr_cor_ext <= n2;
end
end
end
endmodule
| 7.364512 |
module cycloneiv_pciehip_pciexp_dcfiforam (
data,
wren,
wraddress,
rdaddress,
wrclock,
rdclock,
q
);
parameter addr_width = 4;
parameter data_width = 32;
input [data_width - 1:0] data;
input wren;
input [addr_width - 1:0] wraddress;
input [addr_width - 1:0] rdaddress;
input wrclock;
input rdclock;
output [data_width - 1:0] q;
wire [data_width - 1:0] q;
reg [data_width - 1:0] ram_block[0:2 ** addr_width - 1];
reg [addr_width - 1:0] rdaddr_r;
reg [addr_width - 1:0] wraddr_r;
reg wren_r;
reg [data_width - 1:0] wrdata_r;
// Write process
always @(posedge wrclock) begin
wren_r <= wren;
wraddr_r <= wraddress;
wrdata_r <= data;
if (wren_r == 1'b1) begin
ram_block[wraddr_r] <= wrdata_r;
end
end
// Read process
always @(posedge rdclock) begin
rdaddr_r <= rdaddress;
end
assign q = ram_block[rdaddr_r];
endmodule
| 7.364512 |
module cycloneiv_pciehip_pciexp_dcram_rtry (
wrclock,
wren,
wraddress,
data,
rdclock,
rdaddress,
q
);
parameter addr_width = 'd4;
parameter data_width = 'd32;
input wrclock;
input wren;
input [data_width - 1:0] data;
input [addr_width - 1:0] wraddress;
input rdclock;
input [addr_width - 1:0] rdaddress;
output [data_width - 1:0] q;
wire [data_width - 1:0] q;
// -------------------------------------------------------------
reg [data_width - 1:0] ram_block [(1<<addr_width)-1:0];
reg [addr_width - 1:0] read_addr_r;
reg [addr_width - 1:0] wraddr_r;
reg wren_r;
reg [data_width - 1:0] wrdata_r;
// Write process
always @(posedge wrclock) begin : process_1
wren_r <= wren;
wraddr_r <= wraddress;
wrdata_r <= data;
if (wren_r == 1'b1) begin
ram_block[wraddr_r] <= wrdata_r;
end
end
// Read process
always @(posedge rdclock) begin : process_3
read_addr_r <= rdaddress;
end
assign q = ram_block[read_addr_r];
endmodule
| 7.364512 |
module cycloneiv_pciehip_pciexp_dcram_rxvc (
wrclock,
wren,
wraddress,
data,
rdclock,
rdaddress,
q
);
parameter addr_width = 'd4;
parameter data_width = 'd32;
input wrclock;
input wren;
input [data_width - 1:0] data;
input [addr_width - 1:0] wraddress;
input rdclock;
input [addr_width - 1:0] rdaddress;
output [data_width - 1:0] q;
wire [data_width - 1:0] q;
// -------------------------------------------------------------
reg [data_width - 1:0] ram_block [(1<<addr_width)-1:0];
reg [addr_width - 1:0] read_addr_r;
reg [addr_width - 1:0] wraddr_r;
reg wren_r;
reg [data_width - 1:0] wrdata_r;
// Write process
always @(posedge wrclock) begin : process_1
wren_r <= wren;
wraddr_r <= wraddress;
wrdata_r <= data;
if (wren_r == 1'b1) begin
ram_block[wraddr_r] <= wrdata_r;
end
end
// Read process
always @(posedge rdclock) begin : process_3
read_addr_r <= rdaddress;
end
assign q = ram_block[read_addr_r];
endmodule
| 7.364512 |
module is not intended to be instantiated by rather referenced by an
// absolute path from the altpcietb_bfm_log.v include file. This allows all
// users of altpcietb_bfm_log.v to see a common set of values.
//-----------------------------------------------------------------------------
// Copyright (c) 2005 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
module altpcietb_bfm_log_common(dummy_out) ;
output dummy_out;
`include "altpcietb_bfm_log.v"
integer log_file ;
reg [EBFM_MSG_ERROR_CONTINUE:EBFM_MSG_DEBUG] suppressed_msg_mask ;
reg [EBFM_MSG_ERROR_CONTINUE:EBFM_MSG_DEBUG] stop_on_msg_mask ;
initial
begin
suppressed_msg_mask = {EBFM_MSG_ERROR_CONTINUE-EBFM_MSG_DEBUG+1{1'b0}} ;
suppressed_msg_mask[EBFM_MSG_DEBUG] = 1'b1 ;
stop_on_msg_mask = {EBFM_MSG_ERROR_CONTINUE-EBFM_MSG_DEBUG+1{1'b0}} ;
end
endmodule
| 8.44882 |
module altpcietb_bfm_shmem_common (
dummy_out
);
`include "altpcietb_bfm_constants.v"
`include "altpcietb_bfm_log.v"
`include "altpcietb_bfm_shmem.v"
output dummy_out;
reg [7:0] shmem[0:SHMEM_SIZE-1];
// Protection Bit for the Shared Memory
// This bit protects critical data in Shared Memory from being overwritten.
// Critical data includes things like the BAR table that maps BAR numbers to addresses.
// Deassert this bit to REMOVE protection of the CRITICAL data.
reg protect_bfm_shmem;
initial begin
shmem_fill(0, SHMEM_FILL_ZERO, SHMEM_SIZE, {64{1'b0}});
protect_bfm_shmem = 1'b1;
end
endmodule
| 6.756527 |
module altpcietb_ltssm_mon (
rp_clk,
rstn,
rp_ltssm,
ep_ltssm,
dummy_out
);
`include "altpcietb_bfm_constants.v"
`include "altpcietb_bfm_log.v"
`include "altpcietb_bfm_shmem.v"
`include "altpcietb_bfm_rdwr.v"
input rp_clk;
input rstn;
input [4:0] rp_ltssm;
input [4:0] ep_ltssm;
output dummy_out;
reg [4:0] rp_ltssm_r;
reg [4:0] ep_ltssm_r;
task conv_ltssm;
input device;
input detect_timout;
input [4:0] ltssm;
reg [(23)*8:1] ltssm_str;
reg dummy, dummy2;
begin
case (ltssm)
5'b00000: ltssm_str = "DETECT.QUIET ";
5'b00001: ltssm_str = "DETECT.ACTIVE ";
5'b00010: ltssm_str = "POLLING.ACTIVE ";
5'b00011: ltssm_str = "POLLING.COMPLIANCE ";
5'b00100: ltssm_str = "POLLING.CONFIG ";
5'b00110: ltssm_str = "CONFIG.LINKWIDTH.START ";
5'b00111: ltssm_str = "CONFIG.LINKWIDTH.ACCEPT";
5'b01000: ltssm_str = "CONFIG.LANENUM.ACCEPT ";
5'b01001: ltssm_str = "CONFIG.LANENUM.WAIT ";
5'b01010: ltssm_str = "CONFIG.COMPLETE ";
5'b01011: ltssm_str = "CONFIG.IDLE ";
5'b01100: ltssm_str = "RECOVERY.RCVRLOCK ";
5'b01101: ltssm_str = "RECOVERY.RCVRCFG ";
5'b01110: ltssm_str = "RECOVERY.IDLE ";
5'b01111: ltssm_str = "L0 ";
5'b10000: ltssm_str = "DISABLE ";
5'b10001: ltssm_str = "LOOPBACK.ENTRY ";
5'b10010: ltssm_str = "LOOPBACK.ACTIVE ";
5'b10011: ltssm_str = "LOOPBACK.EXIT ";
5'b10100: ltssm_str = "HOT RESET ";
5'b10101: ltssm_str = "L0s ";
5'b10110: ltssm_str = "L1.ENTRY ";
5'b10111: ltssm_str = "L1.IDLE ";
5'b11000: ltssm_str = "L2.IDLE ";
5'b11001: ltssm_str = "L2.TRANSMITWAKE ";
5'b11010: ltssm_str = "RECOVERY.SPEED ";
default: ltssm_str = "UNKNOWN ";
endcase
if (detect_timout == 1)
dummy = ebfm_display(EBFM_MSG_ERROR_FATAL, {" LTSSM does not change from DETECT.QUIET"});
else if (device == 0) dummy = ebfm_display(EBFM_MSG_INFO, {" RP LTSSM State: ", ltssm_str});
else dummy = ebfm_display(EBFM_MSG_INFO, {" EP LTSSM State: ", ltssm_str});
end
endtask
reg [3:0] detect_cnt;
always @(posedge rp_clk) begin
rp_ltssm_r <= rp_ltssm;
ep_ltssm_r <= ep_ltssm;
if (rp_ltssm_r != rp_ltssm) conv_ltssm(0, 0, rp_ltssm);
if (ep_ltssm_r != ep_ltssm) conv_ltssm(1, 0, ep_ltssm);
end
always @(posedge rp_clk or negedge rstn) begin
if (rstn == 1'b0) begin
detect_cnt <= 4'h0;
end else begin
if (rp_ltssm_r != rp_ltssm) begin
if (detect_cnt == 4'b1000) begin
conv_ltssm(1, 1, rp_ltssm);
end else if (rp_ltssm == 5'b01111) begin
detect_cnt <= 4'h0;
end else if (rp_ltssm == 5'b00000) begin
detect_cnt <= detect_cnt + 4'h1;
end
end
end
end
endmodule
| 6.629067 |
module contains the clock synchronization logic for a signal from clock
// domain 1 to clock domain 2.
// if the cg_common_clock_mode_i is active, signal1 will be passed through to
// signal 2 with a direct connection
module altpciexpav128_clksync ( cg_common_clock_mode_i,
Clk1_i,
Clk2_i,
Clk1Rstn_i,
Clk2Rstn_i,
Sig1_i,
Sig2_o,
SyncPending_o,
Ack_o);
input cg_common_clock_mode_i;
input Clk1_i;
input Clk2_i;
input Clk1Rstn_i;
input Clk2Rstn_i;
input Sig1_i;
output Sig2_o;
output Ack_o;
output SyncPending_o;
wire input_rise;
reg input_sig_reg;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg output1_reg;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg output2_reg;
reg output3_reg;
reg sig2_o_reg;
reg req_reg;
reg ack_reg;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ack1_reg;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ack2_reg;
reg ack3_reg;
reg pending_reg;
always @(posedge Clk1_i or negedge Clk1Rstn_i)
begin
if(~Clk1Rstn_i)
input_sig_reg <= 1'b0;
else
input_sig_reg <= Sig1_i;
end
// detect the rising edge of the input signal to be transfer to clock domain 2
assign input_rise = ~input_sig_reg & Sig1_i;
// input signal toggles req_reg flop. The other clock domain asserts single cycle pulse
// on edge detection
always @(posedge Clk1_i or negedge Clk1Rstn_i)
begin
if(~Clk1Rstn_i)
begin
req_reg <= 1'b0;
pending_reg <= 1'b0;
end
else
begin
if(input_rise)
req_reg <= ~req_reg;
if (input_rise)
pending_reg <= 1'b1;
else if (ack3_reg^ack2_reg)
pending_reg <= 1'b0;
end
end
// forward synch reg with double registers
always @(posedge Clk2_i or negedge Clk2Rstn_i)
begin
if(~Clk2Rstn_i)
begin
output1_reg <= 1'b0;
output2_reg <= 1'b0;
output3_reg <= 1'b0;
sig2_o_reg <= 1'b0;
ack_reg <= 1'b0;
end
else
begin
output1_reg <= req_reg;
output2_reg <= output1_reg;
output3_reg <= output2_reg;
// self clear
if (output3_reg^output2_reg)
sig2_o_reg <= 1'b1;
else
sig2_o_reg <= 1'b0;
if (output3_reg^output2_reg)
ack_reg <= ~ack_reg;
end
end
// backward synch reg. double register sync the ack signal from clock domain2
always @(posedge Clk1_i or negedge Clk1Rstn_i)
begin
if(~Clk1Rstn_i)
begin
ack1_reg <= 1'b0;
ack2_reg <= 1'b0;
ack3_reg <= 1'b0;
end
else
begin
ack1_reg <= ack_reg;
ack2_reg <= ack1_reg;
ack3_reg <= ack2_reg;
end
end
// Muxing the output based on the parameter cg_common_clock_mode_i
// the entire sync logic will be synthesized away if the same clock domain
// is used.
assign Sig2_o = (cg_common_clock_mode_i == 0) ? sig2_o_reg : input_sig_reg;
// Ackknowlege out
assign Ack_o = ack2_reg;
/// sync is pending
assign SyncPending_o = (cg_common_clock_mode_i == 0) ? pending_reg : 1'b0;
endmodule
| 7.358377 |
module altpciexpav128_fifo #(
parameter FIFO_DEPTH = 3,
parameter DATA_WIDTH = 144
) (
// global signals
input clk,
input rstn,
input srst,
input wrreq,
input rdreq,
input [DATA_WIDTH-1:0] data,
output [DATA_WIDTH-1:0] q,
output reg [ 3:0] fifo_count
);
reg [DATA_WIDTH-1:0] fifo_reg [FIFO_DEPTH-1:0];
wire [FIFO_DEPTH-1:0] fifo_wrreq;
// fifo word counter
always @(posedge clk or negedge rstn) begin
if (~rstn) fifo_count <= 4'h0;
else if (srst) fifo_count <= 4'h0;
else if (rdreq & ~wrreq) fifo_count <= fifo_count - 1'b1;
else if (~rdreq & wrreq) fifo_count <= fifo_count + 1'b1;
end
generate
genvar i;
for (i = 0; i < FIFO_DEPTH - 1; i = i + 1) begin : register_array
assign fifo_wrreq[i] = wrreq & (fifo_count == i | (fifo_count == i + 1 & rdreq));
always @(posedge clk or negedge rstn) begin
if (~rstn) fifo_reg[i] <= {DATA_WIDTH{1'b0}};
else if (srst) fifo_reg[i] <= {DATA_WIDTH{1'b0}};
else if (fifo_wrreq[i]) fifo_reg[i] <= data;
else if (rdreq) fifo_reg[i] <= fifo_reg[i+1];
end
end
endgenerate
/// the last register
assign fifo_wrreq[FIFO_DEPTH-1] = wrreq & (fifo_count == FIFO_DEPTH - 1 | (fifo_count == FIFO_DEPTH & rdreq)) ;
always @(posedge clk or negedge rstn) begin
if (~rstn) fifo_reg[FIFO_DEPTH-1] <= {DATA_WIDTH{1'b0}};
else if (srst) fifo_reg[FIFO_DEPTH-1] <= {DATA_WIDTH{1'b0}};
else if (fifo_wrreq[FIFO_DEPTH-1]) fifo_reg[FIFO_DEPTH-1] <= data;
end
assign q = fifo_reg[0];
endmodule
| 8.703434 |
module altpciexpav128_p2a_addrtrans (
k_bar_i,
cb_p2a_avalon_addr_b0_i,
cb_p2a_avalon_addr_b1_i,
cb_p2a_avalon_addr_b2_i,
cb_p2a_avalon_addr_b3_i,
cb_p2a_avalon_addr_b4_i,
cb_p2a_avalon_addr_b5_i,
cb_p2a_avalon_addr_b6_i,
PCIeAddr_i,
BarHit_i,
AvlAddr_o
);
input [223:0] k_bar_i;
input [31:0] cb_p2a_avalon_addr_b0_i;
input [31:0] cb_p2a_avalon_addr_b1_i;
input [31:0] cb_p2a_avalon_addr_b2_i;
input [31:0] cb_p2a_avalon_addr_b3_i;
input [31:0] cb_p2a_avalon_addr_b4_i;
input [31:0] cb_p2a_avalon_addr_b5_i;
input [31:0] cb_p2a_avalon_addr_b6_i;
input [31:0] PCIeAddr_i;
input [6:0] BarHit_i;
output [31:0] AvlAddr_o;
reg [31:0] bar_parameter;
reg [31:0] avl_addr;
wire [31:0] bar0;
wire [31:0] bar1;
wire [31:0] bar2;
wire [31:0] bar3;
wire [31:0] bar4;
wire [31:0] bar5;
wire [31:0] exp_rom_bar;
assign bar0 = k_bar_i[31:0];
assign bar1 = k_bar_i[63:32];
assign bar2 = k_bar_i[95:64];
assign bar3 = k_bar_i[127:96];
assign bar4 = k_bar_i[159:128];
assign bar5 = k_bar_i[191:160];
assign exp_rom_bar = k_bar_i[223:192];
// mux to select the right BAR parameter to use.
// based on the BAR hit information, determined BAR paremeter
// is used for the address translation
always @(BarHit_i or bar0 or bar1 or bar2 or bar3 or bar4 or bar5 or exp_rom_bar) begin
case (BarHit_i)
7'b0000001: bar_parameter = bar0;
7'b0000010: bar_parameter = bar1;
7'b0000100: bar_parameter = bar2;
7'b0001000: bar_parameter = bar3;
7'b0010000: bar_parameter = bar4;
7'b0100000: bar_parameter = bar5;
7'b1000000: bar_parameter = exp_rom_bar;
default: bar_parameter = 32'h00000000;
endcase
end
// mux to select the right avalon address entry to use
// Based on the BAR hit information, select which entry in the table to
// be used for the address translation
always @(BarHit_i or cb_p2a_avalon_addr_b0_i or cb_p2a_avalon_addr_b1_i or
cb_p2a_avalon_addr_b2_i or cb_p2a_avalon_addr_b3_i or
cb_p2a_avalon_addr_b4_i or cb_p2a_avalon_addr_b5_i or
cb_p2a_avalon_addr_b6_i)
begin
case (BarHit_i)
7'b0000001: avl_addr = cb_p2a_avalon_addr_b0_i;
7'b0000010: avl_addr = cb_p2a_avalon_addr_b1_i;
7'b0000100: avl_addr = cb_p2a_avalon_addr_b2_i;
7'b0001000: avl_addr = cb_p2a_avalon_addr_b3_i;
7'b0010000: avl_addr = cb_p2a_avalon_addr_b4_i;
7'b0100000: avl_addr = cb_p2a_avalon_addr_b5_i;
7'b1000000: avl_addr = cb_p2a_avalon_addr_b6_i;
default: avl_addr = 32'h00000000;
endcase
end
// address translation. The high order bits is from the corresponding
// entry of the table and low order is passed through unchanged.
assign AvlAddr_o = (PCIeAddr_i & ~({bar_parameter[31:4], 4'b0000})) |
(avl_addr & ({bar_parameter[31:4], 4'b0000})) ;
endmodule
| 8.703434 |
module contains the clock synchronization logic for a signal from clock
// domain 1 to clock domain 2.
// if the cg_common_clock_mode_i is active, signal1 will be passed through to
// signal 2 with a direct connection
module altpciexpav_clksync ( cg_common_clock_mode_i,
Clk1_i,
Clk2_i,
Clk1Rstn_i,
Clk2Rstn_i,
Sig1_i,
Sig2_o,
SyncPending_o,
Ack_o);
input cg_common_clock_mode_i;
input Clk1_i;
input Clk2_i;
input Clk1Rstn_i;
input Clk2Rstn_i;
input Sig1_i;
output Sig2_o;
output Ack_o;
output SyncPending_o;
wire input_rise;
reg input_sig_reg;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg output1_reg;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg output2_reg;
reg output3_reg;
reg sig2_o_reg;
reg req_reg;
reg ack_reg;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ack1_reg;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ack2_reg;
reg ack3_reg;
reg pending_reg;
always @(posedge Clk1_i or negedge Clk1Rstn_i)
begin
if(~Clk1Rstn_i)
input_sig_reg <= 1'b0;
else
input_sig_reg <= Sig1_i;
end
// detect the rising edge of the input signal to be transfer to clock domain 2
assign input_rise = ~input_sig_reg & Sig1_i;
// input signal toggles req_reg flop. The other clock domain asserts single cycle pulse
// on edge detection
always @(posedge Clk1_i or negedge Clk1Rstn_i)
begin
if(~Clk1Rstn_i)
begin
req_reg <= 1'b0;
pending_reg <= 1'b0;
end
else
begin
if(input_rise)
req_reg <= ~req_reg;
if (input_rise)
pending_reg <= 1'b1;
else if (ack3_reg^ack2_reg)
pending_reg <= 1'b0;
end
end
// forward synch reg with double registers
always @(posedge Clk2_i or negedge Clk2Rstn_i)
begin
if(~Clk2Rstn_i)
begin
output1_reg <= 1'b0;
output2_reg <= 1'b0;
output3_reg <= 1'b0;
sig2_o_reg <= 1'b0;
ack_reg <= 1'b0;
end
else
begin
output1_reg <= req_reg;
output2_reg <= output1_reg;
output3_reg <= output2_reg;
// self clear
if (output3_reg^output2_reg)
sig2_o_reg <= 1'b1;
else
sig2_o_reg <= 1'b0;
if (output3_reg^output2_reg)
ack_reg <= ~ack_reg;
end
end
// backward synch reg. double register sync the ack signal from clock domain2
always @(posedge Clk1_i or negedge Clk1Rstn_i)
begin
if(~Clk1Rstn_i)
begin
ack1_reg <= 1'b0;
ack2_reg <= 1'b0;
ack3_reg <= 1'b0;
end
else
begin
ack1_reg <= ack_reg;
ack2_reg <= ack1_reg;
ack3_reg <= ack2_reg;
end
end
// Muxing the output based on the parameter cg_common_clock_mode_i
// the entire sync logic will be synthesized away if the same clock domain
// is used.
assign Sig2_o = (cg_common_clock_mode_i == 0) ? sig2_o_reg : input_sig_reg;
// Ackknowlege out
assign Ack_o = ack2_reg;
/// sync is pending
assign SyncPending_o = (cg_common_clock_mode_i == 0) ? pending_reg : 1'b0;
endmodule
| 7.358377 |
module altpciexpav_stif_p2a_addrtrans (
k_bar_i,
cb_p2a_avalon_addr_b0_i,
cb_p2a_avalon_addr_b1_i,
cb_p2a_avalon_addr_b2_i,
cb_p2a_avalon_addr_b3_i,
cb_p2a_avalon_addr_b4_i,
cb_p2a_avalon_addr_b5_i,
cb_p2a_avalon_addr_b6_i,
PCIeAddr_i,
BarHit_i,
AvlAddr_o
);
input [227:0] k_bar_i;
input [31:0] cb_p2a_avalon_addr_b0_i;
input [31:0] cb_p2a_avalon_addr_b1_i;
input [31:0] cb_p2a_avalon_addr_b2_i;
input [31:0] cb_p2a_avalon_addr_b3_i;
input [31:0] cb_p2a_avalon_addr_b4_i;
input [31:0] cb_p2a_avalon_addr_b5_i;
input [31:0] cb_p2a_avalon_addr_b6_i;
input [31:0] PCIeAddr_i;
input [6:0] BarHit_i;
output [31:0] AvlAddr_o;
reg [31:0] bar_parameter;
reg [31:0] avl_addr;
wire [31:0] bar0;
wire [31:0] bar1;
wire [31:0] bar2;
wire [31:0] bar3;
wire [31:0] bar4;
wire [31:0] bar5;
wire [31:0] exp_rom_bar;
assign bar0 = k_bar_i[31:0];
assign bar1 = k_bar_i[63:32];
assign bar2 = k_bar_i[95:64];
assign bar3 = k_bar_i[127:96];
assign bar4 = k_bar_i[159:128];
assign bar5 = k_bar_i[191:160];
assign exp_rom_bar = k_bar_i[223:192];
// mux to select the right BAR parameter to use.
// based on the BAR hit information, determined BAR paremeter
// is used for the address translation
always @(BarHit_i or bar0 or bar1 or bar2 or bar3 or bar4 or bar5 or exp_rom_bar) begin
case (BarHit_i)
7'b0000001: bar_parameter = bar0;
7'b0000010: bar_parameter = bar1;
7'b0000100: bar_parameter = bar2;
7'b0001000: bar_parameter = bar3;
7'b0010000: bar_parameter = bar4;
7'b0100000: bar_parameter = bar5;
7'b1000000: bar_parameter = exp_rom_bar;
default: bar_parameter = 32'h00000000;
endcase
end
// mux to select the right avalon address entry to use
// Based on the BAR hit information, select which entry in the table to
// be used for the address translation
always @(BarHit_i or cb_p2a_avalon_addr_b0_i or cb_p2a_avalon_addr_b1_i or
cb_p2a_avalon_addr_b2_i or cb_p2a_avalon_addr_b3_i or
cb_p2a_avalon_addr_b4_i or cb_p2a_avalon_addr_b5_i or
cb_p2a_avalon_addr_b6_i)
begin
case (BarHit_i)
7'b0000001: avl_addr = cb_p2a_avalon_addr_b0_i;
7'b0000010: avl_addr = cb_p2a_avalon_addr_b1_i;
7'b0000100: avl_addr = cb_p2a_avalon_addr_b2_i;
7'b0001000: avl_addr = cb_p2a_avalon_addr_b3_i;
7'b0010000: avl_addr = cb_p2a_avalon_addr_b4_i;
7'b0100000: avl_addr = cb_p2a_avalon_addr_b5_i;
7'b1000000: avl_addr = cb_p2a_avalon_addr_b6_i;
default: avl_addr = 32'h00000000;
endcase
end
// address translation. The high order bits is from the corresponding
// entry of the table and low order is passed through unchanged.
assign AvlAddr_o = (PCIeAddr_i & ~({bar_parameter[31:4], 4'b0000})) |
(avl_addr & ({bar_parameter[31:4], 4'b0000})) ;
endmodule
| 7.929651 |
module altpciexpav_stif_reg_fifo #(
parameter FIFO_DEPTH = 5,
parameter DATA_WIDTH = 304
) (
// global signals
input clk,
input rstn,
input srst,
input wrreq,
input rdreq,
input [DATA_WIDTH-1:0] data,
output [DATA_WIDTH-1:0] q,
output reg [ 3:0] fifo_count
);
reg [DATA_WIDTH-1:0] fifo_reg [FIFO_DEPTH-1:0];
wire [FIFO_DEPTH-1:0] fifo_wrreq;
// fifo word counter
always @(posedge clk or negedge rstn) begin
if (~rstn) fifo_count <= 4'h0;
else if (srst) fifo_count <= 4'h0;
else if (rdreq & ~wrreq) fifo_count <= fifo_count - 1;
else if (~rdreq & wrreq) fifo_count <= fifo_count + 1;
end
generate
genvar i;
for (i = 0; i < FIFO_DEPTH - 1; i = i + 1) begin : register_array
assign fifo_wrreq[i] = wrreq & (fifo_count == i | (fifo_count == i + 1 & rdreq));
always @(posedge clk or negedge rstn) begin
if (~rstn) fifo_reg[i] <= {DATA_WIDTH{1'b0}};
else if (srst) fifo_reg[i] <= {DATA_WIDTH{1'b0}};
else if (fifo_wrreq[i]) fifo_reg[i] <= data;
else if (rdreq) fifo_reg[i] <= fifo_reg[i+1];
end
end
endgenerate
/// the last register
assign fifo_wrreq[FIFO_DEPTH-1] = wrreq & (fifo_count == FIFO_DEPTH - 1 | (fifo_count == FIFO_DEPTH & rdreq)) ;
always @(posedge clk or negedge rstn) begin
if (~rstn) fifo_reg[FIFO_DEPTH-1] <= {DATA_WIDTH{1'b0}};
else if (srst) fifo_reg[FIFO_DEPTH-1] <= {DATA_WIDTH{1'b0}};
else if (fifo_wrreq[FIFO_DEPTH-1]) fifo_reg[FIFO_DEPTH-1] <= data;
end
assign q = fifo_reg[0];
endmodule
| 7.929651 |
module altpcie_a10mlab #(
parameter WIDTH = 20,
parameter ADDR_WIDTH = 5,
parameter SIM_EMULATE = 1'b0 // this may not be exactly the same at the fine grain timing level
) (
input wclk,
input wena,
input [ADDR_WIDTH-1:0] waddr_reg,
input [WIDTH-1:0] wdata_reg,
input [ADDR_WIDTH-1:0] raddr,
output [WIDTH-1:0] rdata
);
localparam NUM_WORDS = (1 << ADDR_WIDTH);
genvar i;
generate
if (!SIM_EMULATE) begin
/////////////////////////////////////////////
// hardware cells
for (i = 0; i < WIDTH; i = i + 1) begin : ml
wire wclk_w = wclk; // workaround strange modelsim warning due to cell model tristate
twentynm_mlab_cell lrm (
.clk0(wclk_w),
.ena0(wena),
// synthesis translate off
.clk1(1'b0),
.ena1(1'b1),
.ena2(1'b1),
.clr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
// synthesis translate on
.portabyteenamasks(1'b1),
.portadatain(wdata_reg[i]),
.portaaddr(waddr_reg),
.portbaddr(raddr),
.portbdataout(rdata[i])
);
defparam lrm.mixed_port_feed_through_mode = "dont_care";
defparam lrm.logical_ram_name = "lrm"; defparam lrm.logical_ram_depth = 1 << ADDR_WIDTH;
defparam lrm.logical_ram_width = WIDTH; defparam lrm.first_address = 0;
defparam lrm.last_address = (1 << ADDR_WIDTH) - 1; defparam lrm.first_bit_number = i;
defparam lrm.data_width = 1; defparam lrm.address_width = ADDR_WIDTH;
end
end else begin
/////////////////////////////////////////////
// sim equivalent
reg [WIDTH-1:0] storage[0:NUM_WORDS-1];
integer k = 0;
initial begin
for (k = 0; k < NUM_WORDS; k = k + 1) begin
storage[k] = 0;
end
end
always @(posedge wclk) begin
if (wena) storage[waddr_reg] <= wdata_reg;
end
reg [WIDTH-1:0] rdata_b = 0;
always @(*) begin
rdata_b = storage[raddr];
end
assign rdata = rdata_b;
end
endgenerate
endmodule
| 7.233059 |
module altpcie_avl_stub ( /*AUTOARG*/
// Outputs
m_ChipSelect,
m_Read,
m_Write,
m_BurstCount,
m_ByteEnable,
m_Address,
m_WriteData,
s_WaitRequest,
s_ReadData,
s_ReadDataValid,
// Inputs
m_WaitRequest,
m_ReadData,
m_ReadDataValid,
s_Read,
s_Write,
s_BurstCount,
s_ByteEnable,
s_Address,
s_WriteData
);
output m_ChipSelect;
output m_Read;
output m_Write;
output [5:0] m_BurstCount;
output [15:0] m_ByteEnable;
output [63:0] m_Address;
output [127:0] m_WriteData;
input m_WaitRequest;
input [127:0] m_ReadData;
input m_ReadDataValid;
output s_WaitRequest;
output [127:0] s_ReadData;
output s_ReadDataValid;
input s_Read;
input s_Write;
input [5:0] s_BurstCount;
input [15:0] s_ByteEnable;
input [31:0] s_Address;
input [127:0] s_WriteData;
/*AUTOREG*/
assign m_Address = 0;
assign m_BurstCount = 0;
assign m_ByteEnable = 0;
assign m_ChipSelect = 0;
assign m_Read = 0;
assign m_Write = 0;
assign m_WriteData = 0;
assign s_ReadData = 0;
assign s_ReadDataValid = 0;
assign s_WaitRequest = 0;
endmodule
| 7.00397 |
modules used in PTC CV
module altpcie_hip_bitsync2
#(
parameter DWIDTH = 1, // Sync Data input
parameter RESET_VAL = 0 // Reset value
)
(
input wire clk, // clock
input wire rst_n, // async reset
input wire [DWIDTH-1:0] data_in, // data in
output wire [DWIDTH-1:0] data_out // data out
);
// 2-stage synchronizer
localparam SYNCSTAGE = 2;
// synchronizer
altpcie_hip_bitsync
#(
.DWIDTH(DWIDTH), // Sync Data input
.SYNCSTAGE(SYNCSTAGE), // Sync stages
.RESET_VAL(RESET_VAL) // Reset value
) altpcie_hip_bitsync2
(
.clk(clk), // clock
.rst_n(rst_n), // async reset
.data_in(data_in), // data in
.data_out(data_out) // data out
);
endmodule
| 7.161353 |
module altpcie_hip_bitsync #(
parameter DWIDTH = 1, // Sync Data input
parameter SYNCSTAGE = 2, // Sync stages
parameter RESET_VAL = 0 // Reset value
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire [DWIDTH-1:0] data_in, // data in
output wire [DWIDTH-1:0] data_out // data out
);
// Define wires/regs
reg [(DWIDTH*SYNCSTAGE)-1:0] sync_regs;
wire reset_value;
assign reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0; // To eliminate truncating warning
// Sync Always block
always @(negedge rst_n or posedge clk) begin
if (rst_n == 1'b0) begin
sync_regs[(DWIDTH*SYNCSTAGE)-1:DWIDTH] <= {(DWIDTH * (SYNCSTAGE - 1)) {reset_value}};
end else begin
sync_regs[(DWIDTH*SYNCSTAGE)-1:DWIDTH] <= sync_regs[((DWIDTH*(SYNCSTAGE-1))-1):0];
end
end
// Separated out the first stage of FFs without reset
always @(posedge clk) begin
sync_regs[DWIDTH-1:0] <= data_in;
end
assign data_out = sync_regs[((DWIDTH*SYNCSTAGE)-1):(DWIDTH*(SYNCSTAGE-1))];
endmodule
| 7.8011 |
module is to assist timing closure on TL_CFG bus
//-----------------------------------------------------------------------------
module altpcie_tl_cfg_pipe
(
input clk,
input srst,
output reg [ 3:0] o_tl_cfg_add,
output reg [31:0] o_tl_cfg_ctl,
output reg o_tl_cfg_ctl_wr,
output reg [52:0] o_tl_cfg_sts,
output reg o_tl_cfg_sts_wr,
input [ 3:0] i_tl_cfg_add,
input [31:0] i_tl_cfg_ctl,
input i_tl_cfg_ctl_wr,
input [52:0] i_tl_cfg_sts,
input i_tl_cfg_sts_wr
);
reg sts_wr_r,sts_wr_rr;
reg ctl_wr_r,ctl_wr_rr;
always @ (posedge clk)
begin
if (srst)
begin
o_tl_cfg_add <= 4'h0;
o_tl_cfg_ctl <= {32{1'b0}};
o_tl_cfg_ctl_wr <= {1{1'b0}};
o_tl_cfg_sts <= {53{1'b0}};
o_tl_cfg_sts_wr <= {1{1'b0}};
end
else
begin
// sts pipeline
sts_wr_r <= i_tl_cfg_sts_wr;
sts_wr_rr <= sts_wr_r;
o_tl_cfg_sts_wr <= sts_wr_rr;
if (o_tl_cfg_sts_wr != sts_wr_rr)
o_tl_cfg_sts <= i_tl_cfg_sts;
// ctl pipeline
ctl_wr_r <= i_tl_cfg_ctl_wr;
ctl_wr_rr <= ctl_wr_r;
o_tl_cfg_ctl_wr <= ctl_wr_rr;
if (o_tl_cfg_ctl_wr != ctl_wr_rr)
begin
o_tl_cfg_add <= i_tl_cfg_add;
o_tl_cfg_ctl <= i_tl_cfg_ctl;
end
end
end
endmodule
| 6.759612 |
module altpcie_reset_delay_sync #(
parameter ACTIVE_RESET = 0,
parameter WIDTH_RST = 1,
parameter NODENAME = "altpcie_reset_delay_sync", // Expecting Instance name
parameter LOCK_TIME_CNT_WIDTH = 1
) (
input clk,
input async_rst,
output reg [WIDTH_RST-1:0] sync_rst /* synthesis preserve */
);
wire sync_rst_clk;
localparam SDC = {
"-name SDC_STATEMENT \"set_false_path -from [get_fanins -async *",
NODENAME,
"*rs_meta\[*\]] -to [get_keepers *",
NODENAME,
"*rs_meta\[*\]]\" "
};
(* altera_attribute = SDC *)
reg [2:0] rs_meta = (ACTIVE_RESET==0)?3'b000:3'b111 /* synthesis preserve dont_replicate */;
// synthesis translate_off
initial begin
sync_rst[WIDTH_RST-1:0] = {WIDTH_RST{1'b0}};
$display(
"INFO: altpcie_reset_delay_sync::---------------------------------------------------------------------------------------------");
$display("INFO: altpcie_reset_delay_sync:: NODENAME is %s", NODENAME);
$display("INFO: altpcie_reset_delay_sync:: SDC is %s", SDC);
rs_meta = (ACTIVE_RESET == 0) ? 3'b000 : 3'b111;
end
// synthesis translate_on
always @(posedge clk) begin
sync_rst[WIDTH_RST-1:0] <= {WIDTH_RST{sync_rst_clk}};
end
generate
begin : g_rstsync
if (ACTIVE_RESET == 0) begin : g_rstsync
always @(posedge clk or negedge async_rst) begin
if (!async_rst) rs_meta <= 3'b000;
else rs_meta <= {rs_meta[1:0], 1'b1};
end
if (LOCK_TIME_CNT_WIDTH > 1) begin : g_rstsync1
wire ready_sync = rs_meta[2];
reg [LOCK_TIME_CNT_WIDTH-1:0] cntr = {LOCK_TIME_CNT_WIDTH{1'b0}} /* synthesis preserve */;
assign sync_rst_clk = cntr[LOCK_TIME_CNT_WIDTH-1];
always @(posedge clk) begin
sync_rst[WIDTH_RST-1:0] <= {WIDTH_RST{sync_rst_clk}};
end
always @(posedge clk or negedge ready_sync) begin
if (!ready_sync) cntr <= {LOCK_TIME_CNT_WIDTH{1'b0}};
else if (!sync_rst_clk) cntr <= cntr + 1'b1;
end
end else begin : g_rstsync2
assign sync_rst_clk = rs_meta[2];
end
end else begin : g_rstsync3 // ACTIVE_RESET=1
always @(posedge clk or posedge async_rst) begin
if (async_rst) rs_meta <= 3'b111;
else rs_meta <= {rs_meta[1:0], 1'b0};
end
if (LOCK_TIME_CNT_WIDTH > 1) begin : g_rstsync4
wire ready_sync = rs_meta[2];
wire sync_rst_clkn;
reg [LOCK_TIME_CNT_WIDTH-1:0] cntr = {LOCK_TIME_CNT_WIDTH{1'b0}} /* synthesis preserve */;
assign sync_rst_clk = ~sync_rst_clk;
assign sync_rst_clkn = cntr[LOCK_TIME_CNT_WIDTH-1];
always @(posedge clk or posedge ready_sync) begin
if (ready_sync) cntr <= {LOCK_TIME_CNT_WIDTH{1'b0}};
else if (!sync_rst_clkn) cntr <= cntr + 1'b1;
end
end else begin : g_rstsync5
assign sync_rst_clk = rs_meta[2];
end
end
end
endgenerate
endmodule
| 7.866151 |
module altpcie_rs_a10_hip (
input pld_clk,
input dlup_exit,
input hotrst_exit,
input l2_exit,
input npor_core,
input [4:0] ltssm,
output reg hiprst
);
localparam [4:0] LTSSM_POL = 5'b00010;
localparam [4:0] LTSSM_CPL = 5'b00011;
localparam [4:0] LTSSM_DET = 5'b00000;
localparam [4:0] LTSSM_RCV = 5'b01100;
localparam [4:0] LTSSM_DIS = 5'b10000;
localparam [4:0] LTSSM_DETA = 5'b00001;
localparam [4:0] LTSSM_DETQ = 5'b00000;
reg hiprst_r;
wire npor_sync;
reg dlup_exit_r;
reg exits_r;
reg hotrst_exit_r;
reg l2_exit_r;
reg [4:0] rsnt_cntn;
reg [4:0] ltssm_r;
reg [4:0] ltssm_rr;
//reset Synchronizer
altpcie_reset_delay_sync #(
.ACTIVE_RESET (0),
.WIDTH_RST (1),
.NODENAME ("npor_sync_altpcie_reset_delay_sync_altpcie_rs_a10_hip"),
.LOCK_TIME_CNT_WIDTH(1)
) npor_sync_altpcie_reset_delay_sync_altpcie_rs_a10_hip (
.clk (pld_clk),
.async_rst(npor_core),
.sync_rst (npor_sync)
);
//Reset delay
always @(posedge pld_clk or negedge npor_sync) begin
if (npor_sync == 1'b0) begin
rsnt_cntn <= 5'h0;
end else if (exits_r == 1'b1) begin
rsnt_cntn <= 5'd10;
end else if (rsnt_cntn != 5'd20) begin
rsnt_cntn <= rsnt_cntn + 5'h1;
end
end
//sync and config reset
always @(posedge pld_clk or negedge npor_sync) begin
if (npor_sync == 1'b0) begin
hiprst_r <= 1'b1;
end else begin
if (exits_r == 1'b1) begin
hiprst_r <= 1'b1;
end else if (rsnt_cntn == 5'd20) begin
hiprst_r <= 1'b0;
end
end
end
always @(posedge pld_clk or negedge npor_sync) begin
if (npor_sync == 1'b0) begin
dlup_exit_r <= 1'b1;
hotrst_exit_r <= 1'b1;
l2_exit_r <= 1'b1;
exits_r <= 1'b0;
hiprst <= 1'b1;
ltssm_r <= LTSSM_DETQ;
ltssm_rr <= LTSSM_DETQ;
end else begin
ltssm_r <= ltssm;
ltssm_rr <= ltssm_r;
hiprst <= hiprst_r;
dlup_exit_r <= dlup_exit;
hotrst_exit_r <= hotrst_exit;
l2_exit_r <= l2_exit;
exits_r <= ((l2_exit_r == 1'b0)||(hotrst_exit_r == 1'b0)||(dlup_exit_r == 1'b0)||(ltssm_r == LTSSM_DIS))?1'b1:1'b0;
end
end
endmodule
| 6.599681 |
module altpcie_sc_bitsync_node #(
parameter DWIDTH = 1, // Sync Data input
parameter NODENAME = "altpcie_sc_bitsync_node", // Instance name
parameter SYNCSTAGE = 2, // Sync stages
parameter SDC_TYPE = 0, // 0: Multi Cycle=3, 1:Multi Cycle=2, 2: Set False Path
parameter RESET_VAL = 0 // Reset value
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire [DWIDTH-1:0] data_in, // data in
output wire [DWIDTH-1:0] data_out // data out
);
altpcie_sc_bitsync #(
.DWIDTH (DWIDTH), // Sync Data input
.NODENAME (NODENAME), // Sync stages
.SYNCSTAGE(SYNCSTAGE), // 0: Multi Cycle=3, 1:Multi Cycle=2, 2: Set False Path
.SDC_TYPE (SDC_TYPE), // Instance name
.RESET_VAL(RESET_VAL) // Reset value
) altpcie_sc_bitsync (
.clk (clk), // clock
.rst_n (rst_n), // async reset
.data_in (data_in), // data in
.data_out(data_out) // data out
);
endmodule
| 6.984807 |
module dffp (
q,
clk,
ena,
d,
clrn,
prn
);
input d;
input clk;
input clrn;
input prn;
input ena;
output q;
tri1 prn, clrn, ena;
reg q;
always @(posedge clk or negedge clrn or negedge prn)
if (prn == 1'b0) q <= 1;
else if (clrn == 1'b0) q <= 0;
else begin
if (ena == 1'b1) q <= d;
end
endmodule
| 6.992594 |
module pll_iobuf (
i,
oe,
io,
o
);
input i;
input oe;
inout io;
output o;
reg o;
always @(io) begin
o = io;
end
assign io = (oe == 1) ? i : 1'bz;
endmodule
| 6.54618 |
module MF_pll_reg (
q,
clk,
ena,
d,
clrn,
prn
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q = 0;
always @(posedge clk or negedge clrn or negedge prn) begin
if (prn == 1'b0) q <= 1;
else if (clrn == 1'b0) q <= 0;
else if ((clk == 1) & (ena == 1'b1)) q <= d;
end
endmodule
| 6.578739 |
module arm_m_cntr (
clk,
reset,
cout,
initial_value,
modulus,
time_delay
);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk) begin
if (reset) begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
cout_tmp <= tmp_cout;
end else begin
if (clk_last_value !== clk) begin
if (clk === 1'b1 && first_rising_edge) begin
first_rising_edge = 0;
tmp_cout = clk;
cout_tmp <= #(time_delay) tmp_cout;
end else if (first_rising_edge == 0) begin
if (count < modulus) count = count + 1;
else begin
count = 1;
tmp_cout = ~tmp_cout;
cout_tmp <= #(time_delay) tmp_cout;
end
end
end
end
clk_last_value = clk;
end
and (cout, cout_tmp, 1'b1);
endmodule
| 6.684371 |
module arm_scale_cntr (
clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap
);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg init;
integer count;
integer output_shift_count;
reg cout_tmp;
initial begin
count = 1;
first_rising_edge = 0;
tmp_cout = 0;
output_shift_count = 1;
end
always @(clk or reset) begin
if (init !== 1'b1) begin
clk_last_value = 0;
init = 1'b1;
end
if (reset) begin
count = 1;
output_shift_count = 1;
tmp_cout = 0;
first_rising_edge = 0;
end else if (clk_last_value !== clk) begin
if (mode == " off") tmp_cout = 0;
else if (mode == "bypass") begin
tmp_cout = clk;
first_rising_edge = 1;
end else if (first_rising_edge == 0) begin
if (clk == 1) begin
if (output_shift_count == initial_value) begin
tmp_cout = clk;
first_rising_edge = 1;
end else output_shift_count = output_shift_count + 1;
end
end else if (output_shift_count < initial_value) begin
if (clk == 1) output_shift_count = output_shift_count + 1;
end else begin
count = count + 1;
if (mode == " even" && (count == (high * 2) + 1)) tmp_cout = 0;
else if (mode == " odd" && (count == (high * 2))) tmp_cout = 0;
else if (count == (high + low) * 2 + 1) begin
tmp_cout = 1;
count = 1; // reset count
end
end
end
clk_last_value = clk;
cout_tmp <= tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule
| 6.900873 |
module ttn_m_cntr (
clk,
reset,
cout,
initial_value,
modulus,
time_delay
);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk) begin
if (reset) begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
cout_tmp <= tmp_cout;
end else begin
if (clk_last_value !== clk) begin
if (clk === 1'b1 && first_rising_edge) begin
first_rising_edge = 0;
tmp_cout = clk;
cout_tmp <= #(time_delay) tmp_cout;
end else if (first_rising_edge == 0) begin
if (count < modulus) count = count + 1;
else begin
count = 1;
tmp_cout = ~tmp_cout;
cout_tmp <= #(time_delay) tmp_cout;
end
end
end
end
clk_last_value = clk;
// cout_tmp <= #(time_delay) tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule
| 6.735089 |
module ttn_n_cntr (
clk,
reset,
cout,
modulus
);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk) begin
if (reset) begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
end else begin
if (clk == 1 && clk_last_value !== clk && first_rising_edge) begin
first_rising_edge = 0;
tmp_cout = clk;
end else if (first_rising_edge == 0) begin
if (count < modulus) count = count + 1;
else begin
count = 1;
tmp_cout = ~tmp_cout;
end
end
end
clk_last_value = clk;
end
assign cout = tmp_cout;
endmodule
| 6.545063 |
module ttn_scale_cntr (
clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap
);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg init;
integer count;
integer output_shift_count;
reg cout_tmp;
initial begin
count = 1;
first_rising_edge = 0;
tmp_cout = 0;
output_shift_count = 1;
end
always @(clk or reset) begin
if (init !== 1'b1) begin
clk_last_value = 0;
init = 1'b1;
end
if (reset) begin
count = 1;
output_shift_count = 1;
tmp_cout = 0;
first_rising_edge = 0;
end else if (clk_last_value !== clk) begin
if (mode == " off") tmp_cout = 0;
else if (mode == "bypass") begin
tmp_cout = clk;
first_rising_edge = 1;
end else if (first_rising_edge == 0) begin
if (clk == 1) begin
if (output_shift_count == initial_value) begin
tmp_cout = clk;
first_rising_edge = 1;
end else output_shift_count = output_shift_count + 1;
end
end else if (output_shift_count < initial_value) begin
if (clk == 1) output_shift_count = output_shift_count + 1;
end else begin
count = count + 1;
if (mode == " even" && (count == (high * 2) + 1)) tmp_cout = 0;
else if (mode == " odd" && (count == (high * 2))) tmp_cout = 0;
else if (count == (high + low) * 2 + 1) begin
tmp_cout = 1;
count = 1; // reset count
end
end
end
clk_last_value = clk;
cout_tmp <= tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule
| 6.82995 |
module cda_m_cntr (
clk,
reset,
cout,
initial_value,
modulus,
time_delay
);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk) begin
if (reset) begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
cout_tmp <= tmp_cout;
end else begin
if (clk_last_value !== clk) begin
if (clk === 1'b1 && first_rising_edge) begin
first_rising_edge = 0;
tmp_cout = clk;
cout_tmp <= #(time_delay) tmp_cout;
end else if (first_rising_edge == 0) begin
if (count < modulus) count = count + 1;
else begin
count = 1;
tmp_cout = ~tmp_cout;
cout_tmp <= #(time_delay) tmp_cout;
end
end
end
end
clk_last_value = clk;
// cout_tmp <= #(time_delay) tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule
| 6.852977 |
module cda_n_cntr (
clk,
reset,
cout,
modulus
);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk) begin
if (reset) begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
end else begin
if (clk == 1 && clk_last_value !== clk && first_rising_edge) begin
first_rising_edge = 0;
tmp_cout = clk;
end else if (first_rising_edge == 0) begin
if (count < modulus) count = count + 1;
else begin
count = 1;
tmp_cout = ~tmp_cout;
end
end
end
clk_last_value = clk;
end
assign cout = tmp_cout;
endmodule
| 6.89266 |
module cda_scale_cntr (
clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap
);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg init;
integer count;
integer output_shift_count;
reg cout_tmp;
initial begin
count = 1;
first_rising_edge = 0;
tmp_cout = 0;
output_shift_count = 1;
end
always @(clk or reset) begin
if (init !== 1'b1) begin
clk_last_value = 0;
init = 1'b1;
end
if (reset) begin
count = 1;
output_shift_count = 1;
tmp_cout = 0;
first_rising_edge = 0;
end else if (clk_last_value !== clk) begin
if (mode == " off") tmp_cout = 0;
else if (mode == "bypass") begin
tmp_cout = clk;
first_rising_edge = 1;
end else if (first_rising_edge == 0) begin
if (clk == 1) begin
if (output_shift_count == initial_value) begin
tmp_cout = clk;
first_rising_edge = 1;
end else output_shift_count = output_shift_count + 1;
end
end else if (output_shift_count < initial_value) begin
if (clk == 1) output_shift_count = output_shift_count + 1;
end else begin
count = count + 1;
if (mode == " even" && (count == (high * 2) + 1)) tmp_cout = 0;
else if (mode == " odd" && (count == (high * 2))) tmp_cout = 0;
else if (count == (high + low) * 2 + 1) begin
tmp_cout = 1;
count = 1; // reset count
end
end
end
clk_last_value = clk;
cout_tmp <= tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule
| 6.742481 |
module cycloneiiigl_post_divider (
clk,
reset,
cout
);
// PARAMETER
parameter dpa_divider = 1;
// INPUT PORTS
input clk;
input reset;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
integer modulus;
initial begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
modulus = (dpa_divider == 0) ? 1 : dpa_divider;
end
always @(reset or clk) begin
if (reset) begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
end else begin
if (clk == 1 && clk_last_value !== clk && first_rising_edge) begin
first_rising_edge = 0;
tmp_cout = clk;
end else if (first_rising_edge == 0) begin
if (count < modulus) count = count + 1;
else begin
count = 1;
tmp_cout = ~tmp_cout;
end
end
end
clk_last_value = clk;
end
assign cout = tmp_cout;
endmodule
| 7.203778 |
module altpll_wb_clkgen #(
parameter DEVICE_FAMILY = "",
parameter INPUT_FREQUENCY = 50,
parameter WB_DIVIDE_BY = 1,
parameter WB_MULTIPLY_BY = 1,
parameter SDRAM_DIVIDE_BY = 1,
parameter SDRAM_MULTIPLY_BY = 1
) (
// Main clocks in, depending on board
input sys_clk_pad_i,
// Asynchronous, active low reset in
input rst_n_pad_i,
// Input reset - through a buffer, asynchronous
output async_rst_o,
// Wishbone clock and reset out
output wb_clk_o,
output wb_rst_o,
// Main memory clocks
output sdram_clk_o,
output sdram_rst_o
);
// First, deal with the asychronous reset
wire async_rst;
wire async_rst_n;
assign async_rst_n = rst_n_pad_i;
assign async_rst = ~async_rst_n;
// Everyone likes active-high reset signals...
assign async_rst_o = ~async_rst_n;
// An active-low synchronous reset signal (usually a PLL lock signal)
wire sync_rst_n;
wire pll_lock;
wrapped_altpll #(
.DEVICE_FAMILY(DEVICE_FAMILY),
.INPUT_FREQUENCY(INPUT_FREQUENCY),
.C0_DIVIDE_BY(WB_DIVIDE_BY),
.C0_MULTIPLY_BY(WB_MULTIPLY_BY),
.C1_DIVIDE_BY(SDRAM_DIVIDE_BY),
.C1_MULTIPLY_BY(SDRAM_MULTIPLY_BY)
) wrapped_altpll (
.areset(async_rst),
.inclk0(sys_clk_pad_i),
.c0(wb_clk_o),
.c1(sdram_clk_o),
.locked(pll_lock)
);
assign sync_rst_n = pll_lock;
// Reset generation for wishbone
reg [15:0] wb_rst_shr;
always @(posedge wb_clk_o or posedge async_rst)
if (async_rst) wb_rst_shr <= 16'hffff;
else wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
assign wb_rst_o = wb_rst_shr[15];
// Reset generation for sdram
reg [15:0] sdram_rst_shr;
always @(posedge sdram_clk_o or posedge async_rst)
if (async_rst) sdram_rst_shr <= 16'hffff;
else sdram_rst_shr <= {sdram_rst_shr[14:0], ~(sync_rst_n)};
assign sdram_rst_o = sdram_rst_shr[15];
endmodule
| 7.787885 |
module of the DDL links
//* Author/Designer : Zhang.Fan (fanzhang.ccnu@gmail.com)
//*
//* Revision history:
//* 06-03-2013 : Add ALTRO command handshaking (acmd_ack)
//* 02-25-04-2013 : Add ALTRO command handshaking (acmd_ack)
//*******************************************************************************
//`timescale 1ns / 1ps
module altro_top(
input rdoclk,
//altro bus
inout [39:0] bd,
output writen,
output cstbn,
input ackn,
input trsfn,
input dstbn,
//altro command interface
input acmd_exec,
input acmd_rw,
input [19:0] acmd_addr,
input [19:0] acmd_rx,
output [19:0] acmd_tx,
output acmd_ack,
//dtc edata interface
input fifo_rdreq,
output [31:0] fifo_q,
output fifo_empty,
//readout command
input altrordo_cmd, //
input altroabort_cmd, //
//configuration
input [31:0] altrochmask,
input [4:0] fee_addr,
input LGSEN,
output [31:0] HGOverFlag,
output [15:0] ErrALTROCmd,
output [15:0] ErrALTRORdo,
input ErrClr,
input reset
);
//internal wires
wire ram_addrclr;
wire con_busy;
wire altro_chrdo_en;
wire fifo_almost_full;
wire FlagClear;
wire fifo_wren;
wire Dflag;
wire [1:0] DHeader;
wire [6:0] ChAddr;
altro_if u_altro_if (
.rdoclk(rdoclk),
//altro bus
.bd(bd),
.writen(writen),
.cstbn(cstbn),
.ackn(ackn),
.trsfn(trsfn),
//altro command interface
.acmd_exec(acmd_exec),
.acmd_rw(acmd_rw),
.acmd_addr(acmd_addr),
.acmd_rx(acmd_rx),
.acmd_tx(acmd_tx),
.acmd_ack(acmd_ack),
//configuration
.altrochmask(altrochmask),
.fee_addr(fee_addr),
.altrordo_cmd(altrordo_cmd),
.altroabort_cmd(altroabort_cmd),
//internal wires
.fifo_almost_full(fifo_almost_full),
.altro_chrdo_en(altro_chrdo_en),
.ram_addrclr(ram_addrclr),
.con_busy(con_busy),
.altrochmask_LG(HGOverFlag),
.ErrALTROCmd(ErrALTROCmd),
.ErrALTRORdo(ErrALTRORdo),
.ErrClr(ErrClr),
.reset(reset)
);
fed_build u_fed_build (
.rdoclk(rdoclk),
//altro bus
.bd(bd),
.trsfn(trsfn),
.dstbn(dstbn),
.FlagClear(FlagClear),
.fifo_wren(fifo_wren),
.Dflag(Dflag),
.DHeader(DHeader),
.ChAddr(ChAddr),
//dtc edata interface
.fifo_rdreq(fifo_rdreq),
.fifo_q(fifo_q),
.fifo_empty(fifo_empty),
//internal wires
.fifo_almost_full(fifo_almost_full),
.altro_chrdo_en(altro_chrdo_en),
.ram_addrclr(ram_addrclr),
.con_busy(con_busy),
.reset(reset)
);
LGFlagModule ULGFlagModule (
.rdoclk(rdoclk),
.FlagClear(FlagClear),
.fifo_wren(fifo_wren),
.Dflag(Dflag),
.DHeader(DHeader),
.ChAddr(ChAddr),
.LGSEN(LGSEN),
.OverflowFlag(HGOverFlag),
.reset(reset)
);
endmodule
| 7.294035 |
module altr_hps_and (
input wire and_in1, // and input 1
input wire and_in2, // and input 2
output wire and_out // and output
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign and_out = and_in1 & and_in2;
`else
`endif
endmodule
| 7.049869 |
module altr_hps_bin2gray (
bin_in,
gray_out
);
input [2:0] bin_in;
output [2:0] gray_out;
reg [2:0] gray_out;
always @(*) begin // 3 bit gray code
case (bin_in)
3'b000: gray_out = 3'b000;
3'b001: gray_out = 3'b001;
3'b010: gray_out = 3'b011;
3'b011: gray_out = 3'b010;
3'b100: gray_out = 3'b110;
3'b101: gray_out = 3'b111;
3'b110: gray_out = 3'b101;
3'b111: gray_out = 3'b100;
default: gray_out = 3'b000;
endcase
end
endmodule
| 6.592632 |
module altr_hps_bitsync #(
parameter DWIDTH = 1'b1, // Sync Data input
//parameter SYNCSTAGE = 2, // Sync stages
parameter RESET_VAL = 1'b0 // Reset value
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire [DWIDTH-1:0] data_in, // data in
output wire [DWIDTH-1:0] data_out // data out
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
// End users may pass in RESET_VAL with a width exceeding 1 bit
// Evaluate the value first and use 1 bit value
localparam RESET_VAL_1B = (RESET_VAL == 'd0) ? 1'b0 : 1'b1;
reg [DWIDTH-1:0] dff2;
reg [DWIDTH-1:0] dff1;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
dff2 <= {DWIDTH{RESET_VAL_1B}};
dff1 <= {DWIDTH{RESET_VAL_1B}};
end else begin
dff2 <= dff1;
dff1 <= data_in;
end
// data_out has to be a wire since it needs to also hook up to the TSMC cell
assign data_out = dff2;
`else
`endif
endmodule
| 10.098234 |
module altr_hps_bitsync4 #(
parameter DWIDTH = 1'b1, // Sync Data input
//parameter SYNCSTAGE = 4, // Sync stages
parameter RESET_VAL = 1'b0 // Reset value
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire [DWIDTH-1:0] data_in, // data in
output wire [DWIDTH-1:0] data_out // data out
);
`ifdef ALTR_HPS_INTEL_MACROS_OFF
// End users may pass in RESET_VAL with a width exceeding 1 bit
// Evaluate the value first and use 1 bit value
localparam RESET_VAL_1B = (RESET_VAL == 'd0) ? 1'b0 : 1'b1;
reg [DWIDTH-1:0] dff4;
reg [DWIDTH-1:0] dff3;
reg [DWIDTH-1:0] dff2;
reg [DWIDTH-1:0] dff1;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
dff4 <= {DWIDTH{RESET_VAL_1B}};
dff3 <= {DWIDTH{RESET_VAL_1B}};
dff2 <= {DWIDTH{RESET_VAL_1B}};
dff1 <= {DWIDTH{RESET_VAL_1B}};
end else begin
dff4 <= dff3;
dff3 <= dff2;
dff2 <= dff1;
dff1 <= data_in;
end
// data_out has to be a wire since it needs to also hook up to the TSMC cell
assign data_out = dff4;
`else
`endif
endmodule
| 10.098234 |
module altr_hps_bitsync_generator #(
parameter DWIDTH = 1,
parameter [DWIDTH-1:0] RESET_VAL = 'd0
) (
input wire clk, //clock
input wire rst_n, //async reset
input wire [DWIDTH-1:0] data_in, //data in
output wire [DWIDTH-1:0] data_out //data out
);
genvar i;
generate
for (i = 0; i < DWIDTH; i = i + 1) begin : bit_sync_i
if (RESET_VAL[i] == 1'b0) begin
altr_hps_bitsync #(
.DWIDTH(1),
.RESET_VAL(1'b0)
) bitsync_clr_inst (
.clk(clk),
.rst_n(rst_n),
.data_in(data_in[i]),
.data_out(data_out[i])
);
end else begin
altr_hps_bitsync #(
.DWIDTH(1),
.RESET_VAL(1'b1)
) bitsync_pst_inst (
.clk(clk),
.rst_n(rst_n),
.data_in(data_in[i]),
.data_out(data_out[i])
);
end
end //end for
endgenerate // endgenerate
endmodule
| 10.098234 |
module altr_hps_ckand (
input wire and_in1, // and input 1
input wire and_in2, // and input 2
output wire and_out // and output
);
// -------------------
// Port declarations
// -------------------
wire and_out_n;
// -----
// RTL
// -----
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign and_out = and_in1 & and_in2;
`else
`endif
endmodule
| 7.068816 |
module altr_hps_ckand_gate (
input wire and_clk, // and input 1
input wire and_en, // and input 2
output wire and_out // and output
);
// -------------------
// Port declarations
// -------------------
// -----
// RTL
// -----
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign and_out = and_clk & and_en;
`else
`endif
endmodule
| 7.068816 |
module altr_hps_cknand (
input wire nand_in1, // and input 1
input wire nand_in2, // and input 2
output wire nand_out // and output
);
// -------------------
// Port declarations
// -------------------
// -----
// RTL
// -----
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign nand_out = ~(nand_in1 & nand_in2);
`else
`endif
endmodule
| 7.060948 |
module altr_hps_cknor (
input wire nor_in1, // or input 1
input wire nor_in2, // or input 2
output wire nor_out // or output
);
// -------------------
// Port declarations
// -------------------
// -----
// RTL
// -----
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign nor_out = ~(nor_in1 | nor_in2);
`else
`endif
endmodule
| 7.549032 |
module altr_hps_ckor (
input wire or_in1, // or input 1
input wire or_in2, // or input 2
output wire or_out // or output
);
// -------------------
// Port declarations
// -------------------
// -----
// RTL
// -----
wire or_out_n;
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign or_out = or_in1 | or_in2;
`else
`endif
endmodule
| 7.916579 |
module altr_hps_ckor_gate (
input wire or_clk, // or input 1
input wire or_en, // or input 2
output wire or_out // or output
);
// -------------------
// Port declarations
// -------------------
// -----
// RTL
// -----
`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign or_out = or_clk | or_en;
`else
`endif
endmodule
| 7.916579 |
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