code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module altera_avalon_jtag_uart_2pkhqydp_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input... | 7.767945 |
module altera_avalon_jtag_uart_2pkhqydp_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input... | 7.767945 |
module altera_avalon_jtag_uart_2pkhqydp_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n... | 7.767945 |
module altera_avalon_jtag_uart_2pkhqydp_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
inpu... | 7.767945 |
module altera_avalon_jtag_uart_nbmdwotd_log_module (
// inputs:
clk,
data,
strobe,
valid
);
input clk;
input [7:0] data;
input strobe;
input valid;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
reg [31:0] text_handle; // for $fopen
initial text_handle = $fop... | 7.767945 |
module altera_avalon_jtag_uart_nbmdwotd_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input... | 7.767945 |
module altera_avalon_jtag_uart_nbmdwotd_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input... | 7.767945 |
module altera_avalon_jtag_uart_nbmdwotd_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [9:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n... | 7.767945 |
module altera_avalon_jtag_uart_nbmdwotd_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [9:0] rfifo_used;
inpu... | 7.767945 |
module altera_avalon_lcd_16207_6pcwkhmx (
// inputs:
address,
begintransfer,
read,
write,
writedata,
// outputs:
LCD_E,
LCD_RS,
LCD_RW,
LCD_data,
readdata
);
output LCD_E;
output LCD_RS;
output LCD_RW;
inout [7:0] LCD_data;
output [7:0] readdata;
input [1:0]... | 7.767945 |
module altera_avalon_onchip_memory2_4y7nc2pu (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
);
output [31:0] readdata;
input [15:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken... | 7.767945 |
module altera_avalon_onchip_memory2_mejd6mmm (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
);
output [31:0] readdata;
input [14:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken... | 7.767945 |
module altera_avalon_onchip_memory2_try7plvj (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
);
output [31:0] readdata;
input [15:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken... | 7.767945 |
module fifo_buffer_single_clock_fifo (
// inputs:
aclr,
clock,
data,
rdreq,
wrreq,
// outputs:
empty,
full,
q
);
parameter FIFO_DEPTHS = 2;
parameter FIFO_WIDTHU = 1;
output empty;
output full;
output [35:0] q;
input aclr;
input clock;
input [35:0] data;
inpu... | 6.571683 |
module fifo_buffer_scfifo_with_controls (
// inputs:
clock,
data,
rdreq,
reset_n,
wrreq,
// outputs:
empty,
full,
q
);
parameter FIFO_DEPTHS = 2;
parameter FIFO_WIDTHU = 1;
output empty;
output full;
output [35:0] q;
input clock;
input [35:0] data;
input rdreq;... | 6.571683 |
module fifo_buffer (
// inputs:
avalonmm_read_slave_read,
avalonmm_write_slave_write,
avalonmm_write_slave_writedata,
reset_n,
wrclock,
// outputs:
avalonmm_read_slave_readdata,
avalonmm_read_slave_waitrequest,
avalonmm_write_slave_waitrequest
);
parameter FIFO_DEPTHS = 2;
... | 8.171221 |
module altera_avalon_packets_to_master_inst_for_spichain (
// inputs:
clk,
in_data,
in_endofpacket,
in_startofpacket,
in_valid,
out_ready,
readdata,
readdatavalid,
reset_n,
waitrequest,
// outputs:
address,
byteenable,
in_ready,
out_data,
out_endofpac... | 7.767945 |
module altera_avalon_pio_342yz4ye (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output out_port;
output readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input writed... | 7.767945 |
module altera_avalon_pio_4lxvnb4y (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [17:0] out_port;
output [17:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
... | 7.767945 |
module altera_avalon_pio_5mxhwzsf (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
);
output irq;
output [3:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input [3:0] in_port;
input reset_n;... | 7.767945 |
module altera_avalon_pio_brhxffyx (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [7:0] out_port;
output [7:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
... | 7.767945 |
module altera_avalon_pio_kazrjara (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
bidir_port,
readdata
);
inout bidir_port;
output readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input wri... | 7.767945 |
module altera_avalon_pio_kxgghky6 (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output readdata;
input [1:0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg readdata;
assign clk_en = 1;
//s1,... | 7.767945 |
module altera_avalon_pio_t23333bf (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [8:0] out_port;
output [8:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
... | 7.767945 |
module altera_avalon_pio_vuxkmkdz (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
bidir_port,
readdata
);
inout [3:0] bidir_port;
output [3:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;... | 7.767945 |
module altera_avalon_st_bytes_to_packets_inst_for_spichain (
// inputs:
clk,
in_data,
in_valid,
out_ready,
reset_n,
// outputs:
in_ready,
out_channel,
out_data,
out_endofpacket,
out_startofpacket,
out_valid
);
output in_ready;
output [7:0] out_channel;
output ... | 7.767945 |
module altera_avalon_st_clock_crosser (
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2... | 7.767945 |
module altera_avalon_st_idle_inserter (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7:0] in_data,
// Interface: ST out
input out_ready,
output reg out_v... | 7.767945 |
module altera_avalon_st_idle_remover (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7:0] in_data,
// Interface: ST out
input out_ready,
output reg out_va... | 7.767945 |
module altera_avalon_st_packets_to_bytes_inst_for_spichain (
// inputs:
clk,
in_channel,
in_data,
in_endofpacket,
in_startofpacket,
in_valid,
out_ready,
reset_n,
// outputs:
in_ready,
out_data,
out_valid
);
output in_ready;
output [7:0] out_data;
output out_va... | 7.767945 |
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input cl... | 7.767945 |
module altera_avalon_sysid_qsys #(
parameter ID_VALUE = 1,
parameter TIMESTAMP = 1
) (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalo... | 7.767945 |
module altera_avalon_sysid_qsys_cnhypnam (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 0 : 0;
endmodu... | 7.767945 |
module altera_avalon_sysid_qsys_exz7b53s (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 0 : 0;
endmodu... | 7.767945 |
module altera_avalon_throughput_monitor #(
parameter BC_W = 5
) (
input avs_clock,
input if_clock,
input avs_reset,
input if_reset,
input if_read,
input if_write,
input [BC_W-1:0] if_burstcount,
input if_waitrequest,
input if_readdatav... | 7.767945 |
module altera_avalon_uart_5tcpgvvj_log_module (
// inputs:
clk,
data,
strobe,
valid
);
input clk;
input [7:0] data;
input strobe;
input valid;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
reg [31:0] text_handle; // for $fopen
initial text_handle = $fopen("a... | 7.767945 |
module altera_avalon_uart_5tcpgvvj_rx_stimulus_source (
// inputs:
baud_divisor,
clk,
clk_en,
reset_n,
rx_char_ready,
rxd,
// outputs:
source_rxd
);
output source_rxd;
input [8:0] baud_divisor;
input clk;
input clk_en;
input reset_n;
input rx_char_ready;
input rxd;
... | 7.767945 |
module altera_dcfifo_synchronizer_bundle (
clk,
reset_n,
din,
dout
);
parameter WIDTH = 1;
parameter DEPTH = 3;
input clk;
input reset_n;
input [WIDTH-1:0] din;
output [WIDTH-1:0] dout;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : sync
altera_std_synchronizer... | 6.996057 |
module altera_dpram (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock_a;
input clock_b;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] ... | 7.657338 |
module altera_dpram (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b
);
input [11:0] address_a;
input [11:0] address_b;
input clock_a;
input clock_b;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output ... | 7.657338 |
module altera_dual_boot (
clk,
nreset,
avmm_rcv_address,
avmm_rcv_writedata,
avmm_rcv_write,
avmm_rcv_read,
avmm_rcv_readdata
);
parameter LPM_TYPE = "ALTERA_DUAL_BOOT";
parameter INTENDED_DEVICE_FAMILY = "MAX 10 FPGA";
parameter A_WIDTH = 3;
parameter WD_WIDTH = 4;
parameter RD_WI... | 7.042424 |
module altera_dual_port_ram_simple #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 10
) (
input clk,
input write_enable,
input [ADDR_WIDTH-1:0] write_addr,
input [ADDR_WIDTH-1:0] read_addr,
input [DATA_WIDTH-1:0] data_in,
output [DATA_WIDTH-1:0] data_out
... | 8.9788 |
module altera_edge_detector #(
parameter PULSE_EXT = 0, // 0, 1 = edge detection generate single cycle pulse, >1 = pulse extended for specified clock cycle
parameter EDGE_TYPE = 0, // 0 = falling edge, 1 or else = rising edge
parameter IGNORE_RST_WHILE_BUSY = 0 // 0 = module internal reset will be default... | 8.376436 |
module altera_eth_fifo_pause_ctrl_adapter (
//global
clk,
reset,
//Almost full Data Sink
data_sink_almost_full,
//Almost empty Data Sink
data_sink_almost_empty,
//Av-ST Data Source
pause_ctrl_src_data
);
// =head2 Clock and reset interface
input clk;
input reset;
// =h... | 6.608189 |
module altera_eth_loopback (
clk,
reset_n,
// sink
in_data_0,
in_valid_0,
in_ready_0,
in_startofpacket_0,
in_endofpacket_0,
in_empty_0,
in_error_0,
// sink
in_data_1,
in_valid_1,
in_ready_1,
in_startofpacket_1,
in_endofpacket_1,
in_empty_1,
in_er... | 7.328425 |
module altera_eth_tse_ptp_std_synchronizer #(
parameter width = 1,
parameter depth = 3
) (
input clk,
input reset_n,
input [width-1:0] din,
output [width-1:0] dout
);
genvar i;
generate
for (i = 0; i < width; i = i + 1) begin : nocut_sync
altera_std_synchronizer_nocut #(
... | 6.792487 |
module altera_eth_tse_std_synchronizer #(
parameter depth = 3
) (
input clk,
input reset_n,
input din,
output dout
);
altera_std_synchronizer_nocut #(
.depth(depth)
) std_sync_no_cut (
.clk (clk),
.reset_n(reset_n),
.din (din),
.dout (dout)
);
endmodu... | 6.792487 |
module altera_eth_tse_std_synchronizer_bundle (
clk,
reset_n,
din,
dout
);
// GLOBAL PARAMETER DECLARATION
parameter width = 1;
parameter depth = 3;
// INPUT PORT DECLARATION
input clk;
input reset_n;
input [width-1:0] din;
// OUTPUT PORT DECLARATION
output [width-1:0] dout;
gener... | 6.792487 |
module altera_gtr_clock_gate (
input clk,
input rst_n,
input en,
output clk_gated
);
reg en_flp;
always @(negedge clk or negedge rst_n) begin
if (!rst_n) en_flp <= 1'b0;
else en_flp <= en;
end
assign clk_gated = clk & en_flp;
endmodule
| 7.248689 |
module altera_gtr_clock_mux (
input inclk0,
input rst0_n,
input inclk1,
input rst1_n,
input clksel,
// Disable C104 rule check
// outclk is a generated clock
output outclk /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"C104\"" */
);
reg clksel0_sync_dly;
reg clkse... | 7.248689 |
module altera_gtr_mac_speed_filter (
input clk,
input rst_n,
input [1:0] mac_speed,
output reg [1:0] mac_speed_filtered
);
wire [1:0] mac_speed_sync;
wire update_speed;
wire speed_change_det;
reg speed_change_det_1;
reg speed_change_det_2... | 9.511213 |
module altera_gtr_pipeline_stage #(
parameter DATA_WIDTH = 1
) (
input clk,
input rst_n,
input [DATA_WIDTH-1:0] datain,
output reg [DATA_WIDTH-1:0] dataout
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) dataout <= {DATA_WIDTH{1'b0}};
else d... | 7.795267 |
module altera_gtr_reset_synchronizer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R105\"" */ ( // Disable R105 rule check. This module itself is a reset synchronizer.
input clk,
input rst_n,
output rst_sync_n
);
reg din_sync_1;
reg din_sync_2;
always @(posedge clk or negedge rst_n... | 7.291479 |
module lcell_counter_remap #(
//parameter
parameter family = "Arria 10",
parameter lut_mask = 64'hAAAAAAAAAAAAAAAA,
parameter dont_touch = "on"
) (
input wire dataa,
input wire datab,
input wire datac,
input wire datad,
output wire combout
);
wire gnd /*synthesis keep*/... | 7.012093 |
module altera_irq_bridge
#(
parameter IRQ_WIDTH = 32
)
(
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset,
input [IRQ_WIDTH - 1:0] receiver_irq,
o... | 8.239488 |
module is a simple clock crosser for control signals. It will take
// the asynchronous control signal and synchronize it to the clk domain
// attached to the clk input. It does so by passing the control signal
// through a pair of registers and then sensing the level transition from
// either hi-to-lo or lo-to-hi. *ATT... | 7.514223 |
module crosses the clock domain for a given source
module altera_jtag_src_crosser (
sink_clk,
sink_reset_n,
sink_valid,
sink_data,
src_clk,
src_reset_n,
src_valid,
src_data
);
parameter WIDTH = 8;
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
input ... | 6.867545 |
module altera_jtag_uart #(
parameter SIM_BUFFER_SIZE =100,
parameter SIM_WAIT_COUNT =1000
)(
reset,
clk,
irq,
s_dat_i,
s_sel_i,
s_addr_i,
s_cti_i,
s_stb_i,
s_cyc_i,
s_we_i,
s_dat_o,
s_ack_o,
RxD_din_sim,
RxD_wr_sim,
RxD_ready_sim
... | 6.505063 |
module altera_jtag_uart_wb_hw (
input clk,
rst,
output wb_irq,
output [31:0] dat_o,
output ack_o,
input adr_i,
input stb_i,
input cyc_i,
input we_i,
input [31:0] dat_i,
output dataavailable,
output ready... | 6.505063 |
module altera_jtag_uart_wb (
input clk,
rst,
output wb_irq,
output [31:0] dat_o,
output ack_o,
input adr_i,
input stb_i,
input cyc_i,
input we_i,
input [31:0] dat_i,
output dataavailable,
output readyfor... | 6.505063 |
module dffp (
q,
clk,
ena,
d,
clrn,
prn
);
input d;
input clk;
input clrn;
input prn;
input ena;
output q;
tri1 prn, clrn, ena;
reg q;
always @(posedge clk or negedge clrn or negedge prn)
if (prn == 1'b0) q <= 1;
else if (clrn == 1'b0) q <= 0;
else begin
i... | 6.992594 |
module pll_iobuf (
i,
oe,
io,
o
);
input i;
input oe;
inout io;
output o;
reg o;
always @(io) begin
o = io;
end
assign io = (oe == 1) ? i : 1'bz;
endmodule
| 6.54618 |
module MF_pll_reg (
q,
clk,
ena,
d,
clrn,
prn
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q = 0;
always @(posedge clk ... | 6.578739 |
module arm_m_cntr (
clk,
reset,
cout,
initial_value,
modulus,
time_delay
);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tm... | 6.684371 |
module arm_scale_cntr (
clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap
);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// IN... | 6.900873 |
module ttn_m_cntr (
clk,
reset,
cout,
initial_value,
modulus,
time_delay
);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tm... | 6.735089 |
module ttn_n_cntr (
clk,
reset,
cout,
modulus
);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial begin
... | 6.545063 |
module ttn_scale_cntr (
clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap
);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// IN... | 6.82995 |
module cda_m_cntr (
clk,
reset,
cout,
initial_value,
modulus,
time_delay
);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tm... | 6.852977 |
module cda_n_cntr (
clk,
reset,
cout,
modulus
);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial begin
... | 6.89266 |
module cda_scale_cntr (
clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap
);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// IN... | 6.742481 |
module cycloneiiigl_post_divider (
clk,
reset,
cout
);
// PARAMETER
parameter dpa_divider = 1;
// INPUT PORTS
input clk;
input reset;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp... | 7.203778 |
module stratix_lvds_rx (
rx_in, // input serial data
rx_fastclk, // fast clock from pll
rx_enable0,
rx_enable1,
rx_out // deserialized output data
);
// GLOBAL PARAMETER DECLARATION
parameter number_of_channels = 1;
parameter deserialization_factor = 4;
// LOCAL PARAMETER DECLARATION
... | 6.621821 |
module is used to generate the local loaden signal from fast clock for StratixV
// family. To mimic local clock divider block.
// Limitation : Only available STRATIX V family.
//
// Results expected: Loaden signal
//
//END_MODULE_NAME-----------------------------------------------------------... | 6.574716 |
module is used to generate the tx_outclock for Stratix
// family.
// Limitation : Only available STRATIX family.
//
// Results expected: Output clock.
//
//END_MODULE_NAME----------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
module st... | 6.574716 |
module is used to generate the tx_outclock for StratixII
// family.
// Limitation : Only available STRATIX II family.
//
// Results expected: Output clock.
//
//END_MODULE_NAME----------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
modu... | 6.574716 |
module dcfifo_dffpipe (
d,
clock,
aclr,
q
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_delay = 1;
parameter lpm_width = 64;
// LOCAL PARAMETER DECLARATION
parameter delay = (lpm_delay < 2) ? 1 : lpm_delay - 1;
// INPUT PORT DECLARATION
input [lpm_width-1:0] d;
input clock;
input... | 8.172252 |
module dcfifo_fefifo (
usedw_in,
wreq,
rreq,
clock,
aclr,
empty,
full
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_widthad = 1;
parameter lpm_numwords = 1;
parameter underflow_checking = "ON";
parameter overflow_checking = "ON";
parameter lpm_mode = "READ";
// INPUT PORT ... | 6.754214 |
module dcfifo ( data, rdclk, wrclk, aclr, rdreq, wrreq,
rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_widthu = 1;
parameter lpm_numwords = 2;
parameter delay_rdusedw = 1;
parameter delay_wrusedw = 1;
... | 7.370534 |
module altshift_taps (
shiftin,
clock,
clken,
aclr,
shiftout,
taps
);
// PARAMETER DECLARATION
parameter number_of_taps = 4; // Specifies the number of regularly spaced
// taps along the shift register
parameter tap_distance = 3; // Specifies the distan... | 7.397161 |
module altsquare (
data,
clock,
ena,
aclr,
result
);
// GLOBAL PARAMETER DECLARATION
parameter data_width = 1;
parameter result_width = 1;
parameter pipeline = 0;
parameter representation = "UNSIGNED";
parameter result_alignment = "LSB";
parameter lpm_hint = "UNUSED";
parameter lpm_... | 7.030281 |
module altera_std_synchronizer (
clk,
reset_n,
din,
dout
);
// GLOBAL PARAMETER DECLARATION
parameter depth = 3; // This value must be >= 2 !
// INPUT PORT DECLARATION
input clk;
input reset_n;
input din;
// OUTPUT PORT DECLARATION
output dout;
// QuartusII synthesis directives... | 7.854645 |
module altera_std_synchronizer_bundle (
clk,
reset_n,
din,
dout
);
// GLOBAL PARAMETER DECLARATION
parameter width = 1;
parameter depth = 3;
// INPUT PORT DECLARATION
input clk;
input reset_n;
input [width-1:0] din;
// OUTPUT PORT DECLARATION
output [width-1:0] dout;
generate
... | 7.854645 |
module alt_cal_sv (
busy,
clock,
dprio_addr,
dprio_busy,
dprio_datain,
dprio_dataout,
dprio_rden,
dprio_wren,
quad_addr,
remap_addr,
reset,
start,
testbuses
) /* synthesis synthesis_clearbox=1 */;
parameter number_of_channels = 1;
parameter channel_address_width... | 6.528521 |
module alt_cal_av (
busy,
clock,
dprio_addr,
dprio_busy,
dprio_datain,
dprio_dataout,
dprio_rden,
dprio_wren,
quad_addr,
remap_addr,
reset,
start,
testbuses
) /* synthesis synthesis_clearbox=1 */;
parameter number_of_channels = 1;
parameter channel_address_width... | 6.668376 |
module alt_aeq_s4 #(
parameter show_errors = "NO", // "YES" = show errors; anything else = do not show errors
parameter radce_hflck = 15'h0000, // settings for RADCE_HFLCK CRAM settings - get values from ICD
parameter radce_lflck = 15'h0000, // settings for RADCE_LFLCK CRAM settings - get values from ICD
... | 7.856784 |
module sld_virtual_jtag_basic (
jtag_state_sdr,
jtag_state_sirs,
ir_out,
jtag_state_sir,
jtag_state_cdr,
jtag_state_e2dr,
tms,
jtag_state_sdrs,
jtag_state_tlr,
ir_in,
virtual_state_sdr,
tdi,
jtag_state_uir,
jtag_state_cir,
virtual_state_cdr,
virtual_state_... | 6.971215 |
module altsource_probe (
jtag_state_sdr,
ir_in,
jtag_state_cir,
jtag_state_udr,
jtag_state_e1dr,
source_clk,
probe,
source,
ir_out,
jtag_state_cdr,
jtag_state_tlr,
tdi,
jtag_state_uir,
source_ena,
tdo,
clrn,
raw_tck,
usr1,
ena
);
parameter l... | 8.012029 |
module altera_mgmt_reset (
input clk,
input reset,
input mgmt_data,
input mgmt_valid,
output mgmt_ready,
output reg agent_reset
);
//reset (the input) forces agent_reset active (high) immediately
//system console strobes 1 (data & valid both 1) to enable reset
//or... | 6.656785 |
module altera_modular_adc_conduit_splitter (
input clk,
input rst_n,
input clk_in_pll_locked,
output clk_in_pll_locked_out_1,
output clk_in_pll_locked_out_2
);
//-----------------------------------------------------------------------------//
// This core is specifically for splitter adc pll... | 6.935893 |
module altera_modular_adc_control_avrg_fifo (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q
);
input clock;
input [11:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [11:0] q;
wire sub_wire0;
wire sub_wire1;
wire [11:0] sub_wire2... | 6.935893 |
module altera_modular_adc_dual_sync (
input clk,
input rst_n,
input sync_1_valid,
input sync_2_valid,
output sync_1_ready,
output sync_2_ready
);
wire sync_ready;
assign sync_ready = sync_1_valid & sync_2_valid;
assign sync_1_ready = sync_ready;
assign sync_2_ready = sync_ready;... | 6.935893 |
module altera_modular_adc_response_merge (
input clk,
input rst_n,
input rsp_in_1_valid,
input [ 4:0] rsp_in_1_channel,
input [11:0] rsp_in_1_data,
input rsp_in_1_sop,
input rsp_in_1_eop,
input rsp_in_2_valid,
input [ 4:0] rsp_in_2_channel,
... | 6.935893 |
module altera_modular_adc_sample_store_ram #(
parameter DATA_WIDTH = 16
) (
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q);
input clock;
input [DATA_WIDTH-1:0] data;
input [5:0] rdaddress;
input rden;
input [5:0] wraddress;
input wren;
output [DATA_WIDTH-1:0] q;
`ifndef ALTERA_RESERVED_Q... | 6.935893 |
module altera_modular_adc_sequencer_csr (
input clk,
input rst_n,
input addr,
input read,
input write,
input [31:0] writedata,
input clr_run,
output reg [31:0] readdata,
output reg run,
output reg sw_clr_run,
output ... | 6.935893 |
module altera_msgdma_prefetcher_fifo #(
parameter RESPONSE_FIFO_WIDTH = 64,
parameter RESPONSE_FIFO_DEPTH = 256,
parameter RESPONSE_FIFO_DEPTH_LOG2 = 7,
parameter LATENCY = 2
) (
input clk,
input areset,
input sres... | 6.804526 |
module altera_msgdma_prefetcher_interrupt (
input clk,
input reset,
input write_back_done,
input transfer_complete_irq_mask,
input [7:0] error_irq_mask,
input early_termination_irq_mask,
input [7:0] error,
input early_termination,
input clear... | 6.804526 |
module construct of the Avalon Streaming receive port for the
// chaining DMA application MSI signals.
//-----------------------------------------------------------------------------
// Copyright (c) 2009 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents,... | 6.967781 |
module altpcierd_cdma_ecrc_gen_calc #(
parameter AVALON_ST_128 = 0
) (
clk,
rstn,
crc_data,
crc_valid,
crc_empty,
crc_eop,
crc_sop,
ecrc,
crc_ack
);
input clk;
input rstn;
input [127:0] crc_data;
input crc_valid;
input [3:0] crc_empty;
input crc_eop;
input crc_sop;... | 6.83792 |
module altpcierd_cdma_ecrc_gen_datapath (
clk,
rstn,
data_in,
data_valid,
rdreq,
data_out,
data_out_valid,
full
);
input clk;
input rstn;
input [135:0] data_in;
input data_valid;
input rdreq;
output [135:0] data_out;
output data_out_valid;
output full;
wire emp... | 6.83792 |
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