code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module altera_avalon_jtag_uart_2pkhqydp_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//altera_avalon_jtag_uart_2pkhqydp_log, which is an e_log
altera_avalon_jtag_uart_2pkhqydp_log_module altera_avalon_jtag_uart_2pkhqydp_log (
.clk (clk),
.data (fifo_wdata),
.strobe(fifo_wr),
.valid (fifo_wr)
);
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 7.767945 |
module altera_avalon_jtag_uart_2pkhqydp_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear;
input [7:0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altera_avalon_jtag_uart_2pkhqydp_sim_scfifo_w the_altera_avalon_jtag_uart_2pkhqydp_sim_scfifo_w (
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty(wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 7.767945 |
module altera_avalon_jtag_uart_2pkhqydp_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [31:0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7:0] fifo_rdata;
wire new_rom;
wire [31:0] num_bytes;
wire [ 6:0] rfifo_entries;
wire rfifo_full;
wire [ 5:0] rfifo_used;
wire safe;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//altera_avalon_jtag_uart_2pkhqydp_drom, which is an e_drom
altera_avalon_jtag_uart_2pkhqydp_drom_module altera_avalon_jtag_uart_2pkhqydp_drom (
.clk (clk),
.incr_addr(fifo_rd_d),
.new_rom (new_rom),
.num_bytes(num_bytes),
.q (fifo_rdata),
.reset_n (rst_n),
.safe (safe)
);
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n) begin
if (rst_n == 0) begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end else begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d) bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom) bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 7.767945 |
module altera_avalon_jtag_uart_2pkhqydp_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [7:0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [7:0] fifo_rdata;
wire rfifo_full;
wire [5:0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altera_avalon_jtag_uart_2pkhqydp_sim_scfifo_r the_altera_avalon_jtag_uart_2pkhqydp_sim_scfifo_r (
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata(fifo_rdata),
.rfifo_full(rfifo_full),
.rfifo_used(rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 7.767945 |
module altera_avalon_jtag_uart_nbmdwotd_log_module (
// inputs:
clk,
data,
strobe,
valid
);
input clk;
input [7:0] data;
input strobe;
input valid;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
reg [31:0] text_handle; // for $fopen
initial text_handle = $fopen("altera_avalon_jtag_uart_nbmdwotd_output_stream.dat");
always @(posedge clk) begin
if (valid && strobe) begin
$fwrite(text_handle, "%b\n", data);
// echo raw binary strings to file as ascii to screen
$write("%s", ((data == 8'hd) ? 8'ha : data));
// non-standard; poorly documented; required to get real data stream.
$fflush(text_handle);
end
end // clk
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 7.767945 |
module altera_avalon_jtag_uart_nbmdwotd_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//altera_avalon_jtag_uart_nbmdwotd_log, which is an e_log
altera_avalon_jtag_uart_nbmdwotd_log_module altera_avalon_jtag_uart_nbmdwotd_log (
.clk (clk),
.data (fifo_wdata),
.strobe(fifo_wr),
.valid (fifo_wr)
);
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 7.767945 |
module altera_avalon_jtag_uart_nbmdwotd_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear;
input [7:0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altera_avalon_jtag_uart_nbmdwotd_sim_scfifo_w the_altera_avalon_jtag_uart_nbmdwotd_sim_scfifo_w (
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty(wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 7.767945 |
module altera_avalon_jtag_uart_nbmdwotd_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [9:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [31:0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7:0] fifo_rdata;
wire new_rom;
wire [31:0] num_bytes;
wire [10:0] rfifo_entries;
wire rfifo_full;
wire [ 9:0] rfifo_used;
wire safe;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//altera_avalon_jtag_uart_nbmdwotd_drom, which is an e_drom
altera_avalon_jtag_uart_nbmdwotd_drom_module altera_avalon_jtag_uart_nbmdwotd_drom (
.clk (clk),
.incr_addr(fifo_rd_d),
.new_rom (new_rom),
.num_bytes(num_bytes),
.q (fifo_rdata),
.reset_n (rst_n),
.safe (safe)
);
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n) begin
if (rst_n == 0) begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end else begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d) bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom) bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 11'h400;
assign rfifo_entries = (rfifo_full) ? 11'h400 : bytes_left;
assign rfifo_used = rfifo_entries[9 : 0];
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 7.767945 |
module altera_avalon_jtag_uart_nbmdwotd_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [9:0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [7:0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [7:0] fifo_rdata;
wire rfifo_full;
wire [9:0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altera_avalon_jtag_uart_nbmdwotd_sim_scfifo_r the_altera_avalon_jtag_uart_nbmdwotd_sim_scfifo_r (
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata(fifo_rdata),
.rfifo_full(rfifo_full),
.rfifo_used(rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 1024,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 10,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 7.767945 |
module altera_avalon_lcd_16207_6pcwkhmx (
// inputs:
address,
begintransfer,
read,
write,
writedata,
// outputs:
LCD_E,
LCD_RS,
LCD_RW,
LCD_data,
readdata
);
output LCD_E;
output LCD_RS;
output LCD_RW;
inout [7:0] LCD_data;
output [7:0] readdata;
input [1:0] address;
input begintransfer;
input read;
input write;
input [7:0] writedata;
wire LCD_E;
wire LCD_RS;
wire LCD_RW;
wire [7:0] LCD_data;
wire [7:0] readdata;
assign LCD_RW = address[0];
assign LCD_RS = address[1];
assign LCD_E = read | write;
assign LCD_data = (address[0]) ? 8'bz : writedata;
assign readdata = LCD_data;
//control_slave, which is an e_avalon_slave
endmodule
| 7.767945 |
module altera_avalon_onchip_memory2_4y7nc2pu (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
);
output [31:0] readdata;
input [15:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [31:0] writedata;
wire [31:0] readdata;
wire wren;
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clk),
.clocken0(clken),
.data_a(writedata),
.q_a(readdata),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 32918,
the_altsyncram.numwords_a = 32918, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 16;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .byteena_a (byteenable),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "altera_avalon_onchip_memory2_4y7nc2pu.hex",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 32918,
// the_altsyncram.numwords_a = 32918,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_byteena_a = 4,
// the_altsyncram.widthad_a = 16;
//
//synthesis read_comments_as_HDL off
endmodule
| 7.767945 |
module altera_avalon_onchip_memory2_mejd6mmm (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
);
output [31:0] readdata;
input [14:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [31:0] writedata;
wire [31:0] readdata;
wire wren;
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clk),
.clocken0(clken),
.data_a(writedata),
.q_a(readdata),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 32768,
the_altsyncram.numwords_a = 32768, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 15;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .byteena_a (byteenable),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "altera_avalon_onchip_memory2_mejd6mmm.hex",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 32768,
// the_altsyncram.numwords_a = 32768,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_byteena_a = 4,
// the_altsyncram.widthad_a = 15;
//
//synthesis read_comments_as_HDL off
endmodule
| 7.767945 |
module altera_avalon_onchip_memory2_try7plvj (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
);
output [31:0] readdata;
input [15:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [31:0] writedata;
wire [31:0] readdata;
wire wren;
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clk),
.clocken0(clken),
.data_a(writedata),
.q_a(readdata),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 65536,
the_altsyncram.numwords_a = 65536, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 16;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .byteena_a (byteenable),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "altera_avalon_onchip_memory2_try7plvj.hex",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 65536,
// the_altsyncram.numwords_a = 65536,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_byteena_a = 4,
// the_altsyncram.widthad_a = 16;
//
//synthesis read_comments_as_HDL off
endmodule
| 7.767945 |
module fifo_buffer_single_clock_fifo (
// inputs:
aclr,
clock,
data,
rdreq,
wrreq,
// outputs:
empty,
full,
q
);
parameter FIFO_DEPTHS = 2;
parameter FIFO_WIDTHU = 1;
output empty;
output full;
output [35:0] q;
input aclr;
input clock;
input [35:0] data;
input rdreq;
input wrreq;
wire empty;
wire full;
wire [35:0] q;
scfifo single_clock_fifo (
.aclr(aclr),
.clock(clock),
.data(data),
.empty(empty),
.full(full),
.q(q),
.rdreq(rdreq),
.wrreq(wrreq)
);
defparam single_clock_fifo.add_ram_output_register = "OFF",
single_clock_fifo.lpm_numwords = FIFO_DEPTHS, single_clock_fifo.lpm_showahead = "OFF",
single_clock_fifo.lpm_type = "scfifo", single_clock_fifo.lpm_width = 36,
single_clock_fifo.lpm_widthu = FIFO_WIDTHU, single_clock_fifo.overflow_checking = "ON",
single_clock_fifo.underflow_checking = "ON", single_clock_fifo.use_eab = "OFF";
endmodule
| 6.571683 |
module fifo_buffer_scfifo_with_controls (
// inputs:
clock,
data,
rdreq,
reset_n,
wrreq,
// outputs:
empty,
full,
q
);
parameter FIFO_DEPTHS = 2;
parameter FIFO_WIDTHU = 1;
output empty;
output full;
output [35:0] q;
input clock;
input [35:0] data;
input rdreq;
input reset_n;
input wrreq;
wire empty;
wire full;
wire [35:0] q;
wire wrreq_valid;
//the_scfifo, which is an e_instance
fifo_buffer_single_clock_fifo #(
.FIFO_DEPTHS(FIFO_DEPTHS),
.FIFO_WIDTHU(FIFO_WIDTHU)
) the_scfifo (
.aclr (~reset_n),
.clock(clock),
.data (data),
.empty(empty),
.full (full),
.q (q),
.rdreq(rdreq),
.wrreq(wrreq_valid)
);
assign wrreq_valid = wrreq & ~full;
endmodule
| 6.571683 |
module fifo_buffer (
// inputs:
avalonmm_read_slave_read,
avalonmm_write_slave_write,
avalonmm_write_slave_writedata,
reset_n,
wrclock,
// outputs:
avalonmm_read_slave_readdata,
avalonmm_read_slave_waitrequest,
avalonmm_write_slave_waitrequest
);
parameter FIFO_DEPTHS = 2;
parameter FIFO_WIDTHU = 1;
output [35:0] avalonmm_read_slave_readdata;
output avalonmm_read_slave_waitrequest;
output avalonmm_write_slave_waitrequest;
input avalonmm_read_slave_read;
input avalonmm_write_slave_write;
input [35:0] avalonmm_write_slave_writedata;
input reset_n;
input wrclock;
wire [35:0] avalonmm_read_slave_readdata;
wire avalonmm_read_slave_waitrequest;
wire avalonmm_write_slave_waitrequest;
wire clock;
wire [35:0] data;
wire empty;
wire full;
wire [35:0] q;
wire rdreq;
wire wrreq;
//the_scfifo_with_controls, which is an e_instance
fifo_buffer_scfifo_with_controls #(
.FIFO_DEPTHS(FIFO_DEPTHS),
.FIFO_WIDTHU(FIFO_WIDTHU)
) the_scfifo_with_controls (
.clock (clock),
.data (data),
.empty (empty),
.full (full),
.q (q),
.rdreq (rdreq),
.reset_n(reset_n),
.wrreq (wrreq)
);
//in, which is an e_avalon_slave
//out, which is an e_avalon_slave
assign data = avalonmm_write_slave_writedata;
assign wrreq = avalonmm_write_slave_write;
assign avalonmm_read_slave_readdata = q;
assign rdreq = avalonmm_read_slave_read;
assign clock = wrclock;
assign avalonmm_write_slave_waitrequest = full;
assign avalonmm_read_slave_waitrequest = empty;
endmodule
| 8.171221 |
module altera_avalon_packets_to_master_inst_for_spichain (
// inputs:
clk,
in_data,
in_endofpacket,
in_startofpacket,
in_valid,
out_ready,
readdata,
readdatavalid,
reset_n,
waitrequest,
// outputs:
address,
byteenable,
in_ready,
out_data,
out_endofpacket,
out_startofpacket,
out_valid,
read,
write,
writedata
);
output [31:0] address;
output [3:0] byteenable;
output in_ready;
output [7:0] out_data;
output out_endofpacket;
output out_startofpacket;
output out_valid;
output read;
output write;
output [31:0] writedata;
input clk;
input [7:0] in_data;
input in_endofpacket;
input in_startofpacket;
input in_valid;
input out_ready;
input [31:0] readdata;
input readdatavalid;
input reset_n;
input waitrequest;
wire [31:0] address;
wire [ 3:0] byteenable;
wire in_ready;
wire [ 7:0] out_data;
wire out_endofpacket;
wire out_startofpacket;
wire out_valid;
wire read;
wire write;
wire [31:0] writedata;
altera_avalon_packets_to_master the_altera_avalon_packets_to_master (
.address (address),
.byteenable (byteenable),
.clk (clk),
.in_data (in_data),
.in_endofpacket (in_endofpacket),
.in_ready (in_ready),
.in_startofpacket (in_startofpacket),
.in_valid (in_valid),
.out_data (out_data),
.out_endofpacket (out_endofpacket),
.out_ready (out_ready),
.out_startofpacket(out_startofpacket),
.out_valid (out_valid),
.read (read),
.readdata (readdata),
.readdatavalid (readdatavalid),
.reset_n (reset_n),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata)
);
defparam the_altera_avalon_packets_to_master.EXPORT_MASTER_SIGNALS = 1;
endmodule
| 7.767945 |
module altera_avalon_pio_342yz4ye (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output out_port;
output readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1{(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata;
end
assign readdata = read_mux_out;
assign out_port = data_out;
endmodule
| 7.767945 |
module altera_avalon_pio_4lxvnb4y (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [17:0] out_port;
output [17:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [17:0] writedata;
wire clk_en;
reg [17:0] data_out;
wire [17:0] out_port;
wire [17:0] read_mux_out;
wire [17:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {18{(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata[17 : 0];
end
assign readdata = read_mux_out;
assign out_port = data_out;
endmodule
| 7.767945 |
module altera_avalon_pio_5mxhwzsf (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
);
output irq;
output [3:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input [3:0] in_port;
input reset_n;
input write_n;
input [3:0] writedata;
wire clk_en;
reg [3:0] d1_data_in;
reg [3:0] d2_data_in;
wire [3:0] data_in;
reg [3:0] edge_capture;
wire edge_capture_wr_strobe;
wire [3:0] edge_detect;
wire irq;
reg [3:0] irq_mask;
wire [3:0] read_mux_out;
reg [3:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 2)}} & irq_mask) |
({4 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= read_mux_out;
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2)) irq_mask <= writedata[3 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe) edge_capture[0] <= 0;
else if (edge_detect[0]) edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe) edge_capture[1] <= 0;
else if (edge_detect[1]) edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe) edge_capture[2] <= 0;
else if (edge_detect[2]) edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe) edge_capture[3] <= 0;
else if (edge_detect[3]) edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) begin
d1_data_in <= 0;
d2_data_in <= 0;
end else if (clk_en) begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = ~d1_data_in & d2_data_in;
endmodule
| 7.767945 |
module altera_avalon_pio_brhxffyx (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [7:0] out_port;
output [7:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [7:0] writedata;
wire clk_en;
reg [7:0] data_out;
wire [7:0] out_port;
wire [7:0] read_mux_out;
wire [7:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8{(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata[7 : 0];
end
assign readdata = read_mux_out;
assign out_port = data_out;
endmodule
| 7.767945 |
module altera_avalon_pio_kazrjara (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
bidir_port,
readdata
);
inout bidir_port;
output readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input writedata;
wire bidir_port;
wire clk_en;
reg data_dir;
wire data_in;
reg data_out;
wire read_mux_out;
reg readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({1{(address == 0)}} & data_in) | ({1{(address == 1)}} & data_dir);
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= read_mux_out;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata;
end
assign bidir_port = data_dir ? data_out : 1'bZ;
assign data_in = bidir_port;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_dir <= 0;
else if (chipselect && ~write_n && (address == 1)) data_dir <= writedata;
end
endmodule
| 7.767945 |
module altera_avalon_pio_kxgghky6 (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output readdata;
input [1:0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1{(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= read_mux_out;
end
assign data_in = in_port;
endmodule
| 7.767945 |
module altera_avalon_pio_t23333bf (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [8:0] out_port;
output [8:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [8:0] writedata;
wire clk_en;
reg [8:0] data_out;
wire [8:0] out_port;
wire [8:0] read_mux_out;
wire [8:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {9{(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata[8 : 0];
end
assign readdata = read_mux_out;
assign out_port = data_out;
endmodule
| 7.767945 |
module altera_avalon_pio_vuxkmkdz (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
bidir_port,
readdata
);
inout [3:0] bidir_port;
output [3:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [3:0] writedata;
wire [3:0] bidir_port;
wire clk_en;
reg [3:0] data_dir;
wire [3:0] data_in;
reg [3:0] data_out;
wire [3:0] read_mux_out;
reg [3:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4{(address == 0)}} & data_in) | ({4{(address == 1)}} & data_dir);
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= read_mux_out;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata[3 : 0];
end
assign bidir_port[0] = data_dir[0] ? data_out[0] : 1'bZ;
assign bidir_port[1] = data_dir[1] ? data_out[1] : 1'bZ;
assign bidir_port[2] = data_dir[2] ? data_out[2] : 1'bZ;
assign bidir_port[3] = data_dir[3] ? data_out[3] : 1'bZ;
assign data_in = bidir_port;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_dir <= 0;
else if (chipselect && ~write_n && (address == 1)) data_dir <= writedata[3 : 0];
end
endmodule
| 7.767945 |
module altera_avalon_st_bytes_to_packets_inst_for_spichain (
// inputs:
clk,
in_data,
in_valid,
out_ready,
reset_n,
// outputs:
in_ready,
out_channel,
out_data,
out_endofpacket,
out_startofpacket,
out_valid
);
output in_ready;
output [7:0] out_channel;
output [7:0] out_data;
output out_endofpacket;
output out_startofpacket;
output out_valid;
input clk;
input [7:0] in_data;
input in_valid;
input out_ready;
input reset_n;
wire in_ready;
wire [7:0] out_channel;
wire [7:0] out_data;
wire out_endofpacket;
wire out_startofpacket;
wire out_valid;
altera_avalon_st_bytes_to_packets the_altera_avalon_st_bytes_to_packets (
.clk (clk),
.in_data (in_data),
.in_ready (in_ready),
.in_valid (in_valid),
.out_channel (out_channel),
.out_data (out_data),
.out_endofpacket (out_endofpacket),
.out_ready (out_ready),
.out_startofpacket(out_startofpacket),
.out_valid (out_valid),
.reset_n (reset_n)
);
endmodule
| 7.767945 |
module altera_avalon_st_clock_crosser (
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\""} *)reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= {DATA_WIDTH{1'b0}};
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= {DATA_WIDTH{1'b0}};
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer_nocut #(
.depth(FORWARD_SYNC_DEPTH)
) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer_nocut #(
.depth(BACKWARD_SYNC_DEPTH)
) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate
if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base #(
.BITS_PER_SYMBOL (BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
| 7.767945 |
module altera_avalon_st_idle_inserter (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7:0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7:0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & out_ready) begin
if ((idle_char | escape_char) & ~received_esc & out_ready) begin
received_esc <= 1;
end else begin
received_esc <= 0;
end
end
end
end
always @* begin
//we are always valid
out_valid = 1'b1;
in_ready = out_ready & (~in_valid | ((~idle_char & ~escape_char) | received_esc));
out_data = (~in_valid) ? 8'h4a : //if input is not valid, insert idle
(received_esc) ? in_data ^ 8'h20 : //escaped once, send data XOR'd
(idle_char | escape_char) ? 8'h4d : //input needs escaping, send escape_char
in_data; //send data
end
endmodule
| 7.767945 |
module altera_avalon_st_idle_remover (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7:0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7:0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & in_ready) begin
if (escape_char & ~received_esc) begin
received_esc <= 1;
end else if (out_valid) begin
received_esc <= 0;
end
end
end
end
always @* begin
in_ready = out_ready;
//out valid when in_valid. Except when we get idle or escape
//however, if we have received an escape character, then we are valid
out_valid = in_valid & ~idle_char & (received_esc | ~escape_char);
out_data = received_esc ? (in_data ^ 8'h20) : in_data;
end
endmodule
| 7.767945 |
module altera_avalon_st_packets_to_bytes_inst_for_spichain (
// inputs:
clk,
in_channel,
in_data,
in_endofpacket,
in_startofpacket,
in_valid,
out_ready,
reset_n,
// outputs:
in_ready,
out_data,
out_valid
);
output in_ready;
output [7:0] out_data;
output out_valid;
input clk;
input [7:0] in_channel;
input [7:0] in_data;
input in_endofpacket;
input in_startofpacket;
input in_valid;
input out_ready;
input reset_n;
wire in_ready;
wire [7:0] out_data;
wire out_valid;
altera_avalon_st_packets_to_bytes the_altera_avalon_st_packets_to_bytes (
.clk (clk),
.in_channel (in_channel),
.in_data (in_data),
.in_endofpacket (in_endofpacket),
.in_ready (in_ready),
.in_startofpacket(in_startofpacket),
.in_valid (in_valid),
.out_data (out_data),
.out_ready (out_ready),
.out_valid (out_valid),
.reset_n (reset_n)
);
endmodule
| 7.767945 |
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate
if (PIPELINE_READY == 1) begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0) data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0) data1 <= data0;
else data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end else begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
| 7.767945 |
module altera_avalon_sysid_qsys #(
parameter ID_VALUE = 1,
parameter TIMESTAMP = 1
) (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? TIMESTAMP : ID_VALUE;
endmodule
| 7.767945 |
module altera_avalon_sysid_qsys_cnhypnam (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 0 : 0;
endmodule
| 7.767945 |
module altera_avalon_sysid_qsys_exz7b53s (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 0 : 0;
endmodule
| 7.767945 |
module altera_avalon_throughput_monitor #(
parameter BC_W = 5
) (
input avs_clock,
input if_clock,
input avs_reset,
input if_reset,
input if_read,
input if_write,
input [BC_W-1:0] if_burstcount,
input if_waitrequest,
input if_readdatavalid,
//avalon count interface
input [ 1:0] avs_address,
input avs_read,
output [31:0] avs_readdata,
output avs_waitrequest,
//avalon status interface
input [ 1:0] ctl_address, //not really used, but keeps qsys happy
output [31:0] ctl_readdata
);
localparam MANUFACTURER_ID = 16'h03, REVISION_NUM = 16'h01;
assign ctl_readdata = {MANUFACTURER_ID, REVISION_NUM};
wire togl_to_pmon, togl_from_pmon;
wire [31:0] count_data;
wire [ 1:0] reg_address;
//module provides read access to all counters
altera_pmon_count_csr count_csr (
.avs_clock (avs_clock),
.avs_reset (avs_reset),
.avs_read (avs_read),
.avs_address (avs_address),
.avs_waitrequest(avs_waitrequest),
.avs_readdata (avs_readdata),
.toglout (togl_to_pmon),
.toglin (togl_from_pmon),
.address (reg_address),
.count_data(count_data)
);
//the counters themselves
altera_pmon_counters #(
.BC_W(BC_W)
) pcounters (
.if_clock (if_clock),
.if_reset (if_reset),
.if_read (if_read),
.if_write (if_write),
.if_burstcount (if_burstcount),
.if_waitrequest (if_waitrequest),
.if_readdatavalid(if_readdatavalid),
.address (reg_address),
.toglin (togl_to_pmon),
.toglout (togl_from_pmon),
.count_data(count_data)
);
endmodule
| 7.767945 |
module altera_avalon_uart_5tcpgvvj_log_module (
// inputs:
clk,
data,
strobe,
valid
);
input clk;
input [7:0] data;
input strobe;
input valid;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
reg [31:0] text_handle; // for $fopen
initial text_handle = $fopen("altera_avalon_uart_5tcpgvvj_log_module.txt");
always @(posedge clk) begin
if (valid && strobe) begin
// Send \n (linefeed) instead of \r (^M, Carriage Return)...
$fwrite(text_handle, "%s", ((data == 8'hd) ? 8'ha : data));
// non-standard; poorly documented; required to get real data stream.
$fflush(text_handle);
end
end // clk
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 7.767945 |
module altera_avalon_uart_5tcpgvvj_rx_stimulus_source (
// inputs:
baud_divisor,
clk,
clk_en,
reset_n,
rx_char_ready,
rxd,
// outputs:
source_rxd
);
output source_rxd;
input [8:0] baud_divisor;
input clk;
input clk_en;
input reset_n;
input rx_char_ready;
input rxd;
reg [7:0] d1_stim_data;
reg delayed_unxrx_char_readyxx0;
wire do_send_stim_data;
wire new_rom_pulse;
wire pickup_pulse;
wire safe;
wire source_rxd;
wire [7:0] stim_data;
wire unused_empty;
wire unused_overrun;
wire unused_ready;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//stimulus_transmitter, which is an e_instance
altera_avalon_uart_5tcpgvvj_tx stimulus_transmitter (
.baud_divisor (baud_divisor),
.begintransfer (do_send_stim_data),
.clk (clk),
.clk_en (clk_en),
.do_force_break (1'b0),
.reset_n (reset_n),
.status_wr_strobe(1'b0),
.tx_data (d1_stim_data),
.tx_overrun (unused_overrun),
.tx_ready (unused_ready),
.tx_shift_empty (unused_empty),
.tx_wr_strobe (1'b1),
.txd (source_rxd)
);
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) d1_stim_data <= 0;
else if (do_send_stim_data) d1_stim_data <= stim_data;
end
//altera_avalon_uart_5tcpgvvj_rx_stimulus_source_character_source_rom, which is an e_drom
altera_avalon_uart_5tcpgvvj_rx_stimulus_source_character_source_rom_module altera_avalon_uart_5tcpgvvj_rx_stimulus_source_character_source_rom
(
.clk (clk),
.incr_addr(do_send_stim_data),
.new_rom (new_rom_pulse),
.q (stim_data),
.reset_n (reset_n),
.safe (safe)
);
//delayed_unxrx_char_readyxx0, which is an e_register
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) delayed_unxrx_char_readyxx0 <= 0;
else if (clk_en) delayed_unxrx_char_readyxx0 <= rx_char_ready;
end
assign pickup_pulse = ~(rx_char_ready) & (delayed_unxrx_char_readyxx0);
assign do_send_stim_data = (pickup_pulse || new_rom_pulse) && safe;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign source_rxd = rxd;
//synthesis read_comments_as_HDL off
endmodule
| 7.767945 |
module altera_dcfifo_synchronizer_bundle (
clk,
reset_n,
din,
dout
);
parameter WIDTH = 1;
parameter DEPTH = 3;
input clk;
input reset_n;
input [WIDTH-1:0] din;
output [WIDTH-1:0] dout;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : sync
altera_std_synchronizer_nocut #(
.depth(DEPTH)
) u (
.clk(clk),
.reset_n(reset_n),
.din(din[i]),
.dout(dout[i])
);
end
endgenerate
endmodule
| 6.996057 |
module altera_dpram (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock_a;
input clock_b;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire [31:0] q_a = sub_wire0[31:0];
wire [31:0] q_b = sub_wire1[31:0];
altsyncram altsyncram_component (
.clock0 (clock_a),
.wren_a (wren_a),
.address_b (address_b),
.clock1 (clock_b),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 4096,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 12,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
| 7.657338 |
module altera_dpram (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b
);
input [11:0] address_a;
input [11:0] address_b;
input clock_a;
input clock_b;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 7.657338 |
module altera_dual_boot (
clk,
nreset,
avmm_rcv_address,
avmm_rcv_writedata,
avmm_rcv_write,
avmm_rcv_read,
avmm_rcv_readdata
);
parameter LPM_TYPE = "ALTERA_DUAL_BOOT";
parameter INTENDED_DEVICE_FAMILY = "MAX 10 FPGA";
parameter A_WIDTH = 3;
parameter WD_WIDTH = 4;
parameter RD_WIDTH = 17;
parameter MAX_DATA_WIDTH = 32;
parameter CONFIG_CYCLE = 28;
parameter RESET_TIMER_CYCLE = 40;
input clk;
input nreset;
input [A_WIDTH-1:0] avmm_rcv_address;
input [MAX_DATA_WIDTH-1:0] avmm_rcv_writedata;
input avmm_rcv_write;
input avmm_rcv_read;
output [MAX_DATA_WIDTH-1:0] avmm_rcv_readdata;
alt_dual_boot_avmm alt_dual_boot_avmm_comp (
.clk(clk),
.nreset(nreset),
.avmm_rcv_address(avmm_rcv_address),
.avmm_rcv_writedata(avmm_rcv_writedata),
.avmm_rcv_write(avmm_rcv_write),
.avmm_rcv_read(avmm_rcv_read),
.avmm_rcv_readdata(avmm_rcv_readdata)
);
defparam alt_dual_boot_avmm_comp.LPM_TYPE = LPM_TYPE,
alt_dual_boot_avmm_comp.INTENDED_DEVICE_FAMILY = INTENDED_DEVICE_FAMILY,
alt_dual_boot_avmm_comp.A_WIDTH = A_WIDTH,
alt_dual_boot_avmm_comp.MAX_DATA_WIDTH = MAX_DATA_WIDTH,
alt_dual_boot_avmm_comp.WD_WIDTH = WD_WIDTH, alt_dual_boot_avmm_comp.RD_WIDTH = RD_WIDTH,
alt_dual_boot_avmm_comp.CONFIG_CYCLE = CONFIG_CYCLE,
alt_dual_boot_avmm_comp.RESET_TIMER_CYCLE = RESET_TIMER_CYCLE;
endmodule
| 7.042424 |
module altera_dual_port_ram_simple #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 10
) (
input clk,
input write_enable,
input [ADDR_WIDTH-1:0] write_addr,
input [ADDR_WIDTH-1:0] read_addr,
input [DATA_WIDTH-1:0] data_in,
output [DATA_WIDTH-1:0] data_out
);
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] addr_reg;
always @(posedge clk) begin
if (write_enable) ram[write_addr] <= data_in;
addr_reg <= read_addr;
end
assign data_out = ram[addr_reg];
endmodule
| 8.9788 |
module altera_edge_detector #(
parameter PULSE_EXT = 0, // 0, 1 = edge detection generate single cycle pulse, >1 = pulse extended for specified clock cycle
parameter EDGE_TYPE = 0, // 0 = falling edge, 1 or else = rising edge
parameter IGNORE_RST_WHILE_BUSY = 0 // 0 = module internal reset will be default whenever rst_n asserted, 1 = rst_n request will be ignored while generating pulse out
) (
input clk,
input rst_n,
input signal_in,
output pulse_out
);
localparam IDLE = 0, ARM = 1, CAPT = 2;
localparam SIGNAL_ASSERT = EDGE_TYPE ? 1'b1 : 1'b0;
localparam SIGNAL_DEASSERT = EDGE_TYPE ? 1'b0 : 1'b1;
reg [1:0] state, next_state;
reg pulse_detect;
wire busy_pulsing;
assign busy_pulsing = (IGNORE_RST_WHILE_BUSY) ? pulse_out : 1'b0;
assign reset_qual_n = rst_n | busy_pulsing;
generate
if (PULSE_EXT > 1) begin : pulse_extend
integer i;
reg [PULSE_EXT-1:0] extend_pulse;
always @(posedge clk or negedge reset_qual_n) begin
if (!reset_qual_n) extend_pulse <= {{PULSE_EXT} {1'b0}};
else begin
for (i = 1; i < PULSE_EXT; i = i + 1) begin
extend_pulse[i] <= extend_pulse[i-1];
end
extend_pulse[0] <= pulse_detect;
end
end
assign pulse_out = |extend_pulse;
end else begin : single_pulse
reg pulse_reg;
always @(posedge clk or negedge reset_qual_n) begin
if (!reset_qual_n) pulse_reg <= 1'b0;
else pulse_reg <= pulse_detect;
end
assign pulse_out = pulse_reg;
end
endgenerate
always @(posedge clk) begin
if (!rst_n) state <= IDLE;
else state <= next_state;
end
// edge detect
always @(*) begin
next_state = state;
pulse_detect = 1'b0;
case (state)
IDLE: begin
pulse_detect = 1'b0;
if (signal_in == SIGNAL_DEASSERT) next_state = ARM;
else next_state = IDLE;
end
ARM: begin
pulse_detect = 1'b0;
if (signal_in == SIGNAL_ASSERT) next_state = CAPT;
else next_state = ARM;
end
CAPT: begin
pulse_detect = 1'b1;
if (signal_in == SIGNAL_DEASSERT) next_state = ARM;
else next_state = IDLE;
end
default: begin
pulse_detect = 1'b0;
next_state = IDLE;
end
endcase
end
endmodule
| 8.376436 |
module altera_eth_fifo_pause_ctrl_adapter (
//global
clk,
reset,
//Almost full Data Sink
data_sink_almost_full,
//Almost empty Data Sink
data_sink_almost_empty,
//Av-ST Data Source
pause_ctrl_src_data
);
// =head2 Clock and reset interface
input clk;
input reset;
// =head2 Avalon ST DataIn (Sink) Interface
input data_sink_almost_full;
// =head2 Avalon ST DataIn (Sink) Interface
input data_sink_almost_empty;
// =head2 Avalon ST DataOut (Source) Interface
output [1:0] pause_ctrl_src_data;
reg hold_almost_full;
reg hold_almost_full_1;
reg reg_data_sink_almost_full;
reg reg_data_sink_almost_empty;
always @(posedge clk or posedge reset) begin
if (reset == 1'b1) begin
hold_almost_full <= 1'b0;
reg_data_sink_almost_full <= 1'b0;
reg_data_sink_almost_empty <= 1'b0;
hold_almost_full_1 <= 1'b0;
end else begin
if (data_sink_almost_empty == 1'b1) begin
hold_almost_full <= 1'b0;
end else if (data_sink_almost_full == 1'b1) begin
hold_almost_full <= 1'b1;
end
reg_data_sink_almost_full <= data_sink_almost_full;
reg_data_sink_almost_empty <= data_sink_almost_empty;
hold_almost_full_1 <= hold_almost_full;
end
end
assign pause_ctrl_src_data[1] = reg_data_sink_almost_full;
assign pause_ctrl_src_data[0] = hold_almost_full_1 & reg_data_sink_almost_empty;
endmodule
| 6.608189 |
module altera_eth_loopback (
clk,
reset_n,
// sink
in_data_0,
in_valid_0,
in_ready_0,
in_startofpacket_0,
in_endofpacket_0,
in_empty_0,
in_error_0,
// sink
in_data_1,
in_valid_1,
in_ready_1,
in_startofpacket_1,
in_endofpacket_1,
in_empty_1,
in_error_1,
// source
out_data,
out_valid,
out_ready,
out_startofpacket,
out_endofpacket,
out_empty,
out_error,
// in control
control_address,
control_write,
control_read,
control_readdata,
control_writedata
);
// ---------------------------------------------------------------------
// Parameters
// ---------------------------------------------------------------------
parameter SYMBOLS_PER_BEAT = 4;
parameter BITS_PER_SYMBOL = 8;
parameter ERROR_WIDTH = 1;
parameter USE_PACKETS = 1;
parameter EMPTY_WIDTH = 0;
parameter MAX_CHANNELS = 2;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
// ---------------------------------------------------------------------
// Input/Output Signals
// ---------------------------------------------------------------------
input clk;
input reset_n;
input [DATA_WIDTH - 1 : 0] in_data_0;
input in_valid_0;
input in_startofpacket_0;
input in_endofpacket_0;
input [EMPTY_WIDTH - 1 : 0] in_empty_0;
input [ERROR_WIDTH - 1 : 0] in_error_0;
output in_ready_0;
input [DATA_WIDTH - 1 : 0] in_data_1;
input in_valid_1;
input in_startofpacket_1;
input in_endofpacket_1;
input [EMPTY_WIDTH - 1 : 0] in_empty_1;
input [ERROR_WIDTH - 1 : 0] in_error_1;
output in_ready_1;
output [DATA_WIDTH - 1 : 0] out_data;
output out_valid;
output out_startofpacket;
output out_endofpacket;
output [EMPTY_WIDTH - 1 : 0] out_empty;
output [ERROR_WIDTH - 1 : 0] out_error;
input out_ready;
input control_address;
input control_read;
input control_write;
input [31 : 0] control_writedata;
output reg [31 : 0] control_readdata;
reg selector;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
control_readdata <= 0;
selector <= 0;
end else begin
if (control_write) begin
selector <= 0;
selector <= control_writedata;
end else if (control_read) begin
control_readdata <= 0;
control_readdata <= selector;
end
end
end
assign out_data = selector == 1'b0 ? in_data_0 : in_data_1;
assign out_valid = selector == 1'b0 ? in_valid_0 : in_valid_1;
assign out_startofpacket = selector == 1'b0 ? in_startofpacket_0 : in_startofpacket_1;
assign out_endofpacket = selector == 1'b0 ? in_endofpacket_0 : in_endofpacket_1;
assign out_empty = selector == 1'b0 ? in_empty_0 : in_empty_1;
assign out_error = selector == 1'b0 ? in_error_0 : in_error_1;
assign in_ready_0 = selector == 1'b0 ? out_ready : 1'b0;
assign in_ready_1 = selector == 1'b1 ? out_ready : 1'b0;
endmodule
| 7.328425 |
module altera_eth_tse_ptp_std_synchronizer #(
parameter width = 1,
parameter depth = 3
) (
input clk,
input reset_n,
input [width-1:0] din,
output [width-1:0] dout
);
genvar i;
generate
for (i = 0; i < width; i = i + 1) begin : nocut_sync
altera_std_synchronizer_nocut #(
.depth(depth)
) std_sync_nocut (
.clk (clk),
.reset_n(reset_n),
.din (din[i]),
.dout (dout[i])
);
end
endgenerate
endmodule
| 6.792487 |
module altera_eth_tse_std_synchronizer #(
parameter depth = 3
) (
input clk,
input reset_n,
input din,
output dout
);
altera_std_synchronizer_nocut #(
.depth(depth)
) std_sync_no_cut (
.clk (clk),
.reset_n(reset_n),
.din (din),
.dout (dout)
);
endmodule
| 6.792487 |
module altera_eth_tse_std_synchronizer_bundle (
clk,
reset_n,
din,
dout
);
// GLOBAL PARAMETER DECLARATION
parameter width = 1;
parameter depth = 3;
// INPUT PORT DECLARATION
input clk;
input reset_n;
input [width-1:0] din;
// OUTPUT PORT DECLARATION
output [width-1:0] dout;
generate
genvar i;
for (i = 0; i < width; i = i + 1) begin : sync
altera_eth_tse_std_synchronizer #(
.depth(depth)
) u (
.clk(clk),
.reset_n(reset_n),
.din(din[i]),
.dout(dout[i])
);
end
endgenerate
endmodule
| 6.792487 |
module altera_gtr_clock_gate (
input clk,
input rst_n,
input en,
output clk_gated
);
reg en_flp;
always @(negedge clk or negedge rst_n) begin
if (!rst_n) en_flp <= 1'b0;
else en_flp <= en;
end
assign clk_gated = clk & en_flp;
endmodule
| 7.248689 |
module altera_gtr_clock_mux (
input inclk0,
input rst0_n,
input inclk1,
input rst1_n,
input clksel,
// Disable C104 rule check
// outclk is a generated clock
output outclk /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"C104\"" */
);
reg clksel0_sync_dly;
reg clksel1_sync_dly;
wire clksel0;
wire clksel1;
wire clksel0_sync;
wire clksel1_sync;
wire inclk0_gated;
wire inclk1_gated;
assign clksel0 = ~clksel & ~clksel1_sync_dly;
assign clksel1 = clksel & ~clksel0_sync_dly;
// Disable D103 rule check on this synchronizer flops.
// AND gate combinatorial logic before going into synchronizer input is safe (clksel is static)
altera_std_synchronizer #(
.depth(2)
) u_inclk0_synchronizer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D103\"" */ (
.clk (inclk0),
.reset_n(rst0_n),
.din (clksel0),
.dout (clksel0_sync)
);
// Disable D103 rule check on this synchronizer flops.
// AND gate combinatorial logic before going into synchronizer input is safe (clksel is static)
altera_std_synchronizer #(
.depth(2)
) u_inclk1_synchronizer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D103\"" */ (
.clk (inclk1),
.reset_n(rst1_n),
.din (clksel1),
.dout (clksel1_sync)
);
// Disable C106 rule check
// Register used to latch the en in clock gating component is expected to be inverse of sampling edge
altera_gtr_clock_gate u_clk0_gate /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"C106\"" */ (
.clk (inclk0),
.rst_n (rst0_n),
.en (clksel0_sync),
.clk_gated(inclk0_gated)
);
// Disable C106 rule check
// Register used to latch the en in clock gating component is expected to be inverse of sampling edge
altera_gtr_clock_gate u_clk1_gate /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"C106\"" */ (
.clk (inclk1),
.rst_n (rst1_n),
.en (clksel1_sync),
.clk_gated(inclk1_gated)
);
always @(posedge inclk0 or negedge rst0_n) begin
if (!rst0_n) clksel0_sync_dly <= 1'b0;
else clksel0_sync_dly <= clksel0_sync;
end
always @(posedge inclk1 or negedge rst1_n) begin
if (!rst1_n) clksel1_sync_dly <= 1'b0;
else clksel1_sync_dly <= clksel1_sync;
end
assign outclk = inclk0_gated | inclk1_gated;
endmodule
| 7.248689 |
module altera_gtr_mac_speed_filter (
input clk,
input rst_n,
input [1:0] mac_speed,
output reg [1:0] mac_speed_filtered
);
wire [1:0] mac_speed_sync;
wire update_speed;
wire speed_change_det;
reg speed_change_det_1;
reg speed_change_det_2;
reg speed_change_det_3;
altera_std_synchronizer #(
.depth(2)
) u_mac_speed_0_synchronizer (
.clk (clk),
.reset_n(rst_n),
.din (mac_speed[0]),
.dout (mac_speed_sync[0])
);
altera_std_synchronizer #(
.depth(2)
) u_mac_speed_1_synchronizer (
.clk (clk),
.reset_n(rst_n),
.din (mac_speed[1]),
.dout (mac_speed_sync[1])
);
// Filtering logic
// Since mac_speed is a bus vector, filtering logic here aim at eliminating bit coherency issue after the synchronization
// Once change is detected, delay for 3 clocks before updating the mac_speed_filtered
// mac_speed input from HPS EMAC can be considered static as per BAUM EMAC Design Spec
always @(posedge clk or negedge rst_n) begin
if (!rst_n) mac_speed_filtered <= 2'b00;
else if (update_speed) mac_speed_filtered <= mac_speed_sync;
end
assign speed_change_det = (mac_speed_sync[0] ^ mac_speed_filtered[0]) |
(mac_speed_sync[1] ^ mac_speed_filtered[1]);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
speed_change_det_1 <= 1'b0;
speed_change_det_2 <= 1'b0;
speed_change_det_3 <= 1'b0;
end else begin
speed_change_det_1 <= speed_change_det;
speed_change_det_2 <= speed_change_det_1;
speed_change_det_3 <= speed_change_det_2;
end
end
assign update_speed = speed_change_det_3;
endmodule
| 9.511213 |
module altera_gtr_pipeline_stage #(
parameter DATA_WIDTH = 1
) (
input clk,
input rst_n,
input [DATA_WIDTH-1:0] datain,
output reg [DATA_WIDTH-1:0] dataout
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) dataout <= {DATA_WIDTH{1'b0}};
else dataout <= datain;
end
endmodule
| 7.795267 |
module altera_gtr_reset_synchronizer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R105\"" */ ( // Disable R105 rule check. This module itself is a reset synchronizer.
input clk,
input rst_n,
output rst_sync_n
);
reg din_sync_1;
reg din_sync_2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
din_sync_1 <= 1'b0;
din_sync_2 <= 1'b0;
end else begin
din_sync_1 <= 1'b1;
din_sync_2 <= din_sync_1;
end
end
assign rst_sync_n = din_sync_2;
endmodule
| 7.291479 |
module lcell_counter_remap #(
//parameter
parameter family = "Arria 10",
parameter lut_mask = 64'hAAAAAAAAAAAAAAAA,
parameter dont_touch = "on"
) (
input wire dataa,
input wire datab,
input wire datac,
input wire datad,
output wire combout
);
wire gnd /*synthesis keep*/;
assign gnd = 1'b0;
generate
if (family == "Arria 10") begin
twentynm_lcell_comb lcell_inst (
.dataa (dataa),
.datab (datab),
.datac (datac),
.datad (datad),
.datae (gnd),
.dataf (gnd),
.combout(combout)
);
defparam lcell_inst.lut_mask = lut_mask; defparam lcell_inst.dont_touch = dont_touch;
end // if (family == "Arria 10")
else if (family == "Cyclone 10 GX")
begin
cyclone10gx_lcell_comb lcell_inst (
.dataa (dataa),
.datab (datab),
.datac (datac),
.datad (datad),
.datae (gnd),
.dataf (gnd),
.combout(combout)
);
defparam lcell_inst.lut_mask = lut_mask; defparam lcell_inst.dont_touch = dont_touch;
end
endgenerate
endmodule
| 7.012093 |
module altera_irq_bridge
#(
parameter IRQ_WIDTH = 32
)
(
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset,
input [IRQ_WIDTH - 1:0] receiver_irq,
output sender31_irq,
output sender30_irq,
output sender29_irq,
output sender28_irq,
output sender27_irq,
output sender26_irq,
output sender25_irq,
output sender24_irq,
output sender23_irq,
output sender22_irq,
output sender21_irq,
output sender20_irq,
output sender19_irq,
output sender18_irq,
output sender17_irq,
output sender16_irq,
output sender15_irq,
output sender14_irq,
output sender13_irq,
output sender12_irq,
output sender11_irq,
output sender10_irq,
output sender9_irq,
output sender8_irq,
output sender7_irq,
output sender6_irq,
output sender5_irq,
output sender4_irq,
output sender3_irq,
output sender2_irq,
output sender1_irq,
output sender0_irq
);
wire [31:0] receiver_temp_irq;
assign receiver_temp_irq = {{(32 - IRQ_WIDTH){1'b0}}, receiver_irq}; //to align a non-32bit receiver interface with 32 interfaces of the receiver
assign sender0_irq = receiver_temp_irq[0];
assign sender1_irq = receiver_temp_irq[1];
assign sender2_irq = receiver_temp_irq[2];
assign sender3_irq = receiver_temp_irq[3];
assign sender4_irq = receiver_temp_irq[4];
assign sender5_irq = receiver_temp_irq[5];
assign sender6_irq = receiver_temp_irq[6];
assign sender7_irq = receiver_temp_irq[7];
assign sender8_irq = receiver_temp_irq[8];
assign sender9_irq = receiver_temp_irq[9];
assign sender10_irq = receiver_temp_irq[10];
assign sender11_irq = receiver_temp_irq[11];
assign sender12_irq = receiver_temp_irq[12];
assign sender13_irq = receiver_temp_irq[13];
assign sender14_irq = receiver_temp_irq[14];
assign sender15_irq = receiver_temp_irq[15];
assign sender16_irq = receiver_temp_irq[16];
assign sender17_irq = receiver_temp_irq[17];
assign sender18_irq = receiver_temp_irq[18];
assign sender19_irq = receiver_temp_irq[19];
assign sender20_irq = receiver_temp_irq[20];
assign sender21_irq = receiver_temp_irq[21];
assign sender22_irq = receiver_temp_irq[22];
assign sender23_irq = receiver_temp_irq[23];
assign sender24_irq = receiver_temp_irq[24];
assign sender25_irq = receiver_temp_irq[25];
assign sender26_irq = receiver_temp_irq[26];
assign sender27_irq = receiver_temp_irq[27];
assign sender28_irq = receiver_temp_irq[28];
assign sender29_irq = receiver_temp_irq[29];
assign sender30_irq = receiver_temp_irq[30];
assign sender31_irq = receiver_temp_irq[31];
endmodule
| 8.239488 |
module is a simple clock crosser for control signals. It will take
// the asynchronous control signal and synchronize it to the clk domain
// attached to the clk input. It does so by passing the control signal
// through a pair of registers and then sensing the level transition from
// either hi-to-lo or lo-to-hi. *ATTENTION* This module makes the assumption
// that the control signal will always transition every time is asserted.
// i.e.:
// ____ ___________________
// -> ___| |___ and ___| |_____
//
// on the control signal will be seen as only one assertion of the control
// signal. In short, if your control could be asserted back-to-back, then
// don't use this module. You'll be losing data.
`timescale 1 ns / 1 ns
module altera_jtag_control_signal_crosser (
clk,
reset_n,
async_control_signal,
sense_pos_edge,
sync_control_signal
);
input clk;
input reset_n;
input async_control_signal;
input sense_pos_edge;
output sync_control_signal;
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
reg sync_control_signal;
wire synchronized_raw_signal;
reg edge_detector_register;
altera_std_synchronizer #(.depth(SYNC_DEPTH)) synchronizer (
.clk(clk),
.reset_n(reset_n),
.din(async_control_signal),
.dout(synchronized_raw_signal)
);
always @ (posedge clk or negedge reset_n)
if (~reset_n)
edge_detector_register <= 1'b0;
else
edge_detector_register <= synchronized_raw_signal;
always @* begin
if (sense_pos_edge)
sync_control_signal <= ~edge_detector_register & synchronized_raw_signal;
else
sync_control_signal <= edge_detector_register & ~synchronized_raw_signal;
end
endmodule
| 7.514223 |
module crosses the clock domain for a given source
module altera_jtag_src_crosser (
sink_clk,
sink_reset_n,
sink_valid,
sink_data,
src_clk,
src_reset_n,
src_valid,
src_data
);
parameter WIDTH = 8;
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
input sink_clk;
input sink_reset_n;
input sink_valid;
input [WIDTH-1:0] sink_data;
input src_clk;
input src_reset_n;
output src_valid;
output [WIDTH-1:0] src_data;
reg sink_valid_buffer;
reg [WIDTH-1:0] sink_data_buffer;
reg src_valid;
reg [WIDTH-1:0] src_data /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101 ; {-from \"*\"} CUT=ON " */;
wire synchronized_valid;
altera_jtag_control_signal_crosser #(
.SYNC_DEPTH(SYNC_DEPTH)
) crosser (
.clk(src_clk),
.reset_n(src_reset_n),
.async_control_signal(sink_valid_buffer),
.sense_pos_edge(1'b1),
.sync_control_signal(synchronized_valid)
);
always @ (posedge sink_clk or negedge sink_reset_n) begin
if (~sink_reset_n) begin
sink_valid_buffer <= 1'b0;
sink_data_buffer <= 'b0;
end else begin
sink_valid_buffer <= sink_valid;
if (sink_valid) begin
sink_data_buffer <= sink_data;
end
end //end if
end //always sink_clk
always @ (posedge src_clk or negedge src_reset_n) begin
if (~src_reset_n) begin
src_valid <= 1'b0;
src_data <= {WIDTH{1'b0}};
end else begin
src_valid <= synchronized_valid;
src_data <= synchronized_valid ? sink_data_buffer : src_data;
end
end
endmodule
| 6.867545 |
module altera_jtag_uart #(
parameter SIM_BUFFER_SIZE =100,
parameter SIM_WAIT_COUNT =1000
)(
reset,
clk,
irq,
s_dat_i,
s_sel_i,
s_addr_i,
s_cti_i,
s_stb_i,
s_cyc_i,
s_we_i,
s_dat_o,
s_ack_o,
RxD_din_sim,
RxD_wr_sim,
RxD_ready_sim
);
localparam
Dw = 32,
M_Aw = 32,
TAGw = 3,
SELw = 4;
input reset,clk;
//wishbone slave interface signals
input [Dw-1 : 0] s_dat_i;
input [SELw-1 : 0] s_sel_i;
input s_addr_i;
input [TAGw-1 : 0] s_cti_i;
input s_stb_i;
input s_cyc_i;
input s_we_i;
output irq;
output [Dw-1 : 0] s_dat_o;
output s_ack_o;
input [7:0 ] RxD_din_sim;
input RxD_wr_sim;
output RxD_ready_sim;
`ifdef MODEL_TECH
`define RUN_SIM
`endif
`ifdef VERILATOR
`define RUN_SIM
`endif
`ifdef RUN_SIM
// code for simulation with verilator/mpdelsim
// synthesis translate_off
altera_uart_simulator #(
.BUFFER_SIZE(SIM_BUFFER_SIZE),
.WAIT_COUNT(SIM_WAIT_COUNT)
)
Suart
(
.reset(reset),
.clk(clk),
.s_dat_i(s_dat_i),
.s_sel_i(s_sel_i),
.s_addr_i(s_addr_i),
.s_cti_i(s_cti_i),
.s_stb_i(s_stb_i),
.s_cyc_i(s_cyc_i),
.s_we_i(s_we_i),
.s_dat_o(s_dat_o),
.s_ack_o(s_ack_o),
.RxD_din(RxD_din_sim),
.RxD_wr(RxD_wr_sim),
.RxD_ready(RxD_ready_sim)
);
// synthesis translate_on
`else
`
// code for synthesis
altera_jtag_uart_wb_hw Juart(
.clk(clk),
.rst(reset),
.wb_irq(irq),
.dat_o(s_dat_o),
.ack_o(s_ack_o),
.adr_i(s_addr_i),
.stb_i(s_stb_i),
.cyc_i(s_cyc_i),
.we_i(s_we_i),
.dat_i(s_dat_i),
.dataavailable(),
.readyfordata()
);
assign RxD_ready_sim = 1'bX;
`endif
endmodule
| 6.505063 |
module altera_jtag_uart_wb_hw (
input clk,
rst,
output wb_irq,
output [31:0] dat_o,
output ack_o,
input adr_i,
input stb_i,
input cyc_i,
input we_i,
input [31:0] dat_i,
output dataavailable,
output readyfordata
);
wire av_waitrequest;
assign ack_o = ~av_waitrequest;
qsys_jtag_uart_0 jtag_uart_0 (
.clk (clk),
.rst_n (~rst),
.av_chipselect (stb_i),
.av_address (adr_i),
.av_read_n (~(cyc_i & ~we_i)),
.av_readdata (dat_o),
.av_write_n (~(cyc_i & we_i)),
.av_writedata (dat_i),
.av_waitrequest(av_waitrequest),
.av_irq (wb_irq),
.dataavailable (dataavailable),
.readyfordata (readyfordata)
);
endmodule
| 6.505063 |
module altera_jtag_uart_wb (
input clk,
rst,
output wb_irq,
output [31:0] dat_o,
output ack_o,
input adr_i,
input stb_i,
input cyc_i,
input we_i,
input [31:0] dat_i,
output dataavailable,
output readyfordata
);
wire av_waitrequest;
assign ack_o = ~av_waitrequest;
qsys_jtag_uart_0 jtag_uart_0 (
.clk (clk),
.rst_n (~rst),
.av_chipselect (stb_i),
.av_address (adr_i),
.av_read_n (~(cyc_i & ~we_i)),
.av_readdata (dat_o),
.av_write_n (~(cyc_i & we_i)),
.av_writedata (dat_i),
.av_waitrequest(av_waitrequest),
.av_irq (wb_irq),
.dataavailable (dataavailable),
.readyfordata (readyfordata)
);
endmodule
| 6.505063 |
module dffp (
q,
clk,
ena,
d,
clrn,
prn
);
input d;
input clk;
input clrn;
input prn;
input ena;
output q;
tri1 prn, clrn, ena;
reg q;
always @(posedge clk or negedge clrn or negedge prn)
if (prn == 1'b0) q <= 1;
else if (clrn == 1'b0) q <= 0;
else begin
if (ena == 1'b1) q <= d;
end
endmodule
| 6.992594 |
module pll_iobuf (
i,
oe,
io,
o
);
input i;
input oe;
inout io;
output o;
reg o;
always @(io) begin
o = io;
end
assign io = (oe == 1) ? i : 1'bz;
endmodule
| 6.54618 |
module MF_pll_reg (
q,
clk,
ena,
d,
clrn,
prn
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q = 0;
always @(posedge clk or negedge clrn or negedge prn) begin
if (prn == 1'b0) q <= 1;
else if (clrn == 1'b0) q <= 0;
else if ((clk == 1) & (ena == 1'b1)) q <= d;
end
endmodule
| 6.578739 |
module arm_m_cntr (
clk,
reset,
cout,
initial_value,
modulus,
time_delay
);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk) begin
if (reset) begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
cout_tmp <= tmp_cout;
end else begin
if (clk_last_value !== clk) begin
if (clk === 1'b1 && first_rising_edge) begin
first_rising_edge = 0;
tmp_cout = clk;
cout_tmp <= #(time_delay) tmp_cout;
end else if (first_rising_edge == 0) begin
if (count < modulus) count = count + 1;
else begin
count = 1;
tmp_cout = ~tmp_cout;
cout_tmp <= #(time_delay) tmp_cout;
end
end
end
end
clk_last_value = clk;
end
and (cout, cout_tmp, 1'b1);
endmodule
| 6.684371 |
module arm_scale_cntr (
clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap
);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg init;
integer count;
integer output_shift_count;
reg cout_tmp;
initial begin
count = 1;
first_rising_edge = 0;
tmp_cout = 0;
output_shift_count = 1;
end
always @(clk or reset) begin
if (init !== 1'b1) begin
clk_last_value = 0;
init = 1'b1;
end
if (reset) begin
count = 1;
output_shift_count = 1;
tmp_cout = 0;
first_rising_edge = 0;
end else if (clk_last_value !== clk) begin
if (mode == " off") tmp_cout = 0;
else if (mode == "bypass") begin
tmp_cout = clk;
first_rising_edge = 1;
end else if (first_rising_edge == 0) begin
if (clk == 1) begin
if (output_shift_count == initial_value) begin
tmp_cout = clk;
first_rising_edge = 1;
end else output_shift_count = output_shift_count + 1;
end
end else if (output_shift_count < initial_value) begin
if (clk == 1) output_shift_count = output_shift_count + 1;
end else begin
count = count + 1;
if (mode == " even" && (count == (high * 2) + 1)) tmp_cout = 0;
else if (mode == " odd" && (count == (high * 2))) tmp_cout = 0;
else if (count == (high + low) * 2 + 1) begin
tmp_cout = 1;
count = 1; // reset count
end
end
end
clk_last_value = clk;
cout_tmp <= tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule
| 6.900873 |
module ttn_m_cntr (
clk,
reset,
cout,
initial_value,
modulus,
time_delay
);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk) begin
if (reset) begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
cout_tmp <= tmp_cout;
end else begin
if (clk_last_value !== clk) begin
if (clk === 1'b1 && first_rising_edge) begin
first_rising_edge = 0;
tmp_cout = clk;
cout_tmp <= #(time_delay) tmp_cout;
end else if (first_rising_edge == 0) begin
if (count < modulus) count = count + 1;
else begin
count = 1;
tmp_cout = ~tmp_cout;
cout_tmp <= #(time_delay) tmp_cout;
end
end
end
end
clk_last_value = clk;
// cout_tmp <= #(time_delay) tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule
| 6.735089 |
module ttn_n_cntr (
clk,
reset,
cout,
modulus
);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk) begin
if (reset) begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
end else begin
if (clk == 1 && clk_last_value !== clk && first_rising_edge) begin
first_rising_edge = 0;
tmp_cout = clk;
end else if (first_rising_edge == 0) begin
if (count < modulus) count = count + 1;
else begin
count = 1;
tmp_cout = ~tmp_cout;
end
end
end
clk_last_value = clk;
end
assign cout = tmp_cout;
endmodule
| 6.545063 |
module ttn_scale_cntr (
clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap
);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg init;
integer count;
integer output_shift_count;
reg cout_tmp;
initial begin
count = 1;
first_rising_edge = 0;
tmp_cout = 0;
output_shift_count = 1;
end
always @(clk or reset) begin
if (init !== 1'b1) begin
clk_last_value = 0;
init = 1'b1;
end
if (reset) begin
count = 1;
output_shift_count = 1;
tmp_cout = 0;
first_rising_edge = 0;
end else if (clk_last_value !== clk) begin
if (mode == " off") tmp_cout = 0;
else if (mode == "bypass") begin
tmp_cout = clk;
first_rising_edge = 1;
end else if (first_rising_edge == 0) begin
if (clk == 1) begin
if (output_shift_count == initial_value) begin
tmp_cout = clk;
first_rising_edge = 1;
end else output_shift_count = output_shift_count + 1;
end
end else if (output_shift_count < initial_value) begin
if (clk == 1) output_shift_count = output_shift_count + 1;
end else begin
count = count + 1;
if (mode == " even" && (count == (high * 2) + 1)) tmp_cout = 0;
else if (mode == " odd" && (count == (high * 2))) tmp_cout = 0;
else if (count == (high + low) * 2 + 1) begin
tmp_cout = 1;
count = 1; // reset count
end
end
end
clk_last_value = clk;
cout_tmp <= tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule
| 6.82995 |
module cda_m_cntr (
clk,
reset,
cout,
initial_value,
modulus,
time_delay
);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk) begin
if (reset) begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
cout_tmp <= tmp_cout;
end else begin
if (clk_last_value !== clk) begin
if (clk === 1'b1 && first_rising_edge) begin
first_rising_edge = 0;
tmp_cout = clk;
cout_tmp <= #(time_delay) tmp_cout;
end else if (first_rising_edge == 0) begin
if (count < modulus) count = count + 1;
else begin
count = 1;
tmp_cout = ~tmp_cout;
cout_tmp <= #(time_delay) tmp_cout;
end
end
end
end
clk_last_value = clk;
// cout_tmp <= #(time_delay) tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule
| 6.852977 |
module cda_n_cntr (
clk,
reset,
cout,
modulus
);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk) begin
if (reset) begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
end else begin
if (clk == 1 && clk_last_value !== clk && first_rising_edge) begin
first_rising_edge = 0;
tmp_cout = clk;
end else if (first_rising_edge == 0) begin
if (count < modulus) count = count + 1;
else begin
count = 1;
tmp_cout = ~tmp_cout;
end
end
end
clk_last_value = clk;
end
assign cout = tmp_cout;
endmodule
| 6.89266 |
module cda_scale_cntr (
clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap
);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg init;
integer count;
integer output_shift_count;
reg cout_tmp;
initial begin
count = 1;
first_rising_edge = 0;
tmp_cout = 0;
output_shift_count = 1;
end
always @(clk or reset) begin
if (init !== 1'b1) begin
clk_last_value = 0;
init = 1'b1;
end
if (reset) begin
count = 1;
output_shift_count = 1;
tmp_cout = 0;
first_rising_edge = 0;
end else if (clk_last_value !== clk) begin
if (mode == " off") tmp_cout = 0;
else if (mode == "bypass") begin
tmp_cout = clk;
first_rising_edge = 1;
end else if (first_rising_edge == 0) begin
if (clk == 1) begin
if (output_shift_count == initial_value) begin
tmp_cout = clk;
first_rising_edge = 1;
end else output_shift_count = output_shift_count + 1;
end
end else if (output_shift_count < initial_value) begin
if (clk == 1) output_shift_count = output_shift_count + 1;
end else begin
count = count + 1;
if (mode == " even" && (count == (high * 2) + 1)) tmp_cout = 0;
else if (mode == " odd" && (count == (high * 2))) tmp_cout = 0;
else if (count == (high + low) * 2 + 1) begin
tmp_cout = 1;
count = 1; // reset count
end
end
end
clk_last_value = clk;
cout_tmp <= tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule
| 6.742481 |
module cycloneiiigl_post_divider (
clk,
reset,
cout
);
// PARAMETER
parameter dpa_divider = 1;
// INPUT PORTS
input clk;
input reset;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
integer modulus;
initial begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
modulus = (dpa_divider == 0) ? 1 : dpa_divider;
end
always @(reset or clk) begin
if (reset) begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
end else begin
if (clk == 1 && clk_last_value !== clk && first_rising_edge) begin
first_rising_edge = 0;
tmp_cout = clk;
end else if (first_rising_edge == 0) begin
if (count < modulus) count = count + 1;
else begin
count = 1;
tmp_cout = ~tmp_cout;
end
end
end
clk_last_value = clk;
end
assign cout = tmp_cout;
endmodule
| 7.203778 |
module stratix_lvds_rx (
rx_in, // input serial data
rx_fastclk, // fast clock from pll
rx_enable0,
rx_enable1,
rx_out // deserialized output data
);
// GLOBAL PARAMETER DECLARATION
parameter number_of_channels = 1;
parameter deserialization_factor = 4;
// LOCAL PARAMETER DECLARATION
parameter REGISTER_WIDTH = deserialization_factor * number_of_channels;
// INPUT PORT DECLARATION
input [number_of_channels -1 : 0] rx_in;
input rx_fastclk;
input rx_enable0;
input rx_enable1;
// OUTPUT PORT DECLARATION
output [REGISTER_WIDTH -1:0] rx_out;
// INTERNAL REGISTERS DECLARATION
reg [REGISTER_WIDTH -1 : 0] rx_shift_reg;
reg [REGISTER_WIDTH -1 : 0] rx_parallel_load_reg;
reg [REGISTER_WIDTH -1 : 0] rx_out_hold;
reg enable0_reg;
reg enable0_reg1;
reg enable0_neg;
reg enable1_reg;
// INTERNAL WIRE DECLARATION
wire rx_hold_clk;
// LOCAL INTEGER DECLARATION
integer i1;
integer x;
// INITIAL CONSTRUCT BLOCK
initial begin : INITIALIZATION
rx_shift_reg = {REGISTER_WIDTH{1'b0}};
rx_parallel_load_reg = {REGISTER_WIDTH{1'b0}};
rx_out_hold = {REGISTER_WIDTH{1'b0}};
end //INITIALIZATION
// ALWAYS CONSTRUCT BLOCK
// registering load enable signal
always @(posedge rx_fastclk) begin : LOAD_ENABLE
enable0_reg1 <= enable0_reg;
enable0_reg <= rx_enable0;
enable1_reg <= rx_enable1;
end // LOAD_ENABLE
// Fast clock (on falling edge)
always @(negedge rx_fastclk) begin : NEGEDGE_FAST_CLOCK
// load data when the registered load enable signal is high
if (enable0_neg == 1) rx_parallel_load_reg <= rx_shift_reg;
// Loading input data to shift register
for (i1 = 0; i1 < number_of_channels; i1 = i1 + 1) begin
for (x = deserialization_factor - 1; x > 0; x = x - 1)
rx_shift_reg[x+(i1*deserialization_factor)] <= rx_shift_reg[x-1+(i1*deserialization_factor)];
rx_shift_reg[i1*deserialization_factor] <= rx_in[i1];
end
enable0_neg <= enable0_reg1;
end // NEGEDGE_FAST_CLOCK
// Holding register
always @(posedge rx_hold_clk) begin : HOLD_REGISTER
rx_out_hold <= rx_parallel_load_reg;
end // HOLD_REGISTER
// CONTINOUS ASSIGNMENT
assign rx_out = rx_out_hold;
assign rx_hold_clk = enable1_reg;
endmodule
| 6.621821 |
module is used to generate the local loaden signal from fast clock for StratixV
// family. To mimic local clock divider block.
// Limitation : Only available STRATIX V family.
//
// Results expected: Loaden signal
//
//END_MODULE_NAME----------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
module stratixv_local_clk_divider (
clkin,
lloaden
);
parameter clk_divide_by =1;
input clkin;
output lloaden;
reg[4:0] cnt;
reg lloaden_tmp;
reg count;
initial
begin
cnt = 5'b00000;
count = 1'b0;
lloaden_tmp = 1'b0;
end
assign lloaden = lloaden_tmp;
always@(posedge clkin)
begin
count = 1'b1;
end
always@(negedge clkin)
begin
if(count == 1'b1)
begin
if(cnt < clk_divide_by-1)
cnt = cnt + 1;
else
cnt = 0;
end
end
always@( cnt )
begin
if( cnt == clk_divide_by-1)
lloaden_tmp = 1'b1;
else
lloaden_tmp = 1'b0;
end
endmodule
| 6.574716 |
module is used to generate the tx_outclock for Stratix
// family.
// Limitation : Only available STRATIX family.
//
// Results expected: Output clock.
//
//END_MODULE_NAME----------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
module stratix_tx_outclk (
tx_in,
tx_fastclk,
tx_enable,
tx_out
);
// GLOBAL PARAMETER DECLARATION
// No. of bits per channel (required)
parameter deserialization_factor = 4;
parameter bypass_serializer = "FALSE";
parameter invert_clock = "FALSE";
parameter use_falling_clock_edge = "FALSE";
// INPUT PORT DECLARATION
// Input data (required)
input [9 : 0] tx_in;
// Input clock (required)
input tx_fastclk;
input tx_enable;
// OUTPUT PORT DECLARATION
// Serialized data signal(required)
output tx_out;
// INTERNAL REGISTERS DECLARATION
reg [deserialization_factor -1 : 0] tx_shift_reg;
reg [deserialization_factor -1 : 0] tx_parallel_load_reg;
reg tx_out_neg;
reg enable1_reg0;
reg enable1_reg1;
reg enable1_reg2;
// INTERNAL TRI DECLARATION
tri1 tx_enable;
// LOCAL INTEGER DECLARATION
integer x;
// INITIAL CONSTRUCT BLOCK
initial
begin : INITIALIZATION
tx_parallel_load_reg = {deserialization_factor{1'b0}};
tx_shift_reg = {deserialization_factor{1'b0}};
end // INITIALIZATION
// ALWAYS CONSTRUCT BLOCK
// registering load enable signal
always @ (posedge tx_fastclk)
begin : LOAD_ENABLE_POS
if (tx_fastclk === 1'b1)
begin
enable1_reg1 <= enable1_reg0;
enable1_reg0 <= tx_enable;
end
end // LOAD_ENABLE_POS
always @ (negedge tx_fastclk)
begin : LOAD_ENABLE_NEG
enable1_reg2 <= enable1_reg1;
end // LOAD_ENABLE_NEG
// Fast Clock
always @ (posedge tx_fastclk)
begin : POSEDGE_FAST_CLOCK
if (enable1_reg2 == 1'b1)
tx_shift_reg <= tx_parallel_load_reg;
else// Shift data from shift register to tx_out
begin
for (x=deserialization_factor-1; x >0; x=x-1)
tx_shift_reg[x] <= tx_shift_reg [x-1];
end
tx_parallel_load_reg <= tx_in[deserialization_factor-1 : 0];
end // POSEDGE_FAST_CLOCK
always @ (negedge tx_fastclk)
begin : NEGEDGE_FAST_CLOCK
tx_out_neg <= tx_shift_reg[deserialization_factor-1];
end // NEGEDGE_FAST_CLOCK
// CONTINUOUS ASSIGNMENT
assign tx_out = (bypass_serializer == "TRUE") ? ((invert_clock == "FALSE") ? tx_fastclk : ~tx_fastclk) :
(use_falling_clock_edge == "TRUE") ? tx_out_neg :
tx_shift_reg[deserialization_factor-1];
endmodule
| 6.574716 |
module is used to generate the tx_outclock for StratixII
// family.
// Limitation : Only available STRATIX II family.
//
// Results expected: Output clock.
//
//END_MODULE_NAME----------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
module stratixii_tx_outclk (
tx_in,
tx_fastclk,
tx_enable,
tx_out
);
// GLOBAL PARAMETER DECLARATION
// No. of bits per channel (required)
parameter deserialization_factor = 4;
parameter bypass_serializer = "FALSE";
parameter invert_clock = "FALSE";
parameter use_falling_clock_edge = "FALSE";
// INPUT PORT DECLARATION
// Input data (required)
input [9 : 0] tx_in;
// Input clock (required)
input tx_fastclk;
input tx_enable;
// OUTPUT PORT DECLARATION
// Serialized data signal(required)
output tx_out;
// INTERNAL REGISTERS DECLARATION
reg [deserialization_factor -1 : 0] tx_shift_reg;
reg [deserialization_factor -1 : 0] tx_parallel_load_reg;
reg tx_out_reg;
reg tx_out_neg;
reg enable1_reg;
// INTERNAL TRI DECLARATION
tri1 tx_enable;
// LOCAL INTEGER DECLARATION
integer i1;
integer i2;
integer x;
// INITIAL CONSTRUCT BLOCK
initial
begin : INITIALIZATION
tx_parallel_load_reg = {deserialization_factor{1'b0}};
tx_shift_reg = {deserialization_factor{1'b0}};
enable1_reg = 0;
end // INITIALIZATION
// ALWAYS CONSTRUCT BLOCK
// Fast Clock
always @ (posedge tx_fastclk)
begin : POSEDGE_FAST_CLOCK
// registering enable1 signal
enable1_reg <= tx_enable;
if (enable1_reg == 1'b1)
tx_shift_reg <= tx_parallel_load_reg;
else// Shift data from shift register to tx_out
begin
for (x=deserialization_factor-1; x >0; x=x-1)
tx_shift_reg[x] <= tx_shift_reg [x-1];
end
tx_parallel_load_reg <= tx_in[deserialization_factor-1 : 0];
end // POSEDGE_FAST_CLOCK
always @ (negedge tx_fastclk)
begin : NEGEDGE_FAST_CLOCK
tx_out_neg <= tx_shift_reg[deserialization_factor-1];
end // NEGEDGE_FAST_CLOCK
// CONTINUOUS ASSIGNMENT
assign tx_out = (bypass_serializer == "TRUE") ? ((invert_clock == "FALSE") ? tx_fastclk : ~tx_fastclk) :
(use_falling_clock_edge == "TRUE") ? tx_out_neg :
tx_shift_reg[deserialization_factor-1];
endmodule
| 6.574716 |
module dcfifo_dffpipe (
d,
clock,
aclr,
q
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_delay = 1;
parameter lpm_width = 64;
// LOCAL PARAMETER DECLARATION
parameter delay = (lpm_delay < 2) ? 1 : lpm_delay - 1;
// INPUT PORT DECLARATION
input [lpm_width-1:0] d;
input clock;
input aclr;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
// INTERNAL REGISTERS DECLARATION
reg [(lpm_width*delay)-1:0] dffpipe;
reg [lpm_width-1:0] q;
// LOCAL INTEGER DECLARATION
// INITIAL CONSTRUCT BLOCK
initial begin
dffpipe = {(lpm_width * delay) {1'b0}};
q <= 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge clock or posedge aclr) begin
if (aclr) begin
dffpipe <= {(lpm_width * delay) {1'b0}};
q <= 0;
end else begin
if ((lpm_delay > 0) && ($time > 0)) begin
if (lpm_delay > 1) begin
{q, dffpipe} <= {dffpipe, d};
end else q <= d;
end
end
end // @(posedge aclr or posedge clock)
always @(d) begin
if (lpm_delay == 0) q <= d;
end // @(d)
endmodule
| 8.172252 |
module dcfifo_fefifo (
usedw_in,
wreq,
rreq,
clock,
aclr,
empty,
full
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_widthad = 1;
parameter lpm_numwords = 1;
parameter underflow_checking = "ON";
parameter overflow_checking = "ON";
parameter lpm_mode = "READ";
// INPUT PORT DECLARATION
input [lpm_widthad-1:0] usedw_in;
input wreq, rreq;
input clock;
input aclr;
// OUTPUT PORT DECLARATION
output empty, full;
// INTERNAL REGISTERS DECLARATION
reg [1:0] sm_empty;
reg lrreq;
reg i_empty, i_full;
// LOCAL INTEGER DECLARATION
integer almostfull;
// INITIAL CONSTRUCT BLOCK
initial begin
if ((lpm_mode != "READ") && (lpm_mode != "WRITE")) begin
$display("Error! LPM_MODE must be READ or WRITE.");
$display("Time: %0t Instance: %m", $time);
end
if ((underflow_checking != "ON") && (underflow_checking != "OFF")) begin
$display("Error! UNDERFLOW_CHECKING must be ON or OFF.");
$display("Time: %0t Instance: %m", $time);
end
if ((overflow_checking != "ON") && (overflow_checking != "OFF")) begin
$display("Error! OVERFLOW_CHECKING must be ON or OFF.");
$display("Time: %0t Instance: %m", $time);
end
sm_empty <= 2'b00;
i_empty <= 1'b1;
i_full <= 1'b0;
if (lpm_numwords >= 3) almostfull <= lpm_numwords - 3;
else almostfull <= 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge aclr) begin
sm_empty <= 2'b00;
i_empty <= 1'b1;
i_full <= 1'b0;
lrreq <= 1'b0;
end // @(posedge aclr)
always @(posedge clock) begin
if (underflow_checking == "OFF") lrreq <= rreq;
else lrreq <= rreq && ~i_empty;
if (~aclr && $time > 0) begin
if (lpm_mode == "READ") begin
casex (sm_empty)
// state_empty
2'b00: if (usedw_in != 0) sm_empty <= 2'b01;
// state_non_empty
2'b01:
if (rreq && (((usedw_in == 1) && !lrreq) || ((usedw_in == 2) && lrreq)))
sm_empty <= 2'b10;
// state_emptywait
2'b10:
if (usedw_in > 1) sm_empty <= 2'b01;
else sm_empty <= 2'b00;
default: $display("Error! Invalid sm_empty state in read mode.");
endcase
end // if (lpm_mode == "READ")
else if (lpm_mode == "WRITE")
begin
casex (sm_empty)
// state_empty
2'b00: if (wreq) sm_empty <= 2'b01;
// state_one
2'b01: if (!wreq) sm_empty <= 2'b11;
// state_non_empty
2'b11: if (wreq) sm_empty <= 2'b01;
else if (usedw_in == 0) sm_empty <= 2'b00;
default: $display("Error! Invalid sm_empty state in write mode.");
endcase
end // if (lpm_mode == "WRITE")
if (~aclr && (usedw_in >= almostfull) && ($time > 0)) i_full <= 1'b1;
else i_full <= 1'b0;
end // if (~aclr && $time > 0)
end // @(posedge clock)
always @(sm_empty) begin
i_empty <= !sm_empty[0];
end
// @(sm_empty)
// CONTINOUS ASSIGNMENT
assign empty = i_empty;
assign full = i_full;
endmodule
| 6.754214 |
module dcfifo ( data, rdclk, wrclk, aclr, rdreq, wrreq,
rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_widthu = 1;
parameter lpm_numwords = 2;
parameter delay_rdusedw = 1;
parameter delay_wrusedw = 1;
parameter rdsync_delaypipe = 0;
parameter wrsync_delaypipe = 0;
parameter intended_device_family = "Stratix";
parameter lpm_showahead = "OFF";
parameter underflow_checking = "ON";
parameter overflow_checking = "ON";
parameter clocks_are_synchronized = "FALSE";
parameter use_eab = "ON";
parameter add_ram_output_register = "OFF";
parameter lpm_hint = "USE_EAB=ON";
parameter lpm_type = "dcfifo";
parameter add_usedw_msb_bit = "OFF";
parameter read_aclr_synch = "OFF";
parameter write_aclr_synch = "OFF";
// LOCAL_PARAMETERS_BEGIN
parameter add_width = 1;
parameter ram_block_type = "AUTO";
// LOCAL_PARAMETERS_END
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input rdclk;
input wrclk;
input aclr;
input rdreq;
input wrreq;
// OUTPUT PORT DECLARATION
output rdfull;
output wrfull;
output rdempty;
output wrempty;
output [lpm_widthu-1:0] rdusedw;
output [lpm_widthu-1:0] wrusedw;
output [lpm_width-1:0] q;
// INTERNAL WIRE DECLARATION
wire w_rdfull;
wire w_wrfull;
wire w_rdempty;
wire w_wrempty;
wire [lpm_widthu-1:0] w_rdusedw;
wire [lpm_widthu-1:0] w_wrusedw;
wire [lpm_width-1:0] w_q;
// INTERNAL TRI DECLARATION
tri0 aclr;
dcfifo_mixed_widths DCFIFO_MW (
.data (data),
.rdclk (rdclk),
.wrclk (wrclk),
.aclr (aclr),
.rdreq (rdreq),
.wrreq (wrreq),
.rdfull (w_rdfull),
.wrfull (w_wrfull),
.rdempty (w_rdempty),
.wrempty (w_wrempty),
.rdusedw (w_rdusedw),
.wrusedw (w_wrusedw),
.q (w_q) );
defparam
DCFIFO_MW.lpm_width = lpm_width,
DCFIFO_MW.lpm_widthu = lpm_widthu,
DCFIFO_MW.lpm_width_r = lpm_width,
DCFIFO_MW.lpm_widthu_r = lpm_widthu,
DCFIFO_MW.lpm_numwords = lpm_numwords,
DCFIFO_MW.delay_rdusedw = delay_rdusedw,
DCFIFO_MW.delay_wrusedw = delay_wrusedw,
DCFIFO_MW.rdsync_delaypipe = rdsync_delaypipe,
DCFIFO_MW.wrsync_delaypipe = wrsync_delaypipe,
DCFIFO_MW.intended_device_family = intended_device_family,
DCFIFO_MW.lpm_showahead = lpm_showahead,
DCFIFO_MW.underflow_checking = underflow_checking,
DCFIFO_MW.overflow_checking = overflow_checking,
DCFIFO_MW.clocks_are_synchronized = clocks_are_synchronized,
DCFIFO_MW.use_eab = use_eab,
DCFIFO_MW.add_ram_output_register = add_ram_output_register,
DCFIFO_MW.add_width = add_width,
DCFIFO_MW.ram_block_type = ram_block_type,
DCFIFO_MW.add_usedw_msb_bit = add_usedw_msb_bit,
DCFIFO_MW.read_aclr_synch = read_aclr_synch,
DCFIFO_MW.write_aclr_synch = write_aclr_synch,
DCFIFO_MW.lpm_hint = lpm_hint;
// CONTINOUS ASSIGNMENT
assign rdfull = w_rdfull;
assign wrfull = w_wrfull;
assign rdempty = w_rdempty;
assign wrempty = w_wrempty;
assign rdusedw = w_rdusedw;
assign wrusedw = w_wrusedw;
assign q = w_q;
endmodule
| 7.370534 |
module altshift_taps (
shiftin,
clock,
clken,
aclr,
shiftout,
taps
);
// PARAMETER DECLARATION
parameter number_of_taps = 4; // Specifies the number of regularly spaced
// taps along the shift register
parameter tap_distance = 3; // Specifies the distance between the
// regularly spaced taps in clock cycles
// This number translates to the number of
// memory words that will be needed
parameter width = 8; // Specifies the width of the input pattern
parameter power_up_state = "CLEARED";
parameter lpm_type = "altshift_taps";
parameter intended_device_family = "Stratix";
parameter lpm_hint = "UNUSED";
// SIMULATION_ONLY_PARAMETERS_BEGIN
// Following parameters are used as constant
parameter RAM_WIDTH = width * number_of_taps;
parameter TOTAL_TAP_DISTANCE = number_of_taps * tap_distance;
// SIMULATION_ONLY_PARAMETERS_END
// INPUT PORT DECLARATION
input [width-1:0] shiftin; // Data input to the shifter
input clock; // Positive-edge triggered clock
input clken; // Clock enable for the clock port
input aclr; // Asynchronous clear port
// OUTPUT PORT DECLARATION
output [width-1:0] shiftout; // Output from the end of the shift
// register
output [RAM_WIDTH-1:0] taps; // Output from the regularly spaced taps
// along the shift register
// INTERNAL REGISTERS DECLARATION
reg [ width-1:0] shiftout;
reg [RAM_WIDTH-1:0] taps;
reg [ width-1:0] shiftout_tmp;
reg [RAM_WIDTH-1:0] taps_tmp;
reg [ width-1:0] contents [0:TOTAL_TAP_DISTANCE-1];
// LOCAL INTEGER DECLARATION
integer head; // pointer to memory
integer i; // for loop index
integer j; // for loop index
integer k; // for loop index
integer place;
// TRI STATE DECLARATION
tri1 clken;
tri0 aclr;
// INITIAL CONSTRUCT BLOCK
initial begin
head = 0;
if (power_up_state == "CLEARED") begin
shiftout = 0;
shiftout_tmp = 0;
for (i = 0; i < TOTAL_TAP_DISTANCE; i = i + 1) begin
contents[i] = 0;
end
for (j = 0; j < RAM_WIDTH; j = j + 1) begin
taps[j] = 0;
taps_tmp[j] = 0;
end
end
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge clock or posedge aclr) begin
if (aclr == 1'b1) begin
for (k = 0; k < TOTAL_TAP_DISTANCE; k = k + 1) contents[k] = 0;
head = 0;
shiftout_tmp = 0;
taps_tmp = 0;
end else begin
if (clken == 1'b1) begin
contents[head] = shiftin;
head = (head + 1) % TOTAL_TAP_DISTANCE;
shiftout_tmp = contents[head];
taps_tmp = 0;
for (k = 0; k < number_of_taps; k = k + 1) begin
place = (((number_of_taps - k - 1) * tap_distance) + head) % TOTAL_TAP_DISTANCE;
taps_tmp = taps_tmp | (contents[place] << (k * width));
end
end
end
end
always @(shiftout_tmp) begin
shiftout <= shiftout_tmp;
end
always @(taps_tmp) begin
taps <= taps_tmp;
end
endmodule
| 7.397161 |
module altsquare (
data,
clock,
ena,
aclr,
result
);
// GLOBAL PARAMETER DECLARATION
parameter data_width = 1;
parameter result_width = 1;
parameter pipeline = 0;
parameter representation = "UNSIGNED";
parameter result_alignment = "LSB";
parameter lpm_hint = "UNUSED";
parameter lpm_type = "altsquare";
// INPUT PORT DECLARATION
input [data_width - 1 : 0] data;
input clock;
input ena;
input aclr;
// OUTPUT PORT DECLARATION
output [result_width - 1 : 0] result;
// INTERNAL REGISTER DECLARATION
reg [result_width - 1 : 0] stage_values[pipeline+1 : 0];
reg [data_width - 1 : 0] pos_data_value;
reg [(2*data_width) - 1 : 0] temp_value;
// LOCAL INTEGER DECLARATION
integer i;
// INTERNAL WIRE DECLARATION
wire i_clock;
wire i_aclr;
wire i_clken;
// INTERNAL TRI DECLARATION
tri0 aclr;
tri1 clock;
tri1 clken;
buf (i_clock, clock);
buf (i_aclr, aclr);
buf (i_clken, ena);
// INITIAL CONSTRUCT BLOCK
initial begin : INITIALIZE
if (data_width < 1) begin
$display("data_width (%d) must be greater than 0.(ERROR)\n", data_width);
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (result_width < 1) begin
$display("result_width (%d) must be greater than 0.(ERROR)\n", result_width);
$display("Time: %0t Instance: %m", $time);
$finish;
end
end // INITIALIZE
// ALWAYS CONSTRUCT BLOCK
always @(data or i_aclr) begin
if (i_aclr) // clear the pipeline
for (i = 0; i <= pipeline; i = i + 1) stage_values[i] = 'b0;
else begin
if ((representation == "SIGNED") && (data[data_width-1] == 1)) pos_data_value = (~data) + 1;
else pos_data_value = data;
if ((result_width < (2 * data_width)) && (result_alignment == "MSB")) begin
temp_value = pos_data_value * pos_data_value;
stage_values[pipeline] = temp_value[(2*data_width)-1 : (2*data_width)-result_width];
end else stage_values[pipeline] = pos_data_value * pos_data_value;
end
end
// Pipeline model
always @(posedge i_clock) begin
if (!i_aclr && i_clken == 1) begin
for (i = 0; i < pipeline + 1; i = i + 1)
if (i < pipeline) stage_values[i] <= stage_values[i+1];
end
end
// CONTINOUS ASSIGNMENT
assign result = stage_values[0];
endmodule
| 7.030281 |
module altera_std_synchronizer (
clk,
reset_n,
din,
dout
);
// GLOBAL PARAMETER DECLARATION
parameter depth = 3; // This value must be >= 2 !
// INPUT PORT DECLARATION
input clk;
input reset_n;
input din;
// OUTPUT PORT DECLARATION
output dout;
// QuartusII synthesis directives:
// 1. Preserve all registers ie. do not touch them.
// 2. Do not merge other flip-flops with synchronizer flip-flops.
// QuartusII TimeQuest directives:
// 1. Identify all flip-flops in this module as members of the synchronizer
// to enable automatic metastability MTBF analysis.
// 2. Cut all timing paths terminating on data input pin of the first flop din_s1.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON; -name SDC_STATEMENT \"set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]\" "} *)
reg din_s1;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
//synthesis translate_off
initial begin
if (depth < 2) begin
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
end
end
// the first synchronizer register is either a simple D flop for synthesis
// and non-metastable simulation or a D flop with a method to inject random
// metastable events resulting in random delay of [0,1] cycles
`ifdef __ALTERA_STD__METASTABLE_SIM
reg [31:0] RANDOM_SEED = 123456;
wire next_din_s1;
wire dout;
reg din_last;
reg random;
event metastable_event; // hook for debug monitoring
initial begin
$display("%m: Info: Metastable event injection simulation mode enabled");
end
always @(posedge clk) begin
if (reset_n == 0) random <= $random(RANDOM_SEED);
else random <= $random;
end
assign next_din_s1 = (din_last ^ din) ? random : din;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) din_last <= 1'b0;
else din_last <= din;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) din_s1 <= 1'b0;
else din_s1 <= next_din_s1;
end
`else
//synthesis translate_on
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) din_s1 <= 1'b0;
else din_s1 <= din;
end
//synthesis translate_off
`endif
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
always @(*) begin
if (reset_n && (din_last != din) && (random != din)) begin
$display("%m: Verbose Info: metastable event @ time %t", $time);
->metastable_event;
end
end
`endif
//synthesis translate_on
// the remaining synchronizer registers form a simple shift register
// of length depth-1
generate
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) dreg <= {depth - 1{1'b0}};
else dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) dreg <= {depth - 1{1'b0}};
else dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
assign dout = dreg[depth-2];
endmodule
| 7.854645 |
module altera_std_synchronizer_bundle (
clk,
reset_n,
din,
dout
);
// GLOBAL PARAMETER DECLARATION
parameter width = 1;
parameter depth = 3;
// INPUT PORT DECLARATION
input clk;
input reset_n;
input [width-1:0] din;
// OUTPUT PORT DECLARATION
output [width-1:0] dout;
generate
genvar i;
for (i = 0; i < width; i = i + 1) begin : sync
altera_std_synchronizer #(
.depth(depth)
) u (
.clk(clk),
.reset_n(reset_n),
.din(din[i]),
.dout(dout[i])
);
end
endgenerate
endmodule
| 7.854645 |
module alt_cal_sv (
busy,
clock,
dprio_addr,
dprio_busy,
dprio_datain,
dprio_dataout,
dprio_rden,
dprio_wren,
quad_addr,
remap_addr,
reset,
start,
testbuses
) /* synthesis synthesis_clearbox=1 */;
parameter number_of_channels = 1;
parameter channel_address_width = 1;
parameter sim_model_mode = "TRUE";
parameter lpm_type = "alt_cal_sv";
parameter lpm_hint = "UNUSED";
parameter sample_length = 8'd100;
parameter pma_base_address = 12'h0;
localparam COUNTER_WIDTH = 9;
output busy;
input clock;
output [15:0] dprio_addr;
input dprio_busy;
input [15:0] dprio_datain;
output [15:0] dprio_dataout;
output dprio_rden;
output dprio_wren;
output [8:0] quad_addr;
input [11:0] remap_addr;
input reset;
input start;
input [7:0] testbuses; // always 8 bits - muxing done in the 'B'
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
reg [ 0:0] p0addr_sim;
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
reg [COUNTER_WIDTH-1:0] sim_counter_reg;
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=HIGH"} *)
reg [ 0:0] first_run;
wire [COUNTER_WIDTH-1:0] wire_next_scount_num_dataa;
wire [COUNTER_WIDTH-1:0] wire_next_scount_num_datab;
wire [COUNTER_WIDTH-1:0] wire_next_scount_num_result;
wire [ 0:0] busy_sim;
wire [ 0:0] sim_activator;
wire [ 0:0] sim_counter_and;
wire [COUNTER_WIDTH-1:0] sim_counter_next;
wire [ 0:0] sim_counter_or;
// synopsys translate_off
initial begin
p0addr_sim[0:0] = 0;
first_run = 1;
end
// synopsys translate_on
always @(posedge clock) p0addr_sim[0:0] <= 1'b1;
// synopsys translate_off
initial sim_counter_reg = 0;
// synopsys translate_on
always @(posedge clock) begin
sim_counter_reg <= ({COUNTER_WIDTH{(~start & sim_activator)}} & (({COUNTER_WIDTH{(p0addr_sim | ((~ sim_counter_and) & sim_counter_or))}} & sim_counter_next) | ({COUNTER_WIDTH{sim_counter_and}} & sim_counter_reg)) & {COUNTER_WIDTH{~(first_run & reset)}}) | ({COUNTER_WIDTH{reset & ~first_run}});
if (first_run == 1'b1) begin
first_run <= ~sim_counter_and;
end else begin
first_run <= 1'b0;
end
end
assign wire_next_scount_num_result = wire_next_scount_num_dataa + wire_next_scount_num_datab;
assign wire_next_scount_num_dataa = sim_counter_reg, wire_next_scount_num_datab = 9'b0001;
assign busy = busy_sim,
busy_sim = (~reset & p0addr_sim & (~sim_counter_and)),
dprio_addr = {16{1'b0}},
dprio_dataout = {16{1'b0}},
dprio_rden = 1'b0,
dprio_wren = 1'b0,
quad_addr = {9{1'b0}},
sim_activator = p0addr_sim,
sim_counter_and = &sim_counter_reg,
sim_counter_next = wire_next_scount_num_result,
sim_counter_or = |sim_counter_reg;
endmodule
| 6.528521 |
module alt_cal_av (
busy,
clock,
dprio_addr,
dprio_busy,
dprio_datain,
dprio_dataout,
dprio_rden,
dprio_wren,
quad_addr,
remap_addr,
reset,
start,
testbuses
) /* synthesis synthesis_clearbox=1 */;
parameter number_of_channels = 1;
parameter channel_address_width = 1;
parameter sim_model_mode = "TRUE";
parameter lpm_type = "alt_cal_av";
parameter lpm_hint = "UNUSED";
parameter sample_length = 8'd100;
parameter pma_base_address = 12'h0;
localparam COUNTER_WIDTH = 9;
output busy;
input clock;
output [15:0] dprio_addr;
input dprio_busy;
input [15:0] dprio_datain;
output [15:0] dprio_dataout;
output dprio_rden;
output dprio_wren;
output [8:0] quad_addr;
input [11:0] remap_addr;
input reset;
input start;
input [7:0] testbuses; // always 8 bits - muxing done in the 'B'
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
reg [ 0:0] p0addr_sim;
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
reg [COUNTER_WIDTH-1:0] sim_counter_reg;
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=HIGH"} *)
reg [ 0:0] first_run;
wire [COUNTER_WIDTH-1:0] wire_next_scount_num_dataa;
wire [COUNTER_WIDTH-1:0] wire_next_scount_num_datab;
wire [COUNTER_WIDTH-1:0] wire_next_scount_num_result;
wire [ 0:0] busy_sim;
wire [ 0:0] sim_activator;
wire [ 0:0] sim_counter_and;
wire [COUNTER_WIDTH-1:0] sim_counter_next;
wire [ 0:0] sim_counter_or;
// synopsys translate_off
initial begin
p0addr_sim[0:0] = 0;
first_run = 1;
end
// synopsys translate_on
always @(posedge clock) p0addr_sim[0:0] <= 1'b1;
// synopsys translate_off
initial sim_counter_reg = 0;
// synopsys translate_on
always @(posedge clock) begin
sim_counter_reg <= ({COUNTER_WIDTH{(~start & sim_activator)}} & (({COUNTER_WIDTH{(p0addr_sim | ((~ sim_counter_and) & sim_counter_or))}} & sim_counter_next) | ({COUNTER_WIDTH{sim_counter_and}} & sim_counter_reg)) & {COUNTER_WIDTH{~(first_run & reset)}}) | ({COUNTER_WIDTH{reset & ~first_run}});
if (first_run == 1'b1) begin
first_run <= ~sim_counter_and;
end else begin
first_run <= 1'b0;
end
end
assign wire_next_scount_num_result = wire_next_scount_num_dataa + wire_next_scount_num_datab;
assign wire_next_scount_num_dataa = sim_counter_reg, wire_next_scount_num_datab = 9'b0001;
assign busy = busy_sim,
busy_sim = (~reset & p0addr_sim & (~sim_counter_and)),
dprio_addr = {16{1'b0}},
dprio_dataout = {16{1'b0}},
dprio_rden = 1'b0,
dprio_wren = 1'b0,
quad_addr = {9{1'b0}},
sim_activator = p0addr_sim,
sim_counter_and = &sim_counter_reg,
sim_counter_next = wire_next_scount_num_result,
sim_counter_or = |sim_counter_reg;
endmodule
| 6.668376 |
module alt_aeq_s4 #(
parameter show_errors = "NO", // "YES" = show errors; anything else = do not show errors
parameter radce_hflck = 15'h0000, // settings for RADCE_HFLCK CRAM settings - get values from ICD
parameter radce_lflck = 15'h0000, // settings for RADCE_LFLCK CRAM settings - get values from ICD
parameter use_hw_conv_det = 1'b0, // use hardware convergence detect macro if set to 1'b1 - else, default to soft ip.
parameter number_of_channels = 5,
parameter channel_address_width = 3,
parameter lpm_type = "alt_aeq_s4",
parameter lpm_hint = "UNUSED"
) (
input reconfig_clk,
input aclr,
input calibrate, // 'start'
input shutdown, // shut down (put channel(s) in standby)
input all_channels,
input [channel_address_width-1:0] logical_channel_address,
input [11:0] remap_address,
output [8:0] quad_address,
input [number_of_channels-1:0] adce_done,
output busy,
output reg [number_of_channels-1:0] adce_standby, // put channels into standby - to RX PMA
input adce_continuous,
output adce_cal_busy,
// multiplexed signals for interfacing with DPRIO
input dprio_busy,
input [15:0] dprio_in,
output dprio_wren,
output dprio_rden,
output [15:0] dprio_addr, // increase to 16 bits
output [15:0] dprio_data,
output [ 3:0] eqout,
output timeout,
input [7*number_of_channels-1:0] testbuses,
output [4*number_of_channels-1:0] testbus_sels,
// SHOW_ERRORS option
output [number_of_channels-1:0] conv_error,
output [number_of_channels-1:0] error
// end SHOW_ERRORS option
);
//********************************************************************************
// DECLARATIONS
//********************************************************************************
reg [7:0] busy_counter; // 256 cycles
assign dprio_addr = {16{1'b0}},
dprio_data = {16{1'b0}},
dprio_rden = 1'b0,
dprio_wren = 1'b0,
quad_address = {9{1'b0}},
busy = |busy_counter,
adce_cal_busy = |busy_counter[7:4], // only for the first half of the timer
eqout = {4{1'b0}},
error = {number_of_channels{1'b0}},
conv_error = {number_of_channels{1'b0}},
timeout = 1'b0,
testbus_sels = {4 * number_of_channels{1'b0}};
always @(posedge reconfig_clk) begin
if (aclr) begin
busy_counter <= 8'h0;
adce_standby[logical_channel_address] <= 1'b0;
end else if (calibrate) begin
busy_counter <= 8'hff;
adce_standby <= {number_of_channels{1'b0}};
end else if (shutdown) begin
busy_counter <= 8'hf;
adce_standby[logical_channel_address] <= 1'b1;
end else if (busy) begin // if not 0, keep decrementing
busy_counter <= busy_counter - 1'b1;
end
end
endmodule
| 7.856784 |
module sld_virtual_jtag_basic (
jtag_state_sdr,
jtag_state_sirs,
ir_out,
jtag_state_sir,
jtag_state_cdr,
jtag_state_e2dr,
tms,
jtag_state_sdrs,
jtag_state_tlr,
ir_in,
virtual_state_sdr,
tdi,
jtag_state_uir,
jtag_state_cir,
virtual_state_cdr,
virtual_state_uir,
virtual_state_e2dr,
jtag_state_e2ir,
virtual_state_cir,
jtag_state_pir,
jtag_state_udr,
virtual_state_udr,
tdo,
jtag_state_e1dr,
jtag_state_rti,
virtual_state_pdr,
virtual_state_e1dr,
jtag_state_e1ir,
jtag_state_pdr,
tck
);
parameter lpm_hint = "UNUSED";
parameter sld_sim_action = "UNUSED";
parameter sld_instance_index = 0;
parameter sld_ir_width = 1;
parameter sld_sim_n_scan = 0;
parameter sld_mfg_id = 0;
parameter sld_version = 0;
parameter sld_type_id = 0;
parameter lpm_type = "sld_virtual_jtag_basic";
parameter sld_auto_instance_index = "NO";
parameter sld_sim_total_length = 0;
output jtag_state_sdr;
output jtag_state_sirs;
input [sld_ir_width-1:0] ir_out;
output jtag_state_sir;
output jtag_state_cdr;
output jtag_state_e2dr;
output tms;
output jtag_state_sdrs;
output jtag_state_tlr;
output [sld_ir_width-1:0] ir_in;
output virtual_state_sdr;
output tdi;
output jtag_state_uir;
output jtag_state_cir;
output virtual_state_cdr;
output virtual_state_uir;
output virtual_state_e2dr;
output jtag_state_e2ir;
output virtual_state_cir;
output jtag_state_pir;
output jtag_state_udr;
output virtual_state_udr;
input tdo;
output jtag_state_e1dr;
output jtag_state_rti;
output virtual_state_pdr;
output virtual_state_e1dr;
output jtag_state_e1ir;
output jtag_state_pdr;
output tck;
endmodule
| 6.971215 |
module altsource_probe (
jtag_state_sdr,
ir_in,
jtag_state_cir,
jtag_state_udr,
jtag_state_e1dr,
source_clk,
probe,
source,
ir_out,
jtag_state_cdr,
jtag_state_tlr,
tdi,
jtag_state_uir,
source_ena,
tdo,
clrn,
raw_tck,
usr1,
ena
);
parameter lpm_hint = "UNUSED";
parameter sld_instance_index = 0;
parameter source_initial_value = "0";
parameter sld_ir_width = 4;
parameter probe_width = 1;
parameter source_width = 1;
parameter instance_id = "UNUSED";
parameter lpm_type = "altsource_probe";
parameter sld_auto_instance_index = "YES";
parameter SLD_NODE_INFO = 4746752;
parameter enable_metastability = "NO";
input jtag_state_sdr;
input [sld_ir_width-1:0] ir_in;
input jtag_state_cir;
input jtag_state_udr;
input jtag_state_e1dr;
input source_clk;
input [probe_width-1:0] probe;
output [source_width-1:0] source;
output [sld_ir_width-1:0] ir_out;
input jtag_state_cdr;
input jtag_state_tlr;
input tdi;
input jtag_state_uir;
input source_ena;
output tdo;
input clrn;
input raw_tck;
input usr1;
input ena;
endmodule
| 8.012029 |
module altera_mgmt_reset (
input clk,
input reset,
input mgmt_data,
input mgmt_valid,
output mgmt_ready,
output reg agent_reset
);
//reset (the input) forces agent_reset active (high) immediately
//system console strobes 1 (data & valid both 1) to enable reset
//or strobes 0 (data=0, valid=1) to hold agent in reset
//assume data and valid synchronous to clk
always @(posedge clk or posedge reset) begin
if (reset) agent_reset <= 1'b1;
else if (mgmt_valid) agent_reset <= ~mgmt_data;
end
assign mgmt_ready = 1'b1;
endmodule
| 6.656785 |
module altera_modular_adc_conduit_splitter (
input clk,
input rst_n,
input clk_in_pll_locked,
output clk_in_pll_locked_out_1,
output clk_in_pll_locked_out_2
);
//-----------------------------------------------------------------------------//
// This core is specifically for splitter adc pll locked signal from export
// to 2 ADC's pll lock input
//-----------------------------------------------------------------------------//
assign clk_in_pll_locked_out_1 = clk_in_pll_locked;
assign clk_in_pll_locked_out_2 = clk_in_pll_locked;
endmodule
| 6.935893 |
module altera_modular_adc_control_avrg_fifo (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q
);
input clock;
input [11:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [11:0] q;
wire sub_wire0;
wire sub_wire1;
wire [11:0] sub_wire2;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [11:0] q = sub_wire2[11:0];
scfifo scfifo_component (
.clock(clock),
.data(data),
.rdreq(rdreq),
.sclr(sclr),
.wrreq(wrreq),
.empty(sub_wire0),
.full(sub_wire1),
.q(sub_wire2),
.aclr(),
.almost_empty(),
.almost_full(),
.usedw()
);
defparam scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "MAX 10",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M9K", scfifo_component.lpm_numwords = 64,
scfifo_component.lpm_showahead = "OFF", scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 12, scfifo_component.lpm_widthu = 6,
scfifo_component.overflow_checking = "ON", scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
| 6.935893 |
module altera_modular_adc_dual_sync (
input clk,
input rst_n,
input sync_1_valid,
input sync_2_valid,
output sync_1_ready,
output sync_2_ready
);
wire sync_ready;
assign sync_ready = sync_1_valid & sync_2_valid;
assign sync_1_ready = sync_ready;
assign sync_2_ready = sync_ready;
endmodule
| 6.935893 |
module altera_modular_adc_response_merge (
input clk,
input rst_n,
input rsp_in_1_valid,
input [ 4:0] rsp_in_1_channel,
input [11:0] rsp_in_1_data,
input rsp_in_1_sop,
input rsp_in_1_eop,
input rsp_in_2_valid,
input [ 4:0] rsp_in_2_channel,
input [11:0] rsp_in_2_data,
input rsp_in_2_sop,
input rsp_in_2_eop,
output rsp_out_valid,
output [ 4:0] rsp_out_channel,
output [23:0] rsp_out_data,
output rsp_out_sop,
output rsp_out_eop
);
//--------------------------------------------------------------------------------------------------//
// rsp_in_1_valid and rsp_in_2_valid is guaranteed to be assert/de-assert at the same time (design
// requirement) of the dual adc synchronization in the control core
// Except data, other signal roles of response 1 and 2 is same
//--------------------------------------------------------------------------------------------------//
assign rsp_out_valid = rsp_in_1_valid;
assign rsp_out_channel = rsp_in_1_channel;
assign rsp_out_data = {rsp_in_2_data, rsp_in_1_data};
assign rsp_out_sop = rsp_in_1_sop;
assign rsp_out_eop = rsp_in_1_eop;
endmodule
| 6.935893 |
module altera_modular_adc_sample_store_ram #(
parameter DATA_WIDTH = 16
) (
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q);
input clock;
input [DATA_WIDTH-1:0] data;
input [5:0] rdaddress;
input rden;
input [5:0] wraddress;
input wren;
output [DATA_WIDTH-1:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [DATA_WIDTH-1:0] sub_wire0;
wire [DATA_WIDTH-1:0] q = sub_wire0[DATA_WIDTH-1:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.rden_b (rden),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({DATA_WIDTH{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "MAX 10",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 64,
altsyncram_component.numwords_b = 64,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.rdcontrol_reg_b = "CLOCK0",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
altsyncram_component.widthad_a = 6,
altsyncram_component.widthad_b = 6,
altsyncram_component.width_a = DATA_WIDTH,
altsyncram_component.width_b = DATA_WIDTH,
altsyncram_component.width_byteena_a = 1;
endmodule
| 6.935893 |
module altera_modular_adc_sequencer_csr (
input clk,
input rst_n,
input addr,
input read,
input write,
input [31:0] writedata,
input clr_run,
output reg [31:0] readdata,
output reg run,
output reg sw_clr_run,
output con_mode,
output single_mode,
output recab_mode
);
reg [ 2:0] mode;
wire cmd_addr;
wire cmd_wr_en;
wire cmd_rd_en;
wire [31:0] cmd_internal;
wire [31:0] readdata_nxt;
//--------------------------------------------------------------------------------------------//
// address decode
//--------------------------------------------------------------------------------------------//
assign cmd_addr = (addr == 1'b0);
//--------------------------------------------------------------------------------------------//
// write enable
//--------------------------------------------------------------------------------------------//
assign cmd_wr_en = cmd_addr & write;
//--------------------------------------------------------------------------------------------//
// read enable
//--------------------------------------------------------------------------------------------//
assign cmd_rd_en = cmd_addr & read;
//--------------------------------------------------------------------------------------------//
// mode register bits
//--------------------------------------------------------------------------------------------//
always @(posedge clk or negedge rst_n) begin
if (!rst_n) mode <= 3'h0;
else if (cmd_wr_en & ~run) mode <= writedata[3:1];
end
//--------------------------------------------------------------------------------------------//
// run register bit
//--------------------------------------------------------------------------------------------//
always @(posedge clk or negedge rst_n) begin
if (!rst_n) run <= 1'b0;
else if (clr_run) run <= 1'b0;
else if (cmd_wr_en & writedata[0]) run <= 1'b1;
end
//--------------------------------------------------------------------------------------------//
// Logic to detect SW perform a clear on the run bit
//--------------------------------------------------------------------------------------------//
always @(posedge clk or negedge rst_n) begin
if (!rst_n) sw_clr_run <= 1'b0;
else if (clr_run) sw_clr_run <= 1'b0;
else if (run & con_mode & cmd_wr_en & ~writedata[0]) sw_clr_run <= 1'b1;
end
//--------------------------------------------------------------------------------------------//
// Avalon read data path
//--------------------------------------------------------------------------------------------//
assign cmd_internal = {28'h0, mode, run};
assign readdata_nxt = cmd_internal & {32{cmd_rd_en}};
always @(posedge clk or negedge rst_n) begin
if (!rst_n) readdata <= 32'h0;
else readdata <= readdata_nxt;
end
//--------------------------------------------------------------------------------------------//
// Mode decoding
//--------------------------------------------------------------------------------------------//
assign con_mode = (mode == 3'b000);
assign single_mode = (mode == 3'b001);
assign recab_mode = (mode == 3'b111);
endmodule
| 6.935893 |
module altera_msgdma_prefetcher_fifo #(
parameter RESPONSE_FIFO_WIDTH = 64,
parameter RESPONSE_FIFO_DEPTH = 256,
parameter RESPONSE_FIFO_DEPTH_LOG2 = 7,
parameter LATENCY = 2
) (
input clk,
input areset,
input sreset,
input [RESPONSE_FIFO_WIDTH-1:0] wr_data,
input wrreq,
input rdreq,
output full,
output [RESPONSE_FIFO_WIDTH-1:0] rd_data
);
reg [RESPONSE_FIFO_DEPTH_LOG2-1:0] write_address;
reg [RESPONSE_FIFO_DEPTH_LOG2-1:0] read_address;
reg [RESPONSE_FIFO_DEPTH_LOG2:0] internal_used;
wire internal_full;
//wire internal_empty;
wire [(RESPONSE_FIFO_WIDTH/8)-1:0] write_byteenables;
always @(posedge clk or posedge areset) begin
if (areset) begin
write_address <= 0;
end else begin
if (sreset) begin
write_address <= 0;
end else if (wrreq == 1) begin
write_address <= write_address + 1'b1;
end
end
end
always @(posedge clk or posedge areset) begin
if (areset) begin
read_address <= 0;
end else begin
if (sreset) begin
read_address <= 0;
end else if (rdreq == 1) begin
read_address <= read_address + 1'b1;
end
end
end
assign write_byteenables = {(RESPONSE_FIFO_WIDTH / 8) {1'b1}};
// TODO: Change this to an inferrered RAM when Quartus II supports byte enables for inferred RAM
altsyncram the_dp_ram (
.clock0(clk),
.wren_a(wrreq),
.byteena_a(write_byteenables),
.data_a(wr_data),
.address_a(write_address),
.q_b(rd_data),
.address_b(read_address)
);
defparam the_dp_ram.operation_mode = "DUAL_PORT"; // simple dual port (one read, one write port)
defparam the_dp_ram.lpm_type = "altsyncram";
defparam the_dp_ram.read_during_write_mode_mixed_ports = "DONT_CARE";
defparam the_dp_ram.power_up_uninitialized = "TRUE";
defparam the_dp_ram.byte_size = 8;
defparam the_dp_ram.width_a = RESPONSE_FIFO_WIDTH;
defparam the_dp_ram.width_b = RESPONSE_FIFO_WIDTH;
defparam the_dp_ram.widthad_a = RESPONSE_FIFO_DEPTH_LOG2;
defparam the_dp_ram.widthad_b = RESPONSE_FIFO_DEPTH_LOG2;
defparam the_dp_ram.width_byteena_a = (RESPONSE_FIFO_WIDTH/8);
defparam the_dp_ram.numwords_a = RESPONSE_FIFO_DEPTH;
defparam the_dp_ram.numwords_b = RESPONSE_FIFO_DEPTH;
defparam the_dp_ram.address_reg_b = "CLOCK0";
defparam the_dp_ram.outdata_reg_b = (LATENCY == 2)? "CLOCK0" : "UNREGISTERED";
always @(posedge clk or posedge areset) begin
if (areset) begin
internal_used <= 0;
end else begin
if (sreset) begin
internal_used <= 0;
end else begin
case ({
wrreq, rdreq
})
2'b01: internal_used <= internal_used - 1'b1;
2'b10: internal_used <= internal_used + 1'b1;
default: internal_used <= internal_used;
endcase
end
end
end
//assign internal_empty = (read_address == write_address) & (internal_used == 0);
assign internal_full = (write_address == read_address) & (internal_used != 0);
//assign used = internal_used; // this signal reflects the number of words in the FIFO
//assign empty = internal_empty; // combinational so it'll glitch a little bit
assign full = internal_full; // dito
endmodule
| 6.804526 |
module altera_msgdma_prefetcher_interrupt (
input clk,
input reset,
input write_back_done,
input transfer_complete_irq_mask,
input [7:0] error_irq_mask,
input early_termination_irq_mask,
input [7:0] error,
input early_termination,
input clear_irq,
input global_interrupt_enable_mask,
output reg irq
);
wire set_irq;
always @(posedge clk or posedge reset) begin
if (reset) irq <= 0;
else begin
case ({
clear_irq, set_irq
})
2'b00: irq <= irq;
2'b01: irq <= 1'b1;
2'b10: irq <= 1'b0;
2'b11: irq <= 1'b1;
endcase
end
end
assign set_irq = (global_interrupt_enable_mask == 1) & (write_back_done == 1) & // transfer ended and interrupts are enabled
((transfer_complete_irq_mask == 1) | // transfer ended and the transfer complete IRQ is enabled
((error & error_irq_mask) != 0) | // transfer ended with an error and this IRQ is enabled
((early_termination & early_termination_irq_mask) == 1)); // transfer ended early due to early termination and this IRQ is enabled
endmodule
| 6.804526 |
module construct of the Avalon Streaming receive port for the
// chaining DMA application MSI signals.
//-----------------------------------------------------------------------------
// Copyright (c) 2009 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
module altpcierd_cdma_ast_msi (
input clk_in,
input rstn,
input app_msi_req,
output reg app_msi_ack,
input[2:0] app_msi_tc,
input[4:0] app_msi_num,
input stream_ready,
output reg [7:0] stream_data,
output reg stream_valid);
reg stream_ready_del;
reg app_msi_req_r;
wire [7:0] m_data;
assign m_data[7:5] = app_msi_tc[2:0];
assign m_data[4:0] = app_msi_num[4:0];
//------------------------------------------------------------
// Input register boundary
//------------------------------------------------------------
always @(negedge rstn or posedge clk_in) begin
if (rstn == 1'b0)
stream_ready_del <= 1'b0;
else
stream_ready_del <= stream_ready;
end
//------------------------------------------------------------
// Arbitration between master and target for transmission
//------------------------------------------------------------
// tx_state SM states
always @(negedge rstn or posedge clk_in) begin
if (rstn == 1'b0) begin
app_msi_ack <= 1'b0;
stream_valid <= 1'b0;
stream_data <= 8'h0;
app_msi_req_r <= 1'b0;
end
else begin
app_msi_ack <= stream_ready_del & app_msi_req;
stream_valid <= stream_ready_del & app_msi_req & ~app_msi_req_r;
stream_data <= m_data;
app_msi_req_r <= stream_ready_del ? app_msi_req : app_msi_req_r;
end
end
endmodule
| 6.967781 |
module altpcierd_cdma_ecrc_gen_calc #(
parameter AVALON_ST_128 = 0
) (
clk,
rstn,
crc_data,
crc_valid,
crc_empty,
crc_eop,
crc_sop,
ecrc,
crc_ack
);
input clk;
input rstn;
input [127:0] crc_data;
input crc_valid;
input [3:0] crc_empty;
input crc_eop;
input crc_sop;
output [31:0] ecrc;
input crc_ack;
wire [31:0] crc_int;
wire crc_valid_int;
wire open_empty;
wire open_full;
generate
begin
if (AVALON_ST_128 == 1) begin
altpcierd_tx_ecrc_128 tx_ecrc_128 (
.clk(clk),
.reset_n(rstn),
.data(crc_data),
.datavalid(crc_valid),
.empty(crc_empty),
.endofpacket(crc_eop),
.startofpacket(crc_sop),
.checksum(crc_int),
.crcvalid(crc_valid_int)
);
end
end
endgenerate
generate
begin
if (AVALON_ST_128 == 0) begin
altpcierd_tx_ecrc_64 tx_ecrc_64 (
.clk(clk),
.reset_n(rstn),
.data(crc_data[127:64]),
.datavalid(crc_valid),
.empty(crc_empty[2:0]),
.endofpacket(crc_eop),
.startofpacket(crc_sop),
.checksum(crc_int),
.crcvalid(crc_valid_int)
);
end
end
endgenerate
altpcierd_tx_ecrc_fifo tx_ecrc_fifo (
.aclr (~rstn),
.clock(clk),
.data (crc_int),
.rdreq(crc_ack),
.wrreq(crc_valid_int),
.empty(open_empty),
.full (open_full),
.q (ecrc)
);
endmodule
| 6.83792 |
module altpcierd_cdma_ecrc_gen_datapath (
clk,
rstn,
data_in,
data_valid,
rdreq,
data_out,
data_out_valid,
full
);
input clk;
input rstn;
input [135:0] data_in;
input data_valid;
input rdreq;
output [135:0] data_out;
output data_out_valid;
output full;
wire empty;
reg [6:0] ctl_shift_reg;
wire rdreq_int;
wire open_data_fifo_empty;
wire open_data_fifo_almost_full;
wire open_data_fifo_full;
wire open_ctl_fifo_full;
wire open_ctl_fifo_data;
wire data_bit;
assign data_bit = 1'b1;
// lookahead
altpcierd_tx_ecrc_data_fifo tx_ecrc_data_fifo (
.aclr (~rstn),
.clock (clk),
.data (data_in),
.rdreq (rdreq_int),
.wrreq (data_valid),
.almost_full(open_data_fifo_almost_full),
.empty (open_data_fifo_empty),
.full (open_data_fifo_full),
.q (data_out)
);
// push data_valid thru a shift register to
// wait a minimum time before allowing data fifo
// to be popped. when shifted data_valid is put
// into the control fifo, it is okay to pop data
// fifo whenever avalon ST is ready
always @(posedge clk or negedge rstn) begin
if (rstn == 1'b0) begin
ctl_shift_reg <= 7'h0;
end else begin
ctl_shift_reg <= {
data_valid, ctl_shift_reg[6:1]
}; // always shifting. no throttling because crc module is not throttled.
end
end
assign rdreq_int = (rdreq == 1'b1) & (empty == 1'b0);
assign data_out_valid = (rdreq == 1'b1) & (empty == 1'b0);
// this fifo only serves as an up/down counter for number of
// tx_data_fifo entries which have met the minimum
// required delay time before being popped
// lookahead
altpcierd_tx_ecrc_ctl_fifo tx_ecrc_ctl_fifo (
.aclr (~rstn),
.clock (clk),
.data (data_bit), // data does not matter
.rdreq (rdreq_int),
.wrreq (ctl_shift_reg[0]),
.almost_full(full),
.empty (empty),
.full (open_ctl_fifo_full),
.q (open_ctl_fifo_data)
);
endmodule
| 6.83792 |
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