code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Barrel16R (
input [15:0] data_i,
input [3:0] shift_i,
output reg [15:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i >> 1;
4'b0010: data_o = data_i >> 2;
4'b0011: data_o = data_i >> 3;
4'b0100: data_o = data_i >> 4;
4'b0101: data_o = data_i >> 5;
4'b0110: data_o = data_i >> 6;
4'b0111: data_o = data_i >> 7;
4'b1000: data_o = data_i >> 8;
4'b1001: data_o = data_i >> 9;
4'b1010: data_o = data_i >> 10;
4'b1011: data_o = data_i >> 11;
4'b1100: data_o = data_i >> 12;
4'b1101: data_o = data_i >> 13;
4'b1110: data_o = data_i >> 14;
default: data_o = data_i >> 15;
endcase
endmodule
| 7.464977 |
module Barrel32L (
input [31:0] data_i,
input [4:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
5'b00000: data_o = data_i;
5'b00001: data_o = data_i << 1;
5'b00010: data_o = data_i << 2;
5'b00011: data_o = data_i << 3;
5'b00100: data_o = data_i << 4;
5'b00101: data_o = data_i << 5;
5'b00110: data_o = data_i << 6;
5'b00111: data_o = data_i << 7;
5'b01000: data_o = data_i << 8;
5'b01001: data_o = data_i << 9;
5'b01010: data_o = data_i << 10;
5'b01011: data_o = data_i << 11;
5'b01100: data_o = data_i << 12;
5'b01101: data_o = data_i << 13;
5'b01110: data_o = data_i << 14;
5'b01111: data_o = data_i << 15;
default: data_o = data_i << 16;
endcase
endmodule
| 7.342303 |
module FAd (
a,
b,
c,
cy,
sm
);
input a, b, c;
output cy, sm;
wire x, y, z;
xor x1 (x, a, b);
xor x2 (sm, x, c);
and a1 (y, a, b);
and a2 (z, x, c);
or o1 (cy, y, z);
endmodule
| 7.593245 |
module ALM_fixed (
input clk,
input clear_async,
input clear_sync_0,
input clear_sync_1,
input clk_en_0,
input clk_en_1,
input DataA,
input DataB,
input DataC0,
input DataC1,
input DataD0,
input DataD1,
input DataE,
input DataF,
input carry_in,
output reg carry_out,
output reg out_0,
output reg out_1,
output reg out_2,
output reg out_3,
input config_clk,
input config_in,
input config_en,
output config_out
);
////////////////////////////
// parameters
////////////////////////////
parameter param_XOR6_en = 1'b0;
parameter param_MajAdd_en = 1'b0;
parameter param_fixed = 1'b1;
// registers
wire out_0_temp;
wire out_1_temp;
wire out_2_temp;
wire out_3_temp;
wire carry_out_temp;
reg DataA_reg;
reg DataB_reg;
reg DataC0_reg;
reg DataC1_reg;
reg DataD0_reg;
reg DataD1_reg;
reg DataE_reg;
reg DataF_reg;
reg carry_in_reg;
reg clear_sync_0_reg;
reg clear_sync_1_reg;
reg clk_en_0_reg;
reg clk_en_1_reg;
always @(posedge clk) begin
out_0 <= out_0_temp;
out_1 <= out_1_temp;
out_2 <= out_2_temp;
out_3 <= out_3_temp;
DataA_reg <= DataA;
DataB_reg <= DataB;
DataC0_reg <= DataC0;
DataC1_reg <= DataC1;
DataD0_reg <= DataD0;
DataD1_reg <= DataD1;
DataE_reg <= DataE;
DataF_reg <= DataF;
carry_in_reg <= carry_in;
carry_out <= carry_out_temp;
clear_sync_0_reg <= clear_sync_0;
clear_sync_1_reg <= clear_sync_1;
clk_en_0_reg <= clk_en_0;
clk_en_1_reg <= clk_en_1;
end
defparam ALM_inst.param_XOR6_en = param_XOR6_en;
defparam ALM_inst.param_MajAdd_en = param_MajAdd_en;
defparam ALM_inst.param_fixed = param_fixed;
ALM ALM_inst (
.clk(clk),
.clear_async(clear_async),
.clear_sync_0(clear_sync_0_reg),
.clear_sync_1(clear_sync_1_reg),
.clk_en_0(clk_en_0_reg),
.clk_en_1(clk_en_1_reg),
.DataA (DataA_reg),
.DataB (DataB_reg),
.DataC0(DataC0_reg),
.DataC1(DataC1_reg),
.DataD0(DataD0_reg),
.DataD1(DataD1_reg),
.DataE (DataE_reg),
.DataF (DataF_reg),
.carry_in (carry_in_reg),
.carry_out(carry_out_temp),
.out_0(out_0_temp),
.out_1(out_1_temp),
.out_2(out_2_temp),
.out_3(out_3_temp),
.config_clk(config_clk),
.config_in (config_in),
.config_en (config_en),
.config_out(config_out)
);
endmodule
| 7.892724 |
module is designed to model ALM and it's hyperflex registers. ALM model is just instanciated from ALM.v
// This file is prepared according to the "Intel® Stratix® 10 Logic Array Blocks and Adaptive Logic Modules User Guide", UG-S10-Lab-2018.09.21 and "Intel Stratix 10 GX/SX Device Overview"
module ALM_HF(
// control_signals = clear_sync_0,clk,clk_HF_Controls,clk_HF_Data,clk_en_0,clk_en_1,clear_sync_1,clear_async
input [7:0] control_signals,
// Data = {{DataF},{DataE},{DataD1},{DataD0},{DataC1},{DataC0},{DataB},{DataA}};
input [7:0] Data,
input carry_in,
output carry_out,
// out = {{out_3},{out_2},{out_1},{out_0}};
output [3:0] out,
input config_clk,
input config_in,
input config_en,
output config_out
);
// Parameters
parameter param_XOR6_en = 1'b0;
parameter param_MajAdd_en = 1'b0;
parameter param_fixed = 1'b0;
// Configuration bits
reg HF_unit_selector_Data;
reg HF_unit_selector_clear_sync_0;
reg HF_unit_selector_clear_sync_1;
reg HF_unit_selector_clk_en_0;
reg HF_unit_selector_clk_en_1;
// configuration wires
wire config_out_local;
// wires
wire [7:0] Data_local;
wire clear_sync_0_local;
wire clear_sync_1_local;
wire clk_en_0_local;
wire clk_en_1_local;
wire clk;
wire clk_HF_Data;
wire clk_HF_Controls;
wire clear_async;
wire clear_sync_0;
wire clear_sync_1;
wire clk_en_0;
wire clk_en_1;
// control_signals wirings, page 9 (LSB is on the right of the figure)
// control_signals = clear_sync_0,clk,clk_HF_Controls,clk_HF_Data,clk_en_0,clk_en_1,clear_sync_1,clear_async
assign clk = control_signals[6];
assign clk_HF_Data = control_signals[4];
assign clk_HF_Controls = control_signals[5];
assign clear_async = control_signals[0];
assign clear_sync_0 = control_signals[7];
assign clear_sync_1 = control_signals[1];
assign clk_en_0 = control_signals[3];
assign clk_en_1 = control_signals[2];
// HF on ALM inputs
defparam HF_unit_Data.size = 8;
HF_unit HF_unit_Data(
.clk(clk_HF_Data),
.in(Data),
.selector(HF_unit_selector_Data),
.out(Data_local)
);
// HF on Control signals
HF_unit HF_unit_clear_sync_0(
.clk(clk_HF_Controls),
.in(clear_sync_0),
.selector(HF_unit_selector_clear_sync_0),
.out(clear_sync_0_local)
);
HF_unit HF_unit_clear_sync_1(
.clk(clk_HF_Controls),
.in(clear_sync_1),
.selector(HF_unit_selector_clear_sync_1),
.out(clear_sync_1_local)
);
HF_unit HF_unit_clk_en_0(
.clk(clk_HF_Controls),
.in(clk_en_0),
.selector(HF_unit_selector_clk_en_0),
.out(clk_en_0_local)
);
HF_unit HF_unit_clk_en_1(
.clk(clk_HF_Controls),
.in(clk_en_1),
.selector(HF_unit_selector_clk_en_1),
.out(clk_en_1_local)
);
// ALM instanciation
defparam ALM_inst.param_XOR6_en = param_XOR6_en;
defparam ALM_inst.param_MajAdd_en = param_MajAdd_en;
defparam ALM_inst.param_fixed = param_fixed;
ALM ALM_inst(
.clk(clk),
.clear_async(clear_async),
.clear_sync_0(clear_sync_0_local),
.clear_sync_1(clear_sync_1_local),
.clk_en_0(clk_en_0_local),
.clk_en_1(clk_en_1_local),
.DataA(Data_local[0]),
.DataB(Data_local[1]),
.DataC0(Data_local[2]),
.DataC1(Data_local[3]),
.DataD0(Data_local[4]),
.DataD1(Data_local[5]),
.DataE(Data_local[6]),
.DataF(Data_local[7]),
.carry_in(carry_in),
.carry_out(carry_out),
.out_0(out[0]),
.out_1(out[1]),
.out_2(out[2]),
.out_3(out[3]),
.config_clk(config_clk),
.config_in(config_in),
.config_en(config_en),
.config_out(config_out_local)
);
always @(posedge config_clk)begin
if (config_en)begin
HF_unit_selector_Data <= config_out_local;
HF_unit_selector_clear_sync_0 <= HF_unit_selector_Data;
HF_unit_selector_clear_sync_1 <= HF_unit_selector_clear_sync_0;
HF_unit_selector_clk_en_0 <= HF_unit_selector_clear_sync_1;
HF_unit_selector_clk_en_1 <= HF_unit_selector_clk_en_0;
end
end
assign config_out = HF_unit_selector_clk_en_1;
endmodule
| 7.739429 |
module MISTRAL_ALUT3 (
input A,
B,
C,
output Q
);
parameter [7:0] LUT = 8'h00;
`ifdef cyclonev
specify
(A => Q) = 510;
(B => Q) = 400;
(C => Q) = 97;
endspecify
`endif
`ifdef cyclone10gx
specify
(A => Q) = 165;
(B => Q) = 162;
(C => Q) = 53;
endspecify
`endif
assign Q = LUT >> {C, B, A};
endmodule
| 6.533542 |
module ALM_SOA5 (
input [ 7:0] x,
input [ 7:0] y,
output [15:0] p
);
// Generate abs values
wire [7:0] x_abs;
wire [7:0] y_abs;
// Going for X_abs
assign x_abs = x ^ {8{x[7]}};
// Going for Y_abs
assign y_abs = y ^ {8{y[7]}};
// LOD x
wire [7:0] kx;
wire zero_x;
wire [2:0] code_x;
LOD8 LODx (
.data_i(x_abs),
.zero_o(zero_x),
.data_o(kx)
);
PriorityEncoder_8 PEx (
.data_i(kx),
.code_o(code_x)
);
// LOD y
wire [7:0] ky;
wire zero_y;
wire [2:0] code_y;
LOD8 LODy (
.data_i(y_abs),
.zero_o(zero_y),
.data_o(ky)
);
PriorityEncoder_8 PEy (
.data_i(ky),
.code_o(code_y)
);
wire [2:0] code_x_inv;
wire [2:0] barrel_x;
assign code_x_inv = ~code_x;
Barrel8L BShiftx (
.data_i (x_abs),
.shift_i(code_x_inv),
.data_o (barrel_x)
);
// Barell shift Y
wire [2:0] code_y_inv;
wire [2:0] barrel_y;
assign code_y_inv = ~code_y;
Barrel8L BShifty (
.data_i (y_abs),
.shift_i(code_y_inv),
.data_o (barrel_y)
);
// Addition of Op1 and Op2
wire [5:0] op1;
wire [5:0] op2;
wire [10:0] L;
wire c_in;
assign op1 = {1'b0, code_x, barrel_x[2:1]};
assign op2 = {1'b0, code_y, barrel_y[2:1]};
assign c_in = barrel_x[0] & barrel_y[0];
assign L[10:5] = op1 + op2 + c_in;
assign L[4:0] = {5{1'b1}};
// Anti logarithm
wire [15:0] tmp_out;
AntiLog anti_log (
.data_i(L),
.data_o(tmp_out)
);
// xor
wire prod_sign;
wire [15:0] tmp_sign;
assign prod_sign = x[7] ^ y[7];
assign tmp_sign = {16{prod_sign}} ^ tmp_out;
// is zero
wire not_zero;
assign not_zero = (~zero_x | x[15] | x[0]) & (~zero_y | y[15] | y[0]);
assign p = not_zero ? tmp_sign : 16'b0;
endmodule
| 6.87208 |
module LOD8 (
input [7:0] data_i,
output zero_o,
output [7:0] data_o
);
wire [7:0] z;
wire [1:0] zdet;
wire [1:0] select;
//*****************************************
// Zero detection logic:
//*****************************************
assign zdet[1] = |(data_i[7:4]);
assign zdet[0] = |(data_i[3:0]);
assign zero_o = ~(zdet[1] | zdet[0]);
//*****************************************
// LODs:
//*****************************************
LOD4 lod2_1 (
.data_i(data_i[7:4]),
.data_o(z[7:4])
);
LOD4 lod2_0 (
.data_i(data_i[3:0]),
.data_o(z[3:0])
);
//*****************************************
// Select signals
//*****************************************
LOD2 Middle (
.data_i(zdet),
.data_o(select)
);
//*****************************************
// Multiplexers :
//*****************************************
wire [7:0] tmp_out;
Muxes2in1Array4 Inst_MUX214_1 (
.data_i (z[7:4]),
.select_i(select[1]),
.data_o (tmp_out[7:4])
);
Muxes2in1Array4 Inst_MUX214_0 (
.data_i (z[3:0]),
.select_i(select[0]),
.data_o (tmp_out[3:0])
);
// One hot
assign data_o = tmp_out;
endmodule
| 6.992495 |
module LOD2 (
input [1:0] data_i,
output [1:0] data_o
);
assign data_o[1] = data_i[1];
assign data_o[0] = ~data_i[1] & data_i[0];
endmodule
| 7.907297 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module PriorityEncoder_8 (
input [7:0] data_i,
output [2:0] code_o
);
wire [3:0] tmp0;
assign tmp0 = {data_i[7], data_i[5], data_i[3], data_i[1]};
OR_tree code0 (
tmp0,
code_o[0]
);
wire [3:0] tmp1;
assign tmp1 = {data_i[7], data_i[6], data_i[3], data_i[2]};
OR_tree code1 (
tmp1,
code_o[1]
);
wire [3:0] tmp2;
assign tmp2 = {data_i[7], data_i[6], data_i[5], data_i[4]};
OR_tree code2 (
tmp2,
code_o[2]
);
endmodule
| 6.599169 |
module OR_tree (
input [3:0] data_i,
output data_o
);
wire [1:0] tmp1;
assign tmp1 = data_i[1:0] | data_i[3:2];
assign data_o = tmp1[0] | tmp1[1];
endmodule
| 7.726839 |
module Barrel8L (
input [7:0] data_i,
input [2:0] shift_i,
output [2:0] data_o
);
reg [15:0] tmp;
always @*
case (shift_i)
3'b000: tmp = data_i;
3'b001: tmp = data_i << 1;
3'b010: tmp = data_i << 2;
3'b011: tmp = data_i << 3;
3'b100: tmp = data_i << 4;
3'b101: tmp = data_i << 5;
3'b110: tmp = data_i << 6;
default: tmp = data_i << 7;
endcase
assign data_o = tmp[7:5];
endmodule
| 7.145832 |
module Barrel8R (
input [7:0] data_i,
input [2:0] shift_i,
output reg [7:0] data_o
);
always @*
case (shift_i)
3'b000: data_o = data_i;
3'b001: data_o = data_i << 1;
3'b010: data_o = data_i << 2;
3'b011: data_o = data_i << 3;
3'b100: data_o = data_i << 4;
3'b101: data_o = data_i << 5;
3'b110: data_o = data_i << 6;
default: data_o = data_i << 7;
endcase
endmodule
| 7.052818 |
module Barrel16L (
input [15:0] data_i,
input [3:0] shift_i,
output reg [15:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i << 1;
4'b0010: data_o = data_i << 2;
4'b0011: data_o = data_i << 3;
4'b0100: data_o = data_i << 4;
4'b0101: data_o = data_i << 5;
4'b0110: data_o = data_i << 6;
4'b0111: data_o = data_i << 7;
default: data_o = data_i << 8;
endcase
endmodule
| 7.500498 |
module PriorityEncoder_16_old (
input [15:0] data_i,
output reg [3:0] code_o
);
always @*
case (data_i)
16'b0000000000000001: code_o = 4'b0000;
16'b0000000000000010: code_o = 4'b0001;
16'b0000000000000100: code_o = 4'b0010;
16'b0000000000001000: code_o = 4'b0011;
16'b0000000000010000: code_o = 4'b0100;
16'b0000000000100000: code_o = 4'b0101;
16'b0000000001000000: code_o = 4'b0110;
16'b0000000010000000: code_o = 4'b0111;
16'b0000000100000000: code_o = 4'b1000;
16'b0000001000000000: code_o = 4'b1001;
16'b0000010000000000: code_o = 4'b1010;
16'b0000100000000000: code_o = 4'b1011;
16'b0001000000000000: code_o = 4'b1100;
16'b0010000000000000: code_o = 4'b1101;
16'b0100000000000000: code_o = 4'b1110;
16'b1000000000000000: code_o = 4'b1111;
default: code_o = 4'b0000;
endcase
endmodule
| 6.599169 |
module PriorityEncoder_16 (
input [15:0] data_i,
output [ 3:0] code_o
);
wire [7:0] tmp0;
assign tmp0 = {
data_i[15], data_i[13], data_i[11], data_i[9], data_i[7], data_i[5], data_i[3], data_i[1]
};
OR_tree code0 (
tmp0,
code_o[0]
);
wire [7:0] tmp1;
assign tmp1 = {
data_i[15], data_i[14], data_i[11], data_i[10], data_i[7], data_i[6], data_i[3], data_i[2]
};
OR_tree code1 (
tmp1,
code_o[1]
);
wire [7:0] tmp2;
assign tmp2 = {
data_i[15], data_i[14], data_i[13], data_i[12], data_i[7], data_i[6], data_i[5], data_i[4]
};
OR_tree code2 (
tmp2,
code_o[2]
);
wire [7:0] tmp3;
assign tmp3 = {
data_i[15], data_i[14], data_i[13], data_i[12], data_i[11], data_i[10], data_i[9], data_i[8]
};
OR_tree code3 (
tmp3,
code_o[3]
);
endmodule
| 6.599169 |
module OR_tree (
input [7:0] data_i,
output data_o
);
wire [3:0] tmp1;
wire [1:0] tmp2;
assign tmp1 = data_i[3:0] | data_i[7:4];
assign tmp2 = tmp1[1:0] | tmp1[3:2];
assign data_o = tmp2[0] | tmp2[1];
endmodule
| 7.726839 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module LOD16 (
input [15:0] data_i,
output zero_o,
output [15:0] data_o
);
wire [15:0] z;
wire [ 3:0] select;
wire [ 3:0] zdet;
//*****************************************
// Zero detection logic:
//*****************************************
assign zdet[3] = data_i[15] | data_i[14] | data_i[13] | data_i[12];
assign zdet[2] = data_i[11] | data_i[10] | data_i[9] | data_i[8];
assign zdet[1] = data_i[7] | data_i[6] | data_i[5] | data_i[4];
assign zdet[0] = data_i[3] | data_i[2] | data_i[1] | data_i[0];
assign zero_o = ~(zdet[3] | zdet[2] | zdet[1] | zdet[0]);
//*****************************************
// LODs:
//*****************************************
LOD4 lod4_3 (
.data_i(data_i[15:12]),
.data_o(z[15:12])
);
LOD4 lod4_2 (
.data_i(data_i[11:8]),
.data_o(z[11:8])
);
LOD4 lod4_1 (
.data_i(data_i[7:4]),
.data_o(z[7:4])
);
LOD4 lod4_0 (
.data_i(data_i[3:0]),
.data_o(z[3:0])
);
LOD4 lod4_middle (
.data_i(zdet),
.data_o(select)
);
//*****************************************
// Multiplexers :
//*****************************************
Muxes2in1Array4 Inst_MUX214_3 (
.data_i (z[15:12]),
.select_i(select[3]),
.data_o (data_o[15:12])
);
Muxes2in1Array4 Inst_MUX214_2 (
.data_i (z[11:8]),
.select_i(select[2]),
.data_o (data_o[11:8])
);
Muxes2in1Array4 Inst_MUX214_1 (
.data_i (z[7:4]),
.select_i(select[1]),
.data_o (data_o[7:4])
);
Muxes2in1Array4 Inst_MUX214_0 (
.data_i (z[3:0]),
.select_i(select[0]),
.data_o (data_o[3:0])
);
endmodule
| 7.892753 |
module Barrel16L (
input [15:0] data_i,
input [ 3:0] shift_i,
output [ 6:0] data_o
);
reg [15:0] tmp;
always @*
case (shift_i)
4'b0000: tmp = data_i;
4'b0001: tmp = data_i << 1;
4'b0010: tmp = data_i << 2;
4'b0011: tmp = data_i << 3;
4'b0100: tmp = data_i << 4;
4'b0101: tmp = data_i << 5;
4'b0110: tmp = data_i << 6;
4'b0111: tmp = data_i << 7;
4'b1000: tmp = data_i << 8;
4'b1001: tmp = data_i << 9;
4'b1010: tmp = data_i << 10;
4'b1011: tmp = data_i << 11;
4'b1100: tmp = data_i << 12;
4'b1101: tmp = data_i << 13;
4'b1110: tmp = data_i << 14;
default: tmp = data_i << 15;
endcase
assign data_o = tmp[15:9];
endmodule
| 7.500498 |
module Barrel16R (
input [15:0] data_i,
input [3:0] shift_i,
output reg [15:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i >> 1;
4'b0010: data_o = data_i >> 2;
4'b0011: data_o = data_i >> 3;
4'b0100: data_o = data_i >> 4;
4'b0101: data_o = data_i >> 5;
4'b0110: data_o = data_i >> 6;
4'b0111: data_o = data_i >> 7;
4'b1000: data_o = data_i >> 8;
4'b1001: data_o = data_i >> 9;
4'b1010: data_o = data_i >> 10;
4'b1011: data_o = data_i >> 11;
4'b1100: data_o = data_i >> 12;
4'b1101: data_o = data_i >> 13;
4'b1110: data_o = data_i >> 14;
default: data_o = data_i >> 15;
endcase
endmodule
| 7.464977 |
module Barrel32L (
input [31:0] data_i,
input [4:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
5'b00000: data_o = data_i;
5'b00001: data_o = data_i << 1;
5'b00010: data_o = data_i << 2;
5'b00011: data_o = data_i << 3;
5'b00100: data_o = data_i << 4;
5'b00101: data_o = data_i << 5;
5'b00110: data_o = data_i << 6;
5'b00111: data_o = data_i << 7;
5'b01000: data_o = data_i << 8;
5'b01001: data_o = data_i << 9;
5'b01010: data_o = data_i << 10;
5'b01011: data_o = data_i << 11;
5'b01100: data_o = data_i << 12;
5'b01101: data_o = data_i << 13;
5'b01110: data_o = data_i << 14;
5'b01111: data_o = data_i << 15;
default: data_o = data_i << 16;
endcase
endmodule
| 7.342303 |
module FAd (
a,
b,
c,
cy,
sm
);
input a, b, c;
output cy, sm;
wire x, y, z;
xor x1 (x, a, b);
xor x2 (sm, x, c);
and a1 (y, a, b);
and a2 (z, x, c);
or o1 (cy, y, z);
endmodule
| 7.593245 |
module ALM_SOA_W11 (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
// Generate abs values
wire [15:0] x_abs;
wire [15:0] y_abs;
// Going for X_abs
assign x_abs = x ^ {16{x[15]}};
// Going for Y_abs
assign y_abs = y ^ {16{y[15]}};
// LOD x
wire [15:0] kx;
wire zero_x;
wire [3:0] code_x;
LOD16 LODx (
.data_i(x_abs),
.zero_o(zero_x),
.data_o(kx)
);
PriorityEncoder_16 PEx (
.data_i(kx),
.code_o(code_x)
);
// LOD y
wire [15:0] ky;
wire zero_y;
wire [3:0] code_y;
LOD16 LODy (
.data_i(y_abs),
.zero_o(zero_y),
.data_o(ky)
);
PriorityEncoder_16 PEy (
.data_i(ky),
.code_o(code_y)
);
// Barell shift X
wire [3:0] code_x_inv;
wire [5:0] barrel_x;
assign code_x_inv = ~code_x;
Barrel16L BShiftx (
.data_i (x_abs),
.shift_i(code_x_inv),
.data_o (barrel_x)
);
// Barell shift Y
wire [3:0] code_y_inv;
wire [5:0] barrel_y;
assign code_y_inv = ~code_y;
Barrel16L BShifty (
.data_i (y_abs),
.shift_i(code_y_inv),
.data_o (barrel_y)
);
// Addition of Op1 and Op2
wire [8:0] op1;
wire [8:0] op2;
wire [19:0] L;
wire c_in;
assign op1 = {1'b0, code_x, barrel_x[4:1]};
assign op2 = {1'b0, code_y, barrel_y[4:1]};
assign c_in = barrel_x[0] & barrel_y[0];
assign L[19:11] = c_in + op1 + op2;
assign L[10:0] = {11{1'b1}};
// Anti logarithm
wire [31:0] tmp_out;
AntiLog anti_log (
.data_i(L),
.data_o(tmp_out)
);
// xor
wire prod_sign;
wire [31:0] tmp_sign;
assign prod_sign = x[15] ^ y[15];
assign tmp_sign = {32{prod_sign}} ^ tmp_out;
// is zero
wire not_zero;
assign not_zero = (~zero_x | x[15] | x[0]) & (~zero_y | y[15] | y[0]);
assign p = not_zero ? tmp_sign : 32'b0;
endmodule
| 6.861534 |
module PriorityEncoder_16_old (
input [15:0] data_i,
output reg [3:0] code_o
);
always @*
case (data_i)
16'b0000000000000001: code_o = 4'b0000;
16'b0000000000000010: code_o = 4'b0001;
16'b0000000000000100: code_o = 4'b0010;
16'b0000000000001000: code_o = 4'b0011;
16'b0000000000010000: code_o = 4'b0100;
16'b0000000000100000: code_o = 4'b0101;
16'b0000000001000000: code_o = 4'b0110;
16'b0000000010000000: code_o = 4'b0111;
16'b0000000100000000: code_o = 4'b1000;
16'b0000001000000000: code_o = 4'b1001;
16'b0000010000000000: code_o = 4'b1010;
16'b0000100000000000: code_o = 4'b1011;
16'b0001000000000000: code_o = 4'b1100;
16'b0010000000000000: code_o = 4'b1101;
16'b0100000000000000: code_o = 4'b1110;
16'b1000000000000000: code_o = 4'b1111;
default: code_o = 4'b0000;
endcase
endmodule
| 6.599169 |
module PriorityEncoder_16 (
input [15:0] data_i,
output [ 3:0] code_o
);
wire [7:0] tmp0;
assign tmp0 = {
data_i[15], data_i[13], data_i[11], data_i[9], data_i[7], data_i[5], data_i[3], data_i[1]
};
OR_tree code0 (
tmp0,
code_o[0]
);
wire [7:0] tmp1;
assign tmp1 = {
data_i[15], data_i[14], data_i[11], data_i[10], data_i[7], data_i[6], data_i[3], data_i[2]
};
OR_tree code1 (
tmp1,
code_o[1]
);
wire [7:0] tmp2;
assign tmp2 = {
data_i[15], data_i[14], data_i[13], data_i[12], data_i[7], data_i[6], data_i[5], data_i[4]
};
OR_tree code2 (
tmp2,
code_o[2]
);
wire [7:0] tmp3;
assign tmp3 = {
data_i[15], data_i[14], data_i[13], data_i[12], data_i[11], data_i[10], data_i[9], data_i[8]
};
OR_tree code3 (
tmp3,
code_o[3]
);
endmodule
| 6.599169 |
module OR_tree (
input [7:0] data_i,
output data_o
);
wire [3:0] tmp1;
wire [1:0] tmp2;
assign tmp1 = data_i[3:0] | data_i[7:4];
assign tmp2 = tmp1[1:0] | tmp1[3:2];
assign data_o = tmp2[0] | tmp2[1];
endmodule
| 7.726839 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module LOD16 (
input [15:0] data_i,
output zero_o,
output [15:0] data_o
);
wire [15:0] z;
wire [ 3:0] select;
wire [ 3:0] zdet;
//*****************************************
// Zero detection logic:
//*****************************************
assign zdet[3] = data_i[15] | data_i[14] | data_i[13] | data_i[12];
assign zdet[2] = data_i[11] | data_i[10] | data_i[9] | data_i[8];
assign zdet[1] = data_i[7] | data_i[6] | data_i[5] | data_i[4];
assign zdet[0] = data_i[3] | data_i[2] | data_i[1] | data_i[0];
assign zero_o = ~(zdet[3] | zdet[2] | zdet[1] | zdet[0]);
//*****************************************
// LODs:
//*****************************************
LOD4 lod4_3 (
.data_i(data_i[15:12]),
.data_o(z[15:12])
);
LOD4 lod4_2 (
.data_i(data_i[11:8]),
.data_o(z[11:8])
);
LOD4 lod4_1 (
.data_i(data_i[7:4]),
.data_o(z[7:4])
);
LOD4 lod4_0 (
.data_i(data_i[3:0]),
.data_o(z[3:0])
);
LOD4 lod4_middle (
.data_i(zdet),
.data_o(select)
);
//*****************************************
// Multiplexers :
//*****************************************
Muxes2in1Array4 Inst_MUX214_3 (
.data_i (z[15:12]),
.select_i(select[3]),
.data_o (data_o[15:12])
);
Muxes2in1Array4 Inst_MUX214_2 (
.data_i (z[11:8]),
.select_i(select[2]),
.data_o (data_o[11:8])
);
Muxes2in1Array4 Inst_MUX214_1 (
.data_i (z[7:4]),
.select_i(select[1]),
.data_o (data_o[7:4])
);
Muxes2in1Array4 Inst_MUX214_0 (
.data_i (z[3:0]),
.select_i(select[0]),
.data_o (data_o[3:0])
);
endmodule
| 7.892753 |
module Barrel16L (
input [15:0] data_i,
input [ 3:0] shift_i,
output [ 5:0] data_o
);
reg [15:0] tmp;
always @*
case (shift_i)
4'b0000: tmp = data_i;
4'b0001: tmp = data_i << 1;
4'b0010: tmp = data_i << 2;
4'b0011: tmp = data_i << 3;
4'b0100: tmp = data_i << 4;
4'b0101: tmp = data_i << 5;
4'b0110: tmp = data_i << 6;
4'b0111: tmp = data_i << 7;
4'b1000: tmp = data_i << 8;
4'b1001: tmp = data_i << 9;
4'b1010: tmp = data_i << 10;
4'b1011: tmp = data_i << 11;
4'b1100: tmp = data_i << 12;
4'b1101: tmp = data_i << 13;
4'b1110: tmp = data_i << 14;
default: tmp = data_i << 15;
endcase
assign data_o = tmp[15:10];
endmodule
| 7.500498 |
module Barrel16R (
input [15:0] data_i,
input [3:0] shift_i,
output reg [15:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i >> 1;
4'b0010: data_o = data_i >> 2;
4'b0011: data_o = data_i >> 3;
4'b0100: data_o = data_i >> 4;
4'b0101: data_o = data_i >> 5;
4'b0110: data_o = data_i >> 6;
4'b0111: data_o = data_i >> 7;
4'b1000: data_o = data_i >> 8;
4'b1001: data_o = data_i >> 9;
4'b1010: data_o = data_i >> 10;
4'b1011: data_o = data_i >> 11;
4'b1100: data_o = data_i >> 12;
4'b1101: data_o = data_i >> 13;
4'b1110: data_o = data_i >> 14;
default: data_o = data_i >> 15;
endcase
endmodule
| 7.464977 |
module Barrel32L (
input [31:0] data_i,
input [4:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
5'b00000: data_o = data_i;
5'b00001: data_o = data_i << 1;
5'b00010: data_o = data_i << 2;
5'b00011: data_o = data_i << 3;
5'b00100: data_o = data_i << 4;
5'b00101: data_o = data_i << 5;
5'b00110: data_o = data_i << 6;
5'b00111: data_o = data_i << 7;
5'b01000: data_o = data_i << 8;
5'b01001: data_o = data_i << 9;
5'b01010: data_o = data_i << 10;
5'b01011: data_o = data_i << 11;
5'b01100: data_o = data_i << 12;
5'b01101: data_o = data_i << 13;
5'b01110: data_o = data_i << 14;
5'b01111: data_o = data_i << 15;
default: data_o = data_i << 16;
endcase
endmodule
| 7.342303 |
module FAd (
a,
b,
c,
cy,
sm
);
input a, b, c;
output cy, sm;
wire x, y, z;
xor x1 (x, a, b);
xor x2 (sm, x, c);
and a1 (y, a, b);
and a2 (z, x, c);
or o1 (cy, y, z);
endmodule
| 7.593245 |
module ALM_SOA_W12 (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
// Generate abs values
wire [15:0] x_abs;
wire [15:0] y_abs;
// Going for X_abs
assign x_abs = x ^ {16{x[15]}};
// Going for Y_abs
assign y_abs = y ^ {16{y[15]}};
// LOD x
wire [15:0] kx;
wire zero_x;
wire [3:0] code_x;
LOD16 LODx (
.data_i(x_abs),
.zero_o(zero_x),
.data_o(kx)
);
PriorityEncoder_16 PEx (
.data_i(kx),
.code_o(code_x)
);
// LOD y
wire [15:0] ky;
wire zero_y;
wire [3:0] code_y;
LOD16 LODy (
.data_i(y_abs),
.zero_o(zero_y),
.data_o(ky)
);
PriorityEncoder_16 PEy (
.data_i(ky),
.code_o(code_y)
);
// Barell shift X
wire [3:0] code_x_inv;
wire [5:0] barrel_x;
assign code_x_inv = ~code_x;
Barrel16L BShiftx (
.data_i (x_abs),
.shift_i(code_x_inv),
.data_o (barrel_x)
);
// Barell shift Y
wire [3:0] code_y_inv;
wire [5:0] barrel_y;
assign code_y_inv = ~code_y;
Barrel16L BShifty (
.data_i (y_abs),
.shift_i(code_y_inv),
.data_o (barrel_y)
);
// Addition of Op1 and Op2
wire [7:0] op1;
wire [7:0] op2;
wire [19:0] L;
wire c_in;
assign op1 = {1'b0, code_x, barrel_x[4:2]};
assign op2 = {1'b0, code_y, barrel_y[4:2]};
assign c_in = barrel_x[1] & barrel_y[1];
assign L[19:12] = c_in + op1 + op2;
assign L[11:0] = {12{1'b1}};
// Anti logarithm
wire [31:0] tmp_out;
AntiLog anti_log (
.data_i(L),
.data_o(tmp_out)
);
// xor
wire prod_sign;
wire [31:0] tmp_sign;
assign prod_sign = x[15] ^ y[15];
assign tmp_sign = {32{prod_sign}} ^ tmp_out;
// is zero
wire not_zero;
assign not_zero = (~zero_x | x[15] | x[0]) & (~zero_y | y[15] | y[0]);
assign p = not_zero ? tmp_sign : 32'b0;
endmodule
| 7.215881 |
module PriorityEncoder_16_old (
input [15:0] data_i,
output reg [3:0] code_o
);
always @*
case (data_i)
16'b0000000000000001: code_o = 4'b0000;
16'b0000000000000010: code_o = 4'b0001;
16'b0000000000000100: code_o = 4'b0010;
16'b0000000000001000: code_o = 4'b0011;
16'b0000000000010000: code_o = 4'b0100;
16'b0000000000100000: code_o = 4'b0101;
16'b0000000001000000: code_o = 4'b0110;
16'b0000000010000000: code_o = 4'b0111;
16'b0000000100000000: code_o = 4'b1000;
16'b0000001000000000: code_o = 4'b1001;
16'b0000010000000000: code_o = 4'b1010;
16'b0000100000000000: code_o = 4'b1011;
16'b0001000000000000: code_o = 4'b1100;
16'b0010000000000000: code_o = 4'b1101;
16'b0100000000000000: code_o = 4'b1110;
16'b1000000000000000: code_o = 4'b1111;
default: code_o = 4'b0000;
endcase
endmodule
| 6.599169 |
module PriorityEncoder_16 (
input [15:0] data_i,
output [ 3:0] code_o
);
wire [7:0] tmp0;
assign tmp0 = {
data_i[15], data_i[13], data_i[11], data_i[9], data_i[7], data_i[5], data_i[3], data_i[1]
};
OR_tree code0 (
tmp0,
code_o[0]
);
wire [7:0] tmp1;
assign tmp1 = {
data_i[15], data_i[14], data_i[11], data_i[10], data_i[7], data_i[6], data_i[3], data_i[2]
};
OR_tree code1 (
tmp1,
code_o[1]
);
wire [7:0] tmp2;
assign tmp2 = {
data_i[15], data_i[14], data_i[13], data_i[12], data_i[7], data_i[6], data_i[5], data_i[4]
};
OR_tree code2 (
tmp2,
code_o[2]
);
wire [7:0] tmp3;
assign tmp3 = {
data_i[15], data_i[14], data_i[13], data_i[12], data_i[11], data_i[10], data_i[9], data_i[8]
};
OR_tree code3 (
tmp3,
code_o[3]
);
endmodule
| 6.599169 |
module OR_tree (
input [7:0] data_i,
output data_o
);
wire [3:0] tmp1;
wire [1:0] tmp2;
assign tmp1 = data_i[3:0] | data_i[7:4];
assign tmp2 = tmp1[1:0] | tmp1[3:2];
assign data_o = tmp2[0] | tmp2[1];
endmodule
| 7.726839 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module LOD16 (
input [15:0] data_i,
output zero_o,
output [15:0] data_o
);
wire [15:0] z;
wire [ 3:0] select;
wire [ 3:0] zdet;
//*****************************************
// Zero detection logic:
//*****************************************
assign zdet[3] = data_i[15] | data_i[14] | data_i[13] | data_i[12];
assign zdet[2] = data_i[11] | data_i[10] | data_i[9] | data_i[8];
assign zdet[1] = data_i[7] | data_i[6] | data_i[5] | data_i[4];
assign zdet[0] = data_i[3] | data_i[2] | data_i[1] | data_i[0];
assign zero_o = ~(zdet[3] | zdet[2] | zdet[1] | zdet[0]);
//*****************************************
// LODs:
//*****************************************
LOD4 lod4_3 (
.data_i(data_i[15:12]),
.data_o(z[15:12])
);
LOD4 lod4_2 (
.data_i(data_i[11:8]),
.data_o(z[11:8])
);
LOD4 lod4_1 (
.data_i(data_i[7:4]),
.data_o(z[7:4])
);
LOD4 lod4_0 (
.data_i(data_i[3:0]),
.data_o(z[3:0])
);
LOD4 lod4_middle (
.data_i(zdet),
.data_o(select)
);
//*****************************************
// Multiplexers :
//*****************************************
Muxes2in1Array4 Inst_MUX214_3 (
.data_i (z[15:12]),
.select_i(select[3]),
.data_o (data_o[15:12])
);
Muxes2in1Array4 Inst_MUX214_2 (
.data_i (z[11:8]),
.select_i(select[2]),
.data_o (data_o[11:8])
);
Muxes2in1Array4 Inst_MUX214_1 (
.data_i (z[7:4]),
.select_i(select[1]),
.data_o (data_o[7:4])
);
Muxes2in1Array4 Inst_MUX214_0 (
.data_i (z[3:0]),
.select_i(select[0]),
.data_o (data_o[3:0])
);
endmodule
| 7.892753 |
module Barrel16L (
input [15:0] data_i,
input [ 3:0] shift_i,
output [ 5:0] data_o
);
reg [15:0] tmp;
always @*
case (shift_i)
4'b0000: tmp = data_i;
4'b0001: tmp = data_i << 1;
4'b0010: tmp = data_i << 2;
4'b0011: tmp = data_i << 3;
4'b0100: tmp = data_i << 4;
4'b0101: tmp = data_i << 5;
4'b0110: tmp = data_i << 6;
4'b0111: tmp = data_i << 7;
4'b1000: tmp = data_i << 8;
4'b1001: tmp = data_i << 9;
4'b1010: tmp = data_i << 10;
4'b1011: tmp = data_i << 11;
4'b1100: tmp = data_i << 12;
4'b1101: tmp = data_i << 13;
4'b1110: tmp = data_i << 14;
default: tmp = data_i << 15;
endcase
assign data_o = tmp[15:10];
endmodule
| 7.500498 |
module Barrel16R (
input [15:0] data_i,
input [3:0] shift_i,
output reg [15:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i >> 1;
4'b0010: data_o = data_i >> 2;
4'b0011: data_o = data_i >> 3;
4'b0100: data_o = data_i >> 4;
4'b0101: data_o = data_i >> 5;
4'b0110: data_o = data_i >> 6;
4'b0111: data_o = data_i >> 7;
4'b1000: data_o = data_i >> 8;
4'b1001: data_o = data_i >> 9;
4'b1010: data_o = data_i >> 10;
4'b1011: data_o = data_i >> 11;
4'b1100: data_o = data_i >> 12;
4'b1101: data_o = data_i >> 13;
4'b1110: data_o = data_i >> 14;
default: data_o = data_i >> 15;
endcase
endmodule
| 7.464977 |
module Barrel32L (
input [31:0] data_i,
input [4:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
5'b00000: data_o = data_i;
5'b00001: data_o = data_i << 1;
5'b00010: data_o = data_i << 2;
5'b00011: data_o = data_i << 3;
5'b00100: data_o = data_i << 4;
5'b00101: data_o = data_i << 5;
5'b00110: data_o = data_i << 6;
5'b00111: data_o = data_i << 7;
5'b01000: data_o = data_i << 8;
5'b01001: data_o = data_i << 9;
5'b01010: data_o = data_i << 10;
5'b01011: data_o = data_i << 11;
5'b01100: data_o = data_i << 12;
5'b01101: data_o = data_i << 13;
5'b01110: data_o = data_i << 14;
5'b01111: data_o = data_i << 15;
default: data_o = data_i << 16;
endcase
endmodule
| 7.342303 |
module FAd (
a,
b,
c,
cy,
sm
);
input a, b, c;
output cy, sm;
wire x, y, z;
xor x1 (x, a, b);
xor x2 (sm, x, c);
and a1 (y, a, b);
and a2 (z, x, c);
or o1 (cy, y, z);
endmodule
| 7.593245 |
module ALM_SOA_W13 (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
// Generate abs values
wire [15:0] x_abs;
wire [15:0] y_abs;
// Going for X_abs
assign x_abs = x ^ {16{x[15]}};
// Going for Y_abs
assign y_abs = y ^ {16{y[15]}};
// LOD x
wire [15:0] kx;
wire zero_x;
wire [3:0] code_x;
LOD16 LODx (
.data_i(x_abs),
.zero_o(zero_x),
.data_o(kx)
);
PriorityEncoder_16 PEx (
.data_i(kx),
.code_o(code_x)
);
// LOD y
wire [15:0] ky;
wire zero_y;
wire [3:0] code_y;
LOD16 LODy (
.data_i(y_abs),
.zero_o(zero_y),
.data_o(ky)
);
PriorityEncoder_16 PEy (
.data_i(ky),
.code_o(code_y)
);
// Barell shift X
wire [3:0] code_x_inv;
wire [5:0] barrel_x;
assign code_x_inv = ~code_x;
Barrel16L BShiftx (
.data_i (x_abs),
.shift_i(code_x_inv),
.data_o (barrel_x)
);
// Barell shift Y
wire [3:0] code_y_inv;
wire [5:0] barrel_y;
assign code_y_inv = ~code_y;
Barrel16L BShifty (
.data_i (y_abs),
.shift_i(code_y_inv),
.data_o (barrel_y)
);
// Addition of Op1 and Op2
wire [6:0] op1;
wire [6:0] op2;
wire [19:0] L;
wire c_in;
assign op1 = {1'b0, code_x, barrel_x[4:3]};
assign op2 = {1'b0, code_y, barrel_y[4:3]};
assign c_in = barrel_x[2] & barrel_y[2];
assign L[19:13] = c_in + op1 + op2;
assign L[12:0] = {13{1'b1}};
// Anti logarithm
wire [31:0] tmp_out;
AntiLog anti_log (
.data_i(L),
.data_o(tmp_out)
);
// xor
wire prod_sign;
wire [31:0] tmp_sign;
assign prod_sign = x[15] ^ y[15];
assign tmp_sign = {32{prod_sign}} ^ tmp_out;
// is zero
wire not_zero;
assign not_zero = (~zero_x | x[15] | x[0]) & (~zero_y | y[15] | y[0]);
assign p = not_zero ? tmp_sign : 32'b0;
endmodule
| 6.695534 |
module PriorityEncoder_16_old (
input [15:0] data_i,
output reg [3:0] code_o
);
always @*
case (data_i)
16'b0000000000000001: code_o = 4'b0000;
16'b0000000000000010: code_o = 4'b0001;
16'b0000000000000100: code_o = 4'b0010;
16'b0000000000001000: code_o = 4'b0011;
16'b0000000000010000: code_o = 4'b0100;
16'b0000000000100000: code_o = 4'b0101;
16'b0000000001000000: code_o = 4'b0110;
16'b0000000010000000: code_o = 4'b0111;
16'b0000000100000000: code_o = 4'b1000;
16'b0000001000000000: code_o = 4'b1001;
16'b0000010000000000: code_o = 4'b1010;
16'b0000100000000000: code_o = 4'b1011;
16'b0001000000000000: code_o = 4'b1100;
16'b0010000000000000: code_o = 4'b1101;
16'b0100000000000000: code_o = 4'b1110;
16'b1000000000000000: code_o = 4'b1111;
default: code_o = 4'b0000;
endcase
endmodule
| 6.599169 |
module PriorityEncoder_16 (
input [15:0] data_i,
output [ 3:0] code_o
);
wire [7:0] tmp0;
assign tmp0 = {
data_i[15], data_i[13], data_i[11], data_i[9], data_i[7], data_i[5], data_i[3], data_i[1]
};
OR_tree code0 (
tmp0,
code_o[0]
);
wire [7:0] tmp1;
assign tmp1 = {
data_i[15], data_i[14], data_i[11], data_i[10], data_i[7], data_i[6], data_i[3], data_i[2]
};
OR_tree code1 (
tmp1,
code_o[1]
);
wire [7:0] tmp2;
assign tmp2 = {
data_i[15], data_i[14], data_i[13], data_i[12], data_i[7], data_i[6], data_i[5], data_i[4]
};
OR_tree code2 (
tmp2,
code_o[2]
);
wire [7:0] tmp3;
assign tmp3 = {
data_i[15], data_i[14], data_i[13], data_i[12], data_i[11], data_i[10], data_i[9], data_i[8]
};
OR_tree code3 (
tmp3,
code_o[3]
);
endmodule
| 6.599169 |
module OR_tree (
input [7:0] data_i,
output data_o
);
wire [3:0] tmp1;
wire [1:0] tmp2;
assign tmp1 = data_i[3:0] | data_i[7:4];
assign tmp2 = tmp1[1:0] | tmp1[3:2];
assign data_o = tmp2[0] | tmp2[1];
endmodule
| 7.726839 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module LOD16 (
input [15:0] data_i,
output zero_o,
output [15:0] data_o
);
wire [15:0] z;
wire [ 3:0] select;
wire [ 3:0] zdet;
//*****************************************
// Zero detection logic:
//*****************************************
assign zdet[3] = data_i[15] | data_i[14] | data_i[13] | data_i[12];
assign zdet[2] = data_i[11] | data_i[10] | data_i[9] | data_i[8];
assign zdet[1] = data_i[7] | data_i[6] | data_i[5] | data_i[4];
assign zdet[0] = data_i[3] | data_i[2] | data_i[1] | data_i[0];
assign zero_o = ~(zdet[3] | zdet[2] | zdet[1] | zdet[0]);
//*****************************************
// LODs:
//*****************************************
LOD4 lod4_3 (
.data_i(data_i[15:12]),
.data_o(z[15:12])
);
LOD4 lod4_2 (
.data_i(data_i[11:8]),
.data_o(z[11:8])
);
LOD4 lod4_1 (
.data_i(data_i[7:4]),
.data_o(z[7:4])
);
LOD4 lod4_0 (
.data_i(data_i[3:0]),
.data_o(z[3:0])
);
LOD4 lod4_middle (
.data_i(zdet),
.data_o(select)
);
//*****************************************
// Multiplexers :
//*****************************************
Muxes2in1Array4 Inst_MUX214_3 (
.data_i (z[15:12]),
.select_i(select[3]),
.data_o (data_o[15:12])
);
Muxes2in1Array4 Inst_MUX214_2 (
.data_i (z[11:8]),
.select_i(select[2]),
.data_o (data_o[11:8])
);
Muxes2in1Array4 Inst_MUX214_1 (
.data_i (z[7:4]),
.select_i(select[1]),
.data_o (data_o[7:4])
);
Muxes2in1Array4 Inst_MUX214_0 (
.data_i (z[3:0]),
.select_i(select[0]),
.data_o (data_o[3:0])
);
endmodule
| 7.892753 |
module Barrel16L (
input [15:0] data_i,
input [ 3:0] shift_i,
output [ 5:0] data_o
);
reg [15:0] tmp;
always @*
case (shift_i)
4'b0000: tmp = data_i;
4'b0001: tmp = data_i << 1;
4'b0010: tmp = data_i << 2;
4'b0011: tmp = data_i << 3;
4'b0100: tmp = data_i << 4;
4'b0101: tmp = data_i << 5;
4'b0110: tmp = data_i << 6;
4'b0111: tmp = data_i << 7;
4'b1000: tmp = data_i << 8;
4'b1001: tmp = data_i << 9;
4'b1010: tmp = data_i << 10;
4'b1011: tmp = data_i << 11;
4'b1100: tmp = data_i << 12;
4'b1101: tmp = data_i << 13;
4'b1110: tmp = data_i << 14;
default: tmp = data_i << 15;
endcase
assign data_o = tmp[15:10];
endmodule
| 7.500498 |
module Barrel16R (
input [15:0] data_i,
input [3:0] shift_i,
output reg [15:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i >> 1;
4'b0010: data_o = data_i >> 2;
4'b0011: data_o = data_i >> 3;
4'b0100: data_o = data_i >> 4;
4'b0101: data_o = data_i >> 5;
4'b0110: data_o = data_i >> 6;
4'b0111: data_o = data_i >> 7;
4'b1000: data_o = data_i >> 8;
4'b1001: data_o = data_i >> 9;
4'b1010: data_o = data_i >> 10;
4'b1011: data_o = data_i >> 11;
4'b1100: data_o = data_i >> 12;
4'b1101: data_o = data_i >> 13;
4'b1110: data_o = data_i >> 14;
default: data_o = data_i >> 15;
endcase
endmodule
| 7.464977 |
module Barrel32L (
input [31:0] data_i,
input [4:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
5'b00000: data_o = data_i;
5'b00001: data_o = data_i << 1;
5'b00010: data_o = data_i << 2;
5'b00011: data_o = data_i << 3;
5'b00100: data_o = data_i << 4;
5'b00101: data_o = data_i << 5;
5'b00110: data_o = data_i << 6;
5'b00111: data_o = data_i << 7;
5'b01000: data_o = data_i << 8;
5'b01001: data_o = data_i << 9;
5'b01010: data_o = data_i << 10;
5'b01011: data_o = data_i << 11;
5'b01100: data_o = data_i << 12;
5'b01101: data_o = data_i << 13;
5'b01110: data_o = data_i << 14;
5'b01111: data_o = data_i << 15;
default: data_o = data_i << 16;
endcase
endmodule
| 7.342303 |
module FAd (
a,
b,
c,
cy,
sm
);
input a, b, c;
output cy, sm;
wire x, y, z;
xor x1 (x, a, b);
xor x2 (sm, x, c);
and a1 (y, a, b);
and a2 (z, x, c);
or o1 (cy, y, z);
endmodule
| 7.593245 |
module is designed to verify the ALM.v implementation
// Source(file handeling): https://stackoverflow.com/questions/16630319/how-to-read-a-text-file-line-by-line-in-verilog
`define NULL 0
module ALM_tb();
parameter param_XOR6_en = 1'b1;
parameter param_MajAdd_en = 1'b0;
parameter param_fixed = 1'b1;
parameter bitstream_size = 86 + (param_XOR6_en | param_MajAdd_en) + param_MajAdd_en;
// integers (file)
integer data_file; // file handler
reg [bitstream_size-1:0] captured_data;
// file handler
initial begin
data_file = $fopen("./../bitstream.bst", "r");
if (data_file == `NULL) begin
$display("data_file handle was NULL");
$stop;
end
$fscanf(data_file, "%b\n", captured_data);
end
// register and wires
reg clk;
reg clear_async;
reg clear_sync_0;
reg clear_sync_1;
reg clk_en_0;
reg clk_en_1;
reg DataA;
reg DataB;
reg DataC0;
reg DataC1;
reg DataD0;
reg DataD1;
reg DataE;
reg DataF;
reg carry_in;
wire carry_out;
wire out_0;
wire out_1;
wire out_2;
wire out_3;
reg config_clk;
reg config_in;
reg config_en;
wire config_out;
// clock generators
initial begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial begin
config_clk = 1'b0;
forever #5 config_clk = ~config_clk;
end
// initialization of the inputs
initial begin
clear_async = 1'b0;
clear_sync_0 = 1'b0;
clear_sync_1 = 1'b0;
clk_en_0 = 1'b1;
clk_en_1 = 1'b1;
DataA = 1'b0;
DataB = 1'b0;
DataC0 = 1'b0;
DataC1 = 1'b0;
DataD0 = 1'b0;
DataD1 = 1'b0;
DataE = 1'b0;
DataF = 1'b0;
carry_in = 1'b0;
config_in = 1'b0;
config_en = 1'b0;
end
integer counter;
// Test bench senario
initial begin
// to reset the output registers
clear_async = 1'b1;
@(posedge clk)
clear_async = 1'b0;
// to configure the ALM using bitstream
for (counter = bitstream_size-1; counter >= 0; counter = counter - 1) begin
@(posedge clk)
#1
config_en = 1'b1;
config_in = captured_data[counter];
end
@(posedge clk)
config_en = 1'b0;
config_in = 1'b0;
repeat(100) begin
@(posedge clk)
{DataF, DataE, DataD0, DataC0, DataB, DataA} = $random;
#1
counter = DataF + DataE + DataD0 + DataC0 + DataB + DataA;
if ((counter/2)%2 != out_2) begin
$display("Error. C6:111, 2nd bit is NOT on out_2");
end
if ((counter%2) != out_0) begin
$display("Error. C6:111, 1st bit is NOT on out_0");
end
end
$stop;
end
// Designe under test
defparam ALM_inst.param_XOR6_en = param_XOR6_en;
defparam ALM_inst.param_MajAdd_en = param_MajAdd_en;
defparam ALM_inst.param_fixed = param_fixed;
ALM ALM_inst(
.clk(clk),
.clear_async(clear_async),
.clear_sync_0(clear_sync_0),
.clear_sync_1(clear_sync_1),
.clk_en_0(clk_en_0),
.clk_en_1(clk_en_1),
.DataA(DataA),
.DataB(DataB),
.DataC0(DataC0),
.DataC1(DataC1),
.DataD0(DataD0),
.DataD1(DataD1),
.DataE(DataE),
.DataF(DataF),
.carry_in(carry_in),
.carry_out(carry_out),
.out_0(out_0),
.out_1(out_1),
.out_2(out_2),
.out_3(out_3),
.config_clk(config_clk),
.config_in(config_in),
.config_en(config_en),
.config_out(config_out)
);
endmodule
| 7.739429 |
module
//=================================================================
///////////////////////////////////////////////////////////////////
module alorium_lfsr
(
// Clock and Reset
input clk,
input reset_n,
// Inputs
input new_seed,
input enable,
input wire [7:0] seed,
input long_hb,
// Output
output reg heartbeat,
output reg [7:0] lfsr_data
);
reg [29:0] hb_cnt;
wire feedback;
assign feedback = ~(lfsr_data[7] ^ lfsr_data[5] ^
lfsr_data[4] ^ lfsr_data[3]);
always @(posedge clk) begin
if (!reset_n) begin
heartbeat <= 0;
hb_cnt <= 0;
// LFSR register cannot be all 1's for XNOR LFSR
lfsr_data <= 8'h01;
end
else if (new_seed) begin
// LFSR register cannot be all 1's for XNOR LFSR
lfsr_data <= &seed ? 8'h01 : seed;
hb_cnt <= hb_cnt + 1;
end
else if (enable) begin
lfsr_data <= {lfsr_data[6:0],feedback};
hb_cnt <= hb_cnt + 1;
end // else: !if(!reset_n)
if ((long_hb) && (hb_cnt > 9999999)) begin
hb_cnt <= 0;
heartbeat <= ~heartbeat;
end
else if ((!long_hb) && (hb_cnt > 9)) begin
hb_cnt <= 0;
heartbeat <= ~heartbeat;
end
end // always @ (posedge clk)
endmodule
| 7.574158 |
module alpacacorn #(
parameter ADR_WIDTH = `ADR_WIDTH,
parameter DATA_WIDTH = `DATA_WIDTH
) (
input wire clk_i,
input wire rst_i,
input wire [DATA_WIDTH-1:0] data_i,
output wire [DATA_WIDTH-1:0] data_o,
output wire [ADR_WIDTH-1:0] adr_o,
output wire we_o
);
wire carry_dat_ctr;
wire [`CTR_CARRYMUX_WIDTH-1:0] ctr_carrymux_ctr_dat;
wire ctr_a_reg_en_ctr_dat;
wire [`CTR_MARMUX_WIDTH-1:0] ctr_marmux_ctr_adr;
wire ctr_mar_reg_en_ctr_adr;
wire ctr_pc_reg_en_ctr_adr;
wire ctr_d_reg_en;
wire [`OP_WIDTH-1:0] ctr_aluop_ctr_dat;
reg [DATA_WIDTH-1:0] d_reg;
always @(posedge clk_i) begin : seq
if (rst_i) begin
d_reg <= 0;
end else begin
if (ctr_d_reg_en) begin
d_reg <= data_i;
end
end
end
ctr #(
.ADR_WIDTH(ADR_WIDTH)
) i_ctr (
.clk_i(clk_i),
.rst_i(rst_i),
.carry_i(carry_dat_ctr),
.op_i(d_reg[DATA_WIDTH-1:DATA_WIDTH-`OP_WIDTH]),
.ctr_marmux_o(ctr_marmux_ctr_adr),
.ctr_carrymux_o(ctr_carrymux_ctr_dat),
.ctr_a_reg_en_o(ctr_a_reg_en_ctr_dat),
.ctr_d_reg_en_o(ctr_d_reg_en),
.ctr_mar_reg_en_o(ctr_mar_reg_en_ctr_adr),
.ctr_pc_reg_en_o(ctr_pc_reg_en_ctr_adr),
.ctr_aluop_o(ctr_aluop_ctr_dat),
.ctr_we_o(we_o)
);
adr #(
.ADR_WIDTH(ADR_WIDTH)
) i_adr (
.clk_i(clk_i),
.rst_i(rst_i),
.adr_i(d_reg[ADR_WIDTH-1:0]),
.ctr_marmux_i(ctr_marmux_ctr_adr),
.ctr_mar_reg_en_i(ctr_mar_reg_en_ctr_adr),
.ctr_pc_reg_en_i(ctr_pc_reg_en_ctr_adr),
.adr_o(adr_o)
);
dat #(
.DATA_WIDTH(DATA_WIDTH)
) i_dat (
.clk_i(clk_i),
.rst_i(rst_i),
.data_i(d_reg),
.ctr_aluop_i(ctr_aluop_ctr_dat),
.ctr_carrymux_i(ctr_carrymux_ctr_dat),
.ctr_a_reg_en_i(ctr_a_reg_en_ctr_dat),
.carry_o(carry_dat_ctr),
.data_o (data_o)
);
endmodule
| 7.336376 |
module alpacacorn_soc #(
parameter ADR_WIDTH = `ADR_WIDTH,
parameter DATA_WIDTH = `DATA_WIDTH,
parameter FILE = "tb/tb_alpacacorn_soc_i_sram_dual_port.hex"
) (
input wire clk_i,
input wire rst_n_i,
input wire rs232_rx_i,
output wire rs232_tx_o,
input wire rts_n_i,
output wire cts_n_o,
input wire dtr_n_i,
output wire dsr_n_o,
output wire dcd_n_o,
output wire [7:0] led_fpga_o
);
wire rst;
wire [DATA_WIDTH-1:0] data_sram_alpacacorn;
wire [DATA_WIDTH-1:0] data_alpacacorn_sram;
wire [ADR_WIDTH-1:0] adr_from_alpacacorn;
wire we_from_alpacacorn;
/* Toplevel module instantiations */
rsthandler i_rsthandler (
.clk_i(clk_i),
.rst_button_n_i(rst_n_i),
.rst_o(rst)
);
alpacacorn #(
.ADR_WIDTH (ADR_WIDTH),
.DATA_WIDTH(DATA_WIDTH)
) i_alpacacorn (
.clk_i (clk_i),
.rst_i (rst),
.data_i(data_sram_alpacacorn),
.data_o(data_alpacacorn_sram),
.adr_o (adr_from_alpacacorn),
.we_o (we_from_alpacacorn)
);
sram_dual_port #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADR_WIDTH),
.FILE(FILE)
) i_sram_dual_port (
.wclk_i (clk_i),
.rclk_i (clk_i),
.wen_i (we_from_alpacacorn),
.waddr_i(adr_from_alpacacorn),
.raddr_i(adr_from_alpacacorn),
.data_i (data_alpacacorn_sram),
.data_o (data_sram_alpacacorn)
);
wire [6:0] id_from_led;
led #(
.CONFIG_ID(`ALPACACORN_CONFIG_ID)
) i_led (
.clk_i(clk_i),
.rst_i(rst),
.led_o(id_from_led)
);
wire [11:0] count_led;
wire en_snif_count;
snif #(
.ADR_WIDTH(ADR_WIDTH)
) i_snif (
.clk_i(clk_i),
.rst_i(rst),
.adr_i(adr_from_alpacacorn),
.we_i(we_from_alpacacorn),
.detect_o(en_snif_count)
);
count #(
.WIDTH(12)
) i_count (
.clk_i(clk_i),
.rst_i(rst),
.en_i(en_snif_count),
.count_o(count_led)
);
assign dsr_n_o = 0;
assign dcd_n_o = 0;
assign cts_n_o = 0;
assign rs232_tx_o = 1;
assign led_fpga_o = {count_led[11], id_from_led};
endmodule
| 7.376328 |
module alpha (
input clk,
input [7:0] sw,
input [3:0] pb,
output [7:0] led,
output [6:0] seg,
output dp,
output [3:0] an
);
// Hard Programmed Key
wire [63:0] key = 64'hb5ff63141a19e1a9;
// Import Programmed Plaintext Values
// Pulls in a value mess which contains
// 256 64-bit values to be encoded as the
// secret message.
`include "messages.vh"
// Internal Signals
reg [63:0] in; /* synthesis preserve */
wire [63:0] out;
wire [15:0] data;
reg pb_h; /* synthesis preserve */
reg [ 1:0] byte_sel; /* synthesis preserve */
wire [ 3:0] data_dp;
// Instantiate The DES Top Level
des_enc des_enc (
.clk(clk),
.in (in),
.rst(pb[2]),
.key(key),
.out(out)
);
// Instantiate the 7 SEG Display
seven_seg_dis seven_seg_dis (
.clk(clk),
.rst(pb[3]),
.data_in(data),
.data_dp(data_dp),
.seg(seg),
.dp(dp),
.an(an)
);
// Output Switches to LEDs
assign led = sw;
// Control Output to 7-Segment Display
assign data = (byte_sel[1]) ?
((byte_sel[0]) ? out[63:48] : out[47:32]):
((byte_sel[0]) ? out[31:16] : out[15:0]);
assign data_dp = (byte_sel[1]) ?
((byte_sel[0]) ? ~4'h8 : ~4'h4):
((byte_sel[0]) ? ~4'h2 : ~4'h1);
// User Operation
always @(posedge clk) begin
if (pb[3]) begin
in <= 64'h0000_0000_0000_0000;
pb_h <= 0;
byte_sel <= 2'b00;
end else begin
in <= mess;
// Attempt Minimal Debounce for the PB
pb_h <= pb[0];
if (pb[0] & (~pb_h)) begin
byte_sel <= byte_sel + 2'b01;
end
end
end
endmodule
| 7.148552 |
module alpha2_input_butterfly_1 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_10 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_11 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_12 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_13 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_14 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_15 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_16 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_17 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_18 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_19 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_2 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_20 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_21 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_22 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_23 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_24 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_25 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_26 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_27 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_28 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_29 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_3 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_30 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_31 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_32 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_33 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_34 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_35 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_36 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_37 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_38 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_39 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_4 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_40 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_41 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_42 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_43 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_44 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_45 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_46 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
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