code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Barrel16R (
input [15:0] data_i,
input [3:0] shift_i,
output reg [15:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i >> 1;
4'b0010: data_o = data_i >> 2;
4'b0011: data_o = data_i >> 3;
4'b0100: data_o = data_i >> 4;
... | 7.464977 |
module Barrel32L (
input [31:0] data_i,
input [4:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
5'b00000: data_o = data_i;
5'b00001: data_o = data_i << 1;
5'b00010: data_o = data_i << 2;
5'b00011: data_o = data_i << 3;
5'b00100: data_o = data_i << 4;
... | 7.342303 |
module FAd (
a,
b,
c,
cy,
sm
);
input a, b, c;
output cy, sm;
wire x, y, z;
xor x1 (x, a, b);
xor x2 (sm, x, c);
and a1 (y, a, b);
and a2 (z, x, c);
or o1 (cy, y, z);
endmodule
| 7.593245 |
module ALM_fixed (
input clk,
input clear_async,
input clear_sync_0,
input clear_sync_1,
input clk_en_0,
input clk_en_1,
input DataA,
input DataB,
input DataC0,
input DataC1,
input DataD0,
input DataD1,
input DataE,
input DataF,
input carry_in,
outp... | 7.892724 |
module is designed to model ALM and it's hyperflex registers. ALM model is just instanciated from ALM.v
// This file is prepared according to the "Intel® Stratix® 10 Logic Array Blocks and Adaptive Logic Modules User Guide", UG-S10-Lab-2018.09.21 and "Intel Stratix 10 GX/SX Device Overview"
module ALM_HF(
// contro... | 7.739429 |
module MISTRAL_ALUT3 (
input A,
B,
C,
output Q
);
parameter [7:0] LUT = 8'h00;
`ifdef cyclonev
specify
(A => Q) = 510;
(B => Q) = 400;
(C => Q) = 97;
endspecify
`endif
`ifdef cyclone10gx
specify
(A => Q) = 165;
(B => Q) = 162;
(C => Q) = 53;
endspecify
`endif
assi... | 6.533542 |
module ALM_SOA5 (
input [ 7:0] x,
input [ 7:0] y,
output [15:0] p
);
// Generate abs values
wire [7:0] x_abs;
wire [7:0] y_abs;
// Going for X_abs
assign x_abs = x ^ {8{x[7]}};
// Going for Y_abs
assign y_abs = y ^ {8{y[7]}};
// LOD x
wire [7:0] kx;
wire zero_x;
wire [2:0] code... | 6.87208 |
module LOD8 (
input [7:0] data_i,
output zero_o,
output [7:0] data_o
);
wire [7:0] z;
wire [1:0] zdet;
wire [1:0] select;
//*****************************************
// Zero detection logic:
//*****************************************
assign zdet[1] = |(data_i[7:4]);
assign zdet[0] = |(data... | 6.992495 |
module LOD2 (
input [1:0] data_i,
output [1:0] data_o
);
assign data_o[1] = data_i[1];
assign data_o[0] = ~data_i[1] & data_i[0];
endmodule
| 7.907297 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module PriorityEncoder_8 (
input [7:0] data_i,
output [2:0] code_o
);
wire [3:0] tmp0;
assign tmp0 = {data_i[7], data_i[5], data_i[3], data_i[1]};
OR_tree code0 (
tmp0,
code_o[0]
);
wire [3:0] tmp1;
assign tmp1 = {data_i[7], data_i[6], data_i[3], data_i[2]};
OR_tree code1 (
tm... | 6.599169 |
module OR_tree (
input [3:0] data_i,
output data_o
);
wire [1:0] tmp1;
assign tmp1 = data_i[1:0] | data_i[3:2];
assign data_o = tmp1[0] | tmp1[1];
endmodule
| 7.726839 |
module Barrel8L (
input [7:0] data_i,
input [2:0] shift_i,
output [2:0] data_o
);
reg [15:0] tmp;
always @*
case (shift_i)
3'b000: tmp = data_i;
3'b001: tmp = data_i << 1;
3'b010: tmp = data_i << 2;
3'b011: tmp = data_i << 3;
3'b100: tmp = data_i << 4;
3'b... | 7.145832 |
module Barrel8R (
input [7:0] data_i,
input [2:0] shift_i,
output reg [7:0] data_o
);
always @*
case (shift_i)
3'b000: data_o = data_i;
3'b001: data_o = data_i << 1;
3'b010: data_o = data_i << 2;
3'b011: data_o = data_i << 3;
3'b100: data_o = data_i << 4;
3'b... | 7.052818 |
module Barrel16L (
input [15:0] data_i,
input [3:0] shift_i,
output reg [15:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i << 1;
4'b0010: data_o = data_i << 2;
4'b0011: data_o = data_i << 3;
4'b0100: data_o = data_i << 4;
... | 7.500498 |
module PriorityEncoder_16_old (
input [15:0] data_i,
output reg [3:0] code_o
);
always @*
case (data_i)
16'b0000000000000001: code_o = 4'b0000;
16'b0000000000000010: code_o = 4'b0001;
16'b0000000000000100: code_o = 4'b0010;
16'b0000000000001000: code_o = 4'b0011;
16'b0000000... | 6.599169 |
module PriorityEncoder_16 (
input [15:0] data_i,
output [ 3:0] code_o
);
wire [7:0] tmp0;
assign tmp0 = {
data_i[15], data_i[13], data_i[11], data_i[9], data_i[7], data_i[5], data_i[3], data_i[1]
};
OR_tree code0 (
tmp0,
code_o[0]
);
wire [7:0] tmp1;
assign tmp1 = {
data_i[1... | 6.599169 |
module OR_tree (
input [7:0] data_i,
output data_o
);
wire [3:0] tmp1;
wire [1:0] tmp2;
assign tmp1 = data_i[3:0] | data_i[7:4];
assign tmp2 = tmp1[1:0] | tmp1[3:2];
assign data_o = tmp2[0] | tmp2[1];
endmodule
| 7.726839 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module LOD16 (
input [15:0] data_i,
output zero_o,
output [15:0] data_o
);
wire [15:0] z;
wire [ 3:0] select;
wire [ 3:0] zdet;
//*****************************************
// Zero detection logic:
//*****************************************
assign zdet[3] = data_i[15] | data_i[14] | data... | 7.892753 |
module Barrel16L (
input [15:0] data_i,
input [ 3:0] shift_i,
output [ 6:0] data_o
);
reg [15:0] tmp;
always @*
case (shift_i)
4'b0000: tmp = data_i;
4'b0001: tmp = data_i << 1;
4'b0010: tmp = data_i << 2;
4'b0011: tmp = data_i << 3;
4'b0100: tmp = data_i << 4;
... | 7.500498 |
module Barrel16R (
input [15:0] data_i,
input [3:0] shift_i,
output reg [15:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i >> 1;
4'b0010: data_o = data_i >> 2;
4'b0011: data_o = data_i >> 3;
4'b0100: data_o = data_i >> 4;
... | 7.464977 |
module Barrel32L (
input [31:0] data_i,
input [4:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
5'b00000: data_o = data_i;
5'b00001: data_o = data_i << 1;
5'b00010: data_o = data_i << 2;
5'b00011: data_o = data_i << 3;
5'b00100: data_o = data_i << 4;
... | 7.342303 |
module FAd (
a,
b,
c,
cy,
sm
);
input a, b, c;
output cy, sm;
wire x, y, z;
xor x1 (x, a, b);
xor x2 (sm, x, c);
and a1 (y, a, b);
and a2 (z, x, c);
or o1 (cy, y, z);
endmodule
| 7.593245 |
module ALM_SOA_W11 (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
// Generate abs values
wire [15:0] x_abs;
wire [15:0] y_abs;
// Going for X_abs
assign x_abs = x ^ {16{x[15]}};
// Going for Y_abs
assign y_abs = y ^ {16{y[15]}};
// LOD x
wire [15:0] kx;
wire zero_x;
wire ... | 6.861534 |
module PriorityEncoder_16_old (
input [15:0] data_i,
output reg [3:0] code_o
);
always @*
case (data_i)
16'b0000000000000001: code_o = 4'b0000;
16'b0000000000000010: code_o = 4'b0001;
16'b0000000000000100: code_o = 4'b0010;
16'b0000000000001000: code_o = 4'b0011;
16'b0000000... | 6.599169 |
module PriorityEncoder_16 (
input [15:0] data_i,
output [ 3:0] code_o
);
wire [7:0] tmp0;
assign tmp0 = {
data_i[15], data_i[13], data_i[11], data_i[9], data_i[7], data_i[5], data_i[3], data_i[1]
};
OR_tree code0 (
tmp0,
code_o[0]
);
wire [7:0] tmp1;
assign tmp1 = {
data_i[1... | 6.599169 |
module OR_tree (
input [7:0] data_i,
output data_o
);
wire [3:0] tmp1;
wire [1:0] tmp2;
assign tmp1 = data_i[3:0] | data_i[7:4];
assign tmp2 = tmp1[1:0] | tmp1[3:2];
assign data_o = tmp2[0] | tmp2[1];
endmodule
| 7.726839 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module LOD16 (
input [15:0] data_i,
output zero_o,
output [15:0] data_o
);
wire [15:0] z;
wire [ 3:0] select;
wire [ 3:0] zdet;
//*****************************************
// Zero detection logic:
//*****************************************
assign zdet[3] = data_i[15] | data_i[14] | data_i... | 7.892753 |
module Barrel16L (
input [15:0] data_i,
input [ 3:0] shift_i,
output [ 5:0] data_o
);
reg [15:0] tmp;
always @*
case (shift_i)
4'b0000: tmp = data_i;
4'b0001: tmp = data_i << 1;
4'b0010: tmp = data_i << 2;
4'b0011: tmp = data_i << 3;
4'b0100: tmp = data_i << 4;
... | 7.500498 |
module Barrel16R (
input [15:0] data_i,
input [3:0] shift_i,
output reg [15:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i >> 1;
4'b0010: data_o = data_i >> 2;
4'b0011: data_o = data_i >> 3;
4'b0100: data_o = data_i >> 4;
... | 7.464977 |
module Barrel32L (
input [31:0] data_i,
input [4:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
5'b00000: data_o = data_i;
5'b00001: data_o = data_i << 1;
5'b00010: data_o = data_i << 2;
5'b00011: data_o = data_i << 3;
5'b00100: data_o = data_i << 4;
... | 7.342303 |
module FAd (
a,
b,
c,
cy,
sm
);
input a, b, c;
output cy, sm;
wire x, y, z;
xor x1 (x, a, b);
xor x2 (sm, x, c);
and a1 (y, a, b);
and a2 (z, x, c);
or o1 (cy, y, z);
endmodule
| 7.593245 |
module ALM_SOA_W12 (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
// Generate abs values
wire [15:0] x_abs;
wire [15:0] y_abs;
// Going for X_abs
assign x_abs = x ^ {16{x[15]}};
// Going for Y_abs
assign y_abs = y ^ {16{y[15]}};
// LOD x
wire [15:0] kx;
wire zero_x;
wire ... | 7.215881 |
module PriorityEncoder_16_old (
input [15:0] data_i,
output reg [3:0] code_o
);
always @*
case (data_i)
16'b0000000000000001: code_o = 4'b0000;
16'b0000000000000010: code_o = 4'b0001;
16'b0000000000000100: code_o = 4'b0010;
16'b0000000000001000: code_o = 4'b0011;
16'b0000000... | 6.599169 |
module PriorityEncoder_16 (
input [15:0] data_i,
output [ 3:0] code_o
);
wire [7:0] tmp0;
assign tmp0 = {
data_i[15], data_i[13], data_i[11], data_i[9], data_i[7], data_i[5], data_i[3], data_i[1]
};
OR_tree code0 (
tmp0,
code_o[0]
);
wire [7:0] tmp1;
assign tmp1 = {
data_i[1... | 6.599169 |
module OR_tree (
input [7:0] data_i,
output data_o
);
wire [3:0] tmp1;
wire [1:0] tmp2;
assign tmp1 = data_i[3:0] | data_i[7:4];
assign tmp2 = tmp1[1:0] | tmp1[3:2];
assign data_o = tmp2[0] | tmp2[1];
endmodule
| 7.726839 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module LOD16 (
input [15:0] data_i,
output zero_o,
output [15:0] data_o
);
wire [15:0] z;
wire [ 3:0] select;
wire [ 3:0] zdet;
//*****************************************
// Zero detection logic:
//*****************************************
assign zdet[3] = data_i[15] | data_i[14] | data_i... | 7.892753 |
module Barrel16L (
input [15:0] data_i,
input [ 3:0] shift_i,
output [ 5:0] data_o
);
reg [15:0] tmp;
always @*
case (shift_i)
4'b0000: tmp = data_i;
4'b0001: tmp = data_i << 1;
4'b0010: tmp = data_i << 2;
4'b0011: tmp = data_i << 3;
4'b0100: tmp = data_i << 4;
... | 7.500498 |
module Barrel16R (
input [15:0] data_i,
input [3:0] shift_i,
output reg [15:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i >> 1;
4'b0010: data_o = data_i >> 2;
4'b0011: data_o = data_i >> 3;
4'b0100: data_o = data_i >> 4;
... | 7.464977 |
module Barrel32L (
input [31:0] data_i,
input [4:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
5'b00000: data_o = data_i;
5'b00001: data_o = data_i << 1;
5'b00010: data_o = data_i << 2;
5'b00011: data_o = data_i << 3;
5'b00100: data_o = data_i << 4;
... | 7.342303 |
module FAd (
a,
b,
c,
cy,
sm
);
input a, b, c;
output cy, sm;
wire x, y, z;
xor x1 (x, a, b);
xor x2 (sm, x, c);
and a1 (y, a, b);
and a2 (z, x, c);
or o1 (cy, y, z);
endmodule
| 7.593245 |
module ALM_SOA_W13 (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
// Generate abs values
wire [15:0] x_abs;
wire [15:0] y_abs;
// Going for X_abs
assign x_abs = x ^ {16{x[15]}};
// Going for Y_abs
assign y_abs = y ^ {16{y[15]}};
// LOD x
wire [15:0] kx;
wire zero_x;
wire ... | 6.695534 |
module PriorityEncoder_16_old (
input [15:0] data_i,
output reg [3:0] code_o
);
always @*
case (data_i)
16'b0000000000000001: code_o = 4'b0000;
16'b0000000000000010: code_o = 4'b0001;
16'b0000000000000100: code_o = 4'b0010;
16'b0000000000001000: code_o = 4'b0011;
16'b0000000... | 6.599169 |
module PriorityEncoder_16 (
input [15:0] data_i,
output [ 3:0] code_o
);
wire [7:0] tmp0;
assign tmp0 = {
data_i[15], data_i[13], data_i[11], data_i[9], data_i[7], data_i[5], data_i[3], data_i[1]
};
OR_tree code0 (
tmp0,
code_o[0]
);
wire [7:0] tmp1;
assign tmp1 = {
data_i[1... | 6.599169 |
module OR_tree (
input [7:0] data_i,
output data_o
);
wire [3:0] tmp1;
wire [1:0] tmp2;
assign tmp1 = data_i[3:0] | data_i[7:4];
assign tmp2 = tmp1[1:0] | tmp1[3:2];
assign data_o = tmp2[0] | tmp2[1];
endmodule
| 7.726839 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module LOD16 (
input [15:0] data_i,
output zero_o,
output [15:0] data_o
);
wire [15:0] z;
wire [ 3:0] select;
wire [ 3:0] zdet;
//*****************************************
// Zero detection logic:
//*****************************************
assign zdet[3] = data_i[15] | data_i[14] | data_i... | 7.892753 |
module Barrel16L (
input [15:0] data_i,
input [ 3:0] shift_i,
output [ 5:0] data_o
);
reg [15:0] tmp;
always @*
case (shift_i)
4'b0000: tmp = data_i;
4'b0001: tmp = data_i << 1;
4'b0010: tmp = data_i << 2;
4'b0011: tmp = data_i << 3;
4'b0100: tmp = data_i << 4;
... | 7.500498 |
module Barrel16R (
input [15:0] data_i,
input [3:0] shift_i,
output reg [15:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i >> 1;
4'b0010: data_o = data_i >> 2;
4'b0011: data_o = data_i >> 3;
4'b0100: data_o = data_i >> 4;
... | 7.464977 |
module Barrel32L (
input [31:0] data_i,
input [4:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
5'b00000: data_o = data_i;
5'b00001: data_o = data_i << 1;
5'b00010: data_o = data_i << 2;
5'b00011: data_o = data_i << 3;
5'b00100: data_o = data_i << 4;
... | 7.342303 |
module FAd (
a,
b,
c,
cy,
sm
);
input a, b, c;
output cy, sm;
wire x, y, z;
xor x1 (x, a, b);
xor x2 (sm, x, c);
and a1 (y, a, b);
and a2 (z, x, c);
or o1 (cy, y, z);
endmodule
| 7.593245 |
module is designed to verify the ALM.v implementation
// Source(file handeling): https://stackoverflow.com/questions/16630319/how-to-read-a-text-file-line-by-line-in-verilog
`define NULL 0
module ALM_tb();
parameter param_XOR6_en = 1'b1;
parameter param_MajAdd_en = 1'b0;
parameter param_fixed = 1'b1;
parameter... | 7.739429 |
module
//=================================================================
///////////////////////////////////////////////////////////////////
module alorium_lfsr
(
// Clock and Reset
input clk,
input reset_n,
// Inputs
input new_seed,
input enable,
input wire [7:0] seed,
input long_hb,
//... | 7.574158 |
module alpacacorn #(
parameter ADR_WIDTH = `ADR_WIDTH,
parameter DATA_WIDTH = `DATA_WIDTH
) (
input wire clk_i,
input wire rst_i,
input wire [DATA_WIDTH-1:0] data_i,
output wire [DATA_WIDTH-1:0] data_o,
output wire [ADR_WIDTH-1:0] adr_o,
output wire we_o
);
wire carry_dat_ctr;
wi... | 7.336376 |
module alpacacorn_soc #(
parameter ADR_WIDTH = `ADR_WIDTH,
parameter DATA_WIDTH = `DATA_WIDTH,
parameter FILE = "tb/tb_alpacacorn_soc_i_sram_dual_port.hex"
) (
input wire clk_i,
input wire rst_n_i,
input wire rs232_rx_i,
output wire rs232_tx_o,
input wire rts_n_i,
output wire cts_... | 7.376328 |
module alpha (
input clk,
input [7:0] sw,
input [3:0] pb,
output [7:0] led,
output [6:0] seg,
output dp,
output [3:0] an
);
// Hard Programmed Key
wire [63:0] key = 64'hb5ff63141a19e1a9;
// Import Programmed Plaintext Values
// Pulls in a value mess which contains
/... | 7.148552 |
module alpha2_input_butterfly_1 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pro... | 6.698209 |
module alpha2_input_butterfly_10 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_11 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_12 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_13 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_14 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_15 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_16 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_17 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_18 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_19 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_2 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pro... | 6.698209 |
module alpha2_input_butterfly_20 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_21 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_22 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_23 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_24 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_25 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_26 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_27 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_28 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_29 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_3 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pro... | 6.698209 |
module alpha2_input_butterfly_30 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_31 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_32 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_33 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_34 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_35 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_36 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_37 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_38 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_39 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_4 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pro... | 6.698209 |
module alpha2_input_butterfly_40 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_41 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_42 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_43 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_44 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_45 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_46 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
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