code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module spmv_scatter_pipe #(
parameter PIPE_DEPTH = 3,
parameter URAM_DATA_W = 32
) (
input wire clk,
input wire rst,
input wire [ 31:0] edge_weight,
input wire [URAM_DATA_W-1:0] src_attr,
input wire [ 31:0] edge_dest,
input wire [ 0:0] input_valid,
output wire [ 31:0] update_value,
output wire [ 31:0] update_dest,
output wire [ 0:0] output_valid
);
reg [31:0] dest_reg[PIPE_DEPTH-1:0];
assign update_dest = dest_reg[PIPE_DEPTH-1];
integer i;
always @(posedge clk) begin
if (rst) begin
for (i = 0; i < PIPE_DEPTH; i = i + 1) begin
dest_reg[i] <= 0;
end
end else begin
for (i = 1; i < PIPE_DEPTH; i = i + 1) begin
dest_reg[i] <= dest_reg[i-1];
end
dest_reg[0] <= edge_dest;
end
end
fp_mul multiplier (
.aclk(clk),
.s_axis_a_tvalid(input_valid),
.s_axis_a_tdata(edge_weight),
.s_axis_b_tvalid(input_valid),
.s_axis_b_tdata(src_attr),
.m_axis_result_tvalid(output_valid),
.m_axis_result_tready(1'b1),
.m_axis_result_tdata(update_value)
);
endmodule
| 7.323698 |
module pr_PP #(
parameter PIPE_DEPTH = 5,
parameter URAM_DATA_W = 64,
parameter PAR_SIZE_W = 10,
parameter EDGE_W = 64
) (
input wire clk,
input wire rst,
input wire [ 1:0] control,
input wire [URAM_DATA_W-1:0] buffer_Din,
input wire buffer_Din_valid,
input wire [ EDGE_W-1:0] input_word,
input wire [ 0:0] input_valid,
output wire [URAM_DATA_W-1:0] buffer_Dout,
output wire [ PAR_SIZE_W-1:0] buffer_Dout_Addr,
output wire buffer_Dout_valid,
output wire [ 63:0] output_word,
output wire [ 0:0] output_valid,
output wire [ 0:0] par_active
);
reg [EDGE_W-1:0] input_word_reg;
reg [0:0] input_valid_reg;
always @(posedge clk) begin
if (rst) begin
input_word_reg <= 0;
input_valid_reg <= 0;
end else begin
input_word_reg <= input_word;
input_valid_reg <= input_valid;
end
end
pr_scatter_pipe #(
.PIPE_DEPTH (PIPE_DEPTH),
.URAM_DATA_W(URAM_DATA_W)
) scatter_unit (
.clk(clk),
.rst(rst),
.edge_weight(),
.src_attr(buffer_Dout),
.edge_dest(input_word_reg[63:32]),
.input_valid(input_valid_reg && buffer_Din_valid && control == 1),
.update_value(output_word[63:32]),
.update_dest(output_word[31:0]),
.output_valid(output_valid)
);
pr_gather_pipe #(
.PIPE_DEPTH (PIPE_DEPTH),
.PAR_SIZE_W (PAR_SIZE_W),
.URAM_DATA_W(URAM_DATA_W)
) gather_unit (
.clk(clk),
.rst(rst),
.update_value(input_word_reg[63:32]),
.update_dest(input_word_reg[31:0]),
.dest_attr(buffer_Din),
.input_valid(input_valid_reg && buffer_Din_valid && control == 2),
.WData(buffer_Dout),
.WAddr(buffer_Dout_Addr),
.Wvalid(buffer_Dout_valid),
.par_active(par_active)
);
endmodule
| 7.751799 |
module pr_gather_pipe #(
parameter PIPE_DEPTH = 3,
parameter PAR_SIZE_W = 18,
parameter URAM_DATA_W = 64
) (
input wire clk,
input wire rst,
input wire [ 31:0] update_value,
input wire [ 31:0] update_dest,
input wire [URAM_DATA_W-1:0] dest_attr,
input wire [ 0:0] input_valid,
output wire [URAM_DATA_W-1:0] WData,
output wire [ PAR_SIZE_W-1:0] WAddr,
output wire [ 0:0] Wvalid,
output wire [ 0:0] par_active
);
reg [ 0:0] valid_reg[PIPE_DEPTH-1:0];
reg [31:0] dest_reg [PIPE_DEPTH-1:0];
assign WAddr = dest_reg[PIPE_DEPTH-1][PAR_SIZE_W-1:0];
assign par_active = 1'b1;
reg [31:0] dest_attr_reg[PIPE_DEPTH-1:0];
integer i;
always @(posedge clk) begin
if (rst) begin
for (i = 0; i < PIPE_DEPTH; i = i + 1) begin
dest_reg[i] <= 0;
dest_attr_reg[i] <= 0;
end
end else begin
for (i = 1; i < PIPE_DEPTH; i = i + 1) begin
dest_reg[i] <= dest_reg[i-1];
dest_attr_reg[i] <= dest_attr_reg[i-1];
end
dest_reg[0] <= update_dest;
dest_attr_reg[0] <= dest_attr[63:32];
end
end
fp_add adder (
.aclk(clk),
.s_axis_a_tvalid(input_valid),
.s_axis_a_tdata(update_value),
.s_axis_b_tvalid(input_valid),
.s_axis_b_tdata(dest_attr[31:0]),
.m_axis_result_tvalid(Wvalid),
.m_axis_result_tready(1'b1),
.m_axis_result_tdata(WData[31:0])
);
assign WData[63:32] = dest_attr_reg[PIPE_DEPTH-1];
endmodule
| 7.88561 |
module pr_scatter_pipe #(
parameter PIPE_DEPTH = 3,
parameter URAM_DATA_W = 64
) (
input wire clk,
input wire rst,
input wire [ 31:0] edge_weight,
input wire [URAM_DATA_W-1:0] src_attr,
input wire [ 31:0] edge_dest,
input wire [ 0:0] input_valid,
output wire [ 31:0] update_value,
output wire [ 31:0] update_dest,
output wire [ 0:0] output_valid
);
reg [31:0] dest_reg[PIPE_DEPTH-1:0];
assign update_dest = dest_reg[PIPE_DEPTH-1];
integer i;
always @(posedge clk) begin
if (rst) begin
for (i = 0; i < PIPE_DEPTH; i = i + 1) begin
dest_reg[i] <= 0;
end
end else begin
for (i = 1; i < PIPE_DEPTH; i = i + 1) begin
dest_reg[i] <= dest_reg[i-1];
end
dest_reg[0] <= edge_dest;
end
end
fp_mul multiplier (
.aclk(clk),
.s_axis_a_tvalid(input_valid),
.s_axis_a_tdata(src_attr[31:0]),
.s_axis_b_tvalid(input_valid),
.s_axis_b_tdata(src_attr[63:32]),
.m_axis_result_tvalid(output_valid),
.m_axis_result_tdata(update_value)
);
endmodule
| 7.920956 |
module sssp_PP #(
parameter PIPE_DEPTH = 5,
parameter URAM_DATA_W = 32,
parameter PAR_SIZE_W = 10,
parameter EDGE_W = 64
) (
input wire clk,
input wire rst,
input wire [ 1:0] control,
input wire [ URAM_DATA_W-1:0] buffer_Din,
input wire buffer_Din_valid,
input wire [ EDGE_W-1:0] input_word,
input wire [ 0:0] input_valid,
output wire [ URAM_DATA_W-1:0] buffer_Dout,
output wire [ PAR_SIZE_W-1:0] buffer_Dout_Addr,
output wire buffer_Dout_valid,
output wire [ 63:0] output_word,
output wire [ 0:0] output_valid,
output wire [ 0:0] par_active,
input wire [PAR_SIZE_W+URAM_DATA_W-1:0] forward_input0,
input wire [PAR_SIZE_W+URAM_DATA_W-1:0] forward_input1,
input wire [PAR_SIZE_W+URAM_DATA_W-1:0] forward_input2,
input wire [PAR_SIZE_W+URAM_DATA_W-1:0] forward_input3,
input wire [PAR_SIZE_W+URAM_DATA_W-1:0] forward_input4,
input wire [PAR_SIZE_W+URAM_DATA_W-1:0] forward_input5,
input wire [PAR_SIZE_W+URAM_DATA_W-1:0] forward_input6,
input wire [PAR_SIZE_W+URAM_DATA_W-1:0] forward_input7,
output wire [PAR_SIZE_W+URAM_DATA_W-1:0] forward_output
);
reg [EDGE_W-1:0] input_word_reg;
reg [0:0] input_valid_reg;
always @(posedge clk) begin
if (rst) begin
input_word_reg <= 0;
input_valid_reg <= 0;
end else begin
input_word_reg <= input_word;
input_valid_reg <= input_valid;
end
end
sssp_scatter_pipe #(
.PIPE_DEPTH (PIPE_DEPTH),
.URAM_DATA_W(URAM_DATA_W)
) scatter_unit (
.clk(clk),
.rst(rst),
.edge_weight(input_word_reg[63:48]),
.src_attr(buffer_Dout),
.edge_dest(input_word_reg[47:24]),
.input_valid(input_valid_reg && buffer_Din_valid && control == 1),
.update_value(output_word[63:32]),
.update_dest(output_word[31:0]),
.output_valid(output_valid)
);
wire [31:0] dest_attr;
sssp_gather_pipe #(
.PIPE_DEPTH (PIPE_DEPTH),
.PAR_SIZE_W (PAR_SIZE_W),
.URAM_DATA_W(URAM_DATA_W)
) gather_unit (
.clk(clk),
.rst(rst),
.update_value(input_word_reg[63:32]),
.update_dest(input_word_reg[31:0]),
.dest_attr(dest_attr),
.input_valid(input_valid_reg && buffer_Din_valid && control == 2),
.WData(buffer_Dout),
.WAddr(buffer_Dout_Addr),
.Wvalid(buffer_Dout_valid),
.par_active(par_active)
);
assign dest_attr = ((control==2) && (input_word_reg[PAR_SIZE_W-1:0]==forward_input0[PAR_SIZE_W+URAM_DATA_W-1:URAM_DATA_W])) ? forward_input0[URAM_DATA_W-1:0] :
((control==2) && (input_word_reg[PAR_SIZE_W-1:0]==forward_input1[PAR_SIZE_W+URAM_DATA_W-1:URAM_DATA_W])) ? forward_input1[URAM_DATA_W-1:0] :
((control==2) && (input_word_reg[PAR_SIZE_W-1:0]==forward_input2[PAR_SIZE_W+URAM_DATA_W-1:URAM_DATA_W])) ? forward_input2[URAM_DATA_W-1:0] :
((control==2) && (input_word_reg[PAR_SIZE_W-1:0]==forward_input3[PAR_SIZE_W+URAM_DATA_W-1:URAM_DATA_W])) ? forward_input3[URAM_DATA_W-1:0] :
((control==2) && (input_word_reg[PAR_SIZE_W-1:0]==forward_input4[PAR_SIZE_W+URAM_DATA_W-1:URAM_DATA_W])) ? forward_input4[URAM_DATA_W-1:0] :
((control==2) && (input_word_reg[PAR_SIZE_W-1:0]==forward_input5[PAR_SIZE_W+URAM_DATA_W-1:URAM_DATA_W])) ? forward_input5[URAM_DATA_W-1:0] :
((control==2) && (input_word_reg[PAR_SIZE_W-1:0]==forward_input6[PAR_SIZE_W+URAM_DATA_W-1:URAM_DATA_W])) ? forward_input6[URAM_DATA_W-1:0] :
((control==2) && (input_word_reg[PAR_SIZE_W-1:0]==forward_input7[PAR_SIZE_W+URAM_DATA_W-1:URAM_DATA_W])) ? forward_input7[URAM_DATA_W-1:0] : buffer_Din;
assign forward_output = {buffer_Dout_Addr, buffer_Dout};
endmodule
| 7.398986 |
module sssp_gather_pipe #(
parameter PIPE_DEPTH = 1,
parameter PAR_SIZE_W = 18,
parameter URAM_DATA_W = 32
) (
input wire clk,
input wire rst,
input wire [ 31:0] update_value,
input wire [ 31:0] update_dest,
input wire [URAM_DATA_W-1:0] dest_attr,
input wire [ 0:0] input_valid,
output reg [URAM_DATA_W-1:0] WData,
output reg [ PAR_SIZE_W-1:0] WAddr,
output reg [ 0:0] Wvalid,
output reg [ 0:0] par_active
);
always @(posedge clk) begin
if (rst) begin
WData <= 0;
WAddr <= 0;
Wvalid <= 0;
par_active <= 0;
end else begin
WAddr <= update_dest[PAR_SIZE_W-1:0];
WData[30:0] <= (update_value < dest_attr) ? update_value[30:0] : dest_attr[30:0];
WData[31:31] <= input_valid && (update_value < dest_attr[30:0]);
Wvalid <= input_valid && (update_value < dest_attr[30:0]);
par_active <= input_valid && (update_value < dest_attr[30:0]);
end
end
endmodule
| 7.379624 |
module sssp_scatter_pipe #(
parameter PIPE_DEPTH = 3,
parameter URAM_DATA_W = 32
) (
input wire clk,
input wire rst,
input wire [ 15:0] edge_weight,
input wire [URAM_DATA_W-1:0] src_attr,
input wire [ 23:0] edge_dest,
input wire [ 0:0] input_valid,
output reg [ 31:0] update_value,
output reg [ 31:0] update_dest,
output reg [ 0:0] output_valid
);
always @(posedge clk) begin
if (rst) begin
output_valid <= 0;
update_value <= 0;
update_dest <= 0;
end else begin
output_valid <= input_valid && src_attr[URAM_DATA_W-1:URAM_DATA_W-1];
update_value <= edge_weight + src_attr[URAM_DATA_W-2:0];
update_dest <= edge_dest;
end
end
endmodule
| 7.591014 |
module wcc_PP #(
parameter PIPE_DEPTH = 5,
parameter URAM_DATA_W = 32,
parameter PAR_SIZE_W = 10,
parameter EDGE_W = 64
) (
input wire clk,
input wire rst,
input wire [ 1:0] control,
input wire [ URAM_DATA_W-1:0] buffer_Din,
input wire buffer_Din_valid,
input wire [ EDGE_W-1:0] input_word,
input wire [ 0:0] input_valid,
output wire [ URAM_DATA_W-1:0] buffer_Dout,
output wire [ PAR_SIZE_W-1:0] buffer_Dout_Addr,
output wire buffer_Dout_valid,
output wire [ 63:0] output_word,
output wire [ 0:0] output_valid,
output wire [ 0:0] par_active,
input wire [PAR_SIZE_W+URAM_DATA_W-1:0] forward_input0,
input wire [PAR_SIZE_W+URAM_DATA_W-1:0] forward_input1,
input wire [PAR_SIZE_W+URAM_DATA_W-1:0] forward_input2,
input wire [PAR_SIZE_W+URAM_DATA_W-1:0] forward_input3,
input wire [PAR_SIZE_W+URAM_DATA_W-1:0] forward_input4,
input wire [PAR_SIZE_W+URAM_DATA_W-1:0] forward_input5,
input wire [PAR_SIZE_W+URAM_DATA_W-1:0] forward_input6,
input wire [PAR_SIZE_W+URAM_DATA_W-1:0] forward_input7,
output wire [PAR_SIZE_W+URAM_DATA_W-1:0] forward_output
);
reg [EDGE_W-1:0] input_word_reg;
reg [0:0] input_valid_reg;
always @(posedge clk) begin
if (rst) begin
input_word_reg <= 0;
input_valid_reg <= 0;
end else begin
input_word_reg <= input_word;
input_valid_reg <= input_valid;
end
end
wcc_scatter_pipe #(
.PIPE_DEPTH (PIPE_DEPTH),
.URAM_DATA_W(URAM_DATA_W)
) scatter_unit (
.clk(clk),
.rst(rst),
.edge_weight(),
.src_attr(buffer_Dout),
.edge_dest(input_word_reg[63:32]),
.input_valid(input_valid_reg && buffer_Din_valid && control == 1),
.update_value(output_word[63:32]),
.update_dest(output_word[31:0]),
.output_valid(output_valid)
);
wire [31:0] dest_attr;
wcc_gather_pipe #(
.PIPE_DEPTH (PIPE_DEPTH),
.PAR_SIZE_W (PAR_SIZE_W),
.URAM_DATA_W(URAM_DATA_W)
) gather_unit (
.clk(clk),
.rst(rst),
.update_value(input_word_reg[63:32]),
.update_dest(input_word_reg[31:0]),
.dest_attr(dest_attr),
.input_valid(input_valid_reg && buffer_Din_valid && control == 2),
.WData(buffer_Dout),
.WAddr(buffer_Dout_Addr),
.Wvalid(buffer_Dout_valid),
.par_active(par_active)
);
assign dest_attr = ((control==2) && (input_word_reg[PAR_SIZE_W-1:0]==forward_input0[PAR_SIZE_W+URAM_DATA_W-1:URAM_DATA_W])) ? forward_input0[URAM_DATA_W-1:0] :
((control==2) && (input_word_reg[PAR_SIZE_W-1:0]==forward_input1[PAR_SIZE_W+URAM_DATA_W-1:URAM_DATA_W])) ? forward_input1[URAM_DATA_W-1:0] :
((control==2) && (input_word_reg[PAR_SIZE_W-1:0]==forward_input2[PAR_SIZE_W+URAM_DATA_W-1:URAM_DATA_W])) ? forward_input2[URAM_DATA_W-1:0] :
((control==2) && (input_word_reg[PAR_SIZE_W-1:0]==forward_input3[PAR_SIZE_W+URAM_DATA_W-1:URAM_DATA_W])) ? forward_input3[URAM_DATA_W-1:0] :
((control==2) && (input_word_reg[PAR_SIZE_W-1:0]==forward_input4[PAR_SIZE_W+URAM_DATA_W-1:URAM_DATA_W])) ? forward_input4[URAM_DATA_W-1:0] :
((control==2) && (input_word_reg[PAR_SIZE_W-1:0]==forward_input5[PAR_SIZE_W+URAM_DATA_W-1:URAM_DATA_W])) ? forward_input5[URAM_DATA_W-1:0] :
((control==2) && (input_word_reg[PAR_SIZE_W-1:0]==forward_input6[PAR_SIZE_W+URAM_DATA_W-1:URAM_DATA_W])) ? forward_input6[URAM_DATA_W-1:0] :
((control==2) && (input_word_reg[PAR_SIZE_W-1:0]==forward_input7[PAR_SIZE_W+URAM_DATA_W-1:URAM_DATA_W])) ? forward_input7[URAM_DATA_W-1:0] : buffer_Din;
assign forward_output = {buffer_Dout_Addr, buffer_Dout};
endmodule
| 6.979337 |
module wcc_gather_pipe #(
parameter PIPE_DEPTH = 1,
parameter PAR_SIZE_W = 18,
parameter URAM_DATA_W = 32
) (
input wire clk,
input wire rst,
input wire [ 31:0] update_value,
input wire [ 31:0] update_dest,
input wire [URAM_DATA_W-1:0] dest_attr,
input wire [ 0:0] input_valid,
output reg [URAM_DATA_W-1:0] WData,
output reg [ PAR_SIZE_W-1:0] WAddr,
output reg [ 0:0] Wvalid,
output reg [ 0:0] par_active
);
always @(posedge clk) begin
if (rst) begin
WData <= 0;
WAddr <= 0;
Wvalid <= 0;
par_active <= 0;
end else begin
WAddr <= update_dest[PAR_SIZE_W-1:0];
WData[30:0] <= (update_value < dest_attr) ? update_value[30:0] : dest_attr[30:0];
WData[31:31] <= input_valid && (update_value[30:0] < dest_attr[30:0]);
Wvalid <= input_valid && (update_value[30:0] < dest_attr[30:0]);
par_active <= input_valid && (update_value[30:0] < dest_attr[30:0]);
end
end
endmodule
| 7.202247 |
module wcc_scatter_pipe #(
parameter PIPE_DEPTH = 3,
parameter URAM_DATA_W = 32
) (
input wire clk,
input wire rst,
input wire [ 15:0] edge_weight,
input wire [URAM_DATA_W-1:0] src_attr,
input wire [ 31:0] edge_dest,
input wire [ 0:0] input_valid,
output reg [ 31:0] update_value,
output reg [ 31:0] update_dest,
output reg [ 0:0] output_valid
);
always @(posedge clk) begin
if (rst) begin
output_valid <= 0;
update_value <= 0;
update_dest <= 0;
end else begin
output_valid <= input_valid && src_attr[URAM_DATA_W-1:URAM_DATA_W-1];
update_value <= src_attr[URAM_DATA_W-2:0];
update_dest <= edge_dest;
end
end
endmodule
| 7.522624 |
module decompressor_16 (
input [15:0] data_in,
output [31:0] data_out
);
// decompress the 16-bit input into a 32-bit FP number
reg [ 5:0] total_sum;
wire [ 7:0] exp;
wire [22:0] mantissa;
always @(*) begin
casez (data_in[14:0])
15'b1??_????_????_????: total_sum = 1;
15'b01?_????_????_????: total_sum = 2;
15'b001_????_????_????: total_sum = 3;
15'b000_1???_????_????: total_sum = 4;
15'b000_01??_????_????: total_sum = 5;
15'b000_001?_????_????: total_sum = 6;
15'b000_0001_????_????: total_sum = 7;
15'b000_0000_1???_????: total_sum = 8;
15'b000_0000_01??_????: total_sum = 9;
15'b000_0000_001?_????: total_sum = 10;
15'b000_0000_0001_????: total_sum = 11;
15'b000_0000_0000_1???: total_sum = 12;
15'b000_0000_0000_01??: total_sum = 13;
15'b000_0000_0000_001?: total_sum = 14;
15'b000_0000_0000_0001: total_sum = 15;
default: total_sum = 0;
endcase
end
assign exp = 127 - total_sum;
assign mantissa = {data_in[14:0] << total_sum, 8'b0};
assign data_out = {data_in[15], exp, mantissa};
endmodule
| 7.759808 |
module decompressor_8 (
input [ 7:0] data_in,
output [31:0] data_out
);
// decompress the 8-bit input into a 32-bit FP number
reg [ 5:0] total_sum;
wire [ 7:0] exp;
wire [22:0] mantissa;
always @(*) begin
casez (data_in[6:0])
7'b1??_????: total_sum = 1;
7'b01?_????: total_sum = 2;
7'b001_????: total_sum = 3;
7'b000_1???: total_sum = 4;
7'b000_01??: total_sum = 5;
7'b000_001?: total_sum = 6;
7'b000_0001: total_sum = 7;
default: total_sum = 0;
endcase
end
assign exp = 127 - total_sum;
assign mantissa = {data_in[6:0] << total_sum, 16'b0};
assign data_out = {data_in[7], exp, mantissa};
endmodule
| 7.759808 |
module ALGO_cmos_8_16bit (
input rst,
input pclk,
input [7:0] pdata_i,
input de_i,
input fe_i,
output reg [15:0] pdata_o,
output reg cmos_vsync,
output reg cmos_href,
output reg de_o
);
reg [7:0] pdata_i_d0;
reg [7:0] pdata_i_d1;
reg de_i_d0;
reg [11:0] x_cnt;
// reg cmos_vsync_t;
// reg cmos_href_t;
always @(posedge pclk) begin
de_i_d0 <= de_i;
pdata_i_d0 <= pdata_i;
pdata_i_d1 <= pdata_i_d0;
end
always @(posedge pclk or posedge rst) begin
if (rst) x_cnt <= 12'd0;
else if (de_i) x_cnt <= x_cnt + 12'd1;
else x_cnt <= 12'd0;
end
always @(posedge pclk or posedge rst) begin
if (rst) de_o <= 1'b0;
else if (de_i && x_cnt[0]) de_o <= 1'b1;
else de_o <= 1'b0;
end
always @(posedge pclk or posedge rst) begin
if (rst) pdata_o <= 16'd0;
else if (de_i && x_cnt[0]) pdata_o <= {pdata_i_d0, pdata_i};
else pdata_o <= 16'd0;
end
always @(posedge pclk or posedge rst) begin
if (rst) begin
// cmos_vsync_t <= 0;
// cmos_href_t <= 0;
cmos_vsync <= 0;
cmos_href <= 0;
end else begin
cmos_vsync <= fe_i;
cmos_href <= de_i;
// cmos_vsync <= cmos_vsync_t;
// cmos_href <= cmos_href_t;
end
end
endmodule
| 7.114431 |
module ALGO_pro #(
parameter H_HSV_THRE_MIN = 32'h0,
parameter H_HSV_THRE_MAX = 32'h3DCCCCCD,
parameter S_HSV_THRE_MIN = 0,
parameter S_HSV_THRE_MAX = 32'h3DCCCCCD,
parameter V_HSV_THRE_MIN = 0,
parameter V_HSV_THRE_MAX = 32'h3DCCCCCD
) (
i_cmos_rst_n,
i_cmos_d_pclk,
i_cmos_d,
i_cmos_de,
i_cmos_href,
i_cmos_vsys,
o_hue,
o_href,
o_vsys,
o_data_en
);
input i_cmos_rst_n;
input i_cmos_d_pclk;
input [15:0] i_cmos_d;
input i_cmos_de;
input i_cmos_href;
input i_cmos_vsys;
output [7:0] o_hue;
output o_href;
output o_vsys;
output o_data_en;
wire [7:0] o_y_8b;
wire [7:0] o_cb_8b;
wire [7:0] o_cr_8b;
wire o_hs_422_444;
wire o_vs_422_444;
wire o_data_en_422_444;
ALGO_yuv422_2yuv444 u1 (
.clk (i_cmos_d_pclk),
.rst_n (i_cmos_rst_n),
.i_vs (i_cmos_vsys),
.i_hs (i_cmos_href),
.i_q_16b (i_cmos_d),
.i_data_en(i_cmos_de),
.o_y_8b (o_y_8b),
.o_cb_8b (o_cb_8b),
.o_cr_8b (o_cr_8b),
.o_vs (o_vs_422_444),
.o_hs (o_hs_422_444),
.o_data_en(o_data_en_422_444)
);
wire [7:0] o_r_8b;
wire [7:0] o_g_8b;
wire [7:0] o_b_8b;
wire o_hs_444_888;
wire o_vs_444_888;
wire o_data_en_444_888;
ALGO_yuv444_2rgb888_1 u2 (
.clk (i_cmos_d_pclk),
//.rst_n (i_cmos_rst_n),
.i_y_8b (o_y_8b),
.i_cb_8b (o_cb_8b),
.i_cr_8b (o_cr_8b),
.i_hs (o_hs_422_444),
.i_vs (o_vs_422_444),
.i_data_en(o_data_en_422_444),
.o_r_8b (o_r_8b),
.o_g_8b (o_g_8b),
.o_b_8b (o_b_8b),
.o_vs (o_vs_444_888),
.o_hs (o_hs_444_888),
.o_data_en(o_data_en_444_888)
);
ALGO_rgb888_2hue8 #(
.H_HSV_THRE_MIN(H_HSV_THRE_MIN),
.H_HSV_THRE_MAX(H_HSV_THRE_MAX),
.S_HSV_THRE_MIN(S_HSV_THRE_MIN),
.S_HSV_THRE_MAX(S_HSV_THRE_MAX),
.V_HSV_THRE_MIN(V_HSV_THRE_MIN),
.V_HSV_THRE_MAX(V_HSV_THRE_MAX)
) u3 (
.clk (i_cmos_d_pclk),
.rst_n (i_cmos_rst_n),
.i_vs (o_vs_444_888),
.i_hs (o_hs_444_888),
.i_data_en(o_data_en_444_888),
.i_r_8b (o_b_8b),
.i_g_8b (o_g_8b),
.i_b_8b (o_r_8b),
.o_vs (o_vsys),
.o_hs (o_href),
.o_hue (o_hue),
.o_data_en(o_data_en)
);
endmodule
| 7.454435 |
module decompressor (
input [31:0] decomp_in,
input [1:0] bitmap,
output reg [31:0] result
);
wire [ 7:0] in_8;
wire [15:0] in_16;
wire [31:0] result_8;
wire [31:0] result_16;
assign in_8 = decomp_in[7:0];
assign in_16 = decomp_in[15:0];
decompressor_8 d8_inst (
in_8,
result_8
);
decompressor_16 d16_inst (
in_16,
result_16
);
always @(*) begin
case (bitmap)
2'b00: result <= 0;
2'b01: result <= {result_8[7:0], result_8[15:8], result_8[23:16], result_8[31:24]};
2'b10: result <= {result_16[7:0], result_16[15:8], result_16[23:16], result_16[31:24]};
2'b11: result <= decomp_in;
endcase
end
endmodule
| 7.153112 |
module alg_ae #(
parameter BITS = 8
) (
input pclk,
input rst_n,
input in_vsync,
input stat_done,
input [BITS-1:0] target_val,
input [31:0] pix_cnt,
input [31:0] sum,
output reg [7:0] dgain,
output reg cmos_change_start,
input cmos_change_done,
output reg [9:0] cmos_exposure,
output reg [9:0] cmos_gain
);
`define AE_USE_SHIFT_DIV 1
reg prev_sync;
always @(posedge pclk) prev_sync <= in_vsync;
wire frame_start = ~in_vsync & prev_sync;
always @(posedge pclk or negedge rst_n) begin
if (!rst_n) begin
cmos_change_start <= 0;
end else if (!cmos_change_done) begin
cmos_change_start <= 0;
end else if (frame_start) begin
cmos_change_start <= 1;
end else begin
cmos_change_start <= cmos_change_start;
end
end
`ifdef AE_USE_SHIFT_DIV
wire [33:0] gain0, remain;
wire div_done;
shift_div #(34) div_gain (
pclk,
rst_n,
stat_done,
pix_cnt * target_val,
sum[31:4],
gain0,
remain,
div_done
);
always @(posedge pclk or negedge rst_n) begin
if (!rst_n) dgain <= 8'h10;
else if (div_done) dgain <= gain0 > 32'd255 ? 8'd255 : gain0[7:0];
else dgain <= dgain;
end
`else
reg [31:0] gain0;
wire div_done = frame_start;
always @(posedge pclk or negedge rst_n) begin
if (!rst_n) begin
gain0 <= 8'h10;
end else if (stat_done) begin
gain0 <= pix_cnt * target_val / sum[31:4];
end else begin
gain0 <= gain0;
end
end
always @(posedge pclk) dgain <= gain0 > 32'd255 ? 8'd255 : gain0[7:0];
`endif
always @(posedge pclk or negedge rst_n) begin
if (!rst_n) begin
cmos_exposure = 10'h80;
cmos_gain = 10'h10;
end else if (div_done) begin : ae_change_blk
reg [14:0] expo_diff, gain_diff;
if (gain0[9:0] > 20) begin
expo_diff = (((cmos_exposure * gain0[9:0]) >> 4) - cmos_exposure) >> 1;
expo_diff = expo_diff > 0 ? expo_diff : 1;
gain_diff = (((cmos_gain * gain0[9:0]) >> 4) - cmos_gain) >> 1;
gain_diff = gain_diff > 0 ? gain_diff : 1;
if (cmos_exposure < 10'h3ff) begin
if (cmos_exposure + expo_diff > 10'h3ff) cmos_exposure = 10'h3ff;
else cmos_exposure = cmos_exposure + expo_diff;
end else if (cmos_gain < 10'h3ff) begin
if (cmos_gain + gain_diff > 10'h3ff) cmos_gain = 10'h3ff;
else cmos_gain = cmos_gain + gain_diff;
end
end else if (gain0[9:0] < 12) begin
expo_diff = (cmos_exposure - ((cmos_exposure * gain0[9:0]) >> 4)) >> 1;
expo_diff = expo_diff > 0 ? expo_diff : 1;
gain_diff = (cmos_gain - ((cmos_gain * gain0[9:0]) >> 4)) >> 1;
gain_diff = gain_diff > 0 ? gain_diff : 1;
if (cmos_gain > 16) begin
if (cmos_gain < 16 + gain_diff) cmos_gain = 16;
else cmos_gain = cmos_gain - gain_diff;
end else if (cmos_exposure > 10'h1) begin
if (cmos_exposure < 1 + expo_diff) cmos_exposure = 10'h1;
else cmos_exposure = cmos_exposure - expo_diff;
end
end
end
end
endmodule
| 7.107459 |
module alg_awb #(
parameter BITS = 8
) (
input pclk,
input rst_n,
input stat_done,
input [31:0] pix_cnt,
input [31:0] sum_r,
input [31:0] sum_g,
input [31:0] sum_b,
output reg [7:0] r_gain,
output reg [7:0] g_gain,
output reg [7:0] b_gain
);
`define AWB_USE_SHIFT_DIV 1
always @(*) g_gain = 8'h10;
`ifdef AWB_USE_SHIFT_DIV
wire [31:0] r_gain0, r_remain;
wire r_div_done;
shift_div #(32) div_rgain (
pclk,
rst_n,
stat_done,
sum_g,
{4'd0, sum_r[31:4]},
r_gain0,
r_remain,
r_div_done
);
always @(posedge pclk or negedge rst_n) begin
if (!rst_n) begin
r_gain <= 8'h10;
end else if (r_div_done) begin
r_gain <= r_gain0 > 32'd255 ? 8'd255 : r_gain0[7:0];
end else begin
r_gain <= r_gain;
end
end
wire [31:0] b_gain0, b_remain;
wire b_div_done;
shift_div #(32) div_bgain (
pclk,
rst_n,
stat_done,
sum_g,
{4'd0, sum_b[31:4]},
b_gain0,
b_remain,
b_div_done
);
always @(posedge pclk or negedge rst_n) begin
if (!rst_n) begin
b_gain <= 8'h10;
end else if (b_div_done) begin
b_gain <= b_gain0 > 32'd255 ? 8'd255 : b_gain0[7:0];
end else begin
b_gain <= b_gain;
end
end
`else
always @(posedge pclk or negedge rst_n) begin
if (!rst_n) begin
r_gain <= 8'h10;
b_gain <= 8'h10;
end else if (stat_done) begin
r_gain <= sum_g / sum_r[31:4];
b_gain <= sum_g / sum_b[31:4];
end else begin
r_gain <= r_gain;
b_gain <= b_gain;
end
end
`endif
endmodule
| 7.693443 |
module Alice (
input a,
input b,
output [1:0] qubit
);
wire [1:0] eigen_value = {a, b};
//There can be 4 possible eigen value
//Eigen Value = 2'b00 => Zero
//Eigen Value = 2'b01 => Plus
//Eigen Value = 2'b10 => One
//Eigen Value = 2'b11 => Minus
//These Eigen Values are equivalent of the Quantum State of the Qubit
assign qubit = eigen_value;
endmodule
| 6.781856 |
module align (
input [15:0] a,
output [15:0] value,
output z_s
);
assign value = a[15] ? -a : a;
assign z_s = a[15];
endmodule
| 7.456157 |
module AlignedRAM (
input [31:0] addr,
inout [31:0] data,
input [1:0] size,
input rw,
clk
);
parameter ADDR = 32'h2000_0000;
parameter SIZE = 256;
localparam REAL_SIZE = SIZE / 4;
reg [31:0] mem[REAL_SIZE-1:0];
reg [31:0] buffer;
wire enabled = (addr >= ADDR) && (addr < (ADDR + SIZE));
wire [31:0] internal_addr = (addr - ADDR) >> 2;
always @(posedge clk) begin
if (enabled && rw) begin
case (size)
//2'b01: mem[internal_addr][(addr[1:0] * 8 + 7):(addr[1:0] * 8)] <= data[7:0];
//2'b10: mem[internal_addr][(addr[1] ? 31 : 15):(addr[1] ? 16 : 0)] <= data[15:0];
2'b11: mem[internal_addr] <= data;
endcase
end
end
always @(posedge clk) begin
if (enabled && !rw) begin
buffer = mem[internal_addr];
case (size)
2'b01: buffer = (buffer >> (addr[1:0] * 8)) & 32'hff;
2'b10: buffer = (buffer >> (addr[1] ? 16 : 0)) & 32'hffff;
endcase
end
end
assign data = (enabled && !rw) ? buffer : 32'bz;
endmodule
| 7.979075 |
module aligner (
Exp_a_DI,
Exp_b_DI,
Exp_c_DI,
Mant_a_DI,
Sign_a_DI,
Sign_b_DI,
Sign_c_DI,
Pp_sum_DI,
Pp_carry_DI,
Sub_SO,
Mant_postalig_a_DO,
Exp_postalig_DO,
Sign_postalig_DO,
Sign_amt_DO,
Sft_stop_SO,
Pp_sum_postcal_DO,
Pp_carry_postcal_DO
);
parameter C_RM = 2;
parameter C_RM_NEAREST = 2'h0;
parameter C_RM_TRUNC = 2'h1;
parameter C_RM_PLUSINF = 2'h2;
parameter C_RM_MINUSINF = 2'h3;
parameter C_PC = 5;
parameter C_OP = 32;
parameter C_MANT = 23;
parameter C_EXP = 8;
parameter C_BIAS = 127;
parameter C_HALF_BIAS = 63;
parameter C_LEADONE_WIDTH = 7;
parameter C_MANT_PRENORM = C_MANT + 1;
parameter C_EXP_ZERO = 8'h00;
parameter C_EXP_ONE = 8'h01;
parameter C_EXP_INF = 8'hff;
parameter C_MANT_ZERO = 23'h0;
parameter C_MANT_NAN = 23'h400000;
input wire [C_EXP - 1:0] Exp_a_DI;
input wire [C_EXP - 1:0] Exp_b_DI;
input wire [C_EXP - 1:0] Exp_c_DI;
input wire [C_MANT:0] Mant_a_DI;
input wire Sign_a_DI;
input wire Sign_b_DI;
input wire Sign_c_DI;
input wire [(2 * C_MANT) + 2:0] Pp_sum_DI;
input wire [(2 * C_MANT) + 2:0] Pp_carry_DI;
output wire Sub_SO;
output wire [74:0] Mant_postalig_a_DO;
output wire [C_EXP + 1:0] Exp_postalig_DO;
output wire Sign_postalig_DO;
output wire Sign_amt_DO;
output wire Sft_stop_SO;
output wire [(2 * C_MANT) + 2:0] Pp_sum_postcal_DO;
output wire [(2 * C_MANT) + 2:0] Pp_carry_postcal_DO;
wire [C_EXP + 1:0] Exp_dif_D;
wire [C_EXP + 1:0] Sft_amt_D;
assign Sub_SO = (Sign_a_DI ^ Sign_b_DI) ^ Sign_c_DI;
assign Exp_dif_D = ((Exp_a_DI - Exp_b_DI) - Exp_c_DI) + C_BIAS;
assign Sft_amt_D = (((Exp_b_DI + Exp_c_DI) - Exp_a_DI) - C_BIAS) + 27;
assign Sign_amt_DO = Sft_amt_D[C_EXP+1];
wire Sft_stop_S;
assign Sft_stop_S = ~Sft_amt_D[C_EXP+1] && (Sft_amt_D[C_EXP:0] >= 74);
assign Sft_stop_SO = Sft_stop_S;
function automatic [0:0] sv2v_cast_1;
input reg [0:0] inp;
sv2v_cast_1 = inp;
endfunction
assign Exp_postalig_DO = (Sft_amt_D[C_EXP+1] ? Exp_a_DI : {sv2v_cast_1(
((Exp_b_DI + Exp_c_DI) - C_BIAS) + 27
)});
wire [73:0] Mant_postalig_a_D;
wire [C_MANT:0] Bit_sftout_D;
assign {Mant_postalig_a_D, Bit_sftout_D} = {Mant_a_DI, 74'h0000000000000000000} >> {(Sft_stop_S ? 0 : Sft_amt_D)};
assign Mant_postalig_a_DO = (Sft_amt_D[C_EXP + 1] ? {1'b0, Mant_a_DI, 50'h0000000000000} : {(Sft_stop_S ? 75'h0000000000000000000 : {(Sub_SO ? {1'b1, ~Mant_postalig_a_D} : {1'b0, Mant_postalig_a_D})})});
assign Sign_postalig_DO = (Sft_amt_D[C_EXP+1] ? Sign_a_DI : Sign_b_DI ^ Sign_c_DI);
assign Pp_sum_postcal_DO = (Sft_amt_D[C_EXP + 1] ? {(((2 * C_MANT) + 2) >= 0 ? (2 * C_MANT) + 3 : 1 - ((2 * C_MANT) + 2)) {1'sb0}} : Pp_sum_DI);
assign Pp_carry_postcal_DO = (Sft_amt_D[C_EXP + 1] ? {(((2 * C_MANT) + 2) >= 0 ? (2 * C_MANT) + 3 : 1 - ((2 * C_MANT) + 2)) {1'sb0}} : Pp_carry_DI);
endmodule
| 6.674309 |
module Aligner_tb;
reg clk;
reg reset;
reg wrt_en;
reg push0;
reg pop0;
wire empty0;
wire full0;
wire almost_full0;
reg push1;
reg pop1;
wire empty1;
wire full1;
wire almost_full1;
reg [ 15 : 0] tag_out;
reg [255 : 0] cpr_data_out;
reg [ 7 : 0] len_out;
reg [271 : 0] data_in;
reg [ 7 : 0] len;
wire [255 : 0] data_out;
wire valid;
wire stall;
wire [ 8 : 0] new_len;
wire [ 8 : 0] cur_len;
wire [279 : 0] aligner_in;
wire [279 : 0] fifo_out0;
wire [ 8 : 0] fifo_count0;
wire [255 : 0] fifo_out1;
wire [ 8 : 0] fifo_count1;
initial begin
clk = 1;
reset = 1;
wrt_en = 1;
push0 = 0;
pop0 = 0;
push1 = 0;
pop1 = 0;
@(posedge clk);
push0 = 1;
reset = 0;
cpr_data_out = 256'h0000_0000_0000_0000_0000_0000_A987_6543_21FE_DCBA_9876_5432_1FED_CBA9_8765_4321;
tag_out = 16'b1010101010101111;
len_out = 8'h16;
cpr_data_out = 256'hFEDC_BA98_FEDC_BA98_FEDC_BA98_FEDC_BA98_FEDC_BA98_FEDC_BA98_FEDC_BA98_FEDC_BA98;
tag_out = 16'hFFFF;
$display("fifo_out1 %h", fifo_out1);
@(posedge clk);
pop0 = 1;
if (empty1 == 1'b0) pop1 = 1'b1;
else pop1 = 1'b0;
$display("fifo_out1 %h", fifo_out1);
@(posedge clk);
if (empty1 == 1'b0) pop1 = 1'b1;
else pop1 = 1'b0;
$display("fifo_out1 %h", fifo_out1);
@(posedge clk);
if (empty1 == 1'b0) pop1 = 1'b1;
else pop1 = 1'b0;
$display("fifo_out1 %h", fifo_out1);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
$finish;
end
assign aligner_in = (empty0 == 1'b0 & pop0 == 1'b1) ? fifo_out0 : 0;
FIFO #(
.DATA_WIDTH(280), // 16 + 256 + 8
.ADDR_WIDTH(8)
) fifo0 (
clk,
reset,
push0,
pop0,
{cpr_data_out, tag_out, len_out},
fifo_out0,
empty0,
full0,
almostfull0,
fifo_count0
);
Aligner #(
.DATA_IN_WIDTH(272),
.LEN_WIDTH(8),
.DATA_OUT_WIDTH(256)
) al0 (
clk,
reset,
wrt_en,
aligner_in[279 : 8], // tag + cpr_data
aligner_in[7 : 0], // len
data_out,
valid,
stall
);
FIFO #(
.DATA_WIDTH(256),
.ADDR_WIDTH(8)
) fifo1 (
clk,
reset,
valid,
pop1,
data_out,
fifo_out1,
empty1,
full1,
almostfull1,
fifo_count1
);
always #1 clk = ~clk;
initial begin
$dumpfile("aligner.vcd");
$dumpvars(0, Aligner_tb);
end
endmodule
| 6.559776 |
module alignment (
input [14:0] bigger,
input [14:0] smaller,
output [10:0] aligned_small
);
wire c1;
wire [4:0] bigger_exponent, smaller_exponent, shift_bits;
assign bigger_exponent = bigger [14:10];
assign smaller_exponent = smaller [14:10];
assign aligned_small = ({1'b1,smaller[9:0]} >> shift_bits);
cla_nbit #(
.n(5)
) u1 (
bigger_exponent,
~smaller_exponent + 1'b1,
1'b0,
shift_bits,
c1
);
endmodule
| 6.625423 |
module Alignment_2 (
bef_shift_x,
bef_shift_y,
sgn_d,
out_x,
out_y
);
input [23:0] bef_shift_x, bef_shift_y;
input sgn_d;
output reg [23:0] out_x, out_y;
always @(*) begin
if(sgn_d) //SWAP bloc;
begin
out_x = bef_shift_y;
out_y = bef_shift_x;
end else begin
out_x = bef_shift_x;
out_y = bef_shift_y;
end
end
endmodule
| 6.922723 |
module Alignment_4_2 (
shR_y,
d,
out_y_shR
);
input [52:0] shR_y;
input [7:0] d;
output reg [52:0] out_y_shR;
always @(*) begin
out_y_shR = shR_y >> d;
end
endmodule
| 7.688765 |
module Alignment_4_3 (
out_y_shR,
sticky
);
input [52:0] out_y_shR;
output reg sticky;
always @(*) begin
sticky = |out_y_shR[26:0];
end
endmodule
| 6.844722 |
module Alignment_4_4 (
out_y_shR,
sticky,
out_y_with_T
);
input [52:0] out_y_shR;
input sticky;
output reg [26:0] out_y_with_T;
always @(*) begin
out_y_with_T = {out_y_shR[52:27], sticky};
end
endmodule
| 6.931663 |
module Alignment_5 (
Mx,
My,
Cmp
);
input [22:0] Mx, My;
output reg Cmp;
always @(*) begin
if(Mx>=My) //Compare Block
begin
Cmp = 1'b0;
end else begin
Cmp = 1'b1;
end
end
endmodule
| 6.978224 |
module Alignment_7 (
bit_inv_cont_x,
bit_inv_cont_y,
out_x_shR,
out_y_with_T,
out_11,
out_22
);
input bit_inv_cont_x, bit_inv_cont_y;
input [26:0] out_x_shR;
input [26:0] out_y_with_T;
output reg [26:0] out_11;
output reg [26:0] out_22;
always @(*) begin
if (bit_inv_cont_x) begin
out_11 = ~out_x_shR;
end else begin
out_11 = out_x_shR;
end
if (bit_inv_cont_y) begin
out_22 = ~out_y_with_T;
end else begin
out_22 = out_y_with_T;
end
end
endmodule
| 7.081253 |
module align_1 (
input [7:0] BE,
input [7:0] AE,
output reg [7:0] d
);
always @(AE, BE) begin
if (AE > BE) begin
d = AE - BE;
end else if (AE < BE) begin
d = BE - AE;
end else begin
d = 8'b0;
end
end
endmodule
| 6.70445 |
module align_16 (
input clk,
input [3:0] pos,
input din_valid,
input [15:0] din, // lsbit first
output reg [15:0] dout // lsbit first
);
initial dout = 0;
reg [16+15-1:0] mid = 0;
always @(posedge clk) begin
if (din_valid) begin
case (pos[3:2])
2'b00: mid <= {din, mid[30:16]};
2'b01: mid <= {4'b0, din, mid[26:16]};
2'b10: mid <= {8'h0, din, mid[22:16]};
2'b11: mid <= {12'h0, din, mid[18:16]};
endcase
end
end
always @(posedge clk) begin
case (pos[1:0])
2'b00: dout <= mid[15:0];
2'b01: dout <= mid[16:1];
2'b10: dout <= mid[17:2];
2'b11: dout <= mid[18:3];
endcase
end
endmodule
| 7.017779 |
module align_clk_sync #(
// fsm type parameter
parameter N = 32
) (
// Input side
input clk_in,
input rst_in,
input [N-1:0] i_data,
input i_valid,
output o_stall,
// Output side
input clk_out,
input rst_out,
output [N-1:0] o_data,
output o_valid,
input i_stall
);
// ==========================================================================
// Input side logic (clk_in)
// ==========================================================================
reg [N-1:0] data_q;
reg head_q;
wire latch_input = i_valid & ~o_stall;
always @(posedge clk_in) begin
if (rst_in) begin
head_q <= #`dh 1'b0;
end else begin
if (latch_input) begin
head_q <= #`dh ~head_q;
end
end
end
always @(posedge clk_in) begin
if (latch_input) begin
data_q <= #`dh i_data;
end
end
// ==========================================================================
// Output side logic (clk_out)
// ==========================================================================
reg tail_q;
wire consume_output = o_valid & ~i_stall;
always @(posedge clk_out) begin
if (rst_out) begin
tail_q <= #`dh 1'b0;
end else begin
if (consume_output) begin
tail_q <= #`dh ~tail_q;
end
end
end
// ==========================================================================
// Pointer comparison
// ==========================================================================
wire full = head_q ^ tail_q;
// ==========================================================================
// Module outputs
// ==========================================================================
assign o_data = data_q;
assign o_stall = full;
assign o_valid = full;
endmodule
| 6.562057 |
module align_clk_sync_2 #
(
// fsm type parameter
parameter N = 32
) (
// Input side
input clk_in,
input rst_in,
input [N-1:0] i_data,
input i_valid,
output o_stall,
// Output side
input clk_out,
input rst_out,
output [N-1:0] o_data,
output o_valid,
input i_stall
);
// ==========================================================================
// Input side logic (clk_in)
// ==========================================================================
reg [N-1:0] data0_q;
reg [N-1:0] data1_q;
reg [1:0] head_q;
wire latch_input = i_valid & ~o_stall;
always @(posedge clk_in) begin
if (rst_in) begin
head_q <= #`dh 0;
end
else begin
if (latch_input) begin
head_q <= #`dh head_q + 2'b1;
end
end
end
always @(posedge clk_in) begin
if (latch_input) begin
data0_q <= #`dh (head_q[0]) ? i_data : data0_q;
data1_q <= #`dh (head_q[0]) ? data1_q : i_data;
end
end
// ==========================================================================
// Output side logic (clk_out)
// ==========================================================================
reg [1:0] tail_q;
wire consume_output = o_valid & ~i_stall;
always @(posedge clk_out) begin
if (rst_out) begin
tail_q <= #`dh 0;
end
else begin
if (consume_output) begin
tail_q <= #`dh tail_q + 2'b1;
end
end
end
// ==========================================================================
// Pointer comparison
// ==========================================================================
wire empty = (head_q[0] ~^ tail_q[0]) & (head_q[1] ~^ tail_q[1]);
wire full = (head_q[0] ~^ tail_q[0]) & (head_q[1] ^ tail_q[1]);
// ==========================================================================
// Module outputs (1 LUT delay from registers)
// ==========================================================================
assign o_data = (tail_q[0]) ? data0_q : data1_q;
assign o_stall = full;
assign o_valid = ~empty;
endmodule
| 6.562057 |
module align_clk_sync_2_halfword(
// Input side
input clk_in,
input rst_in,
input [15:0] i_data,
input i_valid_high,
input i_valid_low,
output o_stall,
// Output side
input clk_out,
input rst_out,
output [31:0] o_data,
output o_valid,
input i_stall);
// ==========================================================================
// Input side logic (clk_in)
// ==========================================================================
reg [31:0] data0_q;
reg [31:0] data1_q;
reg [ 1:0] head_q;
wire latch_low = i_valid_low & ~o_stall;
wire latch_high = i_valid_high & ~o_stall;
always @(posedge clk_in) begin
if (rst_in) begin
head_q <= #`dh 0;
end
else begin
if (latch_low) begin
head_q <= #`dh head_q + 2'b1;
end
end
end
always @(posedge clk_in) begin
if(latch_high) begin
data0_q[31:16] <= #`dh (head_q[0]) ? i_data : data0_q[31:16];
data1_q[31:16] <= #`dh (head_q[0]) ? data1_q[31:16] : i_data;
end
if (latch_low) begin
data0_q[15:0] <= #`dh (head_q[0]) ? i_data : data0_q[15:0];
data1_q[15:0] <= #`dh (head_q[0]) ? data1_q[15:0] : i_data;
end
end
// ==========================================================================
// Output side logic (clk_out)
// ==========================================================================
reg [1:0] tail_q;
wire consume_output = o_valid & ~i_stall;
always @(posedge clk_out) begin
if (rst_out) begin
tail_q <= #`dh 0;
end
else begin
if (consume_output) begin
tail_q <= #`dh tail_q + 2'b1;
end
end
end
// ==========================================================================
// Pointer comparison
// ==========================================================================
wire empty = (head_q[0] ~^ tail_q[0]) & (head_q[1] ~^ tail_q[1]);
wire full = (head_q[0] ~^ tail_q[0]) & (head_q[1] ^ tail_q[1]);
// ==========================================================================
// Module outputs (1 LUT delay from registers)
// ==========================================================================
assign o_data = (tail_q[0]) ? data0_q : data1_q;
assign o_stall = full;
assign o_valid = ~empty;
//
endmodule
| 6.562057 |
module align_mux #(
parameter DATA_PATH_WIDTH = 4
) (
input clk,
input [1:0] align,
input [DATA_PATH_WIDTH*8-1:0] in_data,
input [DATA_PATH_WIDTH-1:0] in_charisk,
output reg [DATA_PATH_WIDTH*8-1:0] out_data,
output reg [DATA_PATH_WIDTH-1:0] out_charisk
);
reg [DATA_PATH_WIDTH*8-1:0] in_data_d1;
reg [ DATA_PATH_WIDTH-1:0] in_charisk_d1;
always @(posedge clk) begin
in_data_d1 <= in_data;
in_charisk_d1 <= in_charisk;
end
always @(*) begin
case (align)
'h0: out_data <= in_data_d1;
'h1: out_data <= {in_data[7:0], in_data_d1[31:8]};
'h2: out_data <= {in_data[15:0], in_data_d1[31:16]};
'h3: out_data <= {in_data[23:0], in_data_d1[31:24]};
endcase
case (align)
'h0: out_charisk <= in_charisk_d1;
'h1: out_charisk <= {in_charisk[0:0], in_charisk_d1[3:1]};
'h2: out_charisk <= {in_charisk[1:0], in_charisk_d1[3:2]};
'h3: out_charisk <= {in_charisk[2:0], in_charisk_d1[3:3]};
endcase
end
endmodule
| 7.913104 |
module align_r #(
parameter IN_P_DW_BYTES = 0,
parameter IN_AW = 0,
parameter OUT_P_DW_BYTES = 0
) (
input [ (1<<IN_P_DW_BYTES)*8-1:0] i_dat,
input [ (1<<IN_P_DW_BYTES)-1:0] i_be,
input [ IN_AW-1:0] i_addr,
output [ (1<<OUT_P_DW_BYTES)-1:0] o_be,
output [(1<<OUT_P_DW_BYTES)*8-1:0] o_dat
);
localparam IN_BYTES = (1 << IN_P_DW_BYTES);
localparam OUT_BYTES = (1 << OUT_P_DW_BYTES);
localparam WIN_NUM = (OUT_P_DW_BYTES < IN_P_DW_BYTES) ? (IN_BYTES/OUT_BYTES) : (OUT_BYTES/IN_BYTES);
localparam WIN_P_NUM = (OUT_P_DW_BYTES < IN_P_DW_BYTES) ? (IN_P_DW_BYTES - OUT_P_DW_BYTES) : (OUT_P_DW_BYTES - IN_P_DW_BYTES);
localparam WIN_DW = (OUT_P_DW_BYTES < IN_P_DW_BYTES) ? (OUT_BYTES * 8) : (IN_BYTES * 8);
localparam WIN_P_DW_BYTES = (OUT_P_DW_BYTES < IN_P_DW_BYTES) ? (OUT_P_DW_BYTES) : (IN_P_DW_BYTES);
genvar i;
generate
if (OUT_P_DW_BYTES == IN_P_DW_BYTES) begin : gen_1
assign o_dat = i_dat;
assign o_be = i_be;
end else if (OUT_P_DW_BYTES < IN_P_DW_BYTES) begin : gen_2
wire [ WIN_DW-1:0] rdat_win[WIN_NUM-1:0];
wire [WIN_DW/8-1:0] rbe_win [WIN_NUM-1:0];
for (i = 0; i < WIN_NUM; i = i + 1) begin : gen_r
assign rdat_win[i] = i_dat[i*WIN_DW+:WIN_DW];
assign rbe_win[i] = i_be[i*(WIN_DW/8)+:WIN_DW/8];
end
assign o_dat = rdat_win[i_addr[WIN_P_DW_BYTES+:WIN_P_NUM]];
assign o_be = rbe_win[i_addr[WIN_P_DW_BYTES+:WIN_P_NUM]];
end else begin : gen_3
for (i = 0; i < WIN_NUM; i = i + 1) begin : gen_o
assign o_be[i*(WIN_DW/8) +: (WIN_DW/8)] = {(WIN_DW/8){i_addr[WIN_P_DW_BYTES +: WIN_P_NUM] == i}} & i_be;
assign o_dat[i*WIN_DW+:WIN_DW] = i_dat;
end
end
endgenerate
endmodule
| 6.601645 |
module align_t (
input [15:0] input_a,
output [15:0] a_m,
output [5:0] a_e,
output a_s
);
wire [15:0] a;
assign a = input_a;
assign a_m[15:5] = {1'b1, a[9 : 0]};
assign a_m[4:0] = 8'b0;
assign a_e = a[14 : 10] - 15;
assign a_s = a[15];
endmodule
| 6.666471 |
module align_w #(
parameter IN_P_DW_BYTES = 0,
parameter OUT_P_DW_BYTES = 0,
parameter IN_AW = 0
) (
input [(1<<OUT_P_DW_BYTES)*8-1:0] i_dat,
input [ (1<<OUT_P_DW_BYTES)-1:0] i_be,
input [ IN_AW-1:0] i_addr,
output [ (1<<IN_P_DW_BYTES)-1:0] o_be,
output [ (1<<IN_P_DW_BYTES)*8-1:0] o_out_wdat
);
localparam IN_BYTES = (1 << IN_P_DW_BYTES);
localparam OUT_BYTES = (1 << OUT_P_DW_BYTES);
localparam WIN_NUM = (OUT_P_DW_BYTES <= IN_P_DW_BYTES) ? (IN_BYTES/OUT_BYTES) : (OUT_BYTES/IN_BYTES);
localparam WIN_P_NUM = (OUT_P_DW_BYTES <= IN_P_DW_BYTES) ? (IN_P_DW_BYTES - OUT_P_DW_BYTES) : (OUT_P_DW_BYTES - IN_P_DW_BYTES);
localparam WIN_DW = (OUT_P_DW_BYTES <= IN_P_DW_BYTES) ? (OUT_BYTES * 8) : (IN_BYTES * 8);
localparam WIN_P_DW_BYTES = (OUT_P_DW_BYTES <= IN_P_DW_BYTES) ? (OUT_P_DW_BYTES) : (IN_P_DW_BYTES);
genvar i;
generate
if (OUT_P_DW_BYTES == IN_P_DW_BYTES) begin : gen_1
assign o_be = i_be;
assign o_out_wdat = i_dat;
end else if (OUT_P_DW_BYTES <= IN_P_DW_BYTES) begin : gen_2
for (i = 0; i < WIN_NUM; i = i + 1) begin : gen_o
assign o_be[i*(WIN_DW/8) +: (WIN_DW/8)] = ({(WIN_DW/8){i_addr[WIN_P_DW_BYTES +: WIN_P_NUM] == i}} & i_be);
assign o_out_wdat[i*WIN_DW+:WIN_DW] = i_dat;
end
end else begin : gen_3
wire [WIN_DW-1:0] i_axi_din_win[WIN_NUM-1:0];
wire [WIN_DW/8-1:0] i_be_win[WIN_NUM-1:0];
for (i = 0; i < WIN_NUM; i = i + 1) begin : gen_i
assign i_axi_din_win[i] = i_dat[i*WIN_DW+:WIN_DW];
assign i_be_win[i] = i_be[i*(WIN_DW/8)+:(WIN_DW/8)];
end
assign o_be = i_be_win[i_addr[WIN_P_DW_BYTES+:WIN_P_NUM]];
assign o_out_wdat = i_axi_din_win[i_addr[WIN_P_DW_BYTES+:WIN_P_NUM]];
end
endgenerate
endmodule
| 6.64704 |
module alinhamentos (
doutalign
); // Este modulo é responsavel por gerar as tramas de controlo e alinhamento de trama
output wire [7:0] doutalign; //tramas para inserir no processamento
//Para testes estas variaveis c1, c2, c3, c4, e1 e e2 vão ter o papel de constantes fixadas a '0' lógico
reg [7:0] tramas;
clk_4Mbps clk ();
Contador4 cnt4 ();
initial begin
tramas = 8'h00;
end
assign doutalign = tramas;
always @(posedge clk.saida) begin
case (cnt4.dout4)
4'h00: tramas = 8'h1b;
4'h02: tramas = 8'h1b;
4'h04: tramas = 8'h1b;
4'h06: tramas = 8'h1b;
4'h08: tramas = 8'h1b;
4'h0a: tramas = 8'h1b;
4'h0c: tramas = 8'h1b;
4'h0e: tramas = 8'h1b;
4'h01: tramas = 8'h5f;
4'h03: tramas = 8'h5f;
4'h07: tramas = 8'h5f;
4'h0d: tramas = 8'h5f;
4'h0f: tramas = 8'h5f;
4'h05: tramas = 8'hdf;
4'h09: tramas = 8'hdf;
4'h0b: tramas = 8'hdf;
default: tramas = tramas;
endcase
end
endmodule
| 7.935066 |
module AliniereMantise (
mantise,
mantise_out,
semn
);
input wire [27:0] mantise;
output reg [21:0] mantise_out;
output reg semn;
//output reg op;
reg [5:0] valoare;
reg [10:0] mantisa1, mantisa2;
reg semn1, semn2;
always @(mantise) begin
valoare = mantise[27:22];
mantisa1 = mantise[21:11];
mantisa2 = mantise[10:0];
semn1 = mantisa1[10];
semn2 = mantisa2[10];
mantisa1[10] = 1'b1;
mantisa2[10] = 1'b1;
semn = semn1 ^ semn2;
if (valoare[5] == 1'b1) // exponent1 > exponent2
begin
mantisa2 = mantisa2 >> valoare[4:0];
mantise_out = {mantisa1, mantisa2};
//semn = semn1;
end
else if (valoare[5] == 1'b0) // exponent2 > exponent1
begin
mantisa1 = mantisa1 >> valoare[4:0];
mantise_out = {mantisa2, mantisa1};
//semn = semn2;
end
end
endmodule
| 7.776647 |
module test;
wire Co;
wire [3:0] S;
reg [3:0] A;
reg [3:0] B;
reg Ci;
CLA4 dut (
.Co(Co),
.S (S),
.A (A),
.B (B),
.Ci(Ci)
);
initial begin
#0 A = 4'b1010;
#0 B = 4'b0010;
#0 Ci = 1'b0;
#40 A = 4'b1010;
#40 B = 4'b0111;
#80 A = 4'b1111;
#80 B = 4'b1111;
#160 $finish;
end
endmodule
| 6.964054 |
module CLA4 (
Co,
S,
A,
B,
Ci
);
output Co;
output [3:0] S;
input [3:0] A;
input [3:0] B;
input Ci; // 0
wire [3:0] Carries;
wire [3:0] gene, prop; // Used in CLA
wire [3:0] Xprop, Yprop; // To Find Prop
// For Carry Circuits
wire C1;
wire [1:0] C2;
wire [2:0] C3;
wire [3:0] C4;
// Useless Store
wire [3:0] junk;
FA a (
S[0],
junk[0],
A[0],
B[0],
Ci
);
FA b (
S[1],
junk[1],
A[1],
B[1],
Carries[0]
);
FA c (
S[2],
junk[2],
A[2],
B[2],
Carries[1]
);
FA d (
S[3],
junk[3],
A[3],
B[3],
Carries[3]
);
// This Section Could be Replaced by Half Adders but It Helped to See the Variables
// Generate
and #2(gene[0], A[0], B[0]);
and #2(gene[1], A[1], B[1]);
and #2(gene[2], A[2], B[2]);
and #2(gene[3], A[3], B[3]);
// Propogate Basically a XOR gate
nand #2(Xprop[0], A[0], B[0]);
or #2(Yprop[0], A[0], B[0]);
and #2(prop[0], Xprop[0], Yprop[0]);
nand #2(Xprop[1], A[1], B[1]);
or #2(Yprop[1], A[1], B[1]);
and #2(prop[1], Xprop[1], Yprop[1]);
nand #2(Xprop[2], A[2], B[2]);
or #2(Yprop[2], A[2], B[2]);
and #2(prop[2], Xprop[2], Yprop[2]);
nand #2(Xprop[3], A[3], B[3]);
or #2(Yprop[3], A[3], B[3]);
and #2(prop[3], Xprop[3], Yprop[3]);
// CLA Unit
// C1
and #2(C1, prop[0], Ci);
or #2(Carries[0], C1, gene[0]);
// C2
and #2(C2[0], prop[1], prop[0], Ci);
and #2(C2[1], prop[1], gene[0]);
or #2(Carries[1], gene[1], C2[1], C2[0]);
// C3
and #2(C3[0], prop[2], prop[1], prop[0], Ci);
and #2(C3[1], prop[2], prop[1], gene[0]);
and #2(C3[2], prop[2], gene[1]);
or #2(Carries[2], gene[2], C3[2], C3[1], C3[0]);
// C4
and #2(C4[0], prop[3], prop[2], prop[1], prop[0], Ci);
and #2(C4[1], prop[3], prop[2], prop[1], gene[0]);
and #2(C4[2], prop[3], prop[2], gene[1]);
and #2(C4[3], prop[3], gene[2]);
or #2(Carries[3], gene[3], C4[3], C4[2], C4[1], C4[0]);
assign Co = Carries[3];
endmodule
| 8.659323 |
module FA (
Fsum,
Cout,
U,
V,
Cin
);
output Cout;
output Fsum;
input Cin;
input U;
input V;
wire X, Y, Z;
HA a (
X,
Y,
U,
V
);
HA b (
Fsum,
Z,
Cin,
X
);
or #1 (Cout, Z, Y);
endmodule
| 7.804384 |
module HA (
Sum,
Carry,
P,
Q
);
output Sum, Carry;
input P, Q;
and #4(Carry, P, Q);
xor #5(Sum, P, Q);
endmodule
| 7.201569 |
module allAdd (
input clk,
input hit,
input rst,
output [11:0] num
);
// 控制进位
wire carry_1;
wire carry_2;
wire carry_3;
// wire carry_4;
// wire carry_5;
// wire carry_6;
// wire carry_7;
// wire carry_8;
// rst 信号也相当于进位信号—?都是使得当前清?
assign carry_1 = ~(num[1] & num[3] | rst);
assign carry_2 = ~(num[5] & num[7] & ~carry_1 | rst);
assign carry_3 = ~(num[9] & num[11] & ~carry_2 | rst);
// assign carry_4 = (num[12]&num[15]) & carry_3;
// assign carry_5 = (num[16]&num[19]) & carry_4;
// assign carry_6 = (num[20]&num[23]) & carry_5;
// assign carry_7 = (num[24]&num[27]) & carry_6;
// assign carry_8 = (num[28]&num[31]) & carry_7;
// 控制使能
wire hit_2;
wire hit_3;
// wire hit_4;
// wire hit_5;
// wire hit_6;
// wire hit_7;
// wire hit_8;
assign hit_2 = (num[0] & num[3]) & hit;
assign hit_3 = (num[4] & num[7]) & hit_2;
// assign hit_4 = (num[8]&num[11]) & carry_3;
// assign hit_5 = (num[12]&num[15]) & carry_4;
// assign hit_6 = (num[16]&num[19]) & carry_5;
// assign hit_7 = (num[20]&num[23]) & carry_6;
// assign hit_8 = (num[24]&num[27]) & carry_7;
singleAdd sa1 (
.clk(clk),
.hit(hit),
.carry(carry_1),
.Q(num[3:0])
);
singleAdd sa2 (
.clk(clk),
.hit(hit_2),
.carry(carry_2),
.Q(num[7:4])
);
singleAdd sa3 (
.clk(clk),
.hit(hit_3),
.carry(carry_3),
.Q(num[11:8])
);
// singleAdd sa4(.clk(clk),.rst(rst),.hit(hit_4),.CR(carry_4),.Q(num[15:12]));
// singleAdd sa5(.clk(clk),.rst(rst),.hit(hit_5),.CR(carry_5),.Q(num[19:16]));
// singleAdd sa6(.clk(clk),.rst(rst),.hit(hit_6),.CR(carry_6),.Q(num[23:20]));
// singleAdd sa7(.clk(clk),.rst(rst),.hit(hit_7),.CR(carry_7),.Q(num[27:24]));
// singleAdd sa8(.clk(clk),.rst(rst),.hit(hit_8),.CR(carry_8),.Q(num[31:28]));
endmodule
| 7.283906 |
module ALU (
F,
data,
B
);
output [15:0] F; // Output
input [19:0] data; // A and OP Derive from Data
input [15:0] B; // Input 2
wire [ 3:0] OP;
wire [15:0] A; // Input 1
control unit (
A,
OP,
data
);
hardware toplevel (
F,
A,
B,
OP
);
endmodule
| 7.043664 |
module control (
A,
OP,
data
);
output [3:0] OP;
output [15:0] A;
input [19:0] data;
assign OP[3:0] = data[19:16];
assign A = data[15:0];
endmodule
| 7.715617 |
module hardware (
F,
A,
B,
OP
);
output [15:0] F; // Output
input [15:0] A; // Input 1
input [15:0] B; // Input 2
input [3:0] OP;
wire [15:0] shift_out;
wire [15:0] rca_out;
wire [15:0] and_out;
wire [15:0] or_out;
wire [15:0] multi_out;
wire [15:0] m421_out;
wire [15:0] m221_out;
logic_shift shifter (
shift_out,
A,
OP[3]
);
RCA rca (
rca_out,
A,
B,
OP[3]
);
AND annd (
and_out,
A,
B,
OP[3]
);
OR oor (
or_out,
A,
B,
OP[3]
);
Multiplier multi (
multi_out,
A[7:0],
B[7:0]
);
Mux4to1 m421 (
m421_out,
and_out,
or_out,
multi_out,
"0",
OP[2:1]
);
Mux2to1 m221a (
m221_out,
shift_out,
rca_out,
OP[1]
);
Mux2to1 m221b (
F,
m221_out,
m421_out,
OP[0]
);
endmodule
| 7.166936 |
module fulladder (
r,
cout,
p,
q,
cin
);
input p;
input q;
input cin;
output cout;
output r;
wire x, y, z;
xor #2(x, p, q);
xor #2(r, x, cin);
and #2(y, x, cin);
and #2(z, p, q);
or #2(cout, y, z);
endmodule
| 7.454465 |
module Mux2to1 (
out,
a,
b,
sel
);
output [15:0] out;
input [15:0] a;
input [15:0] b;
input sel;
wire [15:0] selextend;
wire [15:0] x;
wire [15:0] y;
wire [15:0] z;
assign selextend = {16{sel}};
nand #2(x[0], b[0], selextend[0]);
nand #2(x[1], b[1], selextend[1]);
nand #2(x[2], b[2], selextend[2]);
nand #2(x[3], b[3], selextend[3]);
nand #2(x[4], b[4], selextend[4]);
nand #2(x[5], b[5], selextend[5]);
nand #2(x[6], b[6], selextend[6]);
nand #2(x[7], b[7], selextend[7]);
nand #2(x[8], b[8], selextend[8]);
nand #2(x[9], b[9], selextend[9]);
nand #2(x[10], b[10], selextend[10]);
nand #2(x[11], b[11], selextend[11]);
nand #2(x[12], b[12], selextend[12]);
nand #2(x[13], b[13], selextend[13]);
nand #2(x[14], b[14], selextend[14]);
nand #2(x[15], b[15], selextend[15]);
not #2(z[0], selextend[0]);
not #2(z[1], selextend[1]);
not #2(z[2], selextend[2]);
not #2(z[3], selextend[3]);
not #2(z[4], selextend[4]);
not #2(z[5], selextend[5]);
not #2(z[6], selextend[6]);
not #2(z[7], selextend[7]);
not #2(z[8], selextend[8]);
not #2(z[9], selextend[9]);
not #2(z[10], selextend[10]);
not #2(z[11], selextend[11]);
not #2(z[12], selextend[12]);
not #2(z[13], selextend[13]);
not #2(z[14], selextend[14]);
not #2(z[15], selextend[15]);
nand #2(y[0], a[0], z[0]);
nand #2(y[1], a[1], z[1]);
nand #2(y[2], a[2], z[2]);
nand #2(y[3], a[3], z[3]);
nand #2(y[4], a[4], z[4]);
nand #2(y[5], a[5], z[5]);
nand #2(y[6], a[6], z[6]);
nand #2(y[7], a[7], z[7]);
nand #2(y[8], a[8], z[8]);
nand #2(y[9], a[9], z[9]);
nand #2(y[10], a[10], z[10]);
nand #2(y[11], a[11], z[11]);
nand #2(y[12], a[12], z[12]);
nand #2(y[13], a[13], z[13]);
nand #2(y[14], a[14], z[14]);
nand #2(y[15], a[15], z[15]);
nand #2(out[0], x[0], y[0]);
nand #2(out[1], x[1], y[1]);
nand #2(out[2], x[2], y[2]);
nand #2(out[3], x[3], y[3]);
nand #2(out[4], x[4], y[4]);
nand #2(out[5], x[5], y[5]);
nand #2(out[6], x[6], y[6]);
nand #2(out[7], x[7], y[7]);
nand #2(out[8], x[8], y[8]);
nand #2(out[9], x[9], y[9]);
nand #2(out[10], x[10], y[10]);
nand #2(out[11], x[11], y[11]);
nand #2(out[12], x[12], y[12]);
nand #2(out[13], x[13], y[13]);
nand #2(out[14], x[14], y[14]);
nand #2(out[15], x[15], y[15]);
endmodule
| 6.739082 |
module Allign2 (
input [1:0] idle_Allign,
input [35:0] cout_Allign,
input [35:0] zout_Allign,
input [31:0] sout_Allign,
input [1:0] modeout_Allign,
input operationout_Allign,
input NatLogFlagout_Allign,
input [7:0] difference_Allign,
input [7:0] InsTag_Allign,
input clock,
output reg [1:0] idle_Allign2,
output reg [35:0] cout_Allign2,
output reg [35:0] zout_Allign2,
output reg [31:0] sout_Allign2,
output reg [1:0] modeout_Allign2,
output reg operationout_Allign2,
output reg NatLogFlagout_Allign2,
output reg [7:0] InsTag_Allign2
);
parameter mode_circular = 2'b01, mode_linear = 2'b00, mode_hyperbolic = 2'b11;
parameter no_idle = 2'b00, allign_idle = 2'b01, put_idle = 2'b10;
wire z_sign;
wire [7:0] z_exponent;
wire [26:0] z_mantissa;
wire c_sign;
wire [7:0] c_exponent;
wire [26:0] c_mantissa;
assign z_sign = zout_Allign[35];
assign z_exponent = zout_Allign[34:27] - 127;
assign z_mantissa = {zout_Allign[26:0]};
assign c_sign = cout_Allign[35];
assign c_exponent = cout_Allign[34:27] - 127;
assign c_mantissa = {cout_Allign[26:0]};
always @(posedge clock) begin
InsTag_Allign2 <= InsTag_Allign;
idle_Allign2 <= idle_Allign;
modeout_Allign2 <= modeout_Allign;
operationout_Allign2 <= operationout_Allign;
sout_Allign2 <= sout_Allign;
if (idle_Allign != put_idle) begin
if ($signed(c_exponent) > $signed(z_exponent)) begin
zout_Allign2[35] <= zout_Allign[35];
zout_Allign2[34:27] <= z_exponent + difference_Allign + 127;
zout_Allign2[26:0] <= z_mantissa >> difference_Allign;
zout_Allign2[0] <= z_mantissa[0] | z_mantissa[1];
cout_Allign2 <= cout_Allign;
end else if ($signed(c_exponent) <= $signed(z_exponent)) begin
cout_Allign2[35] <= cout_Allign[35];
cout_Allign2[34:27] <= c_exponent + difference_Allign + 127;
cout_Allign2[26:0] <= c_mantissa >> difference_Allign;
cout_Allign2[0] <= c_mantissa[0] | c_mantissa[1];
zout_Allign2 <= zout_Allign;
end
end else begin
zout_Allign2 <= zout_Allign;
cout_Allign2 <= cout_Allign;
end
end
endmodule
| 6.980245 |
module AllignAdder (
input idle_Special,
input [35:0] cout_Special,
input [35:0] zout_Special,
input [31:0] sout_Special,
input [7:0] difference_Special,
input clock,
output reg idle_Allign,
output reg [35:0] cout_Allign,
output reg [35:0] zout_Allign,
output reg [31:0] sout_Allign
);
parameter no_idle = 1'b01, put_idle = 1'b1;
wire z_sign;
wire [7:0] z_exponent;
wire [26:0] z_mantissa;
wire c_sign;
wire [7:0] c_exponent;
wire [26:0] c_mantissa;
assign z_sign = zout_Special[35];
assign z_exponent = zout_Special[34:27] - 127;
assign z_mantissa = {zout_Special[26:0]};
assign c_sign = cout_Special[35];
assign c_exponent = cout_Special[34:27] - 127;
assign c_mantissa = {cout_Special[26:0]};
always @(posedge clock) begin
idle_Allign <= idle_Special;
sout_Allign <= sout_Special;
if (idle_Special != put_idle) begin
if ($signed(c_exponent) > $signed(z_exponent)) begin
zout_Allign[35] <= zout_Special[35];
zout_Allign[34:27] <= z_exponent + difference_Special + 127;
zout_Allign[26:0] <= z_mantissa >> difference_Special;
zout_Allign[0] <= z_mantissa[0] | z_mantissa[1];
cout_Allign <= cout_Special;
end else if ($signed(c_exponent) <= $signed(z_exponent)) begin
cout_Allign[35] <= cout_Special[35];
cout_Allign[34:27] <= c_exponent + difference_Special + 127;
cout_Allign[26:0] <= c_mantissa >> difference_Special;
cout_Allign[0] <= c_mantissa[0] | c_mantissa[1];
zout_Allign <= zout_Special;
end
end else begin
zout_Allign <= zout_Special;
cout_Allign <= cout_Special;
end
end
endmodule
| 7.400136 |
module allocate (
input wire clk,
input wire rst,
input wire [31:0] CPU_addr,
input wire [31:0] main_mem_dout,
output reg [12:0] main_mem_addr,
output reg [ 8:0] cache_data_addr,
output wire [31:0] cache_data_din,
output reg cache_data_we,
input wire start,
output reg done
);
reg [1:0] current_state, next_state;
reg [2:0] counter;
wire [5:0] CPU_addr_index;
assign CPU_addr_index = CPU_addr[10:5];
localparam IDLE = 2'd0, TRANSFER = 2'd1, DONE = 2'd2;
assign cache_data_din = main_mem_dout;
/* first stage */
always @(posedge clk) begin
if (rst) current_state <= IDLE;
else current_state <= next_state;
end
/* second stage */
always @(*) begin
next_state = IDLE;
case (current_state)
IDLE: begin
if (start) next_state = TRANSFER;
else next_state = IDLE;
end
TRANSFER: begin
if (counter == 3'b111) next_state = DONE;
else next_state = TRANSFER;
end
DONE: next_state = IDLE;
default: next_state = IDLE;
endcase
end
/* third stage */
always @(posedge clk) begin
if (rst) begin
counter <= 0;
done <= 0;
cache_data_addr <= 0;
cache_data_we <= 0;
main_mem_addr <= 0;
end else begin
case (current_state)
IDLE: begin
counter <= 0;
done <= 0;
cache_data_addr <= 0;
cache_data_we <= 0;
main_mem_addr <= (CPU_addr[31:5] << 3);
end
TRANSFER: begin
counter <= counter + 1;
main_mem_addr <= (CPU_addr[31:5] << 3) + counter + 1;
cache_data_we <= 1;
cache_data_addr <= (CPU_addr_index << 3) + counter;
end
DONE: begin
cache_data_we <= 0;
done <= 1'b1;
end
endcase
end
end
endmodule
| 7.379282 |
module alloc_three #(
parameter CHANNEL_ID = `LOCAL, //input port
parameter ROUTER_ID_X = 0,
parameter ROUTER_ID_Y = 0
) (
input wire clk,
input wire rstn,
input wire [`DATA_WIDTH-1:0] data_i,
input wire valid_i,
output wire ready_o,
//left out for LOCAL in
//up out for INTER in
output wire A_valid_o,
input wire A_ready_i,
output wire [`DATA_WIDTH-1:0] A_data_o,
//right out for LOCAL in
//down out for INTER in
output wire B_valid_o,
input wire B_ready_i,
output wire [`DATA_WIDTH-1:0] B_data_o,
//inter out for LOCAL in
//local out for INTER in
output wire C_valid_o,
input wire C_ready_i,
output wire [`DATA_WIDTH-1:0] C_data_o
);
wire fifo_full, fifo_wr;
wire fifo_valid, fifo_ready;
wire [`DATA_WIDTH-1:0] fifo_dout;
wire fire_A, fire_B, fire_C, any_fire;
assign fifo_wr = valid_i & (~fifo_full);
assign ready_o = ~fifo_full;
fifo_NoD_wrapper fifo (
.clk (clk),
.rstn (rstn),
.din (data_i),
.wr_en(fifo_wr),
.full (fifo_full),
.dout (fifo_dout),
.ready(fifo_ready),
.valid(fifo_valid)
);
wire [`RTID_H - `RTID_L : 0] data_rt_id;
wire [(`RTID_H-`RTID_L+1)/2-1:0] rt_id_x, rt_id_y;
assign rt_id_x = data_rt_id[`RTID_H-`RTID_L:(`RTID_H-`RTID_L+1)/2];
assign rt_id_y = data_rt_id[(`RTID_H-`RTID_L+1)/2-1:0];
//channel allocation
assign data_rt_id = fifo_dout[`RTID_H:`RTID_L];
wire dst_A, dst_B, dst_C;
generate
if (CHANNEL_ID == `LOCAL) begin : LOCAL
assign dst_A = (rt_id_y < ROUTER_ID_Y);
assign dst_B = (rt_id_y > ROUTER_ID_Y);
assign dst_C = (rt_id_y == ROUTER_ID_Y);
end else begin : INTER
assign dst_A = (rt_id_x < ROUTER_ID_X);
assign dst_B = (rt_id_x > ROUTER_ID_X);
assign dst_C = (rt_id_x == ROUTER_ID_X);
end
endgenerate
//state == 1 indicates there is a packet in flight
reg state;
wire nxt_state;
always @(posedge clk or negedge rstn) begin
if (~rstn) state <= 0;
else state <= nxt_state;
end
wire [1:0] fifo_dout_typebits = fifo_dout[`DATA_WIDTH-1:`DATA_WIDTH-2];
assign nxt_state = (state == 0) & any_fire ? 1 : (
(state == 1) & any_fire & (fifo_dout_typebits == `TAIL) ? 0 : state);
//info registering
reg dst_A_reg, dst_B_reg, dst_C_reg;
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
dst_A_reg <= 0;
dst_B_reg <= 0;
dst_C_reg <= 0;
end else if ((~state) & any_fire) begin
dst_A_reg <= dst_A;
dst_B_reg <= dst_B;
dst_C_reg <= dst_C;
end
end
//generating valid_out for each channel
assign A_valid_o = fifo_valid & (state ? dst_A_reg : dst_A);
assign B_valid_o = fifo_valid & (state ? dst_B_reg : dst_B);
assign C_valid_o = fifo_valid & (state ? dst_C_reg : dst_C);
//fire == 1 indicates a flit finished transportation
assign fifo_ready = A_ready_i & (state ? dst_A_reg : dst_A) |
B_ready_i & (state ? dst_B_reg : dst_B) |
C_ready_i & (state ? dst_C_reg : dst_C);
assign fire_A = A_valid_o & A_ready_i;
assign fire_B = B_valid_o & B_ready_i;
assign fire_C = C_valid_o & C_ready_i;
assign any_fire = fire_A | fire_B | fire_C;
assign A_data_o = fifo_dout;
assign B_data_o = fifo_dout;
assign C_data_o = fifo_dout;
endmodule
| 7.241093 |
module alloc_two #(
parameter CHANNEL_ID = `LEFT, //input port
parameter ROUTER_ID_X = 0,
parameter ROUTER_ID_Y = 0
) (
input wire clk,
input wire rstn,
input wire [`DATA_WIDTH-1:0] data_i,
input wire valid_i,
output wire ready_o,
//right out for LEFT in
//left out for RIGHT in
//down out for UP in
//up out for DOWN in
output wire A_valid_o,
input wire A_ready_i,
output wire [`DATA_WIDTH-1:0] A_data_o,
//inter out for LEFT in
//inter out for RIGHT in
//local out for UP in
//local out for DOWN in
output wire B_valid_o,
input wire B_ready_i,
output wire [`DATA_WIDTH-1:0] B_data_o
);
wire fifo_valid, fifo_full, fifo_wr, fifo_ready;
wire [`DATA_WIDTH-1:0] fifo_dout;
wire fire_A, fire_B, any_fire;
assign fifo_wr = valid_i & (~fifo_full);
assign ready_o = ~fifo_full;
fifo_NoD_wrapper fifo (
.clk (clk),
.rstn (rstn),
.din (data_i),
.wr_en(fifo_wr),
.full (fifo_full),
.dout (fifo_dout),
.ready(fifo_ready),
.valid(fifo_valid)
);
//channel allocation
wire [`RTID_H - `RTID_L : 0] data_rt_id;
assign data_rt_id = fifo_dout[`RTID_H:`RTID_L];
wire dst_A, dst_B;
wire [(`RTID_H-`RTID_L+1)/2-1:0] rt_id_x, rt_id_y;
assign rt_id_x = data_rt_id[`RTID_H-`RTID_L:(`RTID_H-`RTID_L+1)/2];
assign rt_id_y = data_rt_id[(`RTID_H-`RTID_L+1)/2-1:0];
generate
if (CHANNEL_ID == `LEFT) begin : LEFT
assign dst_A = rt_id_y > ROUTER_ID_Y;
assign dst_B = rt_id_y == ROUTER_ID_Y;
end else if (CHANNEL_ID == `RIGHT) begin : RIGHT
assign dst_A = rt_id_y < ROUTER_ID_Y;
assign dst_B = rt_id_y == ROUTER_ID_Y;
end else if (CHANNEL_ID == `UP) begin : UP
assign dst_A = rt_id_x > ROUTER_ID_X;
assign dst_B = rt_id_x == ROUTER_ID_X;
end else begin : DOWN
assign dst_A = rt_id_x < ROUTER_ID_X;
assign dst_B = rt_id_x == ROUTER_ID_X;
end
endgenerate
//state == 1 indicates there is a packet in flight
reg state;
wire nxt_state;
always @(posedge clk or negedge rstn) begin
if (~rstn) state <= 0;
else state <= nxt_state;
end
wire [1:0] fifo_dout_typebits = fifo_dout[`DATA_WIDTH-1:`DATA_WIDTH-2];
assign nxt_state = (state == 0) & any_fire ? 1 : (
(state == 1) & any_fire & (fifo_dout_typebits == `TAIL) ? 0 : state);
//info registering
reg dst_A_reg, dst_B_reg;
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
dst_A_reg <= 0;
dst_B_reg <= 0;
end else if ((~state) & any_fire) begin
dst_A_reg <= dst_A;
dst_B_reg <= dst_B;
end
end
//generating valid_out for each channel
assign A_valid_o = fifo_valid & (state ? dst_A_reg : dst_A);
assign B_valid_o = fifo_valid & (state ? dst_B_reg : dst_B);
//fire == 1 indicates a flit finished transportation
assign fifo_ready = A_ready_i & (state ? dst_A_reg : dst_A) |
B_ready_i & (state ? dst_B_reg : dst_B);
assign fire_A = A_valid_o & A_ready_i;
assign fire_B = B_valid_o & B_ready_i;
assign any_fire = fire_A | fire_B;
assign A_data_o = fifo_dout;
assign B_data_o = fifo_dout;
endmodule
| 6.608122 |
module produces an actual clock
// with 50% duty cycle :)
// Use it as you would use the default clck.
// Examples for 50 MHz --> 1 Hz
module frequency_divider(clk,rst,clk_out); // debug code: , counter);
input clk,rst;
// clk is the original clk
output reg clk_out; // desired clk
// factor = original frequency / (2 x desired frequency) - 1
parameter factor = 28'd24999999;
// keep factor bitsize divisible by 4, just in case you want hex
// bitsize = n + n mod 4 ....n + remainder of n/4
parameter n = 25; // #of bits required to hold factor
// be exact here, no less and no more
reg [n-1:0]counter;
// output reg [n-1:0]counter; // debug code
always @(posedge clk)
begin
if(rst) begin // synchronous reset
counter <= 28'd0; // see comment at factor
// counter <= 12'd24990; // debug code
clk_out <= 1'b0;
end
else if(counter==factor)begin
counter <= 28'd0; // see comment at factor
clk_out <= ~clk_out;
end
// // // //
else
counter <= counter+1;
end
endmodule
| 7.056371 |
module's duty cycle varies.
// Always use negedge of this clock
// otherwise your clock will mess up
// Examples for 50 MHz --> 1 Hz
module frequency_divider_special(clk,rst,clk_out); // debug code: , counter);
input clk,rst;
// clk is the original clk
output clk_out; // desired clk
// factor = original frequency / desired frequency -1
parameter factor = 28'd49999999;
// keep factor bitsize divisible by 4, just in case you want hex
// bitsize = n + n mod 4 ....n + remainder of n/4
parameter n = 26; // #of bits required to hold factor
// be exact here, no less and no more
reg [n-1:0]counter;
// output reg [n-1:0]counter; // debug code
always @(posedge clk)
begin
if(rst) // synchronous reset
counter <= 28'd0; // see comment at factor
// counter <= 28'd49980; // debug code
else if(counter==factor)
counter <= 28'd0;
// // // //
else
counter <= counter+1;
end
assign clk_out =counter[n-1]; // relays most significant (actual)
// bit as the new clock [hacks ]
endmodule
| 7.386754 |
module all_adder_OR1_0_1 (
A,
B,
F
);
input wire A;
input wire B;
output wire F;
OR1 inst (
.A(A),
.B(B),
.F(F)
);
endmodule
| 6.823786 |
module all_adder_OR1_0_1 (
A,
B,
F
);
input A;
input B;
output F;
wire A;
wire B;
wire F;
LUT2 #(
.INIT(4'hE)
) F_INST_0 (
.I0(A),
.I1(B),
.O (F)
);
endmodule
| 6.823786 |
module all_adder_wrapper (
A,
B,
C,
Ci,
S
);
input A;
input B;
output C;
input Ci;
output S;
wire A;
wire B;
wire C;
wire Ci;
wire S;
all_adder all_adder_i (
.A (A),
.B (B),
.C (C),
.Ci(Ci),
.S (S)
);
endmodule
| 7.266315 |
module all_arithm (
input clk,
input [31:0] in_s,
output [31:0] sqrt
);
wire [31:0] real_sqrt;
wire [31:0] rough_sqrt;
wire incorrect;
reg [31:0] in_s_shift[2:0];
reg [31:0] rough_shift[1:0];
wire [23:0] out_D_mantissa;
wire [23:0] out_x_mantissa;
wire [7:0] out_exponent;
wire sign;
wire [31:0] recip;
rough_estimate sqrt_estimate (
.clk(clk),
.in(in_s),
.out(rough_sqrt),
.incorrect(incorrect)
);
recip_first_stage first_recip (
.clk(clk),
.in(rough_sqrt),
.out_D_mantissa(out_D_mantissa),
.out_x_mantissa(out_x_mantissa),
.out_exponent(out_exponent),
.sign(sign)
);
recip_second_stage second_recip (
.clk(clk),
.sign(sign),
.in_D_mantissa(out_D_mantissa),
.in_x_mantissa(out_x_mantissa),
.in_exponent(out_exponent),
.recip(recip)
);
newthon_vavilon_s_x vavilon (
.clk(clk),
.recip(recip),
.in_s(in_s_shift[2][31:0]),
.rough_x(rough_shift[1][31:0]),
.sqrt(real_sqrt)
);
always @(posedge clk) begin
in_s_shift[0] <= in_s;
in_s_shift[1] <= in_s_shift[0];
in_s_shift[2] <= in_s_shift[1];
rough_shift[0] <= rough_sqrt;
rough_shift[1] <= rough_shift[0];
end
assign sqrt = real_sqrt;
endmodule
| 8.460002 |
module all_arithm_testbench;
reg clk;
reg [31:0] in_s;
wire [31:0] sqrt;
all_arithm dut (
.clk (clk),
.in_s(in_s),
.sqrt(sqrt)
);
always #5 clk = ~clk;
initial begin
$dumpfile("all_arithm_testbench.vcd");
$dumpvars;
{clk, in_s} = 0;
#10 in_s = 32'h42800000; // 64
#10 in_s = 32'h57F8A43C; // 546768529915904
#10 in_s = 32'h2EC47772; // 8.934266e-11
#60 $stop;
$finish;
end
endmodule
| 7.030615 |
module all_bgr_top #(
parameter BITS = 32
) (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
input wire [31:0] porst, // start up signal for 32 BGR macros
input wire [ 4:0] s_vbgr, // 5 select lines for Vbgr
input wire [ 4:0] s_va, // 5 select lines for Va
input wire [ 4:0] s_vb, // 5 select lines for Vb
input wire decoder_en_vbgr, // decoder enable pin for Vbgr
input wire decoder_en_va, // decoder enable pin for Va
input wire decoder_en_vb, // decoder enable pin for Vb
input wire switch_en_vbgr, // switch enable pin for Vbgr
input wire switch_en_va, // switch enable pin for Va
input wire switch_en_vb, // switch enable pin for Vb
output wire out_vbgr, // Vout for vbgr
output wire out_va, // Vout for va
output wire out_vb // Vout for vb
);
/*--------------------------------------*/
/* all_bgr_top is initiated here */
/*--------------------------------------*/
/* inverters */
wire switch_en_b_vbgr, switch_en_b_va, switch_en_b_vb;
// inv inv_vbgr (
// .a(switch_en_vbgr),
// .b(switch_en_b_vbgr)
// );
assign switch_en_b_vbgr = ~switch_en_vbgr;
assign switch_en_b_va = ~switch_en_va;
assign switch_en_b_vb = ~switch_en_vb;
// inv inv_va (
// .a(switch_en_va),
// .b(switch_en_b_va)
// );
// inv inv_vb (
// .a(switch_en_vb),
// .b(switch_en_b_vb)
// );
/* bgr */
wire [31:0] vbgr;
wire [31:0] va;
wire [31:0] vb;
wire bgr0_out;
bgr_0 bgr_inst_0 (
`ifdef USE_POWER_PINS
.VDD(vccd1),
.VSS(vssd1),
`endif
.porst(porst[0]),
.va(va[0]),
.vb(vb[0]),
.vbg(bgr0_out)
);
assign vbgr[0] = bgr0_out;
/* decoder */
wire [31:0] c_vbgr; //Vbgr 32-to-1 mux control signal
decoder5x32 decoder_vbgr (
`ifdef USE_POWER_PINS
.VDD(vccd1),
.VSS(vssd1),
`endif
.a (s_vbgr),
.en (decoder_en_vbgr),
.y (c_vbgr)
);
/* switch */
switch switch_vbgr (
`ifdef USE_POWER_PINS
.VDD(vccd1),
.VSS(vssd1),
`endif
.s_en(switch_en_vbgr),
.s_en_b(switch_en_b_vbgr),
.en_b(c_vbgr),
.in(vbgr[31:0]),
.out(out_vbgr)
);
endmodule
| 7.789044 |
module inv (
a,
b
);
input wire a;
output wire b;
assign b = ~a;
endmodule
| 6.790398 |
module all_blocks (
input clk
);
tri [4:0] data_bus;
wire [2:0] grant_bus;
wire [2:0] out_requests[3:0];
wire [2:0] slaves_data [3:0];
master #(4) master_4 (
.clk(clk),
.grant(grant_bus),
.in_request(3'b000),
.data(data_bus),
.out_request(out_requests[0])
);
master #(3) master_3 (
.clk(clk),
.grant(grant_bus),
.in_request(out_requests[0]),
.data(data_bus),
.out_request(out_requests[1])
);
master #(2) master_2 (
.clk(clk),
.grant(grant_bus),
.in_request(out_requests[1]),
.data(data_bus),
.out_request(out_requests[2])
);
master #(1) master_1 (
.clk(clk),
.grant(grant_bus),
.in_request(out_requests[2]),
.data(data_bus),
.out_request(out_requests[3])
);
arbiter arbiter (
.clk(clk),
.in_request(out_requests[3]),
.grant(grant_bus)
);
generate
genvar i;
for (i = 0; i < 4; i = i + 1) begin : slave_generate
slave #(i) slave_ (
.data(data_bus),
.slave_data(slaves_data[i])
);
end
endgenerate
endmodule
| 7.635112 |
module all_blocks_tb;
reg clk;
all_blocks dut (.clk(clk));
always #5 clk = ~clk;
initial begin
$dumpfile("all_blocks_tb.vcd");
$dumpvars;
clk = 0;
#200 $stop;
$finish;
end
endmodule
| 6.681443 |
module all_blocks_testbench;
parameter ADDRESS_WIDTH = 5;
parameter DATA_WIDTH = 8;
parameter BUFFER_LENGTH = 5;
parameter DATA_DELAY = 3;
reg clk;
reg start;
reg [ADDRESS_WIDTH-1:0] address;
reg rom_nram;
wire [DATA_WIDTH-1:0] general_data_bus;
integer i;
all_blocks #(
.ADDRESS_WIDTH(ADDRESS_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.DATA_DELAY(DATA_DELAY),
.BUFFER_LENGTH(BUFFER_LENGTH)
) boje (
.clk(clk),
.address(address),
.start(start),
.out_data(general_data_bus),
.rom_nram(rom_nram)
);
always #5 clk = ~clk;
integer fd_mem, fd_monitor;
initial begin : main
fd_mem = $fopen("all_blocks_contains.txt", "w");
fd_monitor = $fopen("all_blocks_monitor.txt", "w");
$dumpfile("all_blocks_testbench.vcd");
$dumpvars;
$fwrite(fd_mem, "ROM initialization:\n");
for (i = 0; i < 2 ** ADDRESS_WIDTH; i = i + 1) begin
$fwrite(fd_mem, "[%d]", boje.ROM_1.memory[i]);
if ((i + 1) % 8 == 0) begin
$fwrite(fd_mem, "\n");
end
end
$fwrite(fd_mem, "RAM initialization:\n");
for (i = 0; i < 2 ** ADDRESS_WIDTH; i = i + 1) begin
$fwrite(fd_mem, "[%d]", boje.RAM_1.memory[i]);
if ((i + 1) % 8 == 0) begin
$fwrite(fd_mem, "\n");
end
end
{clk, start, address, rom_nram} = 0;
//ROM TO RAM START
#33 start = 1;
address = 0;
rom_nram = 1;
#5 start = 0;
#10 address = 16;
#200 $fwrite(fd_mem, "\nRAM first time:\n");
for (i = 0; i < 2 ** ADDRESS_WIDTH; i = i + 1) begin
$fwrite(fd_mem, "[%d]", boje.RAM_1.memory[i]);
if ((i + 1) % 8 == 0) begin
$fwrite(fd_mem, "\n");
end
end
//ROM TO RAM ENDS
//RAM TO RAM START
#20 address = 17;
#3 start = 1;
rom_nram = 0;
#5 start = 0;
#10 address = 1;
#200 $fwrite(fd_mem, "\nRAM first time:\n");
for (i = 0; i < 2 ** ADDRESS_WIDTH; i = i + 1) begin
$fwrite(fd_mem, "[%d]", boje.RAM_1.memory[i]);
if ((i + 1) % 8 == 0) begin
$fwrite(fd_mem, "\n");
end
end
//RAM TO RAM ENDS
$fclose(fd_mem);
$fclose(fd_monitor);
#20 $stop;
$finish;
end
always @(posedge clk) begin
$fwrite(fd_monitor,
"Time:%3d, addres_counter=%d, state=%d, rw_counter=%d, active=%b, do_shift=%d, buf=",
$time, boje.address_counter, boje.current_state, boje.read_write_counter,
boje.active_memory_decode, boje.do_shift);
for (i = 0; i < BUFFER_LENGTH; i = i + 1) begin
$fwrite(fd_monitor, "%d", boje.buffer_1.shifter[i]);
end
$fwrite(fd_monitor, "\n");
end
endmodule
| 7.368027 |
module mux8 (
Muxout,
D1,
D2,
sel
);
input [7:0] D1;
input [7:0] D2;
input sel;
output reg [7:0] Muxout;
always @(D1 or D2 or sel) begin
if (sel == 1'b0) begin
#10 Muxout <= D1;
end else begin
#10 Muxout <= D2;
end
end
endmodule
| 6.605633 |
module cla8 (
Sum,
Cout,
F,
G,
Ci,
Operate
);
input [7:0] F;
input [7:0] G;
input Operate;
input Ci;
output reg [7:0] Sum;
output reg Cout;
reg [8:0] t;
reg [7:0] inv;
always @(posedge Operate) begin
if (Ci) begin
inv = -F;
t <= inv + G;
end else begin
t <= F + G;
end
#25 Sum <= t[7:0];
#25 Cout <= t[8];
end
endmodule
| 6.866219 |
module all_scoreboard_generator (
input V,
input [2:0] DR1,
DR2,
DR3,
input [1:0] DR1_SIZE,
DR2_SIZE,
DR3_SIZE,
input LD_GPR1,
LD_GPR2,
LD_GPR3,
input LD_SEG,
LD_CSEG,
input LD_MM,
output [23:0] GPR_SCOREBOARD,
output [ 7:0] SEG_SCOREBOARD,
output [ 7:0] MM_SCOREBOARD
);
wire [7:0] and0_out, and1_out, or0_out;
wire [7:0] and2_out;
wire [7:0] seg_scoreboard, cseg_scoreboard, mm_scoreboard;
reg_scoreboard_generator
u_reg_scoreboard_generator_seg (
DR1,
seg_scoreboard,
),
u_reg_scoreboard_generator_cseg (
3'b001,
cseg_scoreboard,
),
u_reg_scoreboard_generator_mm (
DR1,
mm_scoreboard,
);
and3$
and0[7:0] (
and0_out,
seg_scoreboard,
V,
LD_SEG
),
and1[7:0] (
and1_out,
cseg_scoreboard,
V,
LD_CSEG
);
or2$ or0[7:0] (
or0_out,
and0_out,
and1_out
);
assign SEG_SCOREBOARD = or0_out;
and3$ and2[7:0] (
and2_out,
mm_scoreboard,
V,
LD_MM
);
assign MM_SCOREBOARD = and2_out;
wire [2:0] dr1_bar, dr2_bar, dr3_bar;
wire [1:0] dr1_size_bar, dr2_size_bar, dr3_size_bar;
wire [23:0] gpr1_scoreboard, gpr2_scoreboard, gpr3_scoreboard;
inv1$
inv0[2:0] (
dr1_bar,
DR1
),
inv1[2:0] (
dr2_bar,
DR2
),
inv2[2:0] (
dr3_bar,
DR3
),
inv3[1:0] (
dr1_size_bar,
DR1_SIZE
),
inv4[1:0] (
dr2_size_bar,
DR2_SIZE
),
inv5[1:0] (
dr3_size_bar,
DR3_SIZE
);
gpr_scoreboard_generator
u_gpr_scoreboard_generator_gpr1 (
DR1,
dr1_bar,
DR1_SIZE,
dr1_size_bar,
gpr1_scoreboard
),
u_gpr_scoreboard_generator_gpr2 (
DR2,
dr2_bar,
DR2_SIZE,
dr2_size_bar,
gpr2_scoreboard
),
u_gpr_scoreboard_generator_gpr3 (
DR3,
dr3_bar,
DR3_SIZE,
dr3_size_bar,
gpr3_scoreboard
);
wire [23:0] and3_out, and4_out, and5_out;
wire [23:0] or1_out;
and3$
and3[23:0] (
and3_out,
gpr1_scoreboard,
V,
LD_GPR1
),
and4[23:0] (
and4_out,
gpr2_scoreboard,
V,
LD_GPR2
),
and5[23:0] (
and5_out,
gpr3_scoreboard,
V,
LD_GPR3
);
or3$ or1[23:0] (
or1_out,
and3_out,
and4_out,
and5_out
);
assign GPR_SCOREBOARD = or1_out;
endmodule
| 6.907789 |
module data_extract_v1 (
in,
rc,
regime,
exp,
mant
);
function [31:0] log2;
input reg [31:0] value;
begin
value = value - 1;
for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1;
end
endfunction
parameter N = 16;
parameter Bs = log2(N);
parameter es = 2;
input [N-1:0] in;
output rc;
output [Bs-1:0] regime;
output [es-1:0] exp;
output [N-es-1:0] mant;
wire [N-1:0] xin = in;
assign rc = xin[N-2];
wire [ N-1:0] xin_r = rc ? ~xin : xin;
wire [Bs-1:0] lod;
LOD_N #(
.N(N)
) xinst_k (
.in ({xin_r[N-2:0], rc ^ 1'b0}),
.out(lod)
);
assign regime = rc ? lod - 1 : lod;
wire [N-1:0] xin_shifted_res;
wire [N-1:0] xin_shifted_input;
assign xin_shifted_input = {xin[N-3:0], 2'b0};
DSR_left_N_S #(
.N(N),
.S(Bs)
) ls (
.a(xin_shifted_input),
.b(lod),
.c(xin_shifted_res)
);
assign exp = xin_shifted_res[N-1:N-es];
assign mant = xin_shifted_res[N-es-1:0];
endmodule
| 8.552482 |
module add_N (
a,
b,
c
);
parameter N = 10;
input [N-1:0] a, b;
output [N:0] c;
wire [N:0] ain = {1'b0, a};
wire [N:0] bin = {1'b0, b};
add_N_in #(
.N(N)
) a1 (
ain,
bin,
c
);
endmodule
| 6.530958 |
module add_N_with_Sign (
a,
b,
c,
sub
);
parameter N = 10;
input [N-1:0] a, b;
input sub;
output [N:0] c;
wire [N:0] ain = {1'b0, a};
wire [N:0] bin = {1'b0, b};
assign c = sub ? ain - bin : ain + bin;
endmodule
| 6.97792 |
module add_N_in (
a,
b,
c
);
parameter N = 10;
input [N:0] a, b;
output [N:0] c;
assign c = a + b;
endmodule
| 6.842185 |
module abs_regime (
rc,
regime,
regime_N
);
parameter N = 10;
input rc;
input [N-1:0] regime;
output [N:0] regime_N;
assign regime_N = rc ? {1'b0, regime} : -{1'b0, regime};
endmodule
| 6.556222 |
module conv_2c (
a,
c
);
parameter N = 10;
input [N:0] a;
output [N:0] c;
assign c = a + 1'b1;
endmodule
| 6.984783 |
module DSR_left_N_S (
a,
b,
c
);
parameter N = 16;
parameter S = 4;
input [N-1:0] a;
input [S-1:0] b;
output [N-1:0] c;
wire [N-1:0] tmp[S-1:0];
assign tmp[0] = b[0] ? a << 7'd1 : a;
genvar i;
generate
for (i = 1; i < S; i = i + 1) begin : loop_blk
assign tmp[i] = b[i] ? tmp[i-1] << 2 ** i : tmp[i-1];
end
endgenerate
assign c = tmp[S-1];
endmodule
| 6.55013 |
module LOD_N (
in,
out
);
function [31:0] log2;
input reg [31:0] value;
begin
value = value - 1;
for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1;
end
endfunction
parameter N = 64;
parameter S = log2(N);
input [N-1:0] in;
output [S-1:0] out;
wire vld;
LOD #(
.N(N)
) l1 (
in,
out,
vld
);
endmodule
| 6.599292 |
module data_extract (
in,
rc,
regime,
exp,
mant,
Lshift
);
function [31:0] log2;
input reg [31:0] value;
begin
value = value - 1;
for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1;
end
endfunction
parameter N = 16;
parameter Bs = log2(N);
parameter es = 2;
input [N-1:0] in;
output rc;
output [Bs-1:0] regime, Lshift;
output [es-1:0] exp;
output [N-es-1:0] mant;
wire [N-1:0] xin = in;
assign rc = xin[N-2];
wire [Bs-1:0] k0, k1;
LOD_N #(
.N(N)
) xinst_k0 (
.in ({xin[N-2:0], 1'b0}),
.out(k0)
);
LZD_N #(
.N(N)
) xinst_k1 (
.in ({xin[N-3:0], 2'b0}),
.out(k1)
);
assign regime = xin[N-2] ? k1 : k0;
assign Lshift = xin[N-2] ? k1 + 1 : k0;
wire [N-1:0] xin_tmp;
DSR_left_N_S #(
.N(N),
.S(Bs)
) ls (
.a({xin[N-3:0], 2'b0}),
.b(Lshift),
.c(xin_tmp)
);
assign exp = xin_tmp[N-1:N-es];
assign mant = xin_tmp[N-es-1:0];
endmodule
| 7.155904 |
module LZD_N (
in,
out
);
function [31:0] log2;
input reg [31:0] value;
begin
value = value - 1;
for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1;
end
endfunction
parameter N = 64;
parameter S = log2(N);
input [N-1:0] in;
output [S-1:0] out;
wire vld;
LZD #(
.N(N)
) l1 (
in,
out,
vld
);
endmodule
| 6.977394 |
module sub_part_generate (
in,
rc,
regime,
exp,
mant
);
function [31:0] log2;
input reg [31:0] value;
begin
value = value - 1;
for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1;
end
endfunction
parameter N = 32;
parameter Bs = log2(N);
parameter es = 2;
input [N-1:0] in;
output rc;
output [Bs-1:0] regime;
output [es-1:0] exp;
output [N-es-1:0] mant;
wire sign_bit = in[N-1];
wire [N-1:0] twos_comp_in = sign_bit ? -in : in;
wire regime_bit_val = twos_comp_in[N-2];
wire [N-2:0] prio_in = regime_bit_val ? ~twos_comp_in[N-2:0] : twos_comp_in[N-2:0];
wire [Bs-1:0] prio_out;
wire not_all_zero_one;
wire [N-1:0] shifted_twos_comp_in;
wire found;
assign regime = regime_bit_val ? (N - 3 - prio_out) : (N - 2 - prio_out);
assign rc = regime_bit_val;
assign shifted_twos_comp_in = twos_comp_in << (N - prio_out);
prio_encoder #(
.LINES(N - 1)
) pe0 (
.in(prio_in),
.out(prio_out),
.found(found)
);
assign exp = shifted_twos_comp_in[N-1:N-es];
assign mant = shifted_twos_comp_in[N-es-1:0];
endmodule
| 6.643559 |
module prio_encoder (
in,
out,
found
);
parameter LINES = 128;
parameter WIDTH = $clog2(LINES);
input wire [(LINES-1):0] in;
output reg [(WIDTH-1):0] out;
output reg found;
integer I;
always @(in) begin
out = 0;
found = 0;
for (I = 0; I < LINES; I = I + 1) begin
if (in[I]) begin
out = I;
found = 1;
end
end
end
endmodule
| 6.98081 |
module all_tb ();
parameter width = 12;
reg clk;
reg [width-1:0] ad_out;
wire da_clk;
wire [width+1:0] dac_in;
wire sleep_dac;
wire ad_clk;
wire pwdn_adc;
wire [width-1:0] ddc_I;
wire [width-1:0] ddc_Q;
wire [width-1:0] pc_I;
wire [width-1:0] pc_Q;
wire [6*width:0] pc_abs2;
Receiver Receiver_tb (
.clk (clk),
.ad_out (ad_out),
.da_clk (da_clk),
.dac_in (dac_in),
.sleep_dac(sleep_dac),
.ad_clk (ad_clk),
.pwdn_adc (pwdn_adc),
.ddc_I (ddc_I),
.ddc_Q (ddc_Q),
.pc_I (pc_I),
.pc_Q (pc_Q),
.pc_abs2 (pc_abs2)
);
initial begin
#0 clk = 0;
end
always #50 clk = ~clk;
endmodule
| 6.665709 |
module all_zero_detector (
inA,
V
);
parameter n = 64;
// Assigning ports as in/out
input [n-1 : 0] inA;
output V;
assign V = (inA == 16'h0000000000000000) ? 1 : 0;
endmodule
| 8.974287 |
module PriorityEncoder_16_old (
input [15:0] data_i,
output reg [3:0] code_o
);
always @*
case (data_i)
16'b0000000000000001: code_o = 4'b0000;
16'b0000000000000010: code_o = 4'b0001;
16'b0000000000000100: code_o = 4'b0010;
16'b0000000000001000: code_o = 4'b0011;
16'b0000000000010000: code_o = 4'b0100;
16'b0000000000100000: code_o = 4'b0101;
16'b0000000001000000: code_o = 4'b0110;
16'b0000000010000000: code_o = 4'b0111;
16'b0000000100000000: code_o = 4'b1000;
16'b0000001000000000: code_o = 4'b1001;
16'b0000010000000000: code_o = 4'b1010;
16'b0000100000000000: code_o = 4'b1011;
16'b0001000000000000: code_o = 4'b1100;
16'b0010000000000000: code_o = 4'b1101;
16'b0100000000000000: code_o = 4'b1110;
16'b1000000000000000: code_o = 4'b1111;
default: code_o = 4'b0000;
endcase
endmodule
| 6.599169 |
module PriorityEncoder_16 (
input [15:0] data_i,
output [ 3:0] code_o
);
wire [7:0] tmp0;
assign tmp0 = {
data_i[15], data_i[13], data_i[11], data_i[9], data_i[7], data_i[5], data_i[3], data_i[1]
};
OR_tree code0 (
tmp0,
code_o[0]
);
wire [7:0] tmp1;
assign tmp1 = {
data_i[15], data_i[14], data_i[11], data_i[10], data_i[7], data_i[6], data_i[3], data_i[2]
};
OR_tree code1 (
tmp1,
code_o[1]
);
wire [7:0] tmp2;
assign tmp2 = {
data_i[15], data_i[14], data_i[13], data_i[12], data_i[7], data_i[6], data_i[5], data_i[4]
};
OR_tree code2 (
tmp2,
code_o[2]
);
wire [7:0] tmp3;
assign tmp3 = {
data_i[15], data_i[14], data_i[13], data_i[12], data_i[11], data_i[10], data_i[9], data_i[8]
};
OR_tree code3 (
tmp3,
code_o[3]
);
endmodule
| 6.599169 |
module OR_tree (
input [7:0] data_i,
output data_o
);
wire [3:0] tmp1;
wire [1:0] tmp2;
assign tmp1 = data_i[3:0] | data_i[7:4];
assign tmp2 = tmp1[1:0] | tmp1[3:2];
assign data_o = tmp2[0] | tmp2[1];
endmodule
| 7.726839 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module LOD16 (
input [15:0] data_i,
output zero_o,
output [15:0] data_o
);
wire [15:0] z;
wire [ 3:0] select;
wire [ 3:0] zdet;
//*****************************************
// Zero detection logic:
//*****************************************
assign zdet[3] = data_i[15] | data_i[14] | data_i[13] | data_i[12];
assign zdet[2] = data_i[11] | data_i[10] | data_i[9] | data_i[8];
assign zdet[1] = data_i[7] | data_i[6] | data_i[5] | data_i[4];
assign zdet[0] = data_i[3] | data_i[2] | data_i[1] | data_i[0];
assign zero_o = ~(zdet[3] | zdet[2] | zdet[1] | zdet[0]);
//*****************************************
// LODs:
//*****************************************
LOD4 lod4_3 (
.data_i(data_i[15:12]),
.data_o(z[15:12])
);
LOD4 lod4_2 (
.data_i(data_i[11:8]),
.data_o(z[11:8])
);
LOD4 lod4_1 (
.data_i(data_i[7:4]),
.data_o(z[7:4])
);
LOD4 lod4_0 (
.data_i(data_i[3:0]),
.data_o(z[3:0])
);
LOD4 lod4_middle (
.data_i(zdet),
.data_o(select)
);
//*****************************************
// Multiplexers :
//*****************************************
Muxes2in1Array4 Inst_MUX214_3 (
.data_i (z[15:12]),
.select_i(select[3]),
.data_o (data_o[15:12])
);
Muxes2in1Array4 Inst_MUX214_2 (
.data_i (z[11:8]),
.select_i(select[2]),
.data_o (data_o[11:8])
);
Muxes2in1Array4 Inst_MUX214_1 (
.data_i (z[7:4]),
.select_i(select[1]),
.data_o (data_o[7:4])
);
Muxes2in1Array4 Inst_MUX214_0 (
.data_i (z[3:0]),
.select_i(select[0]),
.data_o (data_o[3:0])
);
endmodule
| 7.892753 |
module Barrel16L (
input [15:0] data_i,
input [ 3:0] shift_i,
output [ 6:0] data_o
);
reg [15:0] tmp;
always @*
case (shift_i)
4'b0000: tmp = data_i;
4'b0001: tmp = data_i << 1;
4'b0010: tmp = data_i << 2;
4'b0011: tmp = data_i << 3;
4'b0100: tmp = data_i << 4;
4'b0101: tmp = data_i << 5;
4'b0110: tmp = data_i << 6;
4'b0111: tmp = data_i << 7;
4'b1000: tmp = data_i << 8;
4'b1001: tmp = data_i << 9;
4'b1010: tmp = data_i << 10;
4'b1011: tmp = data_i << 11;
4'b1100: tmp = data_i << 12;
4'b1101: tmp = data_i << 13;
4'b1110: tmp = data_i << 14;
default: tmp = data_i << 15;
endcase
assign data_o = tmp[15:9];
endmodule
| 7.500498 |
module Barrel16R (
input [15:0] data_i,
input [3:0] shift_i,
output reg [15:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i >> 1;
4'b0010: data_o = data_i >> 2;
4'b0011: data_o = data_i >> 3;
4'b0100: data_o = data_i >> 4;
4'b0101: data_o = data_i >> 5;
4'b0110: data_o = data_i >> 6;
4'b0111: data_o = data_i >> 7;
4'b1000: data_o = data_i >> 8;
4'b1001: data_o = data_i >> 9;
4'b1010: data_o = data_i >> 10;
4'b1011: data_o = data_i >> 11;
4'b1100: data_o = data_i >> 12;
4'b1101: data_o = data_i >> 13;
4'b1110: data_o = data_i >> 14;
default: data_o = data_i >> 15;
endcase
endmodule
| 7.464977 |
module Barrel32L (
input [31:0] data_i,
input [4:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
5'b00000: data_o = data_i;
5'b00001: data_o = data_i << 1;
5'b00010: data_o = data_i << 2;
5'b00011: data_o = data_i << 3;
5'b00100: data_o = data_i << 4;
5'b00101: data_o = data_i << 5;
5'b00110: data_o = data_i << 6;
5'b00111: data_o = data_i << 7;
5'b01000: data_o = data_i << 8;
5'b01001: data_o = data_i << 9;
5'b01010: data_o = data_i << 10;
5'b01011: data_o = data_i << 11;
5'b01100: data_o = data_i << 12;
5'b01101: data_o = data_i << 13;
5'b01110: data_o = data_i << 14;
5'b01111: data_o = data_i << 15;
default: data_o = data_i << 16;
endcase
endmodule
| 7.342303 |
module FAd (
a,
b,
c,
cy,
sm
);
input a, b, c;
output cy, sm;
wire x, y, z;
xor x1 (x, a, b);
xor x2 (sm, x, c);
and a1 (y, a, b);
and a2 (z, x, c);
or o1 (cy, y, z);
endmodule
| 7.593245 |
module ALM11_SOA (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
// Generate abs values
wire [15:0] x_abs;
wire [15:0] y_abs;
// Going for X_abs
assign x_abs = x ^ {16{x[15]}};
// Going for Y_abs
assign y_abs = y ^ {16{y[15]}};
// LOD x
wire [15:0] kx;
wire zero_x;
wire [3:0] code_x;
LOD16 LODx (
.data_i(x_abs),
.zero_o(zero_x),
.data_o(kx)
);
PriorityEncoder_16 PEx (
.data_i(kx),
.code_o(code_x)
);
// LOD y
wire [15:0] ky;
wire zero_y;
wire [3:0] code_y;
LOD16 LODy (
.data_i(y_abs),
.zero_o(zero_y),
.data_o(ky)
);
PriorityEncoder_16 PEy (
.data_i(ky),
.code_o(code_y)
);
// Barell shift X
wire [3:0] code_x_inv;
wire [5:0] barrel_x;
assign code_x_inv = ~code_x;
Barrel16L BShiftx (
.data_i (x_abs),
.shift_i(code_x_inv),
.data_o (barrel_x)
);
// Barell shift Y
wire [3:0] code_y_inv;
wire [5:0] barrel_y;
assign code_y_inv = ~code_y;
Barrel16L BShifty (
.data_i (y_abs),
.shift_i(code_y_inv),
.data_o (barrel_y)
);
// Addition of Op1 and Op2
wire [8:0] op1;
wire [8:0] op2;
wire [19:0] L;
wire c_in;
assign op1 = {1'b0, code_x, barrel_x[4:1]};
assign op2 = {1'b0, code_y, barrel_y[4:1]};
assign c_in = barrel_x[0] & barrel_y[0];
assign L[19:11] = c_in + op1 + op2;
assign L[10:0] = {11{1'b1}};
// Anti logarithm
wire [31:0] tmp_out;
AntiLog anti_log (
.data_i(L),
.data_o(tmp_out)
);
// xor
wire prod_sign;
wire [31:0] tmp_sign;
assign prod_sign = x[15] ^ y[15];
assign tmp_sign = {32{prod_sign}} ^ tmp_out;
// is zero
wire not_zero;
assign not_zero = (~zero_x | x[15] | x[0]) & (~zero_y | y[15] | y[0]);
assign p = not_zero ? tmp_sign : 32'b0;
endmodule
| 6.650726 |
module PriorityEncoder_16_old (
input [15:0] data_i,
output reg [3:0] code_o
);
always @*
case (data_i)
16'b0000000000000001: code_o = 4'b0000;
16'b0000000000000010: code_o = 4'b0001;
16'b0000000000000100: code_o = 4'b0010;
16'b0000000000001000: code_o = 4'b0011;
16'b0000000000010000: code_o = 4'b0100;
16'b0000000000100000: code_o = 4'b0101;
16'b0000000001000000: code_o = 4'b0110;
16'b0000000010000000: code_o = 4'b0111;
16'b0000000100000000: code_o = 4'b1000;
16'b0000001000000000: code_o = 4'b1001;
16'b0000010000000000: code_o = 4'b1010;
16'b0000100000000000: code_o = 4'b1011;
16'b0001000000000000: code_o = 4'b1100;
16'b0010000000000000: code_o = 4'b1101;
16'b0100000000000000: code_o = 4'b1110;
16'b1000000000000000: code_o = 4'b1111;
default: code_o = 4'b0000;
endcase
endmodule
| 6.599169 |
module PriorityEncoder_16 (
input [15:0] data_i,
output [ 3:0] code_o
);
wire [7:0] tmp0;
assign tmp0 = {
data_i[15], data_i[13], data_i[11], data_i[9], data_i[7], data_i[5], data_i[3], data_i[1]
};
OR_tree code0 (
tmp0,
code_o[0]
);
wire [7:0] tmp1;
assign tmp1 = {
data_i[15], data_i[14], data_i[11], data_i[10], data_i[7], data_i[6], data_i[3], data_i[2]
};
OR_tree code1 (
tmp1,
code_o[1]
);
wire [7:0] tmp2;
assign tmp2 = {
data_i[15], data_i[14], data_i[13], data_i[12], data_i[7], data_i[6], data_i[5], data_i[4]
};
OR_tree code2 (
tmp2,
code_o[2]
);
wire [7:0] tmp3;
assign tmp3 = {
data_i[15], data_i[14], data_i[13], data_i[12], data_i[11], data_i[10], data_i[9], data_i[8]
};
OR_tree code3 (
tmp3,
code_o[3]
);
endmodule
| 6.599169 |
module OR_tree (
input [7:0] data_i,
output data_o
);
wire [3:0] tmp1;
wire [1:0] tmp2;
assign tmp1 = data_i[3:0] | data_i[7:4];
assign tmp2 = tmp1[1:0] | tmp1[3:2];
assign data_o = tmp2[0] | tmp2[1];
endmodule
| 7.726839 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module LOD16 (
input [15:0] data_i,
output zero_o,
output [15:0] data_o
);
wire [15:0] z;
wire [ 3:0] select;
wire [ 3:0] zdet;
//*****************************************
// Zero detection logic:
//*****************************************
assign zdet[3] = data_i[15] | data_i[14] | data_i[13] | data_i[12];
assign zdet[2] = data_i[11] | data_i[10] | data_i[9] | data_i[8];
assign zdet[1] = data_i[7] | data_i[6] | data_i[5] | data_i[4];
assign zdet[0] = data_i[3] | data_i[2] | data_i[1] | data_i[0];
assign zero_o = ~(zdet[3] | zdet[2] | zdet[1] | zdet[0]);
//*****************************************
// LODs:
//*****************************************
LOD4 lod4_3 (
.data_i(data_i[15:12]),
.data_o(z[15:12])
);
LOD4 lod4_2 (
.data_i(data_i[11:8]),
.data_o(z[11:8])
);
LOD4 lod4_1 (
.data_i(data_i[7:4]),
.data_o(z[7:4])
);
LOD4 lod4_0 (
.data_i(data_i[3:0]),
.data_o(z[3:0])
);
LOD4 lod4_middle (
.data_i(zdet),
.data_o(select)
);
//*****************************************
// Multiplexers :
//*****************************************
Muxes2in1Array4 Inst_MUX214_3 (
.data_i (z[15:12]),
.select_i(select[3]),
.data_o (data_o[15:12])
);
Muxes2in1Array4 Inst_MUX214_2 (
.data_i (z[11:8]),
.select_i(select[2]),
.data_o (data_o[11:8])
);
Muxes2in1Array4 Inst_MUX214_1 (
.data_i (z[7:4]),
.select_i(select[1]),
.data_o (data_o[7:4])
);
Muxes2in1Array4 Inst_MUX214_0 (
.data_i (z[3:0]),
.select_i(select[0]),
.data_o (data_o[3:0])
);
endmodule
| 7.892753 |
module Barrel16L (
input [15:0] data_i,
input [ 3:0] shift_i,
output [ 5:0] data_o
);
reg [15:0] tmp;
always @*
case (shift_i)
4'b0000: tmp = data_i;
4'b0001: tmp = data_i << 1;
4'b0010: tmp = data_i << 2;
4'b0011: tmp = data_i << 3;
4'b0100: tmp = data_i << 4;
4'b0101: tmp = data_i << 5;
4'b0110: tmp = data_i << 6;
4'b0111: tmp = data_i << 7;
4'b1000: tmp = data_i << 8;
4'b1001: tmp = data_i << 9;
4'b1010: tmp = data_i << 10;
4'b1011: tmp = data_i << 11;
4'b1100: tmp = data_i << 12;
4'b1101: tmp = data_i << 13;
4'b1110: tmp = data_i << 14;
default: tmp = data_i << 15;
endcase
assign data_o = tmp[15:10];
endmodule
| 7.500498 |
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