code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module spmv_scatter_pipe #(
parameter PIPE_DEPTH = 3,
parameter URAM_DATA_W = 32
) (
input wire clk,
input wire rst,
input wire [ 31:0] edge_weight,
input wire [URAM_DATA_W-1:0] src_attr,
input wire [ 31:0] edge_dest,
input w... | 7.323698 |
module pr_PP #(
parameter PIPE_DEPTH = 5,
parameter URAM_DATA_W = 64,
parameter PAR_SIZE_W = 10,
parameter EDGE_W = 64
) (
input wire clk,
input wire rst,
input wire [ 1:0] control,
input wire [URAM_DATA_W-1:0] buffer_Din,
input wir... | 7.751799 |
module pr_gather_pipe #(
parameter PIPE_DEPTH = 3,
parameter PAR_SIZE_W = 18,
parameter URAM_DATA_W = 64
) (
input wire clk,
input wire rst,
input wire [ 31:0] update_value,
input wire [ 31:0] update_dest,
input wire [URAM_DA... | 7.88561 |
module pr_scatter_pipe #(
parameter PIPE_DEPTH = 3,
parameter URAM_DATA_W = 64
) (
input wire clk,
input wire rst,
input wire [ 31:0] edge_weight,
input wire [URAM_DATA_W-1:0] src_attr,
input wire [ 31:0] edge_dest,
input wir... | 7.920956 |
module sssp_PP #(
parameter PIPE_DEPTH = 5,
parameter URAM_DATA_W = 32,
parameter PAR_SIZE_W = 10,
parameter EDGE_W = 64
) (
input wire clk,
input wire rst,
input wire [ 1:0] control,
input wire [ ... | 7.398986 |
module sssp_gather_pipe #(
parameter PIPE_DEPTH = 1,
parameter PAR_SIZE_W = 18,
parameter URAM_DATA_W = 32
) (
input wire clk,
input wire rst,
input wire [ 31:0] update_value,
input wire [ 31:0] update_dest,
input wire [URAM_... | 7.379624 |
module sssp_scatter_pipe #(
parameter PIPE_DEPTH = 3,
parameter URAM_DATA_W = 32
) (
input wire clk,
input wire rst,
input wire [ 15:0] edge_weight,
input wire [URAM_DATA_W-1:0] src_attr,
input wire [ 23:0] edge_dest,
input w... | 7.591014 |
module wcc_PP #(
parameter PIPE_DEPTH = 5,
parameter URAM_DATA_W = 32,
parameter PAR_SIZE_W = 10,
parameter EDGE_W = 64
) (
input wire clk,
input wire rst,
input wire [ 1:0] control,
input wire [ ... | 6.979337 |
module wcc_gather_pipe #(
parameter PIPE_DEPTH = 1,
parameter PAR_SIZE_W = 18,
parameter URAM_DATA_W = 32
) (
input wire clk,
input wire rst,
input wire [ 31:0] update_value,
input wire [ 31:0] update_dest,
input wire [URAM_D... | 7.202247 |
module wcc_scatter_pipe #(
parameter PIPE_DEPTH = 3,
parameter URAM_DATA_W = 32
) (
input wire clk,
input wire rst,
input wire [ 15:0] edge_weight,
input wire [URAM_DATA_W-1:0] src_attr,
input wire [ 31:0] edge_dest,
input wi... | 7.522624 |
module decompressor_16 (
input [15:0] data_in,
output [31:0] data_out
);
// decompress the 16-bit input into a 32-bit FP number
reg [ 5:0] total_sum;
wire [ 7:0] exp;
wire [22:0] mantissa;
always @(*) begin
casez (data_in[14:0])
15'b1??_????_????_????: total_sum = 1;
15'b01?_????_... | 7.759808 |
module decompressor_8 (
input [ 7:0] data_in,
output [31:0] data_out
);
// decompress the 8-bit input into a 32-bit FP number
reg [ 5:0] total_sum;
wire [ 7:0] exp;
wire [22:0] mantissa;
always @(*) begin
casez (data_in[6:0])
7'b1??_????: total_sum = 1;
7'b01?_????: total_sum = 2;... | 7.759808 |
module ALGO_cmos_8_16bit (
input rst,
input pclk,
input [7:0] pdata_i,
input de_i,
input fe_i,
output reg [15:0] pdata_o,
output reg cmos_vsync,
output reg cmos_href,
output reg de_o
);
reg [7:0] pdata_i_d0;
reg [7:0] pdata_i_d1;
reg de_i_d0;
reg [11:0] x_cnt;
// reg cmos_... | 7.114431 |
module ALGO_pro #(
parameter H_HSV_THRE_MIN = 32'h0,
parameter H_HSV_THRE_MAX = 32'h3DCCCCCD,
parameter S_HSV_THRE_MIN = 0,
parameter S_HSV_THRE_MAX = 32'h3DCCCCCD,
parameter V_HSV_THRE_MIN = 0,
parameter V_HSV_THRE_MAX = 32'h3DCCCCCD
) (
i_cmos_rst_n,
i_cmos_d_pclk,
i_cmos_d,
i_... | 7.454435 |
module decompressor (
input [31:0] decomp_in,
input [1:0] bitmap,
output reg [31:0] result
);
wire [ 7:0] in_8;
wire [15:0] in_16;
wire [31:0] result_8;
wire [31:0] result_16;
assign in_8 = decomp_in[7:0];
assign in_16 = decomp_in[15:0];
decompressor_8 d8_inst (
in_8,
result_8... | 7.153112 |
module alg_ae #(
parameter BITS = 8
) (
input pclk,
input rst_n,
input in_vsync,
input stat_done,
input [BITS-1:0] target_val,
input [31:0] pix_cnt,
input [31:0] sum,
output reg [7:0] dgain,
output reg cmos_change_start,
input cmos_change_done,
output r... | 7.107459 |
module alg_awb #(
parameter BITS = 8
) (
input pclk,
input rst_n,
input stat_done,
input [31:0] pix_cnt,
input [31:0] sum_r,
input [31:0] sum_g,
input [31:0] sum_b,
output reg [7:0] r_gain,
output reg [7:0] g_gain,
output reg [7:0] b_gain
);
`define AWB_USE_SHIFT_DIV 1
... | 7.693443 |
module Alice (
input a,
input b,
output [1:0] qubit
);
wire [1:0] eigen_value = {a, b};
//There can be 4 possible eigen value
//Eigen Value = 2'b00 => Zero
//Eigen Value = 2'b01 => Plus
//Eigen Value = 2'b10 => One
//Eigen Value = 2'b11 => Minus
//These Eigen Values are equivalent of the ... | 6.781856 |
module align (
input [15:0] a,
output [15:0] value,
output z_s
);
assign value = a[15] ? -a : a;
assign z_s = a[15];
endmodule
| 7.456157 |
module AlignedRAM (
input [31:0] addr,
inout [31:0] data,
input [1:0] size,
input rw,
clk
);
parameter ADDR = 32'h2000_0000;
parameter SIZE = 256;
localparam REAL_SIZE = SIZE / 4;
reg [31:0] mem[REAL_SIZE-1:0];
reg [31:0] buffer;
wire enabled = (addr >= ADDR) && (addr < (ADDR + SIZE));... | 7.979075 |
module aligner (
Exp_a_DI,
Exp_b_DI,
Exp_c_DI,
Mant_a_DI,
Sign_a_DI,
Sign_b_DI,
Sign_c_DI,
Pp_sum_DI,
Pp_carry_DI,
Sub_SO,
Mant_postalig_a_DO,
Exp_postalig_DO,
Sign_postalig_DO,
Sign_amt_DO,
Sft_stop_SO,
Pp_sum_postcal_DO,
Pp_carry_postcal_DO
);
para... | 6.674309 |
module Aligner_tb;
reg clk;
reg reset;
reg wrt_en;
reg push0;
reg pop0;
wire empty0;
wire full0;
wire almost_full0;
reg push1;
reg pop1;
wire empty1;
wire full1;
wire... | 6.559776 |
module alignment (
input [14:0] bigger,
input [14:0] smaller,
output [10:0] aligned_small
);
wire c1;
wire [4:0] bigger_exponent, smaller_exponent, shift_bits;
assign bigger_exponent = bigger [14:10];
assign smaller_exponent = smaller [14:10];
assign aligned_small = ({1'b1,smaller[9:0]} >... | 6.625423 |
module Alignment_2 (
bef_shift_x,
bef_shift_y,
sgn_d,
out_x,
out_y
);
input [23:0] bef_shift_x, bef_shift_y;
input sgn_d;
output reg [23:0] out_x, out_y;
always @(*) begin
if(sgn_d) //SWAP bloc;
begin
out_x = bef_shift_y;
out_y = bef_shift_x;
end else begin
... | 6.922723 |
module Alignment_4_2 (
shR_y,
d,
out_y_shR
);
input [52:0] shR_y;
input [7:0] d;
output reg [52:0] out_y_shR;
always @(*) begin
out_y_shR = shR_y >> d;
end
endmodule
| 7.688765 |
module Alignment_4_3 (
out_y_shR,
sticky
);
input [52:0] out_y_shR;
output reg sticky;
always @(*) begin
sticky = |out_y_shR[26:0];
end
endmodule
| 6.844722 |
module Alignment_4_4 (
out_y_shR,
sticky,
out_y_with_T
);
input [52:0] out_y_shR;
input sticky;
output reg [26:0] out_y_with_T;
always @(*) begin
out_y_with_T = {out_y_shR[52:27], sticky};
end
endmodule
| 6.931663 |
module Alignment_5 (
Mx,
My,
Cmp
);
input [22:0] Mx, My;
output reg Cmp;
always @(*) begin
if(Mx>=My) //Compare Block
begin
Cmp = 1'b0;
end else begin
Cmp = 1'b1;
end
end
endmodule
| 6.978224 |
module Alignment_7 (
bit_inv_cont_x,
bit_inv_cont_y,
out_x_shR,
out_y_with_T,
out_11,
out_22
);
input bit_inv_cont_x, bit_inv_cont_y;
input [26:0] out_x_shR;
input [26:0] out_y_with_T;
output reg [26:0] out_11;
output reg [26:0] out_22;
always @(*) begin
if (bit_inv_cont_x) begin... | 7.081253 |
module align_1 (
input [7:0] BE,
input [7:0] AE,
output reg [7:0] d
);
always @(AE, BE) begin
if (AE > BE) begin
d = AE - BE;
end else if (AE < BE) begin
d = BE - AE;
end else begin
d = 8'b0;
end
end
endmodule
| 6.70445 |
module align_16 (
input clk,
input [3:0] pos,
input din_valid,
input [15:0] din, // lsbit first
output reg [15:0] dout // lsbit first
);
initial dout = 0;
reg [16+15-1:0] mid = 0;
always @(posedge clk) begin
if (din_valid) begin
case (pos[3:2])
2'b00: mid <= {din, mid[30:... | 7.017779 |
module align_clk_sync #(
// fsm type parameter
parameter N = 32
) (
// Input side
input clk_in,
input rst_in,
input [N-1:0] i_data,
input i_valid,
output o_stall,
// Output side
input clk_out,
input rst_out,
output [N-... | 6.562057 |
module align_clk_sync_2 #
(
// fsm type parameter
parameter N = 32
) (
// Input side
input clk_in,
input rst_in,
input [N-1:0] i_data,
input i_valid,
output o_stall,
// Output side
input clk_out,
input rst_out,
output [N-1:0] o_data,
... | 6.562057 |
module align_clk_sync_2_halfword(
// Input side
input clk_in,
input rst_in,
input [15:0] i_data,
input i_valid_high,
input i_valid_low,
output o_stall,
// Output side
input clk_out,
input rst_out,
output [31:0] o_data,
output ... | 6.562057 |
module align_mux #(
parameter DATA_PATH_WIDTH = 4
) (
input clk,
input [1:0] align,
input [DATA_PATH_WIDTH*8-1:0] in_data,
input [DATA_PATH_WIDTH-1:0] in_charisk,
output reg [DATA_PATH_WIDTH*8-1:0] out_data,
output reg [DATA_PATH_WIDTH-1:0] out_charisk
);
reg [DATA_PATH_WIDTH*8-1:0] in_da... | 7.913104 |
module align_r #(
parameter IN_P_DW_BYTES = 0,
parameter IN_AW = 0,
parameter OUT_P_DW_BYTES = 0
) (
input [ (1<<IN_P_DW_BYTES)*8-1:0] i_dat,
input [ (1<<IN_P_DW_BYTES)-1:0] i_be,
input [ IN_AW-1:0] i_addr,
output [ (1<<OUT_P_DW_BYTES)-1:0] o_be,
output [(1... | 6.601645 |
module align_t (
input [15:0] input_a,
output [15:0] a_m,
output [5:0] a_e,
output a_s
);
wire [15:0] a;
assign a = input_a;
assign a_m[15:5] = {1'b1, a[9 : 0]};
assign a_m[4:0] = 8'b0;
assign a_e = a[14 : 10] - 15;
assign a_s = a[15];
endmodule
| 6.666471 |
module align_w #(
parameter IN_P_DW_BYTES = 0,
parameter OUT_P_DW_BYTES = 0,
parameter IN_AW = 0
) (
input [(1<<OUT_P_DW_BYTES)*8-1:0] i_dat,
input [ (1<<OUT_P_DW_BYTES)-1:0] i_be,
input [ IN_AW-1:0] i_addr,
output [ (1<<IN_P_DW_BYTES)-1:0] o_be,
output [ (... | 6.64704 |
module alinhamentos (
doutalign
); // Este modulo é responsavel por gerar as tramas de controlo e alinhamento de trama
output wire [7:0] doutalign; //tramas para inserir no processamento
//Para testes estas variaveis c1, c2, c3, c4, e1 e e2 vão ter o papel de constantes fixadas a '0' lógico
reg [7:0] trama... | 7.935066 |
module AliniereMantise (
mantise,
mantise_out,
semn
);
input wire [27:0] mantise;
output reg [21:0] mantise_out;
output reg semn;
//output reg op;
reg [5:0] valoare;
reg [10:0] mantisa1, mantisa2;
reg semn1, semn2;
always @(mantise) begin
valoare = mantise[27:22];
mantisa1 = mantis... | 7.776647 |
module test;
wire Co;
wire [3:0] S;
reg [3:0] A;
reg [3:0] B;
reg Ci;
CLA4 dut (
.Co(Co),
.S (S),
.A (A),
.B (B),
.Ci(Ci)
);
initial begin
#0 A = 4'b1010;
#0 B = 4'b0010;
#0 Ci = 1'b0;
#40 A = 4'b1010;
#40 B = 4'b0111;
#80 A = 4'b1111;
#80 B =... | 6.964054 |
module CLA4 (
Co,
S,
A,
B,
Ci
);
output Co;
output [3:0] S;
input [3:0] A;
input [3:0] B;
input Ci; // 0
wire [3:0] Carries;
wire [3:0] gene, prop; // Used in CLA
wire [3:0] Xprop, Yprop; // To Find Prop
// For Carry Circuits
wire C1;
wire [1:0] C2;
wire [2:0] C3;
wire ... | 8.659323 |
module FA (
Fsum,
Cout,
U,
V,
Cin
);
output Cout;
output Fsum;
input Cin;
input U;
input V;
wire X, Y, Z;
HA a (
X,
Y,
U,
V
);
HA b (
Fsum,
Z,
Cin,
X
);
or #1 (Cout, Z, Y);
endmodule
| 7.804384 |
module HA (
Sum,
Carry,
P,
Q
);
output Sum, Carry;
input P, Q;
and #4(Carry, P, Q);
xor #5(Sum, P, Q);
endmodule
| 7.201569 |
module allAdd (
input clk,
input hit,
input rst,
output [11:0] num
);
// 控制进位
wire carry_1;
wire carry_2;
wire carry_3;
// wire carry_4;
// wire carry_5;
// wire carry_6;
// wire carry_7;
// wire carry_8;
// rst 信号也相当于进位信号—?都是使得当前清?
assign carry_1 = ~(num[1] & num[3] | rst);
as... | 7.283906 |
module ALU (
F,
data,
B
);
output [15:0] F; // Output
input [19:0] data; // A and OP Derive from Data
input [15:0] B; // Input 2
wire [ 3:0] OP;
wire [15:0] A; // Input 1
control unit (
A,
OP,
data
);
hardware toplevel (
F,
A,
B,
OP
);
end... | 7.043664 |
module control (
A,
OP,
data
);
output [3:0] OP;
output [15:0] A;
input [19:0] data;
assign OP[3:0] = data[19:16];
assign A = data[15:0];
endmodule
| 7.715617 |
module hardware (
F,
A,
B,
OP
);
output [15:0] F; // Output
input [15:0] A; // Input 1
input [15:0] B; // Input 2
input [3:0] OP;
wire [15:0] shift_out;
wire [15:0] rca_out;
wire [15:0] and_out;
wire [15:0] or_out;
wire [15:0] multi_out;
wire [15:0] m421_out;
wire [15:0] m221_o... | 7.166936 |
module fulladder (
r,
cout,
p,
q,
cin
);
input p;
input q;
input cin;
output cout;
output r;
wire x, y, z;
xor #2(x, p, q);
xor #2(r, x, cin);
and #2(y, x, cin);
and #2(z, p, q);
or #2(cout, y, z);
endmodule
| 7.454465 |
module Mux2to1 (
out,
a,
b,
sel
);
output [15:0] out;
input [15:0] a;
input [15:0] b;
input sel;
wire [15:0] selextend;
wire [15:0] x;
wire [15:0] y;
wire [15:0] z;
assign selextend = {16{sel}};
nand #2(x[0], b[0], selextend[0]);
nand #2(x[1], b[1], selextend[1]);
nand #2(x[2... | 6.739082 |
module Allign2 (
input [1:0] idle_Allign,
input [35:0] cout_Allign,
input [35:0] zout_Allign,
input [31:0] sout_Allign,
input [1:0] modeout_Allign,
input operationout_Allign,
input NatLogFlagout_Allign,
input [7:0] difference_Allign,
input [7:0] InsTag_Allign,
input clock,
ou... | 6.980245 |
module AllignAdder (
input idle_Special,
input [35:0] cout_Special,
input [35:0] zout_Special,
input [31:0] sout_Special,
input [7:0] difference_Special,
input clock,
output reg idle_Allign,
output reg [35:0] cout_Allign,
output reg [35:0] zout_Allign,
output reg [31:0] sout_Alli... | 7.400136 |
module allocate (
input wire clk,
input wire rst,
input wire [31:0] CPU_addr,
input wire [31:0] main_mem_dout,
output reg [12:0] main_mem_addr,
output reg [ 8:0] cache_data_addr,
output wire [31:0] cache_data_din,
output reg cache_data_we,
input wire ... | 7.379282 |
module alloc_three #(
parameter CHANNEL_ID = `LOCAL, //input port
parameter ROUTER_ID_X = 0,
parameter ROUTER_ID_Y = 0
) (
input wire clk,
input wire rstn,
input wire [`DATA_WIDTH-1:0] data_i,
input wire valid_i,
output wire ready_o,
//left o... | 7.241093 |
module alloc_two #(
parameter CHANNEL_ID = `LEFT, //input port
parameter ROUTER_ID_X = 0,
parameter ROUTER_ID_Y = 0
) (
input wire clk,
input wire rstn,
input wire [`DATA_WIDTH-1:0] data_i,
input wire valid_i,
output wire ready_o,
//right out... | 6.608122 |
module produces an actual clock
// with 50% duty cycle :)
// Use it as you would use the default clck.
// Examples for 50 MHz --> 1 Hz
module frequency_divider(clk,rst,clk_out); // debug code: , counter);
input clk,rst;
// clk is the original clk
output reg clk_out; // desired clk
// factor = original frequency ... | 7.056371 |
module's duty cycle varies.
// Always use negedge of this clock
// otherwise your clock will mess up
// Examples for 50 MHz --> 1 Hz
module frequency_divider_special(clk,rst,clk_out); // debug code: , counter);
input clk,rst;
// clk is the original clk
output clk_out; // desired clk
// factor = original frequen... | 7.386754 |
module all_adder_OR1_0_1 (
A,
B,
F
);
input wire A;
input wire B;
output wire F;
OR1 inst (
.A(A),
.B(B),
.F(F)
);
endmodule
| 6.823786 |
module all_adder_OR1_0_1 (
A,
B,
F
);
input A;
input B;
output F;
wire A;
wire B;
wire F;
LUT2 #(
.INIT(4'hE)
) F_INST_0 (
.I0(A),
.I1(B),
.O (F)
);
endmodule
| 6.823786 |
module all_adder_wrapper (
A,
B,
C,
Ci,
S
);
input A;
input B;
output C;
input Ci;
output S;
wire A;
wire B;
wire C;
wire Ci;
wire S;
all_adder all_adder_i (
.A (A),
.B (B),
.C (C),
.Ci(Ci),
.S (S)
);
endmodule
| 7.266315 |
module all_arithm (
input clk,
input [31:0] in_s,
output [31:0] sqrt
);
wire [31:0] real_sqrt;
wire [31:0] rough_sqrt;
wire incorrect;
reg [31:0] in_s_shift[2:0];
reg [31:0] rough_shift[1:0];
wire [23:0] out_D_mantissa;
wire [23:0] out_x_mantissa;
wire [7:0] out_exponent;
wire sign;
w... | 8.460002 |
module all_arithm_testbench;
reg clk;
reg [31:0] in_s;
wire [31:0] sqrt;
all_arithm dut (
.clk (clk),
.in_s(in_s),
.sqrt(sqrt)
);
always #5 clk = ~clk;
initial begin
$dumpfile("all_arithm_testbench.vcd");
$dumpvars;
{clk, in_s} = 0;
#10 in_s = 32'h42800000; // 64
... | 7.030615 |
module all_bgr_top #(
parameter BITS = 32
) (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
input wire [31:0] porst, // start up signal for 32 BGR macros
input wire [ 4... | 7.789044 |
module inv (
a,
b
);
input wire a;
output wire b;
assign b = ~a;
endmodule
| 6.790398 |
module all_blocks (
input clk
);
tri [4:0] data_bus;
wire [2:0] grant_bus;
wire [2:0] out_requests[3:0];
wire [2:0] slaves_data [3:0];
master #(4) master_4 (
.clk(clk),
.grant(grant_bus),
.in_request(3'b000),
.data(data_bus),
.out_request(out_requests[0])
);
master #(... | 7.635112 |
module all_blocks_tb;
reg clk;
all_blocks dut (.clk(clk));
always #5 clk = ~clk;
initial begin
$dumpfile("all_blocks_tb.vcd");
$dumpvars;
clk = 0;
#200 $stop;
$finish;
end
endmodule
| 6.681443 |
module all_blocks_testbench;
parameter ADDRESS_WIDTH = 5;
parameter DATA_WIDTH = 8;
parameter BUFFER_LENGTH = 5;
parameter DATA_DELAY = 3;
reg clk;
reg start;
reg [ADDRESS_WIDTH-1:0] address;
reg rom_nram;
wire [DATA_WIDTH-1:0] general_data_bus;
integer i;
all_blocks #(
.ADDRESS_WIDTH(AD... | 7.368027 |
module mux8 (
Muxout,
D1,
D2,
sel
);
input [7:0] D1;
input [7:0] D2;
input sel;
output reg [7:0] Muxout;
always @(D1 or D2 or sel) begin
if (sel == 1'b0) begin
#10 Muxout <= D1;
end else begin
#10 Muxout <= D2;
end
end
endmodule
| 6.605633 |
module cla8 (
Sum,
Cout,
F,
G,
Ci,
Operate
);
input [7:0] F;
input [7:0] G;
input Operate;
input Ci;
output reg [7:0] Sum;
output reg Cout;
reg [8:0] t;
reg [7:0] inv;
always @(posedge Operate) begin
if (Ci) begin
inv = -F;
t <= inv + G;
end else begin
... | 6.866219 |
module all_scoreboard_generator (
input V,
input [2:0] DR1,
DR2,
DR3,
input [1:0] DR1_SIZE,
DR2_SIZE,
DR3_SIZE,
input LD_GPR1,
LD_GPR2,
LD_GPR3,
input LD_SEG,
LD_CSEG,
input LD_MM,
output [23:0] GPR_SCOREBOARD,
output [ 7:0] SEG_SCOREBOARD,
output [ 7:0... | 6.907789 |
module data_extract_v1 (
in,
rc,
regime,
exp,
mant
);
function [31:0] log2;
input reg [31:0] value;
begin
value = value - 1;
for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1;
end
endfunction
parameter N = 16;
parameter Bs = log2(N);
parameter es = 2;
... | 8.552482 |
module add_N (
a,
b,
c
);
parameter N = 10;
input [N-1:0] a, b;
output [N:0] c;
wire [N:0] ain = {1'b0, a};
wire [N:0] bin = {1'b0, b};
add_N_in #(
.N(N)
) a1 (
ain,
bin,
c
);
endmodule
| 6.530958 |
module add_N_with_Sign (
a,
b,
c,
sub
);
parameter N = 10;
input [N-1:0] a, b;
input sub;
output [N:0] c;
wire [N:0] ain = {1'b0, a};
wire [N:0] bin = {1'b0, b};
assign c = sub ? ain - bin : ain + bin;
endmodule
| 6.97792 |
module add_N_in (
a,
b,
c
);
parameter N = 10;
input [N:0] a, b;
output [N:0] c;
assign c = a + b;
endmodule
| 6.842185 |
module abs_regime (
rc,
regime,
regime_N
);
parameter N = 10;
input rc;
input [N-1:0] regime;
output [N:0] regime_N;
assign regime_N = rc ? {1'b0, regime} : -{1'b0, regime};
endmodule
| 6.556222 |
module conv_2c (
a,
c
);
parameter N = 10;
input [N:0] a;
output [N:0] c;
assign c = a + 1'b1;
endmodule
| 6.984783 |
module DSR_left_N_S (
a,
b,
c
);
parameter N = 16;
parameter S = 4;
input [N-1:0] a;
input [S-1:0] b;
output [N-1:0] c;
wire [N-1:0] tmp[S-1:0];
assign tmp[0] = b[0] ? a << 7'd1 : a;
genvar i;
generate
for (i = 1; i < S; i = i + 1) begin : loop_blk
assign tmp[i] = b[i] ? tmp[i-1... | 6.55013 |
module LOD_N (
in,
out
);
function [31:0] log2;
input reg [31:0] value;
begin
value = value - 1;
for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1;
end
endfunction
parameter N = 64;
parameter S = log2(N);
input [N-1:0] in;
output [S-1:0] out;
wire vld;
LOD #(... | 6.599292 |
module data_extract (
in,
rc,
regime,
exp,
mant,
Lshift
);
function [31:0] log2;
input reg [31:0] value;
begin
value = value - 1;
for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1;
end
endfunction
parameter N = 16;
parameter Bs = log2(N);
parameter e... | 7.155904 |
module LZD_N (
in,
out
);
function [31:0] log2;
input reg [31:0] value;
begin
value = value - 1;
for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1;
end
endfunction
parameter N = 64;
parameter S = log2(N);
input [N-1:0] in;
output [S-1:0] out;
wire vld;
LZD #(
... | 6.977394 |
module sub_part_generate (
in,
rc,
regime,
exp,
mant
);
function [31:0] log2;
input reg [31:0] value;
begin
value = value - 1;
for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1;
end
endfunction
parameter N = 32;
parameter Bs = log2(N);
parameter es = 2;
... | 6.643559 |
module prio_encoder (
in,
out,
found
);
parameter LINES = 128;
parameter WIDTH = $clog2(LINES);
input wire [(LINES-1):0] in;
output reg [(WIDTH-1):0] out;
output reg found;
integer I;
always @(in) begin
out = 0;
found = 0;
for (I = 0; I < LINES; I = I + 1) begin
if (in[I]) ... | 6.98081 |
module all_tb ();
parameter width = 12;
reg clk;
reg [width-1:0] ad_out;
wire da_clk;
wire [width+1:0] dac_in;
wire sleep_dac;
wire ad_clk;
wire pwdn_adc;
wire [width-1:0] ddc_I;
wire [width-1:0] ddc_Q;
wire [width-1:0] pc_I;
wire [wi... | 6.665709 |
module all_zero_detector (
inA,
V
);
parameter n = 64;
// Assigning ports as in/out
input [n-1 : 0] inA;
output V;
assign V = (inA == 16'h0000000000000000) ? 1 : 0;
endmodule
| 8.974287 |
module PriorityEncoder_16_old (
input [15:0] data_i,
output reg [3:0] code_o
);
always @*
case (data_i)
16'b0000000000000001: code_o = 4'b0000;
16'b0000000000000010: code_o = 4'b0001;
16'b0000000000000100: code_o = 4'b0010;
16'b0000000000001000: code_o = 4'b0011;
16'b0000000... | 6.599169 |
module PriorityEncoder_16 (
input [15:0] data_i,
output [ 3:0] code_o
);
wire [7:0] tmp0;
assign tmp0 = {
data_i[15], data_i[13], data_i[11], data_i[9], data_i[7], data_i[5], data_i[3], data_i[1]
};
OR_tree code0 (
tmp0,
code_o[0]
);
wire [7:0] tmp1;
assign tmp1 = {
data_i[1... | 6.599169 |
module OR_tree (
input [7:0] data_i,
output data_o
);
wire [3:0] tmp1;
wire [1:0] tmp2;
assign tmp1 = data_i[3:0] | data_i[7:4];
assign tmp2 = tmp1[1:0] | tmp1[3:2];
assign data_o = tmp2[0] | tmp2[1];
endmodule
| 7.726839 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module LOD16 (
input [15:0] data_i,
output zero_o,
output [15:0] data_o
);
wire [15:0] z;
wire [ 3:0] select;
wire [ 3:0] zdet;
//*****************************************
// Zero detection logic:
//*****************************************
assign zdet[3] = data_i[15] | data_i[14] | data... | 7.892753 |
module Barrel16L (
input [15:0] data_i,
input [ 3:0] shift_i,
output [ 6:0] data_o
);
reg [15:0] tmp;
always @*
case (shift_i)
4'b0000: tmp = data_i;
4'b0001: tmp = data_i << 1;
4'b0010: tmp = data_i << 2;
4'b0011: tmp = data_i << 3;
4'b0100: tmp = data_i << 4;
... | 7.500498 |
module Barrel16R (
input [15:0] data_i,
input [3:0] shift_i,
output reg [15:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i >> 1;
4'b0010: data_o = data_i >> 2;
4'b0011: data_o = data_i >> 3;
4'b0100: data_o = data_i >> 4;
... | 7.464977 |
module Barrel32L (
input [31:0] data_i,
input [4:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
5'b00000: data_o = data_i;
5'b00001: data_o = data_i << 1;
5'b00010: data_o = data_i << 2;
5'b00011: data_o = data_i << 3;
5'b00100: data_o = data_i << 4;
... | 7.342303 |
module FAd (
a,
b,
c,
cy,
sm
);
input a, b, c;
output cy, sm;
wire x, y, z;
xor x1 (x, a, b);
xor x2 (sm, x, c);
and a1 (y, a, b);
and a2 (z, x, c);
or o1 (cy, y, z);
endmodule
| 7.593245 |
module ALM11_SOA (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
// Generate abs values
wire [15:0] x_abs;
wire [15:0] y_abs;
// Going for X_abs
assign x_abs = x ^ {16{x[15]}};
// Going for Y_abs
assign y_abs = y ^ {16{y[15]}};
// LOD x
wire [15:0] kx;
wire zero_x;
wire [3... | 6.650726 |
module PriorityEncoder_16_old (
input [15:0] data_i,
output reg [3:0] code_o
);
always @*
case (data_i)
16'b0000000000000001: code_o = 4'b0000;
16'b0000000000000010: code_o = 4'b0001;
16'b0000000000000100: code_o = 4'b0010;
16'b0000000000001000: code_o = 4'b0011;
16'b0000000... | 6.599169 |
module PriorityEncoder_16 (
input [15:0] data_i,
output [ 3:0] code_o
);
wire [7:0] tmp0;
assign tmp0 = {
data_i[15], data_i[13], data_i[11], data_i[9], data_i[7], data_i[5], data_i[3], data_i[1]
};
OR_tree code0 (
tmp0,
code_o[0]
);
wire [7:0] tmp1;
assign tmp1 = {
data_i[1... | 6.599169 |
module OR_tree (
input [7:0] data_i,
output data_o
);
wire [3:0] tmp1;
wire [1:0] tmp2;
assign tmp1 = data_i[3:0] | data_i[7:4];
assign tmp2 = tmp1[1:0] | tmp1[3:2];
assign data_o = tmp2[0] | tmp2[1];
endmodule
| 7.726839 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module LOD16 (
input [15:0] data_i,
output zero_o,
output [15:0] data_o
);
wire [15:0] z;
wire [ 3:0] select;
wire [ 3:0] zdet;
//*****************************************
// Zero detection logic:
//*****************************************
assign zdet[3] = data_i[15] | data_i[14] | data_i... | 7.892753 |
module Barrel16L (
input [15:0] data_i,
input [ 3:0] shift_i,
output [ 5:0] data_o
);
reg [15:0] tmp;
always @*
case (shift_i)
4'b0000: tmp = data_i;
4'b0001: tmp = data_i << 1;
4'b0010: tmp = data_i << 2;
4'b0011: tmp = data_i << 3;
4'b0100: tmp = data_i << 4;
... | 7.500498 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.