code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
);
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module Nand3 (
a,
b,
c,
o
);
output o;
input a, b, c;
wire x, y;
AndGate A (
a,
b,
x
);
AndGate B (
x,
c,
y
);
NotGate C (
y,
o
);
endmodule
| 6.937178 |
module DFlipFlopFEAResetHigh (
d,
c,
q,
q_,
re
);
output q, q_;
input d, c, re;
wire re_, Q, Q_;
NotGate R (
re,
re_
);
NotGate N (
c,
c_
);
DLatchWR D1 (
d,
c,
Q,
Q_,
re_
);
DLatchWR D2 (
Q,
c_,
q,
... | 6.5896 |
module StimDFlipFlopFEAResetHigh;
wire q, q_;
reg d, c, re;
DFlipFlopFEAResetHigh D (
d,
c,
q,
q_,
re
);
initial begin
c = 1'b1;
end
always begin
c = ~c;
#3;
end
initial begin
d = 1'b0;
re = 1'b0;
#10;
d = 1'b1;
#5;
re = 1'b1;
... | 6.622517 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
);
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module Nand3 (
a,
b,
c,
o
);
output o;
input a, b, c;
wire x, y;
AndGate A (
a,
b,
x
);
AndGate B (
x,
c,
y
);
NotGate C (
y,
o
);
endmodule
| 6.937178 |
module DFlipFlopFEAResetLow (
d,
c,
q,
q_,
re
);
output q, q_;
input d, c, re;
wire Q, Q_, c_;
nand (c_, c, c);
DLatchWR D1 (
d,
c,
Q,
Q_,
re
);
DLatchWR D2 (
Q,
c_,
q,
q_,
re
);
endmodule
| 6.5896 |
module StimDFlipFlopFEAResetLow;
wire q, q_;
reg d, c, re;
DFlipFlopFEAResetLow D (
d,
c,
q,
q_,
re
);
initial begin
c = 1'b1;
end
always begin
c = ~c;
#3;
end
initial begin
d = 1'b0;
re = 1'b0;
#10;
d = 1'b1;
#5;
re = 1'b1;
#... | 6.622517 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
);
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module DLatch (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, s, r, x, y;
AndGate S (
d,
d,
s
);
NotGate R (
d,
r
);
nand (x, c, s);
nand (y, c, r);
nand (q, q_, x);
nand (q_, q, y);
endmodule
| 6.957096 |
module DFlipFlopRE (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, Q, Q_;
NotGate C_ (
c,
c_
);
DLatch D1 (
d,
c_,
Q,
Q_
);
DLatch D2 (
Q,
c,
q,
q_
);
endmodule
| 7.021098 |
module StimBinaryCell;
wire DOut;
reg DIn, clk, cs, w, r;
BinaryCell B (
DIn,
clk,
cs,
w,
r,
DOut
);
initial begin
clk = 1'b1;
end
always begin
clk = ~clk;
#3;
end
initial begin
DIn = 1'b0;
cs = 1'b0;
w = 1'b0;
r = 1'b0;
#5;... | 6.597052 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
);
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module DLatch (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, s, r, x, y;
AndGate S (
d,
d,
s
);
NotGate R (
d,
r
);
nand (x, c, s);
nand (y, c, r);
nand (q, q_, x);
nand (q_, q, y);
endmodule
| 6.957096 |
module DFlipFlopRE (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, Q, Q_;
NotGate C_ (
c,
c_
);
DLatch D1 (
d,
c_,
Q,
Q_
);
DLatch D2 (
Q,
c,
q,
q_
);
endmodule
| 7.021098 |
module Reg16Bit (
DIn,
clk,
cs,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, cs, w, r;
BinaryCell B[15:0] (
DIn,
clk,
cs,
w,
r,
DOut
);
endmodule
| 8.10144 |
module StimReg;
wire [15:0] DOut;
reg [15:0] DIn;
reg clk, cs, w, r;
Reg16Bit B (
DIn,
clk,
cs,
w,
r,
DOut
);
initial begin
clk = 1'b1;
end
always begin
clk = ~clk;
#3;
end
initial begin
DIn = 1465;
cs = 1'b0;
w = 1'b0;
r = 1... | 7.427378 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
);
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module DLatch (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, s, r, x, y;
AndGate S (
d,
d,
s
);
NotGate R (
d,
r
);
nand (x, c, s);
nand (y, c, r);
nand (q, q_, x);
nand (q_, q, y);
endmodule
| 6.957096 |
module DFlipFlopRE (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, Q, Q_;
NotGate C_ (
c,
c_
);
DLatch D1 (
d,
c_,
Q,
Q_
);
DLatch D2 (
Q,
c,
q,
q_
);
endmodule
| 7.021098 |
module Reg16Bit (
DIn,
clk,
cs,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, cs, w, r;
BinaryCell B[15:0] (
DIn,
clk,
cs,
w,
r,
DOut
);
endmodule
| 8.10144 |
module DeCoder2 (
e,
i,
o
);
output [1:0] o;
input e, i;
wire i_;
NotGate Ne (
i,
i_
);
AndGate O1 (
i_,
e,
o[0]
);
AndGate O2 (
i,
e,
o[1]
);
endmodule
| 7.055917 |
module DeCoder4 (
e,
i,
o
);
output [3:0] o;
input [1:0] i;
input e;
wire [1:0] t;
DeCoder2 D1 (
e,
i[1],
t[1:0]
);
DeCoder2 D2 (
t[1],
i[0],
o[3:2]
);
DeCoder2 D3 (
t[0],
i[0],
o[1:0]
);
endmodule
| 7.437067 |
module DeCoder8 (
e,
i,
o
);
output [7:0] o;
input [2:0] i;
input e;
wire [1:0] t;
DeCoder2 D1 (
e,
i[2],
t[1:0]
);
DeCoder4 D2 (
t[0],
i[1:0],
o[3:0]
);
DeCoder4 D3 (
t[1],
i[1:0],
o[7:4]
);
endmodule
| 7.495716 |
module Mux4x1 (
i0,
i1,
i2,
i3,
s1,
s0,
o
);
output o;
input i0, i1, i2, i3;
input s1, s0;
wire x, y;
Mux2x1 M_1 (
i0,
i1,
s1,
x
);
Mux2x1 M_2 (
i2,
i3,
s1,
y
);
Mux2x1 M_3 (
x,
y,
s0,
o
);
endmodu... | 8.038083 |
module Mux4x1_16 (
i0,
i1,
i2,
i3,
s,
o
);
output [15:0] o;
input [15:0] i0, i1, i2, i3;
input [1:0] s;
Mux4x1 M[15:0] (
i0,
i1,
i2,
i3,
s[0],
s[1],
o
);
endmodule
| 7.425005 |
module Mux8x1 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s0,
s1,
s2,
o
);
output o;
input i1, i2, i3, i4, i5, i6, i7, i8;
input s2, s1, s0;
wire x, y;
Mux4x1 M1 (
i1,
i2,
i3,
i4,
s0,
s1,
x
);
Mux4x1 M2 (
i5,
i6,... | 7.627269 |
module Mux8x1_16 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s,
o
);
output [15:0] o;
input [15:0] i1, i2, i3, i4, i5, i6, i7, i8;
input [2:0] s;
Mux8x1 M[15:0] (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s[0],
s[1],
s[2],
... | 8.13978 |
module RAM8 (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [2:0] addr;
wire [7:0] cs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 Addr (
e,
addr,
cs
);
Reg16Bit r1 (
DIn,
clk,
... | 6.996489 |
module StimRAM8;
wire [15:0] DOut;
reg [15:0] DIn;
reg e, clk, w, r;
reg [2:0] addr;
RAM8 R (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
initial begin
e = 1'b1;
clk = 1'b1;
end
always begin
clk = ~clk;
#3;
end
initial begin
DIn = 1;
a... | 6.604164 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
);
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module DLatch (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, s, r, x, y;
AndGate S (
d,
d,
s
);
NotGate R (
d,
r
);
nand (x, c, s);
nand (y, c, r);
nand (q, q_, x);
nand (q_, q, y);
endmodule
| 6.957096 |
module DFlipFlopRE (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, Q, Q_;
NotGate C_ (
c,
c_
);
DLatch D1 (
d,
c_,
Q,
Q_
);
DLatch D2 (
Q,
c,
q,
q_
);
endmodule
| 7.021098 |
module Reg16Bit (
DIn,
clk,
cs,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, cs, w, r;
BinaryCell B[15:0] (
DIn,
clk,
cs,
w,
r,
DOut
);
endmodule
| 8.10144 |
module DeCoder2 (
e,
i,
o
);
output [1:0] o;
input e, i;
wire i_;
NotGate Ne (
i,
i_
);
AndGate O1 (
i_,
e,
o[0]
);
AndGate O2 (
i,
e,
o[1]
);
endmodule
| 7.055917 |
module DeCoder4 (
e,
i,
o
);
output [3:0] o;
input [1:0] i;
input e;
wire [1:0] t;
DeCoder2 D1 (
e,
i[1],
t[1:0]
);
DeCoder2 D2 (
t[1],
i[0],
o[3:2]
);
DeCoder2 D3 (
t[0],
i[0],
o[1:0]
);
endmodule
| 7.437067 |
module DeCoder8 (
e,
i,
o
);
output [7:0] o;
input [2:0] i;
input e;
wire [1:0] t;
DeCoder2 D1 (
e,
i[2],
t[1:0]
);
DeCoder4 D2 (
t[0],
i[1:0],
o[3:0]
);
DeCoder4 D3 (
t[1],
i[1:0],
o[7:4]
);
endmodule
| 7.495716 |
module Mux4x1 (
i0,
i1,
i2,
i3,
s1,
s0,
o
);
output o;
input i0, i1, i2, i3;
input s1, s0;
wire x, y;
Mux2x1 M_1 (
i0,
i1,
s1,
x
);
Mux2x1 M_2 (
i2,
i3,
s1,
y
);
Mux2x1 M_3 (
x,
y,
s0,
o
);
endmodu... | 8.038083 |
module Mux4x1_16 (
i0,
i1,
i2,
i3,
s,
o
);
output [15:0] o;
input [15:0] i0, i1, i2, i3;
input [1:0] s;
Mux4x1 M[15:0] (
i0,
i1,
i2,
i3,
s[0],
s[1],
o
);
endmodule
| 7.425005 |
module Mux8x1 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s0,
s1,
s2,
o
);
output o;
input i1, i2, i3, i4, i5, i6, i7, i8;
input s2, s1, s0;
wire x, y;
Mux4x1 M1 (
i1,
i2,
i3,
i4,
s0,
s1,
x
);
Mux4x1 M2 (
i5,
i6,... | 7.627269 |
module Mux8x1_16 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s,
o
);
output [15:0] o;
input [15:0] i1, i2, i3, i4, i5, i6, i7, i8;
input [2:0] s;
Mux8x1 M[15:0] (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s[0],
s[1],
s[2],
... | 8.13978 |
module RAM8 (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [2:0] addr;
wire [7:0] cs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 Addr (
e,
addr,
cs
);
Reg16Bit r1 (
DIn,
clk,
... | 6.996489 |
module RAM64 (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [5:0] addr;
wire [7:0] rs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 RAddr (
e,
addr[5:3],
rs
);
RAM8 R1 (
rs[0],
DIn,
... | 6.898444 |
module StimRAM64;
wire [15:0] DOut;
reg [15:0] DIn;
reg e, clk, w, r;
reg [5:0] addr;
integer i;
RAM64 R (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
initial begin
e = 1'b1;
clk = 1'b1;
end
always begin
clk = ~clk;
#3;
end
initial begin
... | 6.628263 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
);
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module DLatch (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, s, r, x, y;
AndGate S (
d,
d,
s
);
NotGate R (
d,
r
);
nand (x, c, s);
nand (y, c, r);
nand (q, q_, x);
nand (q_, q, y);
endmodule
| 6.957096 |
module DFlipFlopRE (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, Q, Q_;
NotGate C_ (
c,
c_
);
DLatch D1 (
d,
c_,
Q,
Q_
);
DLatch D2 (
Q,
c,
q,
q_
);
endmodule
| 7.021098 |
module Reg16Bit (
DIn,
clk,
cs,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, cs, w, r;
BinaryCell B[15:0] (
DIn,
clk,
cs,
w,
r,
DOut
);
endmodule
| 8.10144 |
module DeCoder2 (
e,
i,
o
);
output [1:0] o;
input e, i;
wire i_;
NotGate Ne (
i,
i_
);
AndGate O1 (
i_,
e,
o[0]
);
AndGate O2 (
i,
e,
o[1]
);
endmodule
| 7.055917 |
module DeCoder4 (
e,
i,
o
);
output [3:0] o;
input [1:0] i;
input e;
wire [1:0] t;
DeCoder2 D1 (
e,
i[1],
t[1:0]
);
DeCoder2 D2 (
t[1],
i[0],
o[3:2]
);
DeCoder2 D3 (
t[0],
i[0],
o[1:0]
);
endmodule
| 7.437067 |
module DeCoder8 (
e,
i,
o
);
output [7:0] o;
input [2:0] i;
input e;
wire [1:0] t;
DeCoder2 D1 (
e,
i[2],
t[1:0]
);
DeCoder4 D2 (
t[0],
i[1:0],
o[3:0]
);
DeCoder4 D3 (
t[1],
i[1:0],
o[7:4]
);
endmodule
| 7.495716 |
module Mux4x1 (
i0,
i1,
i2,
i3,
s1,
s0,
o
);
output o;
input i0, i1, i2, i3;
input s1, s0;
wire x, y;
Mux2x1 M_1 (
i0,
i1,
s1,
x
);
Mux2x1 M_2 (
i2,
i3,
s1,
y
);
Mux2x1 M_3 (
x,
y,
s0,
o
);
endmodu... | 8.038083 |
module Mux4x1_16 (
i0,
i1,
i2,
i3,
s,
o
);
output [15:0] o;
input [15:0] i0, i1, i2, i3;
input [1:0] s;
Mux4x1 M[15:0] (
i0,
i1,
i2,
i3,
s[0],
s[1],
o
);
endmodule
| 7.425005 |
module Mux8x1 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s0,
s1,
s2,
o
);
output o;
input i1, i2, i3, i4, i5, i6, i7, i8;
input s2, s1, s0;
wire x, y;
Mux4x1 M1 (
i1,
i2,
i3,
i4,
s0,
s1,
x
);
Mux4x1 M2 (
i5,
i6,... | 7.627269 |
module Mux8x1_16 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s,
o
);
output [15:0] o;
input [15:0] i1, i2, i3, i4, i5, i6, i7, i8;
input [2:0] s;
Mux8x1 M[15:0] (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s[0],
s[1],
s[2],
... | 8.13978 |
module RAM8 (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [2:0] addr;
wire [7:0] cs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 Addr (
e,
addr,
cs
);
Reg16Bit r1 (
DIn,
clk,
... | 6.996489 |
module RAM64 (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [5:0] addr;
wire [7:0] rs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 RAddr (
e,
addr[5:3],
rs
);
RAM8 R1 (
rs[0],
DIn,
... | 6.898444 |
module RAM512 (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [8:0] addr;
wire [7:0] rs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 RAddr (
e,
addr[8:6],
rs
);
RAM64 R1 (
rs[0],
DIn... | 6.993289 |
module StimRAM512;
wire [15:0] DOut;
reg [15:0] DIn;
reg e, clk, w, r;
reg [8:0] addr;
integer i;
RAM512 R (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
initial begin
e = 1'b1;
clk = 1'b1;
end
always begin
clk = ~clk;
#3;
end
initial begin
... | 6.636479 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
);
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module DLatch (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, s, r, x, y;
AndGate S (
d,
d,
s
);
NotGate R (
d,
r
);
nand (x, c, s);
nand (y, c, r);
nand (q, q_, x);
nand (q_, q, y);
endmodule
| 6.957096 |
module DFlipFlopRE (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, Q, Q_;
NotGate C_ (
c,
c_
);
DLatch D1 (
d,
c_,
Q,
Q_
);
DLatch D2 (
Q,
c,
q,
q_
);
endmodule
| 7.021098 |
module Reg16Bit (
DIn,
clk,
cs,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, cs, w, r;
BinaryCell B[15:0] (
DIn,
clk,
cs,
w,
r,
DOut
);
endmodule
| 8.10144 |
module DeCoder2 (
e,
i,
o
);
output [1:0] o;
input e, i;
wire i_;
NotGate Ne (
i,
i_
);
AndGate O1 (
i_,
e,
o[0]
);
AndGate O2 (
i,
e,
o[1]
);
endmodule
| 7.055917 |
module DeCoder4 (
e,
i,
o
);
output [3:0] o;
input [1:0] i;
input e;
wire [1:0] t;
DeCoder2 D1 (
e,
i[1],
t[1:0]
);
DeCoder2 D2 (
t[1],
i[0],
o[3:2]
);
DeCoder2 D3 (
t[0],
i[0],
o[1:0]
);
endmodule
| 7.437067 |
module DeCoder8 (
e,
i,
o
);
output [7:0] o;
input [2:0] i;
input e;
wire [1:0] t;
DeCoder2 D1 (
e,
i[2],
t[1:0]
);
DeCoder4 D2 (
t[0],
i[1:0],
o[3:0]
);
DeCoder4 D3 (
t[1],
i[1:0],
o[7:4]
);
endmodule
| 7.495716 |
module Mux4x1 (
i0,
i1,
i2,
i3,
s1,
s0,
o
);
output o;
input i0, i1, i2, i3;
input s1, s0;
wire x, y;
Mux2x1 M_1 (
i0,
i1,
s1,
x
);
Mux2x1 M_2 (
i2,
i3,
s1,
y
);
Mux2x1 M_3 (
x,
y,
s0,
o
);
endmodu... | 8.038083 |
module Mux4x1_16 (
i0,
i1,
i2,
i3,
s,
o
);
output [15:0] o;
input [15:0] i0, i1, i2, i3;
input [1:0] s;
Mux4x1 M[15:0] (
i0,
i1,
i2,
i3,
s[0],
s[1],
o
);
endmodule
| 7.425005 |
module Mux8x1 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s0,
s1,
s2,
o
);
output o;
input i1, i2, i3, i4, i5, i6, i7, i8;
input s2, s1, s0;
wire x, y;
Mux4x1 M1 (
i1,
i2,
i3,
i4,
s0,
s1,
x
);
Mux4x1 M2 (
i5,
i6,... | 7.627269 |
module Mux8x1_16 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s,
o
);
output [15:0] o;
input [15:0] i1, i2, i3, i4, i5, i6, i7, i8;
input [2:0] s;
Mux8x1 M[15:0] (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s[0],
s[1],
s[2],
... | 8.13978 |
module RAM8 (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [2:0] addr;
wire [7:0] cs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 Addr (
e,
addr,
cs
);
Reg16Bit r1 (
DIn,
clk,
... | 6.996489 |
module RAM64 (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [5:0] addr;
wire [7:0] rs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 RAddr (
e,
addr[5:3],
rs
);
RAM8 R1 (
rs[0],
DIn,
... | 6.898444 |
module RAM512 (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [8:0] addr;
wire [7:0] rs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 RAddr (
e,
addr[8:6],
rs
);
RAM64 R1 (
rs[0],
DIn... | 6.993289 |
module RAM4K (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [11:0] addr;
wire [7:0] rs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 RAddr (
e,
addr[11:9],
rs
);
RAM512 R1 (
rs[0],
D... | 6.685573 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.