code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Mux8x1 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s0,
s1,
s2,
o
); // 16
output o;
input i1, i2, i3, i4, i5, i6, i7, i8;
input s2, s1, s0;
wire x, y;
Mux4x1 M1 (
i1,
i2,
i3,
i4,
s0,
s1,
x
);
Mux4x1 M2 (
i5,
i6,
i7,
i8,
s0,
s1,
y
);
Mux2x1 M3 (
x,
y,
s2,
o
);
endmodule
| 7.627269 |
module Mux8x1_16 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s,
o
);
output [15:0] o;
input [15:0] i1, i2, i3, i4, i5, i6, i7, i8;
input [2:0] s;
Mux8x1 M[15:0] (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s[0],
s[1],
s[2],
o
);
endmodule
| 8.13978 |
module Sim16Mux8x1; // 15
wire [15:0] o;
reg [15:0] i0, i1, i2, i3, i4, i5, i6, i7;
reg [2:0] s;
Mux8x1_16 M (
i0,
i1,
i2,
i3,
i4,
i5,
i6,
i7,
s,
o
);
initial begin
i0 = 6234;
i1 = 725;
i2 = 7524;
i3 = 5734;
i4 = 8354;
i5 = 28457;
i6 = 2458;
i7 = 2547;
s = 0;
#100;
s = 1;
#100;
s = 2;
#100;
s = 3;
#100;
s = 4;
#100;
s = 5;
#100;
s = 6;
#100;
s = 7;
#100;
i0 = 384;
i1 = 398;
i2 = 9337;
i3 = 9353;
i4 = 2457;
i5 = 8542;
i6 = 3659;
i7 = 2854;
s = 0;
#100;
s = 1;
#100;
s = 2;
#100;
s = 3;
#100;
s = 4;
#100;
s = 5;
#100;
s = 6;
#100;
s = 7;
#100;
i0 = 65535;
i1 = 274;
i2 = 8224;
i3 = 2457;
i4 = 953;
i5 = 356;
i6 = 82;
i7 = 2485;
s = 0;
#100;
s = 1;
#100;
s = 2;
#100;
s = 3;
#100;
s = 4;
#100;
s = 5;
#100;
s = 6;
#100;
s = 7;
#100;
i0 = 136;
i1 = 8564;
i2 = 24377;
i3 = 3548;
i4 = 428;
i5 = 953;
i6 = 9336;
i7 = 524;
s = 0;
#100;
s = 1;
#100;
s = 2;
#100;
s = 3;
#100;
s = 4;
#100;
s = 5;
#100;
s = 6;
#100;
s = 7;
#100;
i0 = 5483;
i1 = 3485;
i2 = 3658;
i3 = 3659;
i4 = 572;
i5 = 54287;
i6 = 8542;
i7 = 57;
s = 0;
#100;
s = 1;
#100;
s = 2;
#100;
s = 3;
#100;
s = 4;
#100;
s = 5;
#100;
s = 6;
#100;
s = 7;
#100;
i0 = 9;
i1 = 39539;
i2 = 54;
i3 = 4845;
i4 = 4258;
i5 = 175;
i6 = 35487;
i7 = 287;
s = 0;
#100;
s = 1;
#100;
s = 2;
#100;
s = 3;
#100;
s = 4;
#100;
s = 5;
#100;
s = 6;
#100;
s = 7;
#100;
i0 = 54;
i1 = 4607;
i2 = 40;
i3 = 749;
i4 = 248;
i5 = 5482;
i6 = 8642;
i7 = 9333;
s = 0;
#100;
s = 1;
#100;
s = 2;
#100;
s = 3;
#100;
s = 4;
#100;
s = 5;
#100;
s = 6;
#100;
s = 7;
#100;
i0 = 46;
i1 = 9;
i2 = 4;
i3 = 4076;
i4 = 2458;
i5 = 5724;
i6 = 2548;
i7 = 9635;
s = 0;
#100;
s = 1;
#100;
s = 2;
#100;
s = 3;
#100;
s = 4;
#100;
s = 5;
#100;
s = 6;
#100;
s = 7;
#100;
i0 = 40;
i1 = 459;
i2 = 55875;
i3 = 3856;
i4 = 3648;
i5 = 836;
i6 = 39;
i7 = 0;
s = 0;
#100;
s = 1;
#100;
s = 2;
#100;
s = 3;
#100;
s = 4;
#100;
s = 5;
#100;
s = 6;
#100;
s = 7;
#100;
i0 = 83;
i1 = 8345;
i2 = 86;
i3 = 465;
i4 = 0;
i5 = 685;
i6 = 836;
i7 = 863;
s = 0;
#100;
s = 1;
#100;
s = 2;
#100;
s = 3;
#100;
s = 4;
#100;
s = 5;
#100;
s = 6;
#100;
s = 7;
#100;
end
endmodule
| 6.960736 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module DMux1x4 (
o,
s,
i0,
i1,
i2,
i3
); // 17
output i0, i1, i2, i3;
input o;
input [1:0] s;
wire a, b;
DMux1x2 D_0 (
o,
s[1],
a,
b
);
DMux1x2 D_1 (
a,
s[0],
i0,
i1
);
DMux1x2 D_2 (
b,
s[0],
i2,
i3
);
endmodule
| 6.513796 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module DMux1x4 (
o,
s,
i0,
i1,
i2,
i3
); // 17
output i0, i1, i2, i3;
input o;
input [1:0] s;
wire a, b;
DMux1x2 D_0 (
o,
s[1],
a,
b
);
DMux1x2 D_1 (
a,
s[0],
i0,
i1
);
DMux1x2 D_2 (
b,
s[0],
i2,
i3
);
endmodule
| 6.513796 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module XorGate (
a,
b,
c
);
output c;
input a, b;
wire a_, b_, x, y;
NotGate Na (
a,
a_
);
NotGate Nb (
b,
b_
);
AndGate A1 (
a,
b_,
x
);
AndGate A2 (
a_,
b,
y
);
OrGate O (
x,
y,
c
);
endmodule
| 7.413558 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module XorGate (
a,
b,
c
);
output c;
input a, b;
wire a_, b_, x, y;
NotGate Na (
a,
a_
);
NotGate Nb (
b,
b_
);
AndGate A1 (
a,
b_,
x
);
AndGate A2 (
a_,
b,
y
);
OrGate O (
x,
y,
c
);
endmodule
| 7.413558 |
module FullAdder (
a,
b,
c0,
s,
c
);
output s, c;
input a, b, c0;
wire c_, x, x_, y, y_;
NotGate N (
c0,
c_
);
XorGate X1 (
a,
b,
x
);
XnorGate X2 (
a,
b,
x_
);
AndGate A (
a,
b,
y
);
OrGate O (
a,
b,
y_
);
AndGate As1 (
x,
c_,
s1
);
AndGate As2 (
x_,
c0,
s2
);
AndGate Ac1 (
y,
c_,
c1
);
AndGate Ac2 (
y_,
c0,
c2
);
OrGate S (
s1,
s2,
s
);
OrGate C (
c1,
c2,
c
);
endmodule
| 7.610141 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module XorGate (
a,
b,
c
);
output c;
input a, b;
wire a_, b_, x, y;
NotGate Na (
a,
a_
);
NotGate Nb (
b,
b_
);
AndGate A1 (
a,
b_,
x
);
AndGate A2 (
a_,
b,
y
);
OrGate O (
x,
y,
c
);
endmodule
| 7.413558 |
module Inc4Bit (
a,
b
);
output [3:0] b;
input [3:0] a;
wire [3:0] c;
HalfAdder H1 (
a[0],
1'b1,
b[0],
c[0]
);
HalfAdder H2 (
a[1],
c[0],
b[1],
c[1]
);
HalfAdder H3 (
a[2],
c[1],
b[2],
c[2]
);
HalfAdder H4 (
a[3],
c[2],
b[3],
c[3]
);
endmodule
| 6.658624 |
module StimInc4Bit;
wire [3:0] o;
reg [3:0] a;
integer i;
Inc4Bit IOut (
a,
o
);
initial begin
for (i = 0; i < 16; i = i + 1) begin
a = i;
#10;
end
end
endmodule
| 7.062436 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module XorGate (
a,
b,
c
);
output c;
input a, b;
wire a_, b_, x, y;
NotGate Na (
a,
a_
);
NotGate Nb (
b,
b_
);
AndGate A1 (
a,
b_,
x
);
AndGate A2 (
a_,
b,
y
);
OrGate O (
x,
y,
c
);
endmodule
| 7.413558 |
module Add4Bit (
a,
b,
s
);
output [3:0] s;
input [3:0] a, b;
wire [3:0] c;
FullAdder F1 (
a[0],
b[0],
1'b0,
s[0],
c[0]
);
FullAdder F2 (
a[1],
b[1],
c[0],
s[1],
c[1]
);
FullAdder F3 (
a[2],
b[2],
c[1],
s[2],
c[2]
);
FullAdder F4 (
a[3],
b[3],
c[2],
s[3],
c[3]
);
endmodule
| 7.402276 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module XorGate (
a,
b,
c
);
output c;
input a, b;
wire a_, b_, x, y;
NotGate Na (
a,
a_
);
NotGate Nb (
b,
b_
);
AndGate A1 (
a,
b_,
x
);
AndGate A2 (
a_,
b,
y
);
OrGate O (
x,
y,
c
);
endmodule
| 7.413558 |
module FullAdder (
a,
b,
c0,
s,
c
);
output s, c;
input a, b, c0;
wire c_, x, x_, y, y_;
NotGate N (
c0,
c_
);
XorGate X1 (
a,
b,
x
);
XnorGate X2 (
a,
b,
x_
);
AndGate A (
a,
b,
y
);
OrGate O (
a,
b,
y_
);
AndGate As1 (
x,
c_,
s1
);
AndGate As2 (
x_,
c0,
s2
);
AndGate Ac1 (
y,
c_,
c1
);
AndGate Ac2 (
y_,
c0,
c2
);
OrGate S (
s1,
s2,
s
);
OrGate C (
c1,
c2,
c
);
endmodule
| 7.610141 |
module StimAdd16Bit;
wire [15:0] o;
reg [15:0] a, b;
Add16Bit A (
a,
b,
o
);
initial begin
a = 15;
b = 15;
#10;
a = 15;
b = 0;
#10;
a = 0;
b = 15;
#10;
a = 0;
b = 0;
#10;
a = 962;
b = 626;
#10;
a = 936;
b = 772;
#10;
a = 485;
b = 727;
#10;
a = 836;
b = 753;
#10;
end
endmodule
| 7.115883 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module XorGate (
a,
b,
c
);
output c;
input a, b;
wire a_, b_, x, y;
NotGate Na (
a,
a_
);
NotGate Nb (
b,
b_
);
AndGate A1 (
a,
b_,
x
);
AndGate A2 (
a_,
b,
y
);
OrGate O (
x,
y,
c
);
endmodule
| 7.413558 |
module StimInc16Bit;
wire [15:0] o;
reg [15:0] a;
integer i;
Inc16Bit IOut (
a,
o
);
initial begin
for (i = 0; i < 65535; i = i + 1051) begin
a = i;
#10;
end
end
endmodule
| 7.145358 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module Neg16 (
a,
b
);
output [15:0] b;
input [15:0] a;
NotGate N[15:0] (
a,
b
);
endmodule
| 7.562441 |
module StimNeg16;
wire [15:0] o;
reg [15:0] a;
Neg16 N (
a,
o
);
initial begin
a = 151;
#10;
a = 1251;
#10;
a = 38563;
#10;
a = 47251;
#10;
a = 12845;
#10;
a = 8221;
#10;
a = 3732;
#10;
a = 1754;
#10;
end
endmodule
| 6.955027 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module XorGate (
a,
b,
c
);
output c;
input a, b;
wire a_, b_, x, y;
NotGate Na (
a,
a_
);
NotGate Nb (
b,
b_
);
AndGate A1 (
a,
b_,
x
);
AndGate A2 (
a_,
b,
y
);
OrGate O (
x,
y,
c
);
endmodule
| 7.413558 |
module FullAdder (
a,
b,
c0,
s,
c
);
output s, c;
input a, b, c0;
wire c_, x, x_, y, y_;
NotGate N (
c0,
c_
);
XorGate X1 (
a,
b,
x
);
XnorGate X2 (
a,
b,
x_
);
AndGate A (
a,
b,
y
);
OrGate O (
a,
b,
y_
);
AndGate As1 (
x,
c_,
s1
);
AndGate As2 (
x_,
c0,
s2
);
AndGate Ac1 (
y,
c_,
c1
);
AndGate Ac2 (
y_,
c0,
c2
);
OrGate S (
s1,
s2,
s
);
OrGate C (
c1,
c2,
c
);
endmodule
| 7.610141 |
module Neg16 (
a,
b
);
output [15:0] b;
input [15:0] a;
NotGate N[15:0] (
a,
b
);
endmodule
| 7.562441 |
module Mux2x1 (
a,
b,
s,
o
);
output o;
input a, b, s;
wire s_, x, y;
NotGate Ns (
s,
s_
);
AndGate Aa (
s_,
a,
x
);
AndGate Ab (
s,
b,
y
);
OrGate O (
x,
y,
o
);
endmodule
| 6.963017 |
module AndGate16w1 (
a,
b,
c
);
output [15:0] c;
input [15:0] a;
input b;
AndGate A[15:0] (
a,
b,
c
);
endmodule
| 6.537312 |
module AndGate16 (
a,
b,
c
);
output [15:0] c;
input [15:0] a, b;
AndGate A[15:0] (
a,
b,
c
);
endmodule
| 7.226935 |
module ALU (
x,
y,
zx,
nx,
zy,
ny,
f,
no,
zr,
ng,
o
);
output [15:0] o;
output zr, ng;
input [15:0] x, y;
input zx, nx, zy, ny, f, no;
wire [15:0] xz, yz, xn, yn, sm, an, to;
wire zx_, zy_;
NotGate Nnx (
zx,
zx_
);
NotGate Nny (
zy,
zy_
);
AndGate16w1 Zx (
x,
zx_,
xz
);
AndGate16w1 Zy (
y,
zy_,
yz
);
XorGate16w1 Nx (
xz,
nx,
xn
);
XorGate16w1 Ny (
yz,
ny,
yn
);
Add16Bit Asm (
xn,
yn,
sm
);
AndGate16 Aan (
xn,
yn,
an
);
Mux16b2x1 Fout (
an,
sm,
f,
to
);
XorGate16w1 No (
to,
no,
o
);
AndGate Ang (
o[15],
o[15],
ng
);
Nor16In Nzr (
o,
zr
);
endmodule
| 7.195527 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
);
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module DLatch (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, s, r, x, y;
AndGate S (
d,
d,
s
);
NotGate R (
d,
r
);
nand (x, c, s);
nand (y, c, r);
nand (q, q_, x);
nand (q_, q, y);
endmodule
| 6.957096 |
module DFlipFlopRE (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, Q, Q_;
NotGate C_ (
c,
c_
);
DLatch D1 (
d,
c_,
Q,
Q_
);
DLatch D2 (
Q,
c,
q,
q_
);
endmodule
| 7.021098 |
module StimDFlipFlopRE;
wire q, q_;
reg d, c;
DFlipFlopRE D (
d,
c,
q,
q_
);
initial begin
c = 1'b1;
end
always begin
c = ~c;
#3;
end
initial begin
d = 1'b0;
#10;
d = 1'b1;
#10;
d = 1'b0;
#10;
d = 1'b1;
#10;
end
endmodule
| 6.622517 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
);
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module DLatch (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, s, r, x, y;
AndGate S (
d,
d,
s
);
NotGate R (
d,
r
);
nand (x, c, s);
nand (y, c, r);
nand (q, q_, x);
nand (q_, q, y);
endmodule
| 6.957096 |
module DFlipFlopRE (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, Q, Q_;
NotGate C_ (
c,
c_
);
DLatch D1 (
d,
c_,
Q,
Q_
);
DLatch D2 (
Q,
c,
q,
q_
);
endmodule
| 7.021098 |
module DFlipFlopRESReset (
d,
c,
q,
q_,
re
);
output q, q_;
input d, c, re;
wire re_, d_;
NotGate Re (
re,
re_
);
AndGate A (
d,
re_,
d_
);
DFlipFlopRE Df (
d_,
c,
q,
q_
);
endmodule
| 7.095347 |
module StimDFlipFlopRESReset;
wire q, q_;
reg d, c, re;
DFlipFlopRESReset D (
d,
c,
q,
q_,
re
);
initial begin
c = 1'b1;
end
always begin
c = ~c;
#3;
end
initial begin
d = 1'b0;
re = 1'b0;
#10;
d = 1'b1;
#5;
re = 1'b1;
#5;
re = 1'b0;
d = 1'b0;
#10;
d = 1'b1;
#5;
re = 1'b1;
#5;
end
endmodule
| 6.622517 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
);
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module Nand3 (
a,
b,
c,
o
);
output o;
input a, b, c;
wire x, y;
AndGate A (
a,
b,
x
);
AndGate B (
x,
c,
y
);
NotGate C (
y,
o
);
endmodule
| 6.937178 |
module DFlipFlopAResetHigh (
d,
c,
q,
q_,
re
);
output q, q_;
input d, c, re;
wire re_, Q, Q_;
NotGate R (
re,
re_
);
NotGate N (
c,
c_
);
DLatchWR D1 (
d,
c_,
Q,
Q_,
re_
);
DLatchWR D2 (
Q,
c,
q,
q_,
re_
);
endmodule
| 6.608996 |
module StimDFlipFlopAResetHigh;
wire q, q_;
reg d, c, re;
DFlipFlopAResetHigh D (
d,
c,
q,
q_,
re
);
initial begin
c = 1'b1;
end
always begin
c = ~c;
#3;
end
initial begin
d = 1'b0;
re = 1'b0;
#10;
d = 1'b1;
#5;
re = 1'b1;
#5;
re = 1'b0;
d = 1'b0;
#10;
d = 1'b1;
#5;
re = 1'b1;
#5;
end
endmodule
| 6.622517 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
);
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module Nand3 (
a,
b,
c,
o
);
output o;
input a, b, c;
wire x, y;
AndGate A (
a,
b,
x
);
AndGate B (
x,
c,
y
);
NotGate C (
y,
o
);
endmodule
| 6.937178 |
module DFlipFlopAResetLow (
d,
c,
q,
q_,
re
);
output q, q_;
input d, c, re;
wire Q, Q_, c_;
nand (c_, c, c);
DLatchWR D1 (
d,
c_,
Q,
Q_,
re
);
DLatchWR D2 (
Q,
c,
q,
q_,
re
);
endmodule
| 6.608996 |
module StimDFlipFlopAResetLow;
wire q, q_;
reg d, c, re;
DFlipFlopAResetLow D (
d,
c,
q,
q_,
re
);
initial begin
c = 1'b1;
end
always begin
c = ~c;
#3;
end
initial begin
d = 1'b0;
re = 1'b0;
#10;
d = 1'b1;
#5;
re = 1'b1;
#5;
re = 1'b0;
d = 1'b0;
#10;
d = 1'b1;
#5;
re = 1'b1;
#5;
end
endmodule
| 6.622517 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
);
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module DLatch (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, s, r, x, y;
AndGate S (
d,
d,
s
);
NotGate R (
d,
r
);
nand (x, c, s);
nand (y, c, r);
nand (q, q_, x);
nand (q_, q, y);
endmodule
| 6.957096 |
module DFlipFlopFE (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, Q, Q_;
NotGate C_ (
c,
c_
);
DLatch D1 (
d,
c,
Q,
Q_
);
DLatch D2 (
Q,
c_,
q,
q_
);
endmodule
| 6.583157 |
module StimDFlipFlopFE;
wire q, q_;
reg d, c;
DFlipFlopFE D (
d,
c,
q,
q_
);
initial begin
c = 1'b1;
end
always begin
c = ~c;
#3;
end
initial begin
d = 1'b0;
#10;
d = 1'b1;
#10;
d = 1'b0;
#10;
d = 1'b1;
#10;
end
endmodule
| 6.622517 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
);
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module DLatch (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, s, r, x, y;
AndGate S (
d,
d,
s
);
NotGate R (
d,
r
);
nand (x, c, s);
nand (y, c, r);
nand (q, q_, x);
nand (q_, q, y);
endmodule
| 6.957096 |
module DFlipFlopFE (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, Q, Q_;
NotGate C_ (
c,
c_
);
DLatch D1 (
d,
c,
Q,
Q_
);
DLatch D2 (
Q,
c_,
q,
q_
);
endmodule
| 6.583157 |
module DFlipFlopFESReset (
d,
c,
q,
q_,
re
);
output q, q_;
input d, c, re;
wire re_, d_;
NotGate Re (
re,
re_
);
AndGate A (
d,
re_,
d_
);
DFlipFlopFE Df (
d_,
c,
q,
q_
);
endmodule
| 6.690207 |
module StimDFlipFlopFESReset;
wire q, q_;
reg d, c, re;
DFlipFlopFESReset D (
d,
c,
q,
q_,
re
);
initial begin
c = 1'b1;
end
always begin
c = ~c;
#3;
end
initial begin
d = 1'b0;
re = 1'b0;
#10;
d = 1'b1;
#5;
re = 1'b1;
#5;
re = 1'b0;
d = 1'b0;
#10;
d = 1'b1;
#5;
re = 1'b1;
#5;
end
endmodule
| 6.622517 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
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