code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ah_regs (
//Inputs
rst_n,
clk,
DataVld,
DataIn,
stateVld,
stateAIn,
stateBIn,
stateCIn,
stateDIn,
StateAComb,
StateBComb,
StateCComb,
StateDComb,
StateEComb,
//Outputs
StateAReg,
StateBReg,
StateCReg,
StateDReg,
A_Reg,
B_R... | 7.187325 |
module AIB (
input TX_CLK,
input RX_CLK,
inout [0:79] PAD,
input [0:79] TX_DATA,
output [0:79] RX_DATA
);
// May add the logic function of a real AIB
// Refer to the offical AIB github
// https://github.com/intel/aib-phy-hardware
endmodule
| 7.280516 |
module aibcr3aux_top_master (
output wire o_por_vcchssi,
output wire o_por_vccl,
output wire osc_clkout,
inout wire device_detect, //Shrink aux74/75 due to limit microbump/C4 bump pin
inout wire por, //Shrink aux85/87 pin due to limit microbump/C4 bump pin
input m_por_ovrd,
... | 7.372169 |
module aibcr3pnr_dll_ctrl (
input wire clk, //reference clock from pll
input wire reinit, //initialization enable
input wire entest, //test enable
input wire ndllrst_in, //reset from core
input wire rb_dll_en, //dll enable
input wire rb_dll_rst_en, //dl... | 7.131444 |
module aibcr3pnr_half_cycle_code_gen #(
parameter FF_DELAY = 200
) (
input wire clk, //reference clock from pll
input wire reset_n, //output for dll reset
input wire [10:0] pvt_ref_binary, //output binary pvt value for delay chain; changed from [9:0] to [10:0]
input wire rb_half_code, ... | 6.731612 |
module aibcr3_aliasd (
ra,
rb
);
input ra;
output rb;
assign rb = ra;
endmodule
| 7.374445 |
module aibcr3_aliasv (
ra,
rb
);
inout rb, ra;
wire w;
assign ra = w;
assign rb = w;
endmodule
| 6.715712 |
module aibcr3_bypmux (
input wire byp,
input wire in0,
input wire in1,
output wire out
);
`ifdef BEHAVIORAL
assign out = (byp) ? in1 : in0;
`else
data_mux_2_1 mx (
.sel(byp),
.in0(in0),
.in1(in1),
.out(out)
);
`endif
endmodule
| 7.052537 |
module aibcr3_bypmux_x4 (
input wire byp,
input wire in0,
input wire in1,
output wire out
);
`ifdef BEHAVIORAL
assign out = (byp) ? in1 : in0;
`else
data_mux_2_1 mx (
.sel(byp),
.in0(in0),
.in1(in1),
.out(out)
);
`endif
endmodule
| 7.052537 |
module aibcr3_dcc_phasedet #(
parameter FF_DELAY = 200
) (
output wire t_down,
output reg t_up,
input wire CLKA,
input wire CLKB,
input wire RSTb
);
`ifdef TIMESCALE_EN
timeunit 100fs; timeprecision 100fs;
`endif
always @(posedge CLKB or negedge RSTb)
if (~RSTb) t_up <= #FF_DELAY 1... | 7.718375 |
module aibcr3_dcc_phasedet_single (
output wire t_down,
output wire t_up,
input wire CLKA,
input wire CLKB,
input wire RSTb
);
aibcr3_dcc_phasedet phasedet (
.t_down(),
.t_up (t_up),
.CLKA (CLKA),
.CLKB (CLKB),
.RSTb (RSTb)
);
assign t_down = !t_up;
end... | 7.718375 |
module aibcr3_ddrmux (
input wire clk,
input wire in0,
input wire in1,
output wire out
);
`ifdef BEHAVIORAL
assign out = (clk) ? in1 : in0;
`else
data_mux_2_1 mx (
.sel(clk),
.in0(in0),
.in1(in1),
.out(out)
);
`endif
endmodule
| 7.68929 |
module aibcr3_dll_phasedet__w_sup (
input wire CLKA,
input wire CLKB,
input wire RSTb,
output wire t_down,
output wire t_up,
inout wire VDD,
inout wire VSS
);
wire i_del_n;
wire i_del_p;
wire phase_clk;
wire phase_clkb;
wire [3:0] unused;
aib_dll_phasedet_inv_6__w_sup XDUM... | 6.502499 |
module aibcr3_dll_phasedet (
input wire CLKA,
input wire CLKB,
input wire RSTb,
output wire t_down,
output wire t_up
);
wire VDD_val;
wire VSS_val;
wire t_up_int;
wire t_down_int;
assign VDD_val = 1'b1;
assign VSS_val = 1'b0;
aibcr3_dll_phasedet__w_sup XDUT (
.CLKA(CLKA),
... | 6.502499 |
module aibcr3_ff_p (
input wire CP,
input wire SDN,
input wire D,
output reg Q
);
always @(posedge CP or negedge SDN) begin
if (!SDN) begin
Q <= 1'b1;
end else begin
Q <= D;
end
end
endmodule
| 7.956854 |
module aibcr3_ff_r (
input wire CP,
input wire CDN,
input wire D,
output reg Q
);
always @(posedge CP or negedge CDN) begin
if (!CDN) begin
Q <= 1'b0;
end else begin
Q <= D;
end
end
endmodule
| 7.89932 |
module aibcr3_ff_rp (
input wire CP,
input wire CDN,
input wire SDN,
input wire D,
output reg Q
);
always @(posedge CP or negedge CDN or negedge SDN) begin
if (!CDN) begin
Q <= 1'b0;
end else if (!SDN) begin
Q <= 1'b1;
end else begin
Q <= D;
end
end
endmod... | 8.05228 |
module aib_frontend_inv_14__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_15__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_chain_8__w_sup (
input wire in,
output wire outb,
inout wire VDD,
inout wire VSS
);
aib_frontend_inv_15__w_sup XINV (
.in (in),
.out(outb),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_lvshift_core_4__w_sup (
input wire inn,
input wire inp,
input wire rst_casc,
input wire rst_outn,
input wire rst_outp,
output wire outn,
output wire outp,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
logic outp_temp;
logic outn_temp;
// ... | 7.511093 |
module aib_frontend_lvshift_core_w_drivers_6__w_sup (
input wire in,
input wire inb,
input wire rst_casc,
input wire rst_out,
input wire rst_outb,
output wire out,
output wire outb,
inout wire VDD,
inout wire VSS
);
wire midn;
wire midp;
aib_frontend_inv_chain_8__w_sup... | 7.511093 |
module aib_frontend_inv_16__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_chain_9__w_sup (
input wire in,
output wire out,
output wire outb,
inout wire VDD,
inout wire VSS
);
aib_frontend_inv_16__w_sup XINV0 (
.in (in),
.out(outb),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_inv_16__w_sup XINV1 (
.in (outb),
... | 7.511093 |
module aib_frontend_inv_chain_10__w_sup (
input wire in,
output wire outb,
inout wire VDD,
inout wire VSS
);
aib_frontend_inv_16__w_sup XINV (
.in (in),
.out(outb),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_lvshift_core_5__w_sup (
input wire inn,
input wire inp,
input wire rst_casc,
input wire rst_outn,
input wire rst_outp,
output wire outn,
output wire outp,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
logic outp_temp;
logic outn_temp;
// ... | 7.511093 |
module aib_frontend_lvshift_core_w_drivers_7__w_sup (
input wire in,
input wire inb,
input wire rst_casc,
input wire rst_out,
input wire rst_outb,
output wire out,
output wire outb,
inout wire VDD,
inout wire VSS
);
wire midn;
wire midp;
aib_frontend_inv_chain_10__w_su... | 7.511093 |
module aib_frontend_lvshift_4__w_sup (
input wire in,
input wire rst_casc,
input wire rst_out,
input wire rst_outb,
output wire out,
output wire outb,
inout wire VDD,
inout wire VDD_in,
inout wire VSS
);
wire in_buf;
wire inb_buf;
aib_frontend_inv_chain_9__w_sup XBUF (... | 7.511093 |
module aib_frontend_inv_17__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_chain_11__w_sup (
input wire in,
output wire outb,
inout wire VDD,
inout wire VSS
);
aib_frontend_inv_17__w_sup XINV (
.in (in),
.out(outb),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_lvshift_core_6__w_sup (
input wire inn,
input wire inp,
output wire outn,
output wire outp,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
logic outp_temp;
logic outn_temp;
// add first two lines of casez to eliminate any X output. This is done to debug... | 7.511093 |
module aib_frontend_lvshift_core_w_drivers_8__w_sup (
input wire in,
input wire inb,
output wire out,
output wire outb,
inout wire VDD,
inout wire VSS
);
wire midn;
wire midp;
aib_frontend_inv_chain_11__w_sup XBUFN (
.in (midn),
.outb(out),
.VDD (VDD),
.VSS (... | 7.511093 |
module aib_frontend_inv_18__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_19__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_chain_12__w_sup (
input wire in,
output wire out,
output wire outb,
inout wire VDD,
inout wire VSS
);
aib_frontend_inv_18__w_sup XINV0 (
.in (in),
.out(outb),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_inv_19__w_sup XINV1 (
.in (outb),
... | 7.511093 |
module aib_frontend_inv_20__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_chain_13__w_sup (
input wire in,
output wire outb,
inout wire VDD,
inout wire VSS
);
wire [0:0] mid;
wire out;
aib_frontend_inv_16__w_sup XINV0 (
.in (in),
.out(mid[0]),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_inv_20__w_sup XINV1 (
.in (... | 7.511093 |
module aib_frontend_nand_3__w_sup (
input wire [1:0] in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~&in);
endmodule
| 7.511093 |
module aib_frontend_nor_2__w_sup (
input wire [1:0] in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~|in);
endmodule
| 7.511093 |
module aib_frontend_aib_se2diff_match_1__w_sup (
input wire en,
input wire enb,
input wire inn,
input wire inp,
output wire outn,
output wire outp,
inout wire VDD,
inout wire VSS
);
wire nand_out;
wire nor_out;
aib_frontend_inv_chain_13__w_sup XBUFN (
.in (nor_out),
... | 7.511093 |
module aib_frontend_inv_21__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_22__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_23__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_24__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_passgate_1__w_sup(
input wire en,
input wire enb,
input wire s,
output trireg d,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
wire tmp;
assign #DELAY tmp = VSS ? 1'bx : (~VDD ? 1'b0 : s);
tranif1 XTRN1 (d, tmp, en );
tranif0 XTRN0 (d, tmp, enb);
endmodule
| 7.511093 |
module aib_frontend_se_to_diff_1__w_sup (
input wire in,
output wire outn,
output wire outp,
inout wire VDD,
inout wire VSS
);
wire midn_inv;
wire midn_pass0;
wire midn_pass1;
wire midp;
aib_frontend_inv_21__w_sup XINVN0 (
.in (in),
.out(midn_inv),
.VDD(VDD),
.... | 7.511093 |
module aib_frontend_nand_4__w_sup (
input wire [1:0] in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~&in);
endmodule
| 7.511093 |
module aib_frontend_aib_se2diff_1__w_sup (
input wire en,
input wire enb,
input wire in,
output wire outn,
output wire outp,
inout wire VDD,
inout wire VSS
);
wire inb;
wire nc;
aib_frontend_se_to_diff_1__w_sup XCORE (
.in (inb),
.outn(outp),
.outp(outn),
... | 7.511093 |
module aib_frontend_aib_rxanlg_core_1__w_sup (
input wire clk_en,
input wire data_en,
input wire iclkn,
input wire iopad,
input wire por,
output wire oclkn,
output wire oclkp,
output wire odat,
output wire odat_async,
output wire por_vccl,
output wire porb_vccl,
inou... | 7.511093 |
module aib_frontend_aib_driver_pu_pd_2__w_sup (
input wire pden,
input wire puenb,
output wire out,
inout wire VDD,
inout wire VSS
);
logic out_temp;
always_comb begin
// puenb connects to PMOS, pden connects to NMOS
casez ({
VDD, VSS, puenb, pden
})
4'b10_00: out_t... | 7.511093 |
module aib_frontend_current_summer_1__w_sup (
input wire [6:0] in,
output wire out
);
tran tr0 (in[0], out);
tran tr1 (in[1], out);
tran tr2 (in[2], out);
tran tr3 (in[3], out);
tran tr4 (in[4], out);
tran tr5 (in[5], out);
tran tr6 (in[6], out);
endmodule
| 7.511093 |
module aib_frontend_nand_5__w_sup (
input wire [1:0] in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~&in);
endmodule
| 7.511093 |
module aib_frontend_nor_3__w_sup (
input wire [1:0] in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~|in);
endmodule
| 7.511093 |
module aib_frontend_aib_driver_pu_pd_3__w_sup (
input wire pden,
input wire puenb,
output wire out,
inout wire VDD,
inout wire VSS
);
logic out_temp;
always_comb begin
// puenb connects to PMOS, pden connects to NMOS
casez ({
VDD, VSS, puenb, pden
})
4'b10_00: out_t... | 7.511093 |
module aib_frontend_aib_driver_output_unit_cell_1__w_sup (
input wire en,
input wire enb,
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
wire nand_pu;
wire nor_pd;
aib_frontend_nand_5__w_sup XNAND (
.in ({en, in}),
.out(nand_pu),
.VDD(VDD),
... | 7.511093 |
module aib_frontend_aib_driver_output_driver_1__w_sup (
input wire din,
input wire [1:0] n_enb_drv,
input wire [1:0] p_en_drv,
input wire tristate,
input wire tristateb,
input wire weak_pden,
input wire weak_puenb,
output wire txpadout,
inout wire VDD,
inout wire VSS
);
wire [... | 7.511093 |
module aib_frontend_inv_25__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_26__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_chain_14__w_sup (
input wire in,
output wire out,
output wire outb,
inout wire VDD,
inout wire VSS
);
aib_frontend_inv_25__w_sup XINV0 (
.in (in),
.out(outb),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_inv_26__w_sup XINV1 (
.in (outb),
... | 7.511093 |
module aib_frontend_inv_27__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_chain_15__w_sup (
input wire in,
output wire outb,
inout wire VDD,
inout wire VSS
);
aib_frontend_inv_27__w_sup XINV (
.in (in),
.out(outb),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_lvshift_core_7__w_sup (
input wire inn,
input wire inp,
input wire rst_casc,
input wire rst_outn,
input wire rst_outp,
output wire outn,
output wire outp,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
logic outp_temp;
logic outn_temp;
// ... | 7.511093 |
module aib_frontend_lvshift_core_w_drivers_9__w_sup (
input wire in,
input wire inb,
input wire rst_casc,
input wire rst_out,
input wire rst_outb,
output wire out,
inout wire VDD,
inout wire VSS
);
wire midn;
wire midp;
aib_frontend_inv_chain_15__w_sup XBUFN (
.in (... | 7.511093 |
module aib_frontend_lvshift_5__w_sup (
input wire in,
input wire rst_casc,
input wire rst_out,
input wire rst_outb,
output wire out,
inout wire VDD,
inout wire VDD_in,
inout wire VSS
);
wire in_buf;
wire inb_buf;
aib_frontend_inv_chain_14__w_sup XBUF (
.in (in),
... | 7.511093 |
module aib_frontend_lvshift_core_w_drivers_10__w_sup (
input wire in,
input wire inb,
input wire rst_casc,
input wire rst_out,
input wire rst_outb,
output wire outb,
inout wire VDD,
inout wire VSS
);
wire midn;
wire midp;
aib_frontend_inv_chain_10__w_sup XBUFP (
.in ... | 7.511093 |
module aib_frontend_lvshift_6__w_sup (
input wire in,
input wire rst_casc,
input wire rst_out,
input wire rst_outb,
output wire out,
output wire outb,
inout wire VDD,
inout wire VDD_in,
inout wire VSS
);
wire in_buf;
wire inb_buf;
aib_frontend_inv_chain_9__w_sup XBUF (... | 7.511093 |
module aib_frontend_lvshift_core_w_drivers_11__w_sup (
input wire in,
input wire inb,
input wire rst_casc,
input wire rst_out,
input wire rst_outb,
output wire out,
inout wire VDD,
inout wire VSS
);
wire midn;
wire midp;
aib_frontend_inv_chain_10__w_sup XBUFN (
.in ... | 7.511093 |
module aib_frontend_lvshift_7__w_sup (
input wire in,
input wire rst_casc,
input wire rst_out,
input wire rst_outb,
output wire out,
inout wire VDD,
inout wire VDD_in,
inout wire VSS
);
wire in_buf;
wire inb_buf;
aib_frontend_inv_chain_9__w_sup XBUF (
.in (in),
... | 7.511093 |
module aib_frontend_aib_txanlg_core_1__w_sup (
input wire din,
input wire [1:0] indrv_buf,
input wire [1:0] ipdrv_buf,
input wire itx_en_buf,
input wire por_vccl,
input wire porb_vccl,
input wire weak_pulldownen,
input wire weak_pullupenb,
output wire txpadout,
inout wire VDDCore... | 7.511093 |
module aib_frontend_aib_frontend_core_1__w_sup (
input wire clk_en,
input wire data_en,
input wire din,
input wire iclkn,
input wire [1:0] indrv_buf,
input wire [1:0] ipdrv_buf,
input wire itx_en_buf,
input wire por,
input wire rxpadin,
input wire weak_pulldownen,
input wire ... | 7.511093 |
module aib_frontend_metal_short_m6_1__w_sup (
inout wire MINUS,
inout wire PLUS
);
tran tr (PLUS, MINUS);
endmodule
| 7.511093 |
module aib_frontend_esd_diode_ndio_1__w_sup (
inout wire MINUS,
inout wire PLUS
);
always @(PLUS) begin
if (PLUS === 1'bz) $display("ESD ndio error: PLUS port is 1'bz");
end
endmodule
| 7.511093 |
module aib_frontend_esd_diode_pdio_1__w_sup (
inout wire MINUS,
inout wire PLUS
);
always @(MINUS) begin
if (MINUS === 1'bz) $display("ESD pdio error: MINUS port is 1'bz");
end
endmodule
| 7.511093 |
module aibcr3_inv_split_align (
din,
dout,
vccl,
vssl
);
input din;
output dout;
input vssl;
input vccl;
assign dout = ~din;
endmodule
| 7.372862 |
module aibcr3_io_nand_delay_line_min (
input nfrzdrv,
input in_p,
input in_n,
output out_p,
output out_n
);
`ifdef TIMESCALE_EN
timeunit 1ps; timeprecision 1ps;
`endif
parameter NAND_DELAY = 20;
wire fout_p;
wire fout_n;
wire osc_out_p;
wire osc_out_n;
//------------------------... | 6.565557 |
module aibcr3_io_nand_delay_line_min_rep (
input nfrzdrv,
input in_p,
input in_n,
output out_p,
output out_n
);
`ifdef TIMESCALE_EN
timeunit 1ps; timeprecision 1ps;
`endif
parameter NAND_DELAY = 20;
wire fout_p;
wire fout_n;
wire osc_out_p;
wire osc_out_n;
//--------------------... | 6.565557 |
module aibcr3_io_nand_x128_delay_line (
input nfrzdrv,
input in_p,
input in_n,
input osc_mode, // Mux control for the x64 ring oscillator
input osc_in_p, // input for the x64 ring oscillator
input osc_in_n, // input for the x64 ring oscillator
... | 6.565557 |
module aibcr3_latch (
input wire E,
input wire CDN,
//input wire vcc,
//input wire vss,
input wire D,
output reg Q
);
always @(*) begin
if (!CDN) begin
Q <= 0;
end else begin
if (E) Q <= D;
end
end
endmodule
| 8.144334 |
module aibcr3_nd2d0_custom (
zn,
a1,
a2,
vcc_regphy,
vss_io
);
output zn;
input a2;
input a1;
input vss_io;
input vcc_regphy;
assign zn = ~(a1 && a2);
endmodule
| 6.734436 |
module aibcr3_quadph_code_gen #(
parameter FF_DELAY = 200
) (
input wire clk, //reference clock from pll
input wire reset_n, //output for dll reset
input wire [9:0] pvt_ref_binary, //output binary pvt value for delay chain
input wire rb_quad_cod... | 6.934796 |
module aibcr3_rxdat_mimic (
input wire odat_in,
input wire vcc_aibcr,
input wire vss_aibcr,
output wire odat_out
);
assign odat_out = odat_in;
endmodule
| 7.432382 |
module aibcr3_split_align (
input din, // input
output dout_p, // splitted output positive
output dout_n // splitted output negative
);
`ifdef TIMESCALE_EN
timeunit 1ps; timeprecision 1ps;
`endif
parameter INV_DELAY = 15; // 15ps
assign #(2 * INV_DELAY) dout_p = din;
assign #(2 * INV_DEL... | 8.544277 |
module aibcr3_str_ioload (
in,
vcc,
vssl
);
input in, vcc, vssl;
// Buses in the design
wire net5;
// specify
// specparam CDS_LIBNAME = "aibcr_lib";
// specparam CDS_CELLNAME = "aibcr_str_ioload";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
assign net5 = ~in... | 6.722411 |
module aibcr3_sync_2ff (
CDN,
CP,
D,
SE,
SI,
Q
);
input CDN, CP, D, SE, SI;
output reg Q;
wire data;
reg flop_0;
assign data = SE ? SI : D;
always @(posedge CP or negedge CDN)
if (!CDN) {Q, flop_0} <= 0;
else if (CDN) {Q, flop_0} <= {flop_0, data};
else {Q, flop_0} <= ... | 6.716574 |
module aibcr3_sync_3ff (
CDN,
CP,
D,
SE,
SI,
Q
);
input CDN, CP, D, SE, SI;
output reg Q;
wire data;
reg flop_1, flop_0;
assign data = SE ? SI : D;
always @(posedge CP or negedge CDN)
if (!CDN) {Q, flop_1, flop_0} <= 0;
else if (CDN) {Q, flop_1, flop_0} <= {flop_1, flop_0, ... | 6.622928 |
module aibcr3_txdat_mimic (
input wire idat_in,
input wire vcc_aibcr,
input wire vss_aibcr,
output wire idat_out
);
assign idat_out = idat_in;
endmodule
| 8.179853 |
module aibcr3_ulvt16_2xarstsyncdff1_b2 (
CLR_N,
CK,
D,
SE,
SI,
Q
);
input CLR_N, CK, D, SE, SI;
output reg Q;
wire data;
reg flop_0;
assign data = SE ? SI : D;
always @(posedge CK or negedge CLR_N)
if (!CLR_N) {Q, flop_0} <= 0;
else if (CLR_N) {Q, flop_0} <= {flop_0, data}... | 8.164146 |
module aibcr3_ulvt16_dffcdn_cust (
input wire CK,
input wire CDN,
input wire D,
output reg Q
);
always @(posedge CK or negedge CDN) begin
if (!CDN) begin
Q <= 1'b0;
end else begin
Q <= D;
end
end
endmodule
| 8.164146 |
module aibcr3_ulvt16_dffsdn_cust (
input wire CK,
input wire SDN,
input wire D,
output reg Q
);
always @(posedge CK or negedge SDN) begin
if (!SDN) begin
Q <= 1'b1;
end else begin
Q <= D;
end
end
endmodule
| 8.164146 |
module aibndaux_top_slave (
o_crdet,
u_crdet,
u_crdet_r,
u_dn_por,
u_dn_por_r,
i_dn_por,
i_crdet_ovrd
);
output o_crdet;
inout u_crdet, u_crdet_r, u_dn_por, u_dn_por_r;
input i_dn_por, i_crdet_ovrd;
wire o_crete_detect;
assign vccl_aibndaux = 1'b1;
assign vssl_aibndaux = 1'b0... | 6.631813 |
module aibndpnr_dll_atech_clkgate_cgc00 (
input wire clk,
input wire en,
output wire clkout
);
reg o;
always @(en, clk) begin
if (~clk) begin
o <= en;
end
end
assign clkout = clk & o;
endmodule
| 7.015995 |
module aibndpnr_dll_atech_clkgate_cgc01 (
input wire clk,
input wire en,
input wire te,
output wire clkout
);
wire d;
reg o;
assign d = en | te;
always @(d, clk) begin
if (~clk) begin
o <= d;
end
end
assign clkout = clk & o;
endmodule
| 7.015995 |
module aibndpnr_dll_atech_clkmux
// IMPORTANT NOTICE: This clock mux behavioral model
// must be mapped to either a transmission gate mux
// or a pass gate mux in the standard cell library.
// Failure to comply will result in glitch hazards.
(
input wire clk1,
input wire clk2,
input wire s,... | 7.015995 |
module aibndpnr_dll_ctrl (
input wire clk, //reference clock from pll
input wire reinit, //initialization enable
input wire entest, //test enable
input wire ndllrst_in, //reset from core
input wire rb_dll_en, //dll enable
input wire rb_dll_rst_en, //dll... | 7.015995 |
module aibnd_aliasd (
PLUS,
MINUS
);
input PLUS;
output MINUS;
assign MINUS = PLUS;
endmodule
| 6.717766 |
module aibnd_analog (
oclkn,
oclkp,
odat,
odat_async,
iopad,
clk_en,
data_en,
iclkn,
ndrv_enb,
pdrv_en,
txdin,
vccl_aibnd,
vssl_aibnd,
weak_pulldownen,
weak_pullupenb
);
output oclkn, oclkp, odat, odat_async;
inout iopad;
input clk_en, data_en, iclkn,... | 6.65117 |
module aibnd_avmm_rst_sync (
pcs_clk,
pcs_clkb,
resetb_sync_buf,
avmm_clk,
avmm_rstb,
vccl_aibnd,
vssl_aibnd
);
output pcs_clk, pcs_clkb, resetb_sync_buf;
input avmm_clk, avmm_rstb, vccl_aibnd, vssl_aibnd;
wire gated_avmm_clk, pcs_clk, reset_b_sync, resetb_sync_buf, avmm_clk, avmm_c... | 6.925604 |
module aibnd_dcc_sense (
up,
vcc_io,
vcc_regphy,
vss_io,
clk_dcc,
dll_reset_n,
nfrzdrv,
pvt_ref_half_gry
);
output up;
inout vcc_io, vcc_regphy, vss_io;
input clk_dcc, dll_reset_n, nfrzdrv;
input [9:0] pvt_ref_half_gry;
wire up, net018, net022, net025; // Conversion Sript... | 6.806032 |
module aibnd_ff_r (
input wire clk,
input wire rb,
input wire d,
//input wire vss,
//input wire vcc,
output reg o
);
always @(posedge clk or negedge rb) begin
if (!rb) begin
o <= 1'b0;
end else begin
o <= d;
end
end
endmodule
| 8.226681 |
module aibnd_ff_rp (
input wire clk,
input wire rb,
input wire psb,
input wire d,
//input wire vss,
//input wire vcc,
output reg o
);
always @(posedge clk or negedge rb or negedge psb) begin
if (!rb) begin
o <= 1'b0;
end else if (!psb) begin
o <= 1'b1;
end els... | 8.55097 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.