code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module ah_regs (
//Inputs
rst_n,
clk,
DataVld,
DataIn,
stateVld,
stateAIn,
stateBIn,
stateCIn,
stateDIn,
StateAComb,
StateBComb,
StateCComb,
StateDComb,
StateEComb,
//Outputs
StateAReg,
StateBReg,
StateCReg,
StateDReg,
A_Reg,
B_Reg,
C_Reg,
D_Reg,
BlockOut
);
`include "ah_params.vh"
input rst_n;
input clk;
input DataVld;
input [DATA_WIDTH - 1:0] DataIn;
input stateVld;
input [STATE_DWIDTH - 1:0] stateAIn;
input [STATE_DWIDTH - 1:0] stateBIn;
input [STATE_DWIDTH - 1:0] stateCIn;
input [STATE_DWIDTH - 1:0] stateDIn;
input [STATE_DWIDTH - 1:0] StateAComb;
input [STATE_DWIDTH - 1:0] StateBComb;
input [STATE_DWIDTH - 1:0] StateCComb;
input [STATE_DWIDTH - 1:0] StateDComb;
input [STATE_DWIDTH - 1:0] StateEComb;
output [STATE_DWIDTH - 1:0] StateAReg;
output [STATE_DWIDTH - 1:0] StateBReg;
output [STATE_DWIDTH - 1:0] StateCReg;
output [STATE_DWIDTH - 1:0] StateDReg;
output [STATE_DWIDTH - 1:0] A_Reg;
output [STATE_DWIDTH - 1:0] B_Reg;
output [STATE_DWIDTH - 1:0] C_Reg;
output [STATE_DWIDTH - 1:0] D_Reg;
output [BLOCK_SIZE-1:0] BlockOut;
reg [STATE_DWIDTH - 1:0] StateAReg;
reg [STATE_DWIDTH - 1:0] StateBReg;
reg [STATE_DWIDTH - 1:0] StateCReg;
reg [STATE_DWIDTH - 1:0] StateDReg;
reg [STATE_DWIDTH - 1:0] A_Reg;
reg [STATE_DWIDTH - 1:0] B_Reg;
reg [STATE_DWIDTH - 1:0] C_Reg;
reg [STATE_DWIDTH - 1:0] D_Reg;
reg [ DATA_WIDTH - 1:0] WtData [15:0];
assign BlockOut = {
WtData[15],
WtData[14],
WtData[13],
WtData[12],
WtData[11],
WtData[10],
WtData[9],
WtData[8],
WtData[7],
WtData[6],
WtData[5],
WtData[4],
WtData[3],
WtData[2],
WtData[1],
WtData[0]
};
always @(posedge clk) begin
if (DataVld) begin
WtData[0] <= DataIn;
WtData[1] <= WtData[0];
WtData[2] <= WtData[1];
WtData[3] <= WtData[2];
WtData[4] <= WtData[3];
WtData[5] <= WtData[4];
WtData[6] <= WtData[5];
WtData[7] <= WtData[6];
WtData[8] <= WtData[7];
WtData[9] <= WtData[8];
WtData[10] <= WtData[9];
WtData[11] <= WtData[10];
WtData[12] <= WtData[11];
WtData[13] <= WtData[12];
WtData[14] <= WtData[13];
WtData[15] <= WtData[14];
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
StateAReg <= 32'b0;
StateBReg <= 32'b0;
StateCReg <= 32'b0;
StateDReg <= 32'b0;
end else begin
if (stateVld) begin
StateAReg <= stateAIn;
StateBReg <= stateBIn;
StateCReg <= stateCIn;
StateDReg <= stateDIn;
end else begin
StateAReg <= StateAComb;
StateBReg <= StateBComb;
StateCReg <= StateCComb;
StateDReg <= StateDComb;
end
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
A_Reg <= 32'b0;
B_Reg <= 32'b0;
C_Reg <= 32'b0;
D_Reg <= 32'b0;
end else begin
if (stateVld) begin
A_Reg <= stateAIn;
B_Reg <= stateBIn;
C_Reg <= stateCIn;
D_Reg <= stateDIn;
end
end
end
endmodule
| 7.187325 |
module AIB (
input TX_CLK,
input RX_CLK,
inout [0:79] PAD,
input [0:79] TX_DATA,
output [0:79] RX_DATA
);
// May add the logic function of a real AIB
// Refer to the offical AIB github
// https://github.com/intel/aib-phy-hardware
endmodule
| 7.280516 |
module aibcr3aux_top_master (
output wire o_por_vcchssi,
output wire o_por_vccl,
output wire osc_clkout,
inout wire device_detect, //Shrink aux74/75 due to limit microbump/C4 bump pin
inout wire por, //Shrink aux85/87 pin due to limit microbump/C4 bump pin
input m_por_ovrd,
input i_osc_clk
);
`ifdef LEVEL_SHIFTER_TEST
wire vccl_aibcr3aux;
wire vcc_aibcr3aux;
`else
wire vccl_aibcr3aux = 1'b1;
wire vcc_aibcr3aux = 1'b1;
`endif
wire vssl_aibcr3aux = 1'b0;
//Changed instantiation to match with the schematic, Jennifer 05/04/18
wire por_out; //After IO buffer
wire por_out_vcc; //After level shifter
aibcr3aux_pasred_baldwin xpasred (
.iopad_crdet(device_detect),
.vssl_aibcr3aux(vssl_aibcr3aux),
.vccl_aibcr3aux(vccl_aibcr3aux),
.iopad_dn_por(por),
.dn_por(por_dummy)
);
assign o_por_vcc = (m_por_ovrd & por_out_vcc);
assign osc_clkout = i_osc_clk;
assign o_por_vcchssi = o_por_vcc;
assign o_por_vccl = 1'b0;
aibcr3_lvshift_vcc xlvlshf1 (
.vccl_aibcr3aux(vccl_aibcr3aux),
.vcc_aibcr3aux(vcc_aibcr3aux),
.out(por_out_vcc),
.in(por)
); //Output go to AND gate to produce o_por_vccl
endmodule
| 7.372169 |
module aibcr3pnr_dll_ctrl (
input wire clk, //reference clock from pll
input wire reinit, //initialization enable
input wire entest, //test enable
input wire ndllrst_in, //reset from core
input wire rb_dll_en, //dll enable
input wire rb_dll_rst_en, //dll reset enable
input wire atpg_en_n, //atpg
input wire test_clr_n, //test clear
output wire dll_reset_n //output for dll reset
);
`ifdef TIMESCALE_EN
timeunit 1ps; timeprecision 1ps;
`endif
wire eni;
wire dll_rst;
////////////////////////////////////////////////////////////////////
// //
// reset and preset //
// //
////////////////////////////////////////////////////////////////////
assign dll_rst = (rb_dll_rst_en) ? ~ndllrst_in : 1'b0; //core reset at "1" if core_reset enabled
assign eni = ~entest & rb_dll_en & (~reinit) & (~dll_rst); //dll enable and non-test
//hd_dpcmn_rst_n_sync unrst ( .rst_n(eni), .rst_n_bypass(test_clr_n), .clk(clk), .scan_mode_n(atpg_en_n), .rst_n_sync(dll_reset_n) );
aibcr3pnr_rstsync unrst (
.rst_n(eni),
.rst_n_bypass(test_clr_n),
.clk(clk),
.scan_mode_n(atpg_en_n),
.rst_n_sync(dll_reset_n)
);
endmodule
| 7.131444 |
module aibcr3pnr_half_cycle_code_gen #(
parameter FF_DELAY = 200
) (
input wire clk, //reference clock from pll
input wire reset_n, //output for dll reset
input wire [10:0] pvt_ref_binary, //output binary pvt value for delay chain; changed from [9:0] to [10:0]
input wire rb_half_code, //select between original or half cycle codes
output reg [10:0] pvt_ref_half_binary //half cycle code (binary) for delay chain; change from [9:0] to [10:0]
);
`ifdef TIMESCALE_EN
timeunit 1ps; timeprecision 1ps;
`endif
wire [7:0] coarse_bin; // change from [6:0] to [7:0]
wire [2:0] fint_bin, fint_bin_inc;
wire [2:0] fine_bin;
wire [8:0] coarse_divided_bin; // change from [7:0] to [8:0]
wire [3:0] fine_divided_bin, coarse_frac_bin;
assign coarse_divided_bin[8:0] = {
1'b0, pvt_ref_binary[10:3]
}; // changed from pvt_ref_binary[9:3] to [10:3]
assign fine_divided_bin[3:0] = {1'b0, pvt_ref_binary[2:0]};
assign coarse_frac_bin[3:0] = {coarse_divided_bin[0], 3'b000};
assign fint_bin[2:0] = coarse_frac_bin[3:1] + fine_divided_bin[3:1];
assign fint_bin_inc[2:0] = ((fine_divided_bin[0] >= 1'd1) && (fint_bin < 3'd7)) ? fint_bin[2:0] + 3'b001 : fint_bin[2:0];
assign coarse_bin = coarse_divided_bin[8:1]; // change from [7:1] to [8:1]
assign fine_bin = fint_bin_inc;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
pvt_ref_half_binary <= #FF_DELAY 11'b000_0000_0000;
end else
case (rb_half_code)
1'b0: pvt_ref_half_binary <= #FF_DELAY pvt_ref_binary;
1'b1: pvt_ref_half_binary <= #FF_DELAY{coarse_bin, fine_bin};
default: pvt_ref_half_binary <= #FF_DELAY{coarse_bin, fine_bin};
endcase
end
endmodule
| 6.731612 |
module aibcr3_aliasd (
ra,
rb
);
input ra;
output rb;
assign rb = ra;
endmodule
| 7.374445 |
module aibcr3_aliasv (
ra,
rb
);
inout rb, ra;
wire w;
assign ra = w;
assign rb = w;
endmodule
| 6.715712 |
module aibcr3_bypmux (
input wire byp,
input wire in0,
input wire in1,
output wire out
);
`ifdef BEHAVIORAL
assign out = (byp) ? in1 : in0;
`else
data_mux_2_1 mx (
.sel(byp),
.in0(in0),
.in1(in1),
.out(out)
);
`endif
endmodule
| 7.052537 |
module aibcr3_bypmux_x4 (
input wire byp,
input wire in0,
input wire in1,
output wire out
);
`ifdef BEHAVIORAL
assign out = (byp) ? in1 : in0;
`else
data_mux_2_1 mx (
.sel(byp),
.in0(in0),
.in1(in1),
.out(out)
);
`endif
endmodule
| 7.052537 |
module aibcr3_dcc_phasedet #(
parameter FF_DELAY = 200
) (
output wire t_down,
output reg t_up,
input wire CLKA,
input wire CLKB,
input wire RSTb
);
`ifdef TIMESCALE_EN
timeunit 100fs; timeprecision 100fs;
`endif
always @(posedge CLKB or negedge RSTb)
if (~RSTb) t_up <= #FF_DELAY 1'b1;
else t_up <= #FF_DELAY CLKA;
assign t_down = !t_up;
endmodule
| 7.718375 |
module aibcr3_dcc_phasedet_single (
output wire t_down,
output wire t_up,
input wire CLKA,
input wire CLKB,
input wire RSTb
);
aibcr3_dcc_phasedet phasedet (
.t_down(),
.t_up (t_up),
.CLKA (CLKA),
.CLKB (CLKB),
.RSTb (RSTb)
);
assign t_down = !t_up;
endmodule
| 7.718375 |
module aibcr3_ddrmux (
input wire clk,
input wire in0,
input wire in1,
output wire out
);
`ifdef BEHAVIORAL
assign out = (clk) ? in1 : in0;
`else
data_mux_2_1 mx (
.sel(clk),
.in0(in0),
.in1(in1),
.out(out)
);
`endif
endmodule
| 7.68929 |
module aibcr3_dll_phasedet__w_sup (
input wire CLKA,
input wire CLKB,
input wire RSTb,
output wire t_down,
output wire t_up,
inout wire VDD,
inout wire VSS
);
wire i_del_n;
wire i_del_p;
wire phase_clk;
wire phase_clkb;
wire [3:0] unused;
aib_dll_phasedet_inv_6__w_sup XDUMD (
.in (phase_clkb),
.out(unused[3]),
.VDD(VDD),
.VSS(VSS)
);
aib_dll_phasedet_inv_6__w_sup XDUMU (
.in (i_del_p),
.out(unused[0]),
.VDD(VDD),
.VSS(VSS)
);
aib_dll_phasedet_flop_strongarm_1__w_sup XFLOPD (
.clk (i_del_n),
.inn (phase_clk),
.inp (phase_clkb),
.rstlb(RSTb),
.outn (unused[2]),
.outp (t_down),
.VDD (VDD),
.VSS (VSS)
);
aib_dll_phasedet_flop_strongarm_1__w_sup XFLOPU (
.clk (phase_clk),
.inn (i_del_n),
.inp (i_del_p),
.rstlb(RSTb),
.outn (unused[1]),
.outp (t_up),
.VDD (VDD),
.VSS (VSS)
);
aib_dll_phasedet_se_to_diff_1__w_sup XSED (
.in (CLKB),
.outn(phase_clkb),
.outp(phase_clk),
.VDD (VDD),
.VSS (VSS)
);
aib_dll_phasedet_se_to_diff_1__w_sup XSEU (
.in (CLKA),
.outn(i_del_n),
.outp(i_del_p),
.VDD (VDD),
.VSS (VSS)
);
endmodule
| 6.502499 |
module aibcr3_dll_phasedet (
input wire CLKA,
input wire CLKB,
input wire RSTb,
output wire t_down,
output wire t_up
);
wire VDD_val;
wire VSS_val;
wire t_up_int;
wire t_down_int;
assign VDD_val = 1'b1;
assign VSS_val = 1'b0;
aibcr3_dll_phasedet__w_sup XDUT (
.CLKA(CLKA),
.CLKB(CLKB),
.RSTb(RSTb),
.t_down(t_down_int),
.t_up(t_up_int),
.VDD(VDD_val),
.VSS(VSS_val)
);
// from tttt_25_0p850_0p970
assign #(64, 62) t_up = t_up_int;
assign #(69, 67) t_down = t_down_int;
endmodule
| 6.502499 |
module aibcr3_ff_p (
input wire CP,
input wire SDN,
input wire D,
output reg Q
);
always @(posedge CP or negedge SDN) begin
if (!SDN) begin
Q <= 1'b1;
end else begin
Q <= D;
end
end
endmodule
| 7.956854 |
module aibcr3_ff_r (
input wire CP,
input wire CDN,
input wire D,
output reg Q
);
always @(posedge CP or negedge CDN) begin
if (!CDN) begin
Q <= 1'b0;
end else begin
Q <= D;
end
end
endmodule
| 7.89932 |
module aibcr3_ff_rp (
input wire CP,
input wire CDN,
input wire SDN,
input wire D,
output reg Q
);
always @(posedge CP or negedge CDN or negedge SDN) begin
if (!CDN) begin
Q <= 1'b0;
end else if (!SDN) begin
Q <= 1'b1;
end else begin
Q <= D;
end
end
endmodule
| 8.05228 |
module aib_frontend_inv_14__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_15__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_chain_8__w_sup (
input wire in,
output wire outb,
inout wire VDD,
inout wire VSS
);
aib_frontend_inv_15__w_sup XINV (
.in (in),
.out(outb),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_lvshift_core_4__w_sup (
input wire inn,
input wire inp,
input wire rst_casc,
input wire rst_outn,
input wire rst_outp,
output wire outn,
output wire outp,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
logic outp_temp;
logic outn_temp;
// add first two lines of casez to eliminate any X output. This is done to debug innovus
always_comb begin
casez ({
rst_outp, rst_outn, rst_casc, inp, inn, VDD, VSS
})
7'b00_1_00_10: {outp_temp, outn_temp} = 2'b00;
7'b00_1_11_10: {outp_temp, outn_temp} = 2'b11;
7'b10_0_??_10: {outp_temp, outn_temp} = 2'b01;
7'b01_0_??_10: {outp_temp, outn_temp} = 2'b10;
7'b00_1_10_10: {outp_temp, outn_temp} = 2'b10;
7'b00_1_01_10: {outp_temp, outn_temp} = 2'b01;
7'b10_1_10_10: {outp_temp, outn_temp} = 2'b01;
7'b01_1_01_10: {outp_temp, outn_temp} = 2'b10;
7'b??_?_??_00: {outp_temp, outn_temp} = 2'b00;
default: {outp_temp, outn_temp} = 2'bxx;
endcase
end
assign #DELAY outp = outp_temp;
assign #DELAY outn = outn_temp;
endmodule
| 7.511093 |
module aib_frontend_lvshift_core_w_drivers_6__w_sup (
input wire in,
input wire inb,
input wire rst_casc,
input wire rst_out,
input wire rst_outb,
output wire out,
output wire outb,
inout wire VDD,
inout wire VSS
);
wire midn;
wire midp;
aib_frontend_inv_chain_8__w_sup XBUFN (
.in (midn),
.outb(out),
.VDD (VDD),
.VSS (VSS)
);
aib_frontend_inv_chain_8__w_sup XBUFP (
.in (midp),
.outb(outb),
.VDD (VDD),
.VSS (VSS)
);
aib_frontend_lvshift_core_4__w_sup XCORE (
.inn(inb),
.inp(in),
.rst_casc(rst_casc),
.rst_outn(rst_outb),
.rst_outp(rst_out),
.outn(midn),
.outp(midp),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_inv_16__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_chain_9__w_sup (
input wire in,
output wire out,
output wire outb,
inout wire VDD,
inout wire VSS
);
aib_frontend_inv_16__w_sup XINV0 (
.in (in),
.out(outb),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_inv_16__w_sup XINV1 (
.in (outb),
.out(out),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_inv_chain_10__w_sup (
input wire in,
output wire outb,
inout wire VDD,
inout wire VSS
);
aib_frontend_inv_16__w_sup XINV (
.in (in),
.out(outb),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_lvshift_core_5__w_sup (
input wire inn,
input wire inp,
input wire rst_casc,
input wire rst_outn,
input wire rst_outp,
output wire outn,
output wire outp,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
logic outp_temp;
logic outn_temp;
// add first two lines of casez to eliminate any X output. This is done to debug innovus
always_comb begin
casez ({
rst_outp, rst_outn, rst_casc, inp, inn, VDD, VSS
})
7'b00_1_00_10: {outp_temp, outn_temp} = 2'b00;
7'b00_1_11_10: {outp_temp, outn_temp} = 2'b11;
7'b10_0_??_10: {outp_temp, outn_temp} = 2'b01;
7'b01_0_??_10: {outp_temp, outn_temp} = 2'b10;
7'b00_1_10_10: {outp_temp, outn_temp} = 2'b10;
7'b00_1_01_10: {outp_temp, outn_temp} = 2'b01;
7'b10_1_10_10: {outp_temp, outn_temp} = 2'b01;
7'b01_1_01_10: {outp_temp, outn_temp} = 2'b10;
7'b??_?_??_00: {outp_temp, outn_temp} = 2'b00;
default: {outp_temp, outn_temp} = 2'bxx;
endcase
end
assign #DELAY outp = outp_temp;
assign #DELAY outn = outn_temp;
endmodule
| 7.511093 |
module aib_frontend_lvshift_core_w_drivers_7__w_sup (
input wire in,
input wire inb,
input wire rst_casc,
input wire rst_out,
input wire rst_outb,
output wire out,
output wire outb,
inout wire VDD,
inout wire VSS
);
wire midn;
wire midp;
aib_frontend_inv_chain_10__w_sup XBUFN (
.in (midn),
.outb(out),
.VDD (VDD),
.VSS (VSS)
);
aib_frontend_inv_chain_10__w_sup XBUFP (
.in (midp),
.outb(outb),
.VDD (VDD),
.VSS (VSS)
);
aib_frontend_lvshift_core_5__w_sup XCORE (
.inn(inb),
.inp(in),
.rst_casc(rst_casc),
.rst_outn(rst_outb),
.rst_outp(rst_out),
.outn(midn),
.outp(midp),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_lvshift_4__w_sup (
input wire in,
input wire rst_casc,
input wire rst_out,
input wire rst_outb,
output wire out,
output wire outb,
inout wire VDD,
inout wire VDD_in,
inout wire VSS
);
wire in_buf;
wire inb_buf;
aib_frontend_inv_chain_9__w_sup XBUF (
.in (in),
.out (in_buf),
.outb(inb_buf),
.VDD (VDD_in),
.VSS (VSS)
);
aib_frontend_lvshift_core_w_drivers_7__w_sup XLEV (
.in(in_buf),
.inb(inb_buf),
.rst_casc(rst_casc),
.rst_out(rst_out),
.rst_outb(rst_outb),
.out(out),
.outb(outb),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_inv_17__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_chain_11__w_sup (
input wire in,
output wire outb,
inout wire VDD,
inout wire VSS
);
aib_frontend_inv_17__w_sup XINV (
.in (in),
.out(outb),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_lvshift_core_6__w_sup (
input wire inn,
input wire inp,
output wire outn,
output wire outp,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
logic outp_temp;
logic outn_temp;
// add first two lines of casez to eliminate any X output. This is done to debug innovus
always_comb begin
casez ({
inp, inn, VDD, VSS
})
4'b00_10: {outp_temp, outn_temp} = 2'b00;
4'b11_10: {outp_temp, outn_temp} = 2'b11;
4'b10_10: {outp_temp, outn_temp} = 2'b10;
4'b01_10: {outp_temp, outn_temp} = 2'b01;
4'b??_00: {outp_temp, outn_temp} = 2'b00;
default: {outp_temp, outn_temp} = 2'bxx;
endcase
end
assign #DELAY outp = outp_temp;
assign #DELAY outn = outn_temp;
endmodule
| 7.511093 |
module aib_frontend_lvshift_core_w_drivers_8__w_sup (
input wire in,
input wire inb,
output wire out,
output wire outb,
inout wire VDD,
inout wire VSS
);
wire midn;
wire midp;
aib_frontend_inv_chain_11__w_sup XBUFN (
.in (midn),
.outb(out),
.VDD (VDD),
.VSS (VSS)
);
aib_frontend_inv_chain_11__w_sup XBUFP (
.in (midp),
.outb(outb),
.VDD (VDD),
.VSS (VSS)
);
aib_frontend_lvshift_core_6__w_sup XCORE (
.inn (inb),
.inp (in),
.outn(midn),
.outp(midp),
.VDD (VDD),
.VSS (VSS)
);
endmodule
| 7.511093 |
module aib_frontend_inv_18__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_19__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_chain_12__w_sup (
input wire in,
output wire out,
output wire outb,
inout wire VDD,
inout wire VSS
);
aib_frontend_inv_18__w_sup XINV0 (
.in (in),
.out(outb),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_inv_19__w_sup XINV1 (
.in (outb),
.out(out),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_inv_20__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_chain_13__w_sup (
input wire in,
output wire outb,
inout wire VDD,
inout wire VSS
);
wire [0:0] mid;
wire out;
aib_frontend_inv_16__w_sup XINV0 (
.in (in),
.out(mid[0]),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_inv_20__w_sup XINV1 (
.in (mid[0]),
.out(out),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_inv_19__w_sup XINV2 (
.in (out),
.out(outb),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_nand_3__w_sup (
input wire [1:0] in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~&in);
endmodule
| 7.511093 |
module aib_frontend_nor_2__w_sup (
input wire [1:0] in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~|in);
endmodule
| 7.511093 |
module aib_frontend_aib_se2diff_match_1__w_sup (
input wire en,
input wire enb,
input wire inn,
input wire inp,
output wire outn,
output wire outp,
inout wire VDD,
inout wire VSS
);
wire nand_out;
wire nor_out;
aib_frontend_inv_chain_13__w_sup XBUFN (
.in (nor_out),
.outb(outn),
.VDD (VDD),
.VSS (VSS)
);
aib_frontend_inv_chain_13__w_sup XBUFP (
.in (nand_out),
.outb(outp),
.VDD (VDD),
.VSS (VSS)
);
aib_frontend_nand_3__w_sup XNAND (
.in ({en, inp}),
.out(nand_out),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_nor_2__w_sup XNOR (
.in ({enb, inn}),
.out(nor_out),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_inv_21__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_22__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_23__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_24__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_passgate_1__w_sup(
input wire en,
input wire enb,
input wire s,
output trireg d,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
wire tmp;
assign #DELAY tmp = VSS ? 1'bx : (~VDD ? 1'b0 : s);
tranif1 XTRN1 (d, tmp, en );
tranif0 XTRN0 (d, tmp, enb);
endmodule
| 7.511093 |
module aib_frontend_se_to_diff_1__w_sup (
input wire in,
output wire outn,
output wire outp,
inout wire VDD,
inout wire VSS
);
wire midn_inv;
wire midn_pass0;
wire midn_pass1;
wire midp;
aib_frontend_inv_21__w_sup XINVN0 (
.in (in),
.out(midn_inv),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_inv_22__w_sup XINVN1 (
.in (midn_inv),
.out(midp),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_inv_23__w_sup XINVN2 (
.in (midp),
.out(outn),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_inv_24__w_sup XINVP0 (
.in (in),
.out(midn_pass0),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_inv_23__w_sup XINVP1 (
.in (midn_pass1),
.out(outp),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_passgate_1__w_sup XPASS (
.en (VDD),
.enb(VSS),
.s (midn_pass0),
.d (midn_pass1),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_nand_4__w_sup (
input wire [1:0] in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~&in);
endmodule
| 7.511093 |
module aib_frontend_aib_se2diff_1__w_sup (
input wire en,
input wire enb,
input wire in,
output wire outn,
output wire outp,
inout wire VDD,
inout wire VSS
);
wire inb;
wire nc;
aib_frontend_se_to_diff_1__w_sup XCORE (
.in (inb),
.outn(outp),
.outp(outn),
.VDD (VDD),
.VSS (VSS)
);
aib_frontend_nor_2__w_sup XDUM (
.in ({enb, VDD}),
.out(nc),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_nand_4__w_sup XNAND (
.in ({en, in}),
.out(inb),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_aib_rxanlg_core_1__w_sup (
input wire clk_en,
input wire data_en,
input wire iclkn,
input wire iopad,
input wire por,
output wire oclkn,
output wire oclkp,
output wire odat,
output wire odat_async,
output wire por_vccl,
output wire porb_vccl,
inout wire VDDCore,
inout wire VDDIO,
inout wire VSS
);
wire clk_en_vccl;
wire clk_enb_vccl;
wire data_en_vccl;
wire data_enb_vccl;
wire dumn;
wire dump;
wire oclkn_vccl;
wire oclkp_vccl;
wire odatb;
wire odatn_vccl;
wire odatp_vccl;
wire por_buf;
wire porb_buf;
wire [2:0] unused;
aib_frontend_inv_14__w_sup XDUM (
.in (VSS),
.out(unused[0]),
.VDD(VDDCore),
.VSS(VSS)
);
aib_frontend_inv_14__w_sup XINV (
.in (odatb),
.out(odat_async),
.VDD(VDDCore),
.VSS(VSS)
);
aib_frontend_lvshift_core_w_drivers_6__w_sup XLV_CLK (
.in(oclkp_vccl),
.inb(oclkn_vccl),
.rst_casc(porb_buf),
.rst_out(por_buf),
.rst_outb(VSS),
.out(oclkp),
.outb(oclkn),
.VDD(VDDCore),
.VSS(VSS)
);
aib_frontend_lvshift_4__w_sup XLV_CLK_EN (
.in(clk_en),
.rst_casc(porb_vccl),
.rst_out(por_vccl),
.rst_outb(VSS),
.out(clk_en_vccl),
.outb(clk_enb_vccl),
.VDD(VDDIO),
.VDD_in(VDDCore),
.VSS(VSS)
);
aib_frontend_lvshift_core_w_drivers_6__w_sup XLV_DATA (
.in(odatp_vccl),
.inb(odatn_vccl),
.rst_casc(porb_buf),
.rst_out(por_buf),
.rst_outb(VSS),
.out(odat),
.outb(odatb),
.VDD(VDDCore),
.VSS(VSS)
);
aib_frontend_lvshift_4__w_sup XLV_DATA_EN (
.in(data_en),
.rst_casc(porb_vccl),
.rst_out(por_vccl),
.rst_outb(VSS),
.out(data_en_vccl),
.outb(data_enb_vccl),
.VDD(VDDIO),
.VDD_in(VDDCore),
.VSS(VSS)
);
aib_frontend_lvshift_core_w_drivers_8__w_sup XLV_DUM (
.in (dump),
.inb (dumn),
.out (unused[1]),
.outb(unused[2]),
.VDD (VDDIO),
.VSS (VSS)
);
aib_frontend_lvshift_core_w_drivers_8__w_sup XLV_POR (
.in (por_buf),
.inb (porb_buf),
.out (por_vccl),
.outb(porb_vccl),
.VDD (VDDIO),
.VSS (VSS)
);
aib_frontend_inv_chain_12__w_sup XPOR (
.in (por),
.out (por_buf),
.outb(porb_buf),
.VDD (VDDCore),
.VSS (VSS)
);
aib_frontend_inv_chain_12__w_sup XPOR_DUM (
.in (VSS),
.out (dump),
.outb(dumn),
.VDD (VDDCore),
.VSS (VSS)
);
aib_frontend_aib_se2diff_match_1__w_sup XSE_CLK (
.en (clk_en_vccl),
.enb (clk_enb_vccl),
.inn (iclkn),
.inp (iopad),
.outn(oclkn_vccl),
.outp(oclkp_vccl),
.VDD (VDDIO),
.VSS (VSS)
);
aib_frontend_aib_se2diff_1__w_sup XSE_DATA (
.en (data_en_vccl),
.enb (data_enb_vccl),
.in (iopad),
.outn(odatn_vccl),
.outp(odatp_vccl),
.VDD (VDDIO),
.VSS (VSS)
);
endmodule
| 7.511093 |
module aib_frontend_aib_driver_pu_pd_2__w_sup (
input wire pden,
input wire puenb,
output wire out,
inout wire VDD,
inout wire VSS
);
logic out_temp;
always_comb begin
// puenb connects to PMOS, pden connects to NMOS
casez ({
VDD, VSS, puenb, pden
})
4'b10_00: out_temp = 1'b1;
4'b10_01: out_temp = 1'bx;
4'b10_10: out_temp = 1'bz;
4'b10_11: out_temp = 1'b0;
4'b00_??: out_temp = 1'b0;
default: out_temp = 1'bx;
endcase
end
assign (weak0, weak1) out = out_temp;
endmodule
| 7.511093 |
module aib_frontend_current_summer_1__w_sup (
input wire [6:0] in,
output wire out
);
tran tr0 (in[0], out);
tran tr1 (in[1], out);
tran tr2 (in[2], out);
tran tr3 (in[3], out);
tran tr4 (in[4], out);
tran tr5 (in[5], out);
tran tr6 (in[6], out);
endmodule
| 7.511093 |
module aib_frontend_nand_5__w_sup (
input wire [1:0] in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~&in);
endmodule
| 7.511093 |
module aib_frontend_nor_3__w_sup (
input wire [1:0] in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~|in);
endmodule
| 7.511093 |
module aib_frontend_aib_driver_pu_pd_3__w_sup (
input wire pden,
input wire puenb,
output wire out,
inout wire VDD,
inout wire VSS
);
logic out_temp;
always_comb begin
// puenb connects to PMOS, pden connects to NMOS
casez ({
VDD, VSS, puenb, pden
})
4'b10_00: out_temp = 1'b1;
4'b10_01: out_temp = 1'bx;
4'b10_10: out_temp = 1'bz;
4'b10_11: out_temp = 1'b0;
4'b00_??: out_temp = 1'b0;
default: out_temp = 1'bx;
endcase
end
assign out = out_temp;
endmodule
| 7.511093 |
module aib_frontend_aib_driver_output_unit_cell_1__w_sup (
input wire en,
input wire enb,
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
wire nand_pu;
wire nor_pd;
aib_frontend_nand_5__w_sup XNAND (
.in ({en, in}),
.out(nand_pu),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_nor_3__w_sup XNOR (
.in ({enb, in}),
.out(nor_pd),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_aib_driver_pu_pd_3__w_sup Xpupd (
.pden (nor_pd),
.puenb(nand_pu),
.out (out),
.VDD (VDD),
.VSS (VSS)
);
endmodule
| 7.511093 |
module aib_frontend_aib_driver_output_driver_1__w_sup (
input wire din,
input wire [1:0] n_enb_drv,
input wire [1:0] p_en_drv,
input wire tristate,
input wire tristateb,
input wire weak_pden,
input wire weak_puenb,
output wire txpadout,
inout wire VDD,
inout wire VSS
);
wire [6:0] txpadout_tmp;
aib_frontend_aib_driver_pu_pd_2__w_sup XPUPD (
.pden (weak_pden),
.puenb(weak_puenb),
.out (txpadout_tmp[6]),
.VDD (VDD),
.VSS (VSS)
);
aib_frontend_current_summer_1__w_sup XSUM (
.in (txpadout_tmp[6:0]),
.out(txpadout)
);
aib_frontend_aib_driver_output_unit_cell_1__w_sup XUNIT_5 (
.en (p_en_drv[0]),
.enb(n_enb_drv[0]),
.in (din),
.out(txpadout_tmp[5]),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_aib_driver_output_unit_cell_1__w_sup XUNIT_4 (
.en (p_en_drv[1]),
.enb(n_enb_drv[1]),
.in (din),
.out(txpadout_tmp[4]),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_aib_driver_output_unit_cell_1__w_sup XUNIT_3 (
.en (p_en_drv[1]),
.enb(n_enb_drv[1]),
.in (din),
.out(txpadout_tmp[3]),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_aib_driver_output_unit_cell_1__w_sup XUNIT_2 (
.en (tristateb),
.enb(tristate),
.in (din),
.out(txpadout_tmp[2]),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_aib_driver_output_unit_cell_1__w_sup XUNIT_1 (
.en (tristateb),
.enb(tristate),
.in (din),
.out(txpadout_tmp[1]),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_aib_driver_output_unit_cell_1__w_sup XUNIT_0 (
.en (tristateb),
.enb(tristate),
.in (din),
.out(txpadout_tmp[0]),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_inv_25__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_26__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_chain_14__w_sup (
input wire in,
output wire out,
output wire outb,
inout wire VDD,
inout wire VSS
);
aib_frontend_inv_25__w_sup XINV0 (
.in (in),
.out(outb),
.VDD(VDD),
.VSS(VSS)
);
aib_frontend_inv_26__w_sup XINV1 (
.in (outb),
.out(out),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_inv_27__w_sup (
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in);
endmodule
| 7.511093 |
module aib_frontend_inv_chain_15__w_sup (
input wire in,
output wire outb,
inout wire VDD,
inout wire VSS
);
aib_frontend_inv_27__w_sup XINV (
.in (in),
.out(outb),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_lvshift_core_7__w_sup (
input wire inn,
input wire inp,
input wire rst_casc,
input wire rst_outn,
input wire rst_outp,
output wire outn,
output wire outp,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
logic outp_temp;
logic outn_temp;
// add first two lines of casez to eliminate any X output. This is done to debug innovus
always_comb begin
casez ({
rst_outp, rst_outn, rst_casc, inp, inn, VDD, VSS
})
7'b00_1_00_10: {outp_temp, outn_temp} = 2'b00;
7'b00_1_11_10: {outp_temp, outn_temp} = 2'b11;
7'b10_0_??_10: {outp_temp, outn_temp} = 2'b01;
7'b01_0_??_10: {outp_temp, outn_temp} = 2'b10;
7'b00_1_10_10: {outp_temp, outn_temp} = 2'b10;
7'b00_1_01_10: {outp_temp, outn_temp} = 2'b01;
7'b10_1_10_10: {outp_temp, outn_temp} = 2'b01;
7'b01_1_01_10: {outp_temp, outn_temp} = 2'b10;
7'b??_?_??_00: {outp_temp, outn_temp} = 2'b00;
default: {outp_temp, outn_temp} = 2'bxx;
endcase
end
assign #DELAY outp = outp_temp;
assign #DELAY outn = outn_temp;
endmodule
| 7.511093 |
module aib_frontend_lvshift_core_w_drivers_9__w_sup (
input wire in,
input wire inb,
input wire rst_casc,
input wire rst_out,
input wire rst_outb,
output wire out,
inout wire VDD,
inout wire VSS
);
wire midn;
wire midp;
aib_frontend_inv_chain_15__w_sup XBUFN (
.in (midn),
.outb(out),
.VDD (VDD),
.VSS (VSS)
);
aib_frontend_lvshift_core_7__w_sup XCORE (
.inn(inb),
.inp(in),
.rst_casc(rst_casc),
.rst_outn(rst_outb),
.rst_outp(rst_out),
.outn(midn),
.outp(midp),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_lvshift_5__w_sup (
input wire in,
input wire rst_casc,
input wire rst_out,
input wire rst_outb,
output wire out,
inout wire VDD,
inout wire VDD_in,
inout wire VSS
);
wire in_buf;
wire inb_buf;
aib_frontend_inv_chain_14__w_sup XBUF (
.in (in),
.out (in_buf),
.outb(inb_buf),
.VDD (VDD_in),
.VSS (VSS)
);
aib_frontend_lvshift_core_w_drivers_9__w_sup XLEV (
.in(in_buf),
.inb(inb_buf),
.rst_casc(rst_casc),
.rst_out(rst_out),
.rst_outb(rst_outb),
.out(out),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_lvshift_core_w_drivers_10__w_sup (
input wire in,
input wire inb,
input wire rst_casc,
input wire rst_out,
input wire rst_outb,
output wire outb,
inout wire VDD,
inout wire VSS
);
wire midn;
wire midp;
aib_frontend_inv_chain_10__w_sup XBUFP (
.in (midp),
.outb(outb),
.VDD (VDD),
.VSS (VSS)
);
aib_frontend_lvshift_core_5__w_sup XCORE (
.inn(inb),
.inp(in),
.rst_casc(rst_casc),
.rst_outn(rst_outb),
.rst_outp(rst_out),
.outn(midn),
.outp(midp),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_lvshift_6__w_sup (
input wire in,
input wire rst_casc,
input wire rst_out,
input wire rst_outb,
output wire out,
output wire outb,
inout wire VDD,
inout wire VDD_in,
inout wire VSS
);
wire in_buf;
wire inb_buf;
aib_frontend_inv_chain_9__w_sup XBUF (
.in (in),
.out (in_buf),
.outb(inb_buf),
.VDD (VDD_in),
.VSS (VSS)
);
aib_frontend_lvshift_core_w_drivers_10__w_sup XLEV (
.in(in_buf),
.inb(inb_buf),
.rst_casc(rst_casc),
.rst_out(rst_out),
.rst_outb(rst_outb),
.outb(outb),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_lvshift_core_w_drivers_11__w_sup (
input wire in,
input wire inb,
input wire rst_casc,
input wire rst_out,
input wire rst_outb,
output wire out,
inout wire VDD,
inout wire VSS
);
wire midn;
wire midp;
aib_frontend_inv_chain_10__w_sup XBUFN (
.in (midn),
.outb(out),
.VDD (VDD),
.VSS (VSS)
);
aib_frontend_lvshift_core_5__w_sup XCORE (
.inn(inb),
.inp(in),
.rst_casc(rst_casc),
.rst_outn(rst_outb),
.rst_outp(rst_out),
.outn(midn),
.outp(midp),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_lvshift_7__w_sup (
input wire in,
input wire rst_casc,
input wire rst_out,
input wire rst_outb,
output wire out,
inout wire VDD,
inout wire VDD_in,
inout wire VSS
);
wire in_buf;
wire inb_buf;
aib_frontend_inv_chain_9__w_sup XBUF (
.in (in),
.out (in_buf),
.outb(inb_buf),
.VDD (VDD_in),
.VSS (VSS)
);
aib_frontend_lvshift_core_w_drivers_11__w_sup XLEV (
.in(in_buf),
.inb(inb_buf),
.rst_casc(rst_casc),
.rst_out(rst_out),
.rst_outb(rst_outb),
.out(out),
.VDD(VDD),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_aib_txanlg_core_1__w_sup (
input wire din,
input wire [1:0] indrv_buf,
input wire [1:0] ipdrv_buf,
input wire itx_en_buf,
input wire por_vccl,
input wire porb_vccl,
input wire weak_pulldownen,
input wire weak_pullupenb,
output wire txpadout,
inout wire VDDCore,
inout wire VDDIO,
inout wire VSS
);
wire din_io;
wire [1:0] nen_drv_io;
wire [1:0] nen_drvb_io;
wire pden_io;
wire [1:0] pen_drv_io;
wire puenb_io;
wire tristate_io;
wire tristateb_io;
aib_frontend_aib_driver_output_driver_1__w_sup XDRV (
.din(din_io),
.n_enb_drv(nen_drvb_io[1:0]),
.p_en_drv(pen_drv_io[1:0]),
.tristate(tristate_io),
.tristateb(tristateb_io),
.weak_pden(pden_io),
.weak_puenb(puenb_io),
.txpadout(txpadout),
.VDD(VDDIO),
.VSS(VSS)
);
aib_frontend_lvshift_5__w_sup XLV_DIN (
.in(din),
.rst_casc(porb_vccl),
.rst_out(por_vccl),
.rst_outb(VSS),
.out(din_io),
.VDD(VDDIO),
.VDD_in(VDDCore),
.VSS(VSS)
);
aib_frontend_lvshift_4__w_sup XLV_ITX_EN (
.in(itx_en_buf),
.rst_casc(porb_vccl),
.rst_out(por_vccl),
.rst_outb(VSS),
.out(tristateb_io),
.outb(tristate_io),
.VDD(VDDIO),
.VDD_in(VDDCore),
.VSS(VSS)
);
aib_frontend_lvshift_6__w_sup XLV_NDRV_1 (
.in(indrv_buf[1]),
.rst_casc(porb_vccl),
.rst_out(por_vccl),
.rst_outb(VSS),
.out(nen_drv_io[1]),
.outb(nen_drvb_io[1]),
.VDD(VDDIO),
.VDD_in(VDDCore),
.VSS(VSS)
);
aib_frontend_lvshift_6__w_sup XLV_NDRV_0 (
.in(indrv_buf[0]),
.rst_casc(porb_vccl),
.rst_out(por_vccl),
.rst_outb(VSS),
.out(nen_drv_io[0]),
.outb(nen_drvb_io[0]),
.VDD(VDDIO),
.VDD_in(VDDCore),
.VSS(VSS)
);
aib_frontend_lvshift_7__w_sup XLV_PD (
.in(weak_pulldownen),
.rst_casc(porb_vccl),
.rst_out(VSS),
.rst_outb(por_vccl),
.out(pden_io),
.VDD(VDDIO),
.VDD_in(VDDCore),
.VSS(VSS)
);
aib_frontend_lvshift_7__w_sup XLV_PDRV_1 (
.in(ipdrv_buf[1]),
.rst_casc(porb_vccl),
.rst_out(por_vccl),
.rst_outb(VSS),
.out(pen_drv_io[1]),
.VDD(VDDIO),
.VDD_in(VDDCore),
.VSS(VSS)
);
aib_frontend_lvshift_7__w_sup XLV_PDRV_0 (
.in(ipdrv_buf[0]),
.rst_casc(porb_vccl),
.rst_out(por_vccl),
.rst_outb(VSS),
.out(pen_drv_io[0]),
.VDD(VDDIO),
.VDD_in(VDDCore),
.VSS(VSS)
);
aib_frontend_lvshift_7__w_sup XLV_PU (
.in(weak_pullupenb),
.rst_casc(porb_vccl),
.rst_out(VSS),
.rst_outb(por_vccl),
.out(puenb_io),
.VDD(VDDIO),
.VDD_in(VDDCore),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_aib_frontend_core_1__w_sup (
input wire clk_en,
input wire data_en,
input wire din,
input wire iclkn,
input wire [1:0] indrv_buf,
input wire [1:0] ipdrv_buf,
input wire itx_en_buf,
input wire por,
input wire rxpadin,
input wire weak_pulldownen,
input wire weak_pullupenb,
output wire oclkn,
output wire oclkp,
output wire odat,
output wire odat_async,
output wire txpadout,
inout wire VDDCore,
inout wire VDDIO,
inout wire VSS
);
wire por_vccl;
wire porb_vccl;
aib_frontend_aib_rxanlg_core_1__w_sup XRX (
.clk_en(clk_en),
.data_en(data_en),
.iclkn(iclkn),
.iopad(rxpadin),
.por(por),
.oclkn(oclkn),
.oclkp(oclkp),
.odat(odat),
.odat_async(odat_async),
.por_vccl(por_vccl),
.porb_vccl(porb_vccl),
.VDDCore(VDDCore),
.VDDIO(VDDIO),
.VSS(VSS)
);
aib_frontend_aib_txanlg_core_1__w_sup XTX (
.din(din),
.indrv_buf(indrv_buf[1:0]),
.ipdrv_buf(ipdrv_buf[1:0]),
.itx_en_buf(itx_en_buf),
.por_vccl(por_vccl),
.porb_vccl(porb_vccl),
.weak_pulldownen(weak_pulldownen),
.weak_pullupenb(weak_pullupenb),
.txpadout(txpadout),
.VDDCore(VDDCore),
.VDDIO(VDDIO),
.VSS(VSS)
);
endmodule
| 7.511093 |
module aib_frontend_metal_short_m6_1__w_sup (
inout wire MINUS,
inout wire PLUS
);
tran tr (PLUS, MINUS);
endmodule
| 7.511093 |
module aib_frontend_esd_diode_ndio_1__w_sup (
inout wire MINUS,
inout wire PLUS
);
always @(PLUS) begin
if (PLUS === 1'bz) $display("ESD ndio error: PLUS port is 1'bz");
end
endmodule
| 7.511093 |
module aib_frontend_esd_diode_pdio_1__w_sup (
inout wire MINUS,
inout wire PLUS
);
always @(MINUS) begin
if (MINUS === 1'bz) $display("ESD pdio error: MINUS port is 1'bz");
end
endmodule
| 7.511093 |
module aibcr3_inv_split_align (
din,
dout,
vccl,
vssl
);
input din;
output dout;
input vssl;
input vccl;
assign dout = ~din;
endmodule
| 7.372862 |
module aibcr3_io_nand_delay_line_min (
input nfrzdrv,
input in_p,
input in_n,
output out_p,
output out_n
);
`ifdef TIMESCALE_EN
timeunit 1ps; timeprecision 1ps;
`endif
parameter NAND_DELAY = 20;
wire fout_p;
wire fout_n;
wire osc_out_p;
wire osc_out_n;
//---------------------------------------------------------------------------------------------------------------------------------------------
//
//---------------------------------------------------------------------------------------------------------------------------------------------
aibcr3_io_cmos_nand_x1 UD00 (
.in_p (in_p),
.in_n (in_n),
.bk (1'b0),
.ci_p (1'b1),
.ci_n (1'b1),
.out_p(fout_p),
.out_n(fout_n),
.co_p (),
.co_n ()
);
aibcr3_io_cmos_8ph_interpolator xinterp (
.nfrzdrv (nfrzdrv),
.fout_p (fout_p),
.fout_n (fout_n),
.gray (3'b000),
.out_p (out_p),
.out_n (out_n),
.osc_out_p(osc_out_p),
.osc_out_n(osc_out_n)
);
endmodule
| 6.565557 |
module aibcr3_io_nand_delay_line_min_rep (
input nfrzdrv,
input in_p,
input in_n,
output out_p,
output out_n
);
`ifdef TIMESCALE_EN
timeunit 1ps; timeprecision 1ps;
`endif
parameter NAND_DELAY = 20;
wire fout_p;
wire fout_n;
wire osc_out_p;
wire osc_out_n;
//---------------------------------------------------------------------------------------------------------------------------------------------
//
//---------------------------------------------------------------------------------------------------------------------------------------------
aibcr3_io_cmos_nand_x1 UD00 (
.in_p (in_p),
.in_n (in_n),
.bk (1'b0),
.ci_p (1'b1),
.ci_n (1'b1),
.out_p(fout_p),
.out_n(fout_n),
.co_p (),
.co_n ()
);
aibcr3_io_cmos_8ph_interpolator_rep xinterp (
.nfrzdrv (nfrzdrv),
.fout_p (fout_p),
.fout_n (fout_n),
.gray (3'b000),
.out_p (out_p),
.out_n (out_n),
.osc_out_p(osc_out_p),
.osc_out_n(osc_out_n)
);
endmodule
| 6.565557 |
module aibcr3_io_nand_x128_delay_line (
input nfrzdrv,
input in_p,
input in_n,
input osc_mode, // Mux control for the x64 ring oscillator
input osc_in_p, // input for the x64 ring oscillator
input osc_in_n, // input for the x64 ring oscillator
output osc_out_p, // output for the x64 ring oscillator
output osc_out_n, // output for the x64 ring oscillator
input [6:0] f_gray,
input [2:0] i_gray,
output out_p,
output out_n
);
`ifdef TIMESCALE_EN
timeunit 1ps; timeprecision 1ps;
`endif
parameter NAND_DELAY = 20;
wire fout_p;
wire fout_n;
wire x128_in_p;
wire x128_in_n;
//---------------------------------------------------------------------------------------------------------------------------------------------
// input mux
//---------------------------------------------------------------------------------------------------------------------------------------------
assign x128_in_p = osc_mode ? osc_in_p : in_p;
assign x128_in_n = osc_mode ? osc_in_n : in_n;
aibcr3_io_cmos_nand_x128 #(
.NAND_DELAY(NAND_DELAY)
) xnand128 (
.in_p (x128_in_p),
.in_n (x128_in_n),
.gray (f_gray[6:0]),
.out_p(fout_p),
.out_n(fout_n)
);
aibcr3_io_cmos_8ph_interpolator xinterp (
.nfrzdrv (nfrzdrv),
.fout_p (fout_p),
.fout_n (fout_n),
.gray (i_gray[2:0]),
.out_p (out_p),
.out_n (out_n),
.osc_out_p(osc_out_p),
.osc_out_n(osc_out_n)
);
endmodule
| 6.565557 |
module aibcr3_latch (
input wire E,
input wire CDN,
//input wire vcc,
//input wire vss,
input wire D,
output reg Q
);
always @(*) begin
if (!CDN) begin
Q <= 0;
end else begin
if (E) Q <= D;
end
end
endmodule
| 8.144334 |
module aibcr3_nd2d0_custom (
zn,
a1,
a2,
vcc_regphy,
vss_io
);
output zn;
input a2;
input a1;
input vss_io;
input vcc_regphy;
assign zn = ~(a1 && a2);
endmodule
| 6.734436 |
module aibcr3_quadph_code_gen #(
parameter FF_DELAY = 200
) (
input wire clk, //reference clock from pll
input wire reset_n, //output for dll reset
input wire [9:0] pvt_ref_binary, //output binary pvt value for delay chain
input wire rb_quad_code, //select between original or quadrature codes
output reg [9:0] pvt_ref_quad_binary //quadrature code (binary) for delay chain
);
`ifdef TIMESCALE_EN
timeunit 1ps; timeprecision 1ps;
`endif
wire [6:0] coarse_bin;
reg [2:0] fint_bin;
wire [2:0] fine_bin;
reg [8:0] coarse_divided_bin;
reg [4:0] fine_divided_bin, coarse_frac_bin;
always @(*) begin
if (~reset_n) begin
coarse_divided_bin = 9'b0_0000_0000;
fine_divided_bin = 5'b0_0000;
coarse_frac_bin = 5'b0_0000;
fint_bin = 3'b000;
end else begin
coarse_divided_bin = {2'b00, pvt_ref_binary[9:3]};
fine_divided_bin = {2'b00, pvt_ref_binary[2:0]};
// coarse_frac_bin = {1'b0,coarse_divided_bin[1:0],2'b00}; //****need to finalize what's the ratio between coarse/fine steps. current coding assumes 20ps/5ps=4
coarse_frac_bin = {coarse_divided_bin[1:0], 3'b000};
fint_bin = coarse_frac_bin[4:2] + fine_divided_bin[4:2];
if ((fine_divided_bin[1:0] >= 2'd2)) begin
fint_bin = fint_bin + 3'b001;
end else begin
fint_bin = fint_bin;
end
end
end
assign coarse_bin = coarse_divided_bin[8:2];
assign fine_bin = fint_bin;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
pvt_ref_quad_binary <= #FF_DELAY 10'b00_0000_0000;
end else
case (rb_quad_code)
1'b0: pvt_ref_quad_binary <= #FF_DELAY pvt_ref_binary;
1'b1: pvt_ref_quad_binary <= #FF_DELAY{coarse_bin, fine_bin};
default: pvt_ref_quad_binary <= #FF_DELAY{coarse_bin, fine_bin};
endcase
end
endmodule
| 6.934796 |
module aibcr3_rxdat_mimic (
input wire odat_in,
input wire vcc_aibcr,
input wire vss_aibcr,
output wire odat_out
);
assign odat_out = odat_in;
endmodule
| 7.432382 |
module aibcr3_split_align (
input din, // input
output dout_p, // splitted output positive
output dout_n // splitted output negative
);
`ifdef TIMESCALE_EN
timeunit 1ps; timeprecision 1ps;
`endif
parameter INV_DELAY = 15; // 15ps
assign #(2 * INV_DELAY) dout_p = din;
assign #(2 * INV_DELAY) dout_n = ~din;
endmodule
| 8.544277 |
module aibcr3_str_ioload (
in,
vcc,
vssl
);
input in, vcc, vssl;
// Buses in the design
wire net5;
// specify
// specparam CDS_LIBNAME = "aibcr_lib";
// specparam CDS_CELLNAME = "aibcr_str_ioload";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
assign net5 = ~in;
endmodule
| 6.722411 |
module aibcr3_sync_2ff (
CDN,
CP,
D,
SE,
SI,
Q
);
input CDN, CP, D, SE, SI;
output reg Q;
wire data;
reg flop_0;
assign data = SE ? SI : D;
always @(posedge CP or negedge CDN)
if (!CDN) {Q, flop_0} <= 0;
else if (CDN) {Q, flop_0} <= {flop_0, data};
else {Q, flop_0} <= 0;
endmodule
| 6.716574 |
module aibcr3_sync_3ff (
CDN,
CP,
D,
SE,
SI,
Q
);
input CDN, CP, D, SE, SI;
output reg Q;
wire data;
reg flop_1, flop_0;
assign data = SE ? SI : D;
always @(posedge CP or negedge CDN)
if (!CDN) {Q, flop_1, flop_0} <= 0;
else if (CDN) {Q, flop_1, flop_0} <= {flop_1, flop_0, data};
else {Q, flop_1, flop_0} <= 0;
endmodule
| 6.622928 |
module aibcr3_txdat_mimic (
input wire idat_in,
input wire vcc_aibcr,
input wire vss_aibcr,
output wire idat_out
);
assign idat_out = idat_in;
endmodule
| 8.179853 |
module aibcr3_ulvt16_2xarstsyncdff1_b2 (
CLR_N,
CK,
D,
SE,
SI,
Q
);
input CLR_N, CK, D, SE, SI;
output reg Q;
wire data;
reg flop_0;
assign data = SE ? SI : D;
always @(posedge CK or negedge CLR_N)
if (!CLR_N) {Q, flop_0} <= 0;
else if (CLR_N) {Q, flop_0} <= {flop_0, data};
else {Q, flop_0} <= 0;
endmodule
| 8.164146 |
module aibcr3_ulvt16_dffcdn_cust (
input wire CK,
input wire CDN,
input wire D,
output reg Q
);
always @(posedge CK or negedge CDN) begin
if (!CDN) begin
Q <= 1'b0;
end else begin
Q <= D;
end
end
endmodule
| 8.164146 |
module aibcr3_ulvt16_dffsdn_cust (
input wire CK,
input wire SDN,
input wire D,
output reg Q
);
always @(posedge CK or negedge SDN) begin
if (!SDN) begin
Q <= 1'b1;
end else begin
Q <= D;
end
end
endmodule
| 8.164146 |
module aibndaux_top_slave (
o_crdet,
u_crdet,
u_crdet_r,
u_dn_por,
u_dn_por_r,
i_dn_por,
i_crdet_ovrd
);
output o_crdet;
inout u_crdet, u_crdet_r, u_dn_por, u_dn_por_r;
input i_dn_por, i_crdet_ovrd;
wire o_crete_detect;
assign vccl_aibndaux = 1'b1;
assign vssl_aibndaux = 1'b0;
assign o_crdet = o_crete_detect | i_crdet_ovrd;
aibndaux_aliasd aliasd2 (
.PLUS (u_dn_por),
.MINUS(u_dn_por_r)
);
aibndaux_pasred_simple xpasred (
.crete_detect(o_crete_detect),
.iopad_crdet(u_crdet),
.vssl_aibndaux(vssl_aibndaux),
.vccl_aibndaux(vccl_aibndaux),
.iopad_dn_por(u_dn_por),
.dn_por(i_dn_por)
);
endmodule
| 6.631813 |
module aibndpnr_dll_atech_clkgate_cgc00 (
input wire clk,
input wire en,
output wire clkout
);
reg o;
always @(en, clk) begin
if (~clk) begin
o <= en;
end
end
assign clkout = clk & o;
endmodule
| 7.015995 |
module aibndpnr_dll_atech_clkgate_cgc01 (
input wire clk,
input wire en,
input wire te,
output wire clkout
);
wire d;
reg o;
assign d = en | te;
always @(d, clk) begin
if (~clk) begin
o <= d;
end
end
assign clkout = clk & o;
endmodule
| 7.015995 |
module aibndpnr_dll_atech_clkmux
// IMPORTANT NOTICE: This clock mux behavioral model
// must be mapped to either a transmission gate mux
// or a pass gate mux in the standard cell library.
// Failure to comply will result in glitch hazards.
(
input wire clk1,
input wire clk2,
input wire s, // Select
output wire clkout
);
assign clkout = s ? clk1 : clk2; // 2:1 clock mux
endmodule
| 7.015995 |
module aibndpnr_dll_ctrl (
input wire clk, //reference clock from pll
input wire reinit, //initialization enable
input wire entest, //test enable
input wire ndllrst_in, //reset from core
input wire rb_dll_en, //dll enable
input wire rb_dll_rst_en, //dll reset enable
input wire atpg_en_n, //atpg
input wire test_clr_n, //test clear
output wire dll_reset_n //output for dll reset
);
`ifdef TIMESCALE_EN
timeunit 1ps; timeprecision 1ps;
`endif
wire eni;
wire dll_rst;
////////////////////////////////////////////////////////////////////
// //
// reset and preset //
// //
////////////////////////////////////////////////////////////////////
assign dll_rst = (rb_dll_rst_en) ? ~ndllrst_in : 1'b0; //core reset at "1" if core_reset enabled
assign eni = ~entest & rb_dll_en & (~reinit) & (~dll_rst); //dll enable and non-test
cdclib_rst_n_sync unrst (
.rst_n(eni),
.rst_n_bypass(test_clr_n),
.clk(clk),
.scan_mode_n(atpg_en_n),
.rst_n_sync(dll_reset_n)
);
endmodule
| 7.015995 |
module aibnd_aliasd (
PLUS,
MINUS
);
input PLUS;
output MINUS;
assign MINUS = PLUS;
endmodule
| 6.717766 |
module aibnd_analog (
oclkn,
oclkp,
odat,
odat_async,
iopad,
clk_en,
data_en,
iclkn,
ndrv_enb,
pdrv_en,
txdin,
vccl_aibnd,
vssl_aibnd,
weak_pulldownen,
weak_pullupenb
);
output oclkn, oclkp, odat, odat_async;
inout iopad;
input clk_en, data_en, iclkn, txdin, vccl_aibnd, vssl_aibnd, weak_pulldownen, weak_pullupenb;
input [15:0] pdrv_en;
input [15:0] ndrv_enb;
aibnd_txanlg xtxbuf (
.vssl_aibnd(vssl_aibnd),
.vccl_aibnd(vccl_aibnd),
.ndrv_enb(ndrv_enb[15:0]),
.weak_pullupenb(weak_pullupenb),
.txpadout(iopad),
.din(txdin),
.pdrv_en(pdrv_en[15:0]),
.weak_pulldownen(weak_pulldownen)
);
aibnd_rxanlg xrxbuf (
.vssl_aibnd(vssl_aibnd),
.vccl_aibnd(vccl_aibnd),
.odat_async(odat_async),
.data_en(data_en),
.clk_en(clk_en),
.odat(odat),
.oclkn(oclkn),
.oclkp(oclkp),
.iopad(iopad),
.iclkn(iclkn)
);
aibnd_d8xsesdd1 xesd1 (
.vssl_aibnd(vssl_aibnd),
.vccl_aibnd(vccl_aibnd),
.iopad(iopad)
);
aibnd_d8xsesdd2 xesd2 (
.vssl_aibnd(vssl_aibnd),
.vccl_aibnd(vccl_aibnd),
.iopad(iopad)
);
endmodule
| 6.65117 |
module aibnd_avmm_rst_sync (
pcs_clk,
pcs_clkb,
resetb_sync_buf,
avmm_clk,
avmm_rstb,
vccl_aibnd,
vssl_aibnd
);
output pcs_clk, pcs_clkb, resetb_sync_buf;
input avmm_clk, avmm_rstb, vccl_aibnd, vssl_aibnd;
wire gated_avmm_clk, pcs_clk, reset_b_sync, resetb_sync_buf, avmm_clk, avmm_clk_inv, pcs_clkb, clockgateb; // Conversion Sript Generated
// specify
// specparam CDS_LIBNAME = "aibnd_lib";
// specparam CDS_CELLNAME = "aibnd_avmm_rst_sync";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
assign pcs_clk = gated_avmm_clk;
assign resetb_sync_buf = reset_b_sync;
assign avmm_clk_inv = !avmm_clk;
assign pcs_clkb = !gated_avmm_clk;
aibnd_2ff_scan xsync (
.d (vccl_aibnd),
.clk(avmm_clk),
.o (reset_b_sync) /*`ifndef INTCNOPWR , .vcc(vccl_aibnd) `endif*/,
.rb (avmm_rstb),
.si (vssl_aibnd) /*`ifndef INTCNOPWR , .vss(vssl_aibnd) `endif*/,
.so (nc_so_sync),
.ssb(vccl_aibnd)
);
aibnd_ff_r fyn0 (
.o (clockgateb),
.d (vccl_aibnd),
.clk(avmm_clk_inv) /*`ifndef INTCNOPWR , .vss(vssl_aibnd) , .vcc(vccl_aibnd) `endif*/,
.rb (reset_b_sync)
);
assign gated_avmm_clk = avmm_clk & clockgateb;
endmodule
| 6.925604 |
module aibnd_dcc_sense (
up,
vcc_io,
vcc_regphy,
vss_io,
clk_dcc,
dll_reset_n,
nfrzdrv,
pvt_ref_half_gry
);
output up;
inout vcc_io, vcc_regphy, vss_io;
input clk_dcc, dll_reset_n, nfrzdrv;
input [9:0] pvt_ref_half_gry;
wire up, net018, net022, net025; // Conversion Sript Generated
io_split_align xsplit_align_0 (
//.vcc_io(vcc_regphy), .vss_io(vss_io),
.dout_n(clk_dcd_split_n),
.dout_p(clk_dcd_split_p),
.din(clk_dcc)
);
assign up = !net018;
assign net022 = !net025;
io_nand_delay_line_min xdelay_line_match (
.nfrzdrv(nfrzdrv),
//.vcc_regphy(vcc_regphy), .vcc_io(vcc_io), .vss_io(vss_io),
.out_n(clkn_mindly),
.out_p(clkp_mindly),
.in_n(clk_dcd_split_n),
.in_p(clk_dcd_split_p)
);
an_io_phdet_ff xsampling ( /*`ifndef INTCNOPWR .vcc(vcc_io), .vss(vss_io), `endif*/
.q(net018),
.clk_p(clkp_dly),
.dn(clkn_mindly),
.dp(clkp_mindly),
.rst_n(dll_reset_n)
);
an_io_phdet_ff xload_match ( /*`ifndef INTCNOPWR .vcc(vcc_io), .vss(vss_io), `endif*/
.q(net025),
.clk_p(clkp_mindly),
.dn(clkn_dly),
.dp(clkp_dly),
.rst_n(dll_reset_n)
);
io_nand_x128_delay_line xdelay_line (
//.vcc_io(vcc_io),
//.vcc_regphy(vcc_regphy), .vss_io(vss_io),
.i_gray(pvt_ref_half_gry[2:0]),
.f_gray(pvt_ref_half_gry[9:3]),
.out_n(clkn_dly),
.out_p(clkp_dly),
.osc_out_n(net014),
.osc_out_p(net015),
.osc_in_n(vcc_io),
.osc_in_p(vss_io),
.osc_mode(vss_io),
.in_n(clk_dcd_split_n),
.in_p(clk_dcd_split_p),
.nfrzdrv(nfrzdrv)
);
endmodule
| 6.806032 |
module aibnd_ff_r (
input wire clk,
input wire rb,
input wire d,
//input wire vss,
//input wire vcc,
output reg o
);
always @(posedge clk or negedge rb) begin
if (!rb) begin
o <= 1'b0;
end else begin
o <= d;
end
end
endmodule
| 8.226681 |
module aibnd_ff_rp (
input wire clk,
input wire rb,
input wire psb,
input wire d,
//input wire vss,
//input wire vcc,
output reg o
);
always @(posedge clk or negedge rb or negedge psb) begin
if (!rb) begin
o <= 1'b0;
end else if (!psb) begin
o <= 1'b1;
end else begin
o <= d;
end
end
endmodule
| 8.55097 |
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