code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module aibnd_hgy_latch (
input wire set,
input wire preset,
input wire clk,
input wire d,
output reg q
);
always @(*) begin
if (set && !preset) begin
q <= 0;
end else if (!set && preset) begin
q <= 1;
end else begin
if (clk) q <= d;
end
end
endmodule
| 6.529145 |
module aibnd_inv_split_align (
din,
dout,
vccl,
vssl
);
input din;
output dout;
input vssl;
input vccl;
assign dout = ~din;
endmodule
| 7.232955 |
module aibnd_io_nand_delay_line_min_rep (
input nfrzdrv,
input in_p,
input in_n,
output out_p,
output out_n
);
`ifdef TIMESCALE_EN
timeunit 1ps; timeprecision 1ps;
`endif
parameter NAND_DELAY = 20;
wire fout_p;
wire fout_n;
wire osc_out_p;
wire osc_out_n;
//---------------------------------------------------------------------------------------------------------------------------------------------
//
//---------------------------------------------------------------------------------------------------------------------------------------------
io_cmos_nand_x1 xnandx1 (
.in_p (in_p),
.in_n (in_n),
.bk (1'b0),
.ci_p (1'b1),
.ci_n (1'b1),
.out_p(fout_p),
.out_n(fout_n),
.co_p (),
.co_n ()
);
aibnd_io_dly_interpolator_rep xinterp (
.nfrzdrv (nfrzdrv),
.fout_p (fout_p),
.fout_n (fout_n),
.gray (3'b000),
.out_p (out_p),
.out_n (out_n),
.osc_out_p(osc_out_p),
.osc_out_n(osc_out_n)
);
endmodule
| 6.708165 |
module aibnd_latch (
input wire clk,
input wire rb,
//input wire vcc,
//input wire vss,
input wire d,
output reg o
);
always @(*) begin
if (!rb) begin
o <= 0;
end else begin
if (clk) o <= d;
end
end
endmodule
| 8.451951 |
module aibnd_quadph_code_gen #(
parameter FF_DELAY = 200
) (
input wire clk, //reference clock from pll
input wire reset_n, //output for dll reset
input wire [9:0] pvt_ref_binary, //output binary pvt value for delay chain
input wire rb_quad_code, //select between original or quadrature codes
output reg [9:0] pvt_ref_quad_binary //quadrature code (binary) for delay chain
);
`ifdef TIMESCALE_EN
timeunit 1ps; timeprecision 1ps;
`endif
wire [6:0] coarse_bin;
reg [2:0] fint_bin;
wire [2:0] fine_bin;
reg [8:0] coarse_divided_bin;
reg [4:0] fine_divided_bin, coarse_frac_bin;
always @(*) begin
if (~reset_n) begin
coarse_divided_bin = 9'b0_0000_0000;
fine_divided_bin = 5'b0_0000;
coarse_frac_bin = 5'b0_0000;
fint_bin = 3'b000;
end else begin
coarse_divided_bin = {2'b00, pvt_ref_binary[9:3]};
fine_divided_bin = {2'b00, pvt_ref_binary[2:0]};
// coarse_frac_bin = {1'b0,coarse_divided_bin[1:0],2'b00}; //****need to finalize what's the ratio between coarse/fine steps. current coding assumes 20ps/5ps=4
coarse_frac_bin = {coarse_divided_bin[1:0], 3'b000};
fint_bin = coarse_frac_bin[4:2] + fine_divided_bin[4:2];
if ((fine_divided_bin[1:0] >= 2'd2)) begin
fint_bin = fint_bin + 3'b001;
end else begin
fint_bin = fint_bin;
end
end
end
assign coarse_bin = coarse_divided_bin[8:2];
assign fine_bin = fint_bin;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
pvt_ref_quad_binary <= #FF_DELAY 10'b00_0000_0000;
end else
case (rb_quad_code)
1'b0: pvt_ref_quad_binary <= #FF_DELAY pvt_ref_binary;
1'b1: pvt_ref_quad_binary <= #FF_DELAY{coarse_bin, fine_bin};
default: pvt_ref_quad_binary <= #FF_DELAY{coarse_bin, fine_bin};
endcase
end
endmodule
| 6.63384 |
module aibnd_redundancy ( //input of input mux
pd_data_in1,
pd_data_in0,
iclkin_dist_in1,
iclkin_dist_in0,
idata0_in1,
idata0_in0,
idata1_in1,
idata1_in0,
idataselb_in1,
idataselb_in0,
iddren_in1,
iddren_in0,
ilaunch_clk_in1,
ilaunch_clk_in0,
ilpbk_dat_in1,
ilpbk_dat_in0,
ilpbk_en_in1,
ilpbk_en_in0,
irxen_in1,
irxen_in0,
istrbclk_in1,
istrbclk_in0,
itxen_in1,
itxen_in0,
indrv_in1,
indrv_in0,
ipdrv_in1,
ipdrv_in0,
async_dat_in1,
async_dat_in0,
//Output of input mux
iclkin_dist_out,
idata0_out,
idata1_out,
idataselb_out,
iddren_out,
ilaunch_clk_out,
ilpbk_dat_out,
ilpbk_en_out,
irxen_out,
istrbclk_out,
itxen_out,
indrv_out,
ipdrv_out,
async_dat_out,
//input of output mux
oclkb_in1,
oclkb_in0,
oclk_in1,
oclk_in0,
odat0_in1,
odat0_in0,
odat1_in1,
odat1_in0,
odat_async_in1,
odat_async_in0,
//Output of output mux
pd_data_out,
oclkb_out,
oclk_out,
odat0_out,
odat1_out,
odat_async_out,
//Mux selection signal
shift_en //Removed VCCL & VSS port
);
//Power Supply
//input vccl, vssl;
//Mux selection signal
input shift_en;
//input of input mux
input iclkin_dist_in1, iclkin_dist_in0;
input idata0_in1, idata0_in0;
input idata1_in1, idata1_in0;
input idataselb_in1, idataselb_in0;
input iddren_in1, iddren_in0;
input ilaunch_clk_in1, ilaunch_clk_in0;
input ilpbk_dat_in1, ilpbk_dat_in0;
input ilpbk_en_in1, ilpbk_en_in0;
input [2:0] irxen_in1, irxen_in0;
input istrbclk_in1, istrbclk_in0;
input itxen_in1, itxen_in0;
input [1:0] indrv_in1, indrv_in0;
input [1:0] ipdrv_in1, ipdrv_in0;
input async_dat_in1, async_dat_in0;
//output of input mux
output iclkin_dist_out;
output idata0_out;
output idata1_out;
output idataselb_out;
output iddren_out;
output ilaunch_clk_out;
output ilpbk_dat_out;
output ilpbk_en_out;
output [2:0] irxen_out;
output istrbclk_out;
output itxen_out;
output [1:0] indrv_out;
output [1:0] ipdrv_out;
output async_dat_out;
//input of output mux
input pd_data_in1, pd_data_in0;
input oclkb_in1, oclkb_in0;
input oclk_in1, oclk_in0;
input odat0_in1, odat0_in0;
input odat1_in1, odat1_in0;
input odat_async_in1, odat_async_in0;
//output of output mux
output pd_data_out;
output oclkb_out;
output oclk_out;
output odat0_out;
output odat1_out;
output odat_async_out;
// Buses in the design
//input mux
assign iclkin_dist_out = shift_en ? iclkin_dist_in1 : iclkin_dist_in0;
assign idata0_out = shift_en ? idata0_in1 : idata0_in0;
assign idata1_out = shift_en ? idata1_in1 : idata1_in0;
assign idataselb_out = shift_en ? idataselb_in1 : idataselb_in0;
assign iddren_out = shift_en ? iddren_in1 : iddren_in0;
assign ilaunch_clk_out = shift_en ? ilaunch_clk_in1 : ilaunch_clk_in0;
assign ilpbk_dat_out = shift_en ? ilpbk_dat_in1 : ilpbk_dat_in0;
assign ilpbk_en_out = shift_en ? ilpbk_en_in1 : ilpbk_en_in0;
assign irxen_out[2] = shift_en ? irxen_in1[2] : irxen_in0[2];
assign irxen_out[1] = shift_en ? irxen_in1[1] : irxen_in0[1];
assign irxen_out[0] = shift_en ? irxen_in1[0] : irxen_in0[0];
assign istrbclk_out = shift_en ? istrbclk_in1 : istrbclk_in0;
assign itxen_out = shift_en ? itxen_in1 : itxen_in0;
assign indrv_out[1] = shift_en ? indrv_in1[1] : indrv_in0[1];
assign indrv_out[0] = shift_en ? indrv_in1[0] : indrv_in0[0];
assign ipdrv_out[1] = shift_en ? ipdrv_in1[1] : ipdrv_in0[1];
assign ipdrv_out[0] = shift_en ? ipdrv_in1[0] : ipdrv_in0[0];
assign async_dat_out = shift_en ? async_dat_in1 : async_dat_in0;
//output mux
assign pd_data_out = shift_en ? pd_data_in1 : pd_data_in0;
assign oclkb_out = shift_en ? oclkb_in1 : oclkb_in0;
assign oclk_out = shift_en ? oclk_in1 : oclk_in0;
assign odat0_out = shift_en ? odat0_in1 : odat0_in0;
assign odat1_out = shift_en ? odat1_in1 : odat1_in0;
assign odat_async_out = shift_en ? odat_async_in1 : odat_async_in0;
endmodule
| 6.639647 |
module aibnd_rxdat_mimic (
input wire vccl_aibnd,
input wire vssl_aibnd,
input wire odat_in,
output wire odat_out
);
assign odat_out = odat_in;
endmodule
| 7.350924 |
module aibnd_str_ioload (
inp
);
input inp;
// Buses in the design
wire net07;
assign vcc_aibnd = 1'b1;
assign vss_aibnd = 1'b0;
//specify
// specparam CDS_LIBNAME = "aibnd_lib";
// specparam CDS_CELLNAME = "aibnd_str_ioload";
// specparam CDS_VIEWNAME = "schematic";
//endspecify
assign net07 = ~inp;
endmodule
| 6.546486 |
module aibnd_txdat_mimic (
input wire vccl_aibnd,
input wire vssl_aibnd,
input wire idata_in,
output wire idata_out
);
assign idata_out = idata_in;
endmodule
| 7.633605 |
module aib_adapter_rxchnl (
// Outputs
output wire [319:0] rx_adapt_dout, // FIFO mode data output
output wire [ 79:0] data_out, // Register mode data output
output wire align_done, // Word Mark alignment done
// Inputs
input atpg_mode, // Scan enabled
input m_gen2_mode, // Generation 2.0 mode
input rxrd_fifo_rstn, // RX FIFO read reset
input rxwr_rstn, // RX write reset
input rxwr_fifo_rstn, // RX FIFO write reset
input [ 79:0] din, // Data input from io buffer
input rxfifo_rd_clk, // Read clock
input rxfifo_wrclk, // FIFO write clock
input [ 1:0] r_rx_fifo_mode, // FIFO mode register
input [ 4:0] rx_align_threshold, // RX FIFO WAM threshold
input [ 3:0] r_rx_phcomp_rd_delay, // Phase compensation register
input r_rx_wa_en, // RX word aligment enable
input rx_wa_mode_sync, // Rx word alignment mode bit
input r_rxswap_en, // RX swapping enable
input [ 4:0] r_rx_mkbit, // Selection of Rx word mark bit
input r_rx_dbi_en // Enable for Rx data bus inversion
);
// Wires
wire [ 79:0] dbi_dout; // Output of data bus inversion
wire [ 79:0] rx_fifo_data_out_sel; // Swapped data or input data to FIFO
wire [319:0] rx_fifo_data_out; // Output from FIFO registered
// FIFO data output
assign rx_adapt_dout = {rx_fifo_data_out[319:80], rx_fifo_data_out_sel};
// Data output after DBI logic
assign data_out = dbi_dout;
// Data after swapping logic.
// Swapping is used only for FIFO 2x with generation 1
assign rx_fifo_data_out_sel[79:0] =
((r_rx_fifo_mode==2'b01) & r_rxswap_en & ~m_gen2_mode) ?
{rx_fifo_data_out[79],
rx_fifo_data_out[38:0],
rx_fifo_data_out[39],
rx_fifo_data_out[78:40]} :
rx_fifo_data_out[79:0];
// DBI logic
aib_rx_dbi rx_dbi (
// Inputs
.rst_n (rxwr_rstn), // Async reset
.clk (rxfifo_wrclk), // FIFO write clock
.data_in (din), // Data input
.dbi_en (r_rx_dbi_en), // Data bus inversion
// Outputs
.data_out(dbi_dout) // Data bus inversion output
);
// RX FIFO data path logic
aib_adapt_rx_fifo aib_adapt_rx_fifo (
// Outputs
.fifo_dout (rx_fifo_data_out), // FIFO data output registered
.align_done (align_done), // Word mark alignment done
// Inputs
.wr_rst_n (rxwr_fifo_rstn), // Rx FIFO write reset
.wr_clk (rxfifo_wrclk), // Rx FIFO write clock
.fifo_din (dbi_dout), // FIFO input
.rd_rst_n (rxrd_fifo_rstn), // Rx FIFO read reset
.rd_clk (rxfifo_rd_clk), // FIFO Read clock
.scan_en (atpg_mode), // Scan enable
.m_gen2_mode (m_gen2_mode), // Generation mode
.r_fifo_mode (r_rx_fifo_mode[1:0]), // RX FIFO mode configuration
.rx_align_threshold(rx_align_threshold[4:0]), // RX FIFO WAM threshold
.r_phcomp_rd_delay (r_rx_phcomp_rd_delay[3:0]), // RX FIFO phase compensation
.r_mkbit (r_rx_mkbit[4:0]), // RX Mark bits
.rx_wa_mode_sync (rx_wa_mode_sync), // Word alignment mode bit
.r_wa_en (r_rx_wa_en) // Word alignment enable
);
endmodule
| 7.294102 |
module aib_adapter_txchnl (
// Outputs
output wire [ 79:0] dout, // AIB Data output
// Inputs
input atpg_mode, // Scan enable
input txwr_fifo_rstn, // Tx write fifo reset
input txrd_rstn, // Tx read reset
input txrd_fifo_rstn, // Tx read fifo reset
input m_gen2_mode, // AIB Generation 2.0 indication
input txfifo_wr_clk, // Write clock
input tx_clk_adapter, // TX DLL clock to adapter
input [319:0] tx_adapt_din, // FIFO mode data input
input [ 79:0] data_in, // Register mode data input
input r_tx_dbi_en, // Enable for tx data bus inversion
input [ 1:0] r_tx_fifo_mode, // TX FIFO mode register
input [ 3:0] r_tx_phcomp_rd_delay, // TX phase compensation register
input r_txswap_en, // TX swapping enable
input r_tx_wm_en, // Tx word mark enable
input [ 4:0] r_tx_mkbit // Selection of word mark bit
);
wire [79:0] fifo_dout; // Output data from FIFO
wire [79:0] merge_dout; // Output slection based on operation mode
wire [79:0] data_in_f_sel; // Swapped data or input data to FIFO
//Mux for bypass mode data and fifo data
assign merge_dout[79:0] = (r_tx_fifo_mode == 2'b11) ? data_in[79:0] : fifo_dout[79:0];
//Data bus inversion logic (DBI)
aib_tx_dbi txdbi (
.rst_n (txrd_rstn), // Async, reset
.clk (tx_clk_adapter), // Near side forwarded clock
.dbi_en (r_tx_dbi_en), // DBI enable
.data_in (merge_dout), // Data to be inverted by DBI logic
.data_out(dout) // Data after DBI logic
);
// Swapping logic used only in Gen 1 mode and 2xFIFO
assign data_in_f_sel[79:0] =
((r_tx_fifo_mode == 2'b01) & r_txswap_en & ~m_gen2_mode) ?
{tx_adapt_din[79],
tx_adapt_din[38:0],
tx_adapt_din[39],
tx_adapt_din[78:40]} :
tx_adapt_din[79:0];
// TX FIFO data path logic
aib_adapt_tx_fifo aib_adapt_tx_fifo (
// Outputs
.fifo_dout (fifo_dout[79:0]), // FIFO data output
// Inputs
.data_in ({tx_adapt_din[319:80], data_in_f_sel[79:0]}), // FIFO data input
.r_fifo_mode (r_tx_fifo_mode[1:0]), // FIFO mode register
.r_phcomp_rd_delay(r_tx_phcomp_rd_delay[3:0]), // Tx phase compensation
.m_gen2_mode (m_gen2_mode), // Generation 2.0 mode
.r_wm_en (r_tx_wm_en), // Tx swapping
.r_mkbit (r_tx_mkbit[4:0]), // Tx Mark bits
.scan_en (atpg_mode), // Scan enable
.wr_clk (txfifo_wr_clk), // Tx write clock
.wr_rst_n (txwr_fifo_rstn), // Tx FIFO write reset
.rd_clk (tx_clk_adapter), // TX DLL clock to adapter
.rd_rst_n (txrd_fifo_rstn) // Tx FIFO read reset
);
endmodule
| 6.903967 |
module aib_adaptrxdbi_rxdp (
input wire rst_n,
input wire clk,
input wire [79:0] data_in,
input wire dbi_en,
output wire [79:0] data_out
);
wire [3:0] dbi_calc;
reg [79:0] last_din, dbi_data_out;
wire [37:0] dbi_dat_lo, dbi_dat_hi;
assign data_out = dbi_en ? dbi_data_out : data_in;
assign dbi_calc = {data_in[79], data_in[78], data_in[39], data_in[38]};
genvar j;
generate
for (j = 0; j < 19; j = j + 1) begin : data_out_gen
assign dbi_dat_lo[2*j] = data_in[2*j] ^ dbi_calc[0];
assign dbi_dat_lo[2*j+1] = data_in[2*j+1] ^ dbi_calc[1];
assign dbi_dat_hi[2*j] = data_in[2*j+40] ^ dbi_calc[2];
assign dbi_dat_hi[2*j+1] = data_in[2*j+1+40] ^ dbi_calc[3];
end
endgenerate
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
dbi_data_out <= 80'h0;
end else dbi_data_out <= {dbi_calc[3:2], dbi_dat_hi, dbi_calc[1:0], dbi_dat_lo};
end
endmodule
| 6.775732 |
module aib_adaptrxdp_fifo_ram #(
parameter DWIDTH = 'd80, // FIFO Input data width
parameter DEPTH = 'd16 // FIFO Depth
) (
input wire wr_clk, // Write Domain Clock
input wire wr_rst_n, // Write Domain Reset
input wire wr_en, // Write Data Enable
input wire [ DEPTH-1:0] wr_ptr, // Write Pointer
input wire [DWIDTH*4-1:0] wr_data, // Write Data In
input wire [ DEPTH-1:0] rd_ptr, // Read Pointer
output reg [DWIDTH*4-1:0] rd_data // Read Data
);
//********************************************************************
// Infer Memory or use Dual Port Memory from Quartus/ASIC Memory
//********************************************************************
wire [DEPTH-1:0] rd_ptr2;
integer m;
integer i, j;
reg [DWIDTH*4-1:0] fifo_mem[DEPTH-1:0];
always @(negedge wr_rst_n or posedge wr_clk) begin
if (~wr_rst_n) begin
for (m = 'd0; m <= (DEPTH - 1'b1); m = m + 1'b1) fifo_mem[m] <= 'd0;
end else if (wr_en) begin
for (m = 'd0; m <= (DEPTH - 1'b1); m = m + 1'b1) begin
if (wr_ptr[m]) begin
fifo_mem[m] <= wr_data;
end
end
end
end
always @* begin : data_out
rd_data = fifo_mem[0];
for (i = 'd0; i <= (DEPTH - 1'b1); i = i + 1'b1) begin
if (rd_ptr[i]) begin
rd_data = fifo_mem[i];
end
end
end
endmodule
| 7.696758 |
module aib_adaptrxdp_map (
input wire [39:0] din,
input wire [79:0] rx_fifo_data_out, // Data from rx fifo
input wire rx_aib_transfer_clk,
input wire rx_aib_transfer_rst_n,
input wire rx_clock_fifo_rd_clk,
input wire rx_reset_fifo_rd_rst_n,
output reg [79:0] r_fifo_dout,
output reg [39:0] reg_dout
);
always @(posedge rx_clock_fifo_rd_clk or negedge rx_reset_fifo_rd_rst_n) begin
if (!rx_reset_fifo_rd_rst_n) begin
r_fifo_dout[79:0] <= {80{1'b0}};
end else begin
r_fifo_dout[79:0] <= rx_fifo_data_out[79:0];
end
end
always @(posedge rx_aib_transfer_clk or negedge rx_aib_transfer_rst_n) begin
if (!rx_aib_transfer_rst_n) begin
reg_dout[39:0] <= {40{1'b0}};
end else begin
reg_dout[39:0] <= din[39:0];
end
end
endmodule
| 7.696758 |
module aib_adaptrxdp_word_align #(
parameter DWIDTH = 'd40 // FIFO Input data width
) (
input wire wr_clk, // clock
input wire wr_rst_n, // async reset
input wire r_wa_en, // Word-align enable
input wire [DWIDTH-1:0] aib_hssi_rx_data_in, // Write Data In
output wire wa_lock, // Go to FIFO, status reg
output wire [ 19:0] word_align_testbus
);
reg wm_bit;
reg wm_bit_d1;
reg wm_bit_d2;
reg wm_bit_d3;
reg wm_bit_d4;
reg wm_bit_d5;
reg wa_lock_lt;
wire wa_lock_int;
//********************************************************************
// Main logic
//********************************************************************
//Word-align
always @(negedge wr_rst_n or posedge wr_clk) begin
if (wr_rst_n == 1'b0) begin
wm_bit <= 1'b0;
wm_bit_d1 <= 1'b0;
wm_bit_d2 <= 1'b0;
wm_bit_d3 <= 1'b0;
wm_bit_d4 <= 1'b0;
wm_bit_d5 <= 1'b0;
end else begin
wm_bit <= aib_hssi_rx_data_in[39];
wm_bit_d1 <= wm_bit;
wm_bit_d2 <= wm_bit_d1;
wm_bit_d3 <= wm_bit_d2;
wm_bit_d4 <= wm_bit_d3;
wm_bit_d5 <= wm_bit_d4;
end
end
always @(negedge wr_rst_n or posedge wr_clk) begin
if (wr_rst_n == 1'b0) begin
wa_lock_lt <= 1'b0;
end else begin
wa_lock_lt <= wa_lock_int || wa_lock_lt;
end
end
assign wa_lock_int = wm_bit && ~wm_bit_d1 && wm_bit_d2 && ~wm_bit_d3 && wm_bit_d4 && ~wm_bit_d5 || ~r_wa_en;
assign wa_lock = wa_lock_int || wa_lock_lt;
assign word_align_testbus = {
13'd0, wa_lock, wm_bit, wm_bit_d1, wm_bit_d2, wm_bit_d3, wm_bit_d4, wm_bit_d5
};
endmodule
| 7.696758 |
module aib_adapttxdp_fifo_ram #(
parameter DWIDTH = 'd80, // FIFO Input data width
parameter DEPTH = 'd16 // FIFO Depth
) (
input wire wr_clk, // Write Domain Clock
input wire wr_en, // write enable
input wire wr_rst_n, // Write Domain Reset
input wire [ DEPTH-1:0] wr_ptr, // Write Pointer
input wire [DWIDTH*4-1:0] wr_data, // Write Data In
input wire [ DEPTH-1:0] rd_ptr, // Read Pointer
output reg [DWIDTH*4-1:0] rd_data // Read Data
);
//********************************************************************
// Infer Memory or use Dual Port Memory from Quartus/ASIC Memory
//********************************************************************
integer m;
integer i;
reg [DWIDTH*4-1:0] fifo_mem[DEPTH-1:0];
always @(negedge wr_rst_n or posedge wr_clk) begin
if (~wr_rst_n) begin
for (m = 'd0; m <= (DEPTH - 1'b1); m = m + 1'b1) fifo_mem[m] <= 'd0;
end else if (wr_en) begin
for (m = 'd0; m <= (DEPTH - 1'b1); m = m + 1'b1) begin
if (wr_ptr[m]) begin
fifo_mem[m] <= wr_data;
end
end
end
end
//assign rd_data = fifo_mem[rd_ptr];
always @* begin : data_out
rd_data = fifo_mem[0];
for (i = 'd0; i <= (DEPTH - 1'b1); i = i + 1'b1) begin
if (rd_ptr[i]) begin
rd_data = fifo_mem[i];
end
end
end
endmodule
| 6.661394 |
module aib_adapttxdp_reg (
input wire tx_clock_fifo_rd_clk,
input wire tx_reset_fifo_rd_rst_n,
input wire [ 1:0] r_tx_fifo_mode,
input wire [39:0] data_in,
output reg [39:0] reg_dout
);
always @(posedge tx_clock_fifo_rd_clk or negedge tx_reset_fifo_rd_rst_n) begin
if (!tx_reset_fifo_rd_rst_n) reg_dout <= {40{1'b0}};
else if (r_tx_fifo_mode[1:0] == 2'b11) begin
reg_dout[39:0] <= data_in[39:0];
end
end
endmodule
| 6.661394 |
module aib_adapt_cmn_pulse_stretch #(
parameter RESET_VAL = 'd0 // reset value
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire [2:0] num_stages, // number of stages required
input wire data_in, // data in
output reg data_out // stretched data out
);
reg data_d1, data_d2, data_d3, data_d4;
reg data_d5, data_d6, data_d7;
reg data_out_comb;
localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0; // To eliminate truncating warning
always @* begin
data_out_comb = data_in;
case (num_stages)
3'b000: data_out_comb = data_in;
3'b001: data_out_comb = data_d1 | data_in;
3'b010: data_out_comb = data_d2 | data_d1 | data_in;
3'b011: data_out_comb = data_d3 | data_d2 | data_d1 | data_in;
3'b100: data_out_comb = data_d4 | data_d3 | data_d2 | data_d1 | data_in;
3'b101: data_out_comb = data_d5 | data_d4 | data_d3 | data_d2 | data_d1 | data_in;
3'b110: data_out_comb = data_d6 | data_d5 | data_d4 | data_d3 | data_d2 | data_d1 | data_in;
3'b111:
data_out_comb = data_d7 | data_d6 | data_d5 | data_d4 | data_d3 | data_d2 | data_d1 | data_in;
default: data_out_comb = data_in;
endcase // case(num_stages)
end // always @ *
always @(negedge rst_n or posedge clk) begin
if (~rst_n) begin
data_d1 <= reset_value;
data_d2 <= reset_value;
data_d3 <= reset_value;
data_d4 <= reset_value;
data_d5 <= reset_value;
data_d6 <= reset_value;
data_d7 <= reset_value;
data_out <= reset_value;
end else begin
data_d1 <= data_in;
data_d2 <= data_d1;
data_d3 <= data_d2;
data_d4 <= data_d3;
data_d5 <= data_d4;
data_d6 <= data_d5;
data_d7 <= data_d6;
data_out <= data_out_comb;
end
end // always @ (negedge rst_n or posedge clk)
endmodule
| 9.632342 |
module aib_adapt_rxchnl (
// Outputs
output wire [319:0] data_out_f,
output wire [ 79:0] data_out,
output wire align_done,
// Inputs
input wire atpg_mode,
input wire m_gen2_mode,
input wire adapt_rstn,
input wire rx_fifo_rstn,
input wire [ 79:0] din, //from io buffer
input wire m_rd_clk,
input wire rxfifo_wrclk,
input wire [ 1:0] r_rx_fifo_mode,
input wire [ 3:0] r_rx_phcomp_rd_delay,
input wire r_rx_wa_en,
input wire r_rxswap_en,
input wire [ 4:0] r_rx_mkbit,
input wire r_rx_dbi_en
);
wire [79:0] dbi_dout, rx_fifo_data_out_sel;
wire [319:0] rx_fifo_data_out;
wire rxwr_rstn, rxrd_rstn;
wire rxwr_fifo_rstn, rxrd_fifo_rstn;
assign data_out_f = {rx_fifo_data_out[319:80], rx_fifo_data_out_sel};
assign data_out = dbi_dout;
assign rx_fifo_data_out_sel[79:0] =((r_rx_fifo_mode==2'b01) & r_rxswap_en & ~m_gen2_mode) ? {rx_fifo_data_out[79], rx_fifo_data_out[38:0], rx_fifo_data_out[39], rx_fifo_data_out[78:40]} : rx_fifo_data_out[79:0];
aib_adaptrxdbi_rxdp rx_dbi (
.rst_n(rxwr_rstn),
.clk(rxfifo_wrclk),
.data_in(din),
.dbi_en(r_rx_dbi_en),
.data_out(dbi_dout)
);
aib_adaptrxdp_fifo rxdp_fifo (
// Outputs
.fifo_dout (rx_fifo_data_out),
.fifo_empty (fifo_empty),
.fifo_pempty(fifo_pempty),
.fifo_pfull (fifo_pfull),
.fifo_full (fifo_full_int),
.align_done (align_done),
// Inputs
.wr_rst_n (rxwr_fifo_rstn),
.wr_clk (rxfifo_wrclk),
.fifo_din (dbi_dout),
.rd_rst_n (rxrd_fifo_rstn),
.rd_clk (m_rd_clk),
.r_pempty (5'b0),
.r_pfull (5'b11111),
.r_empty (5'b0),
.r_full (5'b11111),
.m_gen2_mode (m_gen2_mode),
.r_fifo_mode (r_rx_fifo_mode[1:0]),
.r_phcomp_rd_delay(r_rx_phcomp_rd_delay),
.r_mkbit (r_rx_mkbit),
.r_wa_en (r_rx_wa_en)
);
aib_rstnsync rxwr_rstnsync (
.clk (rxfifo_wrclk), // Destination clock of reset to be synced
.i_rst_n (adapt_rstn), // Asynchronous reset input
.scan_mode (atpg_mode), // Scan bypass for reset
.sync_rst_n(rxwr_rstn) // Synchronized reset output
);
aib_rstnsync rxwr_fifo_rstnsync (
.clk(rxfifo_wrclk),
.i_rst_n(rx_fifo_rstn),
.scan_mode(atpg_mode),
.sync_rst_n(rxwr_fifo_rstn)
);
aib_rstnsync rxrd_rstnsync (
.clk (m_rd_clk), // Destination clock of reset to be synced
.i_rst_n (adapt_rstn), // Asynchronous reset input
.scan_mode (atpg_mode), // Scan bypass for reset
.sync_rst_n(rxrd_rstn) // Synchronized reset output
);
aib_rstnsync rxrd_fifo_rstnsync (
.clk(m_rd_clk),
.i_rst_n(rx_fifo_rstn),
.scan_mode(atpg_mode),
.sync_rst_n(rxrd_fifo_rstn)
);
endmodule
| 6.781638 |
module aib_aliasd (
sig_in,
sig_red
);
output sig_red;
input sig_in;
assign sig_red = sig_in;
endmodule
| 6.869345 |
module aib_aux_channel (
// AIB IO Bidirectional
inout wire iopad_dev_dect,
inout wire iopad_dev_dectrdcy,
inout wire iopad_dev_por,
inout wire iopad_dev_porrdcy,
input m_por_ovrd, //Master onlhy input, it overrides the por signal. For slave, it is tied to "0"
input m_device_detect_ovrd, //Slave only input, it overrides the device_detect signal. For Master, it is tied to "0"
output wire por_ms,
output wire m_device_detect,
input por_sl,
output wire osc_clk,
input ms_nsl, //"1", this is a Master. "0", this is a Slave
input irstb // Output buffer tri-state enable
);
aib_aliasd aliaspor (
.sig_red(iopad_dev_porrdcy),
.sig_in (iopad_dev_por)
);
aib_aliasd aliasdet (
.sig_red(iopad_dev_dectrdcy),
.sig_in (iopad_dev_dect)
);
wire device_detect_oe;
wire device_detect_ie;
wire por_oe;
wire por_ie;
wire device_detect_sl_main;
wire por_ms_main;
assign m_device_detect = device_detect_sl_main | m_device_detect_ovrd;
assign por_ms = por_ms_main & m_por_ovrd;
assign device_detect_oe = (ms_nsl == 1'b1) ? 1'b1 : 1'b0;
assign device_detect_ie = !device_detect_oe;
assign por_oe = (ms_nsl == 1'b1) ? 1'b0 : 1'b1;
assign por_ie = !por_oe;
aib_io_buffer u_device_detect (
// Tx Path
.ilaunch_clk(1'b0),
.irstb (irstb),
.idat0 (1'b1),
.idat1 (1'b1),
.async_data (1'b1),
.oclkn (),
// Rx Path
.iclkn (1'b0),
.inclk (1'b0),
.inclk_dist(1'b0),
.oclk (),
.oclk_b (),
.odat0 (),
.odat1 (),
.odat_async(device_detect_sl_main),
// Bidirectional Data
.io_pad(iopad_dev_dect),
// I/O configuration
.async (1'b1),
.ddren (1'b0),
.txen (device_detect_oe),
.rxen (device_detect_ie),
.weaken (device_detect_ie),
.weakdir(1'b0)
);
aib_io_buffer u_device_por (
// Tx Path
.ilaunch_clk(1'b0),
.irstb (irstb),
.idat0 (por_sl),
.idat1 (por_sl),
.async_data (por_sl),
.oclkn (),
// Rx Path
.iclkn (1'b0),
.inclk (1'b0),
.inclk_dist(1'b0),
.oclk (),
.oclk_b (),
.odat0 (),
.odat1 (),
.odat_async(por_ms_main),
// Bidirectional Data
.io_pad(iopad_dev_por),
// I/O configuration
.async (1'b1),
.ddren (1'b0),
.txen (por_oe),
.rxen (por_ie),
.weaken (por_ie),
.weakdir(1'b1)
);
aib_osc_clk aib_osc_clk (.osc_clk(osc_clk));
endmodule
| 8.407922 |
module aib_avmm_adapt_csr (
output reg [31:0] rx_0,
output reg [31:0] rx_1,
output reg [31:0] tx_0,
output reg [31:0] tx_1,
//Bus Interface
input clk,
input reset,
input [31:0] writedata,
input read,
input write,
input [3:0] byteenable,
output reg [31:0] readdata,
output reg readdatavalid,
input [6:0] address
);
wire reset_n = !reset;
// Protocol management
// combinatorial read data signal declaration
reg [31:0] rdata_comb;
// synchronous process for the read
always @(negedge reset_n, posedge clk)
if (!reset_n) readdata[31:0] <= 32'h0;
else readdata[31:0] <= rdata_comb[31:0];
// read data is always returned on the next cycle
always @(negedge reset_n, posedge clk)
if (!reset_n) readdatavalid <= 1'b0;
else readdatavalid <= read;
//
// Protocol specific assignment to inside signals
//
wire we = write;
wire re = read;
wire [ 6:0] addr = address[6:0];
wire [31:0] din = writedata[31:0];
// A write byte enable for each register
wire [ 3:0] we_rx_0 = we & (addr[6:0] == 7'h08) ? byteenable[3:0] : {4{1'b0}};
wire [ 3:0] we_rx_1 = we & (addr[6:0] == 7'h10) ? byteenable[3:0] : {4{1'b0}};
wire [ 3:0] we_tx_0 = we & (addr[6:0] == 7'h18) ? byteenable[3:0] : {4{1'b0}};
wire [ 3:0] we_tx_1 = we & (addr[6:0] == 7'h1c) ? byteenable[3:0] : {4{1'b0}};
// A read byte enable for each register
always @(negedge reset_n, posedge clk)
if (!reset_n) begin
rx_0[31:0] <= 32'h00000000;
end else begin
if (we_rx_0[0]) begin
rx_0[7:0] <= din[7:0];
end
if (we_rx_0[1]) begin
rx_0[15:8] <= din[15:8];
end
if (we_rx_0[2]) begin
rx_0[23:16] <= din[23:16];
end
if (we_rx_0[3]) begin
rx_0[31:24] <= din[31:24];
end
end
always @(negedge reset_n, posedge clk)
if (!reset_n) begin
rx_1[31:0] <= 32'h00000000;
end else begin
if (we_rx_1[0]) begin
rx_1[7:0] <= din[7:0];
end
if (we_rx_1[1]) begin
rx_1[15:8] <= din[15:8];
end
if (we_rx_1[2]) begin
rx_1[23:16] <= din[23:16];
end
if (we_rx_1[3]) begin
rx_1[31:24] <= din[31:24];
end
end
always @(negedge reset_n, posedge clk)
if (!reset_n) begin
tx_0[31:0] <= 32'h00000000;
end else begin
if (we_tx_0[0]) begin
tx_0[7:0] <= din[7:0];
end
if (we_tx_0[1]) begin
tx_0[15:8] <= din[15:8];
end
if (we_tx_0[2]) begin
tx_0[23:16] <= din[23:16];
end
if (we_tx_0[3]) begin
tx_0[31:24] <= din[31:24];
end
end
always @(negedge reset_n, posedge clk)
if (!reset_n) begin
tx_1[31:0] <= 32'h00000000;
end else begin
if (we_tx_1[0]) begin
tx_1[7:0] <= din[7:0];
end
if (we_tx_1[1]) begin
tx_1[15:8] <= din[15:8];
end
if (we_tx_1[2]) begin
tx_1[23:16] <= din[23:16];
end
if (we_tx_1[3]) begin
tx_1[31:24] <= din[31:24];
end
end
// read process
always @(*) begin
rdata_comb = 32'h0;
if (re) begin
case (addr)
7'h08: begin
rdata_comb[1:0] = rx_0[1:0];
rdata_comb[26:24] = rx_0[26:24];
end
7'h10: begin
rdata_comb[7:0] = rx_1[7:0];
end
7'h18: begin
rdata_comb[1:0] = tx_0[1:0];
rdata_comb[23:16] = tx_0[23:16];
rdata_comb[31:28] = tx_0[31:28];
end
7'h1c: begin
rdata_comb[15:14] = tx_1[15:14];
end
default: begin
rdata_comb = 32'h00000000;
end
endcase
end
end
endmodule
| 7.949418 |
module aib_avmm_io_csr (
output reg [31:0] redund_0,
output reg [31:0] redund_1,
output reg [31:0] redund_2,
output reg [31:0] redund_3,
//Bus Interface
input clk,
input reset,
input [31:0] writedata,
input read,
input write,
input [3:0] byteenable,
output reg [31:0] readdata,
output reg readdatavalid,
input [6:0] address
);
wire reset_n = !reset;
// Protocol management
// combinatorial read data signal declaration
reg [31:0] rdata_comb;
// synchronous process for the read
always @(negedge reset_n, posedge clk)
if (!reset_n) readdata[31:0] <= 32'h0;
else readdata[31:0] <= rdata_comb[31:0];
// read data is always returned on the next cycle
always @(negedge reset_n, posedge clk)
if (!reset_n) readdatavalid <= 1'b0;
else readdatavalid <= read;
//
// Protocol specific assignment to inside signals
//
wire we = write;
wire re = read;
wire [ 6:0] addr = address[6:0];
wire [31:0] din = writedata[31:0];
// A write byte enable for each register
wire [ 3:0] we_redund_0 = we & (addr[6:0] == 7'h20) ? byteenable[3:0] : {4{1'b0}};
wire [ 3:0] we_redund_1 = we & (addr[6:0] == 7'h24) ? byteenable[3:0] : {4{1'b0}};
wire [ 3:0] we_redund_2 = we & (addr[6:0] == 7'h28) ? byteenable[3:0] : {4{1'b0}};
wire [ 3:0] we_redund_3 = we & (addr[6:0] == 7'h1c) ? byteenable[3:0] : {4{1'b0}};
// A read byte enable for each register
always @(negedge reset_n, posedge clk)
if (!reset_n) begin
redund_0[31:0] <= 32'h00000000;
end else begin
if (we_redund_0[0]) begin
redund_0[7:0] <= din[7:0];
end
if (we_redund_0[1]) begin
redund_0[15:8] <= din[15:8];
end
if (we_redund_0[2]) begin
redund_0[23:16] <= din[23:16];
end
if (we_redund_0[3]) begin
redund_0[31:24] <= din[31:24];
end
end
always @(negedge reset_n, posedge clk)
if (!reset_n) begin
redund_1[31:0] <= 32'h00000000;
end else begin
if (we_redund_1[0]) begin
redund_1[7:0] <= din[7:0];
end
if (we_redund_1[1]) begin
redund_1[15:8] <= din[15:8];
end
if (we_redund_1[2]) begin
redund_1[23:16] <= din[23:16];
end
if (we_redund_1[3]) begin
redund_1[31:24] <= din[31:24];
end
end
always @(negedge reset_n, posedge clk)
if (!reset_n) begin
redund_2[31:0] <= 32'h00000000;
end else begin
if (we_redund_2[0]) begin
redund_2[7:0] <= din[7:0];
end
if (we_redund_2[1]) begin
redund_2[15:8] <= din[15:8];
end
if (we_redund_2[2]) begin
redund_2[23:16] <= din[23:16];
end
if (we_redund_2[3]) begin
redund_2[31:24] <= din[31:24];
end
end
always @(negedge reset_n, posedge clk)
if (!reset_n) begin
redund_3[31:0] <= 32'h00000000;
end else begin
if (we_redund_3[0]) begin
redund_3[7:0] <= din[7:0];
end
if (we_redund_3[1]) begin
redund_3[15:8] <= din[15:8];
end
if (we_redund_3[2]) begin
redund_3[23:16] <= din[23:16];
end
if (we_redund_3[3]) begin
redund_3[31:24] <= din[31:24];
end
end
// read process
always @(*) begin
rdata_comb = 32'h0;
if (re) begin
case (addr)
7'h20: begin
rdata_comb = redund_0;
end
7'h24: begin
rdata_comb = redund_1;
end
7'h28: begin
rdata_comb = redund_2;
end
7'h1c: begin
rdata_comb = redund_3;
end
default: begin
rdata_comb = 32'h00000000;
end
endcase
end
end
endmodule
| 7.249838 |
module aib_bitsync #(
parameter DWIDTH = 1'b1, // Sync Data input
parameter RESET_VAL = 1'b0 // Reset value
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire [DWIDTH-1:0] data_in, // data in
output wire [DWIDTH-1:0] data_out // data out
);
// End users may pass in RESET_VAL with a width exceeding 1 bit
// Evaluate the value first and use 1 bit value
localparam RESET_VAL_1B = (RESET_VAL == 'd0) ? 1'b0 : 1'b1;
reg [DWIDTH-1:0] dff2;
reg [DWIDTH-1:0] dff1;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
dff2 <= {DWIDTH{RESET_VAL_1B}};
dff1 <= {DWIDTH{RESET_VAL_1B}};
end else begin
dff2 <= dff1;
dff1 <= data_in;
end
assign data_out = dff2;
endmodule
| 7.300936 |
module aib_bit_sync #(
parameter DWIDTH = 1'b1, // Sync Data input
parameter [DWIDTH-1:0] RESET_VAL = {DWIDTH{1'b0}} // Reset value
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire [DWIDTH-1:0] data_in, // data in
output wire [DWIDTH-1:0] data_out // data out
);
reg [DWIDTH-1:0] dff2;
reg [DWIDTH-1:0] dff1;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
dff2 <= RESET_VAL;
dff1 <= RESET_VAL;
end else begin
dff2 <= dff1;
dff1 <= data_in;
end
assign data_out = dff2;
endmodule
| 6.995603 |
module aib_bscan (
input odat_asyn_aib, //async data RX from AIB
input async_data_adap, //async data TX from HSSI Adapter
input tx_async_en_adap, // TX asynchronous enable from Adapter
input jtag_tx_scanen_in, //JTAG shift DR, active high
input tx_jtag_clk_g, // Gated clock for TX shift register
input rx_jtag_clk_g, // Gated clock for RX shift register
input jtag_tx_scan_in, //JTAG TX data scan in
input jtag_mode_in, //JTAG mode select
input jtag_rstb_en, //reset_en from TAP
input jtag_rstb, //reset signal from TAP
input jtag_intest, //intest from TAP
output jtag_rx_scan_out, //JTAG TX scan chain output
output tx_async_en_aib, // TX asynchronous enable to AIB pad
output odat_asyn_adap, //async data RX to HSSI Adapter
output async_data_aib //async data TX to AIB
);
reg [1:0] tx_reg;
reg rx_reg;
reg rx_nreg;
wire [1:0] tx_shift;
wire [1:0] tx_intst;
wire rx_shift;
assign jtag_rx_scan_out = rx_nreg;
clk_mux async_data_aib_ckmux (
// Inputs
.clk1 (tx_reg[1]), // s=1
.clk2 (async_data_adap), // s=0
.s (jtag_mode_in),
// Outputs
.clkout(async_data_aib)
);
assign tx_async_en_aib = jtag_mode_in ? tx_reg[0] : tx_async_en_adap;
clk_mux odat_asyn_adap_ckmux (
// Inputs
.clk1 (rx_reg), // s=1
.clk2 (odat_asyn_aib), // s=0
.s (jtag_intest),
// Outputs
.clkout(odat_asyn_adap)
);
assign tx_shift[0] = (jtag_tx_scanen_in) ? tx_reg[1] : tx_intst[0];
clk_mux tx_shift_4_ckmux (
// Inputs
.clk1 (jtag_tx_scan_in), // s=1
.clk2 (tx_intst[1]), // s=0
.s (jtag_tx_scanen_in),
// Outputs
.clkout(tx_shift[1])
);
assign tx_intst[0] = (jtag_intest) ? tx_async_en_adap : tx_reg[0];
clk_mux tx_intst_4_ckmux (
// Inputs
.clk1 (async_data_adap), // s=1
.clk2 (tx_reg[1]), // s=0
.s (jtag_intest),
// Outputs
.clkout(tx_intst[1])
);
always @(posedge tx_jtag_clk_g) begin
tx_reg <= tx_shift;
end
clk_mux rx_shift_0_ckmux (
// Inputs
.clk1 (tx_reg[0]), // s=1
.clk2 (odat_asyn_adap), // s=0
.s (jtag_tx_scanen_in),
// Outputs
.clkout(rx_shift)
);
always @(posedge rx_jtag_clk_g) begin
rx_reg <= rx_shift;
end
always @(negedge rx_jtag_clk_g) begin
rx_nreg <= rx_reg;
end
endmodule
| 7.51874 |
module aib_bs_clk_gating (
// Inputs
input jtag_clk, // JTAG clock
input jtag_capture_dr, // Capture data register
input jtag_tx_scanen_in, // JTAG TX scan enable
input i_scan_mode, // Scan mode
// Outputs
output tx_jtag_clk_g, // JATG clock gated for transmit shift register
output rx_jtag_clk_g // JATG clock gated for receive shift register
);
wire rx_jtag_clk_en; // RX JTAG clock enable
// RX JTAG clock enable
assign rx_jtag_clk_en = jtag_tx_scanen_in | jtag_capture_dr;
// TX JTAG clock gate
clk_gate_cel clk_gate_tx_jtag (
.clkout(tx_jtag_clk_g), // Clock gated
.clk (jtag_clk), // Clock input
.en (jtag_tx_scanen_in), // Clock enable
.te (i_scan_mode) // Test enable
); // TX JTAG clock gate
// RX JTAG clock gate
clk_gate_cel clk_gate_rx_jtag (
.clkout(rx_jtag_clk_g), // Clock gated
.clk (jtag_clk), // Clock input
.en (rx_jtag_clk_en), // Clock enable
.te (i_scan_mode) // Test enable
); // RX JTAG clock gate
endmodule
| 7.319835 |
module aib_bus_sync #(
parameter DWIDTH = 1'b1, // Data bus width
parameter [DWIDTH-1:0] RESET_VAL = {DWIDTH{1'h0}} // Reset value
) (
// Inputs
input src_clk, // source clock
input dest_clk, // destination clock
input src_rst_n, // source async reset
input dest_rst_n, // destination async reset
input [DWIDTH-1:0] src_data, // Source data input
// Outputs
output reg [DWIDTH-1:0] dest_data_ff // destination data output
);
wire src_req_sync; // Data request in destination domain
wire if_ready; // Indicates CDC interface ready
wire dest_ack_sync; // Destination acknowledge
wire dest_sample; // Destination signal to sample source data
reg src_req_ff; // Source data request register
reg [DWIDTH-1:0] src_data_ff; // Source data register
reg dest_ack_ff; // Destination acknowledge register
//------------------------------------------------------------------------------
// Source Domain Logic
//------------------------------------------------------------------------------
// Data sample request
always @(posedge src_clk or negedge src_rst_n) begin : src_req_register
if (!src_rst_n) src_req_ff <= 1'b0;
else if (if_ready) src_req_ff <= ~src_req_ff;
end // block: src_req_register
// Source data register
always @(posedge src_clk or negedge src_rst_n) begin : src_data_register
if (!src_rst_n) src_data_ff[DWIDTH-1:0] <= RESET_VAL;
else if (if_ready) src_data_ff[DWIDTH-1:0] <= src_data[DWIDTH-1:0];
end // block: src_data_register
// Interace ready indication
assign if_ready = ~(src_req_ff ^ dest_ack_sync);
// Destination acknowledge synchronization
aib_bit_sync sync_ack_i (
// Inputs
.clk (src_clk), // clock
.rst_n (src_rst_n), // async reset
.data_in (dest_ack_ff), // data in
// Outputs
.data_out(dest_ack_sync) // data out
);
//------------------------------------------------------------------------------
// Source Domain Logic
//------------------------------------------------------------------------------
// Source request synchronization
aib_bit_sync sync_req_i (
// Inputs
.clk (dest_clk), // clock
.rst_n (dest_rst_n), // async reset
.data_in (src_req_ff), // data in
// Outputs
.data_out(src_req_sync) // data out
);
// Source acknowledge
always @(posedge dest_clk or negedge dest_rst_n) begin : dest_ack_register
if (!dest_rst_n) dest_ack_ff <= 1'b0;
else dest_ack_ff <= src_req_sync;
end // block: dest_ack_register
// samples data in destination domain
assign dest_sample = src_req_sync ^ dest_ack_ff;
// Destination data
always @(posedge dest_clk or negedge dest_rst_n) begin : dest_data_register
if (!dest_rst_n) dest_data_ff[DWIDTH-1:0] <= RESET_VAL;
else if (dest_sample) dest_data_ff[DWIDTH-1:0] <= src_data_ff[DWIDTH-1:0];
end // block: dest_data_register
endmodule
| 8.70459 |
module aib_cdc_data_mux #(
parameter DWIDTH = 'd80 // Data bus width
) (
// Inputs
input [DWIDTH-1:0] dmux_in0, // Data input for dmux_sel = 1
input [DWIDTH-1:0] dmux_in1, // Data input for dmux_sel = 0
input dmux_sel, // Data selection
// Outputs
output [DWIDTH-1:0] dmux_out // Data mux output
);
genvar i;
generate
for (i = 0; i < DWIDTH; i = i + 1) begin : dmux_out_gen
dmux_cell dmux_cell (
.d1 (dmux_in0[i]), // Data selected when selection = 1
.d2 (dmux_in1[i]), // Data selected when selection = 0
.s (dmux_sel), // Data selection
.o ( dmux_out[i]) // MUX output data
);
end
endgenerate
endmodule
| 9.05786 |
module aib_dcc (
// AIB IO Bidirectional
input clk_in,
input ms_dcc_cal_req,
input ms_tx_dcc_dll_lock_req,
input sl_dcc_cal_req,
input sl_rx_dcc_dll_lock_req,
output wire ms_dcc_cal_done,
output wire sl_dcc_cal_done,
output wire clk_out,
input ms_nsl,
input atpg_mode,
input reset_n
);
reg ms_dcc_cal_done_r, sl_dcc_cal_done_r;
wire ms_dcc_cal_donew, sl_dcc_cal_donew;
wire ms_dcc_cal_req_sync, sl_dcc_cal_req_sync;
wire reset_n_sync;
assign clk_out = clk_in;
assign ms_dcc_cal_done = ms_dcc_cal_done_r;
assign sl_dcc_cal_done = sl_dcc_cal_done_r;
assign ms_dcc_cal_donew = !ms_tx_dcc_dll_lock_req ? 1'b0 :
(ms_nsl & ms_dcc_cal_req_sync ) ? 1'b1 : ms_dcc_cal_done_r;
assign sl_dcc_cal_donew = !sl_rx_dcc_dll_lock_req ? 1'b0 :
(!ms_nsl & sl_dcc_cal_req_sync ) ? 1'b1 : sl_dcc_cal_done_r;
aib_rstnsync aib_rstnsync (
.clk (clk_in), // Destination clock of reset to be synced
.i_rst_n (reset_n), // Asynchronous reset input
.scan_mode (atpg_mode), // Scan bypass for reset
.sync_rst_n(reset_n_sync) // Synchronized reset output
);
aib_bitsync i_mstxdlldcclockreq (
.clk(clk_in),
.rst_n(reset_n_sync),
.data_in(ms_dcc_cal_req),
.data_out(ms_dcc_cal_req_sync)
);
aib_bitsync i_sltxdlldcclockreq (
.clk(clk_in),
.rst_n(reset_n_sync),
.data_in(sl_dcc_cal_req),
.data_out(sl_dcc_cal_req_sync)
);
always @(posedge clk_in or negedge reset_n_sync) begin
if (~reset_n_sync) begin
ms_dcc_cal_done_r <= 1'b0;
sl_dcc_cal_done_r <= 1'b0;
end else begin
ms_dcc_cal_done_r <= ms_dcc_cal_donew;
sl_dcc_cal_done_r <= sl_dcc_cal_donew;
end
end
endmodule
| 7.294203 |
module aib_dll_ctrl_logic (
input [2:0] freq_range_sel,
output reg [2:0] trim_ctrl_bits
);
always @(*) begin
case (freq_range_sel)
3'b000: trim_ctrl_bits = 3'b100;
3'b001: trim_ctrl_bits = 3'b101;
3'b010: trim_ctrl_bits = 3'b110;
3'b011: trim_ctrl_bits = 3'b111;
3'b100: trim_ctrl_bits = 3'b000;
3'b101: trim_ctrl_bits = 3'b001;
3'b110: trim_ctrl_bits = 3'b010;
3'b111: trim_ctrl_bits = 3'b011;
endcase
end
//========================Frequency LUT======================================
//Freq_range_sel(GHz) Min Max Trim bits(Current trim and cap trim)
// 3'b000 3.2 2.6 3'b100
// 3'b001 2.6 2.1 3'b101
// 3'b010 2.1 1.7 3'b110
// 3'b011 1.7 1.4 3'b111
// 3'b100 1.4 1.1 3'b000
// 3'b101 1.1 0.85 3'b001
// 3'b110 0.85 0.65 3'b010
// 3'b111 0.65 0.50 3'b011
//========================Frequency LUT======================================
endmodule
| 8.733237 |
module aib_fifo_and_sel #(
parameter DWIDTH = 80
) (
output [DWIDTH-1:0] fifo_out_sel, // FIFO output ANDed with read enable
input fifo_rd_en, // FIFO read enable
input [DWIDTH-1:0] fifo_rd_in // FIFO data in write domain
);
// AND logic selects the asynchronous bus only when data is stable
assign fifo_out_sel = fifo_rd_in[DWIDTH-1:0] & {DWIDTH{fifo_rd_en}};
endmodule
| 8.309568 |
module aib_fifo_rdata_buf #(
parameter DWIDTH = 80 // FIFO Input data width
) (
// Output
output reg [DWIDTH-1:0] fifo_rdata_ff,
// Input
input [DWIDTH-1:0] fifo_rdata,
input rd_clk,
input rd_rst_n
);
always @(posedge rd_clk or negedge rd_rst_n) begin
if (!rd_rst_n) fifo_rdata_ff <= {DWIDTH{1'b0}};
else fifo_rdata_ff <= fifo_rdata;
end
endmodule
| 7.18425 |
module aib_mux21 (
input wire mux_in0, // mux in 0
input wire mux_in1, // mux in 1
input wire mux_sel, // mux selector
output wire mux_out // mux out
);
assign mux_out = mux_sel ? mux_in1 : mux_in0;
endmodule
| 8.141275 |
module aib_redundancy ( //input of input mux
idata0_in1,
idata0_in0,
idata1_in1,
idata1_in0,
idataselb_in1,
idataselb_in0,
iddren_in1,
iddren_in0,
irxen_in1,
irxen_in0,
itxen_in1,
itxen_in0,
async_dat_in1,
async_dat_in0,
//Output of input mux
idata0_out,
idata1_out,
idataselb_out,
iddren_out,
irxen_out,
itxen_out,
async_dat_out,
//input of output mux
odat0_in1,
odat0_in0,
odat1_in1,
odat1_in0,
odat_async_in1,
odat_async_in0,
//Output of output mux
odat0_out,
odat1_out,
odat_async_out,
//Mux selection signal
shift_en
);
//Mux selection signal
input shift_en;
//input of input mux
input idata0_in1, idata0_in0;
input idata1_in1, idata1_in0;
input idataselb_in1, idataselb_in0;
input iddren_in1, iddren_in0;
input [2:0] irxen_in1, irxen_in0;
input itxen_in1, itxen_in0;
input async_dat_in1, async_dat_in0;
//output of input mux
output idata0_out;
output idata1_out;
output idataselb_out;
output iddren_out;
output [2:0] irxen_out;
output itxen_out;
output async_dat_out;
//input of output mux
input odat0_in1, odat0_in0;
input odat1_in1, odat1_in0;
input odat_async_in1, odat_async_in0;
//output of output mux
output odat0_out;
output odat1_out;
output odat_async_out;
// Buses in the design
//input mux
assign idata0_out = shift_en ? idata0_in1 : idata0_in0;
assign idata1_out = shift_en ? idata1_in1 : idata1_in0;
assign idataselb_out = shift_en ? idataselb_in1 : idataselb_in0;
assign iddren_out = shift_en ? iddren_in1 : iddren_in0;
assign irxen_out[2] = shift_en ? irxen_in1[2] : irxen_in0[2];
assign irxen_out[1] = shift_en ? irxen_in1[1] : irxen_in0[1];
assign irxen_out[0] = shift_en ? irxen_in1[0] : irxen_in0[0];
assign itxen_out = shift_en ? itxen_in1 : itxen_in0;
//Change to CKMUX
//assign async_dat_out = shift_en? async_dat_in1 : async_dat_in0;
aib_mux21 async_dat_out_ckmux (
.mux_in0(async_dat_in0),
.mux_in1(async_dat_in1),
.mux_sel(shift_en),
.mux_out(async_dat_out)
);
//output mux
assign odat0_out = shift_en ? odat0_in1 : odat0_in0;
assign odat1_out = shift_en ? odat1_in1 : odat1_in0;
//Change to CKMUX
//assign odat_async_out = shift_en? odat_async_in1 : odat_async_in0;
aib_mux21 odat_async_out_ckmux (
.mux_in0(odat_async_in0),
.mux_in1(odat_async_in1),
.mux_sel(shift_en),
.mux_out(odat_async_out)
);
endmodule
| 7.263786 |
module aib_rstnsync (
input wire clk, // Destination clock of reset to be synced
input wire i_rst_n, // Asynchronous reset input
input wire scan_mode, // Scan bypass for reset
output wire sync_rst_n // Synchronized reset output
);
reg first_stg_rst_n;
wire prescan_sync_rst_n;
always @(posedge clk or negedge i_rst_n)
if (!i_rst_n) first_stg_rst_n <= 1'b0;
else first_stg_rst_n <= 1'b1;
aib_bitsync #(
.DWIDTH(1),
.RESET_VAL(0)
) i_sync_rst_n (
.clk (clk),
.rst_n (i_rst_n),
.data_in (first_stg_rst_n),
.data_out(prescan_sync_rst_n)
);
assign sync_rst_n = scan_mode ? i_rst_n : prescan_sync_rst_n;
endmodule
| 8.66439 |
module aib_rst_sync (
input clk, // Destination clock of reset to be synced
input i_rst_n, // Asynchronous reset input
input scan_mode, // Scan bypass for reset
output sync_rst_n // Synchronized reset output
);
wire prescan_sync_rst_n;
aib_bit_sync #(
.DWIDTH(1),
.RESET_VAL(0)
) i_sync_rst_n (
.clk (clk),
.rst_n (i_rst_n),
.data_in (1'b1),
.data_out(prescan_sync_rst_n)
);
// Scan mux
dmux_cell rst_dmux_out (
.o (sync_rst_n), // Output
.d1(i_rst_n), // Data 1 (s=1)
.d2(prescan_sync_rst_n), // Data 2 (s=0)
.s (scan_mode) // Data selection
);
endmodule
| 8.44053 |
module aib_rx_dbi (
// Inputs
input wire rst_n, // Asynchronous reset
input wire clk, // Clock
input wire [79:0] data_in, // Data input before DBI logic
input wire dbi_en, // Data inversion enable
// Outputs
output wire [79:0] data_out // Output data after DBI logic
);
wire [3 : 0] dbi_calc; // Bits 79, 78, 39 and 38 used on DBI calculation
wire [ 37:0] dbi_dat_lo; // Low word with DB calculation - bits from 37-0
wire [ 37:0] dbi_dat_hi; // High word with DB calculation - bits from 77-40
reg [ 79:0] dbi_data_out; // Register data after DBI calculation
// DBI output mux selects data accoding to DBI enable
assign data_out = dbi_en ? dbi_data_out : data_in;
// Data bits 79, 78, 39 and 38 used on DBI calculation
assign dbi_calc = {data_in[79], data_in[78], data_in[39], data_in[38]};
// Calculation of DBI low word and DBI high word
genvar j; // Generate index
generate
for (j = 0; j < 19; j = j + 1) begin : data_out_gen
assign dbi_dat_lo[2*j] = data_in[2*j] ^ dbi_calc[0];
assign dbi_dat_lo[2*j+1] = data_in[2*j+1] ^ dbi_calc[1];
assign dbi_dat_hi[2*j] = data_in[2*j+40] ^ dbi_calc[2];
assign dbi_dat_hi[2*j+1] = data_in[2*j+1+40] ^ dbi_calc[3];
end // block data_out_gen
endgenerate
// Output register to latch DBI calculation
always @(posedge clk or negedge rst_n) begin : dbi_data_out_register
if (!rst_n) begin
dbi_data_out <= 80'h0;
end else begin
dbi_data_out <= {dbi_calc[3:2], dbi_dat_hi, dbi_calc[1:0], dbi_dat_lo};
end
end // block: dbi_data_out_register
endmodule
| 6.758807 |
module AICPU (
input acr_clk,
input acr_rst,
output [31:0] axi_awaddr,
output [3:0] axi_awlen,
output [2:0] axi_awsize,
output [1:0] axi_awburst,
output axi_awlock,
output [3:0] axi_awcache,
output [2:0] axi_awprot,
output axi_awvalid,
input axi_awready,
output [63:0] axi_wdata,
output [7:0] axi_wstrb,
output axi_wlast,
output axi_wvalid,
input axi_wready,
input [7:0] axi_bid,
input [1:0] axi_bresp,
input axi_bvalid,
output axi_bready,
output [7:0] axi_arid,
output [31:0] axi_araddr,
output [3:0] axi_arlen,
output [2:0] axi_arsize,
output [1:0] axi_arburst,
output axi_arlock,
output [3:0] axi_arcache,
output [2:0] axi_arprot,
output axi_arvalid,
input axi_arready,
input [7:0] axi_rid,
input [63:0] axi_rdata,
input [1:0] axi_rresp,
input axi_rlast,
input axi_rvalid,
output axi_rready
);
endmodule
| 7.320631 |
module AIDMA (
input acr_clk,
input acr_rst,
output [31:0] axi_awaddr,
output [3:0] axi_awlen,
output [2:0] axi_awsize,
output [1:0] axi_awburst,
output axi_awlock,
output [3:0] axi_awcache,
output [2:0] axi_awprot,
output axi_awvalid,
input axi_awready,
output [63:0] axi_wdata,
output [7:0] axi_wstrb,
output axi_wlast,
output axi_wvalid,
input axi_wready,
input [7:0] axi_bid,
input [1:0] axi_bresp,
input axi_bvalid,
output axi_bready,
output [7:0] axi_arid,
output [31:0] axi_araddr,
output [3:0] axi_arlen,
output [2:0] axi_arsize,
output [1:0] axi_arburst,
output axi_arlock,
output [3:0] axi_arcache,
output [2:0] axi_arprot,
output axi_arvalid,
input axi_arready,
input [7:0] axi_rid,
input [63:0] axi_rdata,
input [1:0] axi_rresp,
input axi_rlast,
input axi_rvalid,
output axi_rready
);
endmodule
| 6.577363 |
module ainv_checker
#(parameter `BSG_INV_PARAM(data_width_p))
(
input clk_i
, input reset_i
, input en_i
, input [data_width_p-1:0] data_o
, input v_o
, input yumi_i
);
// ainv test is setup in such way that it should only return zero.
always_ff @ (posedge clk_i) begin
if (~reset_i & en_i & v_o & yumi_i)
assert(data_o == '0)
else $fatal("zero output expected.");
end
endmodule
| 6.965132 |
module AISO (
clk,
reset,
reset_s
);
input clk, reset;
output reset_s;
reg temp_res1, temp_res2;
always @(posedge clk or posedge reset) begin
if (reset) temp_res1 <= 1'b0;
else temp_res1 <= 1'b1;
end
always @(posedge clk or posedge reset) begin
if (reset) temp_res2 <= 1'b0;
else temp_res2 <= temp_res1;
end
assign reset_s = ~temp_res2;
endmodule
| 6.553451 |
module models a circuit which takes an asynchronous input,
in this case coming from the reset button, and outputs a
synchronous signal. This is achieved through the use of
a synchronous flop called 'delay_reg'. Synchronous resets will
only reset the state of flops in the system on the active edge
of the clock.
*
* In submitting this file for class work at CSULB, I am confirming that this
is my work and the work of no one else.
*
* In the event other code sources are utilized I will document which portion
of the code and who is the author.
*
* In submitting this code I acknowledge that plagiarism in student project
work is subject to dismissal from the class.
*===========================================================================*/
`timescale 1ns / 1ps
module aiso_rst(clk, reset, reset_s);
input clk, reset;
output reset_s;
reg delay_reg, synch_reg;
always @ (posedge clk, posedge reset)
if (reset)
{delay_reg, synch_reg} <= {1'b0, 1'b0};
else // synchronize the output
{delay_reg, synch_reg} <= {1'b1, delay_reg};
assign reset_s = ~synch_reg; //make the reset HIGH active
endmodule
| 6.591859 |
module AISRAM (
input acr_clk,
input acr_rst,
input [31:0] axi_awaddr,
input [3:0] axi_awlen,
input [2:0] axi_awsize,
input [1:0] axi_awburst,
input axi_awlock,
input [3:0] axi_awcache,
input [2:0] axi_awprot,
input axi_awvalid,
output axi_awready,
input [63:0] axi_wdata,
input [7:0] axi_wstrb,
input axi_wlast,
input axi_wvalid,
output axi_wready,
output [7:0] axi_bid,
output [1:0] axi_bresp,
output axi_bvalid,
input axi_bready,
input [7:0] axi_arid,
input [31:0] axi_araddr,
input [3:0] axi_arlen,
input [2:0] axi_arsize,
input [1:0] axi_arburst,
input axi_arlock,
input [3:0] axi_arcache,
input [2:0] axi_arprot,
input axi_arvalid,
output axi_arready,
output [7:0] axi_rid,
output [63:0] axi_rdata,
output [1:0] axi_rresp,
output axi_rlast,
output axi_rvalid,
input axi_rready
);
endmodule
| 7.06409 |
module Axis_Ctrl_18BitWidth (
Clk,
gRst,
Addr,
MCUportL,
WR,
CS,
Din,
PosLock,
Ref,
Protect,
MO,
nStanby,
DRVRst,
PlsOut,
Dir,
Torque1,
Torque2,
DQtoMCU
);
/*
Axis_Ctrl Axis_Ctrl(
.Clk(),
.gRst(),
.Addr(),
.MCUportL(),
.WR(),
.CS(),
.Din(),
.PosLock(),
.Ref(),
.Protect(),
.MO(),
.nStanby(),
.DRVRst(),
.PlsOut(),
.Dir(),
.DQtoMCU()
);
*/
input Clk;
input gRst;
input [7:0] Addr;
input [15:0] MCUportL;
input WR;
input CS;
input [7:0] Din;
input PosLock;
input Ref;
input Protect;
input MO;
output nStanby;
output DRVRst;
output PlsOut;
output Dir;
output Torque1, Torque2;
output [7:0] DQtoMCU;
wire [15:0] AxisStateCmd;
wire [ 7:0] AxisPlsCmd;
wire [ 7:0] SpeedCmd;
wire [15:0] RefPos;
assign Torque1 = AxisStateCmd[0];
assign Torque2 = AxisStateCmd[1];
assign DirRev = AxisStateCmd[2];
assign DirCmd = AxisStateCmd[3];
wire Dir = ((~DirCmd) & DirRev) | ((DirCmd) & (~DirRev)); //xor ,ߵƽЧ
assign nStanby = AxisStateCmd[4]; //رоƬʡģʽ
assign DRVRst = AxisStateCmd[5]; //رоƬλ
assign RefEn_MCU = AxisStateCmd[8];
assign PlsClr = AxisPlsCmd[0];
assign StepPls = AxisPlsCmd[1];
assign RefClr = AxisPlsCmd[2];
wire SpeedSet;
wire SpeedSetDone;
wire WR_CS = WR | CS;
Axis_WR Axis_WR (
.Clk(WR_CS),
.Addr(Addr),
.MCUportL(MCUportL),
.Din(Din),
.SpeedSetDone(SpeedSetDone),
.SpeedSet(SpeedSet),
.AxisStateCmd(AxisStateCmd),
.AxisPlsCmd(AxisPlsCmd),
.SpeedCmd(SpeedCmd),
.RefPos(RefPos)
);
reg[17:0] PlsCnt;
reg RefDone;
wire[7:0] AxisState = {4'h0,Ref,RefDone,Protect,MO};
wire Continuepls;
assign PlsOut = StepPls | Continuepls;
Axis_RD Axis_RD (
.PClk(Continuepls),
.Addr(Addr),
.PosLock(PosLock),
.PlsCnt(PlsCnt[17:2]),
.Axis(AxisState),
.Din(Din),
.DQ(DQtoMCU)
);
PlsMaker PlsMaker (
.Clk(Clk),
.gRst(gRst),
// .DirCmd(DirCmd),
.SpeedCmd(SpeedCmd),
.SpeedSet(SpeedSet),
.SpeedSetDone(SpeedSetDone),
// .RefClr(RefClr),
// .PlsClr(PlsClr),
// .Ref(Ref),
// .RefPos(RefPos),
// .RefEn(RefEn_MCU),
.Pls_Out(Continuepls)
// .PlsCnt(PlsCnt),
// .RefDone(RefDone)
);
reg Ref0;
reg Ref1;
reg Refpls;
always @(posedge Clk) begin
Ref0 <= Ref;
Ref1 <= Ref0;
end
wire RefEn = (~RefDone) & RefEn_MCU;
always @(posedge Clk) begin
if (RefEn) Refpls <= (~Ref0) & Ref1;
else Refpls <= 1'b0;
end
wire RefDoneClr = gRst | RefClr;
always @(posedge RefDoneClr or posedge Refpls) begin
if (RefDoneClr) RefDone <= 1'b0;
else RefDone <= 1'b1;
end
wire PlsCntClr = PlsClr | gRst | Refpls;
always @(posedge Continuepls or posedge PlsCntClr) begin
if (PlsCntClr) PlsCnt <= 18'h0;
else if (DirCmd) PlsCnt <= PlsCnt + 1'b1;
else PlsCnt <= PlsCnt - 1'b1;
end
endmodule
| 6.753627 |
module ai_accel (
rst_n, // Reset Neg
clk, // Clk
addr, // Address
wr_en, //Write enable
accel_select,
data_in,
data_out, // Output Data
a_mem,
b_mem,
c_mem,
a_show,
b_show,
c_show
);
localparam N = 8;
localparam BITS = 8;
localparam a_offcet = 10'd128;
localparam b_offcet = a_offcet + 10'd64;
localparam c_offcet = b_offcet + 10'd64;
input rst_n;
input clk;
input [9:0] addr;
input wr_en;
input accel_select;
input [31:0] data_in;
output [31:0] data_out;
output a_mem;
output b_mem;
output c_mem;
output a_show;
output b_show;
output c_show;
wire [N*N*BITS-1:0] a_all, b_all, c_all;
wire [31:0] a_in, b_in, a_out, b_out, c_out;
wire [9:0] a_addr, b_addr, c_addr;
wire a_wr, b_wr, c_wr, a_redy, b_redy;
assign a_wr = accel_select & (addr >= a_offcet) & (addr < b_offcet);
assign b_wr = accel_select & (addr >= b_offcet) & (addr < c_offcet);
assign c_wr = accel_select & (addr >= c_offcet) & (addr < c_offcet + N * BITS);
assign a_addr = addr - a_offcet;
assign b_addr = addr - b_offcet;
assign c_addr = addr - c_offcet;
assign data_out = wr_en ? 31'h0 : a_wr ? a_out : b_wr ? b_out : c_wr ? c_out : 31'h0;
one_matrix a_mat (
.in(data_in),
.addr(a_addr),
.select(a_wr),
.wr_one(wr_en),
.clk(clk),
.show(a_show),
.rst(rst_n),
.one_out(a_out),
.mem_out(a_all),
.one_stored(a_mem),
.ready(a_redy)
);
one_matrix b_mat (
.in(data_in),
.addr(a_addr),
.select(b_wr),
.wr_one(wr_en),
.clk(clk),
.show(b_show),
.rst(rst_n),
.one_out(b_out),
.mem_out(b_all),
.one_stored(b_mem),
.ready(b_redy)
);
one_matrix c_mat (
.mem_in(c_all),
.addr(c_addr),
.select(c_wr),
.wr_all(a_redy & b_redy),
.clk(clk),
.rst(rst_n),
.one_out(c_out),
.show(c_show)
);
MAT_MULT#(
.BITS(BITS),
.N(N)
) (
.A(a_all), .B(b_all), .C(c_all)
);
endmodule
| 6.737985 |
module adder (
a,
b,
c,
d
);
input [31:0] a;
input [31:0] b;
input [31:0] c;
output [31:0] d;
wire [15:0] e;
assign e = a[31:24] + b[31:24] + c[31:24]
+ a[23:16] + b[23:16] + c[23:16]
+ a[15:8] + b[15:8] + c[15:8];
assign d = e > 8'hff ? 8'hff : e[7:0];
endmodule
| 7.4694 |
module AI_Engine (
clk,
pl,
en,
RST,
location_vectors_w,
location_vectors_b,
alive_vectors_w,
alive_vectors_b,
piece_to_move,
output_move,
done,
move_vec_P,
move_vec_R,
move_vec_N,
move_vec_B,
move_vec_Q,
move_vec_K,
pieceId,
ready,
end_moves
);
input clk;
input en;
input RST;
input pl;
input [1:0] move_vec_P; //Format: (U(00)/U2(01)/UL(10)/UR(11)(2-bit));
input [4:0] move_vec_R; //Format: (L(00)/R(01)/U(10)/D(11)(2-bit):Squares(3-bit)).
input [2:0] move_vec_N; //Format: (LD(000)/LU(001)/UL(010)/UR(011)/RU(100)/RD(101)/DL(110)/DR(111)(3-bit)).
input [2:0] move_vec_B; //Format: (UL(00)/UR(01)/DL(10)/DR(11)(2-bit):Squares(3-bit)).
input [5:0] move_vec_Q; //Format: (L(000)/R(001)/U(010)/D(011)/UL(100)/UR(101)/DL(110)/DR(111)(3-bit):Squares(3-bit)).
input [2:0] move_vec_K; //Format: (L(000)/R(001)/U(010)/D(011)/UL(100)/UR(101)/DL(110)/DR(111)(3-bit)).
input [3:0] pieceId;
input ready;
input end_moves;
output [95:0] location_vectors_b;
output [95:0] location_vectors_w;
output [15:0] alive_vectors_w;
output [15:0] alive_vectors_b;
output [5:0] output_move;
output [3:0] piece_to_move;
output done;
// parameters that will be written as constants in code
parameter BLACK = 1'b0;
parameter WHITE = 1'b1;
parameter P1 = 4'b1111;
parameter P2 = 4'b1110;
parameter P3 = 4'b1101;
parameter P4 = 4'b1100;
parameter P5 = 4'b1011;
parameter P6 = 4'b1010;
parameter P7 = 4'b1001;
parameter P8 = 4'b1000;
parameter R1 = 4'b0111;
parameter R2 = 4'b0110;
parameter N1 = 4'b0101;
parameter N2 = 4'b0100;
parameter B1 = 4'b0011;
parameter B2 = 4'b0010;
parameter Q1 = 4'b0001;
parameter K1 = 4'b0000;
parameter MAX_DEPTH = 5;
parameter HEUR_WIDTH = 10;
//states in the fsm
parameter RESET = 4'b0000;
parameter EXPLORE = 4'b0001;
// end states
reg [5:0] best_move_d;
reg [5:0] best_move_q;
reg [5:0] last_move_d;
reg [5:0] last_move_q;
reg [1:0] state_d;
reg [1:0] state_q;
reg [3:0] piece_to_move_q;
reg [3:0] piece_to_move_d;
reg done_q;
reg done_d;
reg en_q;
reg pl_q;
reg pl_d;
assign output_move = best_move_q;
assign done = done_q;
assign piece_to_move = piece_to_move_q;
wire [HEUR_WIDTH:0] alpha_w;
reg signed [HEUR_WIDTH:0] alpha_d;
reg signed [HEUR_WIDTH:0] alpha_q;
wire [HEUR_WIDTH:0] beta_w;
reg signed [HEUR_WIDTH:0] beta_d;
reg signed [HEUR_WIDTH:0] beta_q;
wire [HEUR_WIDTH:0] best_value_w;
reg signed [HEUR_WIDTH:0] best_value_d;
reg signed [HEUR_WIDTH:0] best_value_q;
reg signed [HEUR_WIDTH:0] max_p_d;
reg signed [HEUR_WIDTH:0] max_p_q;
always @(*) begin
done_d = done_q;
best_move_d = best_move_q;
max_p_d = max_p_q;
best_value_d = best_value_q;
alpha_d = alpha_w;
beta_d = beta_w;
last_move_d = last_move_q;
piece_to_move_d = piece_to_move_q;
case (state_q)
RESET: begin
if (en_q) begin
state_d = EXPLORE;
best_move_d = 0;
piece_to_move_d = 0;
last_move_d = 0;
pl_d = pl_q;
alpha_d = 11'b10000000001; //very low neg
beta_d = 11'b01111111111; //very high pos
end else begin
state_d = RESET;
end
done_d = 1'b0;
end
EXPLORE: begin
end
endcase
end
// all flip flops
always @(posedge clk) begin
if (RST) begin
state_q <= RESET;
done_q <= 0;
last_move_q <= 0;
best_move_q <= 0;
piece_to_move_q <= 0;
best_value_q <= 0;
alpha_q <= 0;
beta_q <= 0;
pl_q <= BLACK;
max_p_q <= 0;
en_q <= 0;
end else begin
en_q <= en;
piece_to_move_q <= piece_to_move_d;
state_q <= state_d;
best_move_q <= best_move_d;
last_move_q <= last_move_d;
done_q <= done_d;
best_value_q <= best_value_d;
alpha_q <= alpha_d;
beta_q <= beta_d;
max_p_q <= max_p_d;
pl_q <= pl_d;
end
end
endmodule
| 6.658475 |
module AI_Engine (
clk,
pl,
en,
RST,
location_vectors_w,
location_vectors_b,
alive_vectors_w,
alive_vectors_b,
piece_to_move,
output_move,
done,
move_vec_P,
move_vec_R,
move_vec_N,
move_vec_B,
move_vec_Q,
move_vec_K,
pieceId,
ready,
end_moves
);
input clk;
input en;
input RST;
input pl;
input [1:0] move_vec_P; //Format: (U(00)/U2(01)/UL(10)/UR(11)(2-bit));
input [4:0] move_vec_R; //Format: (L(00)/R(01)/U(10)/D(11)(2-bit):Squares(3-bit)).
input [2:0] move_vec_N; //Format: (LD(000)/LU(001)/UL(010)/UR(011)/RU(100)/RD(101)/DL(110)/DR(111)(3-bit)).
input [2:0] move_vec_B; //Format: (UL(00)/UR(01)/DL(10)/DR(11)(2-bit):Squares(3-bit)).
input [5:0] move_vec_Q; //Format: (L(000)/R(001)/U(010)/D(011)/UL(100)/UR(101)/DL(110)/DR(111)(3-bit):Squares(3-bit)).
input [2:0] move_vec_K; //Format: (L(000)/R(001)/U(010)/D(011)/UL(100)/UR(101)/DL(110)/DR(111)(3-bit)).
input [3:0] pieceId;
input ready;
input end_moves;
output [95:0] location_vectors_b;
output [95:0] location_vectors_w;
output [15:0] alive_vectors_w;
output [15:0] alive_vectors_b;
output [5:0] output_move;
output [3:0] piece_to_move;
output done;
// parameters that will be written as constants in code
parameter BLACK = 1'b0;
parameter WHITE = 1'b1;
parameter P1 = 4'b1111;
parameter P2 = 4'b1110;
parameter P3 = 4'b1101;
parameter P4 = 4'b1100;
parameter P5 = 4'b1011;
parameter P6 = 4'b1010;
parameter P7 = 4'b1001;
parameter P8 = 4'b1000;
parameter R1 = 4'b0111;
parameter R2 = 4'b0110;
parameter N1 = 4'b0101;
parameter N2 = 4'b0100;
parameter B1 = 4'b0011;
parameter B2 = 4'b0010;
parameter Q1 = 4'b0001;
parameter K1 = 4'b0000;
parameter MAX_DEPTH = 5;
parameter HEUR_WIDTH = 10;
//states in the fsm
parameter RESET = 4'b0000;
parameter EXPLORE = 4'b0001;
// end states
reg [5:0] best_move_d;
reg [5:0] best_move_q;
reg [5:0] last_move_d;
reg [5:0] last_move_q;
reg [1:0] state_d;
reg [1:0] state_q;
reg [3:0] piece_to_move_q;
reg [3:0] piece_to_move_d;
reg done_q;
reg done_d;
reg en_q;
reg pl_q;
reg pl_d;
assign output_move = best_move_q;
assign done = done_q;
assign piece_to_move = piece_to_move_q;
wire [HEUR_WIDTH:0] alpha_w;
reg signed [HEUR_WIDTH:0] alpha_d;
reg signed [HEUR_WIDTH:0] alpha_q;
wire [HEUR_WIDTH:0] beta_w;
reg signed [HEUR_WIDTH:0] beta_d;
reg signed [HEUR_WIDTH:0] beta_q;
wire [HEUR_WIDTH:0] best_value_w;
reg signed [HEUR_WIDTH:0] best_value_d;
reg signed [HEUR_WIDTH:0] best_value_q;
reg signed [HEUR_WIDTH:0] max_p_d;
reg signed [HEUR_WIDTH:0] max_p_q;
always @(*) begin
done_d = done_q;
best_move_d = best_move_q;
max_p_d = max_p_q;
best_value_d = best_value_q;
alpha_d = alpha_w;
beta_d = beta_w;
last_move_d = last_move_q;
piece_to_move_d = piece_to_move_q;
case (state_q)
RESET: begin
if (en_q) begin
state_d = EXPLORE;
best_move_d = 0;
piece_to_move_d = 0;
last_move_d = 0;
pl_d = pl_q;
alpha_d = 11'b10000000001; //very low neg
beta_d = 11'b01111111111; //very high pos
end else begin
state_d = RESET;
end
done_d = 1'b0;
end
EXPLORE: begin
end
endcase
end
// all flip flops
always @(posedge clk) begin
if (RST) begin
state_q <= RESET;
done_q <= 0;
last_move_q <= 0;
best_move_q <= 0;
piece_to_move_q <= 0;
best_value_q <= 0;
alpha_q <= 0;
beta_q <= 0;
pl_q <= BLACK;
max_p_q <= 0;
en_q <= 0;
end else begin
en_q <= en;
piece_to_move_q <= piece_to_move_d;
state_q <= state_d;
best_move_q <= best_move_d;
last_move_q <= last_move_d;
done_q <= done_d;
best_value_q <= best_value_d;
alpha_q <= alpha_d;
beta_q <= beta_d;
max_p_q <= max_p_d;
pl_q <= pl_d;
end
end
endmodule
| 6.658475 |
module ai_top (
clk,
rst,
wr,
addr_i,
addr_o,
i
);
// parameters
parameter WIDTH = 32;
parameter N_IN = 2;
parameter N_OUT = 2;
parameter N_HL = 1;
parameter N_HL_P = 3;
// common ports
input clk, rst;
// control ports
input wr;
input [7:0] addr_i;
input [7:0] addr_o;
// input ports
input signed [N_IN*WIDTH-1:0] i;
// wires
wire [ N_IN*WIDTH-1:0] read_i_mem;
wire [N_OUT*WIDTH-1:0] o_array;
i_mem #(
.WIDTH(N_IN * WIDTH)
) i_mem (
.clk(clk),
.rst(rst),
.addr(addr_i),
.wr(wr),
.i(i),
.o(read_i_mem)
);
array #(
.N_IN (N_IN),
.N_OUT (N_OUT),
.N_HL (N_HL),
.N_HL_P(N_HL_P),
.WIDTH (WIDTH)
) arr (
.clk(clk),
.rst(rst),
.wr (wr),
.i (read_i_mem),
.o (o_array)
);
o_mem #(
.WIDTH(N_OUT * WIDTH)
) o_mem (
.clk(clk),
.rst(rst),
.addr(addr_o),
.wr(wr),
.i(o_array),
.o()
);
endmodule
| 8.245377 |
module ai_top_tb ();
// parameters
parameter WIDTH = 32;
// registers
reg clk;
reg rst;
reg wr;
reg [7:0] addr_i;
reg [7:0] addr_o;
reg [63:0] i;
ai_top #(
.WIDTH (WIDTH),
.N_IN (2),
.N_OUT (2),
.N_HL (1),
.N_HL_P(3)
) inst_ai_top (
.clk (clk),
.rst (rst),
.wr (wr),
.addr_i(addr_i),
.addr_o(addr_o),
.i (i)
);
initial begin
clk = 1;
rst = 1;
wr = 0;
addr_i = 8'd0;
addr_o = 8'd0;
i = 64'd0;
#100;
rst = 0;
end
always begin
clk = !clk;
#50;
end
endmodule
| 6.601401 |
module AJ (
clock,
angle,
Xin,
Yin,
Xout,
Yout,
Zout
);
//Declaracao do clock
input clock;
//Declaracao das variaveis de entrada
input [15:0] angle, Xin, Yin;
//Declaracao das variaveis de saida
output [15:0] Xout;
output [15:0] Yout;
output [15:0] Zout;
//Declaracao da matriz que contera os valores do arco tangente necessario ao calculo.
//Para realizar os calculos da atan utilizei o ponto fixo 16384 para melhor representar os valores.
wire [15:0] atan[0:11];
assign atan[00] = 16'd12868;
assign atan[01] = 16'd7597;
assign atan[02] = 16'd4014;
assign atan[03] = 16'd2038;
assign atan[04] = 16'd1023;
assign atan[05] = 16'd512;
assign atan[06] = 16'd256;
assign atan[07] = 16'd128;
assign atan[08] = 16'd64;
assign atan[09] = 16'd32;
assign atan[10] = 16'd16;
assign atan[11] = 16'd8;
//Declaracao dos registradores que criara o vetor dos valores
reg [15:0] X[0:11];
reg [15:0] Y[0:11];
reg [15:0] Z[0:11];
// assign X_shift = X[i] >> i ;
//assign Y_shift = Y[i] >> i ;
genvar i;
generate
for (i = 0; i < 11; i = i + 1) begin : cordic
always @(posedge clock) begin
if(Y[i][15] == 1) // Teste para saber se o sinal do Y é positivo ou negativo.
begin
// O problema é que agora os valores aparecem unicamente no final, não constantemente como o Zout.
X[i+1] <= (X[i]) + Y[i] >> i;
Y[i+1] <= (Y[i]) - X[i] >> i;
Z[i+1] <= (Z[i]) + atan[i];
end else begin
X[i+1] <= (X[i]) - Y[i] >> i;
Y[i+1] <= (Y[i]) + X[i] >> i; //X_shift ;
Z[i+1] <= (Z[i]) - atan[i];
end
end
end
endgenerate
always @(posedge clock) begin
X[0] <= Xin;
Y[0] <= Yin;
Z[0] <= angle;
end
assign Xout = X[i];
assign Yout = Y[i];
assign Zout = Z[i];
endmodule
| 7.039364 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module StimOr; // 3
wire c;
reg a, b;
OrGate OG_Out (
a,
b,
c
);
initial begin
a = 1'b0;
b = 1'b0;
#100 a = 1'b1;
b = 1'b0;
#100 a = 1'b0;
b = 1'b1;
#100 a = 1'b1;
b = 1'b1;
#100;
end
endmodule
| 6.667907 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module XorGate (
a,
b,
c
); // 5
output c;
input a, b;
wire x, y, x1, y1;
NotGate NG_1 (
a,
x
);
NotGate NG_2 (
b,
y
);
AndGate AG_1 (
a,
y,
x1
);
AndGate AG_2 (
b,
x,
y1
);
OrGate OG_1 (
x1,
y1,
c
);
endmodule
| 7.413558 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module XorGate (
a,
b,
c
); // 5
output c;
input a, b;
wire x, y, x1, y1;
NotGate NG_1 (
a,
x
);
NotGate NG_2 (
b,
y
);
AndGate AG_1 (
a,
y,
x1
);
AndGate AG_2 (
b,
x,
y1
);
OrGate OG_1 (
x1,
y1,
c
);
endmodule
| 7.413558 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module NotGate16 (
a,
b
); // 7
output [0:15] b;
input [0:15] a;
NotGate N_1[0:15] (
a,
b
);
endmodule
| 6.639123 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module AndGate16 (
a,
b,
c
); // 8
output [0:15] c;
input [0:15] a, b;
AndGate AG_1[0:15] (
a,
b,
c
);
endmodule
| 7.226935 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module SimOr16; // 9
wire [0:15] c;
reg [0:15] a, b;
OrGate16 OG16_Out (
a,
b,
c
);
initial begin
a = 100;
b = 100;
#100;
a = 200;
b = 100;
#100;
a = 235;
b = 62;
#100;
a = 3463;
b = 63547;
#100;
a = 348;
b = 2672;
#100;
a = 1953;
b = 1180;
#100;
a = 1512;
b = 138;
#100;
a = 12630;
b = 10;
#100;
end
endmodule
| 6.585492 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module XorGate (
a,
b,
c
); // 5
output c;
input a, b;
wire x, y, x1, y1;
NotGate NG_1 (
a,
x
);
NotGate NG_2 (
b,
y
);
AndGate AG_1 (
a,
y,
x1
);
AndGate AG_2 (
b,
x,
y1
);
OrGate OG_1 (
x1,
y1,
c
);
endmodule
| 7.413558 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
); // 12
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
); // 12
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
); // 12
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module Mux4x1 (
i0,
i1,
i2,
i3,
s1,
s0,
o
); // 15
output o;
input i0, i1, i2, i3;
input s1, s0;
wire x, y;
Mux2x1 M_1 (
i0,
i1,
s1,
x
);
Mux2x1 M_2 (
i2,
i3,
s1,
y
);
Mux2x1 M_3 (
x,
y,
s0,
o
);
endmodule
| 8.038083 |
module Mux4x1_16 (
i0,
i1,
i2,
i3,
s,
o
);
output [15:0] o;
input [15:0] i0, i1, i2, i3;
input [1:0] s;
Mux4x1 M[15:0] (
i0,
i1,
i2,
i3,
s[0],
s[1],
o
);
endmodule
| 7.425005 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
); // 12
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module Mux4x1 (
i0,
i1,
i2,
i3,
s1,
s0,
o
); // 15
output o;
input i0, i1, i2, i3;
input s1, s0;
wire x, y;
Mux2x1 M_1 (
i0,
i1,
s1,
x
);
Mux2x1 M_2 (
i2,
i3,
s1,
y
);
Mux2x1 M_3 (
x,
y,
s0,
o
);
endmodule
| 8.038083 |
module Mux4x1_16 (
i0,
i1,
i2,
i3,
s,
o
);
output [15:0] o;
input [15:0] i0, i1, i2, i3;
input [1:0] s;
Mux4x1 M[15:0] (
i0,
i1,
i2,
i3,
s[0],
s[1],
o
);
endmodule
| 7.425005 |
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