code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module aibnd_hgy_latch (
input wire set,
input wire preset,
input wire clk,
input wire d,
output reg q
);
always @(*) begin
if (set && !preset) begin
q <= 0;
end else if (!set && preset) begin
q <= 1;
end else begin
if (clk) q <= d;
end
end
endmodule
| 6.529145 |
module aibnd_inv_split_align (
din,
dout,
vccl,
vssl
);
input din;
output dout;
input vssl;
input vccl;
assign dout = ~din;
endmodule
| 7.232955 |
module aibnd_io_nand_delay_line_min_rep (
input nfrzdrv,
input in_p,
input in_n,
output out_p,
output out_n
);
`ifdef TIMESCALE_EN
timeunit 1ps; timeprecision 1ps;
`endif
parameter NAND_DELAY = 20;
wire fout_p;
wire fout_n;
wire osc_out_p;
wire osc_out_n;
//---------------------... | 6.708165 |
module aibnd_latch (
input wire clk,
input wire rb,
//input wire vcc,
//input wire vss,
input wire d,
output reg o
);
always @(*) begin
if (!rb) begin
o <= 0;
end else begin
if (clk) o <= d;
end
end
endmodule
| 8.451951 |
module aibnd_quadph_code_gen #(
parameter FF_DELAY = 200
) (
input wire clk, //reference clock from pll
input wire reset_n, //output for dll reset
input wire [9:0] pvt_ref_binary, //output binary pvt value for delay chain
input wire rb_quad_code... | 6.63384 |
module aibnd_redundancy ( //input of input mux
pd_data_in1,
pd_data_in0,
iclkin_dist_in1,
iclkin_dist_in0,
idata0_in1,
idata0_in0,
idata1_in1,
idata1_in0,
idataselb_in1,
idataselb_in0,
iddren_in1,
iddren_in0,
ilaunch_clk_in1,
ilaunch_clk_in0,
ilpbk_dat_in1,
... | 6.639647 |
module aibnd_rxdat_mimic (
input wire vccl_aibnd,
input wire vssl_aibnd,
input wire odat_in,
output wire odat_out
);
assign odat_out = odat_in;
endmodule
| 7.350924 |
module aibnd_str_ioload (
inp
);
input inp;
// Buses in the design
wire net07;
assign vcc_aibnd = 1'b1;
assign vss_aibnd = 1'b0;
//specify
// specparam CDS_LIBNAME = "aibnd_lib";
// specparam CDS_CELLNAME = "aibnd_str_ioload";
// specparam CDS_VIEWNAME = "schematic";
//endspecif... | 6.546486 |
module aibnd_txdat_mimic (
input wire vccl_aibnd,
input wire vssl_aibnd,
input wire idata_in,
output wire idata_out
);
assign idata_out = idata_in;
endmodule
| 7.633605 |
module aib_adapter_rxchnl (
// Outputs
output wire [319:0] rx_adapt_dout, // FIFO mode data output
output wire [ 79:0] data_out, // Register mode data output
output wire align_done, // Word Mark alignment done
// Inputs
input atpg_mode, ... | 7.294102 |
module aib_adapter_txchnl (
// Outputs
output wire [ 79:0] dout, // AIB Data output
// Inputs
input atpg_mode, // Scan enable
input txwr_fifo_rstn, // Tx write fifo reset
input txrd_rstn, // Tx read reset
... | 6.903967 |
module aib_adaptrxdbi_rxdp (
input wire rst_n,
input wire clk,
input wire [79:0] data_in,
input wire dbi_en,
output wire [79:0] data_out
);
wire [3:0] dbi_calc;
reg [79:0] last_din, dbi_data_out;
wire [37:0] dbi_dat_lo, dbi_dat_hi;
assign data_out = dbi_en ? dbi_data... | 6.775732 |
module aib_adaptrxdp_fifo_ram #(
parameter DWIDTH = 'd80, // FIFO Input data width
parameter DEPTH = 'd16 // FIFO Depth
) (
input wire wr_clk, // Write Domain Clock
input wire wr_rst_n, // Write Domain Reset
input wire wr_en, // Write Da... | 7.696758 |
module aib_adaptrxdp_map (
input wire [39:0] din,
input wire [79:0] rx_fifo_data_out, // Data from rx fifo
input wire rx_aib_transfer_clk,
input wire rx_aib_transfer_rst_n,
input wire rx_clock_fifo_rd_clk,
input wire rx_reset_fifo_rd_rst_n,
output reg [79:0] r_fifo_dout,
output reg [3... | 7.696758 |
module aib_adaptrxdp_word_align #(
parameter DWIDTH = 'd40 // FIFO Input data width
) (
input wire wr_clk, // clock
input wire wr_rst_n, // async reset
input wire r_wa_en, // Word-align enable
input wire [DWIDTH-1:... | 7.696758 |
module aib_adapttxdp_fifo_ram #(
parameter DWIDTH = 'd80, // FIFO Input data width
parameter DEPTH = 'd16 // FIFO Depth
) (
input wire wr_clk, // Write Domain Clock
input wire wr_en, // write enable
input wire wr_rst_n, // Write Domain Re... | 6.661394 |
module aib_adapttxdp_reg (
input wire tx_clock_fifo_rd_clk,
input wire tx_reset_fifo_rd_rst_n,
input wire [ 1:0] r_tx_fifo_mode,
input wire [39:0] data_in,
output reg [39:0] reg_dout
);
always @(posedge tx_clock_fifo_rd_clk or negedge tx_reset_fifo_rd_rst_n) begin
if (!tx_reset... | 6.661394 |
module aib_adapt_cmn_pulse_stretch #(
parameter RESET_VAL = 'd0 // reset value
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire [2:0] num_stages, // number of stages required
input wire data_in, // data in
output reg data_o... | 9.632342 |
module aib_adapt_rxchnl (
// Outputs
output wire [319:0] data_out_f,
output wire [ 79:0] data_out,
output wire align_done,
// Inputs
input wire atpg_mode,
input wire m_gen2_mode,
input wire adapt_rstn,
input wire rx_fifo_rstn,
input w... | 6.781638 |
module aib_aliasd (
sig_in,
sig_red
);
output sig_red;
input sig_in;
assign sig_red = sig_in;
endmodule
| 6.869345 |
module aib_aux_channel (
// AIB IO Bidirectional
inout wire iopad_dev_dect,
inout wire iopad_dev_dectrdcy,
inout wire iopad_dev_por,
inout wire iopad_dev_porrdcy,
input m_por_ovrd, //Master onlhy input, it overrides the por signal. For slave, it is tied to "0"
input ... | 8.407922 |
module aib_avmm_adapt_csr (
output reg [31:0] rx_0,
output reg [31:0] rx_1,
output reg [31:0] tx_0,
output reg [31:0] tx_1,
//Bus Interface
input clk,
input reset,
input [31:0] writedata,
input read,
input write,
input [3:0] byteenable,
output reg [31:0] readdata,
o... | 7.949418 |
module aib_avmm_io_csr (
output reg [31:0] redund_0,
output reg [31:0] redund_1,
output reg [31:0] redund_2,
output reg [31:0] redund_3,
//Bus Interface
input clk,
input reset,
input [31:0] writedata,
input read,
input write,
input [3:0] byteenable,
output reg [31:0] re... | 7.249838 |
module aib_bitsync #(
parameter DWIDTH = 1'b1, // Sync Data input
parameter RESET_VAL = 1'b0 // Reset value
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire [DWIDTH-1:0] data_in, // data in
output wire [DWIDTH-1:0] data_out // data... | 7.300936 |
module aib_bit_sync #(
parameter DWIDTH = 1'b1, // Sync Data input
parameter [DWIDTH-1:0] RESET_VAL = {DWIDTH{1'b0}} // Reset value
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire [DWIDTH-1:0] data_in, // data in
output wire [DWIDT... | 6.995603 |
module aib_bscan (
input odat_asyn_aib, //async data RX from AIB
input async_data_adap, //async data TX from HSSI Adapter
input tx_async_en_adap, // TX asynchronous enable from Adapter
input jtag_tx_scanen_in, //JTAG shift DR, active high
input tx_jtag_clk_g, // Gated clock for TX s... | 7.51874 |
module aib_bs_clk_gating (
// Inputs
input jtag_clk, // JTAG clock
input jtag_capture_dr, // Capture data register
input jtag_tx_scanen_in, // JTAG TX scan enable
input i_scan_mode, // Scan mode
// Outputs
output tx_jtag_clk_g, // JATG clock gated for transmit s... | 7.319835 |
module aib_bus_sync #(
parameter DWIDTH = 1'b1, // Data bus width
parameter [DWIDTH-1:0] RESET_VAL = {DWIDTH{1'h0}} // Reset value
) (
// Inputs
input src_clk, // source clock
input dest_clk, // destination clock
input ... | 8.70459 |
module aib_cdc_data_mux #(
parameter DWIDTH = 'd80 // Data bus width
) (
// Inputs
input [DWIDTH-1:0] dmux_in0, // Data input for dmux_sel = 1
input [DWIDTH-1:0] dmux_in1, // Data input for dmux_sel = 0
input dmux_sel, // Data selection
// Outputs
output [DWIDTH-1:0] dmux... | 9.05786 |
module aib_dcc (
// AIB IO Bidirectional
input clk_in,
input ms_dcc_cal_req,
input ms_tx_dcc_dll_lock_req,
input sl_dcc_cal_req,
input sl_rx_dcc_dll_lock_req,
output wire ms_dcc_cal_done,
output wire sl_dcc_cal_done,
output wire clk_out,
input ... | 7.294203 |
module aib_dll_ctrl_logic (
input [2:0] freq_range_sel,
output reg [2:0] trim_ctrl_bits
);
always @(*) begin
case (freq_range_sel)
3'b000: trim_ctrl_bits = 3'b100;
3'b001: trim_ctrl_bits = 3'b101;
3'b010: trim_ctrl_bits = 3'b110;
3'b011: trim_ctrl_bits = 3'b111;
3'b100:... | 8.733237 |
module aib_fifo_and_sel #(
parameter DWIDTH = 80
) (
output [DWIDTH-1:0] fifo_out_sel, // FIFO output ANDed with read enable
input fifo_rd_en, // FIFO read enable
input [DWIDTH-1:0] fifo_rd_in // FIFO data in write domain
);
// AND logic selects the asynchronous bus only when d... | 8.309568 |
module aib_fifo_rdata_buf #(
parameter DWIDTH = 80 // FIFO Input data width
) (
// Output
output reg [DWIDTH-1:0] fifo_rdata_ff,
// Input
input [DWIDTH-1:0] fifo_rdata,
input rd_clk,
input rd_rst_n
);
always @(posedge rd_clk or negedge rd_rst_n) ... | 7.18425 |
module aib_mux21 (
input wire mux_in0, // mux in 0
input wire mux_in1, // mux in 1
input wire mux_sel, // mux selector
output wire mux_out // mux out
);
assign mux_out = mux_sel ? mux_in1 : mux_in0;
endmodule
| 8.141275 |
module aib_redundancy ( //input of input mux
idata0_in1,
idata0_in0,
idata1_in1,
idata1_in0,
idataselb_in1,
idataselb_in0,
iddren_in1,
iddren_in0,
irxen_in1,
irxen_in0,
itxen_in1,
itxen_in0,
async_dat_in1,
async_dat_in0,
//Output of input mux
idata0_out,
... | 7.263786 |
module aib_rstnsync (
input wire clk, // Destination clock of reset to be synced
input wire i_rst_n, // Asynchronous reset input
input wire scan_mode, // Scan bypass for reset
output wire sync_rst_n // Synchronized reset output
);
reg first_stg_rst_n;
wire prescan_sync_rst_n;
al... | 8.66439 |
module aib_rst_sync (
input clk, // Destination clock of reset to be synced
input i_rst_n, // Asynchronous reset input
input scan_mode, // Scan bypass for reset
output sync_rst_n // Synchronized reset output
);
wire prescan_sync_rst_n;
aib_bit_sync #(
.DWIDTH(1),
.RESET... | 8.44053 |
module aib_rx_dbi (
// Inputs
input wire rst_n, // Asynchronous reset
input wire clk, // Clock
input wire [79:0] data_in, // Data input before DBI logic
input wire dbi_en, // Data inversion enable
// Outputs
output wire [79:0] data_out // Output data afte... | 6.758807 |
module AICPU (
input acr_clk,
input acr_rst,
output [31:0] axi_awaddr,
output [3:0] axi_awlen,
output [2:0] axi_awsize,
output [1:0] axi_awburst,
output axi_awlock,
output [3:0] axi_awcache,
output [2:0] axi_awprot,
output axi_awvalid,
input axi_awready,
output [63:0] axi... | 7.320631 |
module AIDMA (
input acr_clk,
input acr_rst,
output [31:0] axi_awaddr,
output [3:0] axi_awlen,
output [2:0] axi_awsize,
output [1:0] axi_awburst,
output axi_awlock,
output [3:0] axi_awcache,
output [2:0] axi_awprot,
output axi_awvalid,
input axi_awready,
output [63:0] axi... | 6.577363 |
module ainv_checker
#(parameter `BSG_INV_PARAM(data_width_p))
(
input clk_i
, input reset_i
, input en_i
, input [data_width_p-1:0] data_o
, input v_o
, input yumi_i
);
// ainv test is setup in such way that it should only return zero.
always_ff @ (posedge clk_i) begin
if... | 6.965132 |
module AISO (
clk,
reset,
reset_s
);
input clk, reset;
output reset_s;
reg temp_res1, temp_res2;
always @(posedge clk or posedge reset) begin
if (reset) temp_res1 <= 1'b0;
else temp_res1 <= 1'b1;
end
always @(posedge clk or posedge reset) begin
if (reset) temp_res2 <= 1'b0;
el... | 6.553451 |
module models a circuit which takes an asynchronous input,
in this case coming from the reset button, and outputs a
synchronous signal. This is achieved through the use of
a synchronous flop called 'delay_reg'. Synchronous resets will
only reset the s... | 6.591859 |
module AISRAM (
input acr_clk,
input acr_rst,
input [31:0] axi_awaddr,
input [3:0] axi_awlen,
input [2:0] axi_awsize,
input [1:0] axi_awburst,
input axi_awlock,
input [3:0] axi_awcache,
input [2:0] axi_awprot,
input axi_awvalid,
output axi_awready,
input [63:0] axi_wdata,... | 7.06409 |
module Axis_Ctrl_18BitWidth (
Clk,
gRst,
Addr,
MCUportL,
WR,
CS,
Din,
PosLock,
Ref,
Protect,
MO,
nStanby,
DRVRst,
PlsOut,
Dir,
Torque1,
Torque2,
DQtoMCU
);
/*
Axis_Ctrl Axis_Ctrl(
.Clk(),
.gRst(),
.Addr(),
.MCUportL(),
.WR(... | 6.753627 |
module ai_accel (
rst_n, // Reset Neg
clk, // Clk
addr, // Address
wr_en, //Write enable
accel_select,
data_in,
data_out, // Output Data
a_mem,
b_mem,
c_mem,
a_show,
b_show,
c_show
);
localparam N = 8;
localparam BITS = 8;
localparam a_offcet = 10'd128;
... | 6.737985 |
module adder (
a,
b,
c,
d
);
input [31:0] a;
input [31:0] b;
input [31:0] c;
output [31:0] d;
wire [15:0] e;
assign e = a[31:24] + b[31:24] + c[31:24]
+ a[23:16] + b[23:16] + c[23:16]
+ a[15:8] + b[15:8] + c[15:8];
assign d = e > 8'hff ? 8'hff : e[7:0];
endmodule
| 7.4694 |
module AI_Engine (
clk,
pl,
en,
RST,
location_vectors_w,
location_vectors_b,
alive_vectors_w,
alive_vectors_b,
piece_to_move,
output_move,
done,
move_vec_P,
move_vec_R,
move_vec_N,
move_vec_B,
move_vec_Q,
move_vec_K,
pieceId,
ready,
end_mov... | 6.658475 |
module AI_Engine (
clk,
pl,
en,
RST,
location_vectors_w,
location_vectors_b,
alive_vectors_w,
alive_vectors_b,
piece_to_move,
output_move,
done,
move_vec_P,
move_vec_R,
move_vec_N,
move_vec_B,
move_vec_Q,
move_vec_K,
pieceId,
ready,
end_mov... | 6.658475 |
module ai_top (
clk,
rst,
wr,
addr_i,
addr_o,
i
);
// parameters
parameter WIDTH = 32;
parameter N_IN = 2;
parameter N_OUT = 2;
parameter N_HL = 1;
parameter N_HL_P = 3;
// common ports
input clk, rst;
// control ports
input wr;
input [7:0] addr_i;
input [7:0] addr_o;
... | 8.245377 |
module ai_top_tb ();
// parameters
parameter WIDTH = 32;
// registers
reg clk;
reg rst;
reg wr;
reg [7:0] addr_i;
reg [7:0] addr_o;
reg [63:0] i;
ai_top #(
.WIDTH (WIDTH),
.N_IN (2),
.N_OUT (2),
.N_HL (1),
.N_HL_P(3)
) inst_ai_top (
.clk (clk),
.rst... | 6.601401 |
module AJ (
clock,
angle,
Xin,
Yin,
Xout,
Yout,
Zout
);
//Declaracao do clock
input clock;
//Declaracao das variaveis de entrada
input [15:0] angle, Xin, Yin;
//Declaracao das variaveis de saida
output [15:0] Xout;
output [15:0] Yout;
output [15:0] Zout;
//Declaracao da... | 7.039364 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module StimOr; // 3
wire c;
reg a, b;
OrGate OG_Out (
a,
b,
c
);
initial begin
a = 1'b0;
b = 1'b0;
#100 a = 1'b1;
b = 1'b0;
#100 a = 1'b0;
b = 1'b1;
#100 a = 1'b1;
b = 1'b1;
#100;
end
endmodule
| 6.667907 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module XorGate (
a,
b,
c
); // 5
output c;
input a, b;
wire x, y, x1, y1;
NotGate NG_1 (
a,
x
);
NotGate NG_2 (
b,
y
);
AndGate AG_1 (
a,
y,
x1
);
AndGate AG_2 (
b,
x,
y1
);
OrGate OG_1 (
x1,
y1,
c
);
... | 7.413558 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module XorGate (
a,
b,
c
); // 5
output c;
input a, b;
wire x, y, x1, y1;
NotGate NG_1 (
a,
x
);
NotGate NG_2 (
b,
y
);
AndGate AG_1 (
a,
y,
x1
);
AndGate AG_2 (
b,
x,
y1
);
OrGate OG_1 (
x1,
y1,
c
);
... | 7.413558 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module NotGate16 (
a,
b
); // 7
output [0:15] b;
input [0:15] a;
NotGate N_1[0:15] (
a,
b
);
endmodule
| 6.639123 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module AndGate16 (
a,
b,
c
); // 8
output [0:15] c;
input [0:15] a, b;
AndGate AG_1[0:15] (
a,
b,
c
);
endmodule
| 7.226935 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module SimOr16; // 9
wire [0:15] c;
reg [0:15] a, b;
OrGate16 OG16_Out (
a,
b,
c
);
initial begin
a = 100;
b = 100;
#100;
a = 200;
b = 100;
#100;
a = 235;
b = 62;
#100;
a = 3463;
b = 63547;
#100;
a = 348;
b = 2672;
#100;
a =... | 6.585492 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module XorGate (
a,
b,
c
); // 5
output c;
input a, b;
wire x, y, x1, y1;
NotGate NG_1 (
a,
x
);
NotGate NG_2 (
b,
y
);
AndGate AG_1 (
a,
y,
x1
);
AndGate AG_2 (
b,
x,
y1
);
OrGate OG_1 (
x1,
y1,
c
);
... | 7.413558 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
); // 12
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
); // 12
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
); // 12
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module Mux4x1 (
i0,
i1,
i2,
i3,
s1,
s0,
o
); // 15
output o;
input i0, i1, i2, i3;
input s1, s0;
wire x, y;
Mux2x1 M_1 (
i0,
i1,
s1,
x
);
Mux2x1 M_2 (
i2,
i3,
s1,
y
);
Mux2x1 M_3 (
x,
y,
s0,
o
);
... | 8.038083 |
module Mux4x1_16 (
i0,
i1,
i2,
i3,
s,
o
);
output [15:0] o;
input [15:0] i0, i1, i2, i3;
input [1:0] s;
Mux4x1 M[15:0] (
i0,
i1,
i2,
i3,
s[0],
s[1],
o
);
endmodule
| 7.425005 |
module NotGate (
a,
b
); // 1
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
); // 2
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
); // 3
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module Mux2x1 (
a,
b,
s,
c
); // 12
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module Mux4x1 (
i0,
i1,
i2,
i3,
s1,
s0,
o
); // 15
output o;
input i0, i1, i2, i3;
input s1, s0;
wire x, y;
Mux2x1 M_1 (
i0,
i1,
s1,
x
);
Mux2x1 M_2 (
i2,
i3,
s1,
y
);
Mux2x1 M_3 (
x,
y,
s0,
o
);
... | 8.038083 |
module Mux4x1_16 (
i0,
i1,
i2,
i3,
s,
o
);
output [15:0] o;
input [15:0] i0, i1, i2, i3;
input [1:0] s;
Mux4x1 M[15:0] (
i0,
i1,
i2,
i3,
s[0],
s[1],
o
);
endmodule
| 7.425005 |
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