code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ahb_adapter (
/*autoport*/
//output
rddata,
stall,
AHB_haddr,
AHB_hburst,
AHB_hprot,
AHB_hready_in,
AHB_hsize,
AHB_htrans,
AHB_hwdata,
AHB_hwrite,
AHB_sel,
triple_byte_w,
//input
clk,
rst_n,
dataenable,
rd,
wr,
address,
wrdata,
AHB_hrdata,
AHB_hready_out,
AHB_hresp
);
input wire clk; // Clock
input wire rst_n; // Asynchronous reset active low
input wire [3:0] dataenable;
input wire rd;
input wire wr;
input wire [31:0] address;
input wire [31:0] wrdata;
output wire [31:0] rddata;
output wire stall;
wire issue = wr | rd;
input wire [31:0] AHB_hrdata;
input wire AHB_hready_out;
input wire AHB_hresp;
output wire [31:0] AHB_haddr;
output wire [2:0] AHB_hburst;
output wire [3:0] AHB_hprot;
output wire AHB_hready_in;
output reg [2:0] AHB_hsize;
output wire [1:0] AHB_htrans;
output reg [31:0] AHB_hwdata;
output wire AHB_hwrite;
output wire AHB_sel;
output reg triple_byte_w;
reg first_cycle;
assign AHB_haddr = address;
assign AHB_hburst = 3'b000;
assign AHB_hprot = 4'b0011;
assign AHB_hready_in = AHB_hready_out;
assign AHB_htrans = (first_cycle & issue) ? 2'b10 : 2'b00;
assign AHB_hwrite = wr;
assign AHB_sel = issue;
assign rddata = AHB_hrdata;
always @(*) begin
case (dataenable)
4'b1000, 4'b0100, 4'b0010, 4'b0001: begin
AHB_hsize = 3'b0;
end
4'b0011, 4'b1100: begin
AHB_hsize = 3'b1;
end
default: begin
AHB_hsize = 3'b10;
end
endcase
end
always @(posedge clk or negedge rst_n) begin : proc_bridge
if (~rst_n) begin
first_cycle <= 1'b1;
end else begin
if (issue & first_cycle) begin
first_cycle <= 0;
AHB_hwdata <= wrdata;
end
if (~stall) begin
first_cycle <= 1;
end
end
end
assign stall = issue & (first_cycle | ~AHB_hready_out);
always @(posedge clk or negedge rst_n) begin : proc_triple_byte_w
if (~rst_n) begin
triple_byte_w <= 1'b0;
end else if ((dataenable == 4'b1110 || dataenable == 4'b0111) && wr) begin
triple_byte_w <= 1'b1;
end
end
endmodule
| 8.262102 |
module ahb_addr_decode (
// System Address
input wire [31:0] haddr,
// Memory Selection
output wire ram_hsel,
// PIO Selection
output wire pio_hsel,
// Peripheral Selection
output wire apbsys_hsel
);
assign ram_hsel = (haddr[31:16]==16'h1000); // 0x10000000
assign pio_hsel = (haddr[31:16]==16'h2000); // 0x20000000
assign apbsys_hsel = (haddr[31:16]==16'h3000); // 0x30000000
endmodule
| 6.706724 |
module AHB_APB_BRIDGE #(
parameter SLOW_PCLK = 1
) (
input wire HCLK,
input wire HRESETn,
// AHB Slave Port
`AHB_SLAVE_IFC,
// APB Master Port
output wire PCLK,
output wire PRESETn,
input wire PCLKEN,
`APB_MASTER_IFC
);
localparam ST_IDLE = 3'h0, ST_WAIT = 3'h1, ST_SETUP = 3'h2, ST_ACCESS = 3'h3;
reg PENABLE;
reg [31:0] PADDR;
reg PWRITE;
wire Transfer;
wire ACRegEn;
wire [31:0] HADDR_Mux;
reg [ 2:0] state;
reg [ 2:0] nstate;
reg HREADY_next;
wire PWRITE_next;
wire PENABLE_next;
wire APBEn;
generate
if (SLOW_PCLK) assign PCLK = PCLKEN;
else assign PCLK = HCLK;
endgenerate
assign PRESETn = HRESETn;
assign Transfer = HSEL & HREADY & HTRANS[1];
assign ACRegEn = HSEL & HREADY;
`AHB_SLAVE_EPILOGUE
// State Machine
always @*
case (state)
ST_IDLE:
if (Transfer & PCLKEN) nstate = ST_SETUP;
else if (Transfer) nstate = ST_WAIT;
else nstate = ST_IDLE;
ST_WAIT:
if (PCLKEN) nstate = ST_SETUP;
else nstate = ST_WAIT;
ST_SETUP:
if (PCLKEN) nstate = ST_ACCESS;
else nstate = ST_SETUP;
ST_ACCESS:
if (!PREADY) nstate = ST_ACCESS;
else begin
if (Transfer & PCLKEN) nstate = ST_SETUP;
else if (Transfer) nstate = ST_WAIT;
else nstate = ST_IDLE;
end
default: nstate = ST_IDLE;
endcase
always @(posedge HCLK, negedge HRESETn)
if (!HRESETn) state <= ST_IDLE;
else state <= nstate;
//HREADYOUT
reg hreadyout;
always @*
case (nstate)
ST_IDLE: HREADY_next = 1'b1;
ST_WAIT: HREADY_next = 1'b0;
ST_SETUP: HREADY_next = 1'b0;
ST_ACCESS: HREADY_next = PREADY;
default: HREADY_next = 1'b1;
endcase
always @(posedge HCLK, negedge HRESETn)
if (!HRESETn) hreadyout <= 1'b1;
else hreadyout <= HREADY_next;
assign HREADYOUT = hreadyout;
//APBen
assign APBEn = (state == ST_IDLE) && (nstate == ST_SETUP) || (nstate == ST_WAIT);
// HADDRMux
assign HADDR_Mux = (APBEn ? HADDR : last_HADDR);
//PADDR
always @(posedge HCLK, negedge HRESETn)
if (!HRESETn) PADDR <= 'h0;
else if (APBEn) PADDR <= HADDR_Mux;
//PWDATA
assign PWDATA = HWDATA;
//PENABLE
assign PENABLE_next = (nstate == ST_ACCESS);
always @(posedge HCLK, negedge HRESETn)
if (!HRESETn) PENABLE <= 1'b0;
else PENABLE <= PENABLE_next;
//PWRITE
assign PWRITE_next = (APBEn ? HWRITE : last_HWRITE);
always @(posedge HCLK, negedge HRESETn)
if (!HRESETn) PWRITE <= 1'b0;
else if (APBEn) PWRITE <= PWRITE_next;
//HRDATA
assign HRDATA = PRDATA;
endmodule
| 8.45554 |
module AHB_ARB_RB #(
parameter MASTERS = 8,
MASTERS_BIT = $clog2(MASTERS)
) (
input wire [MASTERS-1:0] RB_REQ,
input wire [MASTERS_BIT-1:0] RB_POINTER,
output reg [MASTERS-1:0] RB_GRANT
);
//----------------
// Request Mask
//----------------
wire [MASTERS-1:0] rb_mask;
wire [MASTERS-1:0] rb_req_masked;
wire rb_req_masked_none;
//
assign rb_mask = {MASTERS{1'b1}} << RB_POINTER;
assign rb_req_masked = RB_REQ & rb_mask;
assign rb_req_masked_none = ~(|rb_req_masked);
//----------------------------------------
// Simple Prioiry for Unmasked rb_req
//----------------------------------------
reg [MASTERS-1:0] rb_grant_unmasked;
//
always @* begin
integer mst;
reg found;
found = 1'b0;
for (mst = 0; mst < MASTERS; mst = mst + 1) begin
rb_grant_unmasked[mst] = RB_REQ[mst] & (~found);
found = found | rb_grant_unmasked[mst];
end
end
//----------------------------------------
// Simple Prioiry for Masked rb_req_masked
//----------------------------------------
reg [MASTERS-1:0] rb_grant_masked;
//
always @* begin
integer mst;
reg found;
found = 1'b0;
for (mst = 0; mst < MASTERS; mst = mst + 1) begin
rb_grant_masked[mst] = rb_req_masked[mst] & (~found);
found = found | rb_grant_masked[mst];
end
end
//-----------------------
// Final Granted Signal
//-----------------------
always @* begin
integer mst;
for (mst = 0; mst < MASTERS; mst = mst + 1) begin
RB_GRANT[mst] = (rb_req_masked_none) ? rb_grant_unmasked[mst] : rb_grant_masked[mst];
end
end
//------------------------
// End of Module
//------------------------
endmodule
| 6.818939 |
module ahb_arbiter (
input wire HCLK,
input wire HRESETn,
//Master0
input wire HBUSREQ_M0,
input wire HLOCK_M0,
input wire [`AHB_ADDR_WIDTH - 1 : 0] HADDR_M0,
input wire [1:0] HTRANS_M0,
input wire HWRITE_M0,
input wire [`AHB_DATA_WIDTH - 1 : 0] HWDATA_M0,
output reg HGRANT_M0,
//Master1
input wire HBUSREQ_M1,
input wire HLOCK_M1,
input wire [`AHB_ADDR_WIDTH - 1 : 0] HADDR_M1,
input wire [1:0] HTRANS_M1,
input wire HWRITE_M1,
input wire [`AHB_DATA_WIDTH - 1 : 0] HWDATA_M1,
output reg HGRANT_M1,
//Master2
input wire HBUSREQ_M2,
input wire HLOCK_M2,
input wire [`AHB_ADDR_WIDTH - 1 : 0] HADDR_M2,
input wire [1:0] HTRANS_M2,
input wire HWRITE_M2,
input wire [`AHB_DATA_WIDTH - 1 : 0] HWDATA_M2,
output reg HGRANT_M2,
//to all slave (HADDR_S also needed by bus decoder)
output reg [`AHB_ADDR_WIDTH - 1 : 0] HADDR_S,
output reg [1:0] HTRANS_S,
output reg HWRITE_S,
output reg [`AHB_DATA_WIDTH - 1 : 0] HWDATA_S,
input wire HREADY_S
);
//Logic Start
//
//arbitration
//Priority : master0 > master1 > master2
wire [2:0] HMASTER_A;
reg [2:0] HMASTER_D;
wire [2:0] req;
reg idle;
assign req = {HBUSREQ_M2, HBUSREQ_M1, HBUSREQ_M0};
assign HMASTER_A = {HGRANT_M2, HGRANT_M1, HGRANT_M0};
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
HMASTER_D <= 3'b001;
end else begin
HMASTER_D <= HMASTER_A;
end
end
always @* begin
case (HMASTER_A)
3'b001: idle = (HTRANS_M0 == `IDLE); // && !HLOCK_M0;
3'b010: idle = (HTRANS_M1 == `IDLE); // && !HLOCK_M1;
3'b100: idle = (HTRANS_M2 == `IDLE); // && !HLOCK_M2;
default: idle = 1'b1;
endcase
end
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
HGRANT_M0 <= 1'b0;
HGRANT_M1 <= 1'b1;
HGRANT_M2 <= 1'b0;
end else begin
if (idle && HREADY_S) begin
casex (req)
3'b?01: begin
HGRANT_M0 <= 1'b1;
HGRANT_M1 <= 1'b0;
HGRANT_M2 <= 1'b0;
end
3'b?1?: begin
HGRANT_M0 <= 1'b0;
HGRANT_M1 <= 1'b1;
HGRANT_M2 <= 1'b0;
end
3'b100: begin
HGRANT_M0 <= 1'b0;
HGRANT_M1 <= 1'b0;
HGRANT_M2 <= 1'b1;
end
default: begin
HGRANT_M0 <= 1'b0;
HGRANT_M1 <= 1'b1;
HGRANT_M2 <= 1'b0;
end
endcase
end else begin
HGRANT_M0 <= HGRANT_M0;
HGRANT_M1 <= HGRANT_M1;
HGRANT_M2 <= HGRANT_M2;
end
end
end
always @* begin
case (HMASTER_A)
3'b001: begin
HADDR_S = HADDR_M0;
HTRANS_S = HTRANS_M0;
HWRITE_S = HWRITE_M0;
end
3'b010: begin
HADDR_S = HADDR_M1;
HTRANS_S = HTRANS_M1;
HWRITE_S = HWRITE_M1;
end
3'b100: begin
HADDR_S = HADDR_M2;
HTRANS_S = HTRANS_M2;
HWRITE_S = HWRITE_M2;
end
default: begin
HADDR_S = HADDR_M0;
HTRANS_S = HTRANS_M0;
HWRITE_S = HWRITE_M0;
end
endcase
end
always @* begin
case (HMASTER_D)
3'b001: begin
HWDATA_S = HWDATA_M0;
end
3'b010: begin
HWDATA_S = HWDATA_M1;
end
3'b100: begin
HWDATA_S = HWDATA_M2;
end
default: begin
HWDATA_S = HWDATA_M0;
end
endcase
end
endmodule
| 7.239759 |
module ahb_arbiter_m2 #(
parameter P_NUM = 2
) // the number of masters
(
input wire HRESETn
, input wire HCLK
, input wire HREADY
, input wire HBUSREQ_0
, input wire HBUSREQ_1
, output wire HGRANT_0
, output wire HGRANT_1
, output reg [3:0] HMASTER
);
//---------------------------------------------
wire [0:1] hbusreq = {HBUSREQ_0, HBUSREQ_1};
reg [0:1] hgrant;
assign {HGRANT_0, HGRANT_1} = hgrant;
//---------------------------------------------
always @(posedge HCLK or negedge HRESETn) begin
if (HRESETn == 1'b0) hgrant <= 4'h0;
else begin
if (HREADY == 1'b1) begin
casex ({
hbusreq, hgrant
})
// priority
4'b1x_00: hgrant <= 2'b10;
4'b01_00: hgrant <= 2'b01;
// stay
4'b1x_10: hgrant <= 2'b10;
4'bx1_01: hgrant <= 2'b01;
// last
4'b00_xx: hgrant <= 2'b00;
// last and handover
4'b01_10: hgrant <= 2'b01;
4'b00_10: hgrant <= 2'b00;
4'b10_01: hgrant <= 2'b10;
4'b00_01: hgrant <= 2'b00;
default: hgrant <= 2'b00;
endcase
end
end
end
always @(posedge HCLK or negedge HRESETn) begin
if (HRESETn == 1'b0) begin
HMASTER <= 4'hF;
end else begin
if (HREADY == 1'b1) begin
casex (hgrant)
2'b1x: HMASTER <= #1 4'h0;
2'b01: HMASTER <= #1 4'h1;
default: HMASTER <= #1 4'hF;
endcase
end
end
end
// synopsys translate_off
`ifdef RIGOR
wire [1:0] _hgrant = {HGRANT_0, HGRANT_1};
always @(posedge HCLK) begin
if ((_hgrant != 2'b01) && (_hgrant != 2'b10) && (_hgrant != 2'b00))
$display($time,, "%m ERROR: more than one has been granted! 0x%x", _hgrant);
end
`endif
// synopsys translate_on
endmodule
| 8.187108 |
module ahb_arbiter_m3 (
HRESETn,
HCLK,
HREADY,
HBUSREQ_0,
HBUSREQ_1,
HBUSREQ_2,
HGRANT_0,
HGRANT_1,
HGRANT_2,
HMASTER
);
parameter P_NUM = 3; // the number of masters
input HRESETn;
wire HRESETn;
input HCLK;
wire HCLK;
input HREADY;
wire HREADY;
input HBUSREQ_0;
wire HBUSREQ_0;
input HBUSREQ_1;
wire HBUSREQ_1;
input HBUSREQ_2;
wire HBUSREQ_2;
output HGRANT_0;
wire HGRANT_0;
output HGRANT_1;
wire HGRANT_1;
output HGRANT_2;
wire HGRANT_2;
output [3:0] HMASTER;
reg [3:0] HMASTER;
//---------------------------------------------
wire [0:2] hbusreq = {HBUSREQ_0, HBUSREQ_1, HBUSREQ_2};
reg [0:2] hgrant;
assign {HGRANT_0, HGRANT_1, HGRANT_2} = hgrant;
//---------------------------------------------
always @(posedge HCLK or negedge HRESETn) begin
if (HRESETn == 1'b0) hgrant <= 4'h0;
else begin
if (HREADY == 1'b1) begin // added by ADKI, 2008.12.08.
casex ({
hbusreq, hgrant
})
// priority
6'b1xx_000: hgrant <= 3'b100;
6'b01x_000: hgrant <= 3'b010;
6'b001_000: hgrant <= 3'b001;
// stay
6'b1xx_100: hgrant <= 3'b100;
6'bx1x_010: hgrant <= 3'b010;
6'bxx1_001: hgrant <= 3'b001;
// last
6'b000_xxx: hgrant <= 3'b000;
// last and handover
6'b01x_100: hgrant <= 3'b010;
6'b001_100: hgrant <= 3'b001;
6'b10x_010: hgrant <= 3'b100;
6'b001_010: hgrant <= 3'b001;
6'b1x0_001: hgrant <= 3'b100;
6'b010_001: hgrant <= 3'b010;
default : hgrant <= 3'b000;
endcase
end
end
end
always @(posedge HCLK or negedge HRESETn) begin
if (HRESETn == 1'b0) begin
HMASTER <= 4'hF;
end else begin
if (HREADY == 1'b1) begin
casex (hgrant)
3'b1xx: HMASTER <= #1 4'h0;
3'b01x: HMASTER <= #1 4'h1;
3'b001: HMASTER <= #1 4'h2;
default: HMASTER <= #1 4'hF;
endcase
end
end
end
// synopsys translate_off
`ifdef RIGOR
wire [2:0] _hgrant = {HGRANT_0, HGRANT_1, HGRANT_2};
always @(posedge HCLK) begin
if ((_hgrant != 3'b001) && (_hgrant != 3'b010) && (_hgrant != 3'b100) && (_hgrant != 3'b000))
$display($time,, "%m ERROR: more than one has been granted! 0x%x", _hgrant);
end
`endif
// synopsys translate_on
endmodule
| 8.187108 |
module ahb_async_sram #(
parameter W_DATA = 32,
parameter W_ADDR = 32,
parameter DEPTH = 1 << 11,
parameter W_SRAM_ADDR = $clog2(DEPTH) // Let this default
) (
// Globals
input wire clk,
input wire rst_n,
// AHB lite slave interface
output wire ahbls_hready_resp,
input wire ahbls_hready,
output wire ahbls_hresp,
input wire [W_ADDR-1:0] ahbls_haddr,
input wire ahbls_hwrite,
input wire [ 1:0] ahbls_htrans,
input wire [ 2:0] ahbls_hsize,
input wire [ 2:0] ahbls_hburst,
input wire [ 3:0] ahbls_hprot,
input wire ahbls_hmastlock,
input wire [W_DATA-1:0] ahbls_hwdata,
output wire [W_DATA-1:0] ahbls_hrdata,
output reg [W_SRAM_ADDR-1:0] sram_addr,
inout wire [ W_DATA-1:0] sram_dq,
output reg sram_ce_n,
output wire sram_we_n, // DDR output
output reg sram_oe_n,
output reg [ W_DATA/8-1:0] sram_byte_n
);
parameter W_BYTEADDR = $clog2(W_DATA / 8);
// Tie off unused AHBL signals
assign ahbls_hready_resp = 1'b1;
assign ahbls_hresp = 1'b0;
// Combinatorially generate the byte strobes from address + size buses
wire [W_DATA/8-1:0] bytemask_noshift = ~({W_DATA / 8{1'b1}} << (8'h1 << ahbls_hsize));
wire [W_DATA/8-1:0] bytemask = bytemask_noshift << ahbls_haddr[W_BYTEADDR-1:0];
// AHBL request marshalling/translation
wire we_next = ahbls_htrans[1] && ahbls_hwrite && ahbls_hready;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
sram_addr <= {W_SRAM_ADDR{1'b0}};
sram_ce_n <= 1'b1;
sram_oe_n <= 1'b1;
sram_byte_n <= {W_DATA / 8{1'b1}};
end else if (ahbls_hready) begin
if (ahbls_htrans[1]) begin
sram_addr <= ahbls_haddr[W_BYTEADDR+:W_SRAM_ADDR];
sram_ce_n <= 1'b0;
sram_oe_n <= ahbls_hwrite;
sram_byte_n <= ~bytemask;
end else begin
sram_ce_n <= 1'b1;
sram_oe_n <= 1'b1;
sram_byte_n <= {W_DATA / 8{1'b1}};
end
end
end
ddr_out we_ddr (
.clk (clk),
.rst_n (rst_n),
.d_rise(1'b1),
.d_fall(!we_next),
.q (sram_we_n)
);
// SRAM tristating
wire [W_DATA-1:0] sram_q;
assign ahbls_hrdata = sram_q & {W_DATA{!sram_oe_n}};
tristate_io iobuf[W_DATA-1:0] (
.out(ahbls_hwdata),
.oe (sram_oe_n),
.in (sram_q),
.pad(sram_dq)
);
endmodule
| 8.946783 |
module ahb_async_sram_halfwidth #(
parameter W_DATA = 32,
parameter W_ADDR = 32,
parameter DEPTH = 1 << 11,
parameter W_SRAM_ADDR = $clog2(DEPTH), // Let this default
parameter W_SRAM_DATA = W_DATA / 2 // Let this default
) (
// Globals
input wire clk,
input wire rst_n,
// AHB lite slave interface
output wire ahbls_hready_resp,
input wire ahbls_hready,
output wire ahbls_hresp,
input wire [W_ADDR-1:0] ahbls_haddr,
input wire ahbls_hwrite,
input wire [ 1:0] ahbls_htrans,
input wire [ 2:0] ahbls_hsize,
input wire [ 2:0] ahbls_hburst,
input wire [ 3:0] ahbls_hprot,
input wire ahbls_hmastlock,
input wire [W_DATA-1:0] ahbls_hwdata,
output wire [W_DATA-1:0] ahbls_hrdata,
output wire [ W_SRAM_ADDR-1:0] sram_addr,
output wire [ W_SRAM_DATA-1:0] sram_dq_out,
output wire [ W_SRAM_DATA-1:0] sram_dq_oe,
input wire [ W_SRAM_DATA-1:0] sram_dq_in,
output wire sram_ce_n,
output wire sram_we_n, // DDR output
output wire sram_oe_n,
output wire [W_SRAM_DATA/8-1:0] sram_byte_n
);
parameter W_BYTEADDR = $clog2(W_SRAM_DATA / 8);
assign ahbls_hresp = 1'b0;
reg hready_r;
reg long_dphase;
reg write_dph;
reg read_dph;
reg addr_lsb;
// AHBL decode and muxing
wire [W_SRAM_DATA/8-1:0] bytemask_noshift = ~({W_SRAM_DATA / 8{1'b1}} << (8'h1 << ahbls_hsize));
wire [W_SRAM_DATA/8-1:0] bytemask_aph = bytemask_noshift << ahbls_haddr[W_BYTEADDR-1:0];
wire aphase_full_width = (8'h1 << ahbls_hsize) == W_DATA / 8; // indicates next dphase will be long
wire [W_SRAM_DATA-1:0] sram_rdata;
wire [W_SRAM_DATA-1:0] sram_wdata = ahbls_hwdata[(addr_lsb?W_SRAM_DATA : 0)+:W_SRAM_DATA];
reg [W_SRAM_DATA-1:0] rdata_buf;
assign ahbls_hrdata = {sram_rdata, long_dphase ? rdata_buf : sram_rdata};
assign ahbls_hready_resp = hready_r;
// AHBL state machine
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
hready_r <= 1'b1;
long_dphase <= 1'b0;
write_dph <= 1'b0;
read_dph <= 1'b0;
addr_lsb <= 1'b0;
end else if (ahbls_hready) begin
if (ahbls_htrans[1]) begin
long_dphase <= aphase_full_width;
hready_r <= !aphase_full_width;
write_dph <= ahbls_hwrite;
read_dph <= !ahbls_hwrite;
addr_lsb <= ahbls_haddr[W_BYTEADDR];
end else begin
write_dph <= 1'b0;
long_dphase <= 1'b0;
read_dph <= 1'b0;
hready_r <= 1'b1;
end
end else if (long_dphase && !hready_r) begin
rdata_buf <= sram_rdata;
hready_r <= 1'b1;
addr_lsb <= 1'b1;
end
end
// SRAM PHY hookup
wire ce_aph = ahbls_htrans[1] && ahbls_hready;
wire ce_dph = long_dphase && !hready_r;
reg [W_SRAM_ADDR-1:0] addr_dph;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
addr_dph <= {W_SRAM_ADDR{1'b0}};
end else if (ahbls_hready) begin
addr_dph <= ahbls_haddr[W_BYTEADDR+:W_SRAM_ADDR] | {{W_SRAM_ADDR - 1{1'b0}}, 1'b1};
end
end
assign sram_ce_n = !(ce_aph || ce_dph);
assign sram_we_n = !((ce_aph && ahbls_hwrite) || (ce_dph && write_dph));
assign sram_oe_n = !((ce_aph && !ahbls_hwrite) || (ce_dph && !write_dph));
assign sram_addr = ce_dph ? addr_dph : ahbls_haddr[W_BYTEADDR+:W_SRAM_ADDR];
assign sram_byte_n = ~(bytemask_aph |{W_SRAM_DATA / 8{ce_dph}});
assign sram_rdata = sram_dq_in;
assign sram_dq_out = sram_wdata;
`ifdef FPGA_ICE40
// Output registers are built into pad (relies on the negedge trick for DQ wdata)
assign sram_dq_oe = {W_SRAM_DATA{!sram_we_n}};
`else
// No output registers on DQ
assign sram_dq_oe = {W_SRAM_DATA{write_dph}};
`endif
endmodule
| 8.946783 |
module ahb_bus_decoder (
input wire [`WORD_WIDTH - 1 : 0] HADDR,
output wire HSEL_1, // clint
output wire HSEL_2, // plic
output wire HSEL_3, // uart0
output wire HSEL_4 // spi0
);
assign HSEL_1 = (HADDR[`WORD_WIDTH - 1 : `WORD_WIDTH - `BUS_ADDR_HIGH_CLINT_WIDTH] == `BUS_ADDR_HIGH_CLINT )? 1'b1 : 1'b0;
assign HSEL_2 = (HADDR[`WORD_WIDTH - 1 : `WORD_WIDTH - `BUS_ADDR_HIGH_PLIC_WIDTH] == `BUS_ADDR_HIGH_PLIC )? 1'b1 : 1'b0;
assign HSEL_3 = (HADDR[`WORD_WIDTH - 1 : `WORD_WIDTH - `BUS_ADDR_HIGH_UART0_WIDTH] == `BUS_ADDR_HIGH_UART0 )? 1'b1 : 1'b0;
assign HSEL_4 = (HADDR[`WORD_WIDTH - 1 : `WORD_WIDTH - `BUS_ADDR_HIGH_SPI0_WIDTH] == `BUS_ADDR_HIGH_SPI0 )? 1'b1 : 1'b0;
endmodule
| 7.058028 |
module ahb_bus_matrix
(
// X signals from masters
// We support 3 master and 1 dummy master
input HBUSREQx0;
input HBUSREQx1;
input HBUSREQx2;
input HBUSREQx3;
input HLOCKx0;
input HLOCKx1;
input HLOCKx2;
input HLOCKx3;
input [1:0] HTRANSx0;
input [1:0] HTRANSx1;
input [1:0] HTRANSx2;
input [1:0] HTRANSx3;
input [31:0] HADDRx0;
input [31:0] HADDRx1;
input [31:0] HADDRx2;
input [31:0] HADDRx3;
input HWRITEx0;
input HWRITEx1;
input HWRITEx2;
input HWRITEx3;
input [2:0] HSIZEx0;
input [2:0] HSIZEx1;
input [2:0] HSIZEx2;
input [2:0] HSIZEx3;
input [3:0] HBURSTx0;
input [3:0] HBURSTx1;
input [3:0] HBURSTx2;
input [3:0] HBURSTx3;
input [31:0] HWDATAx0;
input [31:0] HWDATAx1;
input [31:0] HWDATAx2;
input [31:0] HWDATAx3;
// X signals from slaves
// We support 6 slaves and 1 default slave
input HREADYx0;
input HREADYx1;
input HREADYx2;
input HREADYx3;
input HREADYx4;
input HREADYx5;
input HREADYx6;
input [1:0] HRESPx0;
input [1:0] HRESPx1;
input [1:0] HRESPx2;
input [1:0] HRESPx3;
input [1:0] HRESPx4;
input [1:0] HRESPx5;
input [1:0] HRESPx6;
input [31:0] HRDATAx0;
input [31:0] HRDATAx1;
input [31:0] HRDATAx2;
input [31:0] HRDATAx3;
input [31:0] HRDATAx4;
input [31:0] HRDATAx5;
input [31:0] HRDATAx6;
input [3:0] HSPLITx0;
input [3:0] HSPLITx1;
input [3:0] HSPLITx2;
input [3:0] HSPLITx3;
input [3:0] HSPLITx4;
input [3:0] HSPLITx5;
input [3:0] HSPLITx6;
// X signals from arbiter
output HGRANTx0;
output HGRANTx1;
output HGRANTx2;
output HGRANTx3;
// X signals from decoder
output HSELx0;
output HSELx1;
output HSElx2;
output HSELx3;
output HSELx4;
output HSELx5;
output HSELx6;
// AMBA AHB main signals
// Reset
input HRESETn;
// Clock
input HCLK;
// Master-to-slave
output [1:0] HTRANS;
output [31:0] HADDR;
output HWRITE;
output [2:0] HSIZE;
output [3:0] HBURST;
output [31:0] HWDATA;
// Slave-to-master
output HREADY;
output [1:0] HRESP;
output [31:0] HRDATA;
// Signals for mux
// MASTER: which signal owns the current address phase
output [3:0] HMASTER;
output HMASTLOCK;
);
wire [3:0] HMASTERD;
wire [3:0] HSPLIT;
// Arbiter
ahb_arbiter3 arbiter3
(
.HBUSREQx0,
.HLOCKx0,
.HGRANTx0,
.HBUSREQx1,
.HLOCKx1,
.HGRANTx1,
.HBUSREQx2,
.HLOCKx2,
.HGRANTx2,
.HBUSREQx3,
.HLOCKx3,
.HGRANTx3,
.HADDR,
.HSPLIT,
.HTRANS,
.HBURST,
.HRESP,
.HREADY,
.HRESETn,
.HCLK,
.HMASTER,
.HMASTERD,
.HMASTLOCK
);
// Decoder
ahb_decoder decoder
(
.HADDR,
.HSELx0,
.HSELx1,
.HSELx2,
.HSELx3,
.HSELx4,
.HSELx5,
.HSELx6
);
// Master-to-slave mux
ahb_mux_m2s m2s_mux
(
.HADDRx0,
.HWRITEx0,
.HTRANSx0,
.HSIZEx0,
.HBURSTx0,
.HWDATAx0,
.HADDRx1,
.HWRITEx1,
.HTRANSx1,
.HSIZEx1,
.HBURSTx1,
.HWDATAx1,
.HADDRx2,
.HWRITEx2,
.HTRANSx2,
.HSIZEx2,
.HBURSTx2,
.HWDATAx2,
.HADDRx3,
.HWRITEx3,
.HTRANSx3,
.HSIZEx3,
.HBURSTx3,
.HWDATAx3,
.HMASTER,
.HMASTERD,
.HADDR,
.HWRITE,
.HTRANS,
.HSIZE,
.HBURST,
.HWDATA
);
// Slave-to-master mux
ahb_mux_s2m s2m_mux
(
.HCLK,
.HRESETn,
.HRDATAx0,
.HRDATAx1,
.HRDATAx2,
.HRDATAx3,
.HRDATAx4,
.HRDATAx5,
.HRDATAx6,
.HSELx0,
.HSELx1,
.HSELx2,
.HSELx3,
.HSELx4,
.HSELx5,
.HSELx6,
.HREADYx0,
.HREADYx1,
.HREADYx2,
.HREADYx3,
.HREADYx4,
.HREADYx5,
.HREADYx6,
.HRESPx0,
.HRESPx1,
.HRESPx2,
.HRESPx3,
.HRESPx4,
.HRESPx5,
.HRESPx6,
.HREADY,
.HRESP,
.HRDATA
);
// SPLIT signal AND gate
assign HSPLIT = (HSPLITx0 |
HSPLITx1 |
HSPLITx2 |
HSPLITx3 |
HSPLITx4 |
HSPLITx5 |
HSPLITx6);
endmodule
| 8.368121 |
module AHB_CCREG (
// --------------------------
// Input pins: AHB signals //
// --------------------------
// Select
input HSEL,
// Address and control
input [31:0] HADDR,
input HWRITE,
input [1:0] HTRANS,
input [2:0] HSIZE,
input [2:0] HBURST,
// Data in
input [31:0] HWDATA,
// Reset and clock
input HRESETn,
input HCLK,
input HMASTLOCK,
// --------------
// Output pins //
// --------------
// Transfer responses
output HREADY,
output [1:0] HRESP,
// Data out
output [31:0] HRDATA,
//reg IOs
output timer_int,
output ext_int,
output soft_int,
input [63:0] INT_ARR
);
reg [63:0] MTIME;
reg [63:0] MTIMECMP;
genvar i;
integer j;
wire [63:0] IPA; //Gateway
reg [63:0] IE; //enable
reg [4:0] IPRIO[63:1]; //priority of each interrupt
reg [4:0] ITHRES; //global threshold
wire [63:1] ICLAIM; //interrupt claim reg
wire [63:1] ICOMPLETE; //interrupt complete
wire [5:0] IID; //prior coded ICLAIM
wire [3:0] COD_INZERO;
wire [63:1]SELICLAIM;//ICLAIM/ICOMPLETE寄存器一个非常恶心的写法：31位分别对应读取的结果（地址是否等于ICLAIM地址&相应的ICLAIM），结果直接送总线（反正正常情况下未选中应该为0）
wire [3:0] CODO0;
wire [3:0] CODO1;
wire [3:0] CODO2;
wire [3:0] CODO3;
reg HWI;
assign HRESP = 0;
assign HREADY = 1;
assign timer_int = (MTIMECMP != 0) ? ((MTIME > MTIMECMP) ? 1'b1 : 1'b0) : 1'b0;
assign IPA[0] = 0;
pcod16s4 cod1 (
.di ({ICLAIM[15:1], 1'b0}),
.dato(CODO0),
.ni (COD_INZERO[0]),
.en (1'b1)
);
pcod16s4 cod2 (
.di (ICLAIM[31:16]),
.dato(CODO1),
.ni (COD_INZERO[1]),
.en (COD_INZERO[0])
);
pcod16s4 cod3 (
.di (ICLAIM[47:32]),
.dato(CODO2),
.ni (COD_INZERO[2]),
.en (COD_INZERO[1:0] == 2'b11)
);
pcod16s4 cod4 (
.di (ICLAIM[63:48]),
.dato(CODO3),
.ni (COD_INZERO[3]),
.en (COD_INZERO[2:0] == 02'b111)
);
assign IID = {
(!COD_INZERO[1]) ? 2'b01 : (!COD_INZERO[2]) ? 2'b10 : (!COD_INZERO[3]) ? 2'b11 : 2'b00
, CODO0 | CODO1 | CODO2 | CODO3
};
assign HRDATA=
(({32{HADDR[16:2]==14'h00}}&MTIME[31:0])|
({32{HADDR[16:2]==14'h01}}&MTIME[63:32])|
({32{HADDR[16:2]==14'h02}}&MTIMECMP[31:0])|
({32{HADDR[16:2]==14'h03}}&MTIMECMP[63:32])|
{31'b0,(SELICLAIM!=0)}|
({32{HADDR[16:2]==15'h7800}}&{27'h0,ITHRES})|
({32{HADDR[16:12]==7'h79}}&{27'h0,IPRIO[HADDR[9:2]]})|
({32{HADDR[16:2]==15'h7A00}}&{IE[31:1],1'b0})|
({32{HADDR[16:2]==15'h7A01}}&IE[63:32])|
({32{HADDR[16:2]==15'h7A04}}&{IPA[31:1],1'b0})|
({32{HADDR[16:2]==15'h7A05}}&IPA[63:32])|
({32{HADDR[16:2]==15'h7A08}}&{27'h0,IID})|
32'h00000000);
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
MTIME <= 0;
MTIMECMP <= 0;
for (j = 1; j <= 63; j = j + 1) IPRIO[j] = 0;
ITHRES <= 0;
IE <= 0;
HWI <= 0;
end else begin
if (HWRITE) HWI <= HSEL;
else HWI <= 0;
if (HSEL & HWI & HADDR[16:3] == 0) begin
if (HADDR[2]) MTIME <= {HWDATA, MTIME[31:0]};
else MTIME <= {MTIME[63:32], HWDATA};
end else MTIME <= MTIME + 1;
if (HSEL & HWI & HADDR[16:3] == 14'h0001) begin
if (HADDR[2]) MTIMECMP <= {HWDATA, MTIMECMP[31:0]};
else MTIMECMP <= {MTIMECMP[63:32], HWDATA};
end
if (HSEL & HWI & HADDR[16:3] == 15'h3D00) begin
if (HADDR[2]) IE <= {HWDATA, IE[31:0]};
else IE <= {IE[63:32], HWDATA};
end
end
end
generate
for (i = 1; i <= 63; i = i + 1) begin
plic_cell PCELL1 (
.int_src(INT_ARR[i]),
.rst_n(HRESETn),
.prio(IPRIO[i]),
.thres(ITHRES),
.ip(IPA[i]),
.en(IE[i]),
.iclaim(ICLAIM[i]),
.ack(ICOMPLETE[i])
);
assign ICOMPLETE[i] = (HWI & HSEL & (HADDR[16:2] == (15'h7900 + i))) ? 1'b1 : 1'b0;
end
for (i = 1; i <= 63; i = i + 1) begin
assign SELICLAIM[i] = (ICLAIM[i] & HSEL & (HADDR[16:2] == (15'h7900 + i))) ? 1'b1 : 1'b0;
end
endgenerate
assign soft_int = (HWI & HSEL & (HADDR[16:2] == (15'h7A09))) ? 1'b1 : 1'b0;
assign ext_int = (ICLAIM != 0);
endmodule
| 6.746145 |
module ahb_crypto_core_top (
haddr,
hclk,
hprot,
hrdata,
hready,
hresp,
hrst_b,
hsel,
hsize,
htrans,
hwdata,
hwrite,
RSA_Interrupt,
AES_Interrupt,
SHA_Interrupt
);
input [31:0] haddr;
input hclk;
output hready;
input hrst_b;
input hsel;
input [31:0] hwdata;
input hwrite;
output [31:0] hrdata;
output RSA_Interrupt;
output AES_Interrupt;
output SHA_Interrupt;
output [1 : 0] hresp;
input [3 : 0] hprot;
input [2 : 0] hsize;
input [1 : 0] htrans;
wire [ 31:0] haddr;
wire hclk;
wire hready;
wire hrst_b;
wire hsel;
wire [ 31:0] hwdata;
wire hwrite;
wire [ 31:0] hrdata;
wire RSA_Interrupt;
wire AES_Interrupt;
wire [1 : 0] hresp;
wire [3 : 0] hprot;
wire [2 : 0] hsize;
wire [1 : 0] htrans;
wire hsel_rsa;
wire hsel_aes;
wire hsel_sha;
reg hsel_rsa_reg;
reg hsel_aes_reg;
reg hsel_sha_reg;
wire [ 31:0] hrdata_rsa;
wire [ 31:0] hrdata_aes;
wire [ 31:0] hrdata_sha;
assign hsel_rsa = (haddr >= `RSA_BASE_ADDR) && (haddr <= `RSA_OFFSET) && hsel;
assign hsel_aes = (haddr >= `AES_BASE_ADDR) && (haddr <= `AES_OFFSET) && hsel;
assign hsel_sha = (haddr >= `SHA_BASE_ADDR) && (haddr <= `SHA_OFFSET) && hsel;
always @(posedge hclk or negedge hrst_b) begin
if (~hrst_b) begin
hsel_rsa_reg <= 0;
hsel_aes_reg <= 0;
hsel_sha_reg <= 0;
end else begin
hsel_rsa_reg <= hsel_rsa;
hsel_aes_reg <= hsel_aes;
hsel_sha_reg <= hsel_sha;
end
end
ahb_rsa_top x_ahb_rsa_top (
.haddr (haddr),
.hclk (hclk),
.hprot (hprot),
.hrdata(hrdata_rsa),
.hready(),
.hresp (),
.hrst_b(hrst_b),
.hsel (hsel_rsa),
.hsize (hsize),
.htrans(htrans),
.hwdata(hwdata),
.hwrite(hwrite),
.intr (RSA_Interrupt)
);
ahb_aes_top x_ahb_aes_top (
.haddr (haddr),
.hclk (hclk),
.hprot (hprot),
.hrdata(hrdata_aes),
.hready(),
.hresp (),
.hrst_b(hrst_b),
.hsel (hsel_aes),
.hsize (hsize),
.htrans(htrans),
.hwdata(hwdata),
.hwrite(hwrite),
.intr (AES_Interrupt)
);
sha1 x_ahb_sha_top (
.haddr (haddr),
.hclk (hclk),
.hprot (hprot),
.hrdata(hrdata_sha),
.hready(),
.hresp (),
.hrst_b(hrst_b),
.hsel (hsel_sha),
.hsize (hsize),
.htrans(htrans),
.hwdata(hwdata),
.hwrite(hwrite),
.intr (SHA_Interrupt)
);
assign hrdata = hsel_rsa_reg ? hrdata_rsa:
hsel_aes_reg ? hrdata_aes:
hsel_sha_reg ? hrdata_sha: 32'b0;
assign hready = 1;
assign hresp = 2'b00;
//assign SHA_Interrupt = 0;
endmodule
| 6.614733 |
module ahb_ctrl (
input HCLK_I,
input HRESET_N_I,
input HREADY_I,
input HSEL_I,
input [ 2:0] HSIZE_I,
input HWRITE_I,
input [11:0] HADDR_I,
input [31:0] HRDATA_I,
output [31:0] HWDATA_O,
output HRESP_O,
output HREADY_O
);
assign HRESP_O = 0;
assign HREADY_O = write_d;
`ifndef SYNTHESIS
assign HWDATA_O = 32'd1;
`else
assign HWDATA_O = 32'd0;
`endif
// input registers
wire [2:0] adr = HADDR_I[4:2];
reg [2:0] adr_d;
always @(posedge HCLK_I) begin
adr_d <= adr;
end
reg write_d;
always @(posedge HCLK_I /* , negedge HRESET_N_I */)
if (!HRESET_N_I) write_d <= 0;
else write_d <= HWRITE_I & HSEL_I;
always @(posedge HCLK_I)
if (write_d) begin
case (adr_d)
`ifndef SYNTHESIS
3'd1: $write("%c", HRDATA_I[7:0]);
3'd2: begin
$write("Existing by user request, code = %08x\n", HRDATA_I);
$finish(0);
end
`endif
endcase
end
endmodule
| 6.660538 |
module ahb_ctrl_top (
//ahb input signals;
hclk,
hrstn,
hsel,
htrans,
hsize,
hburst,
hwrite,
haddr,
hready_in,
hwdata,
//ahb output signals;
hready_out,
hresp,
hrdata
);
//input&output define;
input wire hclk;
input wire hrstn;
input wire hsel;
input wire [1:0] htrans;
input wire [2:0] hsize;
input wire [2:0] hburst;
input wire hwrite;
input wire [31:0] haddr;
input wire hready_in;
input wire [31:0] hwdata;
output wire hready_out;
output wire [1:0] hresp;
output wire [31:0] hrdata;
wire [7:0] sram_q0;
wire [7:0] sram_q1;
wire [7:0] sram_q2;
wire [7:0] sram_q3;
wire [7:0] sram_q4;
wire [7:0] sram_q5;
wire [7:0] sram_q6;
wire [7:0] sram_q7;
wire [3:0] bank0_csn;
wire [3:0] bank1_csn;
wire sram_we;
wire [12:0] sram_addr;
wire [31:0] sram_wdata;
//instance 8K*8 sram;
sram_core u_sram_core (
.clk(hclk),
.bank0_csn(bank0_csn),
.bank1_csn(bank1_csn),
.sram_we(sram_we),
.sram_wdata(sram_wdata),
.sram_addr(sram_addr),
.sram_q0(sram_q0),
.sram_q1(sram_q1),
.sram_q2(sram_q2),
.sram_q3(sram_q3),
.sram_q4(sram_q4),
.sram_q5(sram_q5),
.sram_q6(sram_q6),
.sram_q7(sram_q7)
);
//instance ahb_slave_inf;
ahb_slave_inf u_ahb_slave_inf (
.hclk(hclk),
.hrstn(hrstn),
.hsel(hsel),
.htrans(htrans),
.hsize(hsize),
.hburst(hburst),
.hwrite(hwrite),
.haddr(haddr),
.hready_in(hready_in),
.hwdata(hwdata),
.hready_out(hready_out),
.hresp(hresp),
.hrdata(hrdata),
.sram_q0(sram_q0),
.sram_q1(sram_q1),
.sram_q2(sram_q2),
.sram_q3(sram_q3),
.sram_q4(sram_q4),
.sram_q5(sram_q5),
.sram_q6(sram_q6),
.sram_q7(sram_q7),
.bank0_csn(bank0_csn),
.bank1_csn(bank1_csn),
.sram_we(sram_we),
.sram_addr(sram_addr),
.sram_wdata(sram_wdata)
);
endmodule
| 6.639144 |
module AHB_DDRAM
(
// --------------------------
// Input pins: AHB signals //
// --------------------------
// Select
input HSEL,
// Address and control
input [31:0] HADDR,
input HWRITE,
input [1:0] HTRANS,
input [2:0] HSIZE,
input [2:0] HBURST,
// Data in
input [31:0] HWDATA,
// Reset and clock
input HRESETn,
input HCLK,
input HMASTLOCK,
// --------------
// Output pins //
// --------------
// Transfer responses
output HREADY,
// Data out
output [31:0] HRDATA,
);
parameter cCAS = 2;
parameter cRAS = 2;
reg [31:0]DOUT;
reg [15:0]DATP;
reg [15:0]DATN;
EG_PHY_DDR_8M_16 DDR1
(.clk(SD_CLK),// SDRAM差分时钟正端1bit位宽
.clk_n(SD_CKN),// SDRAM差分时钟负端1bit位宽
.ras_n(SD_RAS_N),// SDRAM 行选通1bit位宽
.cas_n(SD_CAN_N),//SDRAM列选通1bit位宽
.we_n(SD_WE_N),//SDRAM写使能1bit位宽
.cs_n(SD_CS_N), //SDRAM片选信号1bit位宽
.addr(SD_SA),//SDRAM地址11bits位宽
.ba(SD_BA),// SDRAM BANK地址2bits位宽
.dq(SD_DQ),//SDRAM 数据16 bits位宽
.ldqs(SD_LDQS), //SDRAM低字节数据选通信号1bit位宽
.udqs(SD_UDQS),//SDRAM高字节数据选通信号1bit位宽
.ldm(SD_LDM),//SDRAM低字节数据屏蔽信号1bit位宽
.udm(SD_UDM),//SDRAM高字节数据屏蔽信号1bit位宽
.cke(SD_CKE));//SDRAM 时钟使能1bit位宽
endmodule
| 7.52822 |
module ahb_decoder (
// -------------
// Input pins //
// -------------
input [35:0] HADDR,
// --------------
// Output pins //
// --------------
output HSELx0,
output HSELx7,
output HSELx1,
output HSELx2,
output HSELx3,
output HSELx4,
output HSELx5,
output HSELx6
);
assign HSELx0 = (HADDR[35:16] == 36'h000); //Page 0x0000_0000-0x0000_ffff (64KiB)
assign HSELx1 = (HSELx0 == 0) & (HADDR[35:26] == 10'h00); //Page 0x0001_0000-0x03ff_ffff (64MiB)
assign HSELx2 = (HADDR[35:26] == 10'h01); //Page 0x0400_0000-0x07ff_ffff (64MiB)
assign HSELx3 = 0; //
assign HSELx4 = 0; //
assign HSELx5 = 0; //
assign HSELx6 = 0; //
assign HSELx7 = {HSELx0, HSELx1, HSELx2, HSELx3, HSELx4, HSELx5, HSELx6} == 0; //Reserved
endmodule
| 6.790525 |
module ahb_default_slave (
// Split-capable bits
input [3:0] HMASTER,
input HMASTLOCK,
output reg [15:0] HSPLIT,
// -------------
// Input pins //
// -------------
// Select bit
input HSEL,
// Address and control
input [31:0] HADDR,
input HWRITE,
input [1:0] HTRANS,
input [2:0] HSIZE,
input [2:0] HBURST,
// Write data
input [31:0] HWDATA,
// Reset
input HRESETn,
// Clock
input HCLK,
// --------------
// Output pins //
// --------------
output reg HREADY,
output reg [1:0] HRESP,
output reg [31:0] HRDATA
);
// Simple behavior description of default slave
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
HSPLIT <= 16'b0;
HREADY <= 1'b0;
HRESP <= 2'b0;
HRDATA <= 32'h0;
end else begin
if ((HTRANS == `HTRANS_IDLE) || (HTRANS == `HTRANS_BUSY)) begin
HSPLIT <= 16'b0;
HREADY <= 1'b1;
HRESP <= `HRESP_OKAY;
end // Else meaning HTRANS is SEQ or NONSEQ, output ERROR
else begin
HSPLIT <= 16'b0;
HREADY <= 1'b1;
HRESP <= `HRESP_ERROR;
end
end
end
endmodule
| 6.712259 |
module AHB_DUMMY (
// --------------------------
// Input pins: AHB signals //
// --------------------------
// Select
input HSEL,
// Address and control
input [35:0] HADDR,
input HWRITE,
input [1:0] HTRANS,
input [2:0] HSIZE,
input [2:0] HBURST,
// Data in
input [63:0] HWDATA,
// Reset and clock
input HRESETn,
input HCLK,
input HMASTLOCK,
// --------------
// Output pins //
// --------------
// Transfer responses
output HREADY,
output [1:0] HRESP,
// Data out
output [63:0] HRDATA
);
assign HRESP = 0;
assign HREADY = 1;
assign HRDATA = 0;
endmodule
| 6.904052 |
module ahb_dummy_master (
// Arbiter grant
input HGRANT,
// Transfer responses
input HREADY,
input [1:0] HRESP,
// Reset
input HRESETn,
// Clock
input HCLK,
// Data input
input [31:0] HRDATA,
// To arbiter: HLOCK always LOW
// There's no need for dummy master to actively "request" the bus. So no
// HBUSREQ pin needed.
// output reg HBUSREQ,
output HLOCK,
// Transfer type: always IDLE
output [1:0] HTRANS,
// Address and controls
output [31:0] HADDR,
output HWRITE,
output [2:0] HSIZE,
output [2:0] HBURST,
// Data output
output [31:0] HWDATA
);
// The key operation of dummy master is to output HTRANS as IDLE, and HLOCK as
// LOW. And the rest of output signals valid.
// We try to keep the logic simple.
assign HTRANS = `HTRANS_IDLE;
assign HLOCK = 1'b0;
assign HADDR = 32'b0;
assign HWRITE = 1'b0;
assign HSIZE = 3'b0;
assign HBURST = 3'b0;
assign HWDATA = 32'b0;
endmodule
| 8.22269 |
module AHB_ESRAM (
// --------------------------
// Input pins: AHB signals //
// --------------------------
// Select
input HSEL,
// Address and control
input [35:0] HADDR,
input HWRITE,
input [1:0] HTRANS,
input [2:0] HSIZE,
input [2:0] HBURST,
// Data in
input [63:0] HWDATA,
// Reset and clock
input HRESETn,
input HCLK,
input HMASTLOCK,
// --------------
// Output pins //
// --------------
// Transfer responses
output reg HREADY,
output [1:0] HRESP,
// Data out
output reg [63:0] HRDATA
);
parameter rand_seek_delay = 3;
parameter IDLE = 3'h0;
parameter RWAIT = 3'h1;
parameter RDO = 3'h2;
parameter WWAIT = 3'h3;
parameter WDI = 3'h4;
reg [2:0] delay_cnt;
reg [2:0] burst_cnt;
reg [2:0] rw_fsm;
reg [2:0] next_status;
reg [31:0] stor_array[4194304:0]; //16M Stroage Array
wire BURSTFLAG;
wire [4:0] burst_len;
assign BURSTFLAG = (burst_cnt != 7) & (burst_cnt <= burst_len);
assign burst_len = (({5{HBURST == 3'h0}} & 4'h1) | //BL=1
({5{HBURST == 3'h1}} & 5'h1F) | //Infinity length
({5{HBURST == 3'h2}} & 4'h3) | //BL=4
({5{HBURST==3'h3}}&4'h3)|
({5{HBURST==3'h4}}&4'h7)|
({5{HBURST==3'h5}}&4'h7)|
({5{HBURST==3'h6}}&4'hf)|
({5{HBURST==3'h7}}&4'hf));
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
rw_fsm <= IDLE;
end else begin
rw_fsm <= next_status;
end
end
always @(*) begin
case (rw_fsm)
IDLE: next_status = (HSEL) ? ((HWRITE) ? WWAIT : RWAIT) : IDLE;
RWAIT: next_status = (delay_cnt == rand_seek_delay) ? RDO : RWAIT;
RDO: next_status = (BURSTFLAG) ? RDO : ((HSEL) ? ((HWRITE) ? WWAIT : RWAIT) : IDLE);
WWAIT: next_status = (delay_cnt == rand_seek_delay) ? WDI : WWAIT;
WDI: next_status = (BURSTFLAG) ? WDI : ((HSEL) ? ((HWRITE) ? WWAIT : RWAIT) : IDLE);
default: next_status = IDLE;
endcase
end
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
HRDATA <= 0;
HREADY <= 1;
delay_cnt <= 0;
burst_cnt <= 0;
end else begin
case (next_status)
IDLE: begin
HRDATA <= 0;
HREADY <= 1;
delay_cnt <= 0;
burst_cnt <= 0;
end
RWAIT: begin
burst_cnt <= 0;
HREADY <= 0;
delay_cnt <= delay_cnt + 1;
end
RDO: begin
HREADY <= 1;
HRDATA <= stor_array[HADDR[23:2]];
if (BURSTFLAG) burst_cnt <= burst_cnt + 1;
end
WWAIT: begin
HREADY <= 0;
delay_cnt <= delay_cnt + 1;
end
WDI: begin
HREADY <= 1;
delay_cnt <= 0;
HRDATA <= stor_array[HADDR[23:2]];
if (BURSTFLAG) burst_cnt <= burst_cnt + 1;
end
default: begin
HRDATA <= 0;
HREADY <= 1;
delay_cnt <= 0;
burst_cnt <= 0;
end
endcase
end
end
assign HRESP = 0;
endmodule
| 8.643082 |
module ahb_feeder (
input HCLK,
output reg HRESETn,
output [31:0] HADDR,
output [ 2:0] HBURST,
output HMASTLOCK,
output [ 3:0] HPROT,
output [ 2:0] HSIZE,
output [ 1:0] HTRANS,
output [31:0] HWDATA,
output HWRITE,
input [31:0] HRDATA,
input HREADY,
input HRESP
);
ahb_master ahb_master (
.HCLK(HCLK),
.HRESETn(HRESETn),
.HADDR(HADDR),
.HBURST(HBURST),
.HMASTLOCK(HMASTLOCK),
.HPROT(HPROT),
.HSIZE(HSIZE),
.HTRANS(HTRANS),
.HWDATA(HWDATA),
.HWRITE(HWRITE),
.HRDATA(HRDATA),
.HREADY(HREADY),
.HRESP(HRESP)
);
reg [31:0] data_buf;
reg spi_ready_flag;
localparam UART_DATA_ADDR = 32'hbf400000; // register for data to transmit (only one byte is used)
localparam UART_CTRL_ADDR = 32'hbf400004; // control regster
localparam UART_DVDR_ADDR = 32'hbf400008; // clock divider register
localparam SPI_START_ADDR = 32'hbf000000;
localparam SPI_SS_ADDR = 32'hbf000004;
localparam SPI_READY_ADDR = 32'hbf000008;
localparam SPI_DATA_ADDR = 32'hbf000012;
initial begin
// wait for end of reset
repeat (35) @(posedge HCLK);
// Test PMODJSTK controller
ahb_master.ahb_write(SPI_SS_ADDR, 1'b0);
ahb_master.ahb_write(SPI_DATA_ADDR, 32'b10101010);
ahb_master.ahb_write(SPI_START_ADDR, 1'b1);
spi_ready_flag = 1'b0;
while (spi_ready_flag == 1'b0) begin
ahb_master.ahb_read(SPI_READY_ADDR, spi_ready_flag);
end
ahb_master.ahb_read(SPI_DATA_ADDR, data_buf);
ahb_master.ahb_write(SPI_DATA_ADDR, 32'b00110011);
ahb_master.ahb_write(SPI_START_ADDR, 1'b1);
spi_ready_flag = 1'b0;
while (spi_ready_flag == 1'b0) begin
ahb_master.ahb_read(SPI_READY_ADDR, spi_ready_flag);
end
ahb_master.ahb_read(SPI_DATA_ADDR, data_buf);
ahb_master.ahb_write(SPI_DATA_ADDR, 32'b11111111);
ahb_master.ahb_write(SPI_START_ADDR, 1'b1);
spi_ready_flag = 1'b0;
while (spi_ready_flag == 1'b0) begin
ahb_master.ahb_read(SPI_READY_ADDR, spi_ready_flag);
end
ahb_master.ahb_read(SPI_DATA_ADDR, data_buf);
ahb_master.ahb_write(SPI_START_ADDR, 1'b1);
spi_ready_flag = 1'b0;
while (spi_ready_flag == 1'b0) begin
ahb_master.ahb_read(SPI_READY_ADDR, spi_ready_flag);
end
ahb_master.ahb_read(SPI_DATA_ADDR, data_buf);
ahb_master.ahb_write(SPI_START_ADDR, 1'b1);
spi_ready_flag = 1'b0;
while (spi_ready_flag == 1'b0) begin
ahb_master.ahb_read(SPI_READY_ADDR, spi_ready_flag);
end
ahb_master.ahb_read(SPI_DATA_ADDR, data_buf);
ahb_master.ahb_write(SPI_SS_ADDR, 1'b1);
end
endmodule
| 7.667659 |
module AHB_FLASH_CTRL #(
parameter LINE_SIZE = 128,
NUM_LINES = 32
) (
input HCLK,
input HRESETn,
// AHB-Lite Slave Interface
`AHB_SLAVE_IFC,
// External Interface to Quad I/O
output sck,
output ce_n,
input wire [3:0] din,
output wire [3:0] dout,
output wire [3:0] douten
);
wire [23:0] fr_addr, addr_0;
wire fr_rd, rd_0;
wire fr_done, done_0;
wire [LINE_SIZE-1:0] fr_line, line_0;
wire oe;
AHB_FLASH_CACHE_CTRL #(
.LINE_SIZE(LINE_SIZE),
.NUM_LINES(NUM_LINES)
) CCTRL (
// AHB-Lite Slave Interface
.HCLK(HCLK),
.HRESETn(HRESETn),
.HSEL(HSEL),
.HADDR(HADDR),
.HTRANS(HTRANS),
.HWRITE(HWRITE),
.HREADY(HREADY),
.HREADYOUT(HREADYOUT),
.HRDATA(HRDATA),
// The Flash Reader Interface
.fr_addr(fr_addr),
.fr_rd (fr_rd),
.fr_done(fr_done),
.fr_line(fr_line)
);
FLASH_READER #(
.LINE_SIZE(LINE_SIZE)
) FR (
.clk(HCLK),
.rst_n(HRESETn),
.addr(fr_addr),
.rd(fr_rd),
.done(fr_done),
.line(fr_line),
.sck(sck),
.ce_n(ce_n),
.din(din),
.dout(dout),
.douten(oe)
);
assign douten = {4{oe}};
endmodule
| 7.672362 |
module AHB_FLASH_CACHE_CTRL #(
parameter LINE_SIZE = 128,
NUM_LINES = 32
) (
// AHB-Lite Slave Interface
input HCLK,
input HRESETn,
input HSEL,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire HWRITE,
input wire HREADY,
output reg HREADYOUT,
output wire [31:0] HRDATA,
// The Flash Reader Interface
output wire [ 23:0] fr_addr,
output wire fr_rd,
input wire fr_done,
input wire [LINE_SIZE-1:0] fr_line
);
// The State Machine
localparam [1:0] st_idle = 2'b00;
localparam [1:0] st_wait = 2'b01;
localparam [1:0] st_rw = 2'b10;
reg [1:0] state, nstate;
// Cache wires/buses
wire [31:0] c_datao;
wire [23:0] c_A;
wire c_hit;
reg [ 1:0] c_wr;
//AHB-Lite Address Phase Regs
reg last_HSEL;
reg [31:0] last_HADDR;
reg last_HWRITE;
reg [ 1:0] last_HTRANS;
// AHB Interface lgic
always @(posedge HCLK) begin
if (HREADY) begin
last_HSEL <= HSEL;
last_HADDR <= HADDR;
last_HWRITE <= HWRITE;
last_HTRANS <= HTRANS;
end
end
assign HRDATA = c_datao;
always @(posedge HCLK or negedge HRESETn)
if (!HRESETn) HREADYOUT <= 1'b1;
else
case (state)
st_idle:
if (HTRANS[1] & HSEL & HREADY & c_hit) HREADYOUT <= 1'b1;
else if (HTRANS[1] & HSEL & HREADY & ~c_hit) HREADYOUT <= 1'b0;
else HREADYOUT <= 1'b1;
st_wait:
if (c_wr[1]) HREADYOUT <= 1'b1;
else HREADYOUT <= 1'b0;
st_rw:
if (HTRANS[1] & HSEL & HREADY & c_hit) HREADYOUT <= 1'b1;
else if (HTRANS[1] & HSEL & HREADY & ~c_hit) HREADYOUT <= 1'b0;
//else HREADYOUT <= 1'b1;
endcase
// The controller SM
always @(posedge HCLK or negedge HRESETn)
if (HRESETn == 0) state <= st_idle;
else state <= nstate;
always @* begin
nstate = st_idle;
case (state)
st_idle:
if (HTRANS[1] & HSEL & HREADY & c_hit) nstate = st_rw;
else if (HTRANS[1] & HSEL & HREADY & ~c_hit) nstate = st_wait;
st_wait:
if (c_wr[1]) nstate = st_rw;
else nstate = st_wait;
st_rw: //nstate = st_idle;
if (HTRANS[1] & HSEL & HREADY & c_hit) nstate = st_rw;
else if (HTRANS[1] & HSEL & HREADY & ~c_hit) nstate = st_wait;
endcase
end
// The cache interface
assign c_A = last_HADDR[23:0];
always @(posedge HCLK) begin
c_wr[0] <= fr_done;
c_wr[1] <= c_wr[0];
end
DMC #(
.LINE_SIZE(LINE_SIZE),
.NUM_LINES(NUM_LINES)
) CACHE (
.clk(HCLK),
.rst_n(HRESETn),
.A(last_HADDR[23:0]),
.A_h(HADDR[23:0]),
.Do(c_datao),
.hit(c_hit),
.line(fr_line),
.wr(c_wr[0]) // was 1
);
// The Flash Reader Interface
assign fr_rd = ( HTRANS[1] & HSEL & HREADY & ~c_hit & (state==st_idle) ) |
( HTRANS[1] & HSEL & HREADY & ~c_hit & (state==st_rw) );
assign fr_addr = {HADDR[23:4], 4'd0};
endmodule
| 8.259905 |
module FLASH_READER #(
parameter LINE_SIZE = 128
) (
input wire clk,
input wire rst_n,
input wire [ 23:0] addr,
input wire rd,
output wire done,
output wire [LINE_SIZE-1:0] line,
output reg sck,
output reg ce_n,
input wire [3:0] din,
output [3:0] dout,
output wire douten
);
localparam LINE_BYTES = LINE_SIZE / 8;
localparam LINE_CYCLES = LINE_BYTES * 8;
parameter IDLE = 1'b0, READ = 1'b1;
reg state, nstate;
reg [ 7:0] counter;
reg [23:0] saddr;
reg [ 7:0] data [LINE_BYTES-1 : 0];
reg first;
wire [ 7:0] EBH = 8'heb;
// for debugging
wire [ 7:0] data_0 = data[0];
wire [ 7:0] data_1 = data[1];
wire [ 7:0] data_15 = data[15];
always @*
case (state)
IDLE: if (rd) nstate = READ;
else nstate = IDLE;
READ: if (done) nstate = IDLE;
else nstate = READ;
endcase
always @(posedge clk or negedge rst_n)
if (!rst_n) first = 1'b1;
else if (first & done) first <= 0;
always @(posedge clk or negedge rst_n)
if (!rst_n) state = IDLE;
else state <= nstate;
always @(posedge clk or negedge rst_n)
if (!rst_n) sck <= 1'b0;
else if (~ce_n) sck <= ~sck;
else if (state == IDLE) sck <= 1'b0;
always @(posedge clk or negedge rst_n)
if (!rst_n) ce_n <= 1'b1;
else if (state == READ) ce_n <= 1'b0;
else ce_n <= 1'b1;
always @(posedge clk or negedge rst_n)
if (!rst_n) counter <= 8'b0;
else if (sck & ~done) counter <= counter + 1'b1;
else if (state == IDLE)
if (first) counter <= 8'b0;
else counter <= 8'd8;
always @(posedge clk or negedge rst_n)
if (!rst_n) saddr <= 24'b0;
else if ((state == IDLE) && rd) saddr <= addr;
always @(posedge clk)
if (counter >= 20 && counter <= 19 + LINE_BYTES * 2)
if (sck) data[counter/2-10] <= {data[counter/2-10][3:0], din}; // Optimize!
//assign busy = (state == READ);
assign dout = (counter < 8) ? EBH[7 - counter] :
(counter == 8) ? saddr[23:20] :
(counter == 9) ? saddr[19:16] :
(counter == 10) ? saddr[15:12] :
(counter == 11) ? saddr[11:8] :
(counter == 12) ? saddr[7:4] :
(counter == 13) ? saddr[3:0] :
(counter == 14) ? 4'hA :
(counter == 15) ? 4'h5 : 4'h0;
assign douten = (counter < 20);
assign done = (counter == 20 + LINE_BYTES * 2); // was 19?!
generate
genvar i;
for (i = 0; i < LINE_BYTES; i = i + 1) assign line[i*8+7:i*8] = data[i];
endgenerate
endmodule
| 7.838383 |
module DMC #(
parameter LINE_SIZE = 128,
NUM_LINES = 32
) (
input wire clk,
input wire rst_n,
//
input wire [ 23:0] A,
input wire [ 23:0] A_h,
output wire [ 31:0] Do,
output wire hit,
//
input wire [LINE_SIZE-1:0] line,
input wire wr
);
localparam NUM_WORDS = LINE_SIZE / 32;
localparam NUM_BYTES = LINE_SIZE / 8;
localparam OFFSET_WIDTH = $clog2(NUM_BYTES);
localparam INDEX_WIDTH = $clog2(NUM_LINES);
localparam TAG_WIDTH = 24 + 3 - INDEX_WIDTH - OFFSET_WIDTH;
// Cache storage
reg [ LINE_SIZE-1:0] LINES [NUM_LINES-1:0];
reg [ TAG_WIDTH-1:0] TAGS [NUM_LINES-1:0];
reg VALID [NUM_LINES-1:0];
wire [OFFSET_WIDTH-1:0] offset = A[OFFSET_WIDTH-1:0];
wire [OFFSET_WIDTH-1:2] woffset = A[OFFSET_WIDTH-1:2];
wire [ INDEX_WIDTH-1:0] index = A[OFFSET_WIDTH+INDEX_WIDTH-1:OFFSET_WIDTH];
wire [ TAG_WIDTH-1:0] tag = A[23:OFFSET_WIDTH+INDEX_WIDTH];
wire [ INDEX_WIDTH-1:0] index_h = A_h[OFFSET_WIDTH+INDEX_WIDTH-1:OFFSET_WIDTH];
wire [ TAG_WIDTH-1:0] tag_h = A_h[23:OFFSET_WIDTH+INDEX_WIDTH];
assign hit = VALID[index_h] & (TAGS[index_h] == tag_h);
wire [LINE_SIZE:0] sel_line = LINES[index];
generate
if (NUM_WORDS == 4) begin
assign Do = (offset[3:2] == 2'd0) ? sel_line[31:0] :
(offset[3:2] == 2'd1) ? sel_line[63:32] :
(offset[3:2] == 2'd2) ? sel_line[95:64] : sel_line[127:96];
end else if (NUM_WORDS == 8) begin
assign Do = (offset[4:2] == 'd0) ? sel_line[31:0] :
(offset[4:2] == 'd1) ? sel_line[63:32] :
(offset[4:2] == 'd2) ? sel_line[95:64] :
(offset[4:2] == 'd3) ? sel_line[127:96] :
(offset[4:2] == 'd4) ? sel_line[159:128] :
(offset[4:2] == 'd5) ? sel_line[191:160] :
(offset[4:2] == 'd6) ? sel_line[223:192] : sel_line[255:224];
end
endgenerate
// clear the VALID flags
integer i;
always @(posedge clk or negedge rst_n)
if (!rst_n) for (i = 0; i < NUM_LINES; i = i + 1) VALID[i] <= 1'b0;
else if (wr) VALID[index] <= 1'b1;
always @(posedge clk)
if (wr) begin
LINES[index] <= line;
TAGS[index] <= tag;
end
endmodule
| 7.065437 |
module AHB_FLASH_CTRL_TB;
reg HCLK;
reg HRESETn;
wire HREADY;
reg HWRITE;
reg [2:0] HSIZE;
reg [1:0] HTRANS;
reg [31:0] HADDR, HWDATA;
wire [31:0] HRDATA;
wire [ 3:0] fdi;
wire [ 3:0] fdo;
wire [ 3:0] fdio;
wire [ 3:0] fdoe;
wire fsclk;
wire fcen;
always #5 HCLK = !HCLK;
initial begin
$dumpfile("ahb_flash_ctrl_tb.vcd");
$dumpvars;
#45_000_000 $finish;
end
// RESET
initial begin
HCLK = 0;
HRESETn = 1;
#10;
@(posedge HCLK);
HRESETn = 0;
#100;
@(posedge HCLK);
HRESETn = 1;
end
AHB_FLASH_CTRL #(
.AW(SRAM_AW + 2)
) MUV (
.HCLK(HCLK),
.HRESETn(HRESETn),
// AHB-Lite Slave Interface
.HSEL(1'b1),
.HREADYOUT(HREADY),
.HREADY(HREADY),
.HWDATA(HWDATA),
.HRDATA(HRDATA),
.HSIZE(HSIZE),
.HWRITE(HWRITE),
.HTRANS(HTRANS),
.HADDR(HADDR),
.sck(fsclk),
.ce_n(fcen),
.din(fdi),
.dout(fdo),
.douten(fdoe)
);
/* Program Flash */
assign fdio[0] = fdoe[0] ? fdo[0] : 1'bz;
assign fdio[1] = fdoe[1] ? fdo[1] : 1'bz;
assign fdio[2] = fdoe[2] ? fdo[2] : 1'bz;
assign fdio[3] = fdoe[3] ? fdo[3] : 1'bz;
assign fdi = fdio;
sst26wf080b FLASH (
.SCK(fsclk),
.SIO(fdio),
.CEb(fcen)
);
initial begin
#1 $readmemh("flash.hex", FLASH.I0.memory);
end
`include "AHB_tasks.vh"
// test case
reg [31:0] rdata;
initial begin
@(posedge HRESETn);
#200;
AHB_READ_WORD(32'h0000_0000, rdata);
#25;
`CHECK_W(32'haa_aa_aa_00, 1);
#25;
AHB_READ_WORD(32'h0000_0004, rdata);
#25;
`CHECK_W(32'hbb_bb_bb_01, 2);
#25;
AHB_READ_WORD(32'h0000_000C, rdata);
#25;
`CHECK_W(32'hdd_dd_dd_03, 3);
#25;
AHB_READ_WORD(32'h0000_0014, rdata);
#25;
`CHECK_W(32'hff_ff_ff_05, 4);
#25;
$finish;
end
endmodule
| 7.672362 |
module AHB_FLASH_WRITER (
input wire HCLK,
input wire HRESETn,
// AHB-Lite Slave Interface
// `AHB_SLAVE_IFC(),
input wire HSEL,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire HWRITE,
input wire HREADY,
input wire [31:0] HWDATA,
input wire [ 2:0] HSIZE,
output wire HREADYOUT,
output wire [31:0] HRDATA,
// FLASH Interface from the FR
input wire fr_sck,
inout wire fr_ce_n,
output wire [3:0] fr_din,
input wire [3:0] fr_dout,
input wire fr_douten,
// FLASH Interface
output wire fm_sck,
output wire fm_ce_n,
input wire [3:0] fm_din,
output wire [3:0] fm_dout,
output wire [3:0] fm_douten
);
localparam WE_REG_OFF = 8'h00,
SS_REG_OFF = 8'h04,
SCK_REG_OFF = 8'h08,
OE_REG_OFF = 8'h0c,
SO_REG_OFF = 8'h10,
SI_REG_OFF = 8'h14,
ID_REG_OFF = 8'h18;
//`AHB_SLAVE_EPILOGUE()
reg last_HSEL;
reg [31:0] last_HADDR;
reg last_HWRITE;
reg [ 1:0] last_HTRANS;
always @(posedge HCLK) begin
if (HREADY) begin
last_HSEL <= HSEL;
last_HADDR <= HADDR;
last_HWRITE <= HWRITE;
last_HTRANS <= HTRANS;
end
end
wire rd_enable = last_HSEL & (~last_HWRITE) & last_HTRANS[1];
wire wr_enable = last_HSEL & (last_HWRITE) & last_HTRANS[1];
reg WE_REG;
wire WE_REG_sel = wr_enable & (last_HADDR[7:0] == WE_REG_OFF);
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) WE_REG <= 1'h0;
else if (WE_REG_sel & (HWDATA[31:8] == 24'hA5A855)) WE_REG <= HWDATA[0];
end
`AHB_REG(SS_REG, 1, SS_REG_OFF, 1,)
`AHB_REG(SCK_REG, 1, SCK_REG_OFF, 0,)
`AHB_REG(OE_REG, 4, OE_REG_OFF, 0,)
`AHB_REG(SO_REG, 4, SO_REG_OFF, 0,)
assign HRDATA = (last_HADDR[7:0] == SI_REG_OFF) & rd_enable ? {31'h0, fm_din[1]} :
(last_HADDR[7:0] == ID_REG_OFF) & rd_enable ? {32'hABCD0001} :
32'h0;
assign fm_sck = WE_REG ? SCK_REG : fr_sck;
assign fm_ce_n = WE_REG ? SS_REG : fr_ce_n;
assign fm_douten = WE_REG ? OE_REG : {4{fr_douten}};
assign fm_dout = WE_REG ? SO_REG : fr_dout;
assign fr_din = fm_din;
assign HREADYOUT = 1;
endmodule
| 6.895298 |
module AHB_FSB16 (
//ahb 接口
input wire hclk,
input wire hreset_n,
input wire hsel,
input wire [2:0] hsize,
input wire [1:0] htrans,
input wire hwrite,
input wire [31:0] haddr, //本桥只占用地址的低32位空间
input wire [63:0] hwdata,
output wire [63:0] hrdata,
output wire hresp,
output wire hready,
//fsb16信号
output wire clk,
output wire rst_n,
output wire aen,
output reg size,
output wire wr_n,
input wire rdy_n,
input wire error_n,
input wire irq_n,
output reg Hi_z, //拉高之后表示高阻态
output wire [15:0] AD_out,
input wire [15:0] AD_in,
//对内部中断控制器信号
output wire FSB_irq
);
//AHB传输参数
parameter Idld = 2'b00;
//状态机
parameter stb = 3'h0; //等待状态
parameter read_addr_frame0 = 3'h1; //地址帧
parameter read_addr_frame1 = 3'h2;
parameter write_addr_frame0 = 3'h3;
parameter write_addr_frame1 = 3'h4;
parameter nop_frame = 3'h5; //空帧
parameter read_frame = 3'h6; //读帧
parameter write_frame = 3'h7; //写帧
reg [ 2:0] state;
reg [31:0] ADDR_reg;
reg [15:0] output_reg; //输出寄存器
reg [15:0] DATA_reg; //AD复用寄存器
//主状态机
always @(posedge hclk) begin
if (!hreset_n) begin
state <= stb;
end else begin
case (state)
stb:
if (hsel & (htrans != Idld) & !hwrite) begin
state <= read_addr_frame0;
end else if (hsel & (htrans != Idld) & hwrite) begin
state <= write_addr_frame0;
end
//地址帧
read_addr_frame0: state <= read_addr_frame1;
read_addr_frame1: state <= nop_frame;
write_addr_frame0: state <= write_addr_frame1;
write_addr_frame1: state <= write_frame;
nop_frame: state <= read_frame;
//数据帧
//一个AHB传输可能被分为多个小的数据帧进行传输，trans_ready信号指示了当前传输是否完成
//发生了错误，马上转到stb状态
read_frame: state <= (!rdy_n | !error_n) ? stb : state;
write_frame: state <= (!rdy_n | !error_n) ? stb : state;
default: state <= stb;
endcase
end
end
//输出到AHB寄存器
always @(posedge hclk) begin
if (!rdy_n) begin
output_reg <= AD_in;
end
end
//输出寄存器
always @(posedge hclk) begin
if (state == write_addr_frame0) begin
case (haddr[3:1])
2'b00: DATA_reg <= hwdata[15:0];
2'b01: DATA_reg <= hwdata[31:16];
2'b10: DATA_reg <= hwdata[47:32];
2'b11: DATA_reg <= hwdata[63:48];
endcase
end
end
//地址寄存器
always @(posedge hclk) begin
if (hsel & (htrans != Idld)) begin
ADDR_reg <= haddr[31:0];
end
end
//高阻态指示寄存器
always @(posedge hclk) begin
if (state == read_addr_frame1) begin //当地址传输完成 进入高阻态
Hi_z <= 1'b1;
end else if (state == stb) begin
Hi_z <= 1'b0;
end
end
//FSB16信号
//fsb16信号
assign clk = hclk;
assign rst_n = hreset_n;
//地址帧时，进行地址使能
assign aen = (state==read_addr_frame0)|(state==read_addr_frame1)|(state==write_addr_frame0)|(state==write_addr_frame1);
//传输大小为8bit时，SIZE为0，否则SIZE=1
always @(posedge hclk) begin
if (hsel & (htrans != Idld)) begin
size <= (hsize != 3'b000); //如果不是8位传输 那size=1
end else if (!rdy_n) begin
size <= 1'b0; //传输完成后复位
end
end
assign wr_n = (state == write_addr_frame0) | (state == write_addr_frame1);
assign AD_out = (((state==read_addr_frame0)|(state==write_addr_frame0)) ?ADDR_reg[15:0] :16'b0) |
(((state==read_addr_frame1)|(state==write_addr_frame1)) ?ADDR_reg[31:16]:16'b0) |
(((state==write_frame)) ?DATA_reg :16'b0) ;
//AHB响应
assign hresp = !error_n;
assign hready = !rdy_n;
assign FSB_irq = !irq_n;
assign hrdata = {output_reg, output_reg, output_reg, output_reg};
endmodule
| 9.121818 |
module sm_gpio (
//bus side
input clk,
input rst_n,
input bSel,
input [31:0] bAddr,
input bWrite,
input [31:0] bWData,
output reg [31:0] bRData,
//pin side
input [`SM_GPIO_WIDTH - 1:0] gpioInput,
output [`SM_GPIO_WIDTH - 1:0] gpioOutput
);
wire [`SM_GPIO_WIDTH - 1:0] gpioIn; // debounced input signals
wire gpioOutWe; // output Pin value write enable
wire [`SM_GPIO_WIDTH - 1:0] gpioOut; // output Pin next value
assign gpioOut = bWData[`SM_GPIO_WIDTH-1:0];
assign gpioOutWe = bSel & bWrite & (bAddr[3:0] == `SM_GPIO_REG_OUTPUT);
sm_debouncer #(`SM_GPIO_WIDTH) debounce (
clk,
gpioInput,
gpioIn
);
sm_register_we #(`SM_GPIO_WIDTH) r_output (
clk,
rst_n,
gpioOutWe,
gpioOut,
gpioOutput
);
localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;
always @(*)
case (bAddr[3:0])
default: bRData = {{BLANK_WIDTH{1'b0}}, gpioIn};
`SM_GPIO_REG_INPUT: bRData = {{BLANK_WIDTH{1'b0}}, gpioIn};
`SM_GPIO_REG_OUTPUT: bRData = {{BLANK_WIDTH{1'b0}}, gpioOut};
endcase
endmodule
| 6.836966 |
module AHB_LED #(
parameter LED_WIDTH = 32,
parameter CFG_WIDTH = 32,
parameter SAT_WIDTH = 32
) (
input HCLK,
input HRESETn,
input [`ADDR_WIDTH+1:2] HADDR,
input HSEL,
input HWRITE,
input [ 31:0] HWDATA,
input [ 1:0] HTRANS,
input [ 2:0] HSIZE,
input [ 2:0] HBURST,
input [ 3:0] HPROT,
input HMASTLOCK,
input HREADY,
output reg HREADYOUT,
output HRESP,
output reg [ 31:0] HRDATA,
input [SAT_WIDTH-1:0] LED_STATUS,
output reg [CFG_WIDTH-1:0] LED_CFG,
output reg [LED_WIDTH-1:0] LED
);
reg hsel_reg_1q;
reg hwrite_1q;
reg [`ADDR_WIDTH+1:2] haddr_1q;
reg hresp_tmp;
reg hresp_tmp_1q;
//
assign HRESP = hresp_tmp || hresp_tmp_1q;
always @(posedge HCLK or negedge HRESETn)
if (~HRESETn) begin
HREADYOUT <= 1'b1;
hresp_tmp <= `HRESP_OK;
end else if (HSEL && HREADY && (HTRANS == `HTRANS_NONSEQ || HTRANS == `HTRANS_SEQ)) begin
if (HADDR[`ADDR_WIDTH+1:2] > `LED_UPPER_ADDR) begin
HREADYOUT <= 1'b0;
hresp_tmp <= `HRESP_ERROR;
end else begin
HREADYOUT <= 1'b1;
hresp_tmp <= `HRESP_OK;
end
end else begin
HREADYOUT <= 1'b1;
hresp_tmp <= `HRESP_OK;
end
//
always @(posedge HCLK or negedge HRESETn)
if (~HRESETn) hresp_tmp_1q <= `HRESP_OK;
else hresp_tmp_1q <= hresp_tmp;
//
always @(posedge HCLK or negedge HRESETn)
if (~HRESETn) begin
hsel_reg_1q <= 1'b0 ;
hwrite_1q <= 1'b0 ;
haddr_1q <= 0;
end else if(HSEL && HWRITE && HREADY && (HTRANS == `HTRANS_NONSEQ || HTRANS == `HTRANS_SEQ))begin
hsel_reg_1q <= 1'b1;
hwrite_1q <= 1'b1;
haddr_1q <= HADDR;
end else if (HREADY) begin
hsel_reg_1q <= 1'b0 ;
hwrite_1q <= 1'b0 ;
haddr_1q <= 0;
end
//
always @(posedge HCLK or negedge HRESETn)
if (~HRESETn) HRDATA <= 32'd0;
else if (HSEL && HREADY && (HTRANS == `HTRANS_NONSEQ || HTRANS == `HTRANS_SEQ)) begin
case (HADDR[`ADDR_WIDTH+1:2])
`LED_DATA_ADDR: HRDATA <= {{{32 - CFG_WIDTH} {1'b0}}, LED};
`LED_CFG_ADDR: HRDATA <= {{{32 - LED_WIDTH} {1'b0}}, LED_CFG};
`LED_STAT_ADDR: HRDATA <= {{{32 - SAT_WIDTH} {1'b0}}, LED_STATUS};
default: HRDATA <= 32'h0;
endcase
end
//
always @(posedge HCLK or negedge HRESETn)
if (~HRESETn) begin
LED <= 0;
LED_CFG <= 0;
end else if (hsel_reg_1q && hwrite_1q && HREADY) begin
case (haddr_1q[`ADDR_WIDTH+1:2])
`LED_DATA_ADDR: LED <= HWDATA;
`LED_CFG_ADDR: LED_CFG <= HWDATA;
default: ;
endcase
end
endmodule
| 7.033608 |
module ahb_lite_cordic (
//ABB-Lite side
//Select
input HSEL,
//Global signals
input HCLK,
input HRESETn,
//Address and control
input [31 : 0] HADDR,
input [ 2 : 0] HBURST, //ignored
input HMASTLOCK, // ignored
input [ 3 : 0] HPROT, // ignored
input [ 2 : 0] HSIZE, //000=8bits,001=16bits,010=32bits
input [ 1 : 0] HTRANS, //Transfer type
input HWRITE, //1=write 0=read
input HREADY,
//Master data
input [31 : 0] HWDATA, //Write data from master to slave
//Transfer response
output HREADYOUT, //1=transfer finish
output [ 1:0] HRESP, //Transfer success or failure
//Slave Data
output reg [31 : 0] HRDATA,
//CORDIC side
output reg [31:0] in_interface,
output valid_in_interface,
input valid_out_interface,
//fifo side
output read_fifo_en,
input [31:0] out_fifo,
input empty
);
//FSM states
parameter S_IDLE = 0, S_INIT = 1, S_READ = 2, S_WRITE = 3;
reg [5 : 0] State, Next;
// reg [ 24 : 0 ] delay_u;
// reg [ 4 : 0 ] delay_n;
// reg [ 2 : 0 ] HSIZE_old;
// reg [ 31 : 0 ] HADDR_old;
// reg HWRITE_old;
// reg [ 1 : 0 ] HTRANS_old;
// reg [ 31 : 0 ] DATA;
parameter HTRANS_IDLE = 2'b0;
reg [31 : 0] HADDR_LATCH;
always @(posedge HCLK or negedge HRESETn)
if (~HRESETn) HADDR_LATCH <= 0;
else HADDR_LATCH <= HADDR;
assign HRESP = 2'b0;
// assign HREADYOUT = (State == S_IDLE);
// HREADYOUT= !((State == S_READ) && empty && (!valid_out_interface));
// assign HREADYOUT = !((State == S_READ) && empty);
assign HREADYOUT = 1;
assign valid_in_interface = (State == S_WRITE);
assign read_fifo_en = (State == S_READ) & (HADDR_LATCH != 32'h40010000);
wire NeedAction = (HTRANS != HTRANS_IDLE) && HSEL;
// wire NeedRefresh = ~|delay_u;
// wire DelayFinished = ~|delay_n;
// wire BigDelayFinished = ~|delay_u;
// wire RepeatsFinished = ~|repeat_cnt;
always @(posedge HCLK) begin
if (~HRESETn) State <= S_INIT;
else State <= Next;
end
always @(*) begin
//State change decision
case (State)
S_IDLE: Next = NeedAction ? (HWRITE ? S_WRITE : S_READ) : S_IDLE;
S_INIT: Next = NeedAction ? (HWRITE ? S_WRITE : S_READ) : S_IDLE;
S_READ: Next = NeedAction ? (HWRITE ? S_WRITE : S_READ) : S_IDLE;
S_WRITE: Next = NeedAction ? (HWRITE ? S_WRITE : S_READ) : S_IDLE;
endcase
end
// set CORDIC i/o
always @(*) begin
//data
case (State)
default: in_interface = 32'b0; // 32'b0
// S_READ : HRDATA = out_fifo;
S_WRITE: in_interface = HWDATA;
endcase
HRDATA = (HADDR_LATCH == 32'h40010000) ? (empty ? 0 : 1) : out_fifo;
end
endmodule
| 8.564912 |
module fir_filter (
clk,
n_reset,
sample_data,
fir_coefficient,
load_coeff,
data_ready,
one_k_samples,
modwait,
fir_out,
err
);
input [15:0] sample_data;
input [15:0] fir_coefficient;
output [15:0] fir_out;
input clk, n_reset, load_coeff, data_ready;
output one_k_samples, modwait, err;
wire overflow, cnt_up, clear;
wire [2:0] op;
wire [3:0] src1;
wire [3:0] src2;
wire [3:0] dest;
wire [16:0] result;
wire SYNOPSYS_UNCONNECTED__0;
controller A1 (
.clk(clk),
.n_rst(n_reset),
.dr(data_ready),
.lc(load_coeff),
.overflow(overflow),
.cnt_up(cnt_up),
.clear(clear),
.modwait(modwait),
.op(op),
.src1({SYNOPSYS_UNCONNECTED__0, src1[2:0]}),
.src2(src2),
.dest(dest),
.err(err)
);
counter A2 (
.clk(clk),
.n_rst(n_reset),
.cnt_up(cnt_up),
.clear(clear),
.one_k_samples(one_k_samples)
);
datapath A3 (
.clk(clk),
.n_reset(n_reset),
.op(op),
.src1({1'b0, src1[2:0]}),
.src2(src2),
.dest(dest),
.ext_data1(sample_data),
.ext_data2(fir_coefficient),
.outreg_data(result),
.overflow(overflow)
);
magnitude A4 (
.in (result),
.out(fir_out)
);
endmodule
| 6.553796 |
module ahb_lite_fir_filter (
clk,
n_rst,
hsel,
haddr,
hsize,
htrans,
hwrite,
hwdata,
hrdata,
hresp
);
input [3:0] haddr;
input [1:0] htrans;
input [15:0] hwdata;
output [15:0] hrdata;
input clk, n_rst, hsel, hsize, hwrite;
output hresp;
wire data_ready, new_coeff_set, modwait, err, load_coeff;
wire [ 1:0] set;
wire [15:0] sample_data;
wire [ 1:0] coefficient_num;
wire [15:0] fir_coefficient;
wire [15:0] fir_out;
ahb_lite_slave AHB (
.clk(clk),
.n_rst(n_rst),
.set(set),
.sample_data(sample_data),
.data_ready(data_ready),
.new_coefficient_set(new_coeff_set),
.coefficient_num(coefficient_num),
.fir_coefficient(fir_coefficient),
.modwait(modwait),
.fir_out(fir_out),
.err(err),
.hsel(hsel),
.haddr(haddr),
.hsize(hsize),
.htrans(htrans),
.hwrite(hwrite),
.hwdata(hwdata),
.hrdata(hrdata),
.hresp(hresp)
);
coefficient_loader LC (
.clk(clk),
.n_reset(n_rst),
.new_coefficient_set(new_coeff_set),
.modwait(modwait),
.load_coeff(load_coeff),
.coefficient_num(coefficient_num),
.set(set)
);
fir_filter FIR (
.clk(clk),
.n_reset(n_rst),
.sample_data(sample_data),
.fir_coefficient(fir_coefficient),
.load_coeff(load_coeff),
.data_ready(data_ready),
.modwait(modwait),
.fir_out(fir_out),
.err(err)
);
endmodule
| 7.092286 |
module ahb_lite_mem #(
parameter ADDR_WIDTH = 6,
parameter DELAY_VAL = 2
) (
//ABB-Lite side
input HCLK,
input HRESETn,
input [31:0] HADDR,
input [ 2:0] HBURST,
input HMASTLOCK, // ignored
input [ 3:0] HPROT, // ignored
input HSEL,
input [ 2:0] HSIZE,
input [ 1:0] HTRANS,
input [31:0] HWDATA,
input HWRITE,
output reg [31:0] HRDATA,
output HREADY,
output HRESP,
input SI_Endian // ignored
);
assign HRESP = 1'b0;
parameter S_INIT = 0, S_IDLE = 1, S_READ = 2, S_WRITE = 3, S_WAIT = 4;
parameter HTRANS_IDLE = 2'b0;
reg [4 : 0] State, Next;
reg [31 : 0] HADDR_old;
reg HWRITE_old;
reg [ 1 : 0] HTRANS_old;
reg [ 3 : 0] Delay;
assign HREADY = (State == S_IDLE);
wire NeedAction = HTRANS != HTRANS_IDLE && HSEL;
wire DelayFinished = (~|Delay);
always @(posedge HCLK) begin
if (~HRESETn) State <= S_INIT;
else State <= Next;
end
always @(*) begin
Next = State;
case (State)
S_INIT: Next = S_IDLE;
S_IDLE: Next = ~NeedAction ? S_IDLE : (HWRITE ? S_WRITE : S_READ);
S_READ: Next = S_WAIT;
S_WRITE: Next = S_WAIT;
S_WAIT: Next = DelayFinished ? S_IDLE : S_WAIT;
endcase
end
reg [31:0] ram[(1 << ADDR_WIDTH) - 1 : 0];
always @(posedge HCLK) begin
if (State == S_INIT) begin
HADDR_old <= 32'b0;
HWRITE_old <= 1'b0;
HTRANS_old <= HTRANS_IDLE;
end
if (State == S_IDLE && HSEL) begin
HADDR_old <= HADDR;
HWRITE_old <= HWRITE;
HTRANS_old <= HTRANS;
end
if (State == S_READ) HRDATA <= ram[HADDR_old[ADDR_WIDTH-1+2 : 2]];
if (State == S_WRITE) ram[HADDR_old[ADDR_WIDTH-1+2 : 2]] <= HWDATA;
if (State == S_READ || State == S_WRITE) Delay <= DELAY_VAL;
if (~DelayFinished) Delay <= Delay - 1;
end
endmodule
| 7.336072 |
module ahb_lite_s3 #(
parameter P_HSEL0_START = 16'h0000,
P_HSEL0_SIZE = 16'h0100,
P_HSEL1_START = 16'h1000,
P_HSEL1_SIZE = 16'h0100,
P_HSEL2_START = 16'h2000,
P_HSEL2_SIZE = 16'h0100
) (
input wire HRESETn
, input wire HCLK
, input wire [31:0] M_HADDR
, input wire [ 1:0] M_HTRANS
, input wire M_HWRITE
, input wire [ 2:0] M_HSIZE
, input wire [ 2:0] M_HBURST
, input wire [ 3:0] M_HPROT
, input wire [31:0] M_HWDATA
, output wire [31:0] M_HRDATA
, output wire [ 1:0] M_HRESP
, output wire M_HREADY
, output wire HWRITE
, output wire [31:0] HADDR
, output wire [ 1:0] HTRANS
, output wire [ 2:0] HSIZE
, output wire [ 2:0] HBURST
, output wire [ 3:0] HPROT
, output wire [31:0] HWDATA
, output wire HREADY
, output wire HSEL0
, input wire [ 1:0] HRESP0
, input wire [31:0] HRDATA0
, input wire HREADY0
, output wire HSEL1
, input wire [ 1:0] HRESP1
, input wire [31:0] HRDATA1
, input wire HREADY1
, output wire HSEL2
, input wire [ 1:0] HRESP2
, input wire [31:0] HRDATA2
, input wire HREADY2
, input wire REMAP
);
/*********************************************************/
wire HSELd; // default slave
wire [31:0] HRDATAd;
wire [ 1:0] HRESPd;
wire HREADYd;
/*********************************************************/
assign HADDR = M_HADDR;
assign HTRANS = M_HTRANS;
assign HSIZE = M_HSIZE;
assign HBURST = M_HBURST;
assign HWRITE = M_HWRITE;
assign HPROT = M_HPROT;
assign HWDATA = M_HWDATA;
assign HREADY = M_HREADY;
/*********************************************************/
defparam Uahb_decoder.P_NUM = 3, // how many slaves
Uahb_decoder.P_ADDR_START0 = P_HSEL0_START,
Uahb_decoder.P_ADDR_SIZE0 = P_HSEL0_SIZE ,
Uahb_decoder.P_ADDR_START1 = P_HSEL1_START,
Uahb_decoder.P_ADDR_SIZE1 = P_HSEL1_SIZE ,
Uahb_decoder.P_ADDR_START2 = P_HSEL2_START,
Uahb_decoder.P_ADDR_SIZE2 = P_HSEL2_SIZE ;
ahb_decoder_s3 Uahb_decoder (
.HADDR(M_HADDR),
.HSELd(HSELd), // default
.HSEL0(HSEL0),
.HSEL1(HSEL1),
.HSEL2(HSEL2),
.REMAP(REMAP)
);
/*********************************************************/
ahb_s2m_s3 Uahb_s2m (
.HRESETn(HRESETn),
.HCLK (HCLK),
.HSEL0 (HSEL0),
.HSEL1 (HSEL1),
.HSEL2 (HSEL2),
.HSELd (HSELd),
.HRDATA(M_HRDATA),
.HRESP (M_HRESP),
.HREADY(M_HREADY),
.HRDATA0(HRDATA0),
.HRESP0 (HRESP0 ),
.HREADY0(HREADY0),
.HRDATA1(HRDATA1),
.HRESP1 (HRESP1 ),
.HREADY1(HREADY1),
.HRDATA2(HRDATA2),
.HRESP2 (HRESP2 ),
.HREADY2(HREADY2),
.HRDATAd(HRDATAd),
.HRESPd (HRESPd ),
.HREADYd(HREADYd)
);
/*********************************************************/
ahb_default_slave Uahb_default_slave (
.HRESETn(HRESETn),
.HCLK (HCLK),
.HSEL (HSELd),
.HADDR (HADDR),
.HTRANS (HTRANS),
.HWRITE (HWRITE),
.HSIZE (HSIZE),
.HBURST (HBURST),
.HWDATA (HWDATA),
.HRDATA(HRDATAd),
.HRESP (HRESPd),
.HREADYin(HREADY),
.HREADYout(HREADYd)
);
/*********************************************************/
endmodule
| 6.875631 |
module ahb_lite_uart16550 (
//ABB-Lite side
input HCLK,
input HRESETn,
input [31 : 0] HADDR,
input [ 2 : 0] HBURST,
input HMASTLOCK, // ignored
input [ 3 : 0] HPROT, // ignored
input HSEL,
input [ 2 : 0] HSIZE,
input [ 1 : 0] HTRANS,
input [31 : 0] HWDATA,
input HWRITE,
output reg [31 : 0] HRDATA,
output HREADY,
output HRESP,
input SI_Endian, // ignored
//UART side
input UART_SRX, // UART serial input signal
output UART_STX, // UART serial output signal
output UART_RTS, // UART MODEM Request To Send
input UART_CTS, // UART MODEM Clear To Send
output UART_DTR, // UART MODEM Data Terminal Ready
input UART_DSR, // UART MODEM Data Set Ready
input UART_RI, // UART MODEM Ring Indicator
input UART_DCD, // UART MODEM Data Carrier Detect
//UART internal
output UART_BAUD, // UART baudrate output
output UART_INT // UART interrupt
);
parameter S_INIT = 0, S_IDLE = 1, S_READ = 2, S_WRITE = 3;
reg [1:0] State, Next;
assign HRESP = 1'b0;
assign HREADY = (State == S_IDLE);
always @(posedge HCLK) begin
if (~HRESETn) State <= S_INIT;
else State <= Next;
end
reg [2:0] ADDR_old;
wire [2:0] ADDR = HADDR[4:2];
wire [7:0] ReadData;
parameter HTRANS_IDLE = 2'b0;
wire NeedAction = HTRANS != HTRANS_IDLE && HSEL;
always @(*) begin
//State change decision
case (State)
default: Next = S_IDLE;
S_IDLE: Next = ~NeedAction ? S_IDLE : (HWRITE ? S_WRITE : S_READ);
endcase
end
always @(posedge HCLK) begin
case (State)
S_INIT: ;
S_IDLE: if (HSEL) ADDR_old <= ADDR;
S_READ: HRDATA <= {24'b0, ReadData};
S_WRITE: ;
endcase
end
wire [ 7:0] WriteData = HWDATA[7:0];
wire [ 2:0] ActionAddr;
wire WriteAction;
wire ReadAction;
reg [10:0] conf;
assign {ReadAction, WriteAction, ActionAddr} = conf;
always @(*) begin
//io
case (State)
default: conf = {2'b00, 8'b0};
S_READ: conf = {2'b10, ADDR};
S_WRITE: conf = {2'b01, ADDR_old};
endcase
end
// Registers
uart_regs regs (
.clk (HCLK),
.wb_rst_i (~HRESETn),
.wb_addr_i (ActionAddr),
.wb_dat_i (WriteData),
.wb_dat_o (ReadData),
.wb_we_i (WriteAction),
.wb_re_i (ReadAction),
.modem_inputs({UART_CTS, UART_DSR, UART_RI, UART_DCD}),
.stx_pad_o (UART_STX),
.srx_pad_i (UART_SRX),
.rts_pad_o (UART_RTS),
.dtr_pad_o (UART_DTR),
.int_o (UART_INT),
.baud_o (UART_BAUD)
);
endmodule
| 7.902328 |
module ahb_m2s_m2 #(
parameter NUM_MASTER = 3
) (
input wire HRESETn
, input wire HCLK
, input wire HREADY
, input wire [ 3:0] HMASTER
, output reg [31:0] HADDR
, output reg [ 3:0] HPROT
, output reg [ 1:0] HTRANS
, output reg HWRITE
, output reg [ 2:0] HSIZE
, output reg [ 2:0] HBURST
, output reg [31:0] HWDATA
, input wire [31:0] HADDR_0
, input wire [ 3:0] HPROT_0
, input wire [ 1:0] HTRANS_0
, input wire HWRITE_0
, input wire [ 2:0] HSIZE_0
, input wire [ 2:0] HBURST_0
, input wire [31:0] HWDATA_0
, input wire [31:0] HADDR_1
, input wire [ 3:0] HPROT_1
, input wire [ 1:0] HTRANS_1
, input wire HWRITE_1
, input wire [ 2:0] HSIZE_1
, input wire [ 2:0] HBURST_1
, input wire [31:0] HWDATA_1
);
//----------------------------
reg [3:0] hmaster_delay;
always @(posedge HCLK or negedge HRESETn) begin
if (HRESETn == 1'b0) begin
hmaster_delay <= 4'b0;
end else begin
if (HREADY) begin
hmaster_delay <= HMASTER;
end
end
end
//----------------------------
always @(HMASTER or HADDR_0 or HADDR_1)
case (HMASTER)
4'h0: HADDR = HADDR_0;
4'h1: HADDR = HADDR_1;
default: HADDR = ~32'b0;
endcase
always @(HMASTER or HPROT_0 or HPROT_1)
case (HMASTER)
4'h0: HPROT = HPROT_0;
4'h1: HPROT = HPROT_1;
default: HPROT = 32'b0;
endcase
always @(HMASTER or HTRANS_0 or HTRANS_1)
case (HMASTER)
4'h0: HTRANS = HTRANS_0;
4'h1: HTRANS = HTRANS_1;
default: HTRANS = 32'b0;
endcase
always @(HMASTER or HWRITE_0 or HWRITE_1)
case (HMASTER)
4'h0: HWRITE = HWRITE_0;
4'h1: HWRITE = HWRITE_1;
default: HWRITE = 32'b0;
endcase
always @(HMASTER or HSIZE_0 or HSIZE_1)
case (HMASTER)
4'h0: HSIZE = HSIZE_0;
4'h1: HSIZE = HSIZE_1;
default: HSIZE = 32'b0;
endcase
always @(HMASTER or HBURST_0 or HBURST_1)
case (HMASTER)
4'h0: HBURST = HBURST_0;
4'h1: HBURST = HBURST_1;
default: HBURST = 32'b0;
endcase
always @(hmaster_delay or HWDATA_0 or HWDATA_1)
case (hmaster_delay)
4'h0: HWDATA = HWDATA_0;
4'h1: HWDATA = HWDATA_1;
default: HWDATA = 32'b0;
endcase
endmodule
| 6.552353 |
module ahb_master (
hclk,
hresetn,
hrdata,
hresp,
hready_out,
hwrite,
hready_in,
htrans,
haddr,
hwdata
);
input hclk, hresetn, hready_out;
input [1:0] hresp;
input [31:0] hrdata;
output reg hwrite, hready_in;
output reg [1:0] htrans;
output reg [31:0] haddr, hwdata;
parameter cycle = 10;
integer i;
//Single Transfer
task single_write(input [31:0] addr, data);
begin
@(posedge hclk);
#(cycle / 10);
begin
htrans = 2'd2;
hwrite = 1;
haddr = addr;
hwdata = 0;
hready_in = 1;
end
@(posedge hclk);
#(cycle / 10);
begin
htrans = 2'd0;
hwdata = data;
end
end
endtask
task single_read(input [31:0] addr);
begin
@(posedge hclk);
#(cycle / 10);
begin
htrans = 2'd2;
hwrite = 0;
haddr = addr;
hwdata = 0;
hready_in = 1;
end
@(posedge hclk);
#(cycle / 10);
htrans = 2'd0;
end
endtask
//8-Bit Burst Transfer
//INCR4
task burst_write_8bit_INCR4(input [31:0] addr);
begin
@(posedge hclk);
#(cycle / 10);
begin
htrans = 2'd2;
hwrite = 1;
haddr = addr;
hwdata = 0;
hready_in = 1;
end
for (i = 0; i < 3; i = i + 1) begin
@(posedge hclk);
#(cycle / 10);
begin
htrans = 2'd3;
haddr = haddr[31:0] + 1'b1;
hwdata = {$random};
#cycle;
end
end
@(posedge hclk);
#(cycle / 10);
begin
htrans = 2'd0;
hwdata = {$random};
#cycle;
end
end
endtask
task burst_read_8bit_INCR4(input [31:0] addr);
begin
@(posedge hclk);
#(cycle / 10);
begin
htrans = 2'd2;
hwrite = 0;
haddr = addr;
hwdata = 0;
hready_in = 1;
end
for (i = 0; i < 3; i = i + 1) begin
@(posedge hclk);
#(cycle / 10);
begin
htrans = 2'd3;
haddr = haddr[31:0] + 1'b1;
#cycle;
end
end
@(posedge hclk);
#(cycle / 10);
htrans = 2'd0;
end
endtask
//WRAP4
task burst_write_8bit_WRAP4(input [31:0] addr);
begin
@(posedge hclk);
#(cycle / 10);
begin
htrans = 2'd2;
hwrite = 1;
haddr = addr;
hwdata = 0;
hready_in = 1;
end
for (i = 0; i < 3; i = i + 1) begin
@(posedge hclk);
#(cycle / 10);
begin
htrans = 2'd3;
{haddr[31:2], haddr[1:0]} = {haddr[31:2], haddr[1:0] + 1'b1};
hwdata = {$random};
#cycle;
end
end
@(posedge hclk);
#(cycle / 10);
begin
htrans = 2'd0;
hwdata = {$random};
#cycle;
end
end
endtask
task burst_read_8bit_WRAP4(input [31:0] addr);
begin
@(posedge hclk);
#(cycle / 10);
begin
htrans = 2'd2;
hwrite = 0;
haddr = addr;
hwdata = 0;
hready_in = 1;
end
for (i = 0; i < 3; i = i + 1) begin
@(posedge hclk);
#(cycle / 10);
begin
htrans = 2'd3;
{haddr[31:2], haddr[1:0]} = {haddr[31:2], haddr[1:0] + 1'b1};
#cycle;
end
end
@(posedge hclk);
#(cycle / 10);
htrans = 2'd0;
end
endtask
initial begin
//Single Transfer
/*
single_write(32'h8842_c0a6,{$random});
#(4*cycle);
single_read(32'h8400_b866);
#(3*cycle);
*/
//8-Bit Burst Transfer
//INCR4
/*
burst_write_8bit_INCR4(32'h8842_c0a6);
#(4*cycle);
burst_read_8bit_INCR4(32'h8400_b866);
#(3*cycle);
*/
//WRAP4
/*
burst_write_8bit_WRAP4(32'h8842_c0a6);
#(4*cycle);
*/
burst_read_8bit_WRAP4(32'h8400_b866);
#(3 * cycle);
$finish;
end
endmodule
| 7.377627 |
module ahb_master_slave_with_pcie_altpll_qsys_dffpipe_l2c (
clock,
clrn,
d,
q
) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dffe4a;
reg [0:0] dffe5a;
reg [0:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial dffe4a = 0;
// synopsys translate_on
always @(posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a <= {1{1'b1}};
else if (clrn == 1'b0) dffe4a <= 1'b0;
else if (ena == 1'b1) dffe4a <= (d & (~sclr));
// synopsys translate_off
initial dffe5a = 0;
// synopsys translate_on
always @(posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe5a <= {1{1'b1}};
else if (clrn == 1'b0) dffe5a <= 1'b0;
else if (ena == 1'b1) dffe5a <= (dffe4a & (~sclr));
// synopsys translate_off
initial dffe6a = 0;
// synopsys translate_on
always @(posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a <= {1{1'b1}};
else if (clrn == 1'b0) dffe6a <= 1'b0;
else if (ena == 1'b1) dffe6a <= (dffe5a & (~sclr));
assign ena = 1'b1, prn = 1'b1, q = dffe6a, sclr = 1'b0;
endmodule
| 6.966859 |
module ahb_master_slave_with_pcie_altpll_qsys_stdsync_sv6 (
clk,
din,
dout,
reset_n
) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
ahb_master_slave_with_pcie_altpll_qsys_dffpipe_l2c dffpipe3 (
.clock(clk),
.clrn(reset_n),
.d(din),
.q(wire_dffpipe3_q)
);
assign dout = wire_dffpipe3_q;
endmodule
| 6.966859 |
module ahb_master_slave_with_pcie_altpll_qsys (
address,
areset,
c0,
c1,
c2,
c3,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata
) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
output c1;
output c2;
output c3;
input clk;
output locked;
output phasedone;
input read;
output [31:0] readdata;
input reset;
input write;
input [31:0] writedata;
wire wire_stdsync2_dout;
wire [4:0] wire_sd1_clk;
wire wire_sd1_locked;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg pfdena_reg;
wire wire_pfdena_reg_ena;
reg prev_reset;
wire w_locked;
wire w_pfdena;
wire w_phasedone;
wire w_pll_areset_in;
wire w_reset;
wire w_select_control;
wire w_select_status;
ahb_master_slave_with_pcie_altpll_qsys_stdsync_sv6 stdsync2 (
.clk(clk),
.din(wire_sd1_locked),
.dout(wire_stdsync2_dout),
.reset_n((~reset))
);
ahb_master_slave_with_pcie_altpll_qsys_altpll_drn2 sd1 (
.areset((w_pll_areset_in | areset)),
.clk(wire_sd1_clk),
.inclk({{1{1'b0}}, clk}),
.locked(wire_sd1_locked)
);
// synopsys translate_off
initial pfdena_reg = {1{1'b1}};
// synopsys translate_on
always @(posedge clk or posedge reset)
if (reset == 1'b1) pfdena_reg <= {1{1'b1}};
else if (wire_pfdena_reg_ena == 1'b1) pfdena_reg <= writedata[1];
assign wire_pfdena_reg_ena = (write & w_select_control);
// synopsys translate_off
initial prev_reset = 0;
// synopsys translate_on
always @(posedge clk or posedge reset)
if (reset == 1'b1) prev_reset <= 1'b0;
else prev_reset <= w_reset;
assign c0 = wire_sd1_clk[0],
c1 = wire_sd1_clk[1],
c2 = wire_sd1_clk[2],
c3 = wire_sd1_clk[3],
locked = wire_sd1_locked,
phasedone = 1'b0,
readdata = {
{30{1'b0}},
(read & ((w_select_control & w_pfdena) | (w_select_status & w_phasedone))),
(read & ((w_select_control & w_pll_areset_in) | (w_select_status & w_locked)))
},
w_locked = wire_stdsync2_dout,
w_pfdena = pfdena_reg,
w_phasedone = 1'b1,
w_pll_areset_in = prev_reset,
w_reset = ((write & w_select_control) & writedata[0]),
w_select_control = ((~address[1]) & address[0]),
w_select_status = ((~address[1]) & (~address[0]));
endmodule
| 6.966859 |
module ahb_master_slave_with_pcie (
clk_clk,
reset_reset_n,
pcie_ip_reconfig_togxb_data,
pcie_ip_refclk_export,
pcie_ip_test_in_test_in,
pcie_ip_pcie_rstn_export,
pcie_ip_clocks_sim_clk250_export,
pcie_ip_clocks_sim_clk500_export,
pcie_ip_clocks_sim_clk125_export,
pcie_ip_reconfig_busy_busy_altgxb_reconfig,
pcie_ip_pipe_ext_pipe_mode,
pcie_ip_pipe_ext_phystatus_ext,
pcie_ip_pipe_ext_rate_ext,
pcie_ip_pipe_ext_powerdown_ext,
pcie_ip_pipe_ext_txdetectrx_ext,
pcie_ip_pipe_ext_rxelecidle0_ext,
pcie_ip_pipe_ext_rxdata0_ext,
pcie_ip_pipe_ext_rxstatus0_ext,
pcie_ip_pipe_ext_rxvalid0_ext,
pcie_ip_pipe_ext_rxdatak0_ext,
pcie_ip_pipe_ext_txdata0_ext,
pcie_ip_pipe_ext_txdatak0_ext,
pcie_ip_pipe_ext_rxpolarity0_ext,
pcie_ip_pipe_ext_txcompl0_ext,
pcie_ip_pipe_ext_txelecidle0_ext,
pcie_ip_rx_in_rx_datain_0,
pcie_ip_tx_out_tx_dataout_0,
pcie_ip_reconfig_fromgxb_0_data,
sdram_addr,
sdram_ba,
sdram_cas_n,
sdram_cke,
sdram_cs_n,
sdram_dq,
sdram_dqm,
sdram_ras_n,
sdram_we_n,
altpll_sdram_clk,
pcie_ip_powerdown_pll_powerdown,
pcie_ip_powerdown_gxb_powerdown,
ahb_master_slave_2_0_conduit_end_add_data_sel,
ahb_master_slave_2_0_conduit_end_rdwr_address,
ahb_master_slave_2_0_conduit_end_display_data
);
input clk_clk;
input reset_reset_n;
input [3:0] pcie_ip_reconfig_togxb_data;
input pcie_ip_refclk_export;
input [39:0] pcie_ip_test_in_test_in;
input pcie_ip_pcie_rstn_export;
output pcie_ip_clocks_sim_clk250_export;
output pcie_ip_clocks_sim_clk500_export;
output pcie_ip_clocks_sim_clk125_export;
input pcie_ip_reconfig_busy_busy_altgxb_reconfig;
input pcie_ip_pipe_ext_pipe_mode;
input pcie_ip_pipe_ext_phystatus_ext;
output pcie_ip_pipe_ext_rate_ext;
output [1:0] pcie_ip_pipe_ext_powerdown_ext;
output pcie_ip_pipe_ext_txdetectrx_ext;
input pcie_ip_pipe_ext_rxelecidle0_ext;
input [7:0] pcie_ip_pipe_ext_rxdata0_ext;
input [2:0] pcie_ip_pipe_ext_rxstatus0_ext;
input pcie_ip_pipe_ext_rxvalid0_ext;
input pcie_ip_pipe_ext_rxdatak0_ext;
output [7:0] pcie_ip_pipe_ext_txdata0_ext;
output pcie_ip_pipe_ext_txdatak0_ext;
output pcie_ip_pipe_ext_rxpolarity0_ext;
output pcie_ip_pipe_ext_txcompl0_ext;
output pcie_ip_pipe_ext_txelecidle0_ext;
input pcie_ip_rx_in_rx_datain_0;
output pcie_ip_tx_out_tx_dataout_0;
output [4:0] pcie_ip_reconfig_fromgxb_0_data;
output [11:0] sdram_addr;
output [1:0] sdram_ba;
output sdram_cas_n;
output sdram_cke;
output sdram_cs_n;
inout [31:0] sdram_dq;
output [3:0] sdram_dqm;
output sdram_ras_n;
output sdram_we_n;
output altpll_sdram_clk;
input pcie_ip_powerdown_pll_powerdown;
input pcie_ip_powerdown_gxb_powerdown;
input ahb_master_slave_2_0_conduit_end_add_data_sel;
input [15:0] ahb_master_slave_2_0_conduit_end_rdwr_address;
output [31:0] ahb_master_slave_2_0_conduit_end_display_data;
endmodule
| 6.966859 |
module ahb_master_slave_with_pcie_sdram_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
);
output almost_empty;
output almost_full;
output empty;
output full;
output [60:0] rd_data;
input clk;
input rd;
input reset_n;
input wr;
input [60:0] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ 1:0] entries;
reg [60:0] entry_0;
reg [60:0] entry_1;
wire full;
reg rd_address;
reg [60:0] rd_data;
wire [ 1:0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == 2;
assign almost_full = entries >= 1;
assign empty = entries == 0;
assign almost_empty = entries <= 1;
always @(entry_0 or entry_1 or rd_address) begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full) begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty) begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk) begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule
| 6.966859 |
module ahb_master_slave_with_pcie_sgdma_m_readfifo_m_readfifo (
// inputs:
clk,
m_readfifo_data,
m_readfifo_rdreq,
m_readfifo_wrreq,
reset,
// outputs:
m_readfifo_empty,
m_readfifo_full,
m_readfifo_q,
m_readfifo_usedw
);
output m_readfifo_empty;
output m_readfifo_full;
output [35:0] m_readfifo_q;
output [4:0] m_readfifo_usedw;
input clk;
input [35:0] m_readfifo_data;
input m_readfifo_rdreq;
input m_readfifo_wrreq;
input reset;
wire m_readfifo_empty;
wire m_readfifo_full;
wire [35:0] m_readfifo_q;
wire [ 4:0] m_readfifo_usedw;
scfifo ahb_master_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo (
.aclr(reset),
.clock(clk),
.data(m_readfifo_data),
.empty(m_readfifo_empty),
.full(m_readfifo_full),
.q(m_readfifo_q),
.rdreq(m_readfifo_rdreq),
.usedw(m_readfifo_usedw),
.wrreq(m_readfifo_wrreq)
);
defparam ahb_master_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.add_ram_output_register
= "ON",
ahb_master_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.intended_device_family =
"CYCLONEIVGX",
ahb_master_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.lpm_numwords = 32,
ahb_master_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.lpm_showahead = "OFF",
ahb_master_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.lpm_type = "scfifo",
ahb_master_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.lpm_width = 36,
ahb_master_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.lpm_widthu = 5,
ahb_master_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.overflow_checking = "ON",
ahb_master_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.underflow_checking = "ON",
ahb_master_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.use_eab = "ON";
endmodule
| 6.966859 |
module ahb_master_slave_with_pcie_sgdma_m_writefifo_m_writefifo (
// inputs:
clk,
m_writefifo_data,
m_writefifo_rdreq,
m_writefifo_wrreq,
reset,
// outputs:
m_writefifo_empty,
m_writefifo_full,
m_writefifo_q,
m_writefifo_usedw
);
output m_writefifo_empty;
output m_writefifo_full;
output [35:0] m_writefifo_q;
output [8:0] m_writefifo_usedw;
input clk;
input [35:0] m_writefifo_data;
input m_writefifo_rdreq;
input m_writefifo_wrreq;
input reset;
wire m_writefifo_empty;
wire m_writefifo_full;
wire [35:0] m_writefifo_q;
wire [ 8:0] m_writefifo_usedw;
scfifo ahb_master_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo (
.aclr(reset),
.clock(clk),
.data(m_writefifo_data),
.empty(m_writefifo_empty),
.full(m_writefifo_full),
.q(m_writefifo_q),
.rdreq(m_writefifo_rdreq),
.usedw(m_writefifo_usedw),
.wrreq(m_writefifo_wrreq)
);
defparam
ahb_master_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.add_ram_output_register =
"ON",
ahb_master_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.intended_device_family =
"CYCLONEIVGX",
ahb_master_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.lpm_numwords = 512,
ahb_master_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.lpm_showahead = "ON",
ahb_master_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.lpm_type = "scfifo",
ahb_master_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.lpm_width = 36,
ahb_master_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.lpm_widthu = 9,
ahb_master_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.overflow_checking = "ON",
ahb_master_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.underflow_checking =
"ON", ahb_master_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.use_eab = "ON";
endmodule
| 6.966859 |
module ahb_master_slave_with_pcie_sgdma_command_fifo (
// inputs:
clk,
command_fifo_data,
command_fifo_rdreq,
command_fifo_wrreq,
reset,
// outputs:
command_fifo_empty,
command_fifo_full,
command_fifo_q
);
output command_fifo_empty;
output command_fifo_full;
output [103:0] command_fifo_q;
input clk;
input [103:0] command_fifo_data;
input command_fifo_rdreq;
input command_fifo_wrreq;
input reset;
wire command_fifo_empty;
wire command_fifo_full;
wire [103:0] command_fifo_q;
scfifo ahb_master_slave_with_pcie_sgdma_command_fifo_command_fifo (
.aclr(reset),
.clock(clk),
.data(command_fifo_data),
.empty(command_fifo_empty),
.full(command_fifo_full),
.q(command_fifo_q),
.rdreq(command_fifo_rdreq),
.wrreq(command_fifo_wrreq)
);
defparam ahb_master_slave_with_pcie_sgdma_command_fifo_command_fifo.add_ram_output_register =
"ON", ahb_master_slave_with_pcie_sgdma_command_fifo_command_fifo.intended_device_family =
"CYCLONEIVGX", ahb_master_slave_with_pcie_sgdma_command_fifo_command_fifo.lpm_numwords = 2,
ahb_master_slave_with_pcie_sgdma_command_fifo_command_fifo.lpm_showahead = "OFF",
ahb_master_slave_with_pcie_sgdma_command_fifo_command_fifo.lpm_type = "scfifo",
ahb_master_slave_with_pcie_sgdma_command_fifo_command_fifo.lpm_width = 104,
ahb_master_slave_with_pcie_sgdma_command_fifo_command_fifo.lpm_widthu = 1,
ahb_master_slave_with_pcie_sgdma_command_fifo_command_fifo.overflow_checking = "ON",
ahb_master_slave_with_pcie_sgdma_command_fifo_command_fifo.underflow_checking = "ON",
ahb_master_slave_with_pcie_sgdma_command_fifo_command_fifo.use_eab = "ON";
endmodule
| 6.966859 |
module ahb_master_slave_with_pcie_sgdma_desc_address_fifo (
// inputs:
clk,
desc_address_fifo_data,
desc_address_fifo_rdreq,
desc_address_fifo_wrreq,
reset,
// outputs:
desc_address_fifo_empty,
desc_address_fifo_full,
desc_address_fifo_q
);
output desc_address_fifo_empty;
output desc_address_fifo_full;
output [31:0] desc_address_fifo_q;
input clk;
input [31:0] desc_address_fifo_data;
input desc_address_fifo_rdreq;
input desc_address_fifo_wrreq;
input reset;
wire desc_address_fifo_empty;
wire desc_address_fifo_full;
wire [31:0] desc_address_fifo_q;
scfifo ahb_master_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo (
.aclr(reset),
.clock(clk),
.data(desc_address_fifo_data),
.empty(desc_address_fifo_empty),
.full(desc_address_fifo_full),
.q(desc_address_fifo_q),
.rdreq(desc_address_fifo_rdreq),
.wrreq(desc_address_fifo_wrreq)
);
defparam
ahb_master_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.add_ram_output_register =
"ON",
ahb_master_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.intended_device_family =
"CYCLONEIVGX",
ahb_master_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.lpm_numwords = 2,
ahb_master_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.lpm_showahead = "OFF",
ahb_master_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.lpm_type = "scfifo",
ahb_master_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.lpm_width = 32,
ahb_master_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.lpm_widthu = 1,
ahb_master_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.overflow_checking = "ON",
ahb_master_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.underflow_checking =
"ON", ahb_master_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.use_eab = "OFF";
endmodule
| 6.966859 |
module ahb_master_slave_with_pcie_sgdma_status_token_fifo (
// inputs:
clk,
reset,
status_token_fifo_data,
status_token_fifo_rdreq,
status_token_fifo_wrreq,
// outputs:
status_token_fifo_empty,
status_token_fifo_full,
status_token_fifo_q
);
output status_token_fifo_empty;
output status_token_fifo_full;
output [23:0] status_token_fifo_q;
input clk;
input reset;
input [23:0] status_token_fifo_data;
input status_token_fifo_rdreq;
input status_token_fifo_wrreq;
wire status_token_fifo_empty;
wire status_token_fifo_full;
wire [23:0] status_token_fifo_q;
scfifo ahb_master_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo (
.aclr(reset),
.clock(clk),
.data(status_token_fifo_data),
.empty(status_token_fifo_empty),
.full(status_token_fifo_full),
.q(status_token_fifo_q),
.rdreq(status_token_fifo_rdreq),
.wrreq(status_token_fifo_wrreq)
);
defparam
ahb_master_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo.add_ram_output_register =
"ON",
ahb_master_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo.intended_device_family =
"CYCLONEIVGX",
ahb_master_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo.lpm_numwords = 2,
ahb_master_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo.lpm_showahead = "OFF",
ahb_master_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo.lpm_type = "scfifo",
ahb_master_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo.lpm_width = 24,
ahb_master_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo.lpm_widthu = 1,
ahb_master_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo.overflow_checking = "ON",
ahb_master_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo.underflow_checking =
"ON", ahb_master_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo.use_eab = "ON";
endmodule
| 6.966859 |
module ahb_master_slave_with_qsys_bfm (
clk_clk,
reset_reset_n,
ahb_master_slave_2_0_conduit_end_add_data_sel,
ahb_master_slave_2_0_conduit_end_display_data,
ahb_master_slave_2_0_conduit_end_rdwr_address
);
input clk_clk;
input reset_reset_n;
input ahb_master_slave_2_0_conduit_end_add_data_sel;
output [31:0] ahb_master_slave_2_0_conduit_end_display_data;
input [15:0] ahb_master_slave_2_0_conduit_end_rdwr_address;
endmodule
| 6.966859 |
module ahb_decoder (
input [ 31:0] HADDR,
output [`DEVICE_COUNT - 1:0] HSEL
);
wire [31:0] addr = HADDR;
assign HSEL[0] = `SM_MEM_AHB_RAM;
assign HSEL[1] = `SM_MEM_AHB_GPIO;
assign HSEL[2] = 1'b0; // some new peripheral stub
endmodule
| 6.790525 |
module ahb_response_mux (
input [`DEVICE_COUNT - 1:0] HSEL_R,
// Verilog doesn't allow an I/O port to be a 2D array.
// We can do it with some macros, but
// it will be too hard to read this code in this case
input [ 31:0] RDATA_0,
input [ 31:0] RDATA_1,
input [ 31:0] RDATA_2,
input [`DEVICE_COUNT - 1:0] RESP,
input [`DEVICE_COUNT - 1:0] HREADYOUT,
output reg [31:0] HRDATA,
output reg HRESP,
output reg HREADY
);
always @*
casez (HSEL_R)
3'b??1: begin
HRDATA = RDATA_0;
HRESP = RESP[0];
HREADY = HREADYOUT[0];
end
3'b?10: begin
HRDATA = RDATA_1;
HRESP = RESP[1];
HREADY = HREADYOUT[1];
end
3'b100: begin
HRDATA = RDATA_2;
HRESP = RESP[2];
HREADY = HREADYOUT[2];
end
default: begin
HRDATA = 32'b0;
HRESP = 1'b1;
HREADY = 1'b1;
end //error
endcase
endmodule
| 7.178886 |
module PREFIX_bus(PORTS);
input clk;
input reset;
port MMX_GROUP_AHB;
revport SSX_GROUP_AHB;
input SSX_MMX;
input SSX_MMX_resp;
parameter BUS_WIDTH = GONCAT(GROUP_AHB.IN.WIDTH +);
wire [BUS_WIDTH-1:0] SSX_BUS;
wire [BUS_WIDTH-1:0] MMX_BUS;
assign MMX_BUS = {GONCAT(MMX_GROUP_AHB_CMD.IN ,)};
assign SSX_BUS = CONCAT((MMX_BUS & {BUS_WIDTH{SSX_MMX}}) |);
assign {GONCAT(SSX_GROUP_AHB_CMD.IN ,)} = SSX_BUS;
assign SSX_HWDATA = CONCAT((MMX_HWDATA & {DATA_BITS{SSX_MMX_resp}}) |);
LOOP MX
assign MMX_GROUP_AHB_RESP.OUT = CONCAT(({GROUP_AHB_RESP.OUT.WIDTH{SSX_MMX_resp}} & SSX_GROUP_AHB_RESP.OUT) |);
assign MMX_HREADY = CONCAT(((SSX_MMX|SSX_MMX_resp)&SSX_HREADY) |);
ENDLOOP MX
endmodule
| 6.505295 |
module PREFIX_hlast (PORTS);
input clk;
input reset;
input [1:0] MMX_HTRANS;
input MMX_HREADY;
input [2:0] MMX_HBURST;
output MMX_HLAST;
parameter TRANS_IDLE = 2'b00;
parameter TRANS_BUSY = 2'b01;
parameter TRANS_NONSEQ = 2'b10;
parameter TRANS_SEQ = 2'b11;
parameter BURST_SINGLE = 3'b000;
parameter BURST_INCR4 = 3'b011;
parameter BURST_INCR8 = 3'b101;
parameter BURST_INCR16 = 3'b111;
reg [3:0] MMX_count;
assign MMX_HLAST = (MMX_count == 'd1) | ((MMX_HTRANS == TRANS_NONSEQ) & MMX_HREADY & (MMX_HBURST == BURST_SINGLE));
LOOP MX
always @(posedge clk or posedge reset)
if (reset)
MMX_count <= #FFD 4'd15;
else if ((MMX_HTRANS == TRANS_NONSEQ) & MMX_HREADY)
MMX_count <= #FFD
(MMX_HBURST == BURST_INCR4) ? 4'd3 :
(MMX_HBURST == BURST_INCR8) ? 4'd7 :
(MMX_HBURST == BURST_INCR16) ? 4'd15 :
4'd0;
else if ((MMX_HTRANS == TRANS_SEQ) & MMX_HREADY)
MMX_count <= #FFD MMX_count - 1'b1;
ENDLOOP MX
endmodule
| 6.832833 |
module AHB_MFSPM (
// --------------------------
// Input pins: AHB signals //
// --------------------------
// Select
input HSEL,
// Address and control
input [35:0] HADDR,
input HWRITE,
input [1:0] HTRANS,
input [2:0] HSIZE,
input [2:0] HBURST,
// Data in
input [63:0] HWDATA,
// Reset and clock
input HRESETn,
input HCLK,
input HMASTLOCK,
// --------------
// Output pins //
// --------------
// Transfer responses
output HREADY,
output [1:0] HRESP,
// Data out
output [63:0] HRDATA,
//IOP408
//I-ROM
input [10:0] IOPIADDR,
output [15:0] IOPIDATA,
//D-RAM
input [20:0] IOPRADDR,
input [20:0] IOPWADDR,
input [7:0] IOPWDATA,
output [7:0] IOPRDATA,
output IOPWWAIT,
output IOPRWAIT
);
endmodule
| 6.775234 |
module AHB_MUX_2M1S #(
parameter SZ = 64
) (
input wire HCLK,
input wire HRESETn,
// Port 1
input wire [ 31:0] HADDR_M1,
input wire [ 1:0] HTRANS_M1,
input wire HWRITE_M1,
input wire [ 2:0] HSIZE_M1,
input wire [SZ-1:0] HWDATA_M1,
output wire HREADY_M1,
output wire [SZ-1:0] HRDATA_M1,
// Port 2
input wire [ 31:0] HADDR_M2,
input wire [ 1:0] HTRANS_M2,
input wire HWRITE_M2,
input wire [ 2:0] HSIZE_M2,
input wire [SZ-1:0] HWDATA_M2,
output wire HREADY_M2,
output wire [SZ-1:0] HRDATA_M2,
// Master Port
input wire HREADY,
input wire [SZ-1:0] HRDATA,
output wire [ 31:0] HADDR,
output wire [ 1:0] HTRANS,
output wire HWRITE,
output wire [ 2:0] HSIZE,
output wire [SZ-1:0] HWDATA
);
localparam [4:0] S0 = 1;
localparam [4:0] S1 = 2;
localparam [4:0] S2 = 4;
localparam [4:0] S3 = 8;
localparam [4:0] S4 = 16;
reg [4:0] state, nstate;
always @(posedge HCLK or negedge HRESETn)
if (!HRESETn) state <= S2;
else state <= nstate;
always @* begin
nstate = S0;
case (state)
S0: if (HTRANS_M1[1]) nstate = S1;
else if (HTRANS_M2[1]) nstate = S2;
else nstate = S0;
S1: if (!HTRANS_M1[1] & HREADY) nstate = S2;
else nstate = S1;
S2: if (HTRANS_M1[1] & HREADY) nstate = S1;
else nstate = S2;
endcase
end
assign HREADY_M1 = (state == S0) ? 1'b1 : (state == S1) ? HREADY : ((state == S2) && (HTRANS_M2[1] == 1'b0)) ? HREADY : 1'b0;
assign HREADY_M2 = (state == S0) ? 1'b1 : (state == S2) ? HREADY : ((state == S1) && (HTRANS_M1[1] == 1'b0)) ? HREADY : 1'b0;
assign HRDATA_M1 = HRDATA;
assign HRDATA_M2 = HRDATA;
reg [1:0] htrans;
always @*
case (state)
S0: htrans = (HTRANS_M1[1]) ? HTRANS_M1 : 2'b00;
S1: htrans = (HTRANS_M1[1]) ? HTRANS_M1 : HTRANS_M2;
S2: htrans = (HTRANS_M2[1]) ? HTRANS_M2 : HTRANS_M1;
default: htrans = 2'b00;
endcase
reg [31:0] haddr;
always @*
case (state)
S0: haddr = (HTRANS_M1[1]) ? HADDR_M1 : 32'b0;
S1: haddr = (HTRANS_M1[1]) ? HADDR_M1 : HADDR_M2;
S2: haddr = (HTRANS_M2[1]) ? HADDR_M2 : HADDR_M1;
default: haddr = 32'b0;
endcase
reg [0:0] hwrite;
always @*
case (state)
S0: hwrite = (HTRANS_M1[1]) ? HWRITE_M1 : 1'b0;
S1: hwrite = (HTRANS_M1[1]) ? HWRITE_M1 : HWRITE_M2;
S2: hwrite = (HTRANS_M2[1]) ? HWRITE_M2 : HWRITE_M1;
default: hwrite = 1'b0;
endcase
reg [2:0] hsize;
always @*
case (state)
S0: hsize = (HTRANS_M1[1]) ? HSIZE_M1 : 3'b0;
S1: hsize = (HTRANS_M1[1]) ? HSIZE_M1 : HSIZE_M2;
S2: hsize = (HTRANS_M2[1]) ? HSIZE_M2 : HSIZE_M1;
default: hsize = 3'b0;
endcase
reg [SZ-1:0] hwdata;
always @*
case (state)
S0: hwdata = 'b0;
S1: hwdata = HWDATA_M1;
S2: hwdata = HWDATA_M2;
default: hwdata = 'b0;
endcase
assign HTRANS = htrans;
assign HADDR = haddr;
assign HWDATA = hwdata;
assign HSIZE = hsize;
assign HWRITE = hwrite;
endmodule
| 6.814989 |
module ahb_mux_m2s (
// -------------
// Input pins //
// -------------
// Master 0
// Address and control
input [31:0] HADDRx0,
input HWRITEx0,
input [1:0] HTRANSx0,
input [2:0] HSIZEx0,
input [2:0] HBURSTx0,
// Write data
input [31:0] HWDATAx0,
// Master 1 (default master)
// Address and control
input [31:0] HADDRx1,
input HWRITEx1,
input [1:0] HTRANSx1,
input [2:0] HSIZEx1,
input [2:0] HBURSTx1,
// Write data
input [31:0] HWDATAx1,
// Master 2
// Address and control
input [31:0] HADDRx2,
input HWRITEx2,
input [1:0] HTRANSx2,
input [2:0] HSIZEx2,
input [2:0] HBURSTx2,
// Write data
input [31:0] HWDATAx2,
// Master 3
// Address and control
input [31:0] HADDRx3,
input HWRITEx3,
input [1:0] HTRANSx3,
input [2:0] HSIZEx3,
input [2:0] HBURSTx3,
// Write data
input [31:0] HWDATAx3,
// Select signals
input [3:0] HMASTER,
input [3:0] HMASTERD,
// --------------
// Output pins //
// --------------
output reg [31:0] HADDR,
output reg HWRITE,
output reg [1:0] HTRANS,
output reg [2:0] HSIZE,
output reg [2:0] HBURST,
output reg [31:0] HWDATA
);
// --------------------------
// Address and control mux //
// --------------------------
// Master 1 is default master.
always @(*) begin
case (HMASTER)
4'h0: begin
HADDR = HADDRx0;
HWRITE = HWRITEx0;
HTRANS = HTRANSx0;
HSIZE = HSIZEx0;
HBURST = HBURSTx0;
end
4'h2: begin
HADDR = HADDRx2;
HWRITE = HWRITEx2;
HTRANS = HTRANSx2;
HSIZE = HSIZEx2;
HBURST = HBURSTx2;
end
4'h3: begin
HADDR = HADDRx3;
HWRITE = HWRITEx3;
HTRANS = HTRANSx3;
HSIZE = HSIZEx3;
HBURST = HBURSTx3;
end
default: begin
HADDR = HADDRx1;
HWRITE = HWRITEx1;
HTRANS = HTRANSx1;
HSIZE = HSIZEx1;
HBURST = HBURSTx1;
end
endcase
end
// -----------------
// Write data mux //
// -----------------
always @(*) begin
case (HMASTERD)
4'h0: HWDATA = HWDATAx0;
4'h2: HWDATA = HWDATAx2;
4'h3: HWDATA = HWDATAx3;
default: HWDATA = HWDATAx1;
endcase
end
endmodule
| 9.192769 |
module ahb_mux_s2m (
// -------------
// Input pins //
// -------------
// Clock and reset
input HCLK,
input HRESETn,
// Slave datas
input [63:0] HRDATAx0,
input [63:0] HRDATAx7,
input [63:0] HRDATAx1,
input [63:0] HRDATAx2,
input [63:0] HRDATAx3,
input [63:0] HRDATAx4,
input [63:0] HRDATAx5,
input [63:0] HRDATAx6,
// Control signals
input HSELx0,
input HSELx7,
input HSELx1,
input HSELx2,
input HSELx3,
input HSELx4,
input HSELx5,
input HSELx6,
// Slave responses
input HREADYx0,
input HREADYx7,
input HREADYx1,
input HREADYx2,
input HREADYx3,
input HREADYx4,
input HREADYx5,
input HREADYx6,
input [1:0] HRESPx0,
input [1:0] HRESPx7,
input [1:0] HRESPx1,
input [1:0] HRESPx2,
input [1:0] HRESPx3,
input [1:0] HRESPx4,
input [1:0] HRESPx5,
input [1:0] HRESPx6,
// --------------
// Output pins //
// --------------
output reg HREADY,
output reg [1:0] HRESP,
output reg [63:0] HRDATA
);
// Slave select register
reg [3:0] slave_select;
// Slave select register update
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
slave_select <= 16'b0;
end else begin
// If HREADY is high, update slave_select
if (HREADY) begin
case ({
HSELx7, HSELx6, HSELx5, HSELx4, HSELx3, HSELx2, HSELx1, HSELx0
})
8'b10: slave_select <= 4'h1;
8'b100: slave_select <= 4'h2;
8'b1000: slave_select <= 4'h3;
8'b10000: slave_select <= 4'h4;
8'b100000: slave_select <= 4'h5;
8'b1000000: slave_select <= 4'h6;
8'b10000000: slave_select <= 4'h7;
// Default is for default slave
default: slave_select <= 4'h0;
endcase
end
end
end
// Read data multiplexor
always @(*) begin
case (slave_select)
4'h1: HRDATA = HRDATAx1;
4'h2: HRDATA = HRDATAx2;
4'h3: HRDATA = HRDATAx3;
4'h4: HRDATA = HRDATAx4;
4'h5: HRDATA = HRDATAx5;
4'h6: HRDATA = HRDATAx6;
4'h7: HRDATA = HRDATAx7;
default: HRDATA = HRDATAx0;
endcase
end
// Response multiplexor
always @(*) begin
case (slave_select)
4'h1: begin
HRESP = HRESPx1;
HREADY = HREADYx1;
end
4'h2: begin
HRESP = HRESPx2;
HREADY = HREADYx2;
end
4'h3: begin
HRESP = HRESPx3;
HREADY = HREADYx3;
end
4'h4: begin
HRESP = HRESPx4;
HREADY = HREADYx4;
end
4'h5: begin
HRESP = HRESPx5;
HREADY = HREADYx5;
end
4'h6: begin
HRESP = HRESPx6;
HREADY = HREADYx6;
end
4'h7: begin
HRESP = HRESPx7;
HREADY = HREADYx7;
end
default: begin
HRESP = HRESPx0;
HREADY = HREADYx0;
end
endcase
end
endmodule
| 7.254809 |
module AHB_OCRAM (
// --------------------------
// Input pins: AHB signals //
// --------------------------
// Select
input HSEL,
// Address and control
input [31:0] HADDR,
input HWRITE,
input [1:0] HTRANS,
input [2:0] HSIZE,
input [2:0] HBURST,
// Data in
input [31:0] HWDATA,
// Reset and clock
input HRESETn,
input HCLK,
input HMASTLOCK,
// --------------
// Output pins //
// --------------
// Transfer responses
output HREADY,
output [1:0] HRESP,
// Data out
output [31:0] HRDATA
);
wire [31:0] DI;
wire [31:0] DI8;
wire [31:0] DI16;
wire [ 7:0] DO8;
wire [ 7:0] DO16;
wire [ 7:0] DO24;
wire [ 7:0] DO32;
wire [ 7:0] MUX8O;
wire [15:0] MUX16O;
reg [ 3:0] WE_F;
wire [ 3:0] WE_DEC8;
wire [ 3:0] WE_DEC16;
reg [14:0] WADDR;
//Xilinx native BRAM IP used, configured @ 8bit data width and 32768 depth
BLKRAM8 OCRAM_L8 (
.addra(WADDR),
.clka (HCLK),
.dina (DI[7:0]),
.ena (HSEL),
.wea (WE_F[0]),
.addrb(HADDR[16:2]),
.clkb (HCLK),
.doutb(DO8),
.enb (HSEL)
);
BLKRAM8 OCROM_L16 (
.addra(WADDR),
.clka (HCLK),
.dina (DI[15:8]),
.ena (HSEL),
.wea (WE_F[1]),
.addrb(HADDR[16:2]),
.clkb (HCLK),
.doutb(DO16),
.enb (HSEL)
);
BLKRAM8 OCROM_H24 (
.addra(WADDR),
.clka (HCLK),
.dina (DI[23:16]),
.ena (HSEL),
.wea (WE_F[2]),
.addrb(HADDR[16:2]),
.clkb (HCLK),
.doutb(DO24),
.enb (HSEL)
);
BLKRAM8 OCROM_H32 (
.addra(WADDR),
.clka (HCLK),
.dina (DI[31:24]),
.ena (HSEL),
.wea (WE_F[3]),
.addrb(HADDR[16:2]),
.clkb (HCLK),
.doutb(DO32),
.enb (HSEL)
);
assign MUX8O = //8 Bit Output MUX
(({8{HADDR[1:0]==2'b00}}&DO8)|
({8{HADDR[1:0]==2'b01}}&DO16)|
({8{HADDR[1:0]==2'b10}}&DO24)|
({8{HADDR[1:0]==2'b11}}&DO32));
assign MUX16O = //16 Bit Output MUX
(({16{~HADDR[1]}} & {DO16, DO8}) | ({16{HADDR[1]}} & {DO32, DO24}));
assign HRDATA = //Bus Output MUX
(({32{HSIZE[1:0]==2'b00}}&{24'b0,MUX8O})|
({32{HSIZE[1:0]==2'b01}}&{16'b0,WE_DEC16})|
({32{HSIZE[1:0]==2'b10}}&{DO32,DO24,DO16,DO8}));
assign DI8 = //8 Bit Input MUX
(({32{HADDR[1:0]==2'b00}}&{24'b0,HWDATA[7:0]})|
({32{HADDR[1:0]==2'b01}}&{16'b0,HWDATA[7:0],8'b0})|
({32{HADDR[1:0]==2'b10}}&{8'b0,HWDATA[7:0],16'b0})|
({32{HADDR[1:0]==2'b11}}&{HWDATA[7:0],24'b0}));
assign DI16 = //16 Bit Input MUX
(({32{~HADDR[1]}} & {16'b0, HWDATA[15:0]}) | ({32{HADDR[1]}} & {HWDATA[15:0], 16'b0}));
assign DI = //Bus Input MUX
(({32{HSIZE[1:0]==2'b00}}&DI8)|
({32{HSIZE[1:0]==2'b01}}&DI16)|
({32{HSIZE[1:0]==2'b10}}&HWDATA));
assign WE_DEC8 = //8bit WE Signal gen
(({4{HADDR[1:0]==2'b00}}&4'b0001)|
({4{HADDR[1:0]==2'b01}}&4'b0010)|
({4{HADDR[1:0]==2'b10}}&4'b0100)|
({4{HADDR[1:0]==2'b11}}&4'b1000));
assign WE_DEC16 = (({16{~HADDR[1]}} & 4'b0011) | ({16{HADDR[1]}} & 4'b1100));
// --------------------
// Output generation //
// --------------------
// Normal output signals generation
assign HMASTLOCK_o = HMASTLOCK;
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
WE_F <= 0;
WADDR <= 0;
end else begin
if (HWRITE) begin
WE_F <= //WE Signal select
(({4{HSIZE[1:0]==2'b00}}&WE_DEC8)|
({4{HSIZE[1:0]==2'b01}}&WE_DEC16)|
({4{HSIZE[1:0]==2'b10}})&{4{HWRITE&HSEL}});
WADDR <= HADDR[16:2];
end else WE_F <= 0;
end
end
assign HRESP = 0;
assign HREADY = 1;
endmodule
| 7.580484 |
module apb_pio (
// --------------------------------------------------------------------------
// Port Definitions
// --------------------------------------------------------------------------
input wire HCLK, // Clock
input wire HRESETn, // Reset
// Port1 RW
input wire HSEL, // Device select
input wire [31:0] HADDR, // Address
input wire [ 1:0] HTRANS, // Transfer control
input wire [ 2:0] HSIZE, // Transfer size
input wire [ 3:0] HPROT, // Protection control
input wire HWRITE, // Write control
input wire HREADY, // Transfer phase done
input wire [31:0] HWDATA, // Write data
output wire HREADYOUT, // Device ready
output reg [31:0] HRDATA, // Read data output
output wire HRESP, // Device response
output wire [31:0] GPIO // IO Port
);
// Registers
reg [31:0] pio_reg;
reg ram_wr, ram_rd;
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) ram_wr <= 1'b0;
else begin
if (HSEL && (HTRANS[1] == 1'b1) && HWRITE) ram_wr <= 1'b1;
else ram_wr <= 1'b0;
end
end
always @(*) begin
if (HSEL && (HTRANS[1] == 1'b1) && !HWRITE) ram_rd = 1'b1;
else ram_rd = 1'b0;
end
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
pio_reg <= 'd0;
HRDATA <= 'd0;
end else begin
if (ram_wr) pio_reg <= HWDATA;
else if (ram_rd) HRDATA <= pio_reg;
else HRDATA <= 'd0;
end
end
assign HREADYOUT = 1'b1;
assign HRESP = 1'b0;
assign GPIO = pio_reg;
endmodule
| 6.562932 |
module ahb_ram #(
parameter WIDTH = 6 // memory internal bus width (determines RAM size)
) (
input HCLK,
input HRESETn,
input HSEL,
input HWRITE,
input HREADY,
input [ 1:0] HTRANS,
input [31:0] HADDR,
output [31:0] HRDATA,
input [31:0] HWDATA,
output HREADYOUT,
output HRESP
);
// bus input decode
wire request = HREADY & HSEL & HTRANS != `HTRANS_IDLE;
wire request_r = request & !HWRITE;
wire request_w;
wire request_w_new = request & HWRITE;
sm_register_c r_request_w (
HCLK,
HRESETn,
request_w_new,
request_w
);
wire [31:0] addr_w;
wire [31:0] addr_r = HADDR;
sm_register_we #(32) r_addr_w (
HCLK,
HRESETn,
request,
HADDR,
addr_w
);
// memory interface
wire mem_we = request_w;
wire [31:0] mem_wd = HWDATA;
wire [31:0] mem_addr = request_w ? addr_w : addr_r;
wire mem_valid = request_r | request_w;
wire mem_ready;
wire [31:0] mem_rd;
sm_ram_busy #(WIDTH) ram (
.clk (HCLK),
.rst_n(HRESETn),
.a (mem_addr),
.we (mem_we),
.wd (mem_wd),
.valid(mem_valid),
.ready(mem_ready),
.rd (mem_rd)
);
// read after write hazard
wire hz_raw;
wire hz_raw_new = (request_r & request_w) | request_w_new;
sm_register_c r_hz_raw (
HCLK,
HRESETn,
hz_raw_new,
hz_raw
);
// bus output
assign HREADYOUT = ~hz_raw & mem_ready;
assign HRDATA = mem_rd;
assign HRESP = 1'b0;
endmodule
| 9.169843 |
module is based on a state machine that is used to
// detect the external reset being asserted, and is used to generate the
// system reset output.
//
// The HRESETn is asynchronously asserted(LOW) and always deasserted on
// posedge HCLK.
//
// Copyright (C) 2015 Lianghao Yuan
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St
`ifndef AHB_RESET_CTRL_V
`define AHB_RESET_CTRL_V
module ahb_reset_ctrl(
// ----------------
// Input signals //
// ----------------
//
// HPB clock
input HCLK,
// Power-on reset: Power-on reset input. This active lOW signal causes a
// cold reset when LOW. Can be asserted asynchronously to HCLK. The source
// of the nPOReset signal is implementation-dependent.
input nPOReset,
// The watchdog clock domain reset input. (Ignored in our implementation)
// input WDOGRES,
// -----------------
// Output signals //
// -----------------
//
// The watchdog clock domain reset output. In this implementation we treat
// WDOGRESn as the same with HRESETn. (Ignored in our implementation)
// output WDOGRESn,
// The system reset output
output reg HRESETn
);
// Treat WDOGRESn the same as HRESETn
// assign WDOGRESn = HRESETn;
// Reset signal generation
// We assert the HRESETn asynchronously and deassert it synchronously
always @ (posedge HCLK or negedge nPOReset) begin
if(!nPOReset) begin
HRESETn <= 0;
end
else begin
HRESETn <= 1;
end
end
endmodule
| 8.355054 |
module AHB_ROM (
// --------------------------
// Input pins: AHB signals //
// --------------------------
// Select
input HSEL,
// Address and control
input [35:0] HADDR,
input HWRITE,
input [1:0] HTRANS,
input [2:0] HSIZE,
input [2:0] HBURST,
// Data in
input [63:0] HWDATA,
// Reset and clock
input HRESETn,
input HCLK,
input HMASTLOCK,
// --------------
// Output pins //
// --------------
// Transfer responses
output HREADY,
output [1:0] HRESP,
// Data out
output [63:0] HRDATA
);
wire [63:0] OMUX;
assign HRDATA = OMUX;
wire [31:0] W32;
wire [63:0] DO64;
assign OMUX = (HSEL) ? ((HSIZE == 3'b010) ? ({32'b0, W32}) : DO64) : 64'b0;
assign W32 = (HADDR[2]) ? (DO64[63:32]) : (DO64[31:0]);
BOOTROM64 BOOTROM1 (
.addra(HADDR[13:3]),
.clka (HCLK),
.douta(DO64),
.ena (HSEL)
);
// --------------------
// Output generation //
// --------------------
// Normal output signals generation
assign HMASTLOCK_o = HMASTLOCK;
assign HRESP = 0;
assign HREADY = 1;
endmodule
| 7.094237 |
module AHB_SDIO (
input HSEL,
// Address and control
input [35:0] HADDR,
input HWRITE,
input [1:0] HTRANS,
input [2:0] HSIZE,
input [2:0] HBURST,
// Data in
input [63:0] HWDATA,
// Reset and clock
input HRESETn,
input HCLK,
input HMASTLOCK,
// --------------
// Output pins //
// --------------
// Transfer responses
output reg HREADY,
output HRESP,
// Data out
output reg [63:0] HRDATA,
//SDIO port
output [3:0] SDIO_o,
input [3:0] SDIO_i,
output [3:0] SDIO_dir,
output SDCMD_o,
input SDCMD_i,
output SDCMD_dir,
output SDIOCLK
);
endmodule
| 6.619654 |
module ahb_slave_inf (
//ahb input signals;
hclk,
hrstn,
hsel,
htrans,
hsize,
hburst,
hwrite,
haddr,
hready_in,
hwdata,
//ahb output signals;
hready_out,
hresp,
hrdata,
//sram_core output signals;
sram_q0,
sram_q1,
sram_q2,
sram_q3,
sram_q4,
sram_q5,
sram_q6,
sram_q7,
//sram_core contrl signals;
bank0_csn,
bank1_csn,
sram_we,
sram_addr,
sram_wdata
);
//htrans type;
parameter IDLE = 0;
parameter BUSY = 1;
parameter NONSEQ = 2;
parameter SEQ = 3;
//hresp type;
parameter OKAY = 0;
parameter ERROR = 1;
parameter RETRY = 2;
parameter SPLIT = 3;
//hsize type;
parameter BIT8 = 0;
parameter BIT16 = 1;
parameter BIT32 = 2;
//input&output define;
input wire hclk;
input wire hrstn;
input wire hsel;
input wire [1:0] htrans;
input wire [2:0] hsize;
input wire [2:0] hburst;
input wire hwrite;
input wire [31:0] haddr;
input wire hready_in;
input wire [31:0] hwdata;
output wire hready_out;
output wire [1:0] hresp;
output wire [31:0] hrdata;
input wire [7:0] sram_q0;
input wire [7:0] sram_q1;
input wire [7:0] sram_q2;
input wire [7:0] sram_q3;
input wire [7:0] sram_q4;
input wire [7:0] sram_q5;
input wire [7:0] sram_q6;
input wire [7:0] sram_q7;
output wire [3:0] bank0_csn;
output wire [3:0] bank1_csn;
output wire sram_we;
output wire [12:0] sram_addr;
output wire [31:0] sram_wdata;
reg [1:0] htrans_r;
reg [2:0] hsize_r;
reg [2:0] hburst_r;
reg hwrite_r;
reg [31:0] haddr_r;
wire sram_write;
wire sram_read;
wire sram_we;
wire sram_en;
wire [15:0] sram_addr_64k;
wire bank_sel;
wire [1:0] sram_bist_sel;
wire [1:0] hsize_sel;
reg [3:0] sram_csn;
//ahb slave cmd input;
always @(posedge hclk or negedge hrstn) begin
if (!hrstn) begin
htrans_r <= 2'd0;
hsize_r <= 3'd0;
hburst_r <= 3'd0;
hwrite_r <= 1'b0;
haddr_r <= 32'd0;
end else if (hready_in & hsel) begin
htrans_r <= htrans;
hsize_r <= hsize;
hburst_r <= hburst;
hwrite_r <= hwrite;
haddr_r <= haddr;
end else begin
htrans_r <= 2'd0;
hsize_r <= 3'd0;
hburst_r <= 3'd0;
hwrite_r <= 1'b0;
haddr_r <= 32'd0;
end
end
//sram_we&sram_en;
assign sram_write = (((htrans_r == SEQ) || (htrans_r == NONSEQ)) && (hwrite_r)) ? 1'b1 : 1'b0;
assign sram_read = (((htrans_r == SEQ) || (htrans_r == NONSEQ)) && (!hwrite_r)) ? 1'b1 : 1'b0;
assign sram_we = sram_write;
assign sram_en = (sram_write | sram_read);
//haddr -> sram_addr;
assign sram_addr_64k = haddr_r[15:0];
assign sram_addr = haddr_r[14:2];
//bank sel & sram bist sel;
assign bank_sel = ((sram_en) && (!sram_addr_64k[15])) ? 1'b1 : 1'b0;
assign bank0_csn = ((sram_en) && (!sram_addr_64k[15])) ? sram_csn : 4'b1111;
assign bank1_csn = ((sram_en) && (sram_addr_64k[15])) ? sram_csn : 4'b1111;
assign sram_bist_sel = sram_addr_64k[1:0];
assign hsize_sel = hsize_r[1:0];
//hsize 8/16/32bit -> sram_csn;
always @(*) begin
if (hsize_sel == BIT32) begin
sram_csn = 4'b0000;
end else if (hsize_sel == BIT16) begin
if (sram_bist_sel[1]) begin //big_endian;
sram_csn = 4'b1100;
end else if (!sram_bist_sel[1]) begin
sram_csn = 4'b0011;
end
end else if (hsize_sel == BIT8) begin
case (sram_bist_sel)
2'b11: sram_csn = 4'b1110;
2'b10: sram_csn = 4'b1101;
2'b01: sram_csn = 4'b1011;
2'b00: sram_csn = 4'b0111;
default: sram_csn = 4'b1111;
endcase
end else begin
sram_csn = 4'b1111;
end
end
//data path;
assign sram_wdata = hwdata;
assign hrdata = (bank_sel)?{sram_q3, sram_q2, sram_q1, sram_q0}:{sram_q7, sram_q6, sram_q5, sram_q4};
//ahb cmd output;
assign hready_out = 1'b1; //no delay;
assign hresp = OKAY;
endmodule
| 6.722841 |
module AHB_SLAVE_INTERFACE (
hclk,
hresetn,
hwrite,
hreadyin,
htrans,
haddr,
hwdata,
valid,
haddr_1,
haddr_2,
hwdata_1,
hwdata_2,
temp_selx,
hwrite_reg
);
input hclk, hresetn, hreadyin, hwrite;
input [1:0] htrans;
input [31:0] haddr, hwdata;
output reg valid;
output reg hwrite_reg;
output reg [2:0] temp_selx;
output reg [31:0] hwdata_2, hwdata_1, haddr_2, haddr_1, haddr_3, hwdata_3;
parameter NONSEQ = 2'b10, SEQ = 2'b11;
// address decoding
always @(*) begin
if (haddr >= 32'h80000000 && haddr < 32'h84000000) temp_selx = 3'b001;
else if (haddr >= 32'h84000000 && haddr < 32'h88000000) temp_selx = 3'b010;
else if (haddr >= 32'h88000000 && haddr < 32'h8C000000) temp_selx = 3'b100;
end
//pipelining
always @(posedge hclk) begin
if (hresetn == 1'b1) begin
haddr_1 <= 32'h0;
haddr_2 <= 32'h0;
hwdata_1 <= 32'b0;
hwdata_2 <= 32'b0;
hwrite_reg <= 1'b0;
end else begin
haddr_1 <= haddr;
haddr_2 <= haddr_1;
hwdata_1 <= hwdata;
hwdata_2 <= hwdata_1;
hwrite_reg <= hwrite;
end
end
//generating the valid signal
always @(*) begin
valid = 1'b0;
if(hreadyin == 1'b1 && (htrans == NONSEQ || htrans == SEQ) && (haddr >= 32'h80000000 && haddr < 32'h8C000000))
valid = 1'b1;
end
endmodule
| 7.387726 |
module PREFIX_mem (
PORTS
);
parameter MEM_WORDS = EXPR((2 ^ ADDR_BITS) / (DATA_BITS / 8));
parameter ADDR_LSB = LOG2(EXPR(DATA_BITS / 8));
input clk;
input reset;
revport GROUP_STUB_MEM;
reg [ DATA_BITS-1:0] Mem [MEM_WORDS-1:0];
reg [ DATA_BITS-1:0] DOUT;
wire [ DATA_BITS-1:0] BitSEL;
wire [ADDR_BITS-1:ADDR_LSB] ADDR_WR_word = ADDR_WR[ADDR_BITS-1:ADDR_LSB];
wire [ADDR_BITS-1:ADDR_LSB] ADDR_RD_word = ADDR_RD[ADDR_BITS-1:ADDR_LSB];
assign BitSEL = {CONCAT({8{BSEL[BX]}},)};
always @(posedge clk)
if (WR)
Mem[ADDR_WR_word] <= #FFD(Mem[ADDR_WR_word] & ~BitSEL) | (DIN & BitSEL);
always @(posedge clk or posedge reset)
if (reset) DOUT <= #FFD{DATA_BITS{1'b0}};
else if (RD) DOUT <= #FFD Mem[ADDR_RD_word];
endmodule
| 6.889752 |
module AHB_Slave_no_map (
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire HWRITE,
input wire [31:0] HWDATA,
output wire [31:0] HRDATA,
output wire HREADYOUT
);
assign HREADYOUT = 1'b1;
assign HRDATA = 32'hzzzz_zzzz;
endmodule
| 7.527799 |
module ahb_slave_with_pcie_altpll_qsys_dffpipe_l2c (
clock,
clrn,
d,
q
) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dffe4a;
reg [0:0] dffe5a;
reg [0:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial dffe4a = 0;
// synopsys translate_on
always @(posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a <= {1{1'b1}};
else if (clrn == 1'b0) dffe4a <= 1'b0;
else if (ena == 1'b1) dffe4a <= (d & (~sclr));
// synopsys translate_off
initial dffe5a = 0;
// synopsys translate_on
always @(posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe5a <= {1{1'b1}};
else if (clrn == 1'b0) dffe5a <= 1'b0;
else if (ena == 1'b1) dffe5a <= (dffe4a & (~sclr));
// synopsys translate_off
initial dffe6a = 0;
// synopsys translate_on
always @(posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a <= {1{1'b1}};
else if (clrn == 1'b0) dffe6a <= 1'b0;
else if (ena == 1'b1) dffe6a <= (dffe5a & (~sclr));
assign ena = 1'b1, prn = 1'b1, q = dffe6a, sclr = 1'b0;
endmodule
| 7.051957 |
module ahb_slave_with_pcie_altpll_qsys_stdsync_sv6 (
clk,
din,
dout,
reset_n
) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
ahb_slave_with_pcie_altpll_qsys_dffpipe_l2c dffpipe3 (
.clock(clk),
.clrn(reset_n),
.d(din),
.q(wire_dffpipe3_q)
);
assign dout = wire_dffpipe3_q;
endmodule
| 7.051957 |
module ahb_slave_with_pcie_altpll_qsys (
address,
areset,
c0,
c1,
c2,
c3,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata
) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
output c1;
output c2;
output c3;
input clk;
output locked;
output phasedone;
input read;
output [31:0] readdata;
input reset;
input write;
input [31:0] writedata;
wire wire_stdsync2_dout;
wire [4:0] wire_sd1_clk;
wire wire_sd1_locked;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg pfdena_reg;
wire wire_pfdena_reg_ena;
reg prev_reset;
wire w_locked;
wire w_pfdena;
wire w_phasedone;
wire w_pll_areset_in;
wire w_reset;
wire w_select_control;
wire w_select_status;
ahb_slave_with_pcie_altpll_qsys_stdsync_sv6 stdsync2 (
.clk(clk),
.din(wire_sd1_locked),
.dout(wire_stdsync2_dout),
.reset_n((~reset))
);
ahb_slave_with_pcie_altpll_qsys_altpll_drn2 sd1 (
.areset((w_pll_areset_in | areset)),
.clk(wire_sd1_clk),
.inclk({{1{1'b0}}, clk}),
.locked(wire_sd1_locked)
);
// synopsys translate_off
initial pfdena_reg = {1{1'b1}};
// synopsys translate_on
always @(posedge clk or posedge reset)
if (reset == 1'b1) pfdena_reg <= {1{1'b1}};
else if (wire_pfdena_reg_ena == 1'b1) pfdena_reg <= writedata[1];
assign wire_pfdena_reg_ena = (write & w_select_control);
// synopsys translate_off
initial prev_reset = 0;
// synopsys translate_on
always @(posedge clk or posedge reset)
if (reset == 1'b1) prev_reset <= 1'b0;
else prev_reset <= w_reset;
assign c0 = wire_sd1_clk[0],
c1 = wire_sd1_clk[1],
c2 = wire_sd1_clk[2],
c3 = wire_sd1_clk[3],
locked = wire_sd1_locked,
phasedone = 1'b0,
readdata = {
{30{1'b0}},
(read & ((w_select_control & w_pfdena) | (w_select_status & w_phasedone))),
(read & ((w_select_control & w_pll_areset_in) | (w_select_status & w_locked)))
},
w_locked = wire_stdsync2_dout,
w_pfdena = pfdena_reg,
w_phasedone = 1'b1,
w_pll_areset_in = prev_reset,
w_reset = ((write & w_select_control) & writedata[0]),
w_select_control = ((~address[1]) & address[0]),
w_select_status = ((~address[1]) & (~address[0]));
endmodule
| 7.051957 |
module ahb_slave_with_pcie (
clk_clk,
reset_reset_n,
pcie_ip_reconfig_togxb_data,
pcie_ip_refclk_export,
pcie_ip_test_in_test_in,
pcie_ip_pcie_rstn_export,
pcie_ip_clocks_sim_clk250_export,
pcie_ip_clocks_sim_clk500_export,
pcie_ip_clocks_sim_clk125_export,
pcie_ip_reconfig_busy_busy_altgxb_reconfig,
pcie_ip_pipe_ext_pipe_mode,
pcie_ip_pipe_ext_phystatus_ext,
pcie_ip_pipe_ext_rate_ext,
pcie_ip_pipe_ext_powerdown_ext,
pcie_ip_pipe_ext_txdetectrx_ext,
pcie_ip_pipe_ext_rxelecidle0_ext,
pcie_ip_pipe_ext_rxdata0_ext,
pcie_ip_pipe_ext_rxstatus0_ext,
pcie_ip_pipe_ext_rxvalid0_ext,
pcie_ip_pipe_ext_rxdatak0_ext,
pcie_ip_pipe_ext_txdata0_ext,
pcie_ip_pipe_ext_txdatak0_ext,
pcie_ip_pipe_ext_rxpolarity0_ext,
pcie_ip_pipe_ext_txcompl0_ext,
pcie_ip_pipe_ext_txelecidle0_ext,
pcie_ip_rx_in_rx_datain_0,
pcie_ip_tx_out_tx_dataout_0,
pcie_ip_reconfig_fromgxb_0_data,
sdram_addr,
sdram_ba,
sdram_cas_n,
sdram_cke,
sdram_cs_n,
sdram_dq,
sdram_dqm,
sdram_ras_n,
sdram_we_n,
altpll_sdram_clk,
pcie_ip_powerdown_pll_powerdown,
pcie_ip_powerdown_gxb_powerdown
);
input clk_clk;
input reset_reset_n;
input [3:0] pcie_ip_reconfig_togxb_data;
input pcie_ip_refclk_export;
input [39:0] pcie_ip_test_in_test_in;
input pcie_ip_pcie_rstn_export;
output pcie_ip_clocks_sim_clk250_export;
output pcie_ip_clocks_sim_clk500_export;
output pcie_ip_clocks_sim_clk125_export;
input pcie_ip_reconfig_busy_busy_altgxb_reconfig;
input pcie_ip_pipe_ext_pipe_mode;
input pcie_ip_pipe_ext_phystatus_ext;
output pcie_ip_pipe_ext_rate_ext;
output [1:0] pcie_ip_pipe_ext_powerdown_ext;
output pcie_ip_pipe_ext_txdetectrx_ext;
input pcie_ip_pipe_ext_rxelecidle0_ext;
input [7:0] pcie_ip_pipe_ext_rxdata0_ext;
input [2:0] pcie_ip_pipe_ext_rxstatus0_ext;
input pcie_ip_pipe_ext_rxvalid0_ext;
input pcie_ip_pipe_ext_rxdatak0_ext;
output [7:0] pcie_ip_pipe_ext_txdata0_ext;
output pcie_ip_pipe_ext_txdatak0_ext;
output pcie_ip_pipe_ext_rxpolarity0_ext;
output pcie_ip_pipe_ext_txcompl0_ext;
output pcie_ip_pipe_ext_txelecidle0_ext;
input pcie_ip_rx_in_rx_datain_0;
output pcie_ip_tx_out_tx_dataout_0;
output [4:0] pcie_ip_reconfig_fromgxb_0_data;
output [11:0] sdram_addr;
output [1:0] sdram_ba;
output sdram_cas_n;
output sdram_cke;
output sdram_cs_n;
inout [31:0] sdram_dq;
output [3:0] sdram_dqm;
output sdram_ras_n;
output sdram_we_n;
output altpll_sdram_clk;
input pcie_ip_powerdown_pll_powerdown;
input pcie_ip_powerdown_gxb_powerdown;
endmodule
| 7.051957 |
module ahb_slave_with_pcie_sdram_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
);
output almost_empty;
output almost_full;
output empty;
output full;
output [60:0] rd_data;
input clk;
input rd;
input reset_n;
input wr;
input [60:0] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ 1:0] entries;
reg [60:0] entry_0;
reg [60:0] entry_1;
wire full;
reg rd_address;
reg [60:0] rd_data;
wire [ 1:0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == 2;
assign almost_full = entries >= 1;
assign empty = entries == 0;
assign almost_empty = entries <= 1;
always @(entry_0 or entry_1 or rd_address) begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full) begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty) begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk) begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule
| 7.051957 |
module ahb_slave_with_pcie_sgdma_m_readfifo_m_readfifo (
// inputs:
clk,
m_readfifo_data,
m_readfifo_rdreq,
m_readfifo_wrreq,
reset,
// outputs:
m_readfifo_empty,
m_readfifo_full,
m_readfifo_q,
m_readfifo_usedw
);
output m_readfifo_empty;
output m_readfifo_full;
output [68:0] m_readfifo_q;
output [4:0] m_readfifo_usedw;
input clk;
input [68:0] m_readfifo_data;
input m_readfifo_rdreq;
input m_readfifo_wrreq;
input reset;
wire m_readfifo_empty;
wire m_readfifo_full;
wire [68:0] m_readfifo_q;
wire [ 4:0] m_readfifo_usedw;
scfifo ahb_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo (
.aclr(reset),
.clock(clk),
.data(m_readfifo_data),
.empty(m_readfifo_empty),
.full(m_readfifo_full),
.q(m_readfifo_q),
.rdreq(m_readfifo_rdreq),
.usedw(m_readfifo_usedw),
.wrreq(m_readfifo_wrreq)
);
defparam ahb_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.add_ram_output_register =
"ON", ahb_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.intended_device_family =
"CYCLONEIVGX", ahb_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.lpm_numwords = 32,
ahb_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.lpm_showahead = "OFF",
ahb_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.lpm_type = "scfifo",
ahb_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.lpm_width = 69,
ahb_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.lpm_widthu = 5,
ahb_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.overflow_checking = "ON",
ahb_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.underflow_checking = "ON",
ahb_slave_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.use_eab = "ON";
endmodule
| 7.051957 |
module ahb_slave_with_pcie_sgdma_m_writefifo_m_writefifo (
// inputs:
clk,
m_writefifo_data,
m_writefifo_rdreq,
m_writefifo_wrreq,
reset,
// outputs:
m_writefifo_empty,
m_writefifo_full,
m_writefifo_q,
m_writefifo_usedw
);
output m_writefifo_empty;
output m_writefifo_full;
output [68:0] m_writefifo_q;
output [8:0] m_writefifo_usedw;
input clk;
input [68:0] m_writefifo_data;
input m_writefifo_rdreq;
input m_writefifo_wrreq;
input reset;
wire m_writefifo_empty;
wire m_writefifo_full;
wire [68:0] m_writefifo_q;
wire [ 8:0] m_writefifo_usedw;
scfifo ahb_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo (
.aclr(reset),
.clock(clk),
.data(m_writefifo_data),
.empty(m_writefifo_empty),
.full(m_writefifo_full),
.q(m_writefifo_q),
.rdreq(m_writefifo_rdreq),
.usedw(m_writefifo_usedw),
.wrreq(m_writefifo_wrreq)
);
defparam ahb_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.add_ram_output_register =
"ON", ahb_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.intended_device_family =
"CYCLONEIVGX", ahb_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.lpm_numwords =
512, ahb_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.lpm_showahead = "ON",
ahb_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.lpm_type = "scfifo",
ahb_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.lpm_width = 69,
ahb_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.lpm_widthu = 9,
ahb_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.overflow_checking = "ON",
ahb_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.underflow_checking = "ON",
ahb_slave_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.use_eab = "ON";
endmodule
| 7.051957 |
module ahb_slave_with_pcie_sgdma_command_fifo (
// inputs:
clk,
command_fifo_data,
command_fifo_rdreq,
command_fifo_wrreq,
reset,
// outputs:
command_fifo_empty,
command_fifo_full,
command_fifo_q
);
output command_fifo_empty;
output command_fifo_full;
output [103:0] command_fifo_q;
input clk;
input [103:0] command_fifo_data;
input command_fifo_rdreq;
input command_fifo_wrreq;
input reset;
wire command_fifo_empty;
wire command_fifo_full;
wire [103:0] command_fifo_q;
scfifo ahb_slave_with_pcie_sgdma_command_fifo_command_fifo (
.aclr(reset),
.clock(clk),
.data(command_fifo_data),
.empty(command_fifo_empty),
.full(command_fifo_full),
.q(command_fifo_q),
.rdreq(command_fifo_rdreq),
.wrreq(command_fifo_wrreq)
);
defparam ahb_slave_with_pcie_sgdma_command_fifo_command_fifo.add_ram_output_register = "ON",
ahb_slave_with_pcie_sgdma_command_fifo_command_fifo.intended_device_family = "CYCLONEIVGX",
ahb_slave_with_pcie_sgdma_command_fifo_command_fifo.lpm_numwords = 2,
ahb_slave_with_pcie_sgdma_command_fifo_command_fifo.lpm_showahead = "OFF",
ahb_slave_with_pcie_sgdma_command_fifo_command_fifo.lpm_type = "scfifo",
ahb_slave_with_pcie_sgdma_command_fifo_command_fifo.lpm_width = 104,
ahb_slave_with_pcie_sgdma_command_fifo_command_fifo.lpm_widthu = 1,
ahb_slave_with_pcie_sgdma_command_fifo_command_fifo.overflow_checking = "ON",
ahb_slave_with_pcie_sgdma_command_fifo_command_fifo.underflow_checking = "ON",
ahb_slave_with_pcie_sgdma_command_fifo_command_fifo.use_eab = "ON";
endmodule
| 7.051957 |
module ahb_slave_with_pcie_sgdma_desc_address_fifo (
// inputs:
clk,
desc_address_fifo_data,
desc_address_fifo_rdreq,
desc_address_fifo_wrreq,
reset,
// outputs:
desc_address_fifo_empty,
desc_address_fifo_full,
desc_address_fifo_q
);
output desc_address_fifo_empty;
output desc_address_fifo_full;
output [31:0] desc_address_fifo_q;
input clk;
input [31:0] desc_address_fifo_data;
input desc_address_fifo_rdreq;
input desc_address_fifo_wrreq;
input reset;
wire desc_address_fifo_empty;
wire desc_address_fifo_full;
wire [31:0] desc_address_fifo_q;
scfifo ahb_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo (
.aclr(reset),
.clock(clk),
.data(desc_address_fifo_data),
.empty(desc_address_fifo_empty),
.full(desc_address_fifo_full),
.q(desc_address_fifo_q),
.rdreq(desc_address_fifo_rdreq),
.wrreq(desc_address_fifo_wrreq)
);
defparam ahb_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.add_ram_output_register =
"ON", ahb_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.intended_device_family =
"CYCLONEIVGX", ahb_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.lpm_numwords = 2,
ahb_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.lpm_showahead = "OFF",
ahb_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.lpm_type = "scfifo",
ahb_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.lpm_width = 32,
ahb_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.lpm_widthu = 1,
ahb_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.overflow_checking = "ON",
ahb_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.underflow_checking = "ON",
ahb_slave_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.use_eab = "OFF";
endmodule
| 7.051957 |
module ahb_slave_with_pcie_sgdma_status_token_fifo (
// inputs:
clk,
reset,
status_token_fifo_data,
status_token_fifo_rdreq,
status_token_fifo_wrreq,
// outputs:
status_token_fifo_empty,
status_token_fifo_full,
status_token_fifo_q
);
output status_token_fifo_empty;
output status_token_fifo_full;
output [23:0] status_token_fifo_q;
input clk;
input reset;
input [23:0] status_token_fifo_data;
input status_token_fifo_rdreq;
input status_token_fifo_wrreq;
wire status_token_fifo_empty;
wire status_token_fifo_full;
wire [23:0] status_token_fifo_q;
scfifo ahb_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo (
.aclr(reset),
.clock(clk),
.data(status_token_fifo_data),
.empty(status_token_fifo_empty),
.full(status_token_fifo_full),
.q(status_token_fifo_q),
.rdreq(status_token_fifo_rdreq),
.wrreq(status_token_fifo_wrreq)
);
defparam ahb_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo.add_ram_output_register =
"ON", ahb_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo.intended_device_family =
"CYCLONEIVGX", ahb_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo.lpm_numwords = 2,
ahb_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo.lpm_showahead = "OFF",
ahb_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo.lpm_type = "scfifo",
ahb_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo.lpm_width = 24,
ahb_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo.lpm_widthu = 1,
ahb_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo.overflow_checking = "ON",
ahb_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo.underflow_checking = "ON",
ahb_slave_with_pcie_sgdma_status_token_fifo_status_token_fifo.use_eab = "ON";
endmodule
| 7.051957 |
module ahb_spi (
input HCLK,
input HRESETn,
input [31:0] HADDR,
input [31:0] HWDATA,
input HWRITE,
input HSEL,
output reg [31:0] HRDATA,
input SPI_MISO,
output SPI_MOSI,
output SPI_SCLK,
output reg SPI_SS
);
localparam START_REG_ADDR = 8'h0;
localparam SS_REG_ADDR = 8'h4;
localparam READY_REG_ADDR = 8'h8;
localparam DATA_REG_ADDR = 8'h12;
reg [7:0] data_buf_w;
wire [7:0] data_buf_r;
reg ss_flag;
reg start_flag;
wire ready_flag;
spi_master_driver spi (
.clk_i(HCLK),
.rst_i(~HRESETn),
.start_i(start_flag),
.data_in_bi(data_buf_w),
.busy_o(ready_flag),
.data_out_bo(data_buf_r),
.spi_miso_i(SPI_MISO),
.spi_mosi_o(SPI_MOSI),
.spi_sclk_o(SPI_SCLK),
.spi_cs_i (ss_flag)
);
// AHB bus adapter
reg [11:0] HADDR_dly;
reg HWRITE_dly;
reg HSEL_dly;
always @(posedge HCLK) begin
HADDR_dly <= HADDR[11:0];
HWRITE_dly <= HWRITE;
HSEL_dly <= HSEL;
end
wire [11:0] reg_addr = HADDR_dly;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) begin
data_buf_w <= 8'b0;
start_flag <= 1'b0;
ss_flag <= 1'b1;
end else begin
if (HSEL_dly) begin
// Bus interface logic, write operation
if (HWRITE_dly) begin
case (reg_addr)
DATA_REG_ADDR: data_buf_w <= HWDATA[7:0];
START_REG_ADDR: start_flag <= HWDATA[0];
SS_REG_ADDR: ss_flag <= HWDATA[0];
default:; /* READY_REG_ADDR: do nothing */
endcase
end
// Reset start flag automatically after one tick
if (!(HWRITE_dly && reg_addr == START_REG_ADDR)) begin
start_flag <= 1'b0;
end
end
end
end
// Bus interface logic, data for read operation
always @(*) begin
SPI_SS = ss_flag;
case (reg_addr)
READY_REG_ADDR: HRDATA = ~ready_flag;
DATA_REG_ADDR: HRDATA = data_buf_r;
default: HRDATA = 32'b0;
endcase
end
endmodule
| 8.133474 |
module SPM (
clk,
rst,
x,
y,
p
);
parameter size = 32;
input clk, rst;
input y;
input [size-1:0] x;
output p;
wire [size-1:1] pp;
wire [size-1:0] xy;
genvar i;
CSADD csa0 (
.clk(clk),
.rst(rst),
.x (x[0] & y),
.y (pp[1]),
.sum(p)
);
generate
for (i = 1; i < size - 1; i = i + 1) begin
CSADD csa (
.clk(clk),
.rst(rst),
.x (x[i] & y),
.y (pp[i+1]),
.sum(pp[i])
);
end
endgenerate
TCMP tcmp (
.clk(clk),
.rst(rst),
.a (x[size-1] & y),
.s (pp[size-1])
);
endmodule
| 7.252231 |
module AHB_SPM #(
parameter SIZE = 32
) (
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire HREADY,
input wire [ 1:0] HTRANS,
input wire [ 2:0] HSIZE,
input wire HWRITE,
input wire [31:0] HADDR,
input wire [31:0] HWDATA,
output wire HREADYOUT,
output wire [ 1:0] HRESP,
output wire [31:0] HRDATA
);
localparam X_OFF = 0, Y_OFF = 4, P1_OFF = 8, P2_OFF = 12;
localparam S0 = 0, S1 = 1, S2 = 2, S3 = 3;
reg [7:0] AHB_ADDR;
wire ahb_access = HTRANS[1] & HSEL & HREADY;
wire _ahb_write_ = ahb_access & HWRITE;
wire ahb_read = ahb_access & (~HWRITE);
reg AHB_WRITE;
reg AHB_READ;
wire p;
reg [31:0] X, Y, P0, P1;
reg [7:0] CNT, ncnt;
reg [3:0] STATE, nstate;
always @(posedge HCLK or negedge HRESETn)
if (~HRESETn) begin
AHB_WRITE <= 1'b0;
AHB_READ <= 1'b0;
AHB_ADDR <= 8'b0;
end else begin
AHB_WRITE <= _ahb_write_;
AHB_READ <= ahb_read;
AHB_ADDR <= HADDR[7:0];
end
always @(posedge HCLK or negedge HRESETn)
if (~HRESETn) X <= 32'b0;
else if (AHB_WRITE && (AHB_ADDR == X_OFF)) X <= HWDATA;
always @(posedge HCLK or negedge HRESETn)
if (~HRESETn) Y <= 32'b0;
else if (AHB_WRITE && (AHB_ADDR == Y_OFF)) Y <= HWDATA;
else if (STATE == S1) Y <= Y >> 1;
always @(posedge HCLK or negedge HRESETn)
if (~HRESETn) P0 <= 32'b0;
else if (STATE == S1) P0 <= {p, P0[31:1]};
always @(posedge HCLK or negedge HRESETn)
if (~HRESETn) STATE <= S0;
else STATE <= nstate;
always @*
case (STATE)
S0: if (AHB_WRITE && (AHB_ADDR == Y_OFF)) nstate = S1;
else nstate = S0;
S1: if (CNT == 31) nstate = S0;
else nstate = S1;
endcase
always @(posedge HCLK or negedge HRESETn)
if (~HRESETn) CNT <= 8'd0;
else CNT <= ncnt;
always @* begin
ncnt = 0;
if (CNT == 31) ncnt <= 0;
else if (STATE == S1) ncnt = CNT + 1;
end
SPM spm (
.clk(~HCLK),
.rst(~HRESETn),
.x (X),
.y (Y[0]),
.p (p)
);
assign HREADYOUT = (STATE == S0);
assign HRDATA = P0;
endmodule
| 7.425783 |
module SPM_EXT (
clk,
rst,
X,
Y,
P,
start,
done
);
parameter size = 32;
input clk, rst;
input [size-1:0] X, Y;
output reg [size-1:0] P;
output done;
input start;
reg [31:0] Y_reg;
wire p, y;
assign y = Y_reg[0];
reg [1:0] done_state, done_state_next;
assign done = done_state[1];
SPM spm (
.clk(clk),
.rst(rst),
.x (X),
.y (y),
.p (p)
);
reg [7:0] count;
always @(posedge clk or posedge rst)
if (rst) count <= 7'd0;
else if (start) count <= count + 1'd1;
else if (done) count <= 7'd0;
always @(posedge clk)
if (count == 0 && start == 1) P <= 64'b0;
else if (!done) P <= {p, P[31:1]};
always @(posedge clk or posedge rst)
if (rst) Y_reg <= 0;
else if (count == 0 && start == 1) Y_reg <= Y;
else if (!done) Y_reg <= (Y_reg >> 1);
always @(posedge clk or posedge rst)
if (rst) done_state <= 2'd00;
else done_state <= done_state_next;
always @* begin
done_state_next = done_state;
case (done_state)
2'b00: if (start) done_state_next = 2'b01;
2'b01: if (count == 8'd33) done_state_next = 2'b10;
2'b10: done_state_next = 2'b11;
2'b11: done_state_next = 2'b00;
default: done_state_next = done_state;
endcase
end
//else if(count==7'd33) done <= 1;
//else if(start) done <= 0;
endmodule
| 7.738787 |
module spm_tb;
reg clk, rst, start;
wire p;
wire done;
initial begin
rst = 0;
clk = 0;
start = 0;
#100;
rst = 1;
#500;
rst = 0;
#1000;
@(posedge clk);
start = 1;
@(posedge done);
start = 0;
end
always #10 clk = ~clk;
initial begin
$dumpfile("spm.vcd");
$dumpvars(0);
#100_000;
$display("Timeout -- Exiting");
$finish;
end
wire [31:0] P;
SPM_EXT spm_dut (
.clk(clk),
.rst(rst),
.X(-15),
.Y(20),
.P(P),
.start(start),
.done(done)
);
endmodule
| 6.53398 |
module ahb_srom_ctrl (
//Ahb clock & reset
clk,
rst_n,
//Ahb slave interface
rom_shready_in,
rom_shsel,
rom_shaddr,
rom_shtrans,
rom_shwrite,
rom_shwdata,
rom_shsize,
rom_shburst,
rom_shprot,
rom_shrdata,
rom_shready_out,
rom_shresp,
//Inner srom interface
romcs_n,
romaddr,
romdout
);
//-----------------------------------------------------------//
// PARAMETERS //
//-----------------------------------------------------------//
//-----------------------------------------------------------//
// INPUTS/OUTPUTS //
//-----------------------------------------------------------//
input clk;
input rst_n;
input rom_shready_in;
input rom_shsel;
input [31:0] rom_shaddr;
input [1:0] rom_shtrans;
input rom_shwrite;
input [31:0] rom_shwdata;
input [2:0] rom_shsize;
input [2:0] rom_shburst;
input [3:0] rom_shprot;
output [31:0] rom_shrdata;
output rom_shready_out;
output rom_shresp;
output romcs_n;
output [31:0] romaddr;
input [31:0] romdout;
//-----------------------------------------------------------//
// REGISTERS & WIRES //
//-----------------------------------------------------------//
reg [31:0] rom_shrdata;
wire rom_shready_out;
wire rom_shresp;
wire romcs_n;
wire [31:0] romaddr;
//-----------------------------------------------------------//
// ARCHITECTURE //
//-----------------------------------------------------------//
//This design only valid for 0 waitstate synchronous ROM.
//wire rom_range = (rom_shaddr[31:29] == 3'b000) ? 1'b1 : 1'b0;
wire rom_ahb_rd = rom_shready_in & rom_shsel & rom_shtrans[1] & ~rom_shwrite; //& rom_range;
assign romcs_n = ~rom_ahb_rd;
assign romaddr = rom_shaddr;
assign rom_shready_out = 1'b1;
assign rom_shresp = 1'b0;
reg [1:0] romaddr_1_0_reg;
reg [2:0] rom_shsize_reg;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
romaddr_1_0_reg <= 2'h0;
rom_shsize_reg <= 3'h0;
end else if (rom_ahb_rd) begin
romaddr_1_0_reg <= romaddr[1:0];
rom_shsize_reg <= rom_shsize;
end
end
//byte enable for little endian
always @* begin
case ({
romaddr_1_0_reg, rom_shsize_reg
})
5'b00000: rom_shrdata = {4{romdout[7:0]}};
5'b00001: rom_shrdata = {2{romdout[15:0]}};
5'b00010: rom_shrdata = romdout;
5'b01000: rom_shrdata = {4{romdout[15:8]}};
5'b10000: rom_shrdata = {4{romdout[23:16]}};
5'b10001: rom_shrdata = {2{romdout[31:16]}};
5'b11000: rom_shrdata = {4{romdout[31:24]}};
default: rom_shrdata = romdout; //all other cases are unexpected.
endcase
end
endmodule
| 6.957815 |
module AHB_UART (
// --------------------------
// Input pins: AHB signals //
// --------------------------
// Select
input HSEL,
// Address and control
input [31:0] HADDR,
input HWRITE,
input [1:0] HTRANS,
input [2:0] HSIZE,
input [2:0] HBURST,
// Data in
input [31:0] HWDATA,
// Reset and clock
input HRESETn,
input HCLK,
input HMASTLOCK,
// --------------
// Output pins //
// --------------
// Transfer responses
output HREADY,
output [1:0] HRESP,
// Data out
output [31:0] HRDATA,
input UART_Rx,
output UART_Tx,
output [7:0] UART_INT
);
//This module will IGNORE all width requests, only providing 32bit data
wire BaudL, BaudOut, TINT, RINT, RxError, TxBusy;
reg [31:0] UART_CFG; //module enable, int enable,fifo enable&sel
reg [15:0] UART_DIV;
wire [31:0] UART_STAT;
reg [7:0] TxReg;
reg HWI;
reg [3:0] WADDR;
wire [7:0] TxDat;
wire [7:0] RxReg;
wire [7:0] TFIFOO;
wire TBUFE, RBUFF; //Send Buffer Full/ Receive Buffer Empty
assign RBUFF = 0;
reg send, TFIFOHS, TFIFOWR;
assign UART_INT = ({TBUFE, RBUFF, RxError, TINT, RINT} & UART_CFG[31:24]);
assign UART_STAT = {TBUFE, RBUFF, TxBusy, RxError, RINT, TINT};
assign TxDat = (UART_CFG[4]) ? TFIFOO : TxReg;
assign HRDATA=
(({32{HADDR[6:2]==5'h00}}&UART_CFG)|
({32{HADDR[6:2]==5'h01}}&UART_DIV)|
({32{HADDR[6:2]==5'h02}}&({24'b0,RxReg}))|
({32{HADDR[6:2]==5'h03}}&UART_STAT)|
32'h00000000);
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
UART_CFG <= 0;
UART_DIV <= 0;
HWI <= 0;
WADDR <= 0;
send <= 1'b0;
TFIFOHS <= 1'b0;
end else begin
if (HWRITE) begin
HWI <= HSEL;
WADDR <= HADDR[6:2];
if (UART_CFG[4] & HSEL & HADDR[6:2] == 5'h02) TFIFOWR <= 1'b1;
end else begin
HWI <= 1'b0;
TFIFOWR <= 1'b0;
end
if (HWI)
case (WADDR)
4'h0: UART_CFG <= HWDATA;
4'h1: UART_DIV <= HWDATA[15:0];
4'h2: begin
if (!UART_CFG[4]) begin
send <= 1'b1;
TxReg <= HWDATA[7:0];
end
end
endcase
else begin
if (TxBusy) send <= 1'b0;
else if ((!TBUFE) & UART_CFG[4]) send <= 1;
else send <= 0;
end
TFIFOHS = (UART_CFG[4]) ? TINT : 1'b0;
end
end
BaudGen UBG1 (
.clkdivL(UART_DIV[15:0]),
.en(UART_CFG[7]),
.clk(HCLK),
.rst(~HRESETn),
.BaudOut(BaudOut),
.BaudOutL(BaudL)
);
UART_Tx UTX1 (
.clk(BaudL),
.rst(~HRESETn),
.en(UART_CFG[2]),
.ChkEn(UART_CFG[0]),
.send(send),
.dat(TxDat),
.busy(TxBusy),
.TINT(TINT),
.TxD(UART_Tx)
);
UART_Rx URX1 (
.clk(BaudOut),
.rst(~HRESETn),
.en(UART_CFG[1]),
.ChkEn(UART_CFG[0]),
.RxD(UART_Rx),
.dat(RxReg),
.ERR(RxError),
.INT(RINT)
);
SyncFIFO TFIFO1 (
.clk(HCLK),
.rst_n(HRESETn),
.wr_en(TFIFOWR),
.rd_en({TFIFOHS, TINT} == 2'b01),
.data_in(HWDATA),
.data_out(TFIFOO),
.empty(TBUFE)
);
assign HRESP = 0;
assign HREADY = 1;
endmodule
| 7.69443 |
module AHB_MASTER (
input wire HCLK,
input wire HRESETn,
output wire [31:0] HADDR,
output wire [ 1:0] HTRANS,
output wire [ 2:0] HSIZE,
output wire HWRITE,
output wire [31:0] HWDATA,
input wire HREADY,
input wire [31:0] HRDATA,
input wire wr,
input wire rd,
output wire done,
output wire busy,
input wire [31:0] addr,
input wire [31:0] wdata,
output wire [31:0] rdata
);
localparam
ST_IDLE = 3'd0,
ST_RWAIT = 3'd1,
ST_WWAIT = 3'd2,
ST_RADDR = 3'd3,
ST_RDATA = 3'd4,
ST_WADDR = 3'd5,
ST_WDATA = 3'd6;
reg [2:0] state, nstate;
always @(posedge HCLK or negedge HRESETn)
if (!HRESETn) state <= ST_IDLE;
else state <= nstate;
always @*
case (state)
ST_IDLE: begin
nstate = ST_IDLE;
if (HREADY & rd) nstate = ST_RADDR;
else if (HREADY & wr) nstate = ST_WADDR;
else if (~HREADY & rd) nstate = ST_RWAIT;
else if (~HREADY & wr) nstate = ST_WWAIT;
end
ST_RWAIT: if (HREADY) nstate = ST_RADDR;
else nstate = ST_RWAIT;
ST_WWAIT: if (HREADY) nstate = ST_WADDR;
else nstate = ST_WWAIT;
ST_RADDR: if (HREADY) nstate = ST_RDATA;
else nstate = ST_RADDR;
ST_RDATA: nstate = ST_IDLE;
ST_WADDR:
if (HREADY) nstate = ST_WDATA;
else nstate = ST_WADDR;
ST_WDATA: nstate = ST_IDLE;
default: nstate = ST_IDLE;
endcase
assign done = (state == ST_RDATA) || (state == ST_WDATA);
assign busy = (state != ST_IDLE);
assign HADDR = addr;
assign HWRITE = (state == ST_WADDR);
assign HWDATA = wdata;
assign HTRANS = ((state == ST_WADDR) || (state == ST_RADDR)) ? 2'b10 : 2'b00;
assign HSIZE = 3'b010;
assign rdata = HRDATA;
endmodule
| 8.575682 |
module BAUDGEN (
input wire clk,
input wire rst_n,
input wire [15:0] prescale,
input wire en,
output wire baudtick
);
reg [15:0] count_reg;
wire [15:0] count_next;
//Counter
always @(posedge clk, negedge rst_n) begin
if (!rst_n) count_reg <= 0;
else if (en) count_reg <= count_next;
end
assign count_next = ((count_reg == prescale) ? 0 : count_reg + 1'b1);
assign baudtick = ((count_reg == prescale) ? 1'b1 : 1'b0);
endmodule
| 7.312347 |
module UART_RX (
input wire clk,
input wire resetn,
input wire b_tick, //Baud generator tick
input wire rx, //RS-232 data port
output reg rx_done, //transfer completed
output wire [7:0] dout //output data
);
//STATE DEFINES
localparam [1:0] idle_st = 2'b00;
localparam [1:0] start_st = 2'b01;
localparam [1:0] data_st = 2'b11;
localparam [1:0] stop_st = 2'b10;
//Internal Signals
reg [1:0] current_state;
reg [1:0] next_state;
reg [3:0] b_reg; //baud-rate/over sampling counter
reg [3:0] b_next;
reg [2:0] count_reg; //data-bit counter
reg [2:0] count_next;
reg [7:0] data_reg; //data register
reg [7:0] data_next;
//State Machine
always @(posedge clk, negedge resetn) begin
if (!resetn) begin
current_state <= idle_st;
b_reg <= 0;
count_reg <= 0;
data_reg <= 0;
end else begin
current_state <= next_state;
b_reg <= b_next;
count_reg <= count_next;
data_reg <= data_next;
end
end
//Next State Logic
always @* begin
next_state = current_state;
b_next = b_reg;
count_next = count_reg;
data_next = data_reg;
rx_done = 1'b0;
case (current_state)
idle_st:
if (~rx) begin
next_state = start_st;
b_next = 0;
end
start_st:
if (b_tick)
if (b_reg == 7) begin
next_state = data_st;
b_next = 0;
count_next = 0;
end else b_next = b_reg + 1'b1;
data_st:
if (b_tick)
if (b_reg == 15) begin
b_next = 0;
data_next = {rx, data_reg[7:1]};
if (count_next == 7) // 8 Data bits
next_state = stop_st;
else count_next = count_reg + 1'b1;
end else b_next = b_reg + 1;
stop_st:
if (b_tick)
if(b_reg == 15) //One stop bit
begin
next_state = idle_st;
rx_done = 1'b1;
end else b_next = b_reg + 1;
endcase
end
assign dout = data_reg;
endmodule
| 7.513316 |
module UART_TX (
input wire clk,
input wire resetn,
input wire tx_start,
input wire b_tick, //baud rate tick
input wire [7:0] d_in, //input data
output reg tx_done, //transfer finished
output wire tx //output data to RS-232
);
//STATE DEFINES
localparam [1:0] idle_st = 2'b00;
localparam [1:0] start_st = 2'b01;
localparam [1:0] data_st = 2'b11;
localparam [1:0] stop_st = 2'b10;
//Internal Signals
reg [1:0] current_state;
reg [1:0] next_state;
reg [3:0] b_reg; //baud tick counter
reg [3:0] b_next;
reg [2:0] count_reg; //data bit counter
reg [2:0] count_next;
reg [7:0] data_reg; //data register
reg [7:0] data_next;
reg tx_reg; //output data reg
reg tx_next;
//State Machine
always @(posedge clk, negedge resetn) begin
if (!resetn) begin
current_state <= idle_st;
b_reg <= 0;
count_reg <= 0;
data_reg <= 0;
tx_reg <= 1'b1;
end else begin
current_state <= next_state;
b_reg <= b_next;
count_reg <= count_next;
data_reg <= data_next;
tx_reg <= tx_next;
end
end
//Next State Logic
always @* begin
next_state = current_state;
tx_done = 1'b0;
b_next = b_reg;
count_next = count_reg;
data_next = data_reg;
tx_next = tx_reg;
case (current_state)
idle_st: begin
tx_next = 1'b1;
if (tx_start) begin
next_state = start_st;
b_next = 0;
data_next = d_in;
end
end
start_st: //send start bit
begin
tx_next = 1'b0;
if (b_tick)
if (b_reg == 15) begin
next_state = data_st;
b_next = 0;
count_next = 0;
end else b_next = b_reg + 1;
end
data_st: //send data serially
begin
tx_next = data_reg[0];
if (b_tick)
if (b_reg == 15) begin
b_next = 0;
data_next = data_reg >> 1;
if (count_reg == 7) //8 data bits
next_state = stop_st;
else count_next = count_reg + 1;
end else b_next = b_reg + 1;
end
stop_st: //send stop bit
begin
tx_next = 1'b1;
if (b_tick)
if(b_reg == 15) //one stop bit
begin
next_state = idle_st;
tx_done = 1'b1;
end else b_next = b_reg + 1;
end
endcase
end
assign tx = tx_reg;
endmodule
| 7.089095 |
module UART_MON #(
parameter BITTIME = 813.8
) (
input RX
);
reg [7:0] data;
integer i;
initial begin
forever begin
@(negedge RX);
#BITTIME;
for (i = 0; i < 8; i = i + 1) begin
data = {RX, data[7:1]};
#BITTIME;
end
#BITTIME;
// Enable one of the following lines to display the monitored data
//$write("%c", data);
$display("0x%X", data);
end
end
endmodule
| 7.02112 |
module APB_UART_WRAP (
// APB SLAVE PORT INTERFACE
input PCLK,
input PRESETn,
input [`APB_ADDR_WIDTH-1:0] PADDR,
input PWRITE,
input PSEL,
input PENABLE,
input [`APB_DATA_WIDTH-1:0] PWDATA,
output [`APB_DATA_WIDTH-1:0] PRDATA,
output PREADY,
//Interrupt
output wire UART_INT,
// UART signals
output TxD,
`ifdef USE_FUNC_MODEM
input RxD,
output rts_pad_o,
input cts_pad_i,
output dtr_pad_o,
input dsr_pad_i,
input ri_pad_i,
input dcd_pad_i
`else
input RxD
`endif
);
uart_top WB_UART (
.wb_clk_i(PCLK),
.wb_rst_i(!PRESETn),
.wb_adr_i(PADDR[7:3]),
.wb_dat_i({24'b0, PWDATA}),
.wb_dat_o(PRDATA),
.wb_we_i(PWRITE),
.wb_stb_i(PENABLE),
.wb_cyc_i(PSEL),
.wb_ack_o(PREADY),
.wb_sel_i({4{PSEL}}),
.int_o(UART_INT), // interrupt request
// UART signals
// serial input/output
.stx_pad_o(TxD),
.srx_pad_i(RxD),
// modem signals
`ifdef USE_FUNC_MODEM
.rts_pad_o(rts_pad_o),
.cts_pad_i(cts_pad_i),
.dtr_pad_o(dtr_pad_o),
.dsr_pad_i(dsr_pad_i),
.ri_pad_i (ri_pad_i),
.dcd_pad_i(dcd_pad_i)
`else
.cts_pad_i(1'b0),
.dsr_pad_i(1'b0),
.ri_pad_i (1'b1),
.dcd_pad_i(1'b0)
`endif
);
endmodule
| 7.375981 |
module AHB_XIP_TB ();
wire [3:0] XPIi, XPIo, XPIdir, XPI;
wire XPICS, XPICLK;
reg SysRST;
wire SysRST_N;
reg HCLK;
wire [35:0] HADDR;
wire HWRITE, HMASTLOCK;
wire [63:0] HWDATA;
wire [2:0] HSIZE;
wire [2:0] HBURST;
wire [3:0] HPROT;
wire [1:0] HTRANS;
//Master side ports (MUXed)
wire [63:0] HRDATAM;
wire HREADYM;
wire HRESPM;
//AHB Periheral select
reg HSEL;
wire [63:0] HRDATA;
wire HREADY;
wire HRESP;
//Initialization and stimulation source block
initial begin
#0 HCLK = 0;
SysRST = 1;
#10 SysRST = 0;
end
assign SysRST_N = !SysRST;
always #5 HCLK = ~HCLK;
//SRAM-like read request gen
reg rreq; //请求读一次
reg rbreq; //请求读一行
reg [3:0] rsize;
reg [63:0] raddr; //
wire [63:0] rbdata;
wire [10:0] rlen;
wire rbdo; //cache写
wire rrdy; //传输完成
wire berr; //访问失败
genvar i;
reg dice1;
reg [23:0] dice2;
reg [1:0] dice3;
initial begin
HSEL <= 1'b1;
end
always @(posedge HCLK or posedge SysRST) begin
if (rrdy | SysRST) begin
dice1 <= $random;
dice2 <= $random;
dice3 <= $random;
if (dice1) begin
rbreq <= 1'b1;
rreq <= 1'b0;
raddr <= {48'b0, dice2[23:3], 3'b000};
rsize <= 3'b011;
end else begin
rbreq <= 1'b1;
rreq <= 1'b0;
raddr <= {48'b0, dice2[23:3], 3'b000};
rsize <= dice3;
end
end
end
cache_bus_unit TSG (
.clk(HCLK),
.rst(SysRST),
.write_through_req(1'b0), //请求写穿
.read_req(rreq), //请求读一次
.read_line_req(rbreq), //请求读一行
.size(rsize),
.pa(raddr), //
.wt_data(64'b0),
.line_data(rbdata),
.addr_count(rlen),
.line_write(rbdo), //cache写
.cache_entry_write(), //更新缓存entry
.trans_rdy(rrdy), //传输完成
.bus_error(berr), //访问失败
//AHB总线
//ahb
//ahb
.haddr(HADDR),
.hwrite(HWRITE),
.hsize(HSIZE),
.hburst(HBURST),
.hprot(HPROT),
.htrans(HTRANS),
.hmastlock(HMASTLOCK),
.hwdata(HWDATA),
.hready(HREADYM),
.hresp(HRESPM),
.hreset_n(SysRST_N),
.hrdata(HRDATA),
.bus_ack(1'b0), //总线允许使用
.bus_req() //总线请求使用
);
//wire [3:0]XPIo;
//wire [3:0]XPIi;
//wire [3:0]XPIdir;
assign XPIi = XPI;
generate
for (i = 0; i <= 3; i = i + 1) begin : XPIioctrl
assign XPI[i] = XPIdir[i] ? XPIo[i] : 1'bz;
pullup (XPI[i]);
end
endgenerate
AHB_XIP DUT (
.HSEL(HSEL),
.HADDR(HADDR),
.HWRITE(HWRITE),
.HTRANS(HTRANS),
.HSIZE(HSIZE),
.HBURST(HBURST),
.HWDATA(HWDATA),
.HRESETn(SysRST_N),
.HCLK(HCLK),
.HMASTLOCK(HMASTLOCK),
.HREADY(HREADYM),
.HRESP(HRESPM),
.HRDATA(HRDATA),
.XPIo(XPIo),
.XPIi(XPIi),
.XPIdir(XPIdir),
.XPICS(XPICS),
.XPICLK(XPICLK)
);
W25Q128JVxIM DEVICE1 (
.CSn(XPICS),
.CLK(XPICLK),
.DIO(XPI[0]),
.DO(XPI[1]),
.WPn(XPI[2]),
.HOLDn(XPI[3])
);
endmodule
| 6.542492 |
module AHHRE_10bit (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
// Generate pp
// Radix 4 pp
wire [16:0] pp_rad4_0;
wire [16:0] pp_rad4_1;
wire [16:0] pp_rad4_2;
wire [ 3:0] sign_factor;
rad4_gen rad4_gen1 (
.x1(x[15:10]),
.y(y),
.pp_rad4_0(pp_rad4_0),
.pp_rad4_1(pp_rad4_1),
.pp_rad4_2(pp_rad4_2),
.sign_factor(sign_factor[3:1])
);
// Radix 1024 pp
wire [24:0] PP_o;
app_rad1024 rad1024_gen_v1 (
.x0(x[9:0]),
.y(y),
.PP_o(PP_o),
.sign_factor(sign_factor[0])
);
// Tree
pp_tree_ahhre wallace_tree (
.pp_rad4_0(pp_rad4_0),
.pp_rad4_1(pp_rad4_1),
.pp_rad4_2(pp_rad4_2),
.pp_rad1024(PP_o),
.sign_factor(sign_factor),
.p(p)
);
endmodule
| 7.49107 |
module code (
one,
two,
sign,
y2,
y1,
y0
);
input y2, y1, y0;
output one, two, sign;
wire [1:0] k;
xor x1 (one, y0, y1);
xor x2 (k[1], y2, y1);
not n1 (k[0], one);
and a1 (two, k[0], k[1]);
assign sign = y2;
endmodule
| 6.869541 |
module rad4_gen (
x1,
y,
pp_rad4_0,
pp_rad4_1,
pp_rad4_2,
sign_factor
);
// inputs
// y multiplicand
// x multipland
// P1,P2,P3 partial products
input [15:0] y;
input [5:0] x1;
// output
output [16:0] pp_rad4_0;
output [16:0] pp_rad4_1;
output [16:0] pp_rad4_2;
output [2:0] sign_factor;
wire [2:0] one, two, sign;
code code0 (
one[0],
two[0],
sign[0],
x1[1],
x1[0],
1'b0
);
genvar j;
generate
for (j = 1; j < 3; j = j + 1) begin : pp_code
code code_gen (
one[j],
two[j],
sign[j],
x1[2*j+1],
x1[2*j],
x1[2*j-1]
);
end
endgenerate
wire [16:0] tmp1_pp;
assign tmp1_pp = {y[15], y}; // This variable is introduced because pp has 17 bits
// first pp generation
wire [17:0] out1;
assign out1[0] = sign[0];
genvar i;
generate
for (i = 0; i < 17; i = i + 1) begin : pp_rad4_first
product pp_pr (
tmp1_pp[i],
out1[i],
one[0],
two[0],
sign[0],
pp_rad4_0[i],
out1[i+1]
);
end
endgenerate
// second pp generation
wire [17:0] out2;
assign out2[0] = sign[1];
genvar i2;
generate
for (i2 = 0; i2 < 17; i2 = i2 + 1) begin : pp_second
product pp_pr (
tmp1_pp[i2],
out2[i2],
one[1],
two[1],
sign[1],
pp_rad4_1[i2],
out2[i2+1]
);
end
endgenerate
// third pp generation
wire [17:0] out3;
assign out3[0] = sign[2];
genvar i3;
generate
for (i3 = 0; i3 < 17; i3 = i3 + 1) begin : pp_third
product pp_pr (
tmp1_pp[i3],
out3[i3],
one[2],
two[2],
sign[2],
pp_rad4_2[i3],
out3[i3+1]
);
end
endgenerate
genvar i_sign;
generate
for (i_sign = 0; i_sign < 3; i_sign = i_sign + 1) begin : sgn_fac
sgn_gen sgn_genXX (
one[i_sign],
two[i_sign],
sign[i_sign],
sign_factor[i_sign]
);
end
endgenerate
endmodule
| 6.951944 |
module product (
x1,
x0,
one,
two,
sign,
p,
i
);
input x1, x0, sign, one, two;
output p, i;
wire [1:0] k;
xor xo1 (i, x1, sign);
and a1 (k[1], i, one);
and a0 (k[0], x0, two);
or o1 (p, k[1], k[0]);
endmodule
| 6.586499 |
module rad1024_unit (
input sign,
input [3:0] enc_vec,
input [3:0] a_vec,
output pp_i
);
// sign change
wire [3:0] a_sign;
assign a_sign[3] = sign ^ a_vec[3];
assign a_sign[2] = sign ^ a_vec[2];
assign a_sign[1] = sign ^ a_vec[1];
assign a_sign[0] = sign ^ a_vec[0];
// enc and a_sign
wire [3:0] a_enc;
assign a_enc = a_sign & enc_vec;
// pp_i
assign pp_i = (a_enc[3] | a_enc[2] | a_enc[1] | a_enc[0]);
endmodule
| 6.522902 |
module HAd (
a,
b,
c,
s
);
input a, b;
output c, s;
xor x1 (s, a, b);
and a1 (c, a, b);
endmodule
| 7.388692 |
module FAd (
a,
b,
c,
cy,
sm
);
input a, b, c;
output cy, sm;
wire x, y, z;
xor x1 (x, a, b);
xor x2 (sm, x, c);
and a1 (y, a, b);
and a2 (z, x, c);
or o1 (cy, y, z);
endmodule
| 7.593245 |
module gray (
input Clk,
input Reset,
input En,
output reg [2:0] Output,
output reg Overflow
);
initial begin
Output = 0;
Overflow = 0;
end
always @(posedge Clk) begin
if (Reset) begin
Output <= 0;
Overflow <= 0;
end else begin
if (En) begin
case (Output)
2'b000: Output = 2'b001;
2'b001: Output = 2'b011;
2'b011: Output = 2'b010;
2'b010: Output = 2'b110;
2'b110: Output = 2'b111;
2'b111: Output = 2'b101;
2'b101: Output = 2'b100;
2'b100: begin
Output = 2'b000;
Overflow = 1;
end
endcase
end
end
end
endmodule
| 6.553837 |
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