code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module ahb_adapter (
/*autoport*/
//output
rddata,
stall,
AHB_haddr,
AHB_hburst,
AHB_hprot,
AHB_hready_in,
AHB_hsize,
AHB_htrans,
AHB_hwdata,
AHB_hwrite,
AHB_sel,
triple_byte_w,
//input
clk,
rst_n,
dataenable,
rd,
wr,
address,
wrdat... | 8.262102 |
module ahb_addr_decode (
// System Address
input wire [31:0] haddr,
// Memory Selection
output wire ram_hsel,
// PIO Selection
output wire pio_hsel,
// Peripheral Selection
output wire apbsys_hsel
);
assign ram_hsel = (haddr[31:16]==16'h1000); // 0x10000000
assign pio_hsel ... | 6.706724 |
module AHB_APB_BRIDGE #(
parameter SLOW_PCLK = 1
) (
input wire HCLK,
input wire HRESETn,
// AHB Slave Port
`AHB_SLAVE_IFC,
// APB Master Port
output wire PCLK,
output wire PRESETn,
input wire PCLKEN,
`APB_MASTER_IFC
);
localparam ST_IDLE = 3'h0, ST_WAIT = 3'h1, ST_SETUP =... | 8.45554 |
module AHB_ARB_RB #(
parameter MASTERS = 8,
MASTERS_BIT = $clog2(MASTERS)
) (
input wire [MASTERS-1:0] RB_REQ,
input wire [MASTERS_BIT-1:0] RB_POINTER,
output reg [MASTERS-1:0] RB_GRANT
);
//----------------
// Request Mask
//----------------
wire [MASTERS-1:0] rb_mask;
wire [MASTERS-1:0]... | 6.818939 |
module ahb_arbiter (
input wire HCLK,
input wire HRESETn,
//Master0
input wire HBUSREQ_M0,
input wire HLOCK_M0,
input wire [`AHB_ADDR_WIDTH - 1 : 0] HADDR_M0,
input wire [1:0] HTRANS_M0,
input wire HWRITE_M0,
input wire [`AHB_DATA_WIDTH - 1 : 0] HWDATA_M0,
output reg HGRANT_M0... | 7.239759 |
module ahb_arbiter_m2 #(
parameter P_NUM = 2
) // the number of masters
(
input wire HRESETn
, input wire HCLK
, input wire HREADY
, input wire HBUSREQ_0
, input wire HBUSREQ_1
, output wire HGRANT_0
, output wire HGRANT_1
, output re... | 8.187108 |
module ahb_arbiter_m3 (
HRESETn,
HCLK,
HREADY,
HBUSREQ_0,
HBUSREQ_1,
HBUSREQ_2,
HGRANT_0,
HGRANT_1,
HGRANT_2,
HMASTER
);
parameter P_NUM = 3; // the number of masters
input HRESETn;
wire HRESETn;
input HCLK;
wire HCLK;
input HREADY;
wire HREADY;
input HBUSREQ_0;
... | 8.187108 |
module ahb_async_sram #(
parameter W_DATA = 32,
parameter W_ADDR = 32,
parameter DEPTH = 1 << 11,
parameter W_SRAM_ADDR = $clog2(DEPTH) // Let this default
) (
// Globals
input wire clk,
input wire rst_n,
// AHB lite slave interface
output wire ahbls_hready_resp,
i... | 8.946783 |
module ahb_async_sram_halfwidth #(
parameter W_DATA = 32,
parameter W_ADDR = 32,
parameter DEPTH = 1 << 11,
parameter W_SRAM_ADDR = $clog2(DEPTH), // Let this default
parameter W_SRAM_DATA = W_DATA / 2 // Let this default
) (
// Globals
input wire clk,
input wire rst_n,
// AHB l... | 8.946783 |
module ahb_bus_decoder (
input wire [`WORD_WIDTH - 1 : 0] HADDR,
output wire HSEL_1, // clint
output wire HSEL_2, // plic
output wire HSEL_3, // uart0
output wire HSEL_4 // spi0
);
assign HSEL_1 = (HADDR... | 7.058028 |
module ahb_bus_matrix
(
// X signals from masters
// We support 3 master and 1 dummy master
input HBUSREQx0;
input HBUSREQx1;
input HBUSREQx2;
input HBUSREQx3;
input HLOCKx0;
input HLOCKx1;
input HLOCKx2;
input HLOCKx3;
input [1:0] HTRANSx0;
input [1:0] HTRANSx1;
input [1:0] HTRANSx2;
inpu... | 8.368121 |
module AHB_CCREG (
// --------------------------
// Input pins: AHB signals //
// --------------------------
// Select
input HSEL,
// Address and control
input [31:0] HADDR,
input HWRITE,
input [1:0] HTRANS,
input [2:0] HSIZE,
input [2:0] HBURST,
// Data in
input [31:... | 6.746145 |
module ahb_crypto_core_top (
haddr,
hclk,
hprot,
hrdata,
hready,
hresp,
hrst_b,
hsel,
hsize,
htrans,
hwdata,
hwrite,
RSA_Interrupt,
AES_Interrupt,
SHA_Interrupt
);
input [31:0] haddr;
input hclk;
output hready;
input hrst_b;
input hsel;
input [31... | 6.614733 |
module ahb_ctrl (
input HCLK_I,
input HRESET_N_I,
input HREADY_I,
input HSEL_I,
input [ 2:0] HSIZE_I,
input HWRITE_I,
input [11:0] HADDR_I,
input [31:0] HRDATA_I,
output [31:0] HWDATA_O,
output HRESP_O,
output HREADY_O
);
assign HR... | 6.660538 |
module ahb_ctrl_top (
//ahb input signals;
hclk,
hrstn,
hsel,
htrans,
hsize,
hburst,
hwrite,
haddr,
hready_in,
hwdata,
//ahb output signals;
hready_out,
hresp,
hrdata
);
//input&output define;
input wire hclk;
input wire hrstn;
input wire hsel;
inp... | 6.639144 |
module AHB_DDRAM
(
// --------------------------
// Input pins: AHB signals //
// --------------------------
// Select
input HSEL,
// Address and control
input [31:0] HADDR,
input HWRITE,
input [1:0] HTRANS,
input [2:0] HSIZE,
input [2:0] HBURST,
// Data in
input [31:0] HWDATA,
// Reset and ... | 7.52822 |
module ahb_decoder (
// -------------
// Input pins //
// -------------
input [35:0] HADDR,
// --------------
// Output pins //
// --------------
output HSELx0,
output HSELx7,
output HSELx1,
output HSELx2,
output HSELx3,
output HSELx4,
output HSELx5,
output HS... | 6.790525 |
module ahb_default_slave (
// Split-capable bits
input [3:0] HMASTER,
input HMASTLOCK,
output reg [15:0] HSPLIT,
// -------------
// Input pins //
// -------------
// Select bit
input HSEL,
// Address and control
input [31:0] HADDR,
input HWRITE,
input [1:0] HTRANS,
... | 6.712259 |
module AHB_DUMMY (
// --------------------------
// Input pins: AHB signals //
// --------------------------
// Select
input HSEL,
// Address and control
input [35:0] HADDR,
input HWRITE,
input [1:0] HTRANS,
input [2:0] HSIZE,
input [2:0] HBURST,
// Data in
input [63:... | 6.904052 |
module ahb_dummy_master (
// Arbiter grant
input HGRANT,
// Transfer responses
input HREADY,
input [1:0] HRESP,
// Reset
input HRESETn,
// Clock
input HCLK,
// Data input
input [31:0] HRDATA,
// To arbiter: HLOCK always LOW
// There's no need for dummy master to acti... | 8.22269 |
module AHB_ESRAM (
// --------------------------
// Input pins: AHB signals //
// --------------------------
// Select
input HSEL,
// Address and control
input [35:0] HADDR,
input HWRITE,
input [1:0] HTRANS,
input [2:0] HSIZE,
input [2:0] HBURST,
// Data in
input [63:... | 8.643082 |
module ahb_feeder (
input HCLK,
output reg HRESETn,
output [31:0] HADDR,
output [ 2:0] HBURST,
output HMASTLOCK,
output [ 3:0] HPROT,
output [ 2:0] HSIZE,
output [ 1:0] HTRANS,
output [31:0] HWDATA,
output HWRITE,
... | 7.667659 |
module AHB_FLASH_CTRL #(
parameter LINE_SIZE = 128,
NUM_LINES = 32
) (
input HCLK,
input HRESETn,
// AHB-Lite Slave Interface
`AHB_SLAVE_IFC,
// External Interface to Quad I/O
output sck,
output ce_n,
input wire [3:0] din,
output wire [3:0] dout,
... | 7.672362 |
module AHB_FLASH_CACHE_CTRL #(
parameter LINE_SIZE = 128,
NUM_LINES = 32
) (
// AHB-Lite Slave Interface
input HCLK,
input HRESETn,
input HSEL,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire HWRITE,
input wire ... | 8.259905 |
module FLASH_READER #(
parameter LINE_SIZE = 128
) (
input wire clk,
input wire rst_n,
input wire [ 23:0] addr,
input wire rd,
output wire done,
output wire [LINE_SIZE-1:0] line,
output reg sck,
outpu... | 7.838383 |
module DMC #(
parameter LINE_SIZE = 128,
NUM_LINES = 32
) (
input wire clk,
input wire rst_n,
//
input wire [ 23:0] A,
input wire [ 23:0] A_h,
output wire [ 31:0] Do,
output wire hit,
//
input wire ... | 7.065437 |
module AHB_FLASH_CTRL_TB;
reg HCLK;
reg HRESETn;
wire HREADY;
reg HWRITE;
reg [2:0] HSIZE;
reg [1:0] HTRANS;
reg [31:0] HADDR, HWDATA;
wire [31:0] HRDATA;
wire [ 3:0] fdi;
wire [ 3:0] fdo;
wire [ 3:0] fdio;
wire [ 3:0] fdoe;
wire fsclk;
wire fcen;... | 7.672362 |
module AHB_FLASH_WRITER (
input wire HCLK,
input wire HRESETn,
// AHB-Lite Slave Interface
// `AHB_SLAVE_IFC(),
input wire HSEL,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire HWRITE,
input wire HREADY,
input wire [31:0] HWDATA,
inpu... | 6.895298 |
module AHB_FSB16 (
//ahb 接口
input wire hclk,
input wire hreset_n,
input wire hsel,
input wire [2:0] hsize,
input wire [1:0] htrans,
input wire hwrite,
input wire [31:0] haddr, //本桥只占用地址的低32位空间
input wire [63:0] hwdata,
output wire [63:0] hrdata,
output wire hresp,
outpu... | 9.121818 |
module sm_gpio (
//bus side
input clk,
input rst_n,
input bSel,
input [31:0] bAddr,
input bWrite,
input [31:0] bWData,
output reg [31:0] bRData,
//pin side
input [`SM_GPIO_WIDTH - 1:0] gpioInput,
output [`SM_GPIO_WID... | 6.836966 |
module AHB_LED #(
parameter LED_WIDTH = 32,
parameter CFG_WIDTH = 32,
parameter SAT_WIDTH = 32
) (
input HCLK,
input HRESETn,
input [`ADDR_WIDTH+1:2] HADDR,
input HSEL,
input HWRITE,
inpu... | 7.033608 |
module ahb_lite_cordic (
//ABB-Lite side
//Select
input HSEL,
//Global signals
input HCLK,
input HRESETn,
//Address and control
input [31 : 0] HADDR,
input [ 2 : 0] HBURST, //ignored
input HMASTLOCK, // ignored
input [ 3 : 0] HPROT, ... | 8.564912 |
module fir_filter (
clk,
n_reset,
sample_data,
fir_coefficient,
load_coeff,
data_ready,
one_k_samples,
modwait,
fir_out,
err
);
input [15:0] sample_data;
input [15:0] fir_coefficient;
output [15:0] fir_out;
input clk, n_reset, load_coeff, data_ready;
output one_k_sample... | 6.553796 |
module ahb_lite_fir_filter (
clk,
n_rst,
hsel,
haddr,
hsize,
htrans,
hwrite,
hwdata,
hrdata,
hresp
);
input [3:0] haddr;
input [1:0] htrans;
input [15:0] hwdata;
output [15:0] hrdata;
input clk, n_rst, hsel, hsize, hwrite;
output hresp;
wire data_ready, new_coeff_se... | 7.092286 |
module ahb_lite_mem #(
parameter ADDR_WIDTH = 6,
parameter DELAY_VAL = 2
) (
//ABB-Lite side
input HCLK,
input HRESETn,
input [31:0] HADDR,
input [ 2:0] HBURST,
input HMASTLOCK, // ignored
input [ 3:0] HPROT, // ignored
in... | 7.336072 |
module ahb_lite_s3 #(
parameter P_HSEL0_START = 16'h0000,
P_HSEL0_SIZE = 16'h0100,
P_HSEL1_START = 16'h1000,
P_HSEL1_SIZE = 16'h0100,
P_HSEL2_START = 16'h2000,
P_HSEL2_SIZE = 16'h0100
) (
input wire HRESETn
, input wire HCLK
, input wire [31:0] M_HADDR
, input ... | 6.875631 |
module ahb_lite_uart16550 (
//ABB-Lite side
input HCLK,
input HRESETn,
input [31 : 0] HADDR,
input [ 2 : 0] HBURST,
input HMASTLOCK, // ignored
input [ 3 : 0] HPROT, // ignored
input HSEL,
input [ 2 : 0... | 7.902328 |
module ahb_m2s_m2 #(
parameter NUM_MASTER = 3
) (
input wire HRESETn
, input wire HCLK
, input wire HREADY
, input wire [ 3:0] HMASTER
, output reg [31:0] HADDR
, output reg [ 3:0] HPROT
, output reg [ 1:0] HTRANS
, output reg HWRITE
, output... | 6.552353 |
module ahb_master (
hclk,
hresetn,
hrdata,
hresp,
hready_out,
hwrite,
hready_in,
htrans,
haddr,
hwdata
);
input hclk, hresetn, hready_out;
input [1:0] hresp;
input [31:0] hrdata;
output reg hwrite, hready_in;
output reg [1:0] htrans;
output reg [31:0] haddr, hwdata;
... | 7.377627 |
module ahb_master_slave_with_pcie_altpll_qsys_dffpipe_l2c (
clock,
clrn,
d,
q
) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
/... | 6.966859 |
module ahb_master_slave_with_pcie_altpll_qsys_stdsync_sv6 (
clk,
din,
dout,
reset_n
) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
ahb_master_slave_with_pcie_altpll_qsys_dffpipe_l2c dffpipe3 (
.clock(clk),
... | 6.966859 |
module ahb_master_slave_with_pcie_altpll_qsys (
address,
areset,
c0,
c1,
c2,
c3,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata
) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
output c1;
output c2;
... | 6.966859 |
module ahb_master_slave_with_pcie (
clk_clk,
reset_reset_n,
pcie_ip_reconfig_togxb_data,
pcie_ip_refclk_export,
pcie_ip_test_in_test_in,
pcie_ip_pcie_rstn_export,
pcie_ip_clocks_sim_clk250_export,
pcie_ip_clocks_sim_clk500_export,
pcie_ip_clocks_sim_clk125_export,
pcie_ip_reconfi... | 6.966859 |
module ahb_master_slave_with_pcie_sdram_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
);
output almost_empty;
output almost_full;
output empty;
output full;
output [60:0] rd_data;
i... | 6.966859 |
module ahb_master_slave_with_pcie_sgdma_m_readfifo_m_readfifo (
// inputs:
clk,
m_readfifo_data,
m_readfifo_rdreq,
m_readfifo_wrreq,
reset,
// outputs:
m_readfifo_empty,
m_readfifo_full,
m_readfifo_q,
m_readfifo_usedw
);
output m_readfifo_empty;
output m_readfifo_full;
... | 6.966859 |
module ahb_master_slave_with_pcie_sgdma_m_writefifo_m_writefifo (
// inputs:
clk,
m_writefifo_data,
m_writefifo_rdreq,
m_writefifo_wrreq,
reset,
// outputs:
m_writefifo_empty,
m_writefifo_full,
m_writefifo_q,
m_writefifo_usedw
);
output m_writefifo_empty;
output m_write... | 6.966859 |
module ahb_master_slave_with_pcie_sgdma_command_fifo (
// inputs:
clk,
command_fifo_data,
command_fifo_rdreq,
command_fifo_wrreq,
reset,
// outputs:
command_fifo_empty,
command_fifo_full,
command_fifo_q
);
output command_fifo_empty;
output command_fifo_full;
output [103:0... | 6.966859 |
module ahb_master_slave_with_pcie_sgdma_desc_address_fifo (
// inputs:
clk,
desc_address_fifo_data,
desc_address_fifo_rdreq,
desc_address_fifo_wrreq,
reset,
// outputs:
desc_address_fifo_empty,
desc_address_fifo_full,
desc_address_fifo_q
);
output desc_address_fifo_empty;
o... | 6.966859 |
module ahb_master_slave_with_pcie_sgdma_status_token_fifo (
// inputs:
clk,
reset,
status_token_fifo_data,
status_token_fifo_rdreq,
status_token_fifo_wrreq,
// outputs:
status_token_fifo_empty,
status_token_fifo_full,
status_token_fifo_q
);
output status_token_fifo_empty;
o... | 6.966859 |
module ahb_master_slave_with_qsys_bfm (
clk_clk,
reset_reset_n,
ahb_master_slave_2_0_conduit_end_add_data_sel,
ahb_master_slave_2_0_conduit_end_display_data,
ahb_master_slave_2_0_conduit_end_rdwr_address
);
input clk_clk;
input reset_reset_n;
input ahb_master_slave_2_0_conduit_end_add_data_se... | 6.966859 |
module ahb_decoder (
input [ 31:0] HADDR,
output [`DEVICE_COUNT - 1:0] HSEL
);
wire [31:0] addr = HADDR;
assign HSEL[0] = `SM_MEM_AHB_RAM;
assign HSEL[1] = `SM_MEM_AHB_GPIO;
assign HSEL[2] = 1'b0; // some new peripheral stub
endmodule
| 6.790525 |
module ahb_response_mux (
input [`DEVICE_COUNT - 1:0] HSEL_R,
// Verilog doesn't allow an I/O port to be a 2D array.
// We can do it with some macros, but
// it will be too hard to read this code in this case
input [ 31:0] RDATA_0,
input [ 31:0] RDATA_1,
input [ ... | 7.178886 |
module PREFIX_bus(PORTS);
input clk;
input reset;
port MMX_GROUP_AHB;
revport SSX_GROUP_AHB;
input SSX_MMX;
input SSX_MMX_resp;
parameter BUS_WIDTH = GO... | 6.505295 |
module PREFIX_hlast (PORTS);
input clk;
input reset;
input [1:0] MMX_HTRANS;
input MMX_HREADY;
input [2:0] MMX_HBURST;
output MMX_HLAST;
parameter TRANS_IDLE = 2'b00;
parameter ... | 6.832833 |
module AHB_MFSPM (
// --------------------------
// Input pins: AHB signals //
// --------------------------
// Select
input HSEL,
// Address and control
input [35:0] HADDR,
input HWRITE,
input [1:0] HTRANS,
input [2:0] HSIZE,
input [2:0] HBURST,
// Data in
input [63:... | 6.775234 |
module AHB_MUX_2M1S #(
parameter SZ = 64
) (
input wire HCLK,
input wire HRESETn,
// Port 1
input wire [ 31:0] HADDR_M1,
input wire [ 1:0] HTRANS_M1,
input wire HWRITE_M1,
input wire [ 2:0] HSIZE_M1,
input wire [SZ-1:0] HWDATA_M1,
output wire HREADY_M... | 6.814989 |
module ahb_mux_m2s (
// -------------
// Input pins //
// -------------
// Master 0
// Address and control
input [31:0] HADDRx0,
input HWRITEx0,
input [1:0] HTRANSx0,
input [2:0] HSIZEx0,
input [2:0] HBURSTx0,
// Write data
input [31:0] HWDATAx0,
// Master 1 (default... | 9.192769 |
module ahb_mux_s2m (
// -------------
// Input pins //
// -------------
// Clock and reset
input HCLK,
input HRESETn,
// Slave datas
input [63:0] HRDATAx0,
input [63:0] HRDATAx7,
input [63:0] HRDATAx1,
input [63:0] HRDATAx2,
input [63:0] HRDATAx3,
input [63:0] HRDATAx... | 7.254809 |
module AHB_OCRAM (
// --------------------------
// Input pins: AHB signals //
// --------------------------
// Select
input HSEL,
// Address and control
input [31:0] HADDR,
input HWRITE,
input [1:0] HTRANS,
input [2:0] HSIZE,
input [2:0] HBURST,
// Data in
input [31:... | 7.580484 |
module apb_pio (
// --------------------------------------------------------------------------
// Port Definitions
// --------------------------------------------------------------------------
input wire HCLK, // Clock
input wire HRESETn, // Reset
// Port1 RW
input wire HSEL, /... | 6.562932 |
module ahb_ram #(
parameter WIDTH = 6 // memory internal bus width (determines RAM size)
) (
input HCLK,
input HRESETn,
input HSEL,
input HWRITE,
input HREADY,
input [ 1:0] HTRANS,
input [31:0] HADDR,
output [31:0] HRDATA,
input [31:0] ... | 9.169843 |
module is based on a state machine that is used to
// detect the external reset being asserted, and is used to generate the
// system reset output.
//
// The HRESETn is asynchronously asserted(LOW) and always deasserted on
// posedge HCLK.
//
// Copyright (C) 2015 Lianghao Yuan
// This program is free softwar... | 8.355054 |
module AHB_ROM (
// --------------------------
// Input pins: AHB signals //
// --------------------------
// Select
input HSEL,
// Address and control
input [35:0] HADDR,
input HWRITE,
input [1:0] HTRANS,
input [2:0] HSIZE,
input [2:0] HBURST,
// Data in
input [63:0]... | 7.094237 |
module AHB_SDIO (
input HSEL,
// Address and control
input [35:0] HADDR,
input HWRITE,
input [1:0] HTRANS,
input [2:0] HSIZE,
input [2:0] HBURST,
// Data in
input [63:0] HWDATA,
// Reset and clock
input HRESETn,
input HCLK,
input HMASTLOCK,
// --------------
/... | 6.619654 |
module ahb_slave_inf (
//ahb input signals;
hclk,
hrstn,
hsel,
htrans,
hsize,
hburst,
hwrite,
haddr,
hready_in,
hwdata,
//ahb output signals;
hready_out,
hresp,
hrdata,
//sram_core output signals;
sram_q0,
sram_q1,
sram_q2,
sram_q3,
s... | 6.722841 |
module AHB_SLAVE_INTERFACE (
hclk,
hresetn,
hwrite,
hreadyin,
htrans,
haddr,
hwdata,
valid,
haddr_1,
haddr_2,
hwdata_1,
hwdata_2,
temp_selx,
hwrite_reg
);
input hclk, hresetn, hreadyin, hwrite;
input [1:0] htrans;
input [31:0] haddr, hwdata;
output reg v... | 7.387726 |
module PREFIX_mem (
PORTS
);
parameter MEM_WORDS = EXPR((2 ^ ADDR_BITS) / (DATA_BITS / 8));
parameter ADDR_LSB = LOG2(EXPR(DATA_BITS / 8));
input clk;
input reset;
revport GROUP_STUB_MEM;
reg [ DATA_BITS-1:0] Mem [MEM_WORDS-1:0... | 6.889752 |
module AHB_Slave_no_map (
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire HWRITE,
input wire [31:0] HWDATA,
output wire [31:0] HRDATA,
output wire HREADYOUT
);
assign HREADYOUT = 1'b1;
assign HRDATA = 32'hzzzz_zzzz;
endmodule
| 7.527799 |
module ahb_slave_with_pcie_altpll_qsys_dffpipe_l2c (
clock,
clrn,
d,
q
) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synop... | 7.051957 |
module ahb_slave_with_pcie_altpll_qsys_stdsync_sv6 (
clk,
din,
dout,
reset_n
) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
ahb_slave_with_pcie_altpll_qsys_dffpipe_l2c dffpipe3 (
.clock(clk),
.clrn(reset_n)... | 7.051957 |
module ahb_slave_with_pcie_altpll_qsys (
address,
areset,
c0,
c1,
c2,
c3,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata
) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
output c1;
output c2;
outpu... | 7.051957 |
module ahb_slave_with_pcie (
clk_clk,
reset_reset_n,
pcie_ip_reconfig_togxb_data,
pcie_ip_refclk_export,
pcie_ip_test_in_test_in,
pcie_ip_pcie_rstn_export,
pcie_ip_clocks_sim_clk250_export,
pcie_ip_clocks_sim_clk500_export,
pcie_ip_clocks_sim_clk125_export,
pcie_ip_reconfig_busy_... | 7.051957 |
module ahb_slave_with_pcie_sdram_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
);
output almost_empty;
output almost_full;
output empty;
output full;
output [60:0] rd_data;
input cl... | 7.051957 |
module ahb_slave_with_pcie_sgdma_m_readfifo_m_readfifo (
// inputs:
clk,
m_readfifo_data,
m_readfifo_rdreq,
m_readfifo_wrreq,
reset,
// outputs:
m_readfifo_empty,
m_readfifo_full,
m_readfifo_q,
m_readfifo_usedw
);
output m_readfifo_empty;
output m_readfifo_full;
outpu... | 7.051957 |
module ahb_slave_with_pcie_sgdma_m_writefifo_m_writefifo (
// inputs:
clk,
m_writefifo_data,
m_writefifo_rdreq,
m_writefifo_wrreq,
reset,
// outputs:
m_writefifo_empty,
m_writefifo_full,
m_writefifo_q,
m_writefifo_usedw
);
output m_writefifo_empty;
output m_writefifo_fu... | 7.051957 |
module ahb_slave_with_pcie_sgdma_command_fifo (
// inputs:
clk,
command_fifo_data,
command_fifo_rdreq,
command_fifo_wrreq,
reset,
// outputs:
command_fifo_empty,
command_fifo_full,
command_fifo_q
);
output command_fifo_empty;
output command_fifo_full;
output [103:0] comma... | 7.051957 |
module ahb_slave_with_pcie_sgdma_desc_address_fifo (
// inputs:
clk,
desc_address_fifo_data,
desc_address_fifo_rdreq,
desc_address_fifo_wrreq,
reset,
// outputs:
desc_address_fifo_empty,
desc_address_fifo_full,
desc_address_fifo_q
);
output desc_address_fifo_empty;
output d... | 7.051957 |
module ahb_slave_with_pcie_sgdma_status_token_fifo (
// inputs:
clk,
reset,
status_token_fifo_data,
status_token_fifo_rdreq,
status_token_fifo_wrreq,
// outputs:
status_token_fifo_empty,
status_token_fifo_full,
status_token_fifo_q
);
output status_token_fifo_empty;
output s... | 7.051957 |
module ahb_spi (
input HCLK,
input HRESETn,
input [31:0] HADDR,
input [31:0] HWDATA,
input HWRITE,
input HSEL,
output reg [31:0] HRDATA,
input SPI_MISO,
output SPI_MOSI,
output SPI_SCLK,
output reg SPI_SS... | 8.133474 |
module SPM (
clk,
rst,
x,
y,
p
);
parameter size = 32;
input clk, rst;
input y;
input [size-1:0] x;
output p;
wire [size-1:1] pp;
wire [size-1:0] xy;
genvar i;
CSADD csa0 (
.clk(clk),
.rst(rst),
.x (x[0] & y),
.y (pp[1]),
.sum(p)
);
generate
... | 7.252231 |
module AHB_SPM #(
parameter SIZE = 32
) (
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire HREADY,
input wire [ 1:0] HTRANS,
input wire [ 2:0] HSIZE,
input wire HWRITE,
input wire [31:0] HADDR,
input wire [31:0] HWDATA,
... | 7.425783 |
module SPM_EXT (
clk,
rst,
X,
Y,
P,
start,
done
);
parameter size = 32;
input clk, rst;
input [size-1:0] X, Y;
output reg [size-1:0] P;
output done;
input start;
reg [31:0] Y_reg;
wire p, y;
assign y = Y_reg[0];
reg [1:0] done_state, done_state_next;
assign done = don... | 7.738787 |
module spm_tb;
reg clk, rst, start;
wire p;
wire done;
initial begin
rst = 0;
clk = 0;
start = 0;
#100;
rst = 1;
#500;
rst = 0;
#1000;
@(posedge clk);
start = 1;
@(posedge done);
start = 0;
end
always #10 clk = ~clk;
initial begin
$dumpfile("sp... | 6.53398 |
module ahb_srom_ctrl (
//Ahb clock & reset
clk,
rst_n,
//Ahb slave interface
rom_shready_in,
rom_shsel,
rom_shaddr,
rom_shtrans,
rom_shwrite,
rom_shwdata,
rom_shsize,
rom_shburst,
rom_shprot,
rom_shrdata,
rom_shready_out,
rom_shresp,
//Inner srom int... | 6.957815 |
module AHB_UART (
// --------------------------
// Input pins: AHB signals //
// --------------------------
// Select
input HSEL,
// Address and control
input [31:0] HADDR,
input HWRITE,
input [1:0] HTRANS,
input [2:0] HSIZE,
input [2:0] HBURST,
// Data in
input [31:0... | 7.69443 |
module AHB_MASTER (
input wire HCLK,
input wire HRESETn,
output wire [31:0] HADDR,
output wire [ 1:0] HTRANS,
output wire [ 2:0] HSIZE,
output wire HWRITE,
output wire [31:0] HWDATA,
input wire HREADY,
input wire [31:0] HRDATA,
input wire wr,
input ... | 8.575682 |
module BAUDGEN (
input wire clk,
input wire rst_n,
input wire [15:0] prescale,
input wire en,
output wire baudtick
);
reg [15:0] count_reg;
wire [15:0] count_next;
//Counter
always @(posedge clk, negedge rst_n) begin
if (!rst_n) count_reg <= 0;
else if (en) count_reg <= count_next... | 7.312347 |
module UART_RX (
input wire clk,
input wire resetn,
input wire b_tick, //Baud generator tick
input wire rx, //RS-232 data port
output reg rx_done, //transfer completed
output wire [7:0] dout //output data
);
//STATE DEFINES
localparam [1:0] idle_st = 2'b00;
localpara... | 7.513316 |
module UART_TX (
input wire clk,
input wire resetn,
input wire tx_start,
input wire b_tick, //baud rate tick
input wire [7:0] d_in, //input data
output reg tx_done, //transfer finished
output wire tx //output data to RS-232
);
//... | 7.089095 |
module UART_MON #(
parameter BITTIME = 813.8
) (
input RX
);
reg [7:0] data;
integer i;
initial begin
forever begin
@(negedge RX);
#BITTIME;
for (i = 0; i < 8; i = i + 1) begin
data = {RX, data[7:1]};
#BITTIME;
end
#BITTIME;
// Enable one of the foll... | 7.02112 |
module APB_UART_WRAP (
// APB SLAVE PORT INTERFACE
input PCLK,
input PRESETn,
input [`APB_ADDR_WIDTH-1:0] PADDR,
input PWRITE,
input PSEL,
input ... | 7.375981 |
module AHB_XIP_TB ();
wire [3:0] XPIi, XPIo, XPIdir, XPI;
wire XPICS, XPICLK;
reg SysRST;
wire SysRST_N;
reg HCLK;
wire [35:0] HADDR;
wire HWRITE, HMASTLOCK;
wire [63:0] HWDATA;
wire [2:0] HSIZE;
wire [2:0] HBURST;
wire [3:0] HPROT;
wire [1:0] HTRANS;
//Master side ports (MUXed)
wire [63:0... | 6.542492 |
module AHHRE_10bit (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
// Generate pp
// Radix 4 pp
wire [16:0] pp_rad4_0;
wire [16:0] pp_rad4_1;
wire [16:0] pp_rad4_2;
wire [ 3:0] sign_factor;
rad4_gen rad4_gen1 (
.x1(x[15:10]),
.y(y),
.pp_rad4_0(pp_rad4_0),
.pp... | 7.49107 |
module code (
one,
two,
sign,
y2,
y1,
y0
);
input y2, y1, y0;
output one, two, sign;
wire [1:0] k;
xor x1 (one, y0, y1);
xor x2 (k[1], y2, y1);
not n1 (k[0], one);
and a1 (two, k[0], k[1]);
assign sign = y2;
endmodule
| 6.869541 |
module rad4_gen (
x1,
y,
pp_rad4_0,
pp_rad4_1,
pp_rad4_2,
sign_factor
);
// inputs
// y multiplicand
// x multipland
// P1,P2,P3 partial products
input [15:0] y;
input [5:0] x1;
// output
output [16:0] pp_rad4_0;
output [16:0] pp_rad4_1;
output [16:0] pp_rad4_2;
output [2:... | 6.951944 |
module product (
x1,
x0,
one,
two,
sign,
p,
i
);
input x1, x0, sign, one, two;
output p, i;
wire [1:0] k;
xor xo1 (i, x1, sign);
and a1 (k[1], i, one);
and a0 (k[0], x0, two);
or o1 (p, k[1], k[0]);
endmodule
| 6.586499 |
module rad1024_unit (
input sign,
input [3:0] enc_vec,
input [3:0] a_vec,
output pp_i
);
// sign change
wire [3:0] a_sign;
assign a_sign[3] = sign ^ a_vec[3];
assign a_sign[2] = sign ^ a_vec[2];
assign a_sign[1] = sign ^ a_vec[1];
assign a_sign[0] = sign ^ a_vec[0];
// enc and a_sign
... | 6.522902 |
module HAd (
a,
b,
c,
s
);
input a, b;
output c, s;
xor x1 (s, a, b);
and a1 (c, a, b);
endmodule
| 7.388692 |
module FAd (
a,
b,
c,
cy,
sm
);
input a, b, c;
output cy, sm;
wire x, y, z;
xor x1 (x, a, b);
xor x2 (sm, x, c);
and a1 (y, a, b);
and a2 (z, x, c);
or o1 (cy, y, z);
endmodule
| 7.593245 |
module gray (
input Clk,
input Reset,
input En,
output reg [2:0] Output,
output reg Overflow
);
initial begin
Output = 0;
Overflow = 0;
end
always @(posedge Clk) begin
if (Reset) begin
Output <= 0;
Overflow <= 0;
end else begin
if (En) begin
case (... | 6.553837 |
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