code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module AhaClockSwitch2 (
// Inputs
input wire MASTER_CLK0,
input wire MASTER_CLK1,
input wire SELECT,
// Outputs
output wire CLK_OUT
);
wire m0_clk;
wire m1_clk;
wire m0_sel;
wire m1_sel;
AhaClockSwitchSlice u_m0_clk_switch_slice (
.CLK (MASTER_CLK0),
.SELECT_REQ (~SELECT),
.OTHERS_SELECT(m1_sel),
.CLK_OUT (m0_clk),
.SELECT_ACK(m0_sel)
);
AhaClockSwitchSlice u_m1_clk_switch_slice (
.CLK (MASTER_CLK1),
.SELECT_REQ (SELECT),
.OTHERS_SELECT(m0_sel),
.CLK_OUT (m1_clk),
.SELECT_ACK(m1_sel)
);
assign CLK_OUT = m0_clk | m1_clk;
endmodule
| 9.473661 |
module AhaClockSwitchSlice (
// Inputs
input wire CLK,
input wire SELECT_REQ,
// Others
input wire OTHERS_SELECT,
// Outputs
output wire CLK_OUT,
output wire SELECT_ACK
);
//
// Internal Signals
//
reg r_EN_STAGE0_SYNC;
reg r_EN_STAGE1;
reg r_EN;
wire w_CLK_OUT;
//
// Clock Selection Synchronization Stages
//
always @(posedge CLK) begin
r_EN_STAGE0_SYNC <= SELECT_REQ & ~OTHERS_SELECT;
r_EN_STAGE1 <= r_EN_STAGE0_SYNC;
end
//
// Update of Clock Gating Signal
//
always @(negedge CLK) r_EN <= r_EN_STAGE1;
AhaClockGate u_clock_gate_CLK (
.TE(1'b0),
.E (r_EN),
.CP(CLK),
.Q (w_CLK_OUT)
);
//
// Output Assignments
//
assign CLK_OUT = w_CLK_OUT;
assign SELECT_ACK = r_EN;
endmodule
| 9.473661 |
module AhaCounter #(
parameter WIDTH = 8
) (
input wire CLK,
input wire RESETn,
input wire EN,
output wire [WIDTH-1:0] Q
);
reg [WIDTH-1:0] count_val;
always @(posedge CLK or negedge RESETn) begin
if (~RESETn) count_val <= {WIDTH{1'b0}};
else if (EN) count_val <= count_val + {{(WIDTH - 1) {1'b0}}, 1'b1};
end
assign Q = count_val;
endmodule
| 7.418681 |
module AhaDataSync (
// Inputs
input wire CLK,
input wire RESETn,
input wire D,
// Outputs
output wire Q
);
reg sync_q;
reg sync_qq;
always @(posedge CLK or negedge RESETn) begin
if (~RESETn) begin
sync_q <= 1'b0;
sync_qq <= 1'b0;
end else begin
sync_q <= D;
sync_qq <= sync_q;
end
end
assign Q = sync_qq;
endmodule
| 6.819975 |
module AhaEnGenerator (
// Source Clock and Reset
input wire CLK,
input wire RESETn,
// Clock Enable Signals
output wire By2CLKEN,
output wire By4CLKEN,
output wire By8CLKEN,
output wire By16CLKEN,
output wire By32CLKEN
);
reg [4:0] counter_r;
reg by2clk_en_r;
reg by4clk_en_r;
reg by8clk_en_r;
reg by16clk_en_r;
reg by32clk_en_r;
// Counter
always @(posedge CLK or negedge RESETn) begin
if (~RESETn) counter_r <= 5'h0;
else counter_r <= counter_r + 1'b1;
end
// Enable Signals
always @(posedge CLK or negedge RESETn) begin
if (~RESETn) begin
by2clk_en_r <= 1'b0;
by4clk_en_r <= 1'b0;
by8clk_en_r <= 1'b0;
by16clk_en_r <= 1'b0;
by32clk_en_r <= 1'b0;
end else begin
by2clk_en_r <= counter_r[0] == 1'b1;
by4clk_en_r <= counter_r[1:0] == 2'b11;
by8clk_en_r <= counter_r[2:0] == 3'b111;
by16clk_en_r <= counter_r[3:0] == 4'hF;
by32clk_en_r <= counter_r[4:0] == 5'h1F;
end
end
// Output Clock Assignments
assign By2CLKEN = by2clk_en_r;
assign By4CLKEN = by4clk_en_r;
assign By8CLKEN = by8clk_en_r;
assign By16CLKEN = by16clk_en_r;
assign By32CLKEN = by32clk_en_r;
endmodule
| 7.168404 |
module AhaFreqDivider (
// Source Clock and Reset
input wire CLK,
input wire RESETn,
// Divided Clocks
output wire By2CLK,
output wire By4CLK,
output wire By8CLK,
output wire By16CLK,
output wire By32CLK
);
// Counter register
reg [4:0] counter;
// Generated Clocks
reg by2clk_r;
reg by4clk_r;
reg by8clk_r;
reg by16clk_r;
reg by32clk_r;
// Counter
always @(posedge CLK or negedge RESETn) begin
if (~RESETn) counter <= 5'h0;
else counter <= counter + 1'b1;
end
// Clock Generation
always @(posedge CLK or negedge RESETn) begin
if (~RESETn) begin
by2clk_r <= 1'b0;
by4clk_r <= 1'b0;
by8clk_r <= 1'b0;
by16clk_r <= 1'b0;
by32clk_r <= 1'b0;
end else begin
by2clk_r <= ~counter[0];
by4clk_r <= ~counter[1];
by8clk_r <= ~counter[2];
by16clk_r <= ~counter[3];
by32clk_r <= ~counter[4];
end
end
// Output Clock Assignments
assign By2CLK = by2clk_r;
assign By4CLK = by4clk_r;
assign By8CLK = by8clk_r;
assign By16CLK = by16clk_r;
assign By32CLK = by32clk_r;
endmodule
| 6.757503 |
module AhaLoopBackGen (
input wire [3:0] SELECT,
// Clocks
input wire SYS_CLK,
input wire CPU_CLK,
input wire DAP_CLK,
input wire DP_JTAG_CLK,
input wire UART0_CLK,
input wire SRAM_CLK,
input wire NIC_CLK,
// Debug Signals
input wire DBG_PWR_UP_REQ,
input wire DBG_PWR_UP_ACK,
input wire DBG_SYS_PWR_UP_REQ,
input wire DBG_SYS_PWR_UP_ACK,
// Output
output wire LOOP_BACK
);
reg chosen;
always @(*) begin
chosen = SYS_CLK;
case (SELECT)
4'd0: chosen = SYS_CLK;
4'd1: chosen = CPU_CLK;
4'd2: chosen = DAP_CLK;
4'd3: chosen = DP_JTAG_CLK;
4'd4: chosen = UART0_CLK;
4'd5: chosen = SRAM_CLK;
4'd6: chosen = NIC_CLK;
4'd7: chosen = DBG_PWR_UP_REQ;
4'd8: chosen = DBG_PWR_UP_ACK;
4'd9: chosen = DBG_SYS_PWR_UP_REQ;
4'd10: chosen = DBG_SYS_PWR_UP_ACK;
endcase
end
assign LOOP_BACK = chosen;
endmodule
| 7.354291 |
module AhaResetGen #(
parameter NUM_CYCLES = 1
) (
input wire CLK,
input wire PORESETn,
input wire REQ,
output wire ACK,
output wire Qn
);
// Synchronized Resets
wire poresetn_sync;
wire req_sync;
// Reset Cycles
reg [NUM_CYCLES:0] rst_cycles;
reg [NUM_CYCLES:0] ack_cycles;
// Power-On Reset Synchronization
AhaResetSync u_poreset_sync (
.CLK(CLK),
.Dn (PORESETn),
.Qn (poresetn_sync)
);
// Synchronized Reset Request
AhaDataSync u_req_sync (
.CLK (CLK),
.RESETn(poresetn_sync),
.D (REQ),
.Q (req_sync)
);
// Reset Generation Logic
integer i;
always @(posedge CLK or negedge poresetn_sync) begin
if (~poresetn_sync) rst_cycles <= {(NUM_CYCLES + 1) {1'b0}};
else begin
rst_cycles[0] <= ~req_sync;
for (i = 1; i <= NUM_CYCLES; i = i + 1) rst_cycles[i] <= rst_cycles[i-1];
end
end
// ACK generation
always @(posedge CLK or negedge poresetn_sync) begin
if (~poresetn_sync) ack_cycles <= {(NUM_CYCLES + 1) {1'b0}};
else begin
ack_cycles[0] <= req_sync;
for (i = 1; i <= NUM_CYCLES; i = i + 1) ack_cycles[i] <= ack_cycles[i-1];
end
end
// Output Assignments
assign ACK = ack_cycles[NUM_CYCLES];
assign Qn = (&rst_cycles);
endmodule
| 7.207033 |
module AhaResetGenX4 #(
parameter NUM_CYCLES = 1
) (
input wire CLK,
input wire PORESETn,
// Reset Request Lane 0
input wire REQ_0,
output wire ACK_0,
// Reset Request Lane 1
input wire REQ_1,
output wire ACK_1,
// Reset Request Lane 2
input wire REQ_2,
output wire ACK_2,
// Reset Request Lane 3
input wire REQ_3,
output wire ACK_3,
output wire Qn
);
wire q0_n;
wire q1_n;
wire q2_n;
wire q3_n;
AhaResetGen #(
.NUM_CYCLES(NUM_CYCLES)
) u_rst_gen_0 (
.CLK (CLK),
.PORESETn(PORESETn),
.REQ (REQ_0),
.ACK (ACK_0),
.Qn (q0_n)
);
AhaResetGen #(
.NUM_CYCLES(NUM_CYCLES)
) u_rst_gen_1 (
.CLK (CLK),
.PORESETn(PORESETn),
.REQ (REQ_1),
.ACK (ACK_1),
.Qn (q1_n)
);
AhaResetGen #(
.NUM_CYCLES(NUM_CYCLES)
) u_rst_gen_2 (
.CLK (CLK),
.PORESETn(PORESETn),
.REQ (REQ_2),
.ACK (ACK_2),
.Qn (q2_n)
);
AhaResetGen #(
.NUM_CYCLES(NUM_CYCLES)
) u_rst_gen_3 (
.CLK (CLK),
.PORESETn(PORESETn),
.REQ (REQ_3),
.ACK (ACK_3),
.Qn (q3_n)
);
assign Qn = q0_n & q1_n & q2_n & q3_n;
endmodule
| 6.619256 |
module AhaResetSync (
// Inputs
input wire CLK,
input wire Dn,
// Outputs
output wire Qn
);
reg sync_q;
reg sync_qq;
always @(posedge CLK or negedge Dn) begin
if (~Dn) begin
sync_q <= 1'b0;
sync_qq <= 1'b0;
end else begin
sync_q <= 1'b1;
sync_qq <= sync_q;
end
end
assign Qn = sync_qq;
endmodule
| 7.055947 |
module AhaRomTable (
input PCLK, // APB Clock
input PRESETn, // APB Reset
input PSEL, // APB Select
input PENABLE, // APB Enable
input [11:2] PADDR, // APB Address
input PWRITE, // APB Write
output [31:0] PRDATA // APB Read Data
);
// Local controls
wire unused = PENABLE;
wire addr_reg_we;
wire [ 5:0] nxt_addr_reg;
reg [ 5:0] addr_reg;
reg [31:0] apb_rdata;
assign PRDATA = apb_rdata;
// ---------------------------------------------------------------------------
// Control registration. Map addresses into two regions
// Only supports 4 LSBs of address
// ---------------------------------------------------------------------------
assign addr_reg_we = PSEL & ~PWRITE;
assign nxt_addr_reg = {&PADDR[11:6], ~|PADDR[11:6], PADDR[5:2]};
always @(posedge PCLK or negedge PRESETn)
if (~PRESETn) addr_reg <= 6'b000000;
else if (addr_reg_we) addr_reg <= nxt_addr_reg;
// ---------------------------------------------------------------------------
// Read Multiplexor
// ---------------------------------------------------------------------------
always @*
case (addr_reg)
// --------------------------------------------------------------------
// ROM table entries for debug components inside the Cortex-M3 processor.
//
// NVIC (0x000) - Do not modify
6'b0_1_0000: apb_rdata = 32'hFFF0F003;
// DWT (0x004) - Do not modify
6'b0_1_0001: apb_rdata = 32'hFFF02003;
// FPB (0x008) - Do not modify
6'b0_1_0010: apb_rdata = 32'hFFF03003;
// ITM (0x00C) - Do not modify
6'b0_1_0011: apb_rdata = 32'hFFF01003;
// TPIU (0x010)
6'b0_1_0100: apb_rdata = 32'hFFF41003;
// Target Identification IDs - for identification of target platform
// PID4
6'b1_0_0100: apb_rdata = 32'h00000004;
// PID5
6'b1_0_0101: apb_rdata = 32'h00000000;
// PID6
6'b1_0_0110: apb_rdata = 32'h00000000;
// PID7
6'b1_0_0111: apb_rdata = 32'h00000000;
// PID0
6'b1_0_1000: apb_rdata = 32'h000000C3;
// PID1
6'b1_0_1001: apb_rdata = 32'h000000B4;
// PID2
6'b1_0_1010: apb_rdata = 32'h0000001B;
// PID3
6'b1_0_1011: apb_rdata = 32'h00000000;
// MEMTYPE - Indicates that system memory can be accessed
6'b1_0_0011: apb_rdata = 32'h00000001;
// Do not modify the following ID registers
// CID0
6'b1_0_1100: apb_rdata = 32'h0000000D;
// CID1
6'b1_0_1101: apb_rdata = 32'h00000010;
// CID2
6'b1_0_1110: apb_rdata = 32'h00000005;
// CID3
6'b1_0_1111: apb_rdata = 32'h000000B1;
// No EXTRA ROM ENTRY since PPB is not exported
6'b0_1_0111: apb_rdata = 32'h00000000;
default: apb_rdata = 32'h00000000;
endcase
endmodule
| 7.311897 |
module AhaSram32Kx32 #(
parameter IMAGE_FILE = "None"
) (
input wire CLK,
input wire RESETn,
input wire CEn,
input wire [ 3:0] WEn,
input wire [14:0] A,
input wire [31:0] D,
output wire [31:0] Q
);
//
// Instantiate SIM SRAM Generator
//
AhaSramSimGen #(
.ADDR_WIDTH(15),
.DATA_WIDTH(32),
.IMAGE_FILE(IMAGE_FILE)
) sram_sim_gen_inst (
.CLK (CLK),
.RESETn(RESETn),
.CS (~CEn),
.WE (~WEn),
.ADDR (A),
.WDATA (D),
.RDATA (Q)
);
endmodule
| 6.56025 |
module AhaSram4Kx64 #(
parameter IMAGE_FILE = "None"
) (
input wire CLK,
input wire RESETn,
input wire CEn,
input wire [ 7:0] WEn,
input wire [11:0] A,
input wire [63:0] D,
output wire [63:0] Q
);
//
// Instantiate SIM SRAM Generator
//
AhaSramSimGen #(
.ADDR_WIDTH(12),
.DATA_WIDTH(64),
.IMAGE_FILE(IMAGE_FILE)
) sram_sim_gen_inst (
.CLK (CLK),
.RESETn(RESETn),
.CS (~CEn),
.WE (~WEn),
.ADDR (A),
.WDATA (D),
.RDATA (Q)
);
endmodule
| 6.837859 |
module AhaSramSimGen #(
parameter ADDR_WIDTH,
parameter DATA_WIDTH,
parameter IMAGE_FILE
) (
input wire CLK,
input wire RESETn,
input wire CS,
input wire [(DATA_WIDTH/8)-1:0] WE,
input wire [ (ADDR_WIDTH-1):0] ADDR,
input wire [ (DATA_WIDTH-1):0] WDATA,
output wire [ (DATA_WIDTH-1):0] RDATA
);
//
// Local Parameters
//
localparam MEM_DEPTH = (1 << ADDR_WIDTH);
localparam STRB_WIDTH = DATA_WIDTH / 8;
//
// Internal Signals
//
integer i, fd;
reg [(DATA_WIDTH-1):0] memQ;
reg [(DATA_WIDTH-1):0] memD;
//
// Memory Array
//
reg [(DATA_WIDTH-1):0] memory[MEM_DEPTH-1:0];
//
// Load Memory
//
initial begin : MemInit
fd = $fopen(IMAGE_FILE, "r");
if (fd != 0) begin
$fclose(fd);
$readmemh(IMAGE_FILE, memory);
end else begin
for (i = 0; i < MEM_DEPTH; i = i + 1) memory[i] = {DATA_WIDTH{1'b0}};
end
end
//
// Memory Write
//
always @(posedge CLK) begin : MemWrite
if (CS) begin
memD = memory[ADDR];
for (i = 0; i < STRB_WIDTH; i = i + 1) if (WE[i]) memD[i*8+:8] = WDATA[i*8+:8];
memory[ADDR] = memD;
end
end
//
// Memory Read
//
always @(posedge CLK or negedge RESETn)
if (~RESETn) memQ <= {DATA_WIDTH{1'b0}};
else if (CS) memQ <= memory[ADDR];
//
// Output Assignments
//
assign RDATA = memQ;
endmodule
| 7.340686 |
module AhaSyncPulseGen (
input wire CLK,
input wire RESETn,
input wire D,
output wire RISE_PULSE,
output wire FALL_PULSE
);
reg d_r;
always @(posedge CLK or negedge RESETn) begin
if (~RESETn) d_r <= 1'b0;
else d_r <= D;
end
assign RISE_PULSE = D & ~d_r;
assign FALL_PULSE = ~D & d_r;
endmodule
| 7.560093 |
module AhaSysResetReqGen (
// Clock and Reset
input wire CLK,
input wire RESETn,
// Input Requests
input wire SYSRESETREQ,
input wire LOCKUP,
input wire LOCKUP_RESET_EN,
input wire WDOG_TIMEOUT_RESET,
input wire WDOG_TIMEOUT_RESET_EN,
// Combined System Reset Request
output wire SYSRESETREQ_COMBINED
);
reg rst_r;
// Combine reset requests
wire rst_req = (SYSRESETREQ) |
(LOCKUP & LOCKUP_RESET_EN) |
(WDOG_TIMEOUT_RESET & WDOG_TIMEOUT_RESET_EN);
always @(posedge CLK or negedge RESETn) begin
if (~RESETn) rst_r <= 1'b0;
else rst_r <= rst_req;
end
assign SYSRESETREQ_COMBINED = rst_r;
endmodule
| 8.522256 |
module AhaTimerIntegration (
// Bus Interface
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire HWRITE,
input wire [ 2:0] HSIZE,
input wire [ 2:0] HBURST,
input wire [ 3:0] HPROT,
input wire [31:0] HWDATA,
input wire HREADYMUX,
output wire [31:0] HRDATA,
output wire HREADYOUT,
output wire [ 1:0] HRESP,
// Peripheral Interface
input wire PCLK,
input wire PCLKEN,
input wire PRESETn,
// Interrupts
output wire TIMERINT
);
// Prevent lint messages for unused inputs
wire unused = (|HBURST);
wire [ 1:0] int_hresp;
wire [11:0] int_paddr;
wire int_penable;
wire int_pwrite;
wire [31:0] int_pwdata;
wire int_psel;
wire [31:0] int_prdata;
wire int_pready;
wire int_pslverr;
// AHB-APB Bridge
cmsdk_ahb_to_apb #(
.ADDRWIDTH (12),
.REGISTER_RDATA(1),
.REGISTER_WDATA(0)
) u_cmsdk_ahb_apb_bridge (
.HCLK (HCLK),
.HRESETn(HRESETn),
.PCLKEN (PCLKEN),
.HSEL (HSEL),
.HADDR (HADDR[11:0]),
.HTRANS(HTRANS),
.HSIZE (HSIZE),
.HPROT (HPROT),
.HWRITE(HWRITE),
.HREADY(HREADYMUX),
.HWDATA(HWDATA),
.HREADYOUT(HREADYOUT),
.HRDATA (HRDATA),
.HRESP (int_hresp[0]),
.PADDR (int_paddr),
.PENABLE(int_penable),
.PWRITE (int_pwrite),
.PSTRB ( /*unused*/),
.PPROT ( /*unused*/),
.PWDATA (int_pwdata),
.PSEL (int_psel),
.APBACTIVE( /*unused*/),
.PRDATA (int_prdata),
.PREADY (int_pready),
.PSLVERR(int_pslverr)
);
assign int_hresp[1] = 1'b0;
assign HRESP = int_hresp;
// CMSDK APB Timer
cmsdk_apb_timer u_timer (
.PCLK (PCLK),
.PCLKG (PCLK),
.PRESETn(PRESETn),
.PSEL (int_psel),
.PADDR (int_paddr[11:2]),
.PENABLE(int_penable),
.PWRITE (int_pwrite),
.PWDATA (int_pwdata),
.ECOREVNUM(4'h0),
.PRDATA (int_prdata),
.PREADY (int_pready),
.PSLVERR(int_pslverr),
.EXTIN (1'b1), // no external clock used
.TIMERINT(TIMERINT)
);
endmodule
| 7.50605 |
module AhaTlxDataSync #(
parameter WIDTH = 1
) (
// Inputs
input wire SRC_CLK,
input wire SRC_RESETn,
input wire DEST_CLK,
input wire DEST_RESETn,
input wire [WIDTH-1:0] D,
// Outputs
output wire [WIDTH-1:0] Q
);
// For Synopsys DW IP
/*
DW_data_sync #(
.width (WIDTH),
.pend_mode (1),
.ack_delay (1),
.f_sync_type (2),
.r_sync_type (2),
.send_mode (0)
)
u_aha_tlx_data_sync (
.clk_s (SRC_CLK),
.rst_s_n (SRC_RESETn),
.init_s_n (1'b1),
.send_s (1'b1),
.data_s (D),
.empty_s (),
.full_s (),
.done_s (),
.clk_d (DEST_CLK),
.rst_d_n (DEST_RESETn),
.init_d_n (1'b1),
.data_avail_d (),
.data_d (Q),
.test (1'b0)
);
*/
// For Cadence CW IP
CW_data_sync_1c #(
.width (WIDTH),
.f_sync_type(2),
.tst_mode (0),
.verif_en (0),
.filt_size (1)
) u_aha_tlx_data_sync (
.clk_d (DEST_CLK),
.rst_d_n (DEST_RESETn),
.init_d_n (1'b1),
.data_s (D),
.filt_d (1'b1),
.test (1'b0),
.data_avail_d(),
.data_d (Q),
.max_skew_d ()
// CW Synchronizer doesn't use source clock
//.clk_s (SRC_CLK),
//.rst_s_n (SRC_RESETn),
//.init_s_n (1'b1),
//.send_s (1'b1),
//.empty_s (),
//.full_s (),
//.done_s (),
);
endmodule
| 8.543662 |
module AhaTlxOutputLane (
input wire CLK, // Clock
input wire RESETn, // Reset
input wire D_IN, // TLX Data
input wire START, // Start Pulse
input wire CLEAR, // Clear Pulse (Clears DONE)
input wire [31:0] SEQUENCE, // Sequence to send out
input wire [31:0] LENGTH, // Trip count of sequences to send out
input wire AUTO_STOP, // Stop after LENGTH or run until CLEAR
input wire MODE, // select TLX data or training data output
output wire DONE, // Completed training sequence
output wire ACTIVE, // Status indicating training active
output wire D_OUT // PHY lane output
);
wire start_pulse;
wire clear_pulse;
reg tr_out;
reg [ 4:0] idx;
reg [31:0] count;
reg done_r;
wire done_w;
wire tr_tick = idx == 5'b11111;
parameter [1:0] // synopsys enum code
IDLE = 2'b00, TRAINING = 2'b01, FINISH = 2'b10;
// synopsys state_vector state
reg [1:0] // synopsys enum code
state, next;
// State Update
always @(posedge CLK or negedge RESETn) begin
if (~RESETn) state <= IDLE;
else state <= next;
end
// Next State Logic
always @(*) begin
case (state)
IDLE:
casez ({
clear_pulse, start_pulse
})
2'b1?: next = IDLE;
2'b01: next = TRAINING;
default: next = IDLE;
endcase
TRAINING:
casez ({
clear_pulse, done_w & AUTO_STOP
})
2'b1?: next = IDLE;
2'b01: next = FINISH;
2'b00: next = TRAINING;
default: next = IDLE;
endcase
FINISH: next = IDLE;
default: next = IDLE;
endcase
end
// Index Generator
always @(posedge CLK or negedge RESETn) begin
if (~RESETn) idx <= 5'h0;
else if (state == TRAINING) idx <= idx + 1'b1;
else idx <= 5'h0;
end
// Training output
always @(posedge CLK or negedge RESETn) begin
if (~RESETn) tr_out <= 1'b0;
else if (clear_pulse == 1'b1) tr_out <= 1'b0;
else if ((state == TRAINING) && !done_w) tr_out <= SEQUENCE[idx];
else tr_out <= 1'b0;
end
// Sequence Count
always @(posedge CLK or negedge RESETn) begin
if (~RESETn) count <= {32{1'b0}};
else if (clear_pulse == 1'b1) count <= {32{1'b0}};
else if ((state == TRAINING) & tr_tick) count <= count + 1'b1;
end
// Done Signals
assign done_w = (state == TRAINING) && (count == LENGTH) && (AUTO_STOP == 1'b1);
always @(posedge CLK or negedge RESETn) begin
if (~RESETn) done_r <= 1'b0;
else if ((done_w == 1'b1) && (AUTO_STOP == 1'b1)) done_r <= 1'b1;
else if (clear_pulse == 1'b1) done_r <= 1'b0;
end
AhaSyncPulseGen u_start_pulse_gen (
.CLK (CLK),
.RESETn (RESETn),
.D (START),
.RISE_PULSE(start_pulse),
.FALL_PULSE()
);
AhaSyncPulseGen u_clear_pulse_gen (
.CLK (CLK),
.RESETn (RESETn),
.D (CLEAR),
.RISE_PULSE(clear_pulse),
.FALL_PULSE()
);
assign D_OUT = MODE ? tr_out : D_IN;
assign DONE = done_r;
assign ACTIVE = AUTO_STOP ? (state == TRAINING) && (count != LENGTH) : (state == TRAINING);
endmodule
| 7.342798 |
module AhaTlxPulseSync (
// Inputs
input wire SRC_CLK,
input wire SRC_RESETn,
input wire DEST_CLK,
input wire DEST_RESETn,
input wire D,
// Outputs
output wire Q
);
CW_pulse_sync #(
.reg_event (1),
.f_sync_type(2),
.pulse_mode (1)
) u_aha_tlx_pulse_sync (
.clk_s (SRC_CLK),
.rst_s_n (SRC_RESETn),
.init_s_n(1'b1),
.event_s (D),
.clk_d (DEST_CLK),
.rst_d_n (DEST_RESETn),
.init_d_n(1'b1),
.event_d (Q),
.test (1'b0)
);
endmodule
| 7.121637 |
module AhaUartIntegration (
// Bus Interface
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire HWRITE,
input wire [ 2:0] HSIZE,
input wire [ 2:0] HBURST,
input wire [ 3:0] HPROT,
input wire [31:0] HWDATA,
input wire HREADYMUX,
output wire [31:0] HRDATA,
output wire HREADYOUT,
output wire [ 1:0] HRESP,
// Peripheral Interface
input wire PCLK,
input wire PCLKEN,
input wire PRESETn,
input wire RXD,
output wire TXD,
// Interrupts
output wire TXINT,
output wire RXINT,
output wire TXOVRINT,
output wire RXOVRINT,
output wire UARTINT
);
// Prevent lint messages for unused inputs
wire unused = (|HBURST);
wire [ 1:0] int_hresp;
wire [11:0] int_paddr;
wire int_penable;
wire int_pwrite;
wire [31:0] int_pwdata;
wire int_psel;
wire [31:0] int_prdata;
wire int_pready;
wire int_pslverr;
// AHB-APB Bridge
cmsdk_ahb_to_apb #(
.ADDRWIDTH (12),
.REGISTER_RDATA(1),
.REGISTER_WDATA(0)
) u_cmsdk_ahb_apb_bridge (
.HCLK (HCLK),
.HRESETn(HRESETn),
.PCLKEN (PCLKEN),
.HSEL (HSEL),
.HADDR (HADDR[11:0]),
.HTRANS(HTRANS),
.HSIZE (HSIZE),
.HPROT (HPROT),
.HWRITE(HWRITE),
.HREADY(HREADYMUX),
.HWDATA(HWDATA),
.HREADYOUT(HREADYOUT),
.HRDATA (HRDATA),
.HRESP (int_hresp[0]),
.PADDR (int_paddr),
.PENABLE(int_penable),
.PWRITE (int_pwrite),
.PSTRB ( /*unused*/),
.PPROT ( /*unused*/),
.PWDATA (int_pwdata),
.PSEL (int_psel),
.APBACTIVE( /*unused*/),
.PRDATA (int_prdata),
.PREADY (int_pready),
.PSLVERR(int_pslverr)
);
assign int_hresp[1] = 1'b0;
assign HRESP = int_hresp;
// CMSDK UART
cmsdk_apb_uart u_cmsdk_apb_uart_0 (
.PCLK (PCLK),
.PCLKG (PCLK),
.PRESETn(PRESETn),
.PSEL (int_psel),
.PADDR (int_paddr[11:2]),
.PENABLE(int_penable),
.PWRITE (int_pwrite),
.PWDATA (int_pwdata),
.ECOREVNUM(4'h0),
.PRDATA (int_prdata),
.PREADY (int_pready),
.PSLVERR(int_pslverr),
.RXD (RXD),
.TXD (TXD),
.TXEN ( /*unused*/),
.BAUDTICK( /*unused*/),
.TXINT (TXINT),
.RXINT (RXINT),
.TXOVRINT(TXOVRINT),
.RXOVRINT(RXOVRINT),
.UARTINT (UARTINT)
);
endmodule
| 7.339938 |
module AhaWdogIntegration (
// Bus Interface
input wire HCLK, // Interconnect Clock
input wire HRESETn, // Interconnect Reset (synched to HCLK)
input wire HSEL,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire HWRITE,
input wire [ 2:0] HSIZE,
input wire [ 2:0] HBURST,
input wire [ 3:0] HPROT,
input wire [31:0] HWDATA,
input wire HREADYMUX,
output wire [31:0] HRDATA,
output wire HREADYOUT,
output wire [ 1:0] HRESP,
// Peripheral Interface
input wire PCLK, // Watchdog timer clock
input wire PCLKEN, // Watchdog timer clock qualifier for HCLK
input wire PRESETn, // Watchdog reset (synched to PCLK)
// Interrupts
output wire WDOG_INT, // Watchdog interrupt
output wire WDOG_RESET // Watchdog timeout reset
);
// Prevent lint messages for unused inputs
wire unused = (|HBURST);
wire [ 1:0] int_hresp;
wire [11:0] int_paddr;
wire int_penable;
wire int_pwrite;
wire [31:0] int_pwdata;
wire int_psel;
wire [31:0] int_prdata;
wire int_pready;
wire int_pslverr;
// AHB-APB Bridge
cmsdk_ahb_to_apb #(
.ADDRWIDTH (12),
.REGISTER_RDATA(1),
.REGISTER_WDATA(0)
) u_cmsdk_ahb_apb_bridge (
.HCLK (HCLK),
.HRESETn(HRESETn),
.PCLKEN (PCLKEN),
.HSEL (HSEL),
.HADDR (HADDR[11:0]),
.HTRANS(HTRANS),
.HSIZE (HSIZE),
.HPROT (HPROT),
.HWRITE(HWRITE),
.HREADY(HREADYMUX),
.HWDATA(HWDATA),
.HREADYOUT(HREADYOUT),
.HRDATA (HRDATA),
.HRESP (int_hresp[0]),
.PADDR (int_paddr),
.PENABLE(int_penable),
.PWRITE (int_pwrite),
.PSTRB ( /*unused*/),
.PPROT ( /*unused*/),
.PWDATA (int_pwdata),
.PSEL (int_psel),
.APBACTIVE( /*unused*/),
.PRDATA (int_prdata),
.PREADY (int_pready),
.PSLVERR(int_pslverr)
);
assign int_hresp[1] = 1'b0;
assign HRESP = int_hresp;
// CMSDK Wdog Timer
cmsdk_apb_watchdog u_cmsdk_apb_watchdog (
.PCLK (PCLK), // APB clock
.PRESETn(PRESETn), // APB reset
.PENABLE(int_penable), // APB enable
.PSEL (int_psel), // APB periph select
.PADDR (int_paddr[11:2]), // APB address bus [11:2]
.PWRITE (int_pwrite), // APB write
.PWDATA (int_pwdata), // APB write data [31:0]
.WDOGCLK (PCLK), // Watchdog clock
.WDOGCLKEN(1'b1), // Watchdog clock enable
.WDOGRESn (PRESETn), // Watchdog clock reset
.ECOREVNUM(4'h0), // ECO revision number
.PRDATA(int_prdata), // APB read data [31:0]
.WDOGINT(WDOG_INT), // Watchdog interrupt
.WDOGRES(WDOG_RESET) // Watchdog timeout reset
);
assign int_pready = 1'b1;
assign int_pslverr = 1'b0;
endmodule
| 7.231148 |
module ahb2apb (
apb_haddr,
apb_hburst,
apb_hrdata,
apb_hready,
apb_hresp,
apb_hsel,
apb_hsize,
apb_htrans,
apb_hwdata,
apb_hwrite,
haddr_s2,
hburst_s2,
hmastlock,
hprot_s2,
hrdata_s2,
hready_s2,
hresp_s2,
hsel_s2,
hsize_s2,
htrans_s2,
hwdata_s2,
hwrite_s2,
pad_cpu_rst_b,
pll_core_cpuclk
);
input [31 : 0] apb_hrdata;
input apb_hready;
input [1 : 0] apb_hresp;
input [39 : 0] haddr_s2;
input [2 : 0] hburst_s2;
input hmastlock;
input [3 : 0] hprot_s2;
input hsel_s2;
input [2 : 0] hsize_s2;
input [1 : 0] htrans_s2;
input [127:0] hwdata_s2;
input hwrite_s2;
input pad_cpu_rst_b;
input pll_core_cpuclk;
output [39 : 0] apb_haddr;
output [2 : 0] apb_hburst;
output apb_hsel;
output [2 : 0] apb_hsize;
output [1 : 0] apb_htrans;
output [31 : 0] apb_hwdata;
output apb_hwrite;
output [127:0] hrdata_s2;
output hready_s2;
output [1 : 0] hresp_s2;
reg [31 : 0] apb_hwdata;
reg [ 127:0] hrdata_s2;
reg [39 : 0] latch_haddr;
wire [39 : 0] apb_haddr;
wire [ 2 : 0] apb_hburst;
wire [31 : 0] apb_hrdata;
wire apb_hready;
wire [ 1 : 0] apb_hresp;
wire apb_hsel;
wire [ 2 : 0] apb_hsize;
wire [ 1 : 0] apb_htrans;
wire apb_hwrite;
wire [39 : 0] haddr_s2;
wire [ 2 : 0] hburst_s2;
wire hready_s2;
wire [ 1 : 0] hresp_s2;
wire hsel_s2;
wire [ 2 : 0] hsize_s2;
wire [ 1 : 0] htrans_s2;
wire [ 127:0] hwdata_s2;
wire hwrite_s2;
wire pad_cpu_rst_b;
wire pll_core_cpuclk;
assign hready_s2 = apb_hready;
assign hresp_s2[1:0] = apb_hresp[1:0];
assign apb_hsel = hsel_s2;
assign apb_haddr[39:0] = haddr_s2[39:0];
assign apb_hburst[2:0] = hburst_s2[2:0];
assign apb_hsize[2:0] = hsize_s2[2:0];
assign apb_htrans[1:0] = htrans_s2[1:0];
assign apb_hwrite = hwrite_s2;
always @(posedge pll_core_cpuclk or negedge pad_cpu_rst_b) begin
if (!pad_cpu_rst_b) begin
latch_haddr[39:0] <= 40'b0;
end else if (apb_hready) begin
latch_haddr[39:0] <= haddr_s2[39:0];
end else begin
latch_haddr[39:0] <= latch_haddr[39:0];
end
end
always @(hwdata_s2[63:0] or hwdata_s2[127:64] or latch_haddr[3:2]) begin
case (latch_haddr[3:2])
2'b00: begin
apb_hwdata[31:0] = hwdata_s2[31:0];
end
2'b01: begin
apb_hwdata[31:0] = hwdata_s2[63:32];
end
2'b10: begin
apb_hwdata[31:0] = hwdata_s2[95:64];
end
2'b11: begin
apb_hwdata[31:0] = hwdata_s2[127:96];
end
default: begin
apb_hwdata[31:0] = 32'bx;
end
endcase
end
always @(latch_haddr[3:2] or apb_hrdata[31:0]) begin
case (latch_haddr[3:2])
2'b00: begin
hrdata_s2[127:0] = {96'b0, apb_hrdata[31:0]};
end
2'b01: begin
hrdata_s2[127:0] = {64'b0, apb_hrdata[31:0], 32'b0};
end
2'b10: begin
hrdata_s2[127:0] = {32'b0, apb_hrdata[31:0], 64'b0};
end
2'b11: begin
hrdata_s2[127:0] = {apb_hrdata[31:0], 96'b0};
end
default: begin
hrdata_s2[127:0] = 128'bx;
end
endcase
end
endmodule
| 7.181983 |
module AHB2MEM #(
parameter MEMWIDTH = 14
) // SIZE[Bytes] = 2 ^ MEMWIDTH[Bytes] = 2 ^ MEMWIDTH / 4[Entries]
(
//AHBLITE INTERFACE
//Slave Select Signals
input wire HSEL,
//Global Signal
input wire HCLK,
input wire HRESETn,
//Address, Control & Write Data
input wire HREADY,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire HWRITE,
input wire [2:0] HSIZE,
input wire [31:0] HWDATA,
// Transfer Response & Read Data
output wire HREADYOUT,
output reg [31:0] HRDATA
);
assign HREADYOUT = 1'b1; // Always ready
// Memory Array
reg [31:0] memory[0:(2**(MEMWIDTH-2)-1)];
initial begin
$readmemh("code.hex", memory);
end
// Registers to store Adress Phase Signals
reg APhase_HSEL;
reg APhase_HWRITE;
reg [1:0] APhase_HTRANS;
reg [31:0] APhase_HRADDR;
reg [31:0] APhase_HWADDR;
reg [2:0] APhase_HSIZE;
// Sample the Address Phase
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
APhase_HSEL <= 1'b0;
APhase_HWRITE <= 1'b0;
APhase_HTRANS <= 2'b00;
APhase_HWADDR <= 32'h0;
APhase_HSIZE <= 3'b000;
APhase_HRADDR[MEMWIDTH-2:0] <= {(MEMWIDTH - 1) {1'b0}};
end else if (HREADY) begin
APhase_HSEL <= HSEL;
APhase_HWRITE <= HWRITE;
APhase_HTRANS <= HTRANS;
APhase_HWADDR <= HADDR;
APhase_HSIZE <= HSIZE;
APhase_HRADDR[MEMWIDTH-2:0] <= HADDR[MEMWIDTH:2];
end
end
// Decode the bytes lanes depending on HSIZE & HADDR[1:0]
wire tx_byte = ~APhase_HSIZE[1] & ~APhase_HSIZE[0];
wire tx_half = ~APhase_HSIZE[1] & APhase_HSIZE[0];
wire tx_word = APhase_HSIZE[1];
wire byte_at_00 = tx_byte & ~APhase_HWADDR[1] & ~APhase_HWADDR[0];
wire byte_at_01 = tx_byte & ~APhase_HWADDR[1] & APhase_HWADDR[0];
wire byte_at_10 = tx_byte & APhase_HWADDR[1] & ~APhase_HWADDR[0];
wire byte_at_11 = tx_byte & APhase_HWADDR[1] & APhase_HWADDR[0];
wire half_at_00 = tx_half & ~APhase_HWADDR[1];
wire half_at_10 = tx_half & APhase_HWADDR[1];
wire word_at_00 = tx_word;
wire byte0 = word_at_00 | half_at_00 | byte_at_00;
wire byte1 = word_at_00 | half_at_00 | byte_at_01;
wire byte2 = word_at_00 | half_at_10 | byte_at_10;
wire byte3 = word_at_00 | half_at_10 | byte_at_11;
always @(posedge HCLK) begin
if (APhase_HSEL & APhase_HWRITE & APhase_HTRANS[1]) begin
if (byte0) memory[APhase_HWADDR[MEMWIDTH:2]][7:0] <= HWDATA[7:0];
if (byte1) memory[APhase_HWADDR[MEMWIDTH:2]][15:8] <= HWDATA[15:8];
if (byte2) memory[APhase_HWADDR[MEMWIDTH:2]][23:16] <= HWDATA[23:16];
if (byte3) memory[APhase_HWADDR[MEMWIDTH:2]][31:24] <= HWDATA[31:24];
end
HRDATA = memory[HADDR[MEMWIDTH:2]];
end
endmodule
| 6.873488 |
module AHB2BUTTON (
input wire HCLK,
input wire HRESETn,
input wire button_in,
output wire button_out, // ⲿֵ
output reg button_tick
);
localparam st_idle = 2'b00;
localparam st_wait1 = 2'b01;
localparam st_stable = 2'b10;
localparam st_wait0 = 2'b11;
reg [ 1:0] current_state = st_idle; // ǰ״̬
reg [ 1:0] next_state = st_idle; // һ״̬
reg [21:0] db_clk = {21{1'b1}}; // regڼ״̬Ƿάһʱ
reg [21:0] db_clk_next = {21{1'b1}};
always @(posedge HCLK or negedge HRESETn) begin // ϵͳĽ
if (!HRESETn) begin
current_state <= st_idle;
db_clk <= 0;
end else begin // £һ״̬ǰ״̬ʱҲı
current_state <= next_state;
db_clk <= db_clk_next;
end
end
always @(*) begin
next_state = current_state; // Ĭϲıϵͳ״̬Ҫǰ״̬ⲿȷθı״̬
db_clk_next = db_clk;
button_tick = 0; // ֪Ǹõ
case (current_state) // ݵǰ״ָ̬ıϵͳ״̬
st_idle: begin //
if (button_in) begin // ڿ״̬а
db_clk_next = {21{1'b1}}; // ڼﵽȶҪʱ
next_state = st_wait1; // 鵽£ı״̬ȴźȶ״̬
end
end
st_wait1: begin // а£ȴźȶ
if (button_in) begin
db_clk_next = db_clk - 1;
if (db_clk_next == 0) begin // ȷﵽȶ״̬
next_state = st_stable;
button_tick = 1'b1; // ?
end
end
end
st_stable: begin // źѾȶ
if (~button_in) begin // ǰȶ״̬ͷŵIJ
next_state = st_wait0;
db_clk_next = {21{1'b1}};
end
end
st_wait0: begin // ȷǷͷ
if (~button_in) begin
db_clk_next = db_clk - 1;
if (db_clk_next == 0) begin // ȷͷ
next_state = st_idle;
end
end else begin // ֮ǰİͷһẹ̈Ӧú
next_state = st_stable;
end
end
endcase
end
assign button_out = (current_state == st_stable || current_state == st_wait0) ? 1'b1 : 1'b0;
endmodule
| 6.844729 |
module can_crc (
data,
crc_en,
clk,
n_rst,
crc_out
);
output [14:0] crc_out;
input data, crc_en, clk, n_rst;
wire n18, n26, n30, n32, n38, n40, n46, n1, n2, n3, n4, n5, n6, n7, n8, n9,
n10, n11, n12, n13, n14, n15, n16, n20, n22, n24, n28, n34, n36, n42;
DFFSR \crc_out_reg[0] (
.D (n46),
.CLK(clk),
.R (n_rst),
.S (1'b1),
.Q (crc_out[0])
);
DFFSR \crc_out_reg[1] (
.D (n16),
.CLK(clk),
.R (n_rst),
.S (1'b1),
.Q (crc_out[1])
);
DFFSR \crc_out_reg[2] (
.D (n20),
.CLK(clk),
.R (n_rst),
.S (1'b1),
.Q (crc_out[2])
);
DFFSR \crc_out_reg[3] (
.D (n40),
.CLK(clk),
.R (n_rst),
.S (1'b1),
.Q (crc_out[3])
);
DFFSR \crc_out_reg[4] (
.D (n38),
.CLK(clk),
.R (n_rst),
.S (1'b1),
.Q (crc_out[4])
);
DFFSR \crc_out_reg[5] (
.D (n22),
.CLK(clk),
.R (n_rst),
.S (1'b1),
.Q (crc_out[5])
);
DFFSR \crc_out_reg[6] (
.D (n24),
.CLK(clk),
.R (n_rst),
.S (1'b1),
.Q (crc_out[6])
);
DFFSR \crc_out_reg[7] (
.D (n32),
.CLK(clk),
.R (n_rst),
.S (1'b1),
.Q (crc_out[7])
);
DFFSR \crc_out_reg[8] (
.D (n30),
.CLK(clk),
.R (n_rst),
.S (1'b1),
.Q (crc_out[8])
);
DFFSR \crc_out_reg[9] (
.D (n28),
.CLK(clk),
.R (n_rst),
.S (1'b1),
.Q (crc_out[9])
);
DFFSR \crc_out_reg[10] (
.D (n26),
.CLK(clk),
.R (n_rst),
.S (1'b1),
.Q (crc_out[10])
);
DFFSR \crc_out_reg[11] (
.D (n34),
.CLK(clk),
.R (n_rst),
.S (1'b1),
.Q (crc_out[11])
);
DFFSR \crc_out_reg[12] (
.D (n36),
.CLK(clk),
.R (n_rst),
.S (1'b1),
.Q (crc_out[12])
);
DFFSR \crc_out_reg[13] (
.D (n42),
.CLK(clk),
.R (n_rst),
.S (1'b1),
.Q (crc_out[13])
);
DFFSR \crc_out_reg[14] (
.D (n18),
.CLK(clk),
.R (n_rst),
.S (1'b1),
.Q (crc_out[14])
);
INVX1 U2 (
.A(n1),
.Y(n16)
);
MUX2X1 U3 (
.B(crc_out[1]),
.A(crc_out[0]),
.S(crc_en),
.Y(n1)
);
INVX1 U4 (
.A(n2),
.Y(n20)
);
MUX2X1 U5 (
.B(crc_out[2]),
.A(crc_out[1]),
.S(crc_en),
.Y(n2)
);
INVX1 U6 (
.A(n3),
.Y(n22)
);
MUX2X1 U7 (
.B(crc_out[5]),
.A(crc_out[4]),
.S(crc_en),
.Y(n3)
);
INVX1 U8 (
.A(n4),
.Y(n24)
);
MUX2X1 U9 (
.B(crc_out[6]),
.A(crc_out[5]),
.S(crc_en),
.Y(n4)
);
INVX1 U10 (
.A(n5),
.Y(n28)
);
MUX2X1 U11 (
.B(crc_out[9]),
.A(crc_out[8]),
.S(crc_en),
.Y(n5)
);
MUX2X1 U12 (
.B(n6),
.A(n7),
.S(crc_en),
.Y(n34)
);
INVX1 U13 (
.A(crc_out[11]),
.Y(n6)
);
INVX1 U14 (
.A(n8),
.Y(n36)
);
MUX2X1 U15 (
.B(crc_out[12]),
.A(crc_out[11]),
.S(crc_en),
.Y(n8)
);
INVX1 U16 (
.A(n9),
.Y(n42)
);
MUX2X1 U17 (
.B(crc_out[13]),
.A(crc_out[12]),
.S(crc_en),
.Y(n9)
);
MUX2X1 U18 (
.B(n10),
.A(data),
.S(crc_en),
.Y(n46)
);
INVX1 U19 (
.A(crc_out[0]),
.Y(n10)
);
MUX2X1 U20 (
.B(n11),
.A(crc_out[2]),
.S(crc_en),
.Y(n40)
);
INVX1 U21 (
.A(n12),
.Y(n38)
);
MUX2X1 U22 (
.B(crc_out[4]),
.A(n11),
.S(crc_en),
.Y(n12)
);
INVX1 U23 (
.A(crc_out[3]),
.Y(n11)
);
MUX2X1 U24 (
.B(n13),
.A(crc_out[6]),
.S(crc_en),
.Y(n32)
);
INVX1 U25 (
.A(crc_out[7]),
.Y(n13)
);
MUX2X1 U26 (
.B(n14),
.A(crc_out[7]),
.S(crc_en),
.Y(n30)
);
INVX1 U27 (
.A(crc_out[8]),
.Y(n14)
);
MUX2X1 U28 (
.B(n7),
.A(crc_out[9]),
.S(crc_en),
.Y(n26)
);
INVX1 U29 (
.A(crc_out[10]),
.Y(n7)
);
MUX2X1 U30 (
.B(n15),
.A(crc_out[13]),
.S(crc_en),
.Y(n18)
);
INVX1 U31 (
.A(crc_out[14]),
.Y(n15)
);
endmodule
| 6.880719 |
module tx_sr (
clk,
n_rst,
tx_enable,
load_enable,
tx_data,
tx_out
);
input [31:0] tx_data;
input clk, n_rst, tx_enable, load_enable;
output tx_out;
flex_pts_sr_NUM_BITS32_SHIFT_MSB1 TX_SR (
.clk(clk),
.n_rst(n_rst),
.shift_enable(tx_enable),
.load_enable(load_enable),
.parallel_in(tx_data),
.serial_out(tx_out)
);
endmodule
| 7.061752 |
module rx_sr (
clk,
n_rst,
rx_enable,
can_bus_data,
rx_data
);
output [31:0] rx_data;
input clk, n_rst, rx_enable, can_bus_data;
flex_stp_sr_NUM_BITS32_SHIFT_MSB1 RX_SR (
.clk(clk),
.n_rst(n_rst),
.shift_enable(rx_enable),
.serial_in(can_bus_data),
.parallel_out(rx_data)
);
endmodule
| 6.664377 |
module AHB2CAN_top_t (
HCLK,
HRESETn,
HWRITE,
HSEL,
HADDR,
HWDATA,
HTRANS,
HBURST,
HSIZE,
HRDATA,
HRESP,
HREADYOUT,
rx_data,
tx_data
);
input [31:0] HADDR;
input [31:0] HWDATA;
input [1:0] HTRANS;
input [2:0] HBURST;
input [2:0] HSIZE;
output [31:0] HRDATA;
input HCLK, HRESETn, HWRITE, HSEL, rx_data;
output HRESP, HREADYOUT, tx_data;
wire slave_wait, renable, wenable, sensor_fifo_full, sensor_fifo_empty,
command_fifo_full, command_fifo_empty, sensor_read, sensor_write,
command_read, command_write, read_fifo, write_fifo;
wire [31:0] sensor_data;
wire [15:0] address;
wire [15:0] command_data;
wire [ 2:0] data_size;
wire [ 2:0] burst_size;
wire [31:0] command_rdata;
wire [31:0] command_wdata;
wire [31:0] sensor_rdata;
wire [31:0] sensor_wdata;
wire [31:0] CAN_rx_data;
wire [31:0] CAN_tx_data;
AHB_Slave AHBS (
.HCLK(HCLK),
.HRESETn(HRESETn),
.HWRITE(HWRITE),
.HSEL(HSEL),
.HADDR(HADDR),
.HWDATA(HWDATA),
.HTRANS(HTRANS),
.HBURST(HBURST),
.HSIZE(HSIZE),
.HRDATA(HRDATA),
.HRESP(HRESP),
.HREADYOUT(HREADYOUT),
.sensor_data(sensor_data),
.slave_wait(slave_wait),
.command_data(command_data),
.address(address),
.renable(renable),
.wenable(wenable),
.data_size(data_size),
.burst_size(burst_size)
);
Control_Unit CU (
.clk(HCLK),
.n_rst(HRESETn),
.command_data(command_data),
.address(address),
.renable(renable),
.wenable(wenable),
.data_size(data_size),
.burst_size(burst_size),
.sensor_data(sensor_data),
.slave_wait(slave_wait),
.sensor_fifo_full(sensor_fifo_full),
.sensor_fifo_empty(sensor_fifo_empty),
.sensor_read(sensor_read),
.sensor_write(sensor_write),
.command_fifo_full(command_fifo_full),
.command_fifo_empty(command_fifo_empty),
.command_read(command_read),
.command_write(command_write),
.command_rdata(command_rdata),
.sensor_rdata(sensor_rdata),
.command_wdata(command_wdata),
.sensor_wdata(sensor_wdata),
.rx_data(CAN_rx_data),
.read_fifo(read_fifo),
.write_fifo(write_fifo),
.tx_data(CAN_tx_data)
);
Sensor_FIFO_storage SFIFO (
.write_clk(HCLK),
.read_clk(HCLK),
.n_rst(HRESETn),
.write_command(sensor_write),
.read_command(sensor_read),
.write_data(sensor_wdata),
.fifo_full(sensor_fifo_full),
.fifo_empty(sensor_fifo_empty),
.read_data(sensor_rdata)
);
Command_FIFO_storage CFIFO (
.write_clk(HCLK),
.read_clk(HCLK),
.n_rst(HRESETn),
.write_command(command_write),
.read_command(command_read),
.write_data(command_wdata),
.fifo_full(command_fifo_full),
.fifo_empty(command_fifo_empty),
.read_data(command_rdata)
);
can_register CANbus (
.clk(HCLK),
.n_rst(HRESETn),
.command(CAN_tx_data),
.rxd(rx_data),
.txd(tx_data),
.write_fifo(write_fifo),
.read_fifo(read_fifo),
.send_data(CAN_rx_data)
);
endmodule
| 6.737189 |
module AHB2GPIO (
input wire HCLK,
input wire HRESETn,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [31:0] HWDATA,
input wire HWRITE,
input wire HSEL,
input wire HREADY,
output wire HREADYOUT,
output wire [31:0] HRDATA,
// GPIO Ports
input wire [15:0] GPIOIN,
output wire [15:0] GPIOOUT,
output wire [15:0] GPIOPU,
output wire [15:0] GPIOPD,
output wire [15:0] GPIOEN
);
reg [15:0] gpio_data, gpio_data_next; // Address 0: Port Data
reg [15:0] gpio_dir; // Address 4: Port direction; 1:i/p, 0:o/p
reg [15:0]
gpio_pu,
gpio_pd; // PU (Address: 8) & PD (Address: 16) enable registers @ 8 and 16 respectively
assign GPIOEN = gpio_dir;
assign GPIOPU = gpio_pu;
assign GPIOPD = gpio_pd;
assign GPIOOUT = gpio_data;
assign HREADYOUT = 1'b1;
reg [31:0] last_HADDR;
reg [1:0] last_HTRANS;
reg last_HWRITE;
reg last_HSEL;
always @(posedge HCLK) begin
if (HREADY) begin
last_HADDR <= HADDR;
last_HTRANS <= HTRANS;
last_HWRITE <= HWRITE;
last_HSEL <= HSEL;
end
end
// The GPIO Direction Register (0: o/p, 1: i/p)
always @(posedge HCLK, negedge HRESETn) begin
if (!HRESETn) gpio_dir <= 16'b0;
else if ((last_HADDR[2]) & last_HSEL & last_HWRITE & last_HTRANS[1]) gpio_dir <= HWDATA[15:0];
end
// The GPIO PU Register
always @(posedge HCLK, negedge HRESETn) begin
if (!HRESETn) gpio_pu <= 16'b0;
else if ((last_HADDR[3]) & last_HSEL & last_HWRITE & last_HTRANS[1]) gpio_pu <= HWDATA[15:0];
end
// The GPIO PD Register
always @(posedge HCLK, negedge HRESETn) begin
if (!HRESETn) gpio_pd <= 16'b0;
else if ((last_HADDR[4]) & last_HSEL & last_HWRITE & last_HTRANS[1]) gpio_pd <= HWDATA[15:0];
end
// The GPIO Data
always @(posedge HCLK, negedge HRESETn) begin
if (!HRESETn) gpio_data <= 16'b0;
else if ((last_HADDR[7:0] == 8'd0) & last_HSEL & last_HWRITE & last_HTRANS[1])
gpio_data <= gpio_data_next;
end
integer i;
always @* begin
for (i = 0; i < 16; i = i + 1) begin
if (gpio_dir[i] == 1'b1) gpio_data_next[i] = GPIOIN[i];
else if ((last_HADDR[7:0] == 8'd0) & last_HSEL & last_HWRITE & last_HTRANS[1])
gpio_data_next[i] = HWDATA[i];
else gpio_data_next[i] = gpio_data[i];
end
end
assign HRDATA[31:0] = (~last_HADDR[2]) ? {16'h0, GPIOIN} : {16'h0, gpio_dir};
endmodule
| 6.514349 |
module AHB2LED (
//AHBLITE INTERFACE
//Slave Select Signals
input wire HSEL,
//Global Signal
input wire HCLK,
input wire HRESETn,
//Address, Control & Write Data
input wire HREADY,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire HWRITE,
input wire [2:0] HSIZE,
input wire [31:0] HWDATA,
// Transfer Response & Read Data
output wire HREADYOUT,
output wire [31:0] HRDATA,
//LED Output
output wire [7:0] LED
);
//Address Phase Sampling Registers
reg rHSEL;
reg [31:0] rHADDR;
reg [1:0] rHTRANS;
reg rHWRITE;
reg [2:0] rHSIZE;
reg [7:0] rLED;
//Address Phase Sampling
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
rHSEL <= 1'b0;
rHADDR <= 32'h0;
rHTRANS <= 2'b00;
rHWRITE <= 1'b0;
rHSIZE <= 3'b000;
end else if (HREADY) begin
rHSEL <= HSEL;
rHADDR <= HADDR;
rHTRANS <= HTRANS;
rHWRITE <= HWRITE;
rHSIZE <= HSIZE;
end
end
//Data Phase data transfer
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) rLED <= 8'b0000_0000;
else if (rHSEL & rHWRITE & rHTRANS[1]) rLED <= HWDATA[7:0];
end
//Transfer Response
assign HREADYOUT = 1'b1; //Single cycle Write & Read. Zero Wait state operations
//Read Data
assign HRDATA = {24'h0000_00, rLED};
assign LED = rLED;
endmodule
| 6.594381 |
module AHB2MEM #(
parameter MEMWIDTH = 16
) // SIZE = 64KB = 8 KWords
(
//AHBLITE INTERFACE
//Slave Select Signals
input wire HSEL,
//Global Signal
input wire HCLK,
input wire HRESETn,
//Address, Control & Write Data
input wire HREADY,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire HWRITE,
input wire [2:0] HSIZE,
input wire [31:0] HWDATA,
// Transfer Response & Read Data
output wire HREADYOUT,
output wire [31:0] HRDATA
);
assign HREADYOUT = 1'b1; // Always ready
// Registers to store Adress Phase Signals
reg APhase_HSEL;
reg APhase_HWRITE;
reg [1:0] APhase_HTRANS;
reg [31:0] APhase_HADDR;
reg [2:0] APhase_HSIZE;
// Memory Array
reg [31:0] memory[0:(2**(MEMWIDTH-2)-1)];
initial begin
//$readmemh("../Software/code.hex", memory);
end
// Sample the Address Phase
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
APhase_HSEL <= 1'b0;
APhase_HWRITE <= 1'b0;
APhase_HTRANS <= 2'b00;
APhase_HADDR <= 32'h0;
APhase_HSIZE <= 3'b000;
end else if (HREADY) begin
APhase_HSEL <= HSEL;
APhase_HWRITE <= HWRITE;
APhase_HTRANS <= HTRANS;
APhase_HADDR <= HADDR;
APhase_HSIZE <= HSIZE;
end
end
// Decode the bytes lanes depending on HSIZE & HADDR[1:0]
wire tx_byte = ~APhase_HSIZE[1] & ~APhase_HSIZE[0];
wire tx_half = ~APhase_HSIZE[1] & APhase_HSIZE[0];
wire tx_word = APhase_HSIZE[1];
wire byte_at_00 = tx_byte & ~APhase_HADDR[1] & ~APhase_HADDR[0];
wire byte_at_01 = tx_byte & ~APhase_HADDR[1] & APhase_HADDR[0];
wire byte_at_10 = tx_byte & APhase_HADDR[1] & ~APhase_HADDR[0];
wire byte_at_11 = tx_byte & APhase_HADDR[1] & APhase_HADDR[0];
wire half_at_00 = tx_half & ~APhase_HADDR[1];
wire half_at_10 = tx_half & APhase_HADDR[1];
wire word_at_00 = tx_word;
wire byte0 = word_at_00 | half_at_00 | byte_at_00;
wire byte1 = word_at_00 | half_at_00 | byte_at_01;
wire byte2 = word_at_00 | half_at_10 | byte_at_10;
wire byte3 = word_at_00 | half_at_10 | byte_at_11;
// Writing to the memory
always @(posedge HCLK) begin
if (APhase_HSEL & APhase_HWRITE & APhase_HTRANS[1]) begin
if (byte0) memory[APhase_HADDR[MEMWIDTH:2]][7:0] <= HWDATA[7:0];
if (byte1) memory[APhase_HADDR[MEMWIDTH:2]][15:8] <= HWDATA[15:8];
if (byte2) memory[APhase_HADDR[MEMWIDTH:2]][23:16] <= HWDATA[23:16];
if (byte3) memory[APhase_HADDR[MEMWIDTH:2]][31:24] <= HWDATA[31:24];
end
end
// Reading from memory
// The first 2 words must be known @ Boot Time
wire [31:0] mem_word_0 = 32'h0; // SP
wire [31:0] mem_word_1 = 32'h0; // RESET Vector -- Should point to External Flash
assign HRDATA = (APhase_HADDR[MEMWIDTH:2]==30'h0) ? mem_word_0 :
(APhase_HADDR[MEMWIDTH:2]==30'h1) ? mem_word_1 :
memory[APhase_HADDR[MEMWIDTH:2]];
// Diagnostic Signal out
// assign LED = memory[0][7:0];
endmodule
| 6.873488 |
module AHB2MEM #(
parameter MEMWIDTH = 12
) // SIZE = 1KB = 256 Words
(
//AHBLITE INTERFACE
//Slave Select Signals
input wire HSEL,
//Global Signal
input wire HCLK,
input wire HRESETn,
//Address, Control & Write Data
input wire HREADY,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire HWRITE,
input wire [2:0] HSIZE,
input wire [31:0] HWDATA,
// Transfer Response & Read Data
output wire HREADYOUT,
output wire [31:0] HRDATA,
// output wire [7:0] deLED
//LED Output
output wire [7:0] LED
);
assign HREADYOUT = 1'b1; // Always ready
// Registers to store Adress Phase Signals
reg APhase_HSEL;
reg APhase_HWRITE;
reg [1:0] APhase_HTRANS;
reg [31:0] APhase_HADDR;
reg [2:0] APhase_HSIZE;
// Memory Array
reg [31:0] memory[0:(2**(MEMWIDTH-2)-1)];
initial begin
memory[0] = 'h000003FC;
memory[1] = 'h00000081;
memory[2] = 'h00000000;
memory[3] = 'h00000000;
memory[4] = 'h00000000;
memory[5] = 'h00000000;
memory[6] = 'h00000000;
memory[7] = 'h00000000;
memory[8] = 'h00000000;
memory[9] = 'h00000000;
memory[10] = 'h00000000;
memory[11] = 'h00000000;
memory[12] = 'h00000000;
memory[13] = 'h00000000;
memory[14] = 'h00000000;
memory[15] = 'h00000000;
memory[16] = 'h00000000;
memory[17] = 'h00000000;
memory[18] = 'h00000000;
memory[19] = 'h00000000;
memory[20] = 'h00000000;
memory[21] = 'h00000000;
memory[22] = 'h00000000;
memory[23] = 'h00000000;
memory[24] = 'h00000000;
memory[25] = 'h00000000;
memory[26] = 'h00000000;
memory[27] = 'h00000000;
memory[28] = 'h00000000;
memory[29] = 'h00000000;
memory[30] = 'h00000000;
memory[31] = 'h00000000;
memory[32] = 'h20554906;
memory[33] = 'h48066008;
memory[34] = 'hD1FD3801;
memory[35] = 'h20AA4903;
memory[36] = 'h48036008;
memory[37] = 'hD1FD3801;
memory[38] = 'h0000E7F2;
memory[39] = 'h50000000;
memory[40] = 'h002FFFFF;
memory[42] = 'h002FFFFF;
end
// deLED <= memory[0][0:7];
// Sample the Address Phase
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
APhase_HSEL <= 1'b0;
APhase_HWRITE <= 1'b0;
APhase_HTRANS <= 2'b00;
APhase_HADDR <= 32'h0;
APhase_HSIZE <= 3'b000;
end else if (HREADY) begin
APhase_HSEL <= HSEL;
APhase_HWRITE <= HWRITE;
APhase_HTRANS <= HTRANS;
APhase_HADDR <= HADDR;
APhase_HSIZE <= HSIZE;
end
end
// Decode the bytes lanes depending on HSIZE & HADDR[1:0]
wire tx_byte = ~APhase_HSIZE[1] & ~APhase_HSIZE[0];
wire tx_half = ~APhase_HSIZE[1] & APhase_HSIZE[0];
wire tx_word = APhase_HSIZE[1];
wire byte_at_00 = tx_byte & ~APhase_HADDR[1] & ~APhase_HADDR[0];
wire byte_at_01 = tx_byte & ~APhase_HADDR[1] & APhase_HADDR[0];
wire byte_at_10 = tx_byte & APhase_HADDR[1] & ~APhase_HADDR[0];
wire byte_at_11 = tx_byte & APhase_HADDR[1] & APhase_HADDR[0];
wire half_at_00 = tx_half & ~APhase_HADDR[1];
wire half_at_10 = tx_half & APhase_HADDR[1];
wire word_at_00 = tx_word;
wire byte0 = word_at_00 | half_at_00 | byte_at_00;
wire byte1 = word_at_00 | half_at_00 | byte_at_01;
wire byte2 = word_at_00 | half_at_10 | byte_at_10;
wire byte3 = word_at_00 | half_at_10 | byte_at_11;
// Writing to the memory
always @(posedge HCLK) begin
if (APhase_HSEL & APhase_HWRITE & APhase_HTRANS[1]) begin
if (byte0) memory[APhase_HADDR[MEMWIDTH:2]][7:0] <= HWDATA[7:0];
if (byte1) memory[APhase_HADDR[MEMWIDTH:2]][15:8] <= HWDATA[15:8];
if (byte2) memory[APhase_HADDR[MEMWIDTH:2]][23:16] <= HWDATA[23:16];
if (byte3) memory[APhase_HADDR[MEMWIDTH:2]][31:24] <= HWDATA[31:24];
end
end
// Reading from memory
assign HRDATA = memory[APhase_HADDR[MEMWIDTH:2]];
// Diagnostic Signal out
assign LED = memory[35][7:0];
endmodule
| 6.873488 |
module ahb2ocp_ram (
clk,
rst_n,
rd_e,
addr,
rdata,
wr_e,
wdata,
be,
cs
);
// Default parameters
parameter WORDS = 8;
parameter DATA_SIZE = 1;
parameter ADDR_SIZE = 3;
input clk; // clock synchronizes all read inputs
input rst_n; // asynchronous reset in rclk domain
input rd_e; // '0' for read
input [ADDR_SIZE-1:0] addr; // address for read
input wr_e; // '0' for write
input [DATA_SIZE-1:0] wdata; // data to be written
input [DATA_SIZE-1:0] be; // bit enables for writing data
input cs; // chip select signal
output [DATA_SIZE-1:0] rdata; // read data
reg [ADDR_SIZE-1:0] rd_addr_q; // Read address latched
reg [DATA_SIZE-1:0] mem[0:WORDS-1]; // Memory array
reg [DATA_SIZE-1:0] tmp_data; // Temporary data used when computing write data
// Data appears after 1 clock edge so registering address
always @(posedge clk or negedge rst_n) begin
if (!rst_n & cs) rd_addr_q <= {ADDR_SIZE{1'b0}};
else if (rd_e & cs) rd_addr_q <= addr;
end
always @(posedge clk) begin
if (wr_e & cs) begin
tmp_data = mem[addr];
mem[addr] <= (tmp_data & ~be) | (wdata & be);
end
end
assign rdata = mem[rd_addr_q];
// Check for errors
always @(posedge clk) begin
begin
if (cs & (addr > WORDS && wr_e))
$display(
"%t:%m:ERROR: ",
$time,
"write address out of range, MAX = ",
WORDS,
" Attempted = ",
addr
);
end
end
endmodule
| 8.316932 |
module AHB2RAM #(
parameter MEMWIDTH = 15
) // Size = 32KB
(
input wire HSEL,
input wire HCLK,
input wire HRESETn,
input wire HREADY,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire HWRITE,
input wire [ 2:0] HSIZE,
input wire [31:0] HWDATA,
output wire HREADYOUT,
output wire [31:0] HRDATA
);
assign HREADYOUT = 1'b1; // Always ready
// Memory Array
reg [31:0] memory [0:(2**(MEMWIDTH-2)-1)];
// Registers to store Adress Phase Signals
reg [31:0] hwdata_mask;
reg we;
reg [31:0] buf_hwaddr;
// kaito part
reg [31:0] HRDATA_tmp;
reg HSEL_tmp;
always @(posedge HCLK) begin
/* #10 */ HSEL_tmp <= HSEL;
end
assign HRDATA = HRDATA_tmp;
/*
reg HWRITE_tmp;
always @(posedge HCLK) begin
if(HREADY) begin
HSEL_tmp <= HSEL;
HWRITE_tmp <= HWRITE;
end
end
assign HRDATA = HSEL_tmp ? HRDATA_tmp : 32'hzzzz_zzzz;
*/
// Sample the Address Phase
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
we <= 1'b0;
buf_hwaddr <= 32'h0;
end else if (HREADY) begin
we <= HSEL & HWRITE & HTRANS[1];
buf_hwaddr <= HADDR;
casez (HSIZE[1:0])
2'b1?: hwdata_mask <= 32'hFFFFFFFF; // Word write
2'b01: hwdata_mask <= (32'h0000FFFF << (16 * HADDR[1])); // Halfword write
2'b00: hwdata_mask <= (32'h000000FF << (8 * HADDR[1:0])); // Byte write
endcase
end
end
// Read and Write Memory
always @(posedge HCLK) begin
if (we) memory[buf_hwaddr[MEMWIDTH:2]] <= (HWDATA & hwdata_mask) | (HRDATA & ~hwdata_mask);
HRDATA_tmp = memory[HADDR[MEMWIDTH:2]];
end
// always @(*) begin
// HRDATA_tmp <= memory[HADDR[MEMWIDTH:2]];
// end
endmodule
| 7.962486 |
module ahb2regbus (
//AHB IF
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [`AHB_ADDR_WIDTH - 1 : 0] HADDR,
input wire HWRITE,
input wire [1:0] HTRANS,
input wire [2:0] HBURST,
input wire [`AHB_DATA_WIDTH - 1 : 0] HWDATA,
output wire HREADY,
output reg [1:0] HRESP,
output wire [`AHB_DATA_WIDTH - 1 : 0] HRDATA,
//IP reg bus
input wire [`AHB_DATA_WIDTH - 1 : 0] ip_read_data,
output wire [`AHB_DATA_WIDTH - 1 : 0] ip_write_data,
output reg [`AHB_ADDR_WIDTH - 1 : 0] ip_addr,
output reg valid_reg_access,
output reg ip_wr1_rd0
);
parameter IP_REG_START_OFFSET = 12'h000;
parameter IP_REG_END_OFFSET = 12'h148;
parameter IP_OFFSET_RANGE_R = 11;
parameter IP_OFFSET_RANGE_L = 0;
//Logic Start
//IP register is always ready to receive any ahb transaction
assign HREADY = 1'b1;
wire valid_ahb_addr;
wire valid_ahb_ctrl;
wire valid_addr_phase;
assign valid_ahb_addr = HSEL && ((HADDR[IP_OFFSET_RANGE_R : IP_OFFSET_RANGE_L] >= IP_REG_START_OFFSET) && (HADDR[IP_OFFSET_RANGE_R : IP_OFFSET_RANGE_L] <= IP_REG_END_OFFSET));
assign valid_ahb_ctrl = HSEL && (HTRANS == `NONSEQ);
assign valid_addr_phase = valid_ahb_addr && valid_ahb_ctrl;
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
valid_reg_access <= 1'b0;
end else begin
if (valid_addr_phase) begin
valid_reg_access <= 1'b1;
end else begin
valid_reg_access <= 1'b0;
end
end
end
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
ip_addr <= {`AHB_ADDR_WIDTH{1'b0}};
ip_wr1_rd0 <= 1'b0;
end else begin
if (valid_addr_phase) begin
ip_addr <= HADDR;
ip_wr1_rd0 <= HWRITE;
end else begin
ip_addr <= {`AHB_ADDR_WIDTH{1'b0}};
ip_wr1_rd0 <= 1'b0;
end
end
end
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
HRESP <= `OKAY;
end else begin
if (HSEL && (!(valid_ahb_addr && valid_ahb_ctrl))) begin
HRESP <= `ERROR;
end else begin
HRESP <= `OKAY;
end
end
end
assign ip_write_data = HWDATA;
assign HRDATA = ip_read_data;
endmodule
| 6.922833 |
module AHB2ROM #(
parameter MEMWIDTH = 15
) // Size = 32KB
(
input wire HSEL,
input wire HCLK,
input wire HRESETn,
input wire HREADY,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire HWRITE,
input wire [ 2:0] HSIZE,
input wire [31:0] HWDATA,
output wire HREADYOUT,
output reg [31:0] HRDATA
);
assign HREADYOUT = 1'b1; // Always ready
// Memory Array
reg [31:0] memory[0:(2**(MEMWIDTH-2)-1)];
initial begin
(*rom_style="block"*) $readmemh("code.hex", memory);
end
// Registers to store Adress Phase Signals
reg [31:0] hwdata_mask;
reg we;
reg [31:0] buf_hwaddr;
// Sample the Address Phase
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
we <= 1'b0;
buf_hwaddr <= 32'h0;
end else if (HREADY) begin
we <= HSEL & HWRITE & HTRANS[1];
buf_hwaddr <= HADDR;
casez (HSIZE[1:0])
2'b1?: hwdata_mask <= 32'hFFFFFFFF; // Word write
2'b01: hwdata_mask <= (32'h0000FFFF << (16 * HADDR[1])); // Halfword write
2'b00: hwdata_mask <= (32'h000000FF << (8 * HADDR[1:0])); // Byte write
endcase
end
end
// Read and Write Memory
always @(posedge HCLK) begin
if (we) memory[buf_hwaddr[MEMWIDTH:2]] <= (HWDATA & hwdata_mask) | (HRDATA & ~hwdata_mask);
HRDATA = memory[HADDR[MEMWIDTH:2]];
end
endmodule
| 7.60337 |
module AHB2SLAVE #(
parameter PixelBitWidth = 8,
parameter Height = 32,
parameter Width = 32
) (
//AHBLITE INTERFACE
//Slave Select Signals
input wire HSEL,
//Global Signal
input wire HCLK,
input wire HRESETn,
//Address, Control & Write Data
input wire HREADY,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire HWRITE,
input wire [2:0] HSIZE,
input wire [31:0] HWDATA,
// Transfer Response & Read Data
output reg HREADYOUT,
output reg [31:0] HRDATA,
//init_image
input [7:0] init_image
);
reg AddressPhase_HSEL;
reg AddressPhase_HWRITE;
reg [1:0] AddressPhase_HTRANS;
reg [31:0] AddressPhase_HADDR;
reg [2:0] AddressPhase_HSIZE;
reg [PixelBitWidth - 1:0] Image[Height * Width - 1:0];
integer i;
//assign HREADYOUT = 1;
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
// reset
AddressPhase_HSEL <= 1'b0;
AddressPhase_HWRITE <= 1'b0;
AddressPhase_HTRANS <= 2'b00;
AddressPhase_HADDR <= 32'h0;
AddressPhase_HSIZE <= 3'b000;
HREADYOUT <= 0;
HRDATA <= 32'b0;
for (i = 0; i < Height * Width - 1; i = i + 1) begin
Image[i] <= init_image;
end
//Image <= init_image;
end else if (HREADY & HSEL) begin
AddressPhase_HSEL <= HSEL;
AddressPhase_HWRITE <= HWRITE;
AddressPhase_HTRANS <= HTRANS;
AddressPhase_HADDR <= HADDR;
AddressPhase_HSIZE <= HSIZE;
HREADYOUT <= 1;
//if being selected and read, load data to read data line. Next posedge of clk, master will read HRDATA
if (~HWRITE & HTRANS[1]) begin
HRDATA[31:24] <= Image[HADDR[10:1]][PixelBitWidth-1:0];
HRDATA[23:16] <= Image[HADDR[10:1]+1][PixelBitWidth-1:0];
HRDATA[15:8] <= Image[HADDR[10:1]+2][PixelBitWidth-1:0];
HRDATA[7:0] <= Image[HADDR[10:1]+3][PixelBitWidth-1:0];
end
end else begin
HREADYOUT <= 0;
AddressPhase_HSEL <= 1'b0;
AddressPhase_HWRITE <= 1'b0;
AddressPhase_HTRANS <= 2'b00;
AddressPhase_HADDR <= 32'h0;
AddressPhase_HSIZE <= 3'b000;
end
end
always @(posedge HCLK) begin
if (AddressPhase_HSEL & AddressPhase_HWRITE & AddressPhase_HTRANS[1]) begin
//write 4 bytes
Image[AddressPhase_HADDR[10:1]][PixelBitWidth-1:0] <= HWDATA[31:24];
Image[AddressPhase_HADDR[10:1]+1][PixelBitWidth-1:0] <= HWDATA[23:16];
Image[AddressPhase_HADDR[10:1]+2][PixelBitWidth-1:0] <= HWDATA[15:8];
Image[AddressPhase_HADDR[10:1]+3][PixelBitWidth-1:0] <= HWDATA[7:0];
end
end
endmodule
| 7.091131 |
module AHB2TUART (
//AHBLITE INTERFACE
//Slave Select Signals
input wire HSEL,
//Global Signal
input wire HCLK,
input wire HRESETn,
//Address, Control & Write Data
input wire HREADY,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire HWRITE,
input wire [2:0] HSIZE,
input wire [31:0] HWDATA,
// Transfer Response & Read Data
output wire HREADYOUT,
output wire [31:0] HRDATA,
//LED Output for debugging purposes
output wire [7:0] LED,
//UART Output
output wire UART_TX
);
//Address Phase Sampling Registers
reg rHSEL;
reg [31:0] rHADDR;
reg [1:0] rHTRANS;
reg rHWRITE;
reg [2:0] rHSIZE;
reg [7:0] rLED;
reg [7:0] rUartTxData;
reg rUartStart;
wire uartBusy;
/* Address Phase Sampling */
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
rHSEL <= 1'b0;
rHADDR <= 32'h0;
rHTRANS <= 2'b00;
rHWRITE <= 1'b0;
rHSIZE <= 3'b000;
end else if (HREADY) begin
rHSEL <= HSEL;
rHADDR <= HADDR;
rHTRANS <= HTRANS;
rHWRITE <= HWRITE;
rHSIZE <= HSIZE;
end
end
/* Data Phase data transfer */
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
rLED <= 8'b0000_0000;
rUartStart <= 1'b0;
end /* We are in the data phase, so take latched addr data */
else if (rHSEL & rHWRITE & rHTRANS[1] && (rHADDR[31:24] == 8'h50)) begin
rLED <= HWDATA[7:0];
rUartTxData <= HWDATA[7:0];
rUartStart <= 1'b1;
end else rUartStart <= 1'b0;
end
/* Instantiate Trivial UART */
tuart u_tuart (
.CLOCK(HCLK),
.DATA (rUartTxData),
.START(rUartStart),
.BUSY (uartBusy),
.TX (UART_TX)
);
//Transfer Response
assign HREADYOUT = 1'b1; //Single cycle Write & Read. Zero Wait state operations
//Read Data
assign HRDATA = {24'h0000_00, rLED};
assign LED = rLED;
endmodule
| 7.355591 |
module has to start at address 0.
It occupies 8 bytes (2 words) only
*/
//`default_nettype none
module AHB2TWROM
(
//AHBLITE INTERFACE
//Slave Select Signals
input wire HSEL,
//Global Signal
input wire HCLK,
input wire HRESETn,
//Address, Control & Write Data
input wire HREADY,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire HWRITE,
input wire [2:0] HSIZE,
input wire [31:0] HWDATA,
// Transfer Response & Read Data
output wire HREADYOUT,
output wire [31:0] HRDATA
);
assign HREADYOUT = 1'b1; // Always ready
// Registers to store Adress Phase Signals
reg APhase_HSEL;
reg APhase_HWRITE;
reg [1:0] APhase_HTRANS;
reg [31:0] APhase_HADDR;
reg [2:0] APhase_HSIZE;
// Change SP initial value based on the SoC SRAM configuration
// PC value has to do with teh startup code.
wire [31:0] SP = 32'h<%=SPAddress%>;
wire [31:0] PC = 32'h00000101;
// Sample the Address Phase
always @(posedge HCLK or negedge HRESETn)
begin
if(!HRESETn)
begin
APhase_HSEL <= 1'b0;
APhase_HWRITE <= 1'b0;
APhase_HTRANS <= 2'b00;
APhase_HADDR <= 32'h0;
APhase_HSIZE <= 3'b000;
end
else if(HREADY)
begin
APhase_HSEL <= HSEL;
APhase_HWRITE <= HWRITE;
APhase_HTRANS <= HTRANS;
APhase_HADDR <= HADDR;
APhase_HSIZE <= HSIZE;
end
end
// Reading from memory
assign HRDATA = APhase_HADDR[2] ? PC : SP;
endmodule
| 6.811751 |
module ahb2wb (
adr_o,
dat_o,
dat_i,
ack_i,
cyc_o,
we_o,
stb_o,
hclk,
hresetn,
haddr,
htrans,
hwrite,
hsize,
hburst,
hsel,
hwdata,
hrdata,
hresp,
hready,
clk_i,
rst_i
);
//parameter declaration
parameter AWIDTH = 32;
parameter DWIDTH = 32;
//**************************************
// input ports
//**************************************
//wishbone ports
input [DWIDTH-1:0] dat_i; // data input from wishbone slave
input ack_i; // acknowledment from wishbone slave
input clk_i;
input rst_i;
//AHB ports
input hclk; // clock
input hresetn; // active low reset
input [DWIDTH-1:0] hwdata; // data bus
input hwrite; // write/read enable
input [2:0] hburst; // burst type
input [2:0] hsize; // data size
input [1:0] htrans; // type of transfer
input hsel; // slave select
input [AWIDTH-1:0] haddr; // address bus
//**************************************
// output ports
//**************************************
//wishbone ports
output [AWIDTH-1:0] adr_o; // address to wishbone slave
output [DWIDTH-1:0] dat_o; // data output for wishbone slave
output cyc_o; // signal to indicate valid bus cycle
output we_o; // write enable
output stb_o; // strobe to indicate valid data transfer cycle
// AHB ports
output [DWIDTH-1:0] hrdata; // data output for wishbone slave
output [1:0] hresp; // response signal from slave
output hready; // slave ready
//**************************************
// inout ports
//**************************************
//**********************************************************************************
// datatype declaration
reg [ DWIDTH-1:0] hrdata;
reg hready;
reg [ 1:0] hresp;
reg stb_o;
wire we_o;
reg cyc_o;
wire [ AWIDTH-1:0] adr_o;
reg [ DWIDTH-1:0] dat_o;
// local memory registers
reg [AWIDTH-1 : 0] addr_temp;
reg hwrite_temp; // to hold write enable signal temporarily
//*******************************************************************
// AHB WISHBONE BRIDGE logic
//*******************************************************************
assign #2 we_o = hwrite_temp;
assign #2 adr_o = {addr_temp[AWIDTH-1:2]};
always @(posedge hclk) begin
if (!hresetn) begin
hresp <= 2'b00;
cyc_o <= 'b0;
stb_o <= 'b0;
addr_temp <= 'bx;
hwrite_temp <= 'bx;
dat_o <= 'bx;
end else if (hready & hsel) begin
case (hburst)
// single transfer
3'b000: begin
case (htrans)
// idle transfer type
2'b00: begin
cyc_o <= 'b0;
hresp <= 2'b00; // ok response
stb_o <= 'b0;
end
// busy transfer type
2'b01: begin
hresp <= 2'b00; // ok response
stb_o <= 'b0;
cyc_o <= 'b1;
end
// Non-Sequential
2'b10: begin
cyc_o <= 'b1;
stb_o <= 'b1;
addr_temp <= haddr;
hwrite_temp <= hwrite; // control signal stored that was received in address phase
end
endcase
end
default: cyc_o <= 'b0;
endcase
end else if (!hsel & hready) begin
cyc_o <= 'b0; //invalid bus transfer
end
end
// combinational logic - asynchronous read/write
always @(hwrite_temp or hwdata or dat_i or ack_i or hresetn or stb_o) begin
if (!hresetn) begin
hready <= 'b1;
end else begin
if (stb_o) hready <= ack_i;
else hready <= 'b1;
if (hwrite_temp) dat_o = hwdata;
else if (!hwrite_temp) hrdata = dat_i;
end
end
endmodule
| 9.917351 |
module AHB64_ATP ();
reg SysRST;
wire SysRST_N;
reg HCLK;
wire [35:0] HADDR;
wire HWRITE, HMASTLOCK;
wire [63:0] HWDATA;
wire [2:0] HSIZE;
wire [2:0] HBURST;
wire [3:0] HPROT;
wire [1:0] HTRANS;
//Master side ports (MUXed)
wire [63:0] HRDATAM;
wire HREADYM;
wire [1:0] HRESPM;
//AHB Periheral select
wire HSEL_BOOT;
wire HSEL_XTROM;
wire HSEL_MSRAM;
wire HSEL_DUMMY;
wire [63:0] HRDATA_BOOT;
wire [63:0] HRDATA_XTROM;
wire [63:0] HRDATA_MSRAM;
wire [63:0] HRDATA_DUMMY;
wire HREADY_BOOT;
wire HREADY_XTROM;
wire HREADY_MSRAM;
wire HREADY_DUMMY;
wire [1:0] HRESP_BOOT;
wire [1:0] HRESP_XTROM;
wire [1:0] HRESP_MSRAM;
wire [1:0] HRESP_DUMMY;
//Initialization and stimulation source block
initial begin
#0 HCLK = 0;
SysRST = 1;
#10 SysRST = 0;
end
assign SysRST_N = !SysRST;
always #5 HCLK = ~HCLK;
/*
always@(posedge HCLK or negedge SysRST_N) if(!SysRST_N)HADDR=36'h0;
else HADDR<=HADDR+17'h10000;
*/
prv464_top CPU1 (
.cacheability_block(32'b0), //可缓存的区，即物理地址[63:31],这个区间里的内存是可以缓存的
.clk(HCLK), //时钟信号，和AHB总线同步
.rst(SysRST), //复位信号，高有效，AHB总线的复位信号是空脚
.haddr(HADDR),
.hwrite(HWRITE),
.hsize(HSIZE),
.hburst(HBURST),
.hprot(HPROT),
.htrans(HTRANS),
.hmastlock(HMASTLOCK),
.hwdata(HWDATA),
.hready(HREADYM),
.hresp(HRESPM),
.hreset_n(SysRST_N),
.hrdata(HRDATAM),
//外部中断信号
.m_time_int(1'B0),
.m_soft_int(1'B0),
.m_ext_int(1'B0), //对M模式的中断信号
.s_ext_int(1'B0), //对S模式的中断信号
//外部时钟信号
.mtime(64'B0)
);
AHB_ROM BOOTROM1 (
HSEL_BOOT,
HADDR,
HWRITE,
HTRANS,
HSIZE,
HBURST,
HWDATA,
SysRST_N,
HCLK,
HMASTLOCK,
HREADY_BOOT,
HRESP_BOOT,
HRDATA_BOOT
);
AHB_ESRAM MSRAM1 (
HSEL_MSRAM,
HADDR,
HWRITE,
HTRANS,
HSIZE,
HBURST,
HWDATA,
SysRST_N,
HCLK,
HMASTLOCK,
HREADY_MSRAM,
HRESP_MSRAM,
HRDATA_MSRAM
);
AHB_DUMMY XTROM1 (
HSEL_XTROM,
HADDR,
HWRITE,
HTRANS,
HSIZE,
HBURST,
HWDATA,
SysRST_N,
HCLK,
HMASTLOCK,
HREADY_XTROM,
HRESP_XTROM,
HRDATA_XTROM
); //eXTernal SPI flash ROM leave blank
//AHB Related Modules
ahb_decoder DEC1 (
.HADDR (HADDR),
.HSELx0(HSEL_BOOT),
.HSELx1(HSEL_XTROM),
.HSELx2(HSEL_MSRAM),
.HSELx7(HSEL_DUMMY)
);
ahb_mux_s2m AHBMUX1 (
.HCLK(HCLK),
.HRESETn(SysRST_N),
.HRDATAx0(HRDATA_BOOT),
.HRDATAx1(HRDATA_XTROM),
.HRDATAx2(HRDATA_MSRAM),
.HRDATAx7(HRDATA_DUMMY),
.HSELx0(HSEL_BOOT),
.HSELx1(HSEL_XTROM),
.HSELx2(HSEL_MSRAM),
.HSELx3(1'b0),
.HSELx4(1'b0),
.HSELx5(1'b0),
.HSELx6(1'b0),
.HSELx7(HSEL_DUMMY),
.HREADYx0(HREADY_BOOT),
.HREADYx1(HREADY_XTROM),
.HREADYx2(HREADY_MSRAM),
.HREADYx7(HREADY_DUMMY),
.HRESPx0(HRESP_BOOT),
.HRESPx7(HRESP_XTROM),
.HRESPx1(HRESP_MSRAM),
.HRESPx2(HRESP_DUMMY),
.HREADY(HREADYM),
.HRESP(HRESPM),
.HRDATA(HRDATAM)
);
AHB_DUMMY DUMMY1 (
HSEL_DUMMY,
HADDR,
HWRITE,
HTRANS,
HSIZE,
HBURST,
HWDATA,
SysRST_N,
HCLK,
HMASTLOCK,
HREADY_DUMMY,
HRESP_DUMMY,
HRDATA_DUMMY
);
always @(HADDR)
if (HADDR == 36'hF55AAAA55) begin
#5 $monitor("Simulation Successfully Finished");
#5 $stop; //Stop Condition
end else if (HADDR == 36'hFAA5555AA) begin
#5 $monitor("Simulation Failed");
#5 $stop; //Stop Condition
end
endmodule
| 6.513614 |
module AHB7SEGDEC (
//Input
input wire HCLK,
input wire HRESETn,
input wire [31:0] HADDR,
input wire [31:0] HWDATA,
input wire [1:0] HTRANS,
input wire HWRITE,
input wire HSEL,
input wire HREADY,
//Output
output [31:0] HRDATA,
output HREADYOUT,
//7segment displa
output [6:0] seg,
output [3:0] an,
output dp
);
localparam [3:0] DIGIT1_ADDR = 4'h0;
localparam [3:0] DIGIT2_ADDR = 4'h4;
localparam [3:0] DIGIT3_ADDR = 4'h8;
localparam [3:0] DIGIT4_ADDR = 4'hC;
reg last_HWRITE;
reg [31:0] last_HADDR;
reg last_HSEL;
reg [1:0] last_HTRANS;
reg [7:0] DIGIT1 = 8'hA;
reg [7:0] DIGIT2 = 8'hB;
reg [7:0] DIGIT3 = 8'hC;
reg [7:0] DIGIT4 = 8'hD;
assign HREADYOUT = 1'b1; //Always ready
always @(posedge HCLK)
if (HREADY) begin
last_HWRITE <= HWRITE;
last_HSEL <= HSEL;
last_HADDR <= HADDR;
last_HTRANS <= HTRANS;
end
always @(posedge HCLK, negedge HRESETn) begin
if (!HRESETn) begin
DIGIT1 <= 7'b0_0101;
DIGIT2 <= 7'b0_1110;
DIGIT3 <= 7'b0_0000;
DIGIT4 <= 7'b0_0001;
end else if (last_HWRITE & last_HSEL & last_HTRANS[1]) begin
if (last_HADDR[3:0] == DIGIT1_ADDR) DIGIT1 <= HWDATA[7:0];
else if (last_HADDR[3:0] == DIGIT2_ADDR) DIGIT2 <= HWDATA[7:0];
else if (last_HADDR[3:0] == DIGIT3_ADDR) DIGIT3 <= HWDATA[7:0];
else if (last_HADDR[3:0] == DIGIT4_ADDR) DIGIT4 <= HWDATA[7:0];
end
end
assign HRDATA = (last_HADDR[3:0] == DIGIT1_ADDR) ? {24'h000_0000,DIGIT1} :
(last_HADDR[3:0] == DIGIT2_ADDR) ? {24'h000_0000,DIGIT2} :
(last_HADDR[3:0] == DIGIT3_ADDR) ? {24'h000_0000,DIGIT3} :
(last_HADDR[3:0] == DIGIT4_ADDR) ? {24'h000_0000,DIGIT4} :
32'h0000_0000;
reg [31:0] counter;
reg [ 3:0] ring = 4'b0001;
//reg [3:0] ring;
wire [ 7:0] code;
wire [ 6:0] seg_out;
assign seg = ~seg_out;
assign an = ~ring;
//assign seg = 7'b0101010;
//assign an = 4'b1010;
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) counter <= 32'h0000_0000;
else counter <= counter + 1'b1;
end
always @(posedge counter[15] or negedge HRESETn) begin
if (!HRESETn) ring <= 4'b0001;
else ring <= {ring[2:0], ring[3]};
end
assign code =
(ring == 4'b0001) ? DIGIT1[7:0] :
(ring == 4'b0010) ? DIGIT2[7:0] :
(ring == 4'b0100) ? DIGIT3[7:0] :
(ring == 4'b1000) ? DIGIT4[7:0] :
4'b1_1110;
assign dp = ~code[7];
parameter A = 7'b0000001;
parameter B = 7'b0000010;
parameter C = 7'b0000100;
parameter D = 7'b0001000;
parameter E = 7'b0010000;
parameter F = 7'b0100000;
parameter G = 7'b1000000;
assign seg_out =
(code[6:0] == 7'h0) ? A|B|C|D|E|F :
(code[6:0] == 7'h1) ? B|C :
(code[6:0] == 7'h2) ? A|B|G|E|D :
(code[6:0] == 7'h3) ? A|B|C|D|G :
(code[6:0] == 7'h4) ? F|B|G|C :
(code[6:0] == 7'h5) ? A|F|G|C|D :
(code[6:0] == 7'h6) ? A|F|G|C|D|E :
(code[6:0] == 7'h7) ? A|B|C :
(code[6:0] == 7'h8) ? A|B|C|D|E|F|G :
(code[6:0] == 7'h9) ? A|B|C|D|F|G :
(code[6:0] == 7'ha) ? A|F|B|G|E|C :
(code[6:0] == 7'hb) ? F|G|C|D|E :
(code[6:0] == 7'hc) ? G|E|D :
(code[6:0] == 7'hd) ? B|C|G|E|D :
(code[6:0] == 7'he) ? A|F|G|E|D :
(code[6:0] == 7'hf) ? A|F|G|E :
(code[6:0] == 7'hf) ? A|F|G|E :
(code[6:0] == 7'h10) ? A|B|C|D|E|F|G : //0x10 = Blank
(code[6:0] == 7'h11) ? G : //0x10 = -
(code[6:0] == 7'h12) ? A : //0x10 = _
(code[6:0] == 7'h13) ? D : //0x10 = _
7'b000_0000;
endmodule
| 7.503795 |
module AHB7SEGDEC (
//AHBLITE INTERFACE
//Slave Select Signals
input wire HSEL,
//Global Signal
input wire HCLK,
input wire HRESETn,
//Address, Control & Write Data
input wire HREADY,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire HWRITE,
input wire [2:0] HSIZE,
input wire [31:0] HWDATA,
// Transfer Response & Read Data
output wire HREADYOUT,
output wire [31:0] HRDATA,
//7segment displa
output reg [6:0] seg,
output [7:0] an,
output dp
);
//Address Phase Sampling Registers
reg rHSEL;
reg [31:0] rHADDR;
reg [1:0] rHTRANS;
reg rHWRITE;
reg [2:0] rHSIZE;
//Address Phase Sampling
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
rHSEL <= 1'b0;
rHADDR <= 32'h0;
rHTRANS <= 2'b00;
rHWRITE <= 1'b0;
rHSIZE <= 3'b000;
end else begin
if (HREADY) begin
rHSEL <= HSEL;
rHADDR <= HADDR;
rHTRANS <= HTRANS;
rHWRITE <= HWRITE;
rHSIZE <= HSIZE;
end
end
end
//Data Phase data transfer
reg [31:0] DATA;
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) DATA <= 32'h12345678;
else begin
if (rHSEL & rHWRITE & rHTRANS[1]) DATA <= HWDATA[31:0];
end
end
//Transfer Response
assign HREADYOUT = 1'b1; //Single cycle Write & Read. Zero Wait state operations
//Read Data
assign HRDATA = DATA;
reg [15:0] counter;
reg [7:0] ring = 8'b00000001;
wire [3:0] code;
wire [6:0] seg_out;
reg scan_clk;
assign an = ring;
assign dp = 1'b1;
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
counter <= 16'h0000;
scan_clk <= 1'b0;
end else begin
if (counter == 16'h7000) begin
scan_clk <= ~scan_clk;
counter <= 16'h0000;
end else counter <= counter + 1'b1;
end
end
always @(posedge scan_clk or negedge HRESETn) begin
if (!HRESETn) ring <= 8'b00000001;
else ring <= {ring[6:0], ring[7]};
end
assign code =
(ring == 8'b00000001) ? DATA[3:0] :
(ring == 8'b00000010) ? DATA[7:4] :
(ring == 8'b00000100) ? DATA[11:8] :
(ring == 8'b00001000) ? DATA[15:12] :
(ring == 8'b00010000) ? DATA[19:16]:
(ring == 8'b00100000) ? DATA[23:20]:
(ring == 8'b01000000) ? DATA [27:24]:
(ring == 8'b10000000) ? DATA [31:28]:
8'b1111110;
always @(*)
case (code) //a-b-c-d-e-f-g
4'b0000: seg = 7'b00000001; //0
4'b0001: seg = 7'b1001111; //1
4'b0010: seg = 7'b0010010; //2
4'b0011: seg = 7'b0000110; //3
4'b0100: seg = 7'b1001100; //4
4'b0101: seg = 7'b0100100; //5
4'b0110: seg = 7'b0100000; //6
4'b0111: seg = 7'b0001111; //7
4'b1000: seg = 7'b0000000; //8
4'b1001: seg = 7'b0000100; //9
4'b1010: seg = 7'b0001000; //A
4'b1011: seg = 7'b1100000; //B
4'b1100: seg = 7'b0110001; //C
4'b1101: seg = 7'b1000010; //D
4'b1110: seg = 7'b0110000; //E
4'b1111: seg = 7'b0111000; //F
default: seg = 7'b1111111; //no display
endcase
endmodule
| 7.503795 |
module AHBDUMMY2 (
//Inputs
input wire HSEL,
input wire HCLK,
input wire HRESETn,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [31:0] HWDATA,
input wire HWRITE,
input wire HREADY,
//Output
output reg HREADYOUT,
output reg [31:0] HRDATA
);
//State parameters
localparam [1:0] st_idle = 2'b00;
localparam [1:0] st_wait = 2'b01;
localparam [1:0] st_rw = 2'b10;
//Register select parameters
localparam [3:0] REG0 = 4'h0;
localparam [3:0] REG1 = 4'h4;
localparam [3:0] REG2 = 4'h8;
localparam [3:0] REG3 = 4'hC;
//State machine registers
reg [1:0] current_state;
reg [1:0] next_state;
reg [3:0] wait_reg;
reg [3:0] wait_next;
reg HREADYOUT_next;
//Data Regs
reg [31:0] d_reg0;
reg [31:0] d_reg1;
reg [31:0] d_reg2;
reg [31:0] d_reg3;
//AHB-Lite Address Phase Regs
reg last_HSEL;
reg [31:0] last_HADDR;
reg last_HWRITE;
reg [1:0] last_HTRANS;
always @(posedge HCLK) begin
if (HREADY) begin
last_HSEL <= HSEL;
last_HADDR <= HADDR;
last_HWRITE <= HWRITE;
last_HTRANS <= HTRANS;
end
end
//State Machine
always @(posedge HCLK, negedge HRESETn) begin
if (!HRESETn) begin
current_state <= st_idle;
HREADYOUT <= 1'b0;
wait_reg <= 4'h0;
end else begin
current_state <= next_state;
HREADYOUT <= HREADYOUT_next;
wait_reg <= wait_next;
end
end
//Next State Logic
always @* begin
next_state = current_state;
HREADYOUT_next = 1'b0;
wait_next = wait_reg;
case (current_state)
st_idle:
if (HSEL & HREADY) begin
next_state = st_wait;
case (HADDR[3:0])
REG0: wait_next = 4'h0;
REG1: wait_next = 4'h4;
REG2: wait_next = 4'h8;
REG3: wait_next = 4'hC;
default: wait_next = 4'h0;
endcase
end
st_wait:
if (wait_reg == 0) begin
next_state = st_idle;
HREADYOUT_next = 1'b1;
end else wait_next = wait_reg - 1'b1;
endcase
end
//Register 0
always @(posedge HCLK, negedge HRESETn) begin
if (!HRESETn) d_reg0 <= 32'h0000_0000;
else if (last_HSEL & last_HWRITE & last_HTRANS[1] & HREADYOUT)
if (last_HADDR[3:0] == REG0) d_reg0 <= HWDATA;
end
//Register 1
always @(posedge HCLK, negedge HRESETn) begin
if (!HRESETn) d_reg1 <= 32'h0000_0000;
else if (last_HSEL & last_HWRITE & last_HTRANS[1] & HREADYOUT)
if (last_HADDR[3:0] == REG1) d_reg1 <= HWDATA;
end
//Register 2
always @(posedge HCLK, negedge HRESETn) begin
if (!HRESETn) d_reg2 <= 32'h0000_0000;
else if (last_HSEL & last_HWRITE & last_HTRANS[1] & HREADYOUT)
if (last_HADDR[3:0] == REG2) d_reg2 <= HWDATA;
end
//Register 3
always @(posedge HCLK, negedge HRESETn) begin
if (!HRESETn) d_reg3 <= 32'h0000_0000;
else if (last_HSEL & last_HWRITE & last_HTRANS[1] & HREADYOUT)
if (last_HADDR[3:0] == REG3) d_reg3 <= HWDATA;
end
//Multiplexer for Output
always @* begin
if (last_HSEL)
case (last_HADDR[3:0])
REG0: HRDATA = d_reg0;
REG1: HRDATA = d_reg1;
REG2: HRDATA = d_reg2;
REG3: HRDATA = d_reg3;
default: HRDATA = 0;
endcase
else HRDATA = 0;
end
endmodule
| 6.980403 |
module AHBGPIO (
input wire HCLK,
input wire HRESETn,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [31:0] HWDATA,
input wire HWRITE,
input wire HSEL,
input wire HREADY,
input wire [15:0] GPIOIN,
//Output
output wire HREADYOUT,
output wire [31:0] HRDATA,
output wire [15:0] GPIOOUT
);
localparam [7:0] gpio_data_addr = 8'h00;
localparam [7:0] gpio_dir_addr = 8'h04;
reg [15:0] gpio_dataout;
reg [15:0] gpio_datain;
reg [15:0] gpio_dir;
reg [15:0] gpio_data_next;
reg [31:0] last_HADDR;
reg [1:0] last_HTRANS;
reg last_HWRITE;
reg last_HSEL;
integer i;
assign HREADYOUT = 1'b1;
// Set Registers from address phase
always @(posedge HCLK) begin
if (HREADY) begin
last_HADDR <= HADDR;
last_HTRANS <= HTRANS;
last_HWRITE <= HWRITE;
last_HSEL <= HSEL;
end
end
// Update in/out switch
always @(posedge HCLK, negedge HRESETn) begin
if (!HRESETn) begin
gpio_dir <= 16'h0000;
end else if ((last_HADDR[7:0] == gpio_dir_addr) & last_HSEL & last_HWRITE & last_HTRANS[1])
gpio_dir <= HWDATA[15:0];
end
// Update output value
always @(posedge HCLK, negedge HRESETn) begin
if (!HRESETn) begin
gpio_dataout <= 16'h0000;
end
else if ((gpio_dir == 16'h0001) & (last_HADDR[7:0] == gpio_data_addr) & last_HSEL & last_HWRITE & last_HTRANS[1])
gpio_dataout <= HWDATA[15:0];
end
// Update input value
always @(posedge HCLK, negedge HRESETn) begin
if (!HRESETn) begin
gpio_datain <= 16'h0000;
end else if (gpio_dir == 16'h0000) gpio_datain <= GPIOIN;
else if (gpio_dir == 16'h0001) gpio_datain <= GPIOOUT;
end
assign HRDATA[15:0] = gpio_datain;
assign GPIOOUT = gpio_dataout;
endmodule
| 6.767078 |
module ahbl0_ipgen_lscc_ahbl_prio_arb #(
parameter M = 32
) (
// -----------------------------------------------------------------------------
// Module Parameters
// -----------------------------------------------------------------------------
// ------------------------------------------------------------------------------
// Input/Output Ports
// ------------------------------------------------------------------------------
input [(M - 1):0] req_i,
output reg [(M - 1):0] gnt_o
);
// ------------------------------------------------------------------------------
// Combinatorial Block
// ------------------------------------------------------------------------------
always @(*) begin
gnt_o = (req_i & (-req_i));
end
endmodule
| 8.795294 |
module ahbl0_ipgen_lscc_ahbl_decoder_prim #(
parameter F = 8,
parameter M_ADDR_WIDTH = 32,
parameter FULL_DECODE_EN = 1,
parameter FRAGMENT_EN = 4'd1,
parameter [((F * 32) - 1):0] BASE_ADDR = {
32'h0, 32'h0, 32'h0, 32'h0, 32'h0, 32'h0, 32'h0, 32'h0
},
parameter [((F * 32) - 1):0] ADDR_RANGE = {
32'h400, 32'h400, 32'h400, 32'h400, 32'h400, 32'h400, 32'h400, 32'h400
}
) (
// -----------------------------------------------------------------------------
// Module Parameters
// -----------------------------------------------------------------------------
//parameter K = 32,
// ------------------------------------------------------------------------------
// Input/Output Ports
// ------------------------------------------------------------------------------
input enable_i,
input [(M_ADDR_WIDTH - 1):10] addr_i,
output wire sel_o
);
// ------------------------------------------------------------------------------
// Local Parameters
// ------------------------------------------------------------------------------
// ------------------------------------------------------------------------------
// Wire Declarations
// ------------------------------------------------------------------------------
wire [(FRAGMENT_EN - 1):0] sel_w;
// ------------------------------------------------------------------------------
// Assign Statements
// ------------------------------------------------------------------------------
assign sel_o = (|sel_w);
// ------------------------------------------------------------------------------
// Generate Blocks
// ------------------------------------------------------------------------------
genvar i;
// Slave 0
generate
for (i = 0; (i < FRAGMENT_EN); i = (i + 1)) begin : genblk1
ahbl0_ipgen_lscc_ahbl_decoder_comp #(
.FULL_DECODE_EN(FULL_DECODE_EN),
.BASE_ADDR(BASE_ADDR[((32*(i+1))-1):(32*i)]),
.ADDR_RANGE(ADDR_RANGE[((32*(i+1))-1):(32*i)]),
.ADDR_WIDTH(M_ADDR_WIDTH)
) u_lscc_ahbl_decoder_comp ( // .K (K),
.enable_i(enable_i),
.addr_i(addr_i),
.sel_o(sel_w[i])
);
end
endgenerate
endmodule
| 8.795294 |
module ahbl0_ipgen_lscc_ahbl_decoder_comp #(
parameter FULL_DECODE_EN = 1,
parameter BASE_ADDR = 32'h0,
parameter ADDR_RANGE = 32'h400,
parameter ADDR_WIDTH = 32
) (
// ------------------------------------------------------------------------------
// Module Parameters
// ------------------------------------------------------------------------------
//parameter K = 32,
// ------------------------------------------------------------------------------
// Input/Output Ports
// ------------------------------------------------------------------------------
input enable_i,
input [(ADDR_WIDTH - 1):10] addr_i,
output reg sel_o
);
// ------------------------------------------------------------------------------
// Local Parameters
// ------------------------------------------------------------------------------
localparam MAX_ADDR = ((BASE_ADDR + ADDR_RANGE) - 1);
localparam RANGE_WIDTH = ((ADDR_RANGE >= 32'h400) ? clog2((ADDR_RANGE - 1)) : 10);
// ------------------------------------------------------------------------------
// Wire Declarations
// ------------------------------------------------------------------------------
wire [(ADDR_WIDTH - 1):0] min_addr = BASE_ADDR;
wire match_up_bits;
//wire [ADDR_WIDTH-1:0] addr = {K{1'b0}} | {addr_i[ADDR_WIDTH-1:10],{10{1'b0}}};
// ------------------------------------------------------------------------------
// Combinatorial Blocks
// ------------------------------------------------------------------------------
generate
if (FULL_DECODE_EN) begin : full_dec
assign match_up_bits = ((addr_i[(ADDR_WIDTH - 1):10] >= BASE_ADDR[(ADDR_WIDTH - 1):10]) && (addr_i[(ADDR_WIDTH - 1):10] <= MAX_ADDR[(ADDR_WIDTH - 1):10])) ;
end else begin : partial_dec
if ((ADDR_WIDTH > RANGE_WIDTH)) begin : addr_gt_range
assign match_up_bits = (addr_i[(ADDR_WIDTH - 1):RANGE_WIDTH] == min_addr[(ADDR_WIDTH - 1):RANGE_WIDTH]) ;
end else begin : addr_eq_range
assign match_up_bits = 1'b1;
end
end
endgenerate
always @(*) begin
sel_o = (enable_i ? match_up_bits : 1'b0);
end
//------------------------------------------------------------------------------
// Function Definition
//------------------------------------------------------------------------------
function integer clog2(input integer depth);
begin
if ((depth == 0)) clog2 = 1;
else for (clog2 = 0; (depth > 0); clog2 = (clog2 + 1)) depth = (depth >> 1);
end
endfunction
//
endmodule
| 8.795294 |
module ahbl0_ipgen_lscc_ahbl_default_slv #(
parameter DATA_WIDTH = 32
) (
// -----------------------------------------------------------------------------
// Module Parameters
// -----------------------------------------------------------------------------
// ------------------------------------------------------------------------------
// Input/Output Ports
// ------------------------------------------------------------------------------
input ahbl_hclk_i,
input ahbl_hresetn_i,
input ahbl_hsel_i,
input [1:0] ahbl_htrans_i,
output reg ahbl_hready_def_o,
output reg ahbl_hresp_def_o,
output wire [(DATA_WIDTH - 1):0] ahbl_hrdata_def_o
);
// ------------------------------------------------------------------------------
// Local Parameters
// ------------------------------------------------------------------------------
localparam ST_WIDTH = 2;
localparam ST_RDY = 0;
localparam ST_ERR0 = 1;
localparam ST_ERR1 = 2;
localparam IDLE = 2'b00;
localparam BUSY = 2'b01;
localparam NSEQ = 2'b10;
localparam SEQ = 2'b11;
// ------------------------------------------------------------------------------
// Combinatorial Registers
// ------------------------------------------------------------------------------
reg [(ST_WIDTH - 1):0] ns_sm;
// ------------------------------------------------------------------------------
// Sequential Registers3
// ------------------------------------------------------------------------------
reg [(ST_WIDTH - 1):0] cs_sm;
// ------------------------------------------------------------------------------
// Assign Statements
// ------------------------------------------------------------------------------
assign ahbl_hrdata_def_o = {DATA_WIDTH{1'b1}};
// ------------------------------------------------------------------------------
// Combinatorial Block
// ------------------------------------------------------------------------------
always @(*) begin
ns_sm = cs_sm;
ahbl_hready_def_o = 1'b1;
ahbl_hresp_def_o = 1'b0;
case (cs_sm)
ST_RDY: begin
if (ahbl_hsel_i) begin
ns_sm = (((ahbl_htrans_i == NSEQ) || (ahbl_htrans_i == SEQ)) ? ST_ERR0 : ST_RDY);
end
end
ST_ERR0: begin
// if (ahbl_hsel_i) begin
ahbl_hready_def_o = 1'b0;
ahbl_hresp_def_o = 1'b1;
ns_sm = ST_ERR1;
// end
// else begin
// ns_sm = ST_RDY;
// end
end
ST_ERR1: begin
ahbl_hready_def_o = 1'b1;
ahbl_hresp_def_o = 1'b1;
ns_sm = (((ahbl_htrans_i == IDLE) || (ahbl_htrans_i == BUSY)) ? ST_RDY : ST_ERR0);
end
default: begin
ns_sm = ST_RDY;
end
endcase // case (cs_sm)
end
// ------------------------------------------------------------------------------
// Sequential Block
// ------------------------------------------------------------------------------
always @(posedge ahbl_hclk_i or negedge ahbl_hresetn_i) begin
if ((~ahbl_hresetn_i)) begin
cs_sm <= ST_RDY;
end else begin
cs_sm <= ns_sm;
end
end
endmodule
| 8.795294 |
module ahbl2apb_top (
input clk_i,
input rst_n_i,
input pclk_i,
input presetn_i,
input ahbl_mstr_dummy_in,
output ahbl_mstr_dummy_out,
input apb_slv_dummy_in,
output apb_slv_dummy_out
);
`include "dut_params.v"
wire pclk_w;
wire presetn_w;
wire ahbl_hsel_i;
wire ahbl_hready_i;
wire [ADDR_WIDTH-1:0] ahbl_haddr_i;
wire [ 2:0] ahbl_hburst_i;
wire [ 2:0] ahbl_hsize_i;
wire ahbl_hmastlock_i;
wire [ 3:0] ahbl_hprot_i;
wire [ 1:0] ahbl_htrans_i;
wire ahbl_hwrite_i;
wire [DATA_WIDTH-1:0] ahbl_hwdata_i;
wire ahbl_hreadyout_o;
wire ahbl_hresp_o;
wire [DATA_WIDTH-1:0] ahbl_hrdata_o;
wire apb_psel_o;
wire [ADDR_WIDTH-1:0] apb_paddr_o;
wire [DATA_WIDTH-1:0] apb_pwdata_o;
wire apb_pwrite_o;
wire apb_penable_o;
wire apb_pready_i;
wire apb_pslverr_i;
wire [DATA_WIDTH-1:0] apb_prdata_i;
generate
if (APB_CLK_EN) begin : dual_clk
assign pclk_w = pclk_i;
assign presetn_w = presetn_i;
end else begin : single_clk
assign pclk_w = clk_i;
assign presetn_w = rst_n_i;
end
endgenerate
`include "dut_inst.v"
lscc_ahbl_master_dummy #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH)
) ahbl_mst (
.ahbl_hclk_i (clk_i),
.ahbl_hresetn_i (rst_n_i),
.ahbl_hsel_o (ahbl_hsel_i),
.ahbl_hready_o (ahbl_hready_i),
.ahbl_haddr_o (ahbl_haddr_i),
.ahbl_hburst_o (ahbl_hburst_i),
.ahbl_hsize_o (ahbl_hsize_i),
.ahbl_hmastlock_o (ahbl_hmastlock_i),
.ahbl_hprot_o (ahbl_hprot_i),
.ahbl_htrans_o (ahbl_htrans_i),
.ahbl_hwdata_o (ahbl_hwdata_i),
.ahbl_hwrite_o (ahbl_hwrite_i),
.ahbl_hreadyout_i (ahbl_hreadyout_o),
.ahbl_hresp_i (ahbl_hresp_o),
.ahbl_hrdata_i (ahbl_hrdata_o),
.ahbl_mstr_dummy_in (ahbl_mstr_dummy_in),
.ahbl_mstr_dummy_out(ahbl_mstr_dummy_out)
);
lscc_apb_slave_dummy #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH)
) apb_slv (
.apb_pclk_i (pclk_w),
.apb_presetn_i (presetn_w),
.apb_psel_i (apb_psel_o),
.apb_paddr_i (apb_paddr_o),
.apb_pwdata_i (apb_pwdata_o),
.apb_pwrite_i (apb_pwrite_o),
.apb_penable_i (apb_penable_o),
.apb_pready_o (apb_pready_i),
.apb_pslverr_o (apb_pslverr_i),
.apb_prdata_o (apb_prdata_i),
.apb_slv_dummy_in (apb_slv_dummy_in),
.apb_slv_dummy_out(apb_slv_dummy_out)
);
endmodule
| 6.906275 |
module AHBLite2AvalonMemoryMapped #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32
) (
clk,
reset_n,
ahb_haddr,
ahb_hwrite,
ahb_hsize,
ahb_hburst,
ahb_hmastlock,
ahb_hprot,
ahb_htrans,
ahb_hwdata,
ahb_hrdata,
ahb_hready,
ahb_hresp,
avl_address,
avl_write,
avl_read,
avl_burstcount,
avl_beginbursttransfer,
avl_lock,
avl_writedata,
avl_readdata,
avl_readdatavalid,
avl_waitrequest_n,
avl_response
);
input clk;
input reset_n;
input [ADDR_WIDTH-1:0] ahb_haddr;
input ahb_hwrite;
input [2:0] ahb_hsize;
input [2:0] ahb_hburst;
input ahb_hmastlock;
input [3:0] ahb_hprot;
input [1:0] ahb_htrans;
input [DATA_WIDTH-1:0] ahb_hwdata;
output [DATA_WIDTH-1:0] ahb_hrdata;
output ahb_hready;
output ahb_hresp;
output [ADDR_WIDTH-1:0] avl_address;
output avl_write;
output avl_read;
output [11:0] avl_burstcount;
output avl_beginbursttransfer;
output avl_lock;
output [DATA_WIDTH-1:0] avl_writedata;
input [DATA_WIDTH-1:0] avl_readdata;
input avl_readdatavalid;
input avl_waitrequest_n;
input [1:0] avl_response;
reg [ADDR_WIDTH-1:0] r_haddr;
reg r_hwrite;
reg [2:0] r_hsize;
reg [2:0] r_hburst;
reg [1:0] r_htrans;
reg r_hready;
reg [DATA_WIDTH-1:0] r_readdata;
reg r_pendingread;
assign avl_address = r_haddr;
assign avl_write = ((r_htrans != `AHB_HTRANS_NONSEQ && r_htrans != `AHB_HTRANS_SEQ) || (avl_waitrequest_n && !r_hready))? 1'b0 : r_hwrite;
assign avl_read = ((r_htrans != `AHB_HTRANS_NONSEQ && r_htrans != `AHB_HTRANS_SEQ) || (avl_waitrequest_n && !r_hready))? 1'b0 : !r_hwrite;
// TODO
assign avl_burstcount = 1'b1;
// TODO
assign avl_beginbursttransfer = 1'b0;
// XXX: NO LOCK IN THIS VERSION
assign avl_lock = 1'b0;
assign avl_writedata = ahb_hwdata;
assign ahb_hrdata = avl_readdatavalid ? avl_readdata : r_readdata;
//assign ahb_hready = avl_waitrequest_n && (avl_waitrequest_n || r_pendingread);
assign ahb_hready = avl_waitrequest_n && (!r_pendingread || avl_readdatavalid);
assign ahb_hresp = (`AVL_RESPONSE_SLAVEERROR == avl_response || `AVL_RESPONSE_DECODEERROR == avl_response)? `AHB_HRESP_ERROR : `AHB_HRESP_OKAY;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
r_htrans <= `AHB_HTRANS_IDLE;
end else begin
r_haddr <= ahb_haddr;
r_hwrite <= ahb_hwrite;
r_hsize <= ahb_hsize;
r_hburst <= ahb_hburst;
r_htrans <= ahb_htrans;
end
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
r_pendingread <= 1'b0;
end else begin
if ((`AHB_HTRANS_NONSEQ == ahb_htrans || `AHB_HTRANS_SEQ == ahb_htrans) && !ahb_hwrite) begin
r_pendingread <= 1'b1;
end else if (avl_readdatavalid) begin
r_pendingread <= 1'b0;
end
end
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
r_readdata <= 'h0;
end else begin
if (avl_readdatavalid) begin
r_readdata <= avl_readdata;
end
end
end
always @(posedge clk or negedge reset_n) begin
r_hready <= ahb_hready;
end
endmodule
| 8.394763 |
module AHBLiteMaster (
HREADY,
HRESETn,
HCLK,
HRDATA,
WRITE,
ADDR,
WDATA,
HADDR,
HWRITE,
HWDATA,
RDATA
);
parameter ADDR_WIDTH = 32;
parameter DATA_WIDTH = 32;
input HRESETn;
input HCLK;
input [ADDR_WIDTH - 1:0] ADDR;
input WRITE;
input [DATA_WIDTH - 1:0] WDATA;
output [DATA_WIDTH - 1:0] RDATA;
reg [DATA_WIDTH - 1:0] RDATA = 32'hZZZZZZZZ;
input HREADY;
output [ADDR_WIDTH - 1:0] HADDR;
reg [ADDR_WIDTH - 1:0] HADDR = 32'hZZZZZZZZ;
output HWRITE;
reg HWRITE = 1'bZ;
output [DATA_WIDTH - 1:0] HWDATA;
reg [DATA_WIDTH - 1:0] HWDATA = 32'hZZZZZZZZ;
input [DATA_WIDTH - 1:0] HRDATA;
// Buffer regs
reg [DATA_WIDTH - 1:0] WDATA_AHB_master_buffer = 32'hZZZZZZZZ;
reg HWRITE_AHB_master_buffer;
// 1. The master drives the address and control signals onto the bus after the rising edge of HCLK.
// 2. The slave then samples the address and control information on the next rising edge of HCLK.
// 3. After the slave has sampled the address and control it can start to drive the appropriate HREADY response.
// This response is sampled by the master on the third rising edge of HCLK.
always @(posedge HCLK) begin
if (!HRESETn) begin
HADDR <= 32'h00000000;
HWDATA <= 32'h00000000;
HWRITE <= 1'b0;
WDATA_AHB_master_buffer <= 32'h00000000;
HWRITE_AHB_master_buffer <= 1'b0;
end else begin
// WDATA is released at the same time with the ADDR,
// but HWDATA gets WDATA at the next rising edge of HCLK,
// so we must buffer WDATA for a HCLK.
// And when HREADY is low, we still need to update WDATA_AHB_master_buffer
WDATA_AHB_master_buffer <= WDATA;
// HADDR is modified to update all the time, even when HREADY is low
HADDR <= ADDR;
// Only when HREADY is high, we need to update HADDR, HWRITE,
// and if HWRITE is high, HWDATA need to be updated,
// and if HWRITE is low, SLAVE need to prepare HRDATA
if (HREADY) begin
HWRITE <= WRITE;
// We need to buffer HWRITE for RDATA
HWRITE_AHB_master_buffer <= HWRITE;
// if HWRITE is high, AHB bus write buffered WDATA to HWDATA
// if HWRITE is low, SLAVE prepares HRDADA
if (HWRITE) begin
HWDATA <= WDATA_AHB_master_buffer;
end
// else if (!HWRITE)// SLAVE prepares HRDADA
// begin
// end
end
end
end
// Master send Slave response HRDADA to RDADA
always @(posedge HCLK) begin
if (!HRESETn) begin
RDATA <= 32'h00000000;
end else begin
if (HREADY) begin
// 1. At next rising edge after HRDATA is prepared, RDATA get HRDATA's value
// so we detect HWRITE_AHB_master_buffer which is buffered HWRITE
// 2. Actually, we don't need to buffer HWRITE if SLAVE always puts right HRDATA on bus.
// Here we buffer it in case of changing HRDATA when HWRITE is high.
// 3. When HREADY is pulled down, we do not care about HRDATA. But when it recovers,
// we need to update RDATA to the latest HRDATA
if (!HWRITE_AHB_master_buffer) begin
RDATA <= HRDATA;
end
end
end
end
endmodule
| 8.496748 |
module AHBlite_Block_RAM #(
parameter ADDR_WIDTH = 14
) (
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [2:0] HSIZE,
input wire [3:0] HPROT,
input wire HWRITE,
input wire [31:0] HWDATA,
input wire HREADY,
output wire HREADYOUT,
output wire [31:0] HRDATA,
output wire HRESP,
output wire [ADDR_WIDTH-1:0] BRAM_RDADDR,
output wire [ADDR_WIDTH-1:0] BRAM_WRADDR,
input wire [31:0] BRAM_RDATA,
output wire [31:0] BRAM_WDATA,
output wire [3:0] BRAM_WRITE
);
assign HRESP = 1'b0;
assign HRDATA = BRAM_RDATA;
wire trans_en;
assign trans_en = HSEL & HTRANS[1];
wire write_en;
assign write_en = trans_en & HWRITE;
wire read_en;
assign read_en = trans_en & (~HWRITE);
reg [3:0] size_dec;
always @(*) begin
case ({
HADDR[1:0], HSIZE[1:0]
})
4'h0 : size_dec = 4'h1;
4'h1 : size_dec = 4'h3;
4'h2 : size_dec = 4'hf;
4'h4 : size_dec = 4'h2;
4'h8 : size_dec = 4'h4;
4'h9 : size_dec = 4'hc;
4'hc : size_dec = 4'h8;
default : size_dec = 4'h0;
endcase
end
reg [3:0] size_reg;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) size_reg <= 0;
else if (write_en & HREADY) size_reg <= size_dec;
end
reg [ADDR_WIDTH-1:0] addr_reg;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) addr_reg <= 0;
else if (trans_en & HREADY) addr_reg <= HADDR[(ADDR_WIDTH+1):2];
end
reg wr_en_reg;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) wr_en_reg <= 1'b0;
else if (HREADY) wr_en_reg <= write_en;
else wr_en_reg <= 1'b0;
end
assign BRAM_RDADDR = HADDR[(ADDR_WIDTH+1):2];
assign BRAM_WRADDR = addr_reg;
assign HREADYOUT = 1'b1;
assign BRAM_WRITE = wr_en_reg ? size_reg : 4'h0;
assign BRAM_WDATA = HWDATA;
endmodule
| 7.162418 |
module AHBlite_Block_RAM_FM_Data #(
parameter FM_ADDR_WIDTH = 6
) (
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [ 31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire [ 2:0] HSIZE,
input wire [ 3:0] HPROT,
input wire HWRITE,
input wire [ 31:0] HWDATA,
input wire HREADY,
output wire HREADYOUT,
output wire [ 31:0] HRDATA,
output wire HRESP,
output wire [FM_ADDR_WIDTH-1:0] FM_RDADDR,
output wire [FM_ADDR_WIDTH-1:0] FM_WRADDR,
input wire [ 31:0] FM_RDATA,
output wire [ 31:0] FM_WDATA,
output wire [ 3:0] FM_WRITE
);
assign HRESP = 1'b0;
assign HRDATA = FM_RDATA;
wire trans_en;
assign trans_en = HSEL & HTRANS[1];
wire write_en;
assign write_en = trans_en & HWRITE;
wire read_en;
assign read_en = trans_en & (~HWRITE);
reg [3:0] size_dec;
always @(*) begin
case ({
HADDR[1:0], HSIZE[1:0]
})
4'h0: size_dec = 4'h1;
4'h1: size_dec = 4'h3;
4'h2: size_dec = 4'hf;
4'h4: size_dec = 4'h2;
4'h8: size_dec = 4'h4;
4'h9: size_dec = 4'hc;
4'hc: size_dec = 4'h8;
default: size_dec = 4'h0;
endcase
end
reg [3:0] size_reg;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) size_reg <= 0;
else if (write_en & HREADY) size_reg <= size_dec;
end
reg [FM_ADDR_WIDTH-1:0] addr_reg;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) addr_reg <= 0;
else if (trans_en & HREADY) addr_reg <= HADDR[(FM_ADDR_WIDTH+1):2];
end
reg wr_en_reg;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) wr_en_reg <= 1'b0;
else if (HREADY) wr_en_reg <= write_en;
else wr_en_reg <= 1'b0;
end
assign FM_RDADDR = HADDR[(FM_ADDR_WIDTH+1):2];
assign FM_WRADDR = addr_reg;
assign HREADYOUT = 1'b1;
assign FM_WRITE = wr_en_reg ? size_reg : 4'h0;
assign FM_WDATA = HWDATA;
endmodule
| 7.162418 |
module AHBlite_Block_ROM #(
parameter ADDR_WIDTH = 13
) (
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [ 31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire [ 2:0] HSIZE,
input wire [ 3:0] HPROT,
input wire HWRITE,
input wire [ 31:0] HWDATA,
input wire HREADY,
output wire HREADYOUT,
output wire [ 31:0] HRDATA,
output wire [ 1:0] HRESP,
output wire [ADDR_WIDTH-1:0] BRAM_ADDR,
input wire [ 31:0] BRAM_RDATA
);
assign HRESP = 2'b0;
assign HRDATA = BRAM_RDATA;
assign BRAM_ADDR = HADDR[(ADDR_WIDTH+1):2];
assign HREADYOUT = 1'b1;
endmodule
| 7.162418 |
module AHBlite_BUS0 (
input wire HCLK,
input wire HRESETn,
// Master Interface
input wire [31:0] HADDR,
input wire [31:0] HWDATA,
output wire [31:0] HRDATA,
output wire HREADY,
// Slave # 0
output wire HSEL_S0,
input wire HREADY_S0,
input wire [31:0] HRDATA_S0,
// Slave # 1
output wire HSEL_S1,
input wire HREADY_S1,
input wire [31:0] HRDATA_S1,
// Slave # 2
output wire HSEL_S2,
input wire HREADY_S2,
input wire [31:0] HRDATA_S2,
// Slave # 3
output wire HSEL_S3,
input wire HREADY_S3,
input wire [31:0] HRDATA_S3,
// Slave # 4
output wire HSEL_S4,
input wire HREADY_S4,
input wire [31:0] HRDATA_S4,
// SubSystem # 0
output wire HSEL_SS0,
input wire HREADY_SS0,
input wire [31:0] HRDATA_SS0
);
wire [7:0] PAGE = HADDR[31:24];
reg [7:0] APAGE;
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) APAGE <= 8'h0;
else if (HREADY) APAGE <= PAGE;
end
assign HSEL_S0 = (PAGE == 8'h00);
assign HSEL_S1 = (PAGE == 8'h20);
assign HSEL_S2 = (PAGE == 8'h48);
assign HSEL_S3 = (PAGE == 8'h49);
assign HSEL_S4 = (PAGE == 8'h4A);
assign HSEL_SS0 = (PAGE == 8'h40);
assign HREADY =
(APAGE == 8'h00) ? HREADY_S0 :
(APAGE == 8'h20) ? HREADY_S1 :
(APAGE == 8'h48) ? HREADY_S2 :
(APAGE == 8'h49) ? HREADY_S3 :
(APAGE == 8'h4A) ? HREADY_S4 :
(APAGE == 8'h40) ? HREADY_SS0 :
1'b1;
assign HRDATA =
(APAGE == 8'h00) ? HRDATA_S0 :
(APAGE == 8'h20) ? HRDATA_S1 :
(APAGE == 8'h48) ? HRDATA_S2 :
(APAGE == 8'h49) ? HRDATA_S3 :
(APAGE == 8'h4A) ? HRDATA_S4 :
(APAGE == 8'h40) ? HRDATA_SS0 :
32'hDEADBEEF;
endmodule
| 6.683942 |
module AHBlite_BusMatrix_Arbiter_ACCC (
input HCLK,
input HRESETn,
input REQ_SYS,
input REQ_DMA,
input HREADY_Outputstage_ACCC,
input HSEL_Outputstage_ACCC,
input [1:0] HTRANS_Outputstage_ACCC,
input [2:0] HBURST_Outputstage_ACCC,
output wire [1:0] PORT_SEL_ARBITER_ACCC,
output wire PORT_NOSEL_ARBITER_ACCC
);
reg noport;
wire noport_next;
assign noport_next = (~REQ_DMA) & (~REQ_SYS) & (~HSEL_Outputstage_ACCC);
reg [1:0] selport;
wire [1:0] selport_next;
assign selport_next = REQ_SYS ? 2'b01 : (REQ_DMA ? 2'b10 : 2'b00);
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) begin
noport <= 1'b1;
selport <= 2'b00;
end else if (HREADY_Outputstage_ACCC) begin
noport <= noport_next;
selport <= selport_next;
end
end
assign PORT_NOSEL_ARBITER_ACCC = noport;
assign PORT_SEL_ARBITER_ACCC = selport;
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Arbiter_CAMERA (
input HCLK,
input HRESETn,
input REQ_SYS,
input REQ_DMA,
input REQ_ACC,
input HREADY_Outputstage_CAMERA,
input HSEL_Outputstage_CAMERA,
input [1:0] HTRANS_Outputstage_CAMERA,
input [2:0] HBURST_Outputstage_CAMERA,
output wire [1:0] PORT_SEL_ARBITER_CAMERA,
output wire PORT_NOSEL_ARBITER_CAMERA
);
reg noport;
wire noport_next;
assign noport_next = (~REQ_SYS) & (~REQ_DMA) & (~REQ_ACC) & (~HSEL_Outputstage_CAMERA);
reg [1:0] selport;
wire [1:0] selport_next;
assign selport_next = REQ_SYS ? 2'b01 : (REQ_DMA ? 2'b10 : ((REQ_ACC ? 2'b11 : 2'b00)));
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) begin
noport <= 1'b1;
selport <= 2'b00;
end else if (HREADY_Outputstage_CAMERA) begin
noport <= noport_next;
selport <= selport_next;
end
end
assign PORT_NOSEL_ARBITER_CAMERA = noport;
assign PORT_SEL_ARBITER_CAMERA = selport;
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Arbiter_DMAC (
input HCLK,
input HRESETn,
input REQ_SUB,
input HREADY_Outputstage_DMAC,
input HSEL_Outputstage_DMAC,
input [1:0] HTRANS_Outputstage_DMAC,
input [2:0] HBURST_Outputstage_DMAC,
output wire [1:0] PORT_SEL_ARBITER_DMAC,
output wire PORT_NOSEL_ARBITER_DMAC
);
reg noport;
wire noport_next;
assign noport_next = (~REQ_SUB) & (~HSEL_Outputstage_DMAC);
reg [1:0] selport;
wire [1:0] selport_next;
assign selport_next = REQ_SUB ? 2'b11 : 2'b00;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) begin
noport <= 1'b1;
selport <= 2'b00;
end else if (HREADY_Outputstage_DMAC) begin
noport <= noport_next;
selport <= selport_next;
end
end
assign PORT_NOSEL_ARBITER_DMAC = noport;
assign PORT_SEL_ARBITER_DMAC = selport;
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Arbiter_DTCM (
input HCLK,
input HRESETn,
input REQ_SYS,
input REQ_DMA,
input REQ_ACC,
input HREADY_Outputstage_DTCM,
input HSEL_Outputstage_DTCM,
input [1:0] HTRANS_Outputstage_DTCM,
input [2:0] HBURST_Outputstage_DTCM,
output wire [1:0] PORT_SEL_ARBITER_DTCM,
output wire PORT_NOSEL_ARBITER_DTCM
);
reg noport;
wire noport_next;
assign noport_next = (~REQ_SYS) & (~REQ_DMA) & (~REQ_ACC) & (~HSEL_Outputstage_DTCM);
reg [1:0] selport;
wire [1:0] selport_next;
assign selport_next = REQ_SYS ? 2'b01 : (REQ_DMA ? 2'b10 : (REQ_ACC ? 2'b11 : 2'b00));
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) begin
noport <= 1'b1;
selport <= 2'b00;
end else if (HREADY_Outputstage_DTCM) begin
noport <= noport_next;
selport <= selport_next;
end
end
assign PORT_NOSEL_ARBITER_DTCM = noport;
assign PORT_SEL_ARBITER_DTCM = selport;
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Arbiter_GPIO (
input HCLK,
input HRESETn,
input REQ_SUB,
input HREADY_Outputstage_GPIO,
input HSEL_Outputstage_GPIO,
input [1:0] HTRANS_Outputstage_GPIO,
input [2:0] HBURST_Outputstage_GPIO,
output wire [1:0] PORT_SEL_ARBITER_GPIO,
output wire PORT_NOSEL_ARBITER_GPIO
);
reg noport;
wire noport_next;
assign noport_next = (~REQ_SUB) & (~HSEL_Outputstage_GPIO);
reg [1:0] selport;
wire [1:0] selport_next;
assign selport_next = REQ_SUB ? 2'b11 : 2'b00;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) begin
noport <= 1'b1;
selport <= 2'b00;
end else if (HREADY_Outputstage_GPIO) begin
noport <= noport_next;
selport <= selport_next;
end
end
assign PORT_NOSEL_ARBITER_GPIO = noport;
assign PORT_SEL_ARBITER_GPIO = selport;
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Arbiter_ITCM (
input HCLK,
input HRESETn,
input REQ_ICODE,
input REQ_DCODE,
input HREADY_Outputstage_ITCM,
input HSEL_Outputstage_ITCM,
input [1:0] HTRANS_Outputstage_ITCM,
input [2:0] HBURST_Outputstage_ITCM,
output wire [1:0] PORT_SEL_ARBITER_ITCM,
output wire PORT_NOSEL_ARBITER_ITCM
);
reg noport;
wire noport_next;
assign noport_next = (~REQ_ICODE) & (~REQ_DCODE) & (~HSEL_Outputstage_ITCM);
reg [1:0] selport;
wire [1:0] selport_next;
assign selport_next = REQ_DCODE ? 2'b01 : (REQ_ICODE ? 2'b10 : 2'b00);
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) begin
noport <= 1'b1;
selport <= 2'b00;
end else if (HREADY_Outputstage_ITCM) begin
noport <= noport_next;
selport <= selport_next;
end
end
assign PORT_NOSEL_ARBITER_ITCM = noport;
assign PORT_SEL_ARBITER_ITCM = selport;
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Arbiter_OLED (
input HCLK,
input HRESETn,
input REQ_SUB,
input HREADY_Outputstage_OLED,
input HSEL_Outputstage_OLED,
input [1:0] HTRANS_Outputstage_OLED,
input [2:0] HBURST_Outputstage_OLED,
output wire [1:0] PORT_SEL_ARBITER_OLED,
output wire PORT_NOSEL_ARBITER_OLED
);
reg noport;
wire noport_next;
assign noport_next = (~REQ_SUB) & (~HSEL_Outputstage_OLED);
reg [1:0] selport;
wire [1:0] selport_next;
assign selport_next = REQ_SUB ? 2'b11 : 2'b00;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) begin
noport <= 1'b1;
selport <= 2'b00;
end else if (HREADY_Outputstage_OLED) begin
noport <= noport_next;
selport <= selport_next;
end
end
assign PORT_NOSEL_ARBITER_OLED = noport;
assign PORT_SEL_ARBITER_OLED = selport;
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Arbiter_ROM (
input HCLK,
input HRESETn,
input REQ_ICODE,
input REQ_DCODE,
input HREADY_Outputstage_ROM,
input HSEL_Outputstage_ROM,
input [1:0] HTRANS_Outputstage_ROM,
input [2:0] HBURST_Outputstage_ROM,
output wire [1:0] PORT_SEL_ARBITER_ROM,
output wire PORT_NOSEL_ARBITER_ROM
);
reg noport;
wire noport_next;
assign noport_next = (~REQ_ICODE) & (~REQ_DCODE) & (~HSEL_Outputstage_ROM);
reg [1:0] selport;
wire [1:0] selport_next;
assign selport_next = REQ_DCODE ? 2'b01 : (REQ_ICODE ? 2'b10 : 2'b00);
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) begin
noport <= 1'b1;
selport <= 2'b00;
end else if (HREADY_Outputstage_ROM) begin
noport <= noport_next;
selport <= selport_next;
end
end
assign PORT_NOSEL_ARBITER_ROM = noport;
assign PORT_SEL_ARBITER_ROM = selport;
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Arbiter_SUB (
input HCLK,
input HRESETn,
input REQ_SYS,
input HREADY_Outputstage_SUB,
input HSEL_Outputstage_SUB,
input [1:0] HTRANS_Outputstage_SUB,
input [2:0] HBURST_Outputstage_SUB,
output wire [1:0] PORT_SEL_ARBITER_SUB,
output wire PORT_NOSEL_ARBITER_SUB
);
reg noport;
wire noport_next;
assign noport_next = (~REQ_SYS) & (~HSEL_Outputstage_SUB);
reg [1:0] selport;
wire [1:0] selport_next;
assign selport_next = REQ_SYS ? 2'b11 : 2'b00;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) begin
noport <= 1'b1;
selport <= 2'b00;
end else if (HREADY_Outputstage_SUB) begin
noport <= noport_next;
selport <= selport_next;
end
end
assign PORT_NOSEL_ARBITER_SUB = noport;
assign PORT_SEL_ARBITER_SUB = selport;
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Arbiter_TIMER (
input HCLK,
input HRESETn,
input REQ_SUB,
input HREADY_Outputstage_TIMER,
input HSEL_Outputstage_TIMER,
input [1:0] HTRANS_Outputstage_TIMER,
input [2:0] HBURST_Outputstage_TIMER,
output wire [1:0] PORT_SEL_ARBITER_TIMER,
output wire PORT_NOSEL_ARBITER_TIMER
);
reg noport;
wire noport_next;
assign noport_next = (~REQ_SUB) & (~HSEL_Outputstage_TIMER);
reg [1:0] selport;
wire [1:0] selport_next;
assign selport_next = REQ_SUB ? 2'b11 : 2'b00;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) begin
noport <= 1'b1;
selport <= 2'b00;
end else if (HREADY_Outputstage_TIMER) begin
noport <= noport_next;
selport <= selport_next;
end
end
assign PORT_NOSEL_ARBITER_TIMER = noport;
assign PORT_SEL_ARBITER_TIMER = selport;
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Arbiter_UART (
input HCLK,
input HRESETn,
input REQ_SUB,
input HREADY_Outputstage_UART,
input HSEL_Outputstage_UART,
input [1:0] HTRANS_Outputstage_UART,
input [2:0] HBURST_Outputstage_UART,
output wire [1:0] PORT_SEL_ARBITER_UART,
output wire PORT_NOSEL_ARBITER_UART
);
reg noport;
wire noport_next;
assign noport_next = (~REQ_SUB) & (~HSEL_Outputstage_UART);
reg [1:0] selport;
wire [1:0] selport_next;
assign selport_next = REQ_SUB ? 2'b11 : 2'b00;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) begin
noport <= 1'b1;
selport <= 2'b00;
end else if (HREADY_Outputstage_UART) begin
noport <= noport_next;
selport <= selport_next;
end
end
assign PORT_NOSEL_ARBITER_UART = noport;
assign PORT_SEL_ARBITER_UART = selport;
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Decoder_ACC (
input HCLK,
input HRESETn,
// FROM INPUTSTAGE
input HREADY,
input [31:0] HADDR,
input [1:0] HTRANS,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_DTCM,
input HREADYOUT_Outputstage_DTCM,
input [1:0] HRESP_DTCM,
input [31:0] HRDATA_DTCM,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_CAMERA,
input HREADYOUT_Outputstage_CAMERA,
input [1:0] HRESP_CAMERA,
input [31:0] HRDATA_CAMERA,
// OUTPUTSTAGE HSEL
output wire HSEL_Decoder_ACC_DTCM,
output wire HSEL_Decoder_ACC_CAMERA,
// SELOUTPUT
output wire ACTIVE_Decoder_ACC,
output wire HREADYOUT,
output wire [1:0] HRESP,
output wire [31:0] HRDATA
);
assign HSEL_Decoder_ACC_DTCM = (HADDR[31:12] == 20'h20000);
assign HSEL_Decoder_ACC_CAMERA = (HADDR[31:16] == 16'h4001);
assign ACTIVE_Decoder_ACC = HSEL_Decoder_ACC_DTCM ? ACTIVE_Outputstage_DTCM :
(HSEL_Decoder_ACC_CAMERA ? ACTIVE_Outputstage_CAMERA : 1'b1);
reg [1:0] sel_reg;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) sel_reg <= 2'b0;
else if (HREADY) sel_reg <= {HSEL_Decoder_ACC_DTCM, HSEL_Decoder_ACC_CAMERA};
end
assign HREADYOUT = (sel_reg == 2'b01) ? HREADYOUT_Outputstage_CAMERA :
((sel_reg == 2'b10) ? HREADYOUT_Outputstage_DTCM : 1'b1);
assign HRESP = (sel_reg == 2'b01) ? HRESP_CAMERA : ((sel_reg == 2'b10) ? HRESP_DTCM : 2'b00);
assign HRDATA = (sel_reg == 2'b01) ? HRDATA_CAMERA : ((sel_reg == 2'b10) ? HRDATA_DTCM : 32'b0);
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Decoder_DCODE (
input HCLK,
input HRESETn,
// FROM INPUTSTAGE
input HREADY,
input [31:0] HADDR,
input [1:0] HTRANS,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_ITCM,
input HREADYOUT_Outputstage_ITCM,
input [1:0] HRESP_ITCM,
input [31:0] HRDATA_ITCM,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_ROM,
input HREADYOUT_Outputstage_ROM,
input [1:0] HRESP_ROM,
input [31:0] HRDATA_ROM,
// OUTPUTSTAGE HSEL
output wire HSEL_Decoder_DCODE_ITCM,
output wire HSEL_Decoder_DCODE_ROM,
// SELOUTPUT
output wire ACTIVE_Decoder_DCODE,
output wire HREADYOUT,
output wire [1:0] HRESP,
output wire [31:0] HRDATA
);
assign HSEL_Decoder_DCODE_ITCM = (HADDR[31:15] == 17'h1);
assign HSEL_Decoder_DCODE_ROM = (HADDR[31:15] == 17'b0);
assign ACTIVE_Decoder_DCODE = HSEL_Decoder_DCODE_ITCM ? ACTIVE_Outputstage_ITCM :
(HSEL_Decoder_DCODE_ROM ? ACTIVE_Outputstage_ROM : 1'b1);
reg [1:0] sel_reg;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) sel_reg <= 2'b0;
else if (HREADY) sel_reg <= {HSEL_Decoder_DCODE_ITCM, HSEL_Decoder_DCODE_ROM};
end
assign HREADYOUT = (sel_reg == 2'b10) ? HREADYOUT_Outputstage_ITCM :
((sel_reg == 2'b01) ? HREADYOUT_Outputstage_ROM : 1'b1);
assign HRESP = (sel_reg == 2'b10) ? HRESP_ITCM : ((sel_reg == 2'b01) ? HRESP_ROM : 2'b0);
assign HRDATA = (sel_reg == 2'b10) ? HRDATA_ITCM : ((sel_reg == 2'b01) ? HRDATA_ROM : 32'b0);
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Decoder_DMA (
input HCLK,
input HRESETn,
// FROM INPUTSTAGE
input HREADY,
input [31:0] HADDR,
input [1:0] HTRANS,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_DTCM,
input HREADYOUT_Outputstage_DTCM,
input [1:0] HRESP_DTCM,
input [31:0] HRDATA_DTCM,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_CAMERA,
input HREADYOUT_Outputstage_CAMERA,
input [1:0] HRESP_CAMERA,
input [31:0] HRDATA_CAMERA,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_ACCC,
input HREADYOUT_Outputstage_ACCC,
input [1:0] HRESP_ACCC,
input [31:0] HRDATA_ACCC,
// OUTPUTSTAGE HSEL
output wire HSEL_Decoder_DMA_DTCM,
output wire HSEL_Decoder_DMA_CAMERA,
output wire HSEL_Decoder_DMA_ACCC,
// SELOUTPUT
output wire ACTIVE_Decoder_DMA,
output wire HREADYOUT,
output wire [1:0] HRESP,
output wire [31:0] HRDATA
);
assign HSEL_Decoder_DMA_DTCM = (HADDR[31:12] == 20'h20000);
assign HSEL_Decoder_DMA_CAMERA = (HADDR[31:16] == 16'h4001);
assign HSEL_Decoder_DMA_ACCC = (HADDR[31:16] == 16'h4003);
assign ACTIVE_Decoder_DMA = HSEL_Decoder_DMA_DTCM ? ACTIVE_Outputstage_DTCM :
(HSEL_Decoder_DMA_CAMERA ? ACTIVE_Outputstage_CAMERA :
(HSEL_Decoder_DMA_ACCC ? ACTIVE_Outputstage_ACCC :1'b1));
reg [2:0] sel_reg;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) sel_reg <= 3'b0;
else if (HREADY)
sel_reg <= {HSEL_Decoder_DMA_DTCM, HSEL_Decoder_DMA_CAMERA, HSEL_Decoder_DMA_ACCC};
end
assign HREADYOUT = (sel_reg == 3'b001) ? HREADYOUT_Outputstage_ACCC :
((sel_reg == 3'b010) ? HREADYOUT_Outputstage_CAMERA :
((sel_reg == 3'b100) ? HREADYOUT_Outputstage_DTCM : 1'b1));
assign HRESP = (sel_reg == 3'b001) ? HRESP_ACCC :
((sel_reg == 3'b010) ? HRESP_CAMERA :
((sel_reg == 3'b100) ? HRESP_DTCM : 2'b00));
assign HRDATA = (sel_reg == 3'b0001) ? HRDATA_ACCC :
((sel_reg == 3'b010) ? HRDATA_CAMERA :
((sel_reg == 3'b100) ? HRDATA_DTCM : 32'b0));
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Decoder_ICODE (
input HCLK,
input HRESETn,
// FROM INPUTSTAGE
input HREADY,
input [31:0] HADDR,
input [1:0] HTRANS,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_ITCM,
input HREADYOUT_Outputstage_ITCM,
input [1:0] HRESP_ITCM,
input [31:0] HRDATA_ITCM,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_ROM,
input HREADYOUT_Outputstage_ROM,
input [1:0] HRESP_ROM,
input [31:0] HRDATA_ROM,
// OUTPUTSTAGE HSEL
output wire HSEL_Decoder_ICODE_ITCM,
output wire HSEL_Decoder_ICODE_ROM,
// SELOUTPUT
output wire ACTIVE_Decoder_ICODE,
output wire HREADYOUT,
output wire [1:0] HRESP,
output wire [31:0] HRDATA
);
assign HSEL_Decoder_ICODE_ITCM = (HADDR[31:15] == 17'h1);
assign HSEL_Decoder_ICODE_ROM = (HADDR[31:15] == 17'b0);
assign ACTIVE_Decoder_ICODE = HSEL_Decoder_ICODE_ITCM ? ACTIVE_Outputstage_ITCM :
(HSEL_Decoder_ICODE_ROM ? ACTIVE_Outputstage_ROM : 1'b1);
reg [1:0] sel_reg;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) sel_reg <= 2'b0;
else if (HREADY) sel_reg <= {HSEL_Decoder_ICODE_ITCM, HSEL_Decoder_ICODE_ROM};
end
assign HREADYOUT = (sel_reg == 2'b10) ? HREADYOUT_Outputstage_ITCM :
((sel_reg == 2'b01) ? HREADYOUT_Outputstage_ROM : 1'b1);
assign HRESP = (sel_reg == 2'b10) ? HRESP_ITCM : ((sel_reg == 2'b01) ? HRESP_ROM : 2'b0);
assign HRDATA = (sel_reg == 2'b10) ? HRDATA_ITCM : ((sel_reg == 2'b01) ? HRDATA_ROM : 32'b0);
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Decoder_SUB (
input HCLK,
input HRESETn,
// FROM INPUTSTAGE
input HREADY,
input [31:0] HADDR,
input [1:0] HTRANS,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_DMAC,
input HREADYOUT_Outputstage_DMAC,
input [1:0] HRESP_DMAC,
input [31:0] HRDATA_DMAC,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_GPIO,
input HREADYOUT_Outputstage_GPIO,
input [1:0] HRESP_GPIO,
input [31:0] HRDATA_GPIO,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_OLED,
input HREADYOUT_Outputstage_OLED,
input [1:0] HRESP_OLED,
input [31:0] HRDATA_OLED,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_TIMER,
input HREADYOUT_Outputstage_TIMER,
input [1:0] HRESP_TIMER,
input [31:0] HRDATA_TIMER,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_UART,
input HREADYOUT_Outputstage_UART,
input [1:0] HRESP_UART,
input [31:0] HRDATA_UART,
// OUTPUTSTAGE HSEL
output wire HSEL_Decoder_SUB_DMAC,
output wire HSEL_Decoder_SUB_GPIO,
output wire HSEL_Decoder_SUB_OLED,
output wire HSEL_Decoder_SUB_TIMER,
output wire HSEL_Decoder_SUB_UART,
// SELOUTPUT
output wire ACTIVE_Decoder_SUB,
output wire HREADYOUT,
output wire [1:0] HRESP,
output wire [31:0] HRDATA
);
assign HSEL_Decoder_SUB_DMAC = (HADDR[31:8] == 28'h400002);
assign HSEL_Decoder_SUB_UART = (HADDR[31:8] == 28'h400001);
assign HSEL_Decoder_SUB_GPIO = (HADDR[31:8] == 28'h400000);
assign HSEL_Decoder_SUB_OLED = (HADDR[31:8] == 24'h400003);
assign HSEL_Decoder_SUB_TIMER = (HADDR[31:8] == 24'h400004);
assign ACTIVE_Decoder_SUB = HSEL_Decoder_SUB_DMAC ? ACTIVE_Outputstage_DMAC :
(HSEL_Decoder_SUB_GPIO ? ACTIVE_Outputstage_GPIO :
(HSEL_Decoder_SUB_OLED ? ACTIVE_Outputstage_OLED :
(HSEL_Decoder_SUB_UART ? ACTIVE_Outputstage_UART :
(HSEL_Decoder_SUB_TIMER ? ACTIVE_Outputstage_TIMER: 1'b1))));
reg [4:0] sel_reg;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) sel_reg <= 5'b0;
else if (HREADY)
sel_reg <= {
HSEL_Decoder_SUB_TIMER,
HSEL_Decoder_SUB_UART,
HSEL_Decoder_SUB_DMAC,
HSEL_Decoder_SUB_GPIO,
HSEL_Decoder_SUB_OLED
};
end
assign HREADYOUT = (sel_reg == 5'b00001) ? HREADYOUT_Outputstage_OLED :
((sel_reg == 5'b00010) ? HREADYOUT_Outputstage_GPIO :
((sel_reg == 5'b00100) ? HREADYOUT_Outputstage_DMAC :
((sel_reg == 5'b01000) ? HREADYOUT_Outputstage_UART :
((sel_reg == 5'b10000) ? HREADYOUT_Outputstage_TIMER : 1'b1))));
assign HRESP = (sel_reg == 5'b00001) ? HRESP_OLED :
((sel_reg == 5'b00010) ? HRESP_GPIO :
((sel_reg == 5'b00100) ? HRESP_DMAC :
((sel_reg == 5'b01000) ? HRESP_UART :
((sel_reg == 5'b10000) ? HRESP_TIMER : 2'b00))));
assign HRDATA = (sel_reg == 5'b00001) ? HRDATA_OLED :
((sel_reg == 5'b00010) ? HRDATA_GPIO :
((sel_reg == 5'b00100) ? HRDATA_DMAC :
((sel_reg == 5'b01000) ? HRDATA_UART :
((sel_reg == 5'b10000) ? HRDATA_TIMER : 32'b0))));
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Decoder_SYS (
input HCLK,
input HRESETn,
// FROM INPUTSTAGE
input HREADY,
input [31:0] HADDR,
input [1:0] HTRANS,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_DTCM,
input HREADYOUT_Outputstage_DTCM,
input [1:0] HRESP_DTCM,
input [31:0] HRDATA_DTCM,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_SUB,
input HREADYOUT_Outputstage_SUB,
input [1:0] HRESP_SUB,
input [31:0] HRDATA_SUB,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_CAMERA,
input HREADYOUT_Outputstage_CAMERA,
input [1:0] HRESP_CAMERA,
input [31:0] HRDATA_CAMERA,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_ACCC,
input HREADYOUT_Outputstage_ACCC,
input [1:0] HRESP_ACCC,
input [31:0] HRDATA_ACCC,
// OUTPUTSTAGE HSEL
output wire HSEL_Decoder_SYS_DTCM,
output wire HSEL_Decoder_SYS_CAMERA,
output wire HSEL_Decoder_SYS_ACCC,
output wire HSEL_Decoder_SYS_SUB,
// SELOUTPUT
output wire ACTIVE_Decoder_SYS,
output wire HREADYOUT,
output wire [1:0] HRESP,
output wire [31:0] HRDATA
);
assign HSEL_Decoder_SYS_DTCM = (HADDR[31:12] == 20'h20000);
assign HSEL_Decoder_SYS_CAMERA = (HADDR[31:16] == 16'h4001);
assign HSEL_Decoder_SYS_SUB = (HADDR[31:16] == 16'h4000);
assign HSEL_Decoder_SYS_ACCC = (HADDR[31:16] == 16'h4003);
assign ACTIVE_Decoder_SYS = HSEL_Decoder_SYS_DTCM ? ACTIVE_Outputstage_DTCM :
(HSEL_Decoder_SYS_CAMERA ? ACTIVE_Outputstage_CAMERA :
(HSEL_Decoder_SYS_ACCC ? ACTIVE_Outputstage_ACCC :
(HSEL_Decoder_SYS_SUB ? ACTIVE_Outputstage_SUB : 1'b1)));
reg [3:0] sel_reg;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) sel_reg <= 4'b0;
else if (HREADY)
sel_reg <= {
HSEL_Decoder_SYS_SUB, HSEL_Decoder_SYS_DTCM, HSEL_Decoder_SYS_CAMERA, HSEL_Decoder_SYS_ACCC
};
end
assign HREADYOUT = (sel_reg == 4'b0001) ? HREADYOUT_Outputstage_ACCC :
((sel_reg == 4'b0010) ? HREADYOUT_Outputstage_CAMERA :
((sel_reg == 4'b0100) ? HREADYOUT_Outputstage_DTCM :
((sel_reg == 4'b1000) ? HREADYOUT_Outputstage_SUB : 1'b1)));
assign HRESP = (sel_reg == 4'b0001) ? HRESP_ACCC :
((sel_reg == 4'b0010) ? HRESP_CAMERA :
((sel_reg == 4'b0100) ? HRESP_DTCM :
((sel_reg == 4'b1000) ? HRESP_SUB : 2'b00)));
assign HRDATA = (sel_reg == 4'b0001) ? HRDATA_ACCC :
((sel_reg == 4'b0010) ? HRDATA_CAMERA :
((sel_reg == 4'b0100) ? HRDATA_DTCM :
((sel_reg == 4'b1000) ? HRDATA_SUB : 32'b0)));
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Inputstage (
input HCLK,
input HRESETn,
input [31:0] HADDR,
input [ 1:0] HTRANS,
input HWRITE,
input [ 2:0] HSIZE,
input [ 2:0] HBURST,
input [ 3:0] HPROT,
input HREADY,
input ACTIVE_Decoder,
input HREADYOUT_Decoder,
input [ 1:0] HRESP_Decoder,
output wire HREADYOUT,
output wire [ 1:0] HRESP,
output wire [31:0] HADDR_Inputstage,
output wire [ 1:0] HTRANS_Inputstage,
output wire HWRITE_Inputstage,
output wire [ 2:0] HSIZE_Inputstage,
output wire [ 2:0] HBURST_Inputstage,
output wire [ 3:0] HPROT_Inputstage,
output wire TRANS_HOLD
);
// TRANS START CONTRL
wire trans_req;
wire trans_valid;
assign trans_req = HTRANS[1];
assign trans_valid = trans_req & HREADY;
// SIGNAL REG
reg [ 1:0] trans_reg;
reg [31:0] addr_reg;
reg write_reg;
reg [ 2:0] size_reg;
reg [ 2:0] burst_reg;
reg [ 3:0] prot_reg;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) begin
trans_reg <= 2'b0;
addr_reg <= 32'b0;
write_reg <= 1'b0;
size_reg <= 3'b0;
burst_reg <= 3'b0;
prot_reg <= 4'b0;
end else if (trans_valid) begin
trans_reg <= HTRANS;
addr_reg <= HADDR;
write_reg <= HWRITE;
size_reg <= HSIZE;
burst_reg <= HBURST;
prot_reg <= HPROT;
end
end
// TRANS STATE
reg trans_state;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) trans_state <= 1'b0;
else if (HREADY) trans_state <= trans_req;
end
// TRANS PENDING
reg trans_pend;
wire trans_wait;
wire trans_done;
assign trans_wait = trans_valid & (~ACTIVE_Decoder);
assign trans_done = ACTIVE_Decoder & HREADYOUT_Decoder;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) trans_pend <= 1'b0;
else if (trans_wait) trans_pend <= 1'b1;
else if (trans_done) trans_pend <= 1'b0;
end
assign TRANS_HOLD = trans_valid | trans_pend;
assign HTRANS_Inputstage = trans_pend ? trans_reg : HTRANS;
assign HADDR_Inputstage = trans_pend ? addr_reg : HADDR;
assign HWRITE_Inputstage = trans_pend ? write_reg : HWRITE;
assign HSIZE_Inputstage = trans_pend ? size_reg : HSIZE;
assign HBURST_Inputstage = trans_pend ? burst_reg : HBURST;
assign HPROT_Inputstage = trans_pend ? prot_reg : HPROT;
assign HREADYOUT = (~trans_state) ? 1'b1 : ((trans_pend) ? 1'b0 : HREADYOUT_Decoder);
assign HRESP = (~trans_state) ? 2'b00 : ((trans_pend) ? 2'b00 : HRESP_Decoder);
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Outputstage_ACCC (
input HCLK,
input HRESETn,
input HSEL_SYS,
input [31:0] HADDR_SYS,
input [ 1:0] HTRANS_SYS,
input HWRITE_SYS,
input [ 2:0] HSIZE_SYS,
input [ 2:0] HBURST_SYS,
input [ 3:0] HPROT_SYS,
input [31:0] HWDATA_SYS,
input TRANS_HOLD_SYS,
input HSEL_DMA,
input [31:0] HADDR_DMA,
input [ 1:0] HTRANS_DMA,
input HWRITE_DMA,
input [ 2:0] HSIZE_DMA,
input [ 2:0] HBURST_DMA,
input [ 3:0] HPROT_DMA,
input [31:0] HWDATA_DMA,
input TRANS_HOLD_DMA,
input HREADYOUT,
output wire ACTIVE_SYS,
output wire ACTIVE_DMA,
output wire HSEL,
output wire [31:0] HADDR,
output wire [1:0] HTRANS,
output wire HWRITE,
output wire [2:0] HSIZE,
output wire [2:0] HBURST,
output wire [3:0] HPROT,
output wire HREADY,
output wire [31:0] HWDATA
);
wire REQ_SYS;
wire REQ_DMA;
assign REQ_SYS = TRANS_HOLD_SYS & HSEL_SYS;
assign REQ_DMA = TRANS_HOLD_DMA & HSEL_DMA;
wire noport;
wire [1:0] selport;
AHBlite_BusMatrix_Arbiter_ACCC accc_arb (
.HCLK (HCLK),
.HRESETn (HRESETn),
.REQ_SYS (REQ_SYS),
.REQ_DMA (REQ_DMA),
.HREADY_Outputstage_ACCC(HREADY),
.HSEL_Outputstage_ACCC (HSEL),
.HTRANS_Outputstage_ACCC(HTRANS),
.HBURST_Outputstage_ACCC(HBURST),
.PORT_SEL_ARBITER_ACCC (selport),
.PORT_NOSEL_ARBITER_ACCC(noport)
);
assign ACTIVE_SYS = (~noport) & (selport == 2'b01);
assign ACTIVE_DMA = (~noport) & (selport == 2'b10);
assign HSEL = noport ? 1'b0 :
((selport == 2'b01) ? HSEL_SYS :
((selport == 2'b10) ? HSEL_DMA : 1'b0));
assign HADDR = noport ? 32'b0 :
((selport == 2'b01) ? HADDR_SYS :
((selport == 2'b10) ? HADDR_DMA : 32'b0));
assign HTRANS = noport ? 2'b0 :
((selport == 2'b01) ? HTRANS_SYS :
((selport == 2'b10) ? HTRANS_DMA : 2'b0));
assign HWRITE = noport ? 1'b0 :
((selport == 2'b01) ? HWRITE_SYS :
((selport == 2'b10) ? HWRITE_DMA : 1'b0));
assign HSIZE = noport ? 3'b0 :
((selport == 2'b01) ? HSIZE_SYS :
((selport == 2'b10) ? HSIZE_DMA : 3'b0));
assign HBURST = noport ? 3'b0 :
((selport == 2'b01) ? HBURST_SYS :
((selport == 2'b10) ? HBURST_DMA : 3'b0));
assign HPROT = noport ? 4'b0 :
((selport == 2'b01) ? HPROT_SYS :
((selport == 2'b10) ? HPROT_DMA : 4'b0));
reg trans_state;
assign HREADY = trans_state ? HREADYOUT : 1'b1;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) trans_state <= 1'b0;
else if (HREADY) trans_state <= HSEL;
end
reg [1:0] selport_data;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) selport_data <= 2'b0;
else if (HREADY) selport_data <= selport;
end
assign HWDATA = (selport_data == 2'b01) ? HWDATA_SYS : (
(selport_data == 2'b10) ? HWDATA_DMA : 32'b0);
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Outputstage_DMAC (
input HCLK,
input HRESETn,
input HSEL_SUB,
input [31:0] HADDR_SUB,
input [ 1:0] HTRANS_SUB,
input HWRITE_SUB,
input [ 2:0] HSIZE_SUB,
input [ 2:0] HBURST_SUB,
input [ 3:0] HPROT_SUB,
input [31:0] HWDATA_SUB,
input TRANS_HOLD_SUB,
input HREADYOUT,
output wire ACTIVE_SUB,
output wire HSEL,
output wire [31:0] HADDR,
output wire [1:0] HTRANS,
output wire HWRITE,
output wire [2:0] HSIZE,
output wire [2:0] HBURST,
output wire [3:0] HPROT,
output wire HREADY,
output wire [31:0] HWDATA
);
wire REQ_SUB;
assign REQ_SUB = TRANS_HOLD_SUB & HSEL_SUB;
wire noport;
wire [1:0] selport;
AHBlite_BusMatrix_Arbiter_DMAC dmac_arb (
.HCLK (HCLK),
.HRESETn (HRESETn),
.REQ_SUB (REQ_SUB),
.HREADY_Outputstage_DMAC(HREADY),
.HSEL_Outputstage_DMAC (HSEL),
.HTRANS_Outputstage_DMAC(HTRANS),
.HBURST_Outputstage_DMAC(HBURST),
.PORT_SEL_ARBITER_DMAC (selport),
.PORT_NOSEL_ARBITER_DMAC(noport)
);
assign ACTIVE_SUB = (~noport) & (selport == 2'b11);
assign HSEL = noport ? 1'b0 : ((selport == 2'b11) ? HSEL_SUB : 1'b0);
assign HADDR = noport ? 32'b0 : ((selport == 2'b11) ? HADDR_SUB : 32'b0);
assign HTRANS = noport ? 2'b0 : ((selport == 2'b11) ? HTRANS_SUB : 2'b0);
assign HWRITE = noport ? 1'b0 : ((selport == 2'b11) ? HWRITE_SUB : 1'b0);
assign HSIZE = noport ? 3'b0 : ((selport == 2'b11) ? HSIZE_SUB : 3'b0);
assign HBURST = noport ? 3'b0 : ((selport == 2'b11) ? HBURST_SUB : 3'b0);
assign HPROT = noport ? 4'b0 : ((selport == 2'b11) ? HPROT_SUB : 4'b0);
reg trans_state;
assign HREADY = trans_state ? HREADYOUT : 1'b1;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) trans_state <= 1'b0;
else if (HREADY) trans_state <= HSEL;
end
reg [1:0] selport_data;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) selport_data <= 2'b0;
else if (HREADY) selport_data <= selport;
end
assign HWDATA = (selport_data == 2'b11) ? HWDATA_SUB : 32'b0;
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Outputstage_GPIO (
input HCLK,
input HRESETn,
input HSEL_SUB,
input [31:0] HADDR_SUB,
input [ 1:0] HTRANS_SUB,
input HWRITE_SUB,
input [ 2:0] HSIZE_SUB,
input [ 2:0] HBURST_SUB,
input [ 3:0] HPROT_SUB,
input [31:0] HWDATA_SUB,
input TRANS_HOLD_SUB,
input HREADYOUT,
output wire ACTIVE_SUB,
output wire HSEL,
output wire [31:0] HADDR,
output wire [1:0] HTRANS,
output wire HWRITE,
output wire [2:0] HSIZE,
output wire [2:0] HBURST,
output wire [3:0] HPROT,
output wire HREADY,
output wire [31:0] HWDATA
);
wire REQ_SUB;
assign REQ_SUB = TRANS_HOLD_SUB & HSEL_SUB;
wire noport;
wire [1:0] selport;
AHBlite_BusMatrix_Arbiter_GPIO gpio_arb (
.HCLK (HCLK),
.HRESETn (HRESETn),
.REQ_SUB (REQ_SUB),
.HREADY_Outputstage_GPIO(HREADY),
.HSEL_Outputstage_GPIO (HSEL),
.HTRANS_Outputstage_GPIO(HTRANS),
.HBURST_Outputstage_GPIO(HBURST),
.PORT_SEL_ARBITER_GPIO (selport),
.PORT_NOSEL_ARBITER_GPIO(noport)
);
assign ACTIVE_SUB = (~noport) & (selport == 2'b11);
assign HSEL = noport ? 1'b0 : ((selport == 2'b11) ? HSEL_SUB : 1'b0);
assign HADDR = noport ? 32'b0 : ((selport == 2'b11) ? HADDR_SUB : 32'b0);
assign HTRANS = noport ? 2'b0 : ((selport == 2'b11) ? HTRANS_SUB : 2'b0);
assign HWRITE = noport ? 1'b0 : ((selport == 2'b11) ? HWRITE_SUB : 1'b0);
assign HSIZE = noport ? 3'b0 : ((selport == 2'b11) ? HSIZE_SUB : 3'b0);
assign HBURST = noport ? 3'b0 : ((selport == 2'b11) ? HBURST_SUB : 3'b0);
assign HPROT = noport ? 4'b0 : ((selport == 2'b11) ? HPROT_SUB : 4'b0);
reg trans_state;
assign HREADY = trans_state ? HREADYOUT : 1'b1;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) trans_state <= 1'b0;
else if (HREADY) trans_state <= HSEL;
end
reg [1:0] selport_data;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) selport_data <= 2'b0;
else if (HREADY) selport_data <= selport;
end
assign HWDATA = (selport_data == 2'b11) ? HWDATA_SUB : 32'b0;
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Outputstage_ITCM (
input HCLK,
input HRESETn,
input HSEL_ICODE,
input [31:0] HADDR_ICODE,
input [ 1:0] HTRANS_ICODE,
input HWRITE_ICODE,
input [ 2:0] HSIZE_ICODE,
input [ 2:0] HBURST_ICODE,
input [ 3:0] HPROT_ICODE,
input [31:0] HWDATA_ICODE,
input TRANS_HOLD_ICODE,
input HSEL_DCODE,
input [31:0] HADDR_DCODE,
input [ 1:0] HTRANS_DCODE,
input HWRITE_DCODE,
input [ 2:0] HSIZE_DCODE,
input [ 2:0] HBURST_DCODE,
input [ 3:0] HPROT_DCODE,
input [31:0] HWDATA_DCODE,
input TRANS_HOLD_DCODE,
input HREADYOUT,
output wire ACTIVE_DCODE,
output wire ACTIVE_ICODE,
output wire HSEL,
output wire [31:0] HADDR,
output wire [1:0] HTRANS,
output wire HWRITE,
output wire [2:0] HSIZE,
output wire [2:0] HBURST,
output wire [3:0] HPROT,
output wire HREADY,
output wire [31:0] HWDATA
);
wire REQ_DCODE;
wire REQ_ICODE;
assign REQ_DCODE = TRANS_HOLD_DCODE & HSEL_DCODE;
assign REQ_ICODE = TRANS_HOLD_ICODE & HSEL_ICODE;
wire noport;
wire [1:0] selport;
AHBlite_BusMatrix_Arbiter_ITCM ITCM_arb (
.HCLK (HCLK),
.HRESETn (HRESETn),
.REQ_DCODE (REQ_DCODE),
.REQ_ICODE (REQ_ICODE),
.HREADY_Outputstage_ITCM(HREADY),
.HSEL_Outputstage_ITCM (HSEL),
.HTRANS_Outputstage_ITCM(HTRANS),
.HBURST_Outputstage_ITCM(HBURST),
.PORT_SEL_ARBITER_ITCM (selport),
.PORT_NOSEL_ARBITER_ITCM(noport)
);
assign ACTIVE_DCODE = (~noport) & (selport == 2'b01);
assign ACTIVE_ICODE = (~noport) & (selport == 2'b10);
assign HSEL = noport ? 1'b0 :
((selport == 2'b01) ? HSEL_DCODE :
((selport == 2'b10) ? HSEL_ICODE : 1'b0));
assign HADDR = noport ? 32'b0 :
((selport == 2'b01) ? HADDR_DCODE :
((selport == 2'b10) ? HADDR_ICODE : 32'b0));
assign HTRANS = noport ? 2'b0 :
((selport == 2'b01) ? HTRANS_DCODE :
((selport == 2'b10) ? HTRANS_ICODE : 2'b0));
assign HWRITE = noport ? 1'b0 :
((selport == 2'b01) ? HWRITE_DCODE :
((selport == 2'b10) ? HWRITE_ICODE : 1'b0));
assign HSIZE = noport ? 3'b0 :
((selport == 2'b01) ? HSIZE_DCODE :
((selport == 2'b10) ? HSIZE_ICODE : 3'b0));
assign HBURST = noport ? 3'b0 :
((selport == 2'b01) ? HBURST_DCODE :
((selport == 2'b10) ? HBURST_ICODE : 3'b0));
assign HPROT = noport ? 4'b0 :
((selport == 2'b01) ? HPROT_DCODE :
((selport == 2'b10) ? HPROT_ICODE : 4'b0));
reg trans_state;
assign HREADY = trans_state ? HREADYOUT : 1'b1;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) trans_state <= 1'b0;
else if (HREADY) trans_state <= HSEL;
end
reg [1:0] selport_data;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) selport_data <= 2'b0;
else if (HREADY) selport_data <= selport;
end
assign HWDATA = (selport_data == 2'b01) ? HWDATA_DCODE :
((selport_data == 2'b10) ? HWDATA_ICODE : 32'b0);
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Outputstage_OLED (
input HCLK,
input HRESETn,
input HSEL_SUB,
input [31:0] HADDR_SUB,
input [ 1:0] HTRANS_SUB,
input HWRITE_SUB,
input [ 2:0] HSIZE_SUB,
input [ 2:0] HBURST_SUB,
input [ 3:0] HPROT_SUB,
input [31:0] HWDATA_SUB,
input TRANS_HOLD_SUB,
input HREADYOUT,
output wire ACTIVE_SUB,
output wire HSEL,
output wire [31:0] HADDR,
output wire [1:0] HTRANS,
output wire HWRITE,
output wire [2:0] HSIZE,
output wire [2:0] HBURST,
output wire [3:0] HPROT,
output wire HREADY,
output wire [31:0] HWDATA
);
wire REQ_SUB;
assign REQ_SUB = TRANS_HOLD_SUB & HSEL_SUB;
wire noport;
wire [1:0] selport;
AHBlite_BusMatrix_Arbiter_OLED oled_arb (
.HCLK (HCLK),
.HRESETn (HRESETn),
.REQ_SUB (REQ_SUB),
.HREADY_Outputstage_OLED(HREADY),
.HSEL_Outputstage_OLED (HSEL),
.HTRANS_Outputstage_OLED(HTRANS),
.HBURST_Outputstage_OLED(HBURST),
.PORT_SEL_ARBITER_OLED (selport),
.PORT_NOSEL_ARBITER_OLED(noport)
);
assign ACTIVE_SUB = (~noport) & (selport == 2'b11);
assign HSEL = noport ? 1'b0 : ((selport == 2'b11) ? HSEL_SUB : 1'b0);
assign HADDR = noport ? 32'b0 : ((selport == 2'b11) ? HADDR_SUB : 32'b0);
assign HTRANS = noport ? 2'b0 : ((selport == 2'b11) ? HTRANS_SUB : 2'b0);
assign HWRITE = noport ? 1'b0 : ((selport == 2'b11) ? HWRITE_SUB : 1'b0);
assign HSIZE = noport ? 3'b0 : ((selport == 2'b11) ? HSIZE_SUB : 3'b0);
assign HBURST = noport ? 3'b0 : ((selport == 2'b11) ? HBURST_SUB : 3'b0);
assign HPROT = noport ? 4'b0 : ((selport == 2'b11) ? HPROT_SUB : 4'b0);
reg trans_state;
assign HREADY = trans_state ? HREADYOUT : 1'b1;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) trans_state <= 1'b0;
else if (HREADY) trans_state <= HSEL;
end
reg [1:0] selport_data;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) selport_data <= 2'b0;
else if (HREADY) selport_data <= selport;
end
assign HWDATA = (selport_data == 2'b11) ? HWDATA_SUB : 32'b0;
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Outputstage_ROM (
input HCLK,
input HRESETn,
input HSEL_ICODE,
input [31:0] HADDR_ICODE,
input [ 1:0] HTRANS_ICODE,
input HWRITE_ICODE,
input [ 2:0] HSIZE_ICODE,
input [ 2:0] HBURST_ICODE,
input [ 3:0] HPROT_ICODE,
input [31:0] HWDATA_ICODE,
input TRANS_HOLD_ICODE,
input HSEL_DCODE,
input [31:0] HADDR_DCODE,
input [ 1:0] HTRANS_DCODE,
input HWRITE_DCODE,
input [ 2:0] HSIZE_DCODE,
input [ 2:0] HBURST_DCODE,
input [ 3:0] HPROT_DCODE,
input [31:0] HWDATA_DCODE,
input TRANS_HOLD_DCODE,
input HREADYOUT,
output wire ACTIVE_DCODE,
output wire ACTIVE_ICODE,
output wire HSEL,
output wire [31:0] HADDR,
output wire [1:0] HTRANS,
output wire HWRITE,
output wire [2:0] HSIZE,
output wire [2:0] HBURST,
output wire [3:0] HPROT,
output wire HREADY,
output wire [31:0] HWDATA
);
wire REQ_DCODE;
wire REQ_ICODE;
assign REQ_DCODE = TRANS_HOLD_DCODE & HSEL_DCODE;
assign REQ_ICODE = TRANS_HOLD_ICODE & HSEL_ICODE;
wire noport;
wire [1:0] selport;
AHBlite_BusMatrix_Arbiter_ROM ROM_arb (
.HCLK (HCLK),
.HRESETn (HRESETn),
.REQ_DCODE (REQ_DCODE),
.REQ_ICODE (REQ_ICODE),
.HREADY_Outputstage_ROM(HREADY),
.HSEL_Outputstage_ROM (HSEL),
.HTRANS_Outputstage_ROM(HTRANS),
.HBURST_Outputstage_ROM(HBURST),
.PORT_SEL_ARBITER_ROM (selport),
.PORT_NOSEL_ARBITER_ROM(noport)
);
assign ACTIVE_DCODE = (~noport) & (selport == 2'b01);
assign ACTIVE_ICODE = (~noport) & (selport == 2'b10);
assign HSEL = noport ? 1'b0 :
((selport == 2'b01) ? HSEL_DCODE :
((selport == 2'b10) ? HSEL_ICODE : 1'b0));
assign HADDR = noport ? 32'b0 :
((selport == 2'b01) ? HADDR_DCODE :
((selport == 2'b10) ? HADDR_ICODE : 32'b0));
assign HTRANS = noport ? 2'b0 :
((selport == 2'b01) ? HTRANS_DCODE :
((selport == 2'b10) ? HTRANS_ICODE : 2'b0));
assign HWRITE = noport ? 1'b0 :
((selport == 2'b01) ? HWRITE_DCODE :
((selport == 2'b10) ? HWRITE_ICODE : 1'b0));
assign HSIZE = noport ? 3'b0 :
((selport == 2'b01) ? HSIZE_DCODE :
((selport == 2'b10) ? HSIZE_ICODE : 3'b0));
assign HBURST = noport ? 3'b0 :
((selport == 2'b01) ? HBURST_DCODE :
((selport == 2'b10) ? HBURST_ICODE : 3'b0));
assign HPROT = noport ? 4'b0 :
((selport == 2'b01) ? HPROT_DCODE :
((selport == 2'b10) ? HPROT_ICODE : 4'b0));
reg trans_state;
assign HREADY = trans_state ? HREADYOUT : 1'b1;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) trans_state <= 1'b0;
else if (HREADY) trans_state <= HSEL;
end
reg [1:0] selport_data;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) selport_data <= 2'b0;
else if (HREADY) selport_data <= selport;
end
assign HWDATA = (selport_data == 2'b01) ? HWDATA_DCODE :
((selport_data == 2'b10) ? HWDATA_ICODE : 32'b0);
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Outputstage_SUB (
input HCLK,
input HRESETn,
input HSEL_SYS,
input [31:0] HADDR_SYS,
input [ 1:0] HTRANS_SYS,
input HWRITE_SYS,
input [ 2:0] HSIZE_SYS,
input [ 2:0] HBURST_SYS,
input [ 3:0] HPROT_SYS,
input [31:0] HWDATA_SYS,
input TRANS_HOLD_SYS,
input HREADYOUT,
output wire ACTIVE_SYS,
output wire HSEL,
output wire [31:0] HADDR,
output wire [1:0] HTRANS,
output wire HWRITE,
output wire [2:0] HSIZE,
output wire [2:0] HBURST,
output wire [3:0] HPROT,
output wire HREADY,
output wire [31:0] HWDATA
);
wire REQ_SYS;
assign REQ_SYS = TRANS_HOLD_SYS & HSEL_SYS;
wire noport;
wire [1:0] selport;
AHBlite_BusMatrix_Arbiter_SUB sub_arb (
.HCLK (HCLK),
.HRESETn (HRESETn),
.REQ_SYS (REQ_SYS),
.HREADY_Outputstage_SUB(HREADY),
.HSEL_Outputstage_SUB (HSEL),
.HTRANS_Outputstage_SUB(HTRANS),
.HBURST_Outputstage_SUB(HBURST),
.PORT_SEL_ARBITER_SUB (selport),
.PORT_NOSEL_ARBITER_SUB(noport)
);
assign ACTIVE_SYS = (~noport) & (selport == 2'b11);
assign HSEL = noport ? 1'b0 : ((selport == 2'b11) ? HSEL_SYS : 1'b0);
assign HADDR = noport ? 32'b0 : ((selport == 2'b11) ? HADDR_SYS : 32'b0);
assign HTRANS = noport ? 2'b0 : ((selport == 2'b11) ? HTRANS_SYS : 2'b0);
assign HWRITE = noport ? 1'b0 : ((selport == 2'b11) ? HWRITE_SYS : 1'b0);
assign HSIZE = noport ? 3'b0 : ((selport == 2'b11) ? HSIZE_SYS : 3'b0);
assign HBURST = noport ? 3'b0 : ((selport == 2'b11) ? HBURST_SYS : 3'b0);
assign HPROT = noport ? 4'b0 : ((selport == 2'b11) ? HPROT_SYS : 4'b0);
reg trans_state;
assign HREADY = trans_state ? HREADYOUT : 1'b1;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) trans_state <= 1'b0;
else if (HREADY) trans_state <= HSEL;
end
reg [1:0] selport_data;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) selport_data <= 2'b0;
else if (HREADY) selport_data <= selport;
end
assign HWDATA = (selport_data == 2'b11) ? HWDATA_SYS : 32'b0;
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Outputstage_TIMER (
input HCLK,
input HRESETn,
input HSEL_SUB,
input [31:0] HADDR_SUB,
input [ 1:0] HTRANS_SUB,
input HWRITE_SUB,
input [ 2:0] HSIZE_SUB,
input [ 2:0] HBURST_SUB,
input [ 3:0] HPROT_SUB,
input [31:0] HWDATA_SUB,
input TRANS_HOLD_SUB,
input HREADYOUT,
output wire ACTIVE_SUB,
output wire HSEL,
output wire [31:0] HADDR,
output wire [1:0] HTRANS,
output wire HWRITE,
output wire [2:0] HSIZE,
output wire [2:0] HBURST,
output wire [3:0] HPROT,
output wire HREADY,
output wire [31:0] HWDATA
);
wire REQ_SUB;
assign REQ_SUB = TRANS_HOLD_SUB & HSEL_SUB;
wire noport;
wire [1:0] selport;
AHBlite_BusMatrix_Arbiter_TIMER oled_arb (
.HCLK (HCLK),
.HRESETn (HRESETn),
.REQ_SUB (REQ_SUB),
.HREADY_Outputstage_TIMER(HREADY),
.HSEL_Outputstage_TIMER (HSEL),
.HTRANS_Outputstage_TIMER(HTRANS),
.HBURST_Outputstage_TIMER(HBURST),
.PORT_SEL_ARBITER_TIMER (selport),
.PORT_NOSEL_ARBITER_TIMER(noport)
);
assign ACTIVE_SUB = (~noport) & (selport == 2'b11);
assign HSEL = noport ? 1'b0 : ((selport == 2'b11) ? HSEL_SUB : 1'b0);
assign HADDR = noport ? 32'b0 : ((selport == 2'b11) ? HADDR_SUB : 32'b0);
assign HTRANS = noport ? 2'b0 : ((selport == 2'b11) ? HTRANS_SUB : 2'b0);
assign HWRITE = noport ? 1'b0 : ((selport == 2'b11) ? HWRITE_SUB : 1'b0);
assign HSIZE = noport ? 3'b0 : ((selport == 2'b11) ? HSIZE_SUB : 3'b0);
assign HBURST = noport ? 3'b0 : ((selport == 2'b11) ? HBURST_SUB : 3'b0);
assign HPROT = noport ? 4'b0 : ((selport == 2'b11) ? HPROT_SUB : 4'b0);
reg trans_state;
assign HREADY = trans_state ? HREADYOUT : 1'b1;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) trans_state <= 1'b0;
else if (HREADY) trans_state <= HSEL;
end
reg [1:0] selport_data;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) selport_data <= 2'b0;
else if (HREADY) selport_data <= selport;
end
assign HWDATA = (selport_data == 2'b11) ? HWDATA_SUB : 32'b0;
endmodule
| 7.446207 |
module AHBlite_BusMatrix_Outputstage_UART (
input HCLK,
input HRESETn,
input HSEL_SUB,
input [31:0] HADDR_SUB,
input [ 1:0] HTRANS_SUB,
input HWRITE_SUB,
input [ 2:0] HSIZE_SUB,
input [ 2:0] HBURST_SUB,
input [ 3:0] HPROT_SUB,
input [31:0] HWDATA_SUB,
input TRANS_HOLD_SUB,
input HREADYOUT,
output wire ACTIVE_SUB,
output wire HSEL,
output wire [31:0] HADDR,
output wire [1:0] HTRANS,
output wire HWRITE,
output wire [2:0] HSIZE,
output wire [2:0] HBURST,
output wire [3:0] HPROT,
output wire HREADY,
output wire [31:0] HWDATA
);
wire REQ_SUB;
assign REQ_SUB = TRANS_HOLD_SUB & HSEL_SUB;
wire noport;
wire [1:0] selport;
AHBlite_BusMatrix_Arbiter_UART uart_arb (
.HCLK (HCLK),
.HRESETn (HRESETn),
.REQ_SUB (REQ_SUB),
.HREADY_Outputstage_UART(HREADY),
.HSEL_Outputstage_UART (HSEL),
.HTRANS_Outputstage_UART(HTRANS),
.HBURST_Outputstage_UART(HBURST),
.PORT_SEL_ARBITER_UART (selport),
.PORT_NOSEL_ARBITER_UART(noport)
);
assign ACTIVE_SUB = (~noport) & (selport == 2'b11);
assign HSEL = noport ? 1'b0 : ((selport == 2'b11) ? HSEL_SUB : 1'b0);
assign HADDR = noport ? 32'b0 : ((selport == 2'b11) ? HADDR_SUB : 32'b0);
assign HTRANS = noport ? 2'b0 : ((selport == 2'b11) ? HTRANS_SUB : 2'b0);
assign HWRITE = noport ? 1'b0 : ((selport == 2'b11) ? HWRITE_SUB : 1'b0);
assign HSIZE = noport ? 3'b0 : ((selport == 2'b11) ? HSIZE_SUB : 3'b0);
assign HBURST = noport ? 3'b0 : ((selport == 2'b11) ? HBURST_SUB : 3'b0);
assign HPROT = noport ? 4'b0 : ((selport == 2'b11) ? HPROT_SUB : 4'b0);
reg trans_state;
assign HREADY = trans_state ? HREADYOUT : 1'b1;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) trans_state <= 1'b0;
else if (HREADY) trans_state <= HSEL;
end
reg [1:0] selport_data;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) selport_data <= 2'b0;
else if (HREADY) selport_data <= selport;
end
assign HWDATA = (selport_data == 2'b11) ? HWDATA_SUB : 32'b0;
endmodule
| 7.446207 |
module AHBlite_db_reg (
// AHB Interface
// clock and reset
input wire HCLK,
//input wire HCLKG, // Gated clock
input wire HRESETn, // Reset
// input ports
input wire HSEL, // Select
input wire [23:2] HADDR, // Address
input wire HREADY, //
input wire HWRITE, // Write control
input wire [ 1:0] HTRANS, // AHB transfer type
input wire [ 2:0] HSIZE, // AHB hsize
input wire [31:0] HWDATA, // Write data
// output ports
output wire [31:0] HRDATA, // Read data
output wire HREADYOUT, // Device ready
output wire [ 1:0] HRESP,
// IP Interface
// db_reg register/fields
output [ 3:0] db_reg
);
reg IOSEL;
reg [23:0] IOADDR;
reg IOWRITE; // I/O transfer direction
reg [ 2:0] IOSIZE; // I/O transfer size
reg IOTRANS;
// registered HSEL, update only if selected to reduce toggling
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) IOSEL <= 1'b0;
else IOSEL <= HSEL & HREADY;
end
// registered address, update only if selected to reduce toggling
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) IOADDR <= 24'd0;
else IOADDR <= HADDR[23:0];
end
// Data phase write control
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) IOWRITE <= 1'b0;
else IOWRITE <= HWRITE;
end
// registered hsize, update only if selected to reduce toggling
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) IOSIZE <= {3{1'b0}};
else IOSIZE <= HSIZE[2:0];
end
// registered HTRANS, update only if selected to reduce toggling
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) IOTRANS <= 1'b0;
else IOTRANS <= HTRANS[1];
end
wire rd_enable;
assign rd_enable = IOSEL & (~IOWRITE) & IOTRANS;
wire wr_enable = IOTRANS & IOWRITE & IOSEL;
reg [3:0] db_reg;
// Register: db_reg
wire db_reg_select = wr_enable & (IOADDR[23:2] == 20'h0);
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) db_reg <= 4'h0;
else if (db_reg_select) db_reg <= HWDATA;
end
assign HRDATA =
(IOADDR[23:2] == 22'h0) ? {28'd0,db_reg} :
32'hDEADBEEF;
assign HREADYOUT = 1'b1; // Always ready
endmodule
| 7.903209 |
module AHBlite_Decoder #(
parameter Port0_en = 1,
parameter Port1_en = 1,
parameter Port2_en = 1,
parameter Port3_en = 1,
parameter Port4_en = 1
) (
input [31:0] HADDR,
output wire P0_HSEL,
output wire P1_HSEL,
output wire P2_HSEL,
output wire P3_HSEL,
output wire P4_HSEL
);
//RAMCODE-----------------------------------
//0x00000000-0x0000ffff
/*Insert RAMCODE decoder code there*/
assign P0_HSEL = (HADDR[31:16] == 16'h0000) ? Port0_en : 1'b0;
/***********************************/
//RAMDATA-----------------------------
//0X20000000-0X2000FFFF
/*Insert RAMDATA decoder code there*/
assign P1_HSEL = (HADDR[31:16] == 16'h2000) ? Port1_en : 1'b0;
/***********************************/
//PERIPHRAL-----------------------------
//0X40010000-0X4001FFFF
/*Insert RAMDATA decoder code there*/
assign P2_HSEL = (HADDR[31:16] == 16'h4001) ? Port2_en : 1'b0;
/***********************************/
//0X40000010 UART RX DATA
//0X40000014 UART TX STATE
//0X40000018 UART TX DATA
/*Insert UART decoder code there*/
assign P3_HSEL = (HADDR[31:4] == 28'h4000001) ? Port3_en : 1'b0;
/***********************************/
assign P4_HSEL = (HADDR[31:4] == 28'h4000002) ? Port4_en : 1'b0;
endmodule
| 7.379811 |
module AHBlite_Keyboard (
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire [ 2:0] HSIZE,
input wire [ 3:0] HPROT,
input wire HWRITE,
input wire [31:0] HWDATA,
input wire HREADY,
output wire HREADYOUT,
output wire [31:0] HRDATA,
output wire HRESP,
input wire [15:0] key_data,
output wire key_clear
);
assign HRESP = 1'b0;
assign HREADYOUT = 1'b1;
wire write_en;
assign write_en = HSEL & HTRANS[1] & HWRITE & HREADY;
reg wr_en_reg;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) wr_en_reg <= 1'b0;
else if (write_en) wr_en_reg <= 1'b1;
else wr_en_reg <= 1'b0;
end
assign key_clear = wr_en_reg ? HWDATA[0] : 1'b0;
assign HRDATA = {16'h0, key_data};
endmodule
| 6.90908 |
module AHBlite_SPI (
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [2:0] HSIZE,
input wire [3:0] HPROT,
input wire HWRITE,
input wire [31:0] HWDATA,
input wire HREADY,
output wire HREADYOUT,
output [31:0] HRDATA,
output wire HRESP,
output wire scs,
output wire sck,
output wire mosi,
input wire miso
);
assign HRESP = 1'b0;
//AHB to wishbone
reg sel_reg;
wire [1:0] addr_reg_n;
reg [1:0] addr_reg;
wire write_en;
reg wr_en_reg;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) sel_reg <= 1'b0;
else sel_reg <= HSEL & HTRANS[1];
end
assign addr_reg_n = ~(HSEL & HTRANS[1]) ? 2'b00 : HADDR[3:2];
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) addr_reg <= 2'd0;
else addr_reg <= addr_reg_n;
end
assign write_en = HSEL & HTRANS[1] & (HWRITE) & HREADY;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) wr_en_reg <= 1'b0;
else if (write_en) wr_en_reg <= 1'b1;
else wr_en_reg <= 1'b0;
end
spi u_spi (
.clk_i (HCLK),
.rst_i (HRESETn),
.cyc_i (sel_reg),
.stb_i (sel_reg),
.adr_i (addr_reg),
.we_i (wr_en_reg),
.dat_i (HWDATA),
.dat_o (HRDATA),
.ack_o (HREADYOUT),
.inta_o(),
.scs_o (scs),
.sck_o (sck),
.mosi_o(mosi),
.miso_i(miso)
);
endmodule
| 6.606167 |
module ahblite_sys_tb ();
reg RESET, CLK;
wire [7:0] LED;
AHBLITE_SYS dut (
.CLK (CLK),
.RESET(RESET),
.LED (LED)
);
// Note: you can modify this to give a 50MHz clock or whatever is appropriate
initial begin
CLK = 0;
forever begin
#5 CLK = 1;
#5 CLK = 0;
end
end
initial begin
RESET = 0;
#30 RESET = 1;
#20 RESET = 0;
end
endmodule
| 6.556387 |
module AHBlite_WaveformGenerator (
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire [ 2:0] HSIZE,
input wire [ 3:0] HPROT,
input wire HWRITE,
input wire [31:0] HWDATA,
input wire HREADY,
output wire HREADYOUT,
output wire [31:0] HRDATA,
output wire HRESP,
output reg wgen
);
assign HRESP = 1'b0;
assign HREADYOUT = 1'b1;
wire write_en;
assign write_en = HSEL & HTRANS[1] & HWRITE & HREADY;
reg wr_en_reg;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) wr_en_reg <= 1'b0;
else if (write_en) wr_en_reg <= 1'b1;
else wr_en_reg <= 1'b0;
end
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) wgen <= 1'b0;
else if (wr_en_reg && HREADY) wgen <= HWDATA[0];
end
assign HRDATA = {31'b0, wgen};
endmodule
| 6.604643 |
module AHBL_BUS_8 #(parameter BAD_DATA=32'DEADBEEF,
SLAVE_ENABLE=8'hff,
S0_PAGE=8'h00,
S1_PAGE=8'h00,
S2_PAGE=8'h00,
S3_PAGE=8'h00,
S4_PAGE=8'h00,
S5_PAGE=8'h00,
S6_PAGE=8'h00,
S7_PAGE=8'h00
) (
input wire HCLK,
input wire HRESETn,
// Master Interface
input wire [31:0] HADDR,
input wire [31:0] HWDATA,
output wire [31:0] HRDATA,
output wire HREADY,
// Slave # 0
output wire HSEL_S0,
input wire HREADY_S0,
input wire [31:0] HRDATA_S0,
// Slave # 1
output wire HSEL_S1,
input wire HREADY_S1,
input wire [31:0] HRDATA_S1,
// Slave # 2
output wire HSEL_S2,
input wire HREADY_S2,
input wire [31:0] HRDATA_S2,
// Slave # 3
output wire HSEL_S3,
input wire HREADY_S3,
input wire [31:0] HRDATA_S3,
// Slave # 4
output wire HSEL_S4,
input wire HREADY_S4,
input wire [31:0] HRDATA_S4,
// Slave # 5
output wire HSEL_S5,
input wire HREADY_S5,
input wire [31:0] HRDATA_S5,
// Slave # 6
output wire HSEL_S6,
input wire HREADY_S6,
input wire [31:0] HRDATA_S6,
// Slave # 7
output wire HSEL_S7,
input wire HREADY_S7,
input wire [31:0] HRDATA_S7
);
wire [7:0] PAGE = HADDR[31:24];
wire [7:0] HSEL = { HSEL_S7, HSEL_S6, HSEL_S5, HSEL_S4, HSEL_S3, HSEL_S2, HSEL_S1, HSEL_S0 };
reg [7:0] AHSEL;
always@ (posedge HCLK or negedge HRESETn) begin
if(HREADY)
AHSEL <= HSEL;
end
assign HSEL_S0 = (PAGE == S0_PAGE) & SLAVE_ENABLE[0];
assign HSEL_S1 = (PAGE == S1_PAGE) & SLAVE_ENABLE[1];
assign HSEL_S2 = (PAGE == S2_PAGE) & SLAVE_ENABLE[2];
assign HSEL_S3 = (PAGE == S3_PAGE) & SLAVE_ENABLE[3];
assign HSEL_S4 = (PAGE == S4_PAGE) & SLAVE_ENABLE[4];
assign HSEL_S5 = (PAGE == S5_PAGE) & SLAVE_ENABLE[5];
assign HSEL_S6 = (PAGE == S6_PAGE) & SLAVE_ENABLE[6];
assign HSEL_S7 = (PAGE == S7_PAGE) & SLAVE_ENABLE[7];
assign HREADY =
AHSEL[0] ? HREADY_S0 :
AHSEL[1] ? HREADY_S1 :
AHSEL[2] ? HREADY_S2 :
AHSEL[3] ? HREADY_S3 :
AHSEL[4] ? HREADY_S4 :
AHSEL[5] ? HREADY_S5 :
AHSEL[6] ? HREADY_S6 :
AHSEL[7] ? HREADY_S7 :
1'b1;
assign HRDATA =
AHSEL[0] ? HRDATA_S0 :
AHSEL[1] ? HRDATA_S1 :
AHSEL[2] ? HRDATA_S2 :
AHSEL[3] ? HRDATA_S3 :
AHSEL[4] ? HRDATA_S4 :
AHSEL[5] ? HRDATA_S5 :
AHSEL[6] ? HRDATA_S6 :
AHSEL[7] ? HRDATA_S7 :
32'hDEADBEEF;
endmodule
| 6.870344 |
module ahbl_master_assertions #(
parameter W_ADDR = 32,
parameter W_DATA = 32
) (
input wire clk,
input wire rst_n,
input wire src_hready,
input wire src_hresp,
input wire src_hexokay,
input wire [W_ADDR-1:0] src_haddr,
input wire src_hwrite,
input wire [ 1:0] src_htrans,
input wire [ 2:0] src_hsize,
input wire [ 2:0] src_hburst,
input wire [ 3:0] src_hprot,
input wire src_hmastlock,
input wire src_hexcl,
input wire [W_DATA-1:0] src_hwdata,
input wire [W_DATA-1:0] src_hrdata
);
// Data-phase monitoring
reg src_active_dph;
reg src_write_dph;
reg [W_ADDR-1:0] src_addr_dph;
reg [ 2:0] src_size_dph;
reg src_excl_dph;
reg global_reservation_valid;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
src_active_dph <= 1'b0;
src_write_dph <= 1'b0;
src_addr_dph <= {W_ADDR{1'b0}};
src_size_dph <= 3'h0;
src_excl_dph <= 1'b0;
global_reservation_valid <= 1'b0;
end else if (src_hready) begin
src_active_dph <= src_htrans[1];
src_write_dph <= src_hwrite;
src_addr_dph <= src_haddr;
src_size_dph <= src_hsize;
src_excl_dph <= src_hexcl && src_htrans[1];
if (src_excl_dph) global_reservation_valid <= src_hexokay && !src_write_dph;
end
end
// Assertions for all downstream requests
always @(posedge clk)
if (rst_n) begin : dst_ahbl_req_properties
// Address phase properties (inactive when request is IDLE):
if (src_htrans != 2'b00) begin
// Transfer must be naturally aligned
assert (!(src_haddr & ~({W_ADDR{1'b1}} << src_hsize)));
// HSIZE appropriate for bus width
assert (8 << src_hsize <= W_DATA);
// No deassertion or change of active request
if ($past(src_htrans[1] && !src_hready && !src_hresp)) begin
assert ($stable({src_htrans, src_hwrite, src_haddr, src_hsize, src_hburst, src_hprot,
src_hmastlock}));
end
// SEQ only issued following an NSEQ or SEQ, never an IDLE
if (src_htrans == 2'b11) assert (src_active_dph);
// SEQ transfer addresses must be sequential with previous transfer (note
// this only supports INCRx bursts)
if (src_htrans == 2'b11) assert (src_haddr == src_addr_dph + W_DATA / 8);
// No pipelining of exclusive transfers
if (src_excl_dph) assert (!(src_hexcl && src_htrans[1]));
end
// Data phase properties:
if (src_active_dph) begin
// Write data stable during write data phase
if (src_write_dph && !$past(src_hready)) assert ($stable(src_hwdata));
// An exclusive write must match a prior exclusive read which was HEXOKAY=1
if (src_write_dph && src_excl_dph) assert (global_reservation_valid);
end
end
endmodule
| 8.849642 |
module ahbl_slave_assumptions #(
parameter W_ADDR = 32,
parameter W_DATA = 32,
parameter MAX_BUS_STALL = -1 // set >= 0 to constrain max stall length
) (
input wire clk,
input wire rst_n,
input wire dst_hready_resp,
input wire dst_hready,
input wire dst_hresp,
input wire dst_hexokay,
input wire [W_ADDR-1:0] dst_haddr,
input wire dst_hwrite,
input wire [ 1:0] dst_htrans,
input wire [ 2:0] dst_hsize,
input wire [ 2:0] dst_hburst,
input wire [ 3:0] dst_hprot,
input wire dst_hmastlock,
input wire dst_hexcl,
input wire [W_DATA-1:0] dst_hwdata,
input wire [W_DATA-1:0] dst_hrdata
);
reg dst_active_dph;
reg dst_write_dph;
reg [W_ADDR-1:0] dst_addr_dph;
reg [ 2:0] dst_size_dph;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
dst_active_dph <= 1'b0;
dst_write_dph <= 1'b0;
dst_addr_dph <= {W_ADDR{1'b0}};
dst_size_dph <= 3'h0;
end else if (dst_hready) begin
dst_active_dph <= dst_htrans[1];
dst_write_dph <= dst_hwrite;
dst_addr_dph <= dst_haddr;
dst_size_dph <= dst_hsize;
end
end
// Assumptions for all downstream responses
always @(posedge clk)
if (rst_n) begin : dst_ahbl_resp_properties
// IDLE->OKAY
if (!dst_active_dph) begin
assume (dst_hready_resp);
assume (!dst_hresp);
end
// Correct two-phase error response.
if (dst_hresp && dst_hready) assume ($past(dst_hresp && !dst_hready));
if (dst_hresp && !dst_hready) assume ($past(!(dst_hresp && !dst_hready)));
if ($past(dst_hresp && !dst_hready)) assume (dst_hresp);
end
generate
if (MAX_BUS_STALL >= 0) begin : constrain_max_bus_stall
reg [7:0] bus_stall_ctr;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
bus_stall_ctr <= 8'h0;
end else begin
if (dst_hready) bus_stall_ctr <= 8'h0;
else bus_stall_ctr <= bus_stall_ctr + ~&bus_stall_ctr;
assume (bus_stall_ctr <= MAX_BUS_STALL);
end
end
end
endgenerate
endmodule
| 8.391163 |
module ahbl_to_apb #(
parameter W_HADDR = 32,
parameter W_PADDR = 16,
parameter W_DATA = 32
) (
input wire clk,
input wire rst_n,
input wire [W_HADDR-1:0] ahbls_haddr,
input wire ahbls_hwrite,
input wire [ 1:0] ahbls_htrans,
input wire [ 2:0] ahbls_hsize,
input wire [ 2:0] ahbls_hburst,
input wire [ 3:0] ahbls_hprot,
input wire ahbls_hmastlock,
input wire [ W_DATA-1:0] ahbls_hwdata,
input wire ahbls_hready,
output reg ahbls_hready_resp,
output reg ahbls_hresp,
output reg [ W_DATA-1:0] ahbls_hrdata,
output reg [W_PADDR-1:0] apbm_paddr,
output reg apbm_psel,
output reg apbm_penable,
output reg apbm_pwrite,
output reg [ W_DATA-1:0] apbm_pwdata,
input wire apbm_pready,
input wire [ W_DATA-1:0] apbm_prdata,
input wire apbm_pslverr
);
// Transfer state machine
localparam W_APB_STATE = 3;
localparam S_READY = 3'd0; // Idle upstream dphase or end of read/write dphase
localparam S_RD0 = 3'd1; // Downstream setup phase (cannot stall)
localparam S_RD1 = 3'd2; // Downstream access phase (may stall or error)
localparam S_WR0 = 3'd3; // Sample hwdata
localparam S_WR1 = 3'd4; // Downstream setup phase (cannot stall)
localparam S_WR2 = 3'd5; // Downstream access phase (may stall or error)
localparam S_ERR0 = 3'd6; // AHBL error response, first cycle
localparam S_ERR1 = 3'd7; // AHBL error response, and accept new address phase if not deasserted.
reg [W_APB_STATE-1:0] apb_state;
reg [W_APB_STATE-1:0] apb_state_nxt;
wire [W_APB_STATE-1:0] aphase_to_dphase =
ahbls_htrans[1] && ahbls_hwrite ? S_WR0 :
ahbls_htrans[1] && !ahbls_hwrite ? S_RD0 : S_READY;
always @(*) begin
apb_state_nxt = apb_state;
case (apb_state)
S_READY: if (ahbls_hready) apb_state_nxt = aphase_to_dphase;
S_WR0: apb_state_nxt = S_WR1;
S_WR1: apb_state_nxt = S_WR2;
S_WR2: if (apbm_pready) apb_state_nxt = apbm_pslverr ? S_ERR0 : S_READY;
S_RD0: apb_state_nxt = S_RD1;
S_RD1: if (apbm_pready) apb_state_nxt = apbm_pslverr ? S_ERR0 : S_READY;
S_ERR0: apb_state_nxt = S_ERR1;
S_ERR1: apb_state_nxt = aphase_to_dphase;
endcase
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
apb_state <= S_READY;
ahbls_hready_resp <= 1'b1;
ahbls_hresp <= 1'b0;
end else begin
apb_state <= apb_state_nxt;
ahbls_hready_resp <= apb_state_nxt == S_READY || apb_state_nxt == S_ERR1;
ahbls_hresp <= apb_state_nxt == S_ERR0 || apb_state_nxt == S_ERR1;
end
end
// Downstream request
always @(*) begin
case (apb_state)
S_RD0: {apbm_psel, apbm_penable, apbm_pwrite} = 3'b100;
S_RD1: {apbm_psel, apbm_penable, apbm_pwrite} = 3'b110;
S_WR1: {apbm_psel, apbm_penable, apbm_pwrite} = 3'b101;
S_WR2: {apbm_psel, apbm_penable, apbm_pwrite} = 3'b111;
default: {apbm_psel, apbm_penable, apbm_pwrite} = 3'b000;
endcase
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
apbm_paddr <= {W_PADDR{1'b0}};
apbm_pwdata <= {W_DATA{1'b0}};
end else begin
if (ahbls_htrans[1] && ahbls_hready) apbm_paddr <= ahbls_haddr[W_PADDR-1:0];
if (apb_state == S_WR0) apbm_pwdata <= ahbls_hwdata;
end
end
// Upstream response
always @(posedge clk or negedge rst_n)
if (!rst_n) ahbls_hrdata <= {W_DATA{1'b0}};
else if (apb_state == S_RD1 && apbm_pready) ahbls_hrdata <= apbm_prdata;
endmodule
| 8.660763 |
module AHBMAS_WBSLV_TOP (
hclk,
hresetn,
// AHB Master Interface (Connect to AHB Slave)
haddr,
htrans,
hwrite,
hsize,
hburst,
hwdata,
hrdata,
hready,
hresp,
// WISHBONE Slave Interface (Connect to WB Master)
data_o,
data_i,
addr_i,
clk_i,
rst_i,
cyc_i,
stb_i,
sel_i,
we_i,
ack_o
);
//PARAMETER
parameter AWIDTH = 32, DWIDTH = 32; //Address Width,Data Width
//INPUTS AND OUTPUTS
// --------------------------------------
//Top level ports for AHB
input hresetn; //AHB Clk
input hclk; //AHB Active Low Reset
// AHB Master Interface (Connect to AHB Slave)
input [DWIDTH-1:0] hrdata; //Read data bus
//Transfer Response from AHB Slave
input [1:0] hresp;
input hready;
//Address and Control Signals
output [AWIDTH-1:0] haddr; //Address
output hwrite; //Write/Read Control
output [2:0] hsize; //Size of Data Control
output [2:0] hburst; //Burst Control
output [31:0] hwdata; //Write data bus
output [1:0] htrans; //Transfer type
// --------------------------------------
// WISHBONE Slave Interface (Connect to WB Master)
output [DWIDTH-1:0] data_o; //Wishbobe Data Ouput
output ack_o; //Wishbone Acknowledge
input [DWIDTH-1:0] data_i; //Wishbone Data Input
input [AWIDTH-1:0] addr_i; //Wishbone Address Input
input cyc_i; //Wishbone Cycle Input
input stb_i; //Wishbone Strobe Input
input [3:0] sel_i; //Wishbone Selection Input
input we_i; //Wishbone Write/Read Control
input clk_i; //Wishbone Clk Input
input rst_i; //Wishbone Active High Reset Input
// datatype declaration
reg [AWIDTH-1:0] haddr;
wire hwrite;
reg [2:0] hsize;
reg [2:0] hburst;
reg [31:0] hwdata;
reg [1:0] htrans;
reg [DWIDTH-1:0] data_o;
reg ack_o;
//SIGNAL DECLARATIONS
reg flag;
reg hready_temp;
//*******************************************************************
// WISHBONE logic Write and Read Operation
//*******************************************************************
//ASSIGN STATEMENTS
assign #2 hwrite = we_i;
//Sysncronous Reset
always @(posedge clk_i) begin
// hready_temp <= hready;
if (rst_i) begin
hsize = 3'b010; //Size of Data Control
hburst = 3'b000; //Burst Control
// hready_temp <= 'b1;
flag <= 'b1;
end //Write Operation : Wait for a valid Cycle, Strobe and Active High Write enable signal
else if (cyc_i & stb_i) begin
if (we_i) begin //Write Cycle: No Need To Check for hready signal for data to be send out
hwdata <= data_i;
end //Read Operation : Wait for a valid Cycle, Strobe and Active Low Write enable signal
else begin // Read Cycle
if (hready) begin
if (flag) begin
flag <= #2'b0;
end else begin
flag <= #2'b1;
end
end
end
end
//else begin
//wb_ack_o<='b0;
//hwdata <= data_i;//when stb goes active low send asyncronously the data
//end
end
always @(we_i or stb_i or addr_i or flag or hready or hrdata) begin
if (we_i) begin
if (hready) begin
haddr <= addr_i;
end
end else begin
if (flag) begin
haddr <= addr_i; //During Flag set Accept Address
end else begin
data_o <= #2 hrdata; //During Flag reset Accept Data
end
end
end
//Logic for Acknowledge from Wishbone Slave
always @(we_i or addr_i or hrdata or hready or flag) begin
if (rst_i) begin
ack_o <= 'b0;
end else if (we_i) ack_o <= hready;
else ack_o <= !flag & hready;
end
//Logic for Transfer Type
always @(cyc_i or stb_i) begin
if (rst_i) begin
htrans <= 2'b00;
end else if (cyc_i) begin
if (stb_i) begin
htrans <= 2'b10; //Transfer type Non Sequential
end else begin
htrans <= 2'b01; //Transfer type Busy
end
end else begin
htrans <= 2'b00; //Transfer type Idle
end
end
endmodule
| 8.825463 |
module AHBQSPIFI (
// AHB-Lite Bus Interface
//Inputs
input wire HSEL,
input wire HCLK,
input wire HRESETn,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [31:0] HWDATA,
input wire HWRITE,
input wire HREADY,
//Output
output reg HREADYOUT,
output /*reg*/ [31:0] HRDATA,
// Flash Memory Interface
output wire spi_clk,
output wire spi_cs,
inout wire [3:0] spi_io
);
//State parameters
localparam [1:0] st_idle = 2'b00;
localparam [1:0] st_wait = 2'b01;
localparam [1:0] st_rw = 2'b10;
//Register select parameters
localparam [3:0] REG0 = 4'h0;
localparam [3:0] REG1 = 4'h4;
localparam [3:0] REG2 = 4'h8;
localparam [3:0] REG3 = 4'hC;
//State machine registers
reg [1:0] current_state;
reg [1:0] next_state;
reg [4:0] wait_reg;
reg [4:0] wait_next;
reg HREADYOUT_next;
//Data Regs
reg [31:0] d_reg0;
reg [31:0] d_reg1;
reg [31:0] d_reg2;
reg [31:0] d_reg3;
//AHB-Lite Address Phase Regs
reg last_HSEL;
reg [31:0] last_HADDR;
reg last_HWRITE;
reg [1:0] last_HTRANS;
// SPI FI Logic
reg ctrl_spi_start;
wire [3:0] spi_I, spi_O;
wire spi_oe;
wire [31:0] mem_addr = {12'd0, last_HADDR[19:0]};
wire [31:0] mem_data;
assign spi_I = spi_io;
assign spi_io = spi_oe ? spi_O : 4'bzzzz;
always @(posedge HCLK or negedge HRESETn)
if (!HRESETn) ctrl_spi_start <= 1'b0;
else if (HREADY & HSEL) ctrl_spi_start <= 1'b1;
else ctrl_spi_start <= 1'b0;
QSPIFI qspifi (
.clk(HCLK),
.reset(HRESETn),
.ahb_addr(last_HADDR),
.ctrl_addr_wr(1'b0),
.ctrl_spi_start(ctrl_spi_start),
.spi_data(mem_data),
.spi_I(spi_I),
.spi_O(spi_O),
.spi_obuf_en(spi_oe),
.spi_CS(spi_cs),
.spi_clk(spi_clk)
);
// AHB Interface Logic
always @(posedge HCLK) begin
if (HREADY) begin
last_HSEL <= HSEL;
last_HADDR <= HADDR;
last_HWRITE <= HWRITE;
last_HTRANS <= HTRANS;
end
end
//State Machine
always @(posedge HCLK, negedge HRESETn) begin
if (!HRESETn) begin
current_state <= st_idle;
HREADYOUT <= 1'b0;
wait_reg <= 4'h0;
end else begin
current_state <= next_state;
HREADYOUT <= HREADYOUT_next;
wait_reg <= wait_next;
end
end
//Next State Logic
always @* begin
next_state = current_state;
HREADYOUT_next = 1'b0;
wait_next = wait_reg;
case (current_state)
st_idle:
if (HSEL & HREADY) begin
next_state = st_wait;
wait_next = 5'd29;
end
st_wait:
if (wait_reg == 0) begin
next_state = st_idle;
HREADYOUT_next = 1'b1;
end else wait_next = wait_reg - 1'b1;
endcase
end
assign HRDATA = mem_data;
endmodule
| 8.366921 |
module ahbslave (
HCLK,
HRESETn,
HADDR,
HADDR_1,
HADDR_2,
HWDATA,
HWDATA_1,
HWDATA_2,
HWRITE,
HWRITEreg,
HRESP,
HRDATA,
PRDATA,
TEMP_SEL,
valid,
HTRANS,
HREADYin
);
//slave memory map
parameter slave0_0 = 32'h8000_0000, slave0_1 = 32'h8400_0000;
parameter slave1_0 = 32'h8400_0001, slave1_1 = 32'h8800_0000;
parameter slave2_0 = 32'h8800_0001, slave2_1 = 32'h8c00_0000;
parameter IDLE = 2'b00, WAIT = 2'b01, NONSEQ = 2'b10, SEQ = 2'b11;
//Input declaration
input HCLK, HRESETn;
input HREADYin, HWRITE;
input [1:0] HTRANS;
input [31:0] HADDR, HWDATA, PRDATA;
//Output declaration
//reg internal register
output reg HWRITEreg, valid;
output reg [1:0] HRESP;
output reg [2:0] TEMP_SEL;
output reg [31:0] HADDR_1, HADDR_2, HWDATA_1, HWDATA_2;
output [31:0] HRDATA;
//assigning prdata = hr data
assign HRDATA = PRDATA;
//pipelining
always @(posedge HCLK, negedge HRESETn) begin
HRESP = 0;
if (~HRESETn) begin
HADDR_1 <= 0;
HADDR_2 <= 0;
HWDATA_1 <= 0;
HWDATA_2 <= 0;
end else begin
HADDR_1 <= HADDR;
HADDR_2 <= HADDR_1;
HWDATA_1 <= HWDATA;
HWDATA_2 <= HWDATA_1;
end
end
//hwritereg transfer
always @(*) begin
if((HADDR>=slave0_0 && HADDR<= slave2_1) && (HTRANS!=IDLE && HTRANS!=WAIT) && (HREADYin==1'b1))
valid = 1'b1;
else valid = 1'bx;
end
// tempsel output generation
always @(*) begin
if (slave0_1 >= HADDR >= slave0_0) TEMP_SEL = 3'b001;
else if (slave1_1 >= HADDR >= slave1_0) TEMP_SEL = 3'b010;
else if (slave2_1 >= HADDR >= slave2_0) TEMP_SEL = 3'b100;
else TEMP_SEL = 3'b100;
end
// hwritereg transfer
always @(posedge HCLK, negedge HRESETn) begin
if (~HRESETn) HWRITEreg <= 0;
else HWRITEreg <= HWRITE;
end
endmodule
| 6.511504 |
module AHBSYSMUX (
input wire HCLK,
input wire HRESETn,
input wire [2:0] MUX_SEL,
input wire [31:0] HRDATA_S0, // SRAM
input wire [31:0] HRDATA_S1, // LED
input wire [31:0] HRDATA_S2, // UART
input wire [31:0] HRDATA_S3, // GPIO
input wire [31:0] HRDATA_S4, //
input wire [31:0] HRDATA_S5, //
input wire [31:0] HRDATA_S6, //
input wire [31:0] HRDATA_NO_MAP, // no map
input wire HREADYOUT_S0,
input wire HREADYOUT_S1,
input wire HREADYOUT_S2,
input wire HREADYOUT_S3,
input wire HREADYOUT_S4,
input wire HREADYOUT_S5,
input wire HREADYOUT_S6,
input wire HREADYOUT_NO_MAP,
output reg HREADY,
output reg [31:0] HRDATA
);
reg [2:0] MUX_SEL_tmp;
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
MUX_SEL_tmp <= 3'b111;
end else if (HREADY) begin
MUX_SEL_tmp <= MUX_SEL;
end
end
always @(*) begin
case (MUX_SEL_tmp)
3'b000: begin
HREADY <= HREADYOUT_S0;
HRDATA <= HRDATA_S0;
end
3'b001: begin
HREADY <= HREADYOUT_S1;
HRDATA <= HRDATA_S1;
end
3'b010: begin
HREADY <= HREADYOUT_S2;
HRDATA <= HRDATA_S2;
end
3'b011: begin
HREADY <= HREADYOUT_S3;
HRDATA <= HRDATA_S3;
end
3'b100: begin
HREADY <= HREADYOUT_S4;
HRDATA <= HRDATA_S4;
end
3'b101: begin
HREADY <= HREADYOUT_S5;
HRDATA <= HRDATA_S5;
end
3'b110: begin
HREADY <= HREADYOUT_S6;
HRDATA <= HRDATA_S6;
end
3'b111: begin
HREADY <= HREADYOUT_NO_MAP;
HRDATA <= HRDATA_NO_MAP;
end
endcase
end
endmodule
| 6.692968 |
module AHBUART (
//AHB Signals
input wire HCLK,
input wire HRESETn,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire [31:0] HWDATA,
input wire HWRITE,
input wire HREADY,
output wire HREADYOUT,
output wire [31:0] HRDATA,
input wire HSEL,
//Serial Port Signals
input wire RsRx, //Input from RS-232
output wire RsTx, //Output to RS-232
//UART Interrupt
output wire uart_irq //Interrupt
);
//Internal Signals
//Data I/O between AHB and FIFO
wire [7:0] uart_wdata;
wire [7:0] uart_rdata;
//Signals from TX/RX to FIFOs
wire uart_wr;
wire uart_rd;
//wires between FIFO and TX/RX
wire [7:0] tx_data;
wire [7:0] rx_data;
wire [7:0] status;
//FIFO Status
wire tx_full;
wire tx_empty;
wire rx_full;
wire rx_empty;
//UART status ticks
wire tx_done;
wire rx_done;
//baud rate signal
wire b_tick;
//AHB Regs
reg [1:0] last_HTRANS;
reg [31:0] last_HADDR;
reg last_HWRITE;
reg last_HSEL;
//Set Registers for AHB Address State
always @(posedge HCLK) begin
if (HREADY) begin
last_HTRANS <= HTRANS;
last_HWRITE <= HWRITE;
last_HSEL <= HSEL;
last_HADDR <= HADDR;
end
end
//If Read and FIFO_RX is empty - wait.
assign HREADYOUT = ~tx_full;
//UART write select
assign uart_wr = last_HTRANS[1] & last_HWRITE & last_HSEL & (last_HADDR[7:0] == 8'h00);
//Only write last 8 bits of Data
assign uart_wdata = HWDATA[7:0];
//UART read select
assign uart_rd = last_HTRANS[1] & ~last_HWRITE & last_HSEL & (last_HADDR[7:0] == 8'h00);
assign HRDATA = (last_HADDR[7:0] == 8'h00) ? {24'h0000_00, uart_rdata} : {24'h0000_00, status};
assign status = {6'b000000, tx_full, rx_empty};
assign uart_irq = ~rx_empty;
//generate a fixed baud rate 19200bps
BAUDGEN uBAUDGEN (
.clk(HCLK),
.resetn(HRESETn),
.baudtick(b_tick)
);
//Transmitter FIFO
FIFO #(
.DWIDTH(8),
.AWIDTH(4)
) uFIFO_TX (
.clk(HCLK),
.resetn(HRESETn),
.rd(tx_done),
.wr(uart_wr),
.w_data(uart_wdata[7:0]),
.empty(tx_empty),
.full(tx_full),
.r_data(tx_data[7:0])
);
//Receiver FIFO
FIFO #(
.DWIDTH(8),
.AWIDTH(4)
) uFIFO_RX (
.clk(HCLK),
.resetn(HRESETn),
.rd(uart_rd),
.wr(rx_done),
.w_data(rx_data[7:0]),
.empty(rx_empty),
.full(rx_full),
.r_data(uart_rdata[7:0])
);
//UART receiver
UART_RX uUART_RX (
.clk(HCLK),
.resetn(HRESETn),
.b_tick(b_tick),
.rx(RsRx),
.rx_done(rx_done),
.dout(rx_data[7:0])
);
//UART transmitter
UART_TX uUART_TX (
.clk(HCLK),
.resetn(HRESETn),
.tx_start(!tx_empty),
.b_tick(b_tick),
.d_in(tx_data[7:0]),
.tx_done(tx_done),
.tx(RsTx)
);
endmodule
| 6.812607 |
module AHBVGA (
input wire HCLK,
input wire HRESETn,
input wire [31:0] HADDR,
input wire [31:0] HWDATA,
input wire HREADY,
input wire HWRITE,
input wire [1:0] HTRANS,
input wire HSEL,
output wire [31:0] HRDATA,
output wire HREADYOUT,
output wire HSYNC,
output wire VSYNC,
output wire [7:0] RGB
);
//Register locations
localparam IMAGEADDR = 4'hA;
localparam CONSOLEADDR = 4'h0;
//Internal AHB signals
reg last_HWRITE;
reg last_HSEL;
reg [ 1:0] last_HTRANS;
reg [31:0] last_HADDR;
wire [ 7:0] console_rgb; //console rgb signal
wire [ 9:0] pixel_x; //current x pixel
wire [ 9:0] pixel_y; //current y pixel
reg console_write; //write to console
reg [ 7:0] console_wdata; //data to write to console
reg image_write; //write to image
reg [ 7:0] image_wdata; //data to write to image
wire [ 7:0] image_rgb; //image color
wire scroll; //scrolling signal
wire sel_console;
wire sel_image;
reg [ 7:0] cin;
always @(posedge HCLK)
if (HREADY) begin
last_HADDR <= HADDR;
last_HWRITE <= HWRITE;
last_HSEL <= HSEL;
last_HTRANS <= HTRANS;
end
//Give time for the screen to refresh before writing
assign HREADYOUT = ~scroll;
//Assign HRDATA
assign HRDATA = 0;
//VGA interface: control the synchronization and color signals for a particular resolution
VGAInterface uVGAInterface (
.CLK(HCLK),
.resetn(HRESETn),
.COLOUR_IN(cin),
.cout(RGB),
.hs(HSYNC),
.vs(VSYNC),
.addrh(pixel_x),
.addrv(pixel_y)
);
//VGA console module: output the pixels in the text region
vga_console uvga_console (
.clk(HCLK),
.resetn(HRESETn),
.pixel_x(pixel_x),
.pixel_y(pixel_y),
.text_rgb(console_rgb),
.font_we(console_write),
.font_data(console_wdata),
.scroll(scroll)
);
//VGA image buffer: output the pixels in the image region
vga_image uvga_image (
.clk(HCLK),
.resetn(HRESETn),
.address(last_HADDR[15:2]),
.pixel_x(pixel_x),
.pixel_y(pixel_y),
.image_we(image_write),
.image_data(image_wdata),
.image_rgb(image_rgb)
);
assign sel_console = (last_HADDR[23:0] == 12'h000000000000);
assign sel_image = (last_HADDR[23:0] != 12'h000000000000);
//Set console write and write data
always @(posedge HCLK, negedge HRESETn) begin
if (!HRESETn) begin
console_write <= 0;
console_wdata <= 0;
end else if (last_HWRITE & last_HSEL & last_HTRANS[1] & HREADYOUT & sel_console) begin
console_write <= 1'b1;
console_wdata <= HWDATA[7:0];
end else begin
console_write <= 1'b0;
console_wdata <= 0;
end
end
//Set image write and image write data
always @(posedge HCLK, negedge HRESETn) begin
if (!HRESETn) begin
image_write <= 0;
image_wdata <= 0;
end else if (last_HWRITE & last_HSEL & last_HTRANS[1] & HREADYOUT & sel_image) begin
image_write <= 1'b1;
image_wdata <= HWDATA[7:0];
end else begin
image_write <= 1'b0;
image_wdata <= 0;
end
end
//Select the rgb color for a particular region
always @* begin
if (!HRESETn) cin <= 8'h00;
else if (pixel_x[9:0] <= 240) //Changed from < to <=
cin <= console_rgb;
else cin <= 8'h00;
end
endmodule
| 7.747442 |
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