code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module AhaClockSwitch2 (
// Inputs
input wire MASTER_CLK0,
input wire MASTER_CLK1,
input wire SELECT,
// Outputs
output wire CLK_OUT
);
wire m0_clk;
wire m1_clk;
wire m0_sel;
wire m1_sel;
AhaClockSwitchSlice u_m0_clk_switch_slice (
.CLK (MASTER_CLK0),
.SELECT_... | 9.473661 |
module AhaClockSwitchSlice (
// Inputs
input wire CLK,
input wire SELECT_REQ,
// Others
input wire OTHERS_SELECT,
// Outputs
output wire CLK_OUT,
output wire SELECT_ACK
);
//
// Internal Signals
//
reg r_EN_STAGE0_SYNC;
reg r_EN_STAGE1;
reg r_EN;
wire w_CLK_OUT;
/... | 9.473661 |
module AhaCounter #(
parameter WIDTH = 8
) (
input wire CLK,
input wire RESETn,
input wire EN,
output wire [WIDTH-1:0] Q
);
reg [WIDTH-1:0] count_val;
always @(posedge CLK or negedge RESETn) begin
if (~RESETn) count_val <= {WIDTH{1'b0}};
else if (... | 7.418681 |
module AhaDataSync (
// Inputs
input wire CLK,
input wire RESETn,
input wire D,
// Outputs
output wire Q
);
reg sync_q;
reg sync_qq;
always @(posedge CLK or negedge RESETn) begin
if (~RESETn) begin
sync_q <= 1'b0;
sync_qq <= 1'b0;
end else begin
sync_q <= D;... | 6.819975 |
module AhaEnGenerator (
// Source Clock and Reset
input wire CLK,
input wire RESETn,
// Clock Enable Signals
output wire By2CLKEN,
output wire By4CLKEN,
output wire By8CLKEN,
output wire By16CLKEN,
output wire By32CLKEN
);
reg [4:0] counter_r;
reg by2clk_en_r;
reg ... | 7.168404 |
module AhaFreqDivider (
// Source Clock and Reset
input wire CLK,
input wire RESETn,
// Divided Clocks
output wire By2CLK,
output wire By4CLK,
output wire By8CLK,
output wire By16CLK,
output wire By32CLK
);
// Counter register
reg [4:0] counter;
// Generated Clocks
reg ... | 6.757503 |
module AhaLoopBackGen (
input wire [3:0] SELECT,
// Clocks
input wire SYS_CLK,
input wire CPU_CLK,
input wire DAP_CLK,
input wire DP_JTAG_CLK,
input wire UART0_CLK,
input wire SRAM_CLK,
input wire NIC_CLK,
// Debug Signals
input wire DBG_PWR_UP_REQ,
input wire DBG_PWR_U... | 7.354291 |
module AhaResetGen #(
parameter NUM_CYCLES = 1
) (
input wire CLK,
input wire PORESETn,
input wire REQ,
output wire ACK,
output wire Qn
);
// Synchronized Resets
wire poresetn_sync;
wire req_sync;
// Reset Cycles
reg [NUM_CYCLES:0] rst_cycles;
reg [NUM_CYCLES:0] ack_cycles;
/... | 7.207033 |
module AhaResetGenX4 #(
parameter NUM_CYCLES = 1
) (
input wire CLK,
input wire PORESETn,
// Reset Request Lane 0
input wire REQ_0,
output wire ACK_0,
// Reset Request Lane 1
input wire REQ_1,
output wire ACK_1,
// Reset Request Lane 2
input wire REQ_2,
output wire ... | 6.619256 |
module AhaResetSync (
// Inputs
input wire CLK,
input wire Dn,
// Outputs
output wire Qn
);
reg sync_q;
reg sync_qq;
always @(posedge CLK or negedge Dn) begin
if (~Dn) begin
sync_q <= 1'b0;
sync_qq <= 1'b0;
end else begin
sync_q <= 1'b1;
sync_qq <= sync_q;
... | 7.055947 |
module AhaRomTable (
input PCLK, // APB Clock
input PRESETn, // APB Reset
input PSEL, // APB Select
input PENABLE, // APB Enable
input [11:2] PADDR, // APB Address
input PWRITE, // APB Write
output [31:0] PRDATA // APB Read Data
);
... | 7.311897 |
module AhaSram32Kx32 #(
parameter IMAGE_FILE = "None"
) (
input wire CLK,
input wire RESETn,
input wire CEn,
input wire [ 3:0] WEn,
input wire [14:0] A,
input wire [31:0] D,
output wire [31:0] Q
);
//
// Instantiate SIM SRAM Generator
//
AhaSramSimGen... | 6.56025 |
module AhaSram4Kx64 #(
parameter IMAGE_FILE = "None"
) (
input wire CLK,
input wire RESETn,
input wire CEn,
input wire [ 7:0] WEn,
input wire [11:0] A,
input wire [63:0] D,
output wire [63:0] Q
);
//
// Instantiate SIM SRAM Generator
//
AhaSramSimGen ... | 6.837859 |
module AhaSramSimGen #(
parameter ADDR_WIDTH,
parameter DATA_WIDTH,
parameter IMAGE_FILE
) (
input wire CLK,
input wire RESETn,
input wire CS,
input wire [(DATA_WIDTH/8)-1:0] WE,
input wire [ (ADDR_WIDTH-1):0] ADDR,
... | 7.340686 |
module AhaSyncPulseGen (
input wire CLK,
input wire RESETn,
input wire D,
output wire RISE_PULSE,
output wire FALL_PULSE
);
reg d_r;
always @(posedge CLK or negedge RESETn) begin
if (~RESETn) d_r <= 1'b0;
else d_r <= D;
end
assign RISE_PULSE = D & ~d_r;
assign FALL_PULSE = ~D... | 7.560093 |
module AhaSysResetReqGen (
// Clock and Reset
input wire CLK,
input wire RESETn,
// Input Requests
input wire SYSRESETREQ,
input wire LOCKUP,
input wire LOCKUP_RESET_EN,
input wire WDOG_TIMEOUT_RESET,
input wire WDOG_TIMEOUT_RESET_EN,
// Combined System Reset Request
output... | 8.522256 |
module AhaTimerIntegration (
// Bus Interface
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire HWRITE,
input wire [ 2:0] HSIZE,
input wire [ 2:0] HBURST,
input wire [ 3:0] HPROT,
input wire [31:... | 7.50605 |
module AhaTlxDataSync #(
parameter WIDTH = 1
) (
// Inputs
input wire SRC_CLK,
input wire SRC_RESETn,
input wire DEST_CLK,
input wire DEST_RESETn,
input wire [WIDTH-1:0] D,
// Outputs
output wire [WIDTH-1:0] Q
);
// For Synopsys DW IP
/*
DW_data_sync #(
.width (W... | 8.543662 |
module AhaTlxOutputLane (
input wire CLK, // Clock
input wire RESETn, // Reset
input wire D_IN, // TLX Data
input wire START, // Start Pulse
input wire CLEAR, // Clear Pulse (Clears DONE)
input wire [31:0] SEQUENCE, // Sequence to send out
input wire [31:0] LENGTH, // Trip cou... | 7.342798 |
module AhaTlxPulseSync (
// Inputs
input wire SRC_CLK,
input wire SRC_RESETn,
input wire DEST_CLK,
input wire DEST_RESETn,
input wire D,
// Outputs
output wire Q
);
CW_pulse_sync #(
.reg_event (1),
.f_sync_type(2),
.pulse_mode (1)
) u_aha_tlx_pulse_sync (
... | 7.121637 |
module AhaUartIntegration (
// Bus Interface
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire HWRITE,
input wire [ 2:0] HSIZE,
input wire [ 2:0] HBURST,
input wire [ 3:0] HPROT,
input wire [31:0... | 7.339938 |
module AhaWdogIntegration (
// Bus Interface
input wire HCLK, // Interconnect Clock
input wire HRESETn, // Interconnect Reset (synched to HCLK)
input wire HSEL,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire HWRITE,
input wire [ 2:0] HSIZE,
input wire... | 7.231148 |
module ahb2apb (
apb_haddr,
apb_hburst,
apb_hrdata,
apb_hready,
apb_hresp,
apb_hsel,
apb_hsize,
apb_htrans,
apb_hwdata,
apb_hwrite,
haddr_s2,
hburst_s2,
hmastlock,
hprot_s2,
hrdata_s2,
hready_s2,
hresp_s2,
hsel_s2,
hsize_s2,
htrans_s2,
... | 7.181983 |
module AHB2MEM #(
parameter MEMWIDTH = 14
) // SIZE[Bytes] = 2 ^ MEMWIDTH[Bytes] = 2 ^ MEMWIDTH / 4[Entries]
(
//AHBLITE INTERFACE
//Slave Select Signals
input wire HSEL,
//Global Signal
input wire HCLK,
input wire HRESETn,
//Address, Control & Write Data
input wire HREADY,
inpu... | 6.873488 |
module AHB2BUTTON (
input wire HCLK,
input wire HRESETn,
input wire button_in,
output wire button_out, // ⲿֵ
output reg button_tick
);
localparam st_idle = 2'b00;
localparam st_wait1 = 2'b01;
localparam st_stable = 2'b10;
localparam st_wait0 = 2'b11;
reg [ 1:0] current_state = st_idle... | 6.844729 |
module can_crc (
data,
crc_en,
clk,
n_rst,
crc_out
);
output [14:0] crc_out;
input data, crc_en, clk, n_rst;
wire n18, n26, n30, n32, n38, n40, n46, n1, n2, n3, n4, n5, n6, n7, n8, n9,
n10, n11, n12, n13, n14, n15, n16, n20, n22, n24, n28, n34, n36, n42;
DFFSR \crc_out_reg[0] (
... | 6.880719 |
module tx_sr (
clk,
n_rst,
tx_enable,
load_enable,
tx_data,
tx_out
);
input [31:0] tx_data;
input clk, n_rst, tx_enable, load_enable;
output tx_out;
flex_pts_sr_NUM_BITS32_SHIFT_MSB1 TX_SR (
.clk(clk),
.n_rst(n_rst),
.shift_enable(tx_enable),
.load_enable(load_e... | 7.061752 |
module rx_sr (
clk,
n_rst,
rx_enable,
can_bus_data,
rx_data
);
output [31:0] rx_data;
input clk, n_rst, rx_enable, can_bus_data;
flex_stp_sr_NUM_BITS32_SHIFT_MSB1 RX_SR (
.clk(clk),
.n_rst(n_rst),
.shift_enable(rx_enable),
.serial_in(can_bus_data),
.parallel_out... | 6.664377 |
module AHB2CAN_top_t (
HCLK,
HRESETn,
HWRITE,
HSEL,
HADDR,
HWDATA,
HTRANS,
HBURST,
HSIZE,
HRDATA,
HRESP,
HREADYOUT,
rx_data,
tx_data
);
input [31:0] HADDR;
input [31:0] HWDATA;
input [1:0] HTRANS;
input [2:0] HBURST;
input [2:0] HSIZE;
output [31:0] HR... | 6.737189 |
module AHB2GPIO (
input wire HCLK,
input wire HRESETn,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [31:0] HWDATA,
input wire HWRITE,
input wire HSEL,
input wire HREADY,
output wire HREADYOUT,
output wire [31:0] HRDATA,
// GPIO Ports
in... | 6.514349 |
module AHB2LED (
//AHBLITE INTERFACE
//Slave Select Signals
input wire HSEL,
//Global Signal
input wire HCLK,
input wire HRESETn,
//Address, Control & Write Data
input wire HREADY,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire HWRITE,
input wire [2:0] HSIZE... | 6.594381 |
module AHB2MEM #(
parameter MEMWIDTH = 16
) // SIZE = 64KB = 8 KWords
(
//AHBLITE INTERFACE
//Slave Select Signals
input wire HSEL,
//Global Signal
input wire HCLK,
input wire HRESETn,
//Address, Control & Write Data
input wire HREADY,
input wire [31:0] HADDR,
input wire [1:... | 6.873488 |
module AHB2MEM #(
parameter MEMWIDTH = 12
) // SIZE = 1KB = 256 Words
(
//AHBLITE INTERFACE
//Slave Select Signals
input wire HSEL,
//Global Signal
input wire HCLK,
input wire HRESETn,
//Address, Control & Write Data
input wire HREADY,
input wire [31:0] HADDR,
input wire [1:... | 6.873488 |
module ahb2ocp_ram (
clk,
rst_n,
rd_e,
addr,
rdata,
wr_e,
wdata,
be,
cs
);
// Default parameters
parameter WORDS = 8;
parameter DATA_SIZE = 1;
parameter ADDR_SIZE = 3;
input clk; // clock synchronizes all read inputs
input rst_n; // asynchronous reset in rclk domain... | 8.316932 |
module AHB2RAM #(
parameter MEMWIDTH = 15
) // Size = 32KB
(
input wire HSEL,
input wire HCLK,
input wire HRESETn,
input wire HREADY,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire HWRITE,
input wire [ 2:0] HSIZE,
input ... | 7.962486 |
module ahb2regbus (
//AHB IF
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [`AHB_ADDR_WIDTH - 1 : 0] HADDR,
input wire HWRITE,
input wire [1:0] HTRANS,
input wire [2:0] HBURST,
input wire [`AHB_DATA_WIDTH - 1 : 0] HWDATA,
output wire HREADY,
output reg [1:0... | 6.922833 |
module AHB2ROM #(
parameter MEMWIDTH = 15
) // Size = 32KB
(
input wire HSEL,
input wire HCLK,
input wire HRESETn,
input wire HREADY,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire HWRITE,
input wire [ 2:0] HSIZE,
input ... | 7.60337 |
module AHB2SLAVE #(
parameter PixelBitWidth = 8,
parameter Height = 32,
parameter Width = 32
) (
//AHBLITE INTERFACE
//Slave Select Signals
input wire HSEL,
//Global Signal
input wire HCLK,
input wire HRESETn,
//Address, Control & Write Data
input wire HREADY,
input wire ... | 7.091131 |
module AHB2TUART (
//AHBLITE INTERFACE
//Slave Select Signals
input wire HSEL,
//Global Signal
input wire HCLK,
input wire HRESETn,
//Address, Control & Write Data
input wire HREADY,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire HWRITE,
input wire [2:0] H... | 7.355591 |
module has to start at address 0.
It occupies 8 bytes (2 words) only
*/
//`default_nettype none
module AHB2TWROM
(
//AHBLITE INTERFACE
//Slave Select Signals
input wire HSEL,
//Global Signal
input wire HCLK,
input wire HRESETn,
//Address, Control & Write Data
input wire HREADY,
input wire [31:0... | 6.811751 |
module ahb2wb (
adr_o,
dat_o,
dat_i,
ack_i,
cyc_o,
we_o,
stb_o,
hclk,
hresetn,
haddr,
htrans,
hwrite,
hsize,
hburst,
hsel,
hwdata,
hrdata,
hresp,
hready,
clk_i,
rst_i
);
//parameter declaration
parameter AWIDTH = 32;
parameter D... | 9.917351 |
module AHB64_ATP ();
reg SysRST;
wire SysRST_N;
reg HCLK;
wire [35:0] HADDR;
wire HWRITE, HMASTLOCK;
wire [63:0] HWDATA;
wire [2:0] HSIZE;
wire [2:0] HBURST;
wire [3:0] HPROT;
wire [1:0] HTRANS;
//Master side ports (MUXed)
wire [63:0] HRDATAM;
wire HREADYM;
wire [1:0] HRESPM;
//AHB Perih... | 6.513614 |
module AHB7SEGDEC (
//Input
input wire HCLK,
input wire HRESETn,
input wire [31:0] HADDR,
input wire [31:0] HWDATA,
input wire [1:0] HTRANS,
input wire HWRITE,
input wire HSEL,
input wire HREADY,
//Output
output [31:0] HRDATA,
output HREADYOUT,
//7segment displa
... | 7.503795 |
module AHB7SEGDEC (
//AHBLITE INTERFACE
//Slave Select Signals
input wire HSEL,
//Global Signal
input wire HCLK,
input wire HRESETn,
//Address, Control & Write Data
input wire HREADY,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire HWRITE,
input wire [2:0] HS... | 7.503795 |
module AHBDUMMY2 (
//Inputs
input wire HSEL,
input wire HCLK,
input wire HRESETn,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [31:0] HWDATA,
input wire HWRITE,
input wire HREADY,
//Output
output reg HREADYOUT,
output reg [31:0] HRDATA
);
//State param... | 6.980403 |
module AHBGPIO (
input wire HCLK,
input wire HRESETn,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [31:0] HWDATA,
input wire HWRITE,
input wire HSEL,
input wire HREADY,
input wire [15:0] GPIOIN,
//Output
output wire HREADYOUT,
output wire [31:0] HRDATA,
... | 6.767078 |
module ahbl0_ipgen_lscc_ahbl_prio_arb #(
parameter M = 32
) (
// -----------------------------------------------------------------------------
// Module Parameters
// -----------------------------------------------------------------------------
// ----------------------------------------------------... | 8.795294 |
module ahbl0_ipgen_lscc_ahbl_decoder_prim #(
parameter F = 8,
parameter M_ADDR_WIDTH = 32,
parameter FULL_DECODE_EN = 1,
parameter FRAGMENT_EN = 4'd1,
parameter [((F * 32) - 1):0] BASE_ADDR = {
32'h0, 32'h0, 32'h0, 32'h0, 32'h0, 32'h0, 32'h0, 32'h0
},
parameter [((F * 32) - 1):0] ADDR_... | 8.795294 |
module ahbl0_ipgen_lscc_ahbl_decoder_comp #(
parameter FULL_DECODE_EN = 1,
parameter BASE_ADDR = 32'h0,
parameter ADDR_RANGE = 32'h400,
parameter ADDR_WIDTH = 32
) (
// ------------------------------------------------------------------------------
// Module Parameters
// --------------------... | 8.795294 |
module ahbl0_ipgen_lscc_ahbl_default_slv #(
parameter DATA_WIDTH = 32
) (
// -----------------------------------------------------------------------------
// Module Parameters
// -----------------------------------------------------------------------------
// ----------------------------------------... | 8.795294 |
module ahbl2apb_top (
input clk_i,
input rst_n_i,
input pclk_i,
input presetn_i,
input ahbl_mstr_dummy_in,
output ahbl_mstr_dummy_out,
input apb_slv_dummy_in,
output apb_slv_dummy_out
);
`include "dut_params.v"
wire pclk_w;
wire presetn_w;
wi... | 6.906275 |
module AHBLite2AvalonMemoryMapped #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32
) (
clk,
reset_n,
ahb_haddr,
ahb_hwrite,
ahb_hsize,
ahb_hburst,
ahb_hmastlock,
ahb_hprot,
ahb_htrans,
ahb_hwdata,
ahb_hrdata,
ahb_hready,
ahb_hresp,
avl_address,
... | 8.394763 |
module AHBLiteMaster (
HREADY,
HRESETn,
HCLK,
HRDATA,
WRITE,
ADDR,
WDATA,
HADDR,
HWRITE,
HWDATA,
RDATA
);
parameter ADDR_WIDTH = 32;
parameter DATA_WIDTH = 32;
input HRESETn;
input HCLK;
input [ADDR_WIDTH - 1:0] ADDR;
input WRITE;
input [DATA_WIDTH - 1:0] WDAT... | 8.496748 |
module AHBlite_Block_RAM #(
parameter ADDR_WIDTH = 14
) (
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [2:0] HSIZE,
input wire [3:0] HPROT,
input wire HWRITE,
input wire [31:0] HWDATA,
input wire HREADY,
... | 7.162418 |
module AHBlite_Block_RAM_FM_Data #(
parameter FM_ADDR_WIDTH = 6
) (
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [ 31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire [ 2... | 7.162418 |
module AHBlite_Block_ROM #(
parameter ADDR_WIDTH = 13
) (
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [ 31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire [ 2:0] HSIZE,
input wire [... | 7.162418 |
module AHBlite_BUS0 (
input wire HCLK,
input wire HRESETn,
// Master Interface
input wire [31:0] HADDR,
input wire [31:0] HWDATA,
output wire [31:0] HRDATA,
output wire HREADY,
// Slave # 0
output wire HSEL_S0,
input wire HREADY_S0,
input wire [31:0]... | 6.683942 |
module AHBlite_BusMatrix_Arbiter_ACCC (
input HCLK,
input HRESETn,
input REQ_SYS,
input REQ_DMA,
input HREADY_Outputstage_ACCC,
input HSEL_Outputstage_ACCC,
input [1:0] HTRANS_Outputstage_ACCC,
input [2:0... | 7.446207 |
module AHBlite_BusMatrix_Arbiter_CAMERA (
input HCLK,
input HRESETn,
input REQ_SYS,
input REQ_DMA,
input REQ_ACC,
input HREADY_Outputstage_CAMERA,
input HSEL_Outputstage_CAMERA,
input [1:0] HTRANS_O... | 7.446207 |
module AHBlite_BusMatrix_Arbiter_DMAC (
input HCLK,
input HRESETn,
input REQ_SUB,
input HREADY_Outputstage_DMAC,
input HSEL_Outputstage_DMAC,
input [1:0] HTRANS_Outputstage_DMAC,
input [2:0] HBURST_Outputstage_DMAC,
... | 7.446207 |
module AHBlite_BusMatrix_Arbiter_DTCM (
input HCLK,
input HRESETn,
input REQ_SYS,
input REQ_DMA,
input REQ_ACC,
input HREADY_Outputstage_DTCM,
input HSEL_Outputstage_DTCM,
input [1:0] HTRANS_Outputs... | 7.446207 |
module AHBlite_BusMatrix_Arbiter_GPIO (
input HCLK,
input HRESETn,
input REQ_SUB,
input HREADY_Outputstage_GPIO,
input HSEL_Outputstage_GPIO,
input [1:0] HTRANS_Outputstage_GPIO,
input [2:0] HBURST_Outputstage_GPIO,
... | 7.446207 |
module AHBlite_BusMatrix_Arbiter_ITCM (
input HCLK,
input HRESETn,
input REQ_ICODE,
input REQ_DCODE,
input HREADY_Outputstage_ITCM,
input HSEL_Outputstage_ITCM,
input [1:0] HTRANS_Outputstage_ITCM,
input ... | 7.446207 |
module AHBlite_BusMatrix_Arbiter_OLED (
input HCLK,
input HRESETn,
input REQ_SUB,
input HREADY_Outputstage_OLED,
input HSEL_Outputstage_OLED,
input [1:0] HTRANS_Outputstage_OLED,
input [2:0] HBURST_Outputstage_OLED,
... | 7.446207 |
module AHBlite_BusMatrix_Arbiter_ROM (
input HCLK,
input HRESETn,
input REQ_ICODE,
input REQ_DCODE,
input HREADY_Outputstage_ROM,
input HSEL_Outputstage_ROM,
input [1:0] HTRANS_Outputstage_ROM,
input [2:0... | 7.446207 |
module AHBlite_BusMatrix_Arbiter_SUB (
input HCLK,
input HRESETn,
input REQ_SYS,
input HREADY_Outputstage_SUB,
input HSEL_Outputstage_SUB,
input [1:0] HTRANS_Outputstage_SUB,
input [2:0] HBURST_Outputstage_SUB,
outpu... | 7.446207 |
module AHBlite_BusMatrix_Arbiter_TIMER (
input HCLK,
input HRESETn,
input REQ_SUB,
input HREADY_Outputstage_TIMER,
input HSEL_Outputstage_TIMER,
input [1:0] HTRANS_Outputstage_TIMER,
input [2:0] HBURST_Outputstage_TIMER,... | 7.446207 |
module AHBlite_BusMatrix_Arbiter_UART (
input HCLK,
input HRESETn,
input REQ_SUB,
input HREADY_Outputstage_UART,
input HSEL_Outputstage_UART,
input [1:0] HTRANS_Outputstage_UART,
input [2:0] HBURST_Outputstage_UART,
... | 7.446207 |
module AHBlite_BusMatrix_Decoder_ACC (
input HCLK,
input HRESETn,
// FROM INPUTSTAGE
input HREADY,
input [31:0] HADDR,
input [1:0] HTRANS,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_DTCM,
input HREADYOUT_Outputstage_DTCM,
input [1:0] HRESP_DTCM,
input [31:0] HRDATA_DTC... | 7.446207 |
module AHBlite_BusMatrix_Decoder_DCODE (
input HCLK,
input HRESETn,
// FROM INPUTSTAGE
input HREADY,
input [31:0] HADDR,
input [1:0] HTRANS,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_ITCM,
input HREADYOUT_Outputstage_ITCM,
input [1:0] HRESP_ITCM,
input [31:0] HRDATA_I... | 7.446207 |
module AHBlite_BusMatrix_Decoder_DMA (
input HCLK,
input HRESETn,
// FROM INPUTSTAGE
input HREADY,
input [31:0] HADDR,
input [1:0] HTRANS,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_DTCM,
input HREADYOUT_Outputstage_DTCM,
input [1:0] HRESP_DTCM,
input [31:0] HRDATA_DTC... | 7.446207 |
module AHBlite_BusMatrix_Decoder_ICODE (
input HCLK,
input HRESETn,
// FROM INPUTSTAGE
input HREADY,
input [31:0] HADDR,
input [1:0] HTRANS,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_ITCM,
input HREADYOUT_Outputstage_ITCM,
input [1:0] HRESP_ITCM,
input [31:0] HRDATA_I... | 7.446207 |
module AHBlite_BusMatrix_Decoder_SUB (
input HCLK,
input HRESETn,
// FROM INPUTSTAGE
input HREADY,
input [31:0] HADDR,
input [1:0] HTRANS,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_DMAC,
input HREADYOUT_Outputstage_DMAC,
input [1:0] HRESP_DMAC,
input [31:0] HRDATA_DMA... | 7.446207 |
module AHBlite_BusMatrix_Decoder_SYS (
input HCLK,
input HRESETn,
// FROM INPUTSTAGE
input HREADY,
input [31:0] HADDR,
input [1:0] HTRANS,
// FROM OUTPUTSTAGE
input ACTIVE_Outputstage_DTCM,
input HREADYOUT_Outputstage_DTCM,
input [1:0] HRESP_DTCM,
input [31:0] HRDATA_DTC... | 7.446207 |
module AHBlite_BusMatrix_Inputstage (
input HCLK,
input HRESETn,
input [31:0] HADDR,
input [ 1:0] HTRANS,
input HWRITE,
input [ 2:0] HSIZE,
input [ 2:0] HBURST,
input [ 3:0] HPROT,
input HREADY,
input ACTIVE_Decoder,
input HREADYOUT_D... | 7.446207 |
module AHBlite_BusMatrix_Outputstage_ACCC (
input HCLK,
input HRESETn,
input HSEL_SYS,
input [31:0] HADDR_SYS,
input [ 1:0] HTRANS_SYS,
input HWRITE_SYS,
input [ 2:0] HSIZE_SYS,
input [ 2:0] HBURST_SYS,
input [ 3:0] HPROT_SYS,
input [31:0] HWDATA_SYS,
input ... | 7.446207 |
module AHBlite_BusMatrix_Outputstage_DMAC (
input HCLK,
input HRESETn,
input HSEL_SUB,
input [31:0] HADDR_SUB,
input [ 1:0] HTRANS_SUB,
input HWRITE_SUB,
input [ 2:0] HSIZE_SUB,
input [ 2:0] HBURST_SUB,
input [ 3:0] HPROT_SUB,
input [31:0] HWDATA_SUB,
input ... | 7.446207 |
module AHBlite_BusMatrix_Outputstage_GPIO (
input HCLK,
input HRESETn,
input HSEL_SUB,
input [31:0] HADDR_SUB,
input [ 1:0] HTRANS_SUB,
input HWRITE_SUB,
input [ 2:0] HSIZE_SUB,
input [ 2:0] HBURST_SUB,
input [ 3:0] HPROT_SUB,
input [31:0] HWDATA_SUB,
input ... | 7.446207 |
module AHBlite_BusMatrix_Outputstage_ITCM (
input HCLK,
input HRESETn,
input HSEL_ICODE,
input [31:0] HADDR_ICODE,
input [ 1:0] HTRANS_ICODE,
input HWRITE_ICODE,
input [ 2:0] HSIZE_ICODE,
input [ 2:0] HBURST_ICODE,
input [ 3:0] HPROT_ICODE,
input [31:0] HWDATA_ICOD... | 7.446207 |
module AHBlite_BusMatrix_Outputstage_OLED (
input HCLK,
input HRESETn,
input HSEL_SUB,
input [31:0] HADDR_SUB,
input [ 1:0] HTRANS_SUB,
input HWRITE_SUB,
input [ 2:0] HSIZE_SUB,
input [ 2:0] HBURST_SUB,
input [ 3:0] HPROT_SUB,
input [31:0] HWDATA_SUB,
input ... | 7.446207 |
module AHBlite_BusMatrix_Outputstage_ROM (
input HCLK,
input HRESETn,
input HSEL_ICODE,
input [31:0] HADDR_ICODE,
input [ 1:0] HTRANS_ICODE,
input HWRITE_ICODE,
input [ 2:0] HSIZE_ICODE,
input [ 2:0] HBURST_ICODE,
input [ 3:0] HPROT_ICODE,
input [31:0] HWDATA_ICODE... | 7.446207 |
module AHBlite_BusMatrix_Outputstage_SUB (
input HCLK,
input HRESETn,
input HSEL_SYS,
input [31:0] HADDR_SYS,
input [ 1:0] HTRANS_SYS,
input HWRITE_SYS,
input [ 2:0] HSIZE_SYS,
input [ 2:0] HBURST_SYS,
input [ 3:0] HPROT_SYS,
input [31:0] HWDATA_SYS,
input ... | 7.446207 |
module AHBlite_BusMatrix_Outputstage_TIMER (
input HCLK,
input HRESETn,
input HSEL_SUB,
input [31:0] HADDR_SUB,
input [ 1:0] HTRANS_SUB,
input HWRITE_SUB,
input [ 2:0] HSIZE_SUB,
input [ 2:0] HBURST_SUB,
input [ 3:0] HPROT_SUB,
input [31:0] HWDATA_SUB,
input ... | 7.446207 |
module AHBlite_BusMatrix_Outputstage_UART (
input HCLK,
input HRESETn,
input HSEL_SUB,
input [31:0] HADDR_SUB,
input [ 1:0] HTRANS_SUB,
input HWRITE_SUB,
input [ 2:0] HSIZE_SUB,
input [ 2:0] HBURST_SUB,
input [ 3:0] HPROT_SUB,
input [31:0] HWDATA_SUB,
input ... | 7.446207 |
module AHBlite_db_reg (
// AHB Interface
// clock and reset
input wire HCLK,
//input wire HCLKG, // Gated clock
input wire HRESETn, // Reset
// input ports
input wire HSEL, // Select
input wire [23:2] HADDR, // Address
input wire HREADY, //
input ... | 7.903209 |
module AHBlite_Decoder #(
parameter Port0_en = 1,
parameter Port1_en = 1,
parameter Port2_en = 1,
parameter Port3_en = 1,
parameter Port4_en = 1
) (
input [31:0] HADDR,
output wire P0_HSEL,
output wire P1_HSEL,
output wire P2_HSEL,
output wire P3_HSEL,
output wire P4_HSEL
);
... | 7.379811 |
module AHBlite_Keyboard (
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire [ 2:0] HSIZE,
input wire [ 3:0] HPROT,
input wire HWRITE,
input wire [31:0] HWDATA,
input wire ... | 6.90908 |
module AHBlite_SPI (
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [2:0] HSIZE,
input wire [3:0] HPROT,
input wire HWRITE,
input wire [31:0] HWDATA,
input wire HREADY,
output wire HREADYOUT,
output [31:0... | 6.606167 |
module ahblite_sys_tb ();
reg RESET, CLK;
wire [7:0] LED;
AHBLITE_SYS dut (
.CLK (CLK),
.RESET(RESET),
.LED (LED)
);
// Note: you can modify this to give a 50MHz clock or whatever is appropriate
initial begin
CLK = 0;
forever begin
#5 CLK = 1;
#5 CLK = 0;
end
... | 6.556387 |
module AHBlite_WaveformGenerator (
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire [ 2:0] HSIZE,
input wire [ 3:0] HPROT,
input wire HWRITE,
input wire [31:0] HWDATA,
input w... | 6.604643 |
module AHBL_BUS_8 #(parameter BAD_DATA=32'DEADBEEF,
SLAVE_ENABLE=8'hff,
S0_PAGE=8'h00,
S1_PAGE=8'h00,
S2_PAGE=8'h00,
S3_PAGE=8'h00,
... | 6.870344 |
module ahbl_master_assertions #(
parameter W_ADDR = 32,
parameter W_DATA = 32
) (
input wire clk,
input wire rst_n,
input wire src_hready,
input wire src_hresp,
input wire src_hexokay,
input wire [W_ADDR-1:0] src_haddr,
input wire ... | 8.849642 |
module ahbl_slave_assumptions #(
parameter W_ADDR = 32,
parameter W_DATA = 32,
parameter MAX_BUS_STALL = -1 // set >= 0 to constrain max stall length
) (
input wire clk,
input wire rst_n,
input wire dst_hready_resp,
input wire dst_hready,
input wire ... | 8.391163 |
module ahbl_to_apb #(
parameter W_HADDR = 32,
parameter W_PADDR = 16,
parameter W_DATA = 32
) (
input wire clk,
input wire rst_n,
input wire [W_HADDR-1:0] ahbls_haddr,
input wire ahbls_hwrite,
input wire [ 1:0] ahbls_htrans,
input wire [ 2:0] ahbls_h... | 8.660763 |
module AHBMAS_WBSLV_TOP (
hclk,
hresetn,
// AHB Master Interface (Connect to AHB Slave)
haddr,
htrans,
hwrite,
hsize,
hburst,
hwdata,
hrdata,
hready,
hresp,
// WISHBONE Slave Interface (Connect to WB Master)
data_o,
data_i,
addr_i,
clk_i,
rst_i,... | 8.825463 |
module AHBQSPIFI (
// AHB-Lite Bus Interface
//Inputs
input wire HSEL,
input wire HCLK,
input wire HRESETn,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [31:0] HWDATA,
input wire HWRITE,
input wire HREADY,
//Output
output reg HREADYOUT,
output /*reg*/... | 8.366921 |
module ahbslave (
HCLK,
HRESETn,
HADDR,
HADDR_1,
HADDR_2,
HWDATA,
HWDATA_1,
HWDATA_2,
HWRITE,
HWRITEreg,
HRESP,
HRDATA,
PRDATA,
TEMP_SEL,
valid,
HTRANS,
HREADYin
);
//slave memory map
parameter slave0_0 = 32'h8000_0000, slave0_1 = 32'h8400_0000;
... | 6.511504 |
module AHBSYSMUX (
input wire HCLK,
input wire HRESETn,
input wire [2:0] MUX_SEL,
input wire [31:0] HRDATA_S0, // SRAM
input wire [31:0] HRDATA_S1, // LED
input wire [31:0] HRDATA_S2, // UART
input wire [31:0] HRDATA_S3, // GPIO
input wire [31:0] HRDATA_S4, //
... | 6.692968 |
module AHBUART (
//AHB Signals
input wire HCLK,
input wire HRESETn,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire [31:0] HWDATA,
input wire HWRITE,
input wire HREADY,
output wire HREADYOUT,
output wire [31:0] HRDATA,
input ... | 6.812607 |
module AHBVGA (
input wire HCLK,
input wire HRESETn,
input wire [31:0] HADDR,
input wire [31:0] HWDATA,
input wire HREADY,
input wire HWRITE,
input wire [1:0] HTRANS,
input wire HSEL,
output wire [31:0] HRDATA,
output wire HREADYOUT,
output wire HSYNC,
output wire VSYNC... | 7.747442 |
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