code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
modules to perform AES Key expansion
// Author : Saurav Sachin Kale (EE19B141), Ruban Vishnu Pandian (EE19B138)
// Date : 10th December, 2021
module AESKeyexpansion_128(
input clk,
input reset,
input start,
input [127:0] short_key,
output [127:0] subkey,
output [3:0] cnt128,
output valid_skey
);
reg [3:0] i;
reg [127:0] prev_period_key_1; //This register keeps track of the previous round key
//since it's used in current key generation
reg status;
wire [31:0] key1, key2, key3, key4;
assign cnt128 = i;
//The current_word_gen_128 module is instantiated 4 times to process 4 words in a clock cycle
//since each round key is comprised of 4 words. In this way, one round key is processed per cycle
current_word_gen_128 word1(.i({i,2'd0}),.prev_word(prev_period_key_1[31:0]),.prev_period_word(prev_period_key_1[127:96]),.current_word(key1));
current_word_gen_128 word2(.i({i,2'd1}),.prev_word(key1),.prev_period_word(prev_period_key_1[95:64]),.current_word(key2));
current_word_gen_128 word3(.i({i,2'd2}),.prev_word(key2),.prev_period_word(prev_period_key_1[63:32]),.current_word(key3));
current_word_gen_128 word4(.i({i,2'd3}),.prev_word(key3),.prev_period_word(prev_period_key_1[31:0]),.current_word(key4));
//The full round key is formed by concatenating 4 individual key words in the right sequence
assign subkey = {key1, key2, key3, key4};
assign valid_skey = status;
//Note: Register 'i' denotes the first 4 bits of the control variable. Since it's a multiple of 4,
//the first 4 bits are enough to determine the control variable completely
always @(posedge clk)
begin
if(reset) begin
i <= 0;
prev_period_key_1 <= 0;
status <= 0; //Reset signal resets the module to its default state
end
else begin
if (start) begin
// $display("1. Short key: %h, %d",short_key, i);
i <= 1; //4
prev_period_key_1 <= short_key;
status <= 1;
//If the module is started, the input key is sampled and stored in "prev_period_key_1".
//Also, the status bit is set to 1.
end
else if((i>=1) && (i<10)) begin //40
//$display("2. Short key: %h, %d",subkey, i);
prev_period_key_1 <= {key1,key2,key3,key4};
i <= i+1; //+4
//In intermediate rounds, "prev_period_key_1" is assigned to current round key so that
//it holds it for the next round
end
else if(i==10) begin //40
//$display("3. Short key: %h, %d", subkey, i);
i <= 0;
status <= 0;
prev_period_key_1 <= 0;
//In the final round, all the registers are made zero since key expansion is done
end
end
end
endmodule
| 7.773518 |
modules to perform AES Key expansion
// Author : Saurav Sachin Kale (EE19B141), Ruban Vishnu Pandian (EE19B138)
// Date : 10th December, 2021
module AESKeyexpansion_192(
input clk,
input reset,
input start,
input [191:0] short_key,
output [127:0] subkey,
output [3:0] cnt192,
output valid_skey
);
reg [4:0] i; //last bit always 0 so can be removed!
reg [191:0] prev_period_key_1; //This register keeps track of the previous 6 words
//since it's used in current key generation
reg status;
wire [31:0] key1, key2, key3, key4;
assign cnt192 = i[4:1];
//The current_word_gen_192 module is instantiated 4 times to process 4 words in a clock cycle
//since each round key is comprised of 4 words. In this way, one round key is processed per cycle
current_word_gen_192 word1(.i({i,1'd0}),.prev_word(prev_period_key_1[31:0]),.prev_period_word(prev_period_key_1[191:160]),.current_word(key1));
current_word_gen_192 word2(.i({i,1'd1}),.prev_word(key1),.prev_period_word(prev_period_key_1[159:128]),.current_word(key2));
current_word_gen_192 word3(.i({i[4:1],2'd2}),.prev_word(key2),.prev_period_word(prev_period_key_1[127:96]),.current_word(key3));
current_word_gen_192 word4(.i({i[4:1],2'd3}),.prev_word(key3),.prev_period_word(prev_period_key_1[95:64]),.current_word(key4));
//The full round key is obtained by concatenating 4 keywords. Only in the second round, we
//instead concatenate prev_period_key_1[63:0], key1, key2 since in that round, the first 2
//keywords are obtained from the input 192-bit key itself
assign subkey = (i==3)? ({prev_period_key_1[63:0], key1, key2}): ({key1, key2, key3, key4}); //6
assign valid_skey = status;
//Note: Register 'i' denotes the first 5 bits of the control variable. Since it's a multiple of 2,
//the first 5 bits are enough to determine the control variable completely
always @(posedge clk)
begin
if(reset) begin
i <= 0;
prev_period_key_1 <= 0;
status <= 0; //Reset signal resets the module to its default state
end
else begin
if (start) begin
i <= 3; //6
prev_period_key_1 <= short_key;
status <= 1;
//If the module is started, the input key is sampled and stored in "prev_period_key_1".
//Also, the status bit is set to 1.
end
else if (i==3) begin //6
i <= 4; //8
prev_period_key_1 = {prev_period_key_1[127:0],key1,key2};
status <= 1;
//Only in the second round,"prev_period_key_1" is updated this way
end
else if((i>=4) && (i<24)) begin //48
i <= i+2; //+4
prev_period_key_1 = {prev_period_key_1[63:0],key1,key2,key3,key4};
status <= 1;
//In intermediate rounds, "prev_period_key_1" is assigned to
//{last two words of prev_period_key_1 + current round key} so that it
//holds it for the next round
end
else if(i==24) begin //48
i <= 0;
status <= 0;
prev_period_key_1 <= 0;
//In the final round, all the registers are made zero since key expansion is done
end
end
end
endmodule
| 7.773518 |
modules to perform AES Key expansion
// Author : Saurav Sachin Kale (EE19B141), Ruban Vishnu Pandian (EE19B138)
// Date : 10th December, 2021
module AESKeyexpansion_256(
input clk,
input reset,
input start,
input [255:0] short_key,
output [127:0] subkey,
output [3:0] cnt256,
output valid_skey
);
reg [3:0] i; //last 2 bit always 0 so can be removed!
reg [127:0] prev_period_key_1, prev_period_key_2;
//These registers keep track of the previous two round keys since they are used in
//current key generation
reg status;
wire [31:0] key1, key2, key3, key4;
assign cnt256 = i;
//The current_word_gen_256 module is instantiated 4 times to process 4 words in a clock cycle
//since each round key is comprised of 4 words. In this way, one round key is processed per cycle
current_word_gen_256 word1(.i({i,2'd0}),.prev_word(prev_period_key_2[31:0]),.prev_period_word(prev_period_key_1[127:96]),.current_word(key1));
current_word_gen_256 word2(.i({i,2'd1}),.prev_word(key1),.prev_period_word(prev_period_key_1[95:64]),.current_word(key2));
current_word_gen_256 word3(.i({i,2'd2}),.prev_word(key2),.prev_period_word(prev_period_key_1[63:32]),.current_word(key3));
current_word_gen_256 word4(.i({i,2'd3}),.prev_word(key3),.prev_period_word(prev_period_key_1[31:0]),.current_word(key4));
//The full round key is formed by concatenating 4 individual key words in the right sequence.
//Only in th second cycle, its directly obtained from the input 256-bit key
assign subkey = (i==1) ? prev_period_key_2 : {key1, key2, key3, key4};
assign valid_skey = status;
//Note: Register 'i' denotes the first 4 bits of the control variable. Since it's a multiple of 4,
//the first 4 bits are enough to determine the control variable completely
always @(posedge clk)
begin
if(reset) begin
i <= 0;
prev_period_key_1 <= 0;
prev_period_key_2 <= 0;
status <= 0; //Reset signal resets the module to its default state
end
else begin
if (start) begin
i <= 1; //4
prev_period_key_1 <= short_key[255:128];
prev_period_key_2 <= short_key[127:0];
status <= 1;
//If the module is started, the input key is sampled and stored in "prev_period_key_1"
//and "prev_period_key_2". Also, the status bit is set to 1.
end
else if(i==1) begin
i <= 2; //8
prev_period_key_1 <= prev_period_key_1;
prev_period_key_2 <= prev_period_key_2;
status <= 1;
//In the second round, round key is simply obtained from the input 256-bit key
end
else if ((i>=2) && (i<14)) begin //56
prev_period_key_1 <= prev_period_key_2;
prev_period_key_2 <= {key1,key2,key3,key4};
i <= i+1; //+4
//In intermediate rounds, "prev_period_key_1" and "prev_period_key_2"
//are updated with the "prev_period_key_2" and current key respectively since
//they are used in the next key generation round
end
else if(i==14) begin //56
i <= 0;
status <= 0;
prev_period_key_1 <= 0;
prev_period_key_2 <= 0;
//In the final round, all the registers are made zero since key expansion is done
end
end
end
endmodule
| 7.773518 |
module ACMP_add_comb (
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 1;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_Add #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_Add_U (
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 6.867962 |
module ACMP_add (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_Add #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_Add_U (
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 7.192736 |
module ACMP_sub_comb (
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 1;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_Sub #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_Sub_U (
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 6.918561 |
module ACMP_sub (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_Sub #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_Sub_U (
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 7.383367 |
module ACMP_mul_ss (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_Mul_ss #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_Mul_U (
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 6.97175 |
module ACMP_mul_us (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_Mul_us #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_Mul_U (
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 7.363069 |
module ACMP_mul_su (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_Mul_su #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_Mul_U (
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 7.245196 |
module ACMP_mul_uu (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_Mul_uu #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_Mul_U (
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 7.425536 |
module ACMP_smul_ss (
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_Mul_ss #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_Mul_U (
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 6.542019 |
module ACMP_smul_us (
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_Mul_us #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_Mul_U (
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 6.647923 |
module ACMP_smul_su (
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_Mul_su #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_Mul_U (
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 6.910677 |
module ACMP_smul_uu (
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_Mul_uu #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_Mul_U (
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 6.836543 |
module ACMP_sdiv_comb (
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 1;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_sdiv #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_sdiv_U (
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 7.383339 |
module ACMP_sdiv (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_sdiv #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_sdiv_U (
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 7.883955 |
module ACMP_udiv_comb (
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 1;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_udiv #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_udiv_U (
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 7.760075 |
module ACMP_udiv (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_udiv #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_udiv_U (
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 8.26032 |
module ACMP_srem_comb (
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 1;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_srem #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_srem_U (
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 6.675611 |
module ACMP_srem (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_srem #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_srem_U (
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 7.570909 |
module ACMP_urem_comb (
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 1;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_urem #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_urem_U (
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 6.842342 |
module ACMP_urem (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_urem #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_urem_U (
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 7.676275 |
module ACMP_sdivsrem_comb (
opcode,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 1;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [1:0] opcode;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_sdivsrem #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_sdivsrem_U (
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode[0]),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 6.86201 |
module ACMP_sdivsrem (
clk,
reset,
ce,
opcode,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [1:0] opcode;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_sdivsrem #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH) ACMP_sdivsrem_U (
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode[0]),
.din0(din0),
.din1(din1),
.dout(dout)
);
endmodule
| 6.86201 |
module AESL_udiv
#(
parameter
NUM_STAGE = 2,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)
(
input clk,
input reset,
input ce,
input [din0_WIDTH-1:0] din0,
input [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
generate
if (NUM_STAGE==1)
begin : comb
assign dout = din0 / din1;
end
else
begin : buff
integer i;
reg [dout_WIDTH-1:0] dout_buff[NUM_STAGE-2:0];
assign dout = dout_buff[NUM_STAGE-2];
always @(posedge clk)
begin
if (ce)
begin
for (i=0;i<NUM_STAGE-1;i=i+1)
begin
if (i==0)
dout_buff[i] <= din0 / din1;
else
dout_buff[i] <= dout_buff[i-1];
end
end
end
end
endgenerate
endmodule
| 6.636771 |
module AESMixColumn (
input clk,
input en,
input [31:0] din,
output [31:0] dout
);
AESMixColumn1 mix1 (
.clk (clk),
.en (en),
.din (din),
.dout(dout[31:24])
);
AESMixColumn2 mix2 (
.clk (clk),
.en (en),
.din (din),
.dout(dout[23:16])
);
AESMixColumn3 mix3 (
.clk (clk),
.en (en),
.din (din),
.dout(dout[15:8])
);
AESMixColumn4 mix4 (
.clk (clk),
.en (en),
.din (din),
.dout(dout[7:0])
);
endmodule
| 6.569976 |
module AESMixColumn1 (
input clk,
input en,
input [31:0] din,
output [7:0] dout
);
wire [8:0] tmp_in1, tmp_in2;
wire [7:0] tmp_out1, tmp_out2;
reg [7:0] b1, b2, b3, b4;
always @(posedge clk) begin
if (en) begin
b4 <= din[7:0];
b3 <= din[15:8];
b2 <= din[23:16];
b1 <= din[31:24];
end
end
assign tmp_in1 = {b1, 1'b0};
assign tmp_in2 = {b2, 1'b0};
AESMod mod1 (
.din (tmp_in1),
.dout(tmp_out1)
);
AESMod mod2 (
.din (tmp_in2),
.dout(tmp_out2)
);
assign dout = tmp_out1 ^ tmp_out2 ^ b2 ^ b3 ^ b4;
endmodule
| 6.988245 |
module AESMixColumn2 (
input clk,
input en,
input [31:0] din,
output [7:0] dout
);
reg [7:0] b1, b2, b3, b4;
always @(posedge clk) begin
if (en) begin
b4 <= din[7:0];
b3 <= din[15:8];
b2 <= din[23:16];
b1 <= din[31:24];
end
end
wire [8:0] tmp_in1, tmp_in2;
wire [7:0] tmp_out1, tmp_out2;
assign tmp_in1 = {b2, 1'b0};
assign tmp_in2 = {b3, 1'b0};
AESMod mod1 (
.din (tmp_in1),
.dout(tmp_out1)
);
AESMod mod2 (
.din (tmp_in2),
.dout(tmp_out2)
);
assign dout = tmp_out1 ^ tmp_out2 ^ b3 ^ b1 ^ b4;
endmodule
| 6.641911 |
module AESMixColumn3 (
input clk,
input en,
input [31:0] din,
output [7:0] dout
);
reg [7:0] b1, b2, b3, b4;
always @(posedge clk) begin
if (en) begin
b4 <= din[7:0];
b3 <= din[15:8];
b2 <= din[23:16];
b1 <= din[31:24];
end
end
wire [8:0] tmp_in1, tmp_in2;
wire [7:0] tmp_out1, tmp_out2;
assign tmp_in1 = {b3, 1'b0};
assign tmp_in2 = {b4, 1'b0};
AESMod mod1 (
.din (tmp_in1),
.dout(tmp_out1)
);
AESMod mod2 (
.din (tmp_in2),
.dout(tmp_out2)
);
assign dout = tmp_out1 ^ tmp_out2 ^ b4 ^ b1 ^ b2;
endmodule
| 6.582093 |
module AESMixColumn4 (
input clk,
input en,
input [31:0] din,
output [7:0] dout
);
reg [7:0] b1, b2, b3, b4;
always @(posedge clk) begin
if (en) begin
b4 <= din[7:0];
b3 <= din[15:8];
b2 <= din[23:16];
b1 <= din[31:24];
end
end
wire [8:0] tmp_in1, tmp_in2;
wire [7:0] tmp_out1, tmp_out2;
assign tmp_in1 = {b4, 1'b0};
assign tmp_in2 = {b1, 1'b0};
AESMod mod1 (
.din (tmp_in1),
.dout(tmp_out1)
);
AESMod mod2 (
.din (tmp_in2),
.dout(tmp_out2)
);
assign dout = tmp_out1 ^ tmp_out2 ^ b1 ^ b2 ^ b3;
endmodule
| 6.786952 |
module AESModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input Clock,
input Reset
);
// [BEGIN USER SIGNALS]
// [END USER SIGNALS]
localparam HiSignal = 1'b1;
localparam LoSignal = 1'b0;
wire Zero = 1'b0;
wire One = 1'b1;
wire true = 1'b1;
wire false = 1'b0;
wire AESModule_L36F29T30_Expr = 1'b0;
wire AESModule_L37F29T30_Expr = 1'b0;
reg [128:1] NextState_Value = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
wire [8:1] SBoxAddress;
wire [8:1] RBoxAddress;
wire [128:1] sbox_Value;
wire [128:1] sbox_Result;
wire [8:1] box_SBoxAddress;
wire [8:1] box_RBoxAddress;
reg [8:1] box_RConAddress = 8'b00000000;
wire [8:1] box_SBox;
wire [8:1] box_RBox;
wire [8:1] box_RCon;
wire [128:1] sboxValuesbox_ValueHardLink;
wire [128:1] sboxResultsbox_ResultHardLink;
wire [8:1] boxSBoxAddressbox_SBoxAddressHardLink;
wire [8:1] boxRBoxAddressbox_RBoxAddressHardLink;
wire [8:1] boxRConAddressbox_RConAddressHardLink;
wire [8:1] boxSBoxbox_SBoxHardLink;
wire [8:1] boxRBoxbox_RBoxHardLink;
wire [8:1] boxRConbox_RConHardLink;
reg [128:1] State_Value = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
wire [128:1] State_ValueDefault = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
wire BoardSignals_Clock;
wire BoardSignals_Reset;
wire BoardSignals_Running;
wire BoardSignals_Starting;
wire BoardSignals_Started;
reg InternalReset = 1'b0;
work_Quokka_BoardSignalsProc BoardSignalsConnection (
BoardSignals_Clock,
BoardSignals_Reset,
BoardSignals_Running,
BoardSignals_Starting,
BoardSignals_Started,
Clock,
Reset,
InternalReset
);
always @(posedge Clock) begin
if (Reset == 1) begin
State_Value <= State_ValueDefault;
end else begin
State_Value <= NextState_Value;
end
end
AESModule_TopLevel_AESModule_sbox AESModule_TopLevel_AESModule_sbox (
// [BEGIN USER MAP FOR sbox]
// [END USER MAP FOR sbox]
.Value (sboxValuesbox_ValueHardLink),
.Result(sboxResultsbox_ResultHardLink)
);
AESModule_TopLevel_AESModule_box AESModule_TopLevel_AESModule_box (
// [BEGIN USER MAP FOR box]
// [END USER MAP FOR box]
.SBoxAddress(boxSBoxAddressbox_SBoxAddressHardLink),
.RBoxAddress(boxRBoxAddressbox_RBoxAddressHardLink),
.RConAddress(boxRConAddressbox_RConAddressHardLink),
.SBox(boxSBoxbox_SBoxHardLink),
.RBox(boxRBoxbox_RBoxHardLink),
.RCon(boxRConbox_RConHardLink)
);
always @* begin
NextState_Value = State_Value;
end
assign SBoxAddress = {{7{1'b0}}, AESModule_L36F29T30_Expr} /*expand*/;
assign RBoxAddress = {{7{1'b0}}, AESModule_L37F29T30_Expr} /*expand*/;
assign box_SBoxAddress = SBoxAddress;
assign box_RBoxAddress = RBoxAddress;
assign sbox_Value = State_Value;
assign sboxValuesbox_ValueHardLink = sbox_Value;
assign sbox_Result = sboxResultsbox_ResultHardLink;
assign boxSBoxAddressbox_SBoxAddressHardLink = box_SBoxAddress;
assign boxRBoxAddressbox_RBoxAddressHardLink = box_RBoxAddress;
assign boxRConAddressbox_RConAddressHardLink = box_RConAddress;
assign box_SBox = boxSBoxbox_SBoxHardLink;
assign box_RBox = boxRBoxbox_RBoxHardLink;
assign box_RCon = boxRConbox_RConHardLink;
// [BEGIN USER ARCHITECTURE]
// [END USER ARCHITECTURE]
endmodule
| 7.134377 |
module AESModule_TopLevel_AESModule_box (
// [BEGIN USER PORTS]
// [END USER PORTS]
input [8:1] SBoxAddress,
input [8:1] RBoxAddress,
input [8:1] RConAddress,
output [8:1] SBox,
output [8:1] RBox,
output [8:1] RCon
);
// [BEGIN USER SIGNALS]
// [END USER SIGNALS]
localparam HiSignal = 1'b1;
localparam LoSignal = 1'b0;
wire Zero = 1'b0;
wire One = 1'b1;
wire true = 1'b1;
wire false = 1'b0;
wire [8:1] Inputs_SBoxAddress;
wire [8:1] Inputs_RBoxAddress;
wire [8:1] Inputs_RConAddress;
wire [8:1] BoxModule_L62F29T57_Index;
wire [8:1] BoxModule_L63F29T57_Index;
wire [8:1] BoxModule_L64F29T57_Index;
reg [8:1] sboxData[0 : 255];
initial begin
$readmemh("AESModule_TopLevel_AESModule_box_sboxData.hex", sboxData);
end
reg [8:1] rboxData[0 : 255];
initial begin
$readmemh("AESModule_TopLevel_AESModule_box_rboxData.hex", rboxData);
end
reg [8:1] rconData[0 : 10];
initial begin
$readmemh("AESModule_TopLevel_AESModule_box_rconData.hex", rconData);
end
assign Inputs_SBoxAddress = SBoxAddress;
assign Inputs_RBoxAddress = RBoxAddress;
assign Inputs_RConAddress = RConAddress;
assign SBox = BoxModule_L62F29T57_Index;
assign RBox = BoxModule_L63F29T57_Index;
assign RCon = BoxModule_L64F29T57_Index;
assign BoxModule_L62F29T57_Index = sboxData[Inputs_SBoxAddress];
assign BoxModule_L63F29T57_Index = rboxData[Inputs_RBoxAddress];
assign BoxModule_L64F29T57_Index = rconData[Inputs_RConAddress];
// [BEGIN USER ARCHITECTURE]
// [END USER ARCHITECTURE]
endmodule
| 7.134377 |
module AESOneRound (
in,
out,
roundkey,
dec,
nomix //nomix = 1 when no mixcolumn
);
input [127:0] in, roundkey;
input dec;
output reg [127:0] out;
input nomix;
reg [127:0] key_in, sub_in, inv_sub_in, inv_sh_in, mix_in, sh_in;
wire [127:0] key_out, sub_out, inv_sub_out, inv_sh_out, mix_out, sh_out;
AddRoundKey a0 (
.in (key_in),
.out(key_out),
.key(roundkey)
);
SubByte s0 (
.in (sub_in),
.out(sub_out)
);
InvSubByte s1 (
.in (inv_sub_in),
.out(inv_sub_out)
);
ShiftRow s2 (
.in (sh_in),
.out(sh_out)
);
InvShiftRow s3 (
.in (inv_sh_in),
.out(inv_sh_out)
);
MixColumn m0 (
.in(mix_in),
.out_test(mix_out),
.dec(dec)
);
always @(*) begin
if (nomix) inv_sh_in = key_out;
else inv_sh_in = mix_out;
inv_sub_in = inv_sh_out;
sub_in = in;
sh_in = sub_out;
if (dec) begin //add -> mix -> invsh -> invsub
key_in = in;
mix_in = key_out;
//inv_sh_in = mix_out;
//inv_sub_in = inv_sh_out;
out = inv_sub_out;
end else begin //sub -> sh -> mix -> add
//sub_in = in;
//sh_in = sub_out;
mix_in = sh_out;
if (nomix) key_in = sh_out;
else key_in = mix_out;
out = key_out;
end
end
endmodule
| 6.632369 |
module AESOneRound ( //two addroundkey
in,
out,
roundkey,
dec,
nomix //nomix = 1 when no mixcolumn
);
input [127:0] in, roundkey;
input dec;
output reg [127:0] out;
input nomix;
reg [127:0] key_in, sub_in, inv_sub_in, inv_sh_in, mix_in, sh_in;
wire [127:0] key_out, sub_out, inv_sub_out, inv_sh_out, mix_out, sh_out;
reg [127:0] key_inv_in;
wire [127:0] key_inv_out;
AddRoundKey a0 (
.in (key_in),
.out(key_out),
.key(roundkey)
);
AddRoundKey ainv (
.in (key_inv_in),
.out(key_inv_out),
.key(roundkey)
);
SubByte s0 (
.in (sub_in),
.out(sub_out)
);
InvSubByte s1 (
.in (inv_sub_in),
.out(inv_sub_out)
);
ShiftRow s2 (
.in (sh_in),
.out(sh_out)
);
InvShiftRow s3 (
.in (inv_sh_in),
.out(inv_sh_out)
);
MixColumn m0 (
.in(mix_in),
.out_test(mix_out),
.dec(dec)
);
always @(*) begin
if (nomix) inv_sh_in = key_inv_out;
else inv_sh_in = mix_out;
inv_sub_in = inv_sh_out;
sub_in = in;
sh_in = sub_out;
key_inv_in = in;
if (nomix) key_in = sh_out;
else key_in = mix_out;
if (dec) begin //add -> mix -> invsh -> invsub
//key_in = in;
mix_in = key_inv_out;
//inv_sh_in = mix_out;
//inv_sub_in = inv_sh_out;
out = inv_sub_out;
end else begin //sub -> sh -> mix -> add
//sub_in = in;
//sh_in = sub_out;
mix_in = sh_out;
// if(nomix)
// key_in = sh_out;
// else
// key_in = mix_out;
out = key_out;
end
end
endmodule
| 6.632369 |
module AESTOP(plain,key,cipher,clk,rst,start,finish,dec);
module AESTOP( clk,
rst_n,
mode, //mode = 1 --> decode?
i_start,
i_key,
i_in,
o_cipher,
o_ready);
input clk,rst_n;
input i_start,mode;
input [127:0] i_key,i_in;
output [127:0] o_cipher;
output o_ready;
//state parameter
localparam S_IDLE = 0;
localparam S_ROUNDKEY = 1;
localparam S_COMPUTE = 2;
localparam S_FIN = 3;
// control
reg [3:0] counter_w,counter_r;
reg [1:0] state_w,state_r;
// data reg and wire
reg [127:0] temp_out_w,temp_out_r;
//module reg and wire
wire key_start;
wire key_finish;
wire [1279:0] roundkeys;
wire [127:0] oneround_in,oneround_out;
reg [127:0] oneround_key;
wire [127:0] xor_in,xor_out;
reg nomix;
//call module
KeySchedule key0(
.key(i_key),
.roundkeys(roundkeys),
.clk(clk),
.rst_n(rst_n),
.start(key_start),
.finish(key_finish)
);
AESOneRound oneround(
.in(oneround_in),
.out(oneround_out),
.roundkey(oneround_key),
.dec(mode),
.nomix(nomix)
);
AddRoundKey xor0( //to xor before start of enc / after end of dec
.in(xor_in),
.key(i_key),
.out(xor_out)
);
//wire assignment
assign xor_in = (mode)? oneround_out:i_in;
assign oneround_in = temp_out_r;
assign key_start = (state_r == S_ROUNDKEY);
//assign oneround_key = roundkeys[1279 -: 128];
//output assignment
assign o_cipher = temp_out_r;
assign o_ready = (state_r == S_FIN);
//comb
//next state logic
always @(*) begin
state_w = state_r;
counter_w = counter_r;
case (state_r)
S_IDLE:begin
if(i_start)
state_w = S_ROUNDKEY;
end
S_ROUNDKEY:begin
if(key_finish)begin
state_w = S_COMPUTE;
end
end
S_COMPUTE:begin
counter_w = counter_r + 1;
if(counter_r == 9)begin
state_w = S_FIN;
counter_w = 0;
end
end
S_FIN:begin
state_w = S_IDLE;
end
endcase
end
always @(*) begin
temp_out_w = temp_out_r;
nomix = 0;
oneround_key = roundkeys[127:0];
case (state_r)
S_IDLE:begin
if(mode)
temp_out_w = i_in;
else
temp_out_w = xor_out;
end
// S_ROUNDKEY:begin
// if(key_finish && mode)begin
// key_shr = 1;//let roundkeys[1279 -: 128] be 10th round
// end
// end
S_COMPUTE:begin
temp_out_w = oneround_out;
if ((counter_r == 9) && (mode))
temp_out_w = xor_out;
if (counter_r == 9 && (!(mode)))
nomix = 1;
if (counter_r == 0 && mode)
nomix = 1;
//round 1 key : roundkeys[1279 -: 128]
//round 2 key : roundkeys[1279-128 -: 128]
//round 3 key : roundkeys[1279-128*2 -: 128]
//round n key : roundkeys[1279-128*(counter_r) -: 128]
if (mode)
oneround_key = roundkeys[1279-128*(9-counter_r) -: 128];
else
oneround_key = roundkeys[1279-128*(counter_r) -: 128];
end
endcase
end
//seq
always @(posedge clk or negedge rst_n) begin
if(!rst_n)begin
counter_r <= 0;
state_r <= S_IDLE;
end
else begin
counter_r <= counter_w;
state_r <= state_w;
temp_out_r <= temp_out_w;
end
end
endmodule
| 7.69443 |
module aes_128 (
clk,
clr,
dat_in,
dat_out,
key,
inv_key
);
input clk, clr;
input [127:0] dat_in;
input [127:0] key;
output [127:0] dat_out;
output [127:0] inv_key;
parameter LATENCY = 10; // currently allowed 0,10
localparam ROUND_LATENCY = (LATENCY == 10 ? 1 : 0);
wire [127:0] start1, start2, start3, start4, start5;
wire [127:0] start6, start7, start8, start9, start10;
wire [127:0] key1, key2, key3, key4, key5;
wire [127:0] key6, key7, key8, key9, key10;
assign start1 = dat_in ^ key;
assign key1 = key;
aes_round_128 r1 (
.clk(clk),
.clr(clr),
.dat_in(start1),
.key_in(key1),
.dat_out(start2),
.key_out(key2),
.skip_mix_col(1'b0),
.rconst(8'h01)
);
defparam r1.LATENCY = ROUND_LATENCY;
aes_round_128 r2 (
.clk(clk),
.clr(clr),
.dat_in(start2),
.key_in(key2),
.dat_out(start3),
.key_out(key3),
.skip_mix_col(1'b0),
.rconst(8'h02)
);
defparam r2.LATENCY = ROUND_LATENCY;
aes_round_128 r3 (
.clk(clk),
.clr(clr),
.dat_in(start3),
.key_in(key3),
.dat_out(start4),
.key_out(key4),
.skip_mix_col(1'b0),
.rconst(8'h04)
);
defparam r3.LATENCY = ROUND_LATENCY;
aes_round_128 r4 (
.clk(clk),
.clr(clr),
.dat_in(start4),
.key_in(key4),
.dat_out(start5),
.key_out(key5),
.skip_mix_col(1'b0),
.rconst(8'h08)
);
defparam r4.LATENCY = ROUND_LATENCY;
aes_round_128 r5 (
.clk(clk),
.clr(clr),
.dat_in(start5),
.key_in(key5),
.dat_out(start6),
.key_out(key6),
.skip_mix_col(1'b0),
.rconst(8'h10)
);
defparam r5.LATENCY = ROUND_LATENCY;
aes_round_128 r6 (
.clk(clk),
.clr(clr),
.dat_in(start6),
.key_in(key6),
.dat_out(start7),
.key_out(key7),
.skip_mix_col(1'b0),
.rconst(8'h20)
);
defparam r6.LATENCY = ROUND_LATENCY;
aes_round_128 r7 (
.clk(clk),
.clr(clr),
.dat_in(start7),
.key_in(key7),
.dat_out(start8),
.key_out(key8),
.skip_mix_col(1'b0),
.rconst(8'h40)
);
defparam r7.LATENCY = ROUND_LATENCY;
aes_round_128 r8 (
.clk(clk),
.clr(clr),
.dat_in(start8),
.key_in(key8),
.dat_out(start9),
.key_out(key9),
.skip_mix_col(1'b0),
.rconst(8'h80)
);
defparam r8.LATENCY = ROUND_LATENCY;
aes_round_128 r9 (
.clk(clk),
.clr(clr),
.dat_in(start9),
.key_in(key9),
.dat_out(start10),
.key_out(key10),
.skip_mix_col(1'b0),
.rconst(8'h1b)
);
defparam r9.LATENCY = ROUND_LATENCY;
aes_round_128 r10 (
.clk(clk),
.clr(clr),
.dat_in(start10),
.key_in(key10),
.dat_out(dat_out),
.key_out(inv_key),
.skip_mix_col(1'b1),
.rconst(8'h36)
);
defparam r10.LATENCY = ROUND_LATENCY;
endmodule
| 6.624619 |
module aes_128 (
clk,
state,
key,
out
);
input clk;
input [127:0] state, key;
output [127:0] out;
(* keep *) reg [127:0] out_reg;
assign out = ~out_reg;
// this is the way to avoid yosys from optimizing away
// all logic related to out, even there is a neg sign
// the range of out is still arbitrary.
endmodule
| 6.624619 |
module aes_128_tb ();
reg [127:0] plain;
reg [127:0] key;
wire [127:0] sub1;
wire [127:0] shftr1;
wire [127:0] mix1;
wire [127:0] key1, key2;
wire [127:0] start2, start3;
wire [127:0] full_out, pipe_out;
reg clk, clr;
initial begin
clk = 0;
clr = 0;
#10 clr = 1;
#10 clr = 0;
plain = 128'h3243f6a8885a308d313198a2e0370734;
key = 128'h2b7e151628aed2a6abf7158809cf4f3c;
end
// initial round building blocks
sub_bytes sb1 (
.in (plain ^ key),
.out(sub1)
);
shift_rows sr1 (
.in (sub1),
.out(shftr1)
);
mix_columns mx1 (
.in (shftr1),
.out(mix1)
);
evolve_key_128 ek1 (
.key_in (key),
.rconst (8'h1),
.key_out(key1)
);
assign start2 = key1 ^ mix1;
// 2nd round in composite layer
aes_round_128 r2 (
.clk(1'b0),
.clr(1'b0),
.dat_in(start2),
.dat_out(start3),
.rconst(8'h2),
.skip_mix_col(1'b0),
.key_in(key1),
.key_out(key2)
);
wire [127:0] inv_key, pipe_inv_key, recovered, pipe_recovered;
// full 128 bit cipher, no pipeline
aes_128 rf (
.clk(1'b0),
.clr(1'b0),
.dat_in(plain),
.key(key),
.dat_out(full_out),
.inv_key(inv_key)
);
defparam rf.LATENCY = 0;
// full 128 bit decipher, no pipeline
inv_aes_128 irf (
.clk(1'b0),
.clr(1'b0),
.dat_in(full_out),
.inv_key(inv_key),
.dat_out(recovered)
);
defparam irf.LATENCY = 0;
// full 128 bit cipher, ten pipeline
aes_128 rp (
.clk(clk),
.clr(clr),
.dat_in(plain),
.key(key),
.dat_out(pipe_out),
.inv_key(pipe_inv_key)
);
defparam rp.LATENCY = 10;
// full 128 bit decipher, ten pipeline
inv_aes_128 irp (
.clk(clk),
.clr(clr),
.dat_in(pipe_out),
.inv_key(pipe_inv_key),
.dat_out(pipe_recovered)
);
defparam irp.LATENCY = 10;
reg [127:0] expected[0:9];
integer n;
initial begin
$display("Testing Building blocks...");
#100
if (start2 != 128'ha49c7ff2689f352b6b5bea43026a5049) begin
$display("Initial round building blocks aren't working");
$stop();
end
#100
if (start3 != 128'haa8f5f0361dde3ef82d24ad26832469a) begin
$display("Second round composite isn't working");
$stop();
end
#100
if (full_out != 128'h3925841d02dc09fbdc118597196a0b32) begin
$display("Full encipher 128 no pipeline not working");
$stop();
end
#100
if (recovered != plain) begin
$display("Full decipher 128 no pipeline not working");
$stop();
end
#100 $display("Blocks OK. Testing pipelined operation");
// test the pipelined version
// fill the pipe, save expected encrypt result
for (n = 0; n < 10; n = n + 1) begin
#100 expected[n] = full_out;
$display("save expected %x", full_out);
#100 clk = ~clk;
#100 clk = ~clk;
key = key + 1;
plain = plain + 1;
end
// drain the pipe and check encrypts against expected
for (n = 0; n < 10; n = n + 1) begin
#100 $display("read back %x", pipe_out);
if (expected[n] != pipe_out) begin
$display("Pipeline output is incorrect time %d", $time);
$stop();
end
#100 clk = ~clk;
#100 clk = ~clk;
end
plain = plain - 10;
// drain the pipe and check decrypts against expected
for (n = 0; n < 10; n = n + 1) begin
#100 $display("read back %x", pipe_recovered);
if (plain != pipe_recovered) begin
$display("Pipeline output is incorrect time %d", $time);
$stop();
end
#100 clk = ~clk;
plain = plain + 1;
#100 clk = ~clk;
end
$display("PASS");
$stop();
end
endmodule
| 7.110925 |
module aes_192_sed (
clk,
start,
state,
p_c_text,
key,
out,
out_valid
);
input clk;
input start;
input [127:0] state, p_c_text;
input [191:0] key;
output [127:0] out;
output out_valid;
wire [127:0] out_temp;
wire out_valid;
// Instantiate the Unit Under Test (UUT)
aes_192 uut (
.clk(clk),
.start(start),
.state(state),
.key(key),
.out(out_temp),
.out_valid(out_valid)
);
// Muxing p_c_text with output of AES core.
assign out = p_c_text ^ out_temp;
endmodule
| 7.075835 |
module AES_DEC (
input [127:0] Din,
input [127:0] Key,
output [127:0] Dout,
input Datardy,
input Keyrdy,
input RST,
input EN,
input CLK,
output BSY,
output Dvld
);
reg [127:0] Dreg;
reg [127:0] Kreg;
reg [127:0] KregX;
reg [ 9:0] Rreg;
reg Dvldreg, BSYreg;
wire [127:0] Dnext, Knext;
DecCore DC (
Dreg,
KregX,
Rreg,
Dnext,
Knext
);
assign Dvld = Dvldreg;
assign Dout = Dreg;
assign BSY = BSYreg;
always @(posedge CLK) begin
if (RST == 0) begin
Rreg <= 10'b1000000000;
Dvldreg <= 0;
BSYreg <= 0;
end else if (EN == 1) begin
if (BSYreg == 0) begin
if (Keyrdy == 1) begin
Kreg <= Key;
KregX <= Key;
Dvldreg <= 0;
end else if (Datardy == 1) begin
Rreg <= {Rreg[0], Rreg[9:1]};
KregX <= Knext;
Dreg <= Din ^ Kreg;
Dvldreg <= 0;
BSYreg <= 1;
end
end else begin
Dreg <= Dnext;
if (Rreg[9] == 1) begin
KregX <= Kreg;
Dvldreg <= 1;
BSYreg <= 0;
end else begin
Rreg <= {Rreg[0], Rreg[9:1]};
KregX <= Knext;
end
end
end
end
endmodule
| 6.571574 |
module AES_CH (
input [127:0] Din,
input [127:0] Key,
output [127:0] Dout,
input Datardy,
input Keyrdy,
input RST,
input EN,
input MODE,
input CLK,
output BSY,
output Dvld
);
wire [127:0] Dout_E;
wire [127:0] Dout_D;
reg [127:0] Dreg;
reg EN_E;
reg EN_D;
AES_ENC AES_ENC (
Din,
Key,
Dout_E,
Datardy,
Keyrdy,
RST,
EN_E,
CLK,
BSY,
Dvld
);
AES_DEC AES_DEC (
Din,
Key,
Dout_D,
Datardy,
Keyrdy,
RST,
EN_D,
CLK,
BSY,
Dvld
);
assign Dout = Dreg;
//MODE 0 = ENC,1 = DEC
always @(*) begin
EN_E <= (EN & (!MODE));
EN_D <= (EN & (MODE));
if (MODE == 0) begin
Dreg = Dout_E;
end else if (MODE == 1) begin
Dreg = Dout_D;
end
end
endmodule
| 6.834951 |
module AES_DEC (
input [127:0] Din,
input [127:0] Key,
output [127:0] Dout,
input Datardy,
input Keyrdy,
input RST,
input EN,
input CLK,
output BSY,
output Dvld
);
reg [127:0] Dreg;
reg [127:0] Kreg;
reg [127:0] KregX;
reg [ 9:0] Rreg;
reg Dvldreg, BSYreg;
wire [127:0] Dnext, Knext;
DecCore DC (
Dreg,
KregX,
Rreg,
Dnext,
Knext
);
assign Dvld = Dvldreg;
assign Dout = Dreg;
assign BSY = BSYreg;
always @(posedge CLK) begin
if (RST == 0) begin
Rreg <= 10'b1000000000;
Dvldreg <= 0;
BSYreg <= 0;
end else if (EN == 1) begin
if (BSYreg == 0) begin
if (Keyrdy == 1) begin
Kreg <= Key;
KregX <= Key;
Dvldreg <= 0;
end else if (Datardy == 1) begin
Rreg <= {Rreg[0], Rreg[9:1]};
KregX <= Knext;
Dreg <= Din ^ Kreg;
Dvldreg <= 0;
BSYreg <= 1;
end
end else begin
Dreg <= Dnext;
if (Rreg[9] == 1) begin
KregX <= Kreg;
Dvldreg <= 1;
BSYreg <= 0;
end else begin
Rreg <= {Rreg[0], Rreg[9:1]};
KregX <= Knext;
end
end
end
end
endmodule
| 6.571574 |
module AES_CO (
input [127:0] Din_E,
input [127:0] Din_D,
input [127:0] Key_E,
input [127:0] Key_D,
output [127:0] Dout_E,
output [127:0] Dout_D,
input Datardy_E,
input Datardy_D,
input Keyrdy_E,
input Keyrdy_D,
input RST,
input EN_E,
input EN_D,
input CLK,
output BSY_E,
output BSY_D,
output Dvld_E,
output Dvld_D
);
AES_ENC AES_ENC (
Din_E,
Key_E,
Dout_E,
Datardy_E,
Keyrdy_E,
RST,
EN_E,
CLK,
BSY_E,
Dvld_E
);
AES_DEC AES_DEC (
Din_D,
Key_D,
Dout_D,
Datardy_D,
Keyrdy_D,
RST,
EN_D,
CLK,
BSY_D,
Dvld_D
);
endmodule
| 7.000918 |
module AES_controller (
clk,
rst,
start,
round_num,
wr,
round_key_addr
);
input wire clk, rst, start;
output reg [3:0] round_num;
output wire [3:0] round_key_addr;
output reg wr;
reg [3:0] round_key_addr_temp;
reg flag;
always @(posedge clk or negedge rst) begin
if (!rst) begin
round_num <= 0;
round_key_addr_temp <= 0;
wr <= 0;
flag <= 0;
end else begin
if (round_num == 10 && round_key_addr_temp == 15);
else if (round_key_addr_temp == 15) begin
flag <= 0;
wr <= 0;
round_num <= round_num + 4'b1;
round_key_addr_temp <= 0;
end else if (start || flag) begin
flag <= 1;
round_key_addr_temp <= round_key_addr_temp + 4'b1;
wr <= 1;
end
end
end
assign round_key_addr = round_key_addr_temp;
endmodule
| 6.931178 |
module aes_control_unit (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input i_en,
input i_flag,
output reg o_busy,
output reg o_dp_en,
output reg o_ready,
output reg o_valid
);
/**********************************************************************
* FSM State Declaration
**********************************************************************/
localparam RESET = 0;
localparam WAIT = 1;
localparam BUSY = 2;
localparam DONE = 3;
/**********************************************************************
* FSM State register Declaration
**********************************************************************/
reg [1:0] current_state;
reg [1:0] next_state;
/**********************************************************************
* FSM State register Declaration
**********************************************************************/
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
current_state <= RESET;
end else begin
current_state <= next_state;
end
end
/**********************************************************************
* State Decoder logic
**********************************************************************/
always @(current_state, i_flag, i_en) begin
case (current_state)
RESET: next_state = WAIT;
WAIT: next_state = (i_en) ? BUSY : WAIT;
BUSY: next_state = (i_flag) ? DONE : BUSY;
DONE: next_state = RESET;
default: next_state = RESET;
endcase
end
/**********************************************************************
* output decoder logic
**********************************************************************/
always @(*) begin
case (current_state)
RESET: begin
o_ready = 1'b0;
o_busy = 1'b0;
o_dp_en = 1'b0;
o_valid = 1'b0;
end
WAIT: begin
o_ready = 1'b1;
o_busy = 1'b0;
o_dp_en = 1'b0;
o_valid = 1'b0;
end
BUSY: begin
o_ready = 1'b0;
o_busy = 1'b1;
o_dp_en = 1'b1;
o_valid = 1'b0;
end
DONE: begin
o_ready = 1'b0;
o_busy = 1'b0;
o_dp_en = 1'b0;
o_valid = 1'b1;
end
default: begin
o_ready = 1'b0;
o_busy = 1'b0;
o_dp_en = 1'b0;
o_valid = 1'b0;
end
endcase
end
endmodule
| 7.340506 |
module aes_core_TOP (
input ICLK,
input IRSTN,
input IENCDEC,
input IINIT,
input INEXT,
output OREADY,
input [255:0] IKEY,
input IKEYLEN,
input [127:0] IBLOCK,
output [127:0] ORESULT,
output ORESULT_VALID
);
aes_core U1 (
.iClk (ICLK),
.iRstn (IRSTN),
.iEncdec (IENCDEC),
.iInit (IINIT),
.iNext (INEXT),
.oReady (OREADY),
.iKey (IKEY),
.iKeylen (IKEYLEN),
.iBlock (IBLOCK),
.oResult (ORESULT),
.oResult_valid (ORESULT_VALID)
);
endmodule
| 7.94061 |
module aes_core_TOP_wrapper (
input clk,
input reset_n,
input encdec,
input init,
input next,
output ready,
input [255:0] key,
input keylen,
input [127:0] block,
output [127:0] result,
output result_valid
);
aes_core_TOP U1_TOP (
.ICLK (clk),
.IRSTN (reset_n),
.IENCDEC (encdec),
.IINIT (init),
.INEXT (next),
.OREADY (ready),
.IKEY (key),
.IKEYLEN (keylen),
.IBLOCK (block),
.ORESULT (result),
.ORESULT_VALID (result_valid)
);
endmodule
| 7.927853 |
module aes_ctrl (
input wire clk,
input wire rst,
input wire aes_start,
output reg aes_ready,
output reg aes_valid,
output reg [3:0] rnd_idx,
output reg plaintext_en,
output reg key_en,
output reg ciphertext_en,
output reg rndkey_en,
output reg sb_mux_ctrl,
output reg keygen_mux_ctrl,
output reg skip_mux_ctrl
);
//RND index count
//mux control
//enable control
localparam IDLE = 2'd0, COUNT = 2'd1;
reg [1:0] state, nstate;
always @* begin
case (state)
IDLE: nstate = (aes_start) ? COUNT : IDLE;
COUNT: nstate = (aes_valid) ? IDLE : COUNT;
endcase
end
always @(posedge clk or posedge rst) begin
if (rst) state <= IDLE;
else begin
state <= nstate;
case (nstate)
IDLE: rnd_idx <= 4'b0;
COUNT: rnd_idx <= rnd_idx + 4'b1;
endcase
end
end
always @(posedge clk or posedge rst) begin
if (rst) begin
plaintext_en <= 0;
key_en <= 0;
ciphertext_en <= 0;
rndkey_en <= 0;
sb_mux_ctrl <= 0;
keygen_mux_ctrl <= 0;
skip_mux_ctrl <= 0;
aes_valid <= 0;
aes_ready <= 1;
end else begin
case (rnd_idx)
4'd0: begin
plaintext_en <= 1;
key_en <= 1;
ciphertext_en <= 1;
rndkey_en <= 1;
sb_mux_ctrl <= 1;
keygen_mux_ctrl <= 0;
skip_mux_ctrl <= 1;
aes_ready <= 0;
aes_valid <= 0;
end
4'd9: begin
plaintext_en <= 0;
key_en <= 0;
ciphertext_en <= 1;
rndkey_en <= 1;
sb_mux_ctrl <= 0;
keygen_mux_ctrl <= 1;
skip_mux_ctrl <= 0;
end
4'd10: begin
plaintext_en <= 0;
key_en <= 0;
ciphertext_en <= 0;
rndkey_en <= 0;
aes_valid <= 1;
aes_ready <= 1;
end
4'd11: begin
aes_valid <= 0;
end
default: begin
plaintext_en <= 0;
key_en <= 0;
ciphertext_en <= 1;
rndkey_en <= 1;
sb_mux_ctrl <= 0;
keygen_mux_ctrl <= 1;
skip_mux_ctrl <= 1;
end
endcase
end
end
endmodule
| 7.085512 |
module aes_data_path #(
parameter RND_SIZE = 128,
WRD_SIZE = 32,
NUM_BLK = 4,
MAX_CNT = 11,
CNT_SIZE = 4,
NUM_RND = 10
) (
// inputs
input clk,
input rst_n,
input i_dp_en,
input [RND_SIZE-1:0] i_rnd_text,
input [RND_SIZE-1:0] i_rnd_key,
// outputs
output [RND_SIZE-1:0] o_cypher_text,
output o_flag
);
`include "round_function.vh"
/**********************************************************************
* Internal Signals as wire and registers
**********************************************************************/
wire [CNT_SIZE-1:0] o_count;
wire [RND_SIZE-1:0] w_pre_rnd_key;
wire [RND_SIZE-1:0] w_next_rnd_key;
wire [RND_SIZE-1:0] w_rnd_txt;
wire [RND_SIZE-1:0] o_rnd_cypher;
/**********************************************************************
* Mux logic
**********************************************************************/
assign w_pre_rnd_key = (o_count == 0) ? i_rnd_key : w_next_rnd_key;
assign w_rnd_txt = (o_count == 0) ? i_rnd_text : o_rnd_cypher;
/**********************************************************************
* Round counter module instantiation
**********************************************************************/
aes_round_counter #(
.MAX_CNT (MAX_CNT),
.CNT_SIZE(CNT_SIZE)
) inst_aes_round_counter (
.clk (clk), // input clk ,
.rst_n (rst_n), // input rst_n ,
.i_cnt_en(i_dp_en), // input i_cnt_en,
.o_flag (o_flag), // output o_flag ,
.o_count (o_count) // output reg [CNT_SIZE-1:0] o_count
);
/**********************************************************************
* key expension Module
**********************************************************************/
aes_key_gen i_aes_key_gen (
.clk (clk),
.rst_n (rst_n),
.pre_rnd_key (w_pre_rnd_key), // input [127:0] pre_rnd_key ,
.i_en_key_gen(i_dp_en), // input i_en_key_gen,
.round_num (o_count), // input [ 3:0] round_num ,
.next_rnd_key(w_next_rnd_key) // output [127:0] next_rnd_key
);
/**********************************************************************
* Round Module Instantiation
**********************************************************************/
aes_round #(
.RND_SIZE(RND_SIZE),
.WRD_SIZE(WRD_SIZE),
.NUM_BLK (NUM_BLK)
) inst_aes_round (
// inputs
.clk (clk), // input clk ,
.rst_n (rst_n), // input rst_n ,
.i_rnd_en (i_dp_en),
.i_rnd_text (w_rnd_txt), // input [RND_SIZE-1:0] i_rnd_text,
.i_rnd_key (w_pre_rnd_key), // input [RND_SIZE-1:0] i_rnd_key ,
.i_rnd_cnt (o_count), // input [CNT_SIZE-1:0] i_rnd_cnt;
// outputs
.o_rnd_cypher(o_rnd_cypher) // output [RND_SIZE-1:0] o_rnd_key
);
assign o_cypher_text = (o_count == 'hb) ? o_rnd_cypher : 'h0;
endmodule
| 7.142304 |
module InvShiftrows (
input [ 31:0] rowin1,
input [ 31:0] rowin2,
input [ 31:0] rowin3,
input [ 31:0] rowin4,
output [127:0] out
);
wire [31:0] rowout1, rowout2, rowout3, rowout4;
assign rowout1 = rowin1;
assign rowout2 = {rowin2[7:0], rowin2[31:8]};
assign rowout3 = {rowin3[15:0], rowin3[31:16]};
assign rowout4 = {rowin4[23:0], rowin4[31:24]};
assign out = {
rowout1[31:24],
rowout2[31:24],
rowout3[31:24],
rowout4[31:24],
rowout1[23:16],
rowout2[23:16],
rowout3[23:16],
rowout4[23:16],
rowout1[15:8],
rowout2[15:8],
rowout3[15:8],
rowout4[15:8],
rowout1[7:0],
rowout2[7:0],
rowout3[7:0],
rowout4[7:0]
};
endmodule
| 7.119217 |
module aes_decrypt (
input wire [127:0] ciphertext,
input wire [127:0] key,
output wire [127:0] plaintext
);
wire [127:0] states [ 0:9]; // 10 states
wire [127:0] subkeys[0:10]; // 11 keys
KeyExpansion U1 (
key,
{
subkeys[0], // well
subkeys[1], // this
subkeys[2], // blows
subkeys[3], // but
subkeys[4], // it
subkeys[5], // is
subkeys[6], // better
subkeys[7], // than
subkeys[8], // flattening
subkeys[9], // the
subkeys[10]
}
); // array
RevInitialRound U2 (
ciphertext,
subkeys[10],
states[0]
);
genvar i;
generate
for (i = 0; i < 9; i = i + 1) begin : URound
RevRound U (
states[i],
subkeys[9-i],
states[i+1]
);
end
endgenerate
RevFinalRound U12 (
states[9],
subkeys[0],
plaintext
);
endmodule
| 6.785639 |
module mixcolums (
input clk,
input rstn,
input [7:0] data0,
input [7:0] data1,
input [7:0] data2,
input [7:0] data3,
output reg [7:0] data0_o,
output reg [7:0] data1_o,
output reg [7:0] data2_o,
output reg [7:0] data3_o
);
reg [7:0] Tmp_p0, Tmp_p1, Tmp;
reg [7:0] Tm_p0_0, Tm_p1_0;
reg [7:0] Tm_p0_1, Tm_p1_1;
reg [7:0] Tm_p0_2, Tm_p1_2;
reg [7:0] Tm_p0_3, Tm_p1_3;
reg [7:0] data0_d1, data0_d2, data0_d3, data0_d4;
reg [7:0] data1_d1, data1_d2, data1_d3, data1_d4;
reg [7:0] data2_d1, data2_d2, data2_d3, data2_d4;
reg [7:0] data3_d1, data3_d2, data3_d3, data3_d4;
always @(`CLK_RST_EDGE)
if (`ZST)
{data0_d1,data0_d2,data0_d3,data0_d4,
data1_d1,data1_d2,data1_d3,data1_d4,
data2_d1,data2_d2,data2_d3,data2_d4,
data3_d1,data3_d2,data3_d3,data3_d4} <= 0;
else begin
{data0_d1, data0_d2, data0_d3, data0_d4} <= {data0, data0_d1, data0_d2, data0_d3};
{data1_d1, data1_d2, data1_d3, data1_d4} <= {data1, data1_d1, data1_d2, data1_d3};
{data2_d1, data2_d2, data2_d3, data2_d4} <= {data2, data2_d1, data2_d2, data2_d3};
{data3_d1, data3_d2, data3_d3, data3_d4} <= {data3, data3_d1, data3_d2, data3_d3};
end
always @(`CLK_RST_EDGE)
if (`ZST) Tmp_p0 <= 0;
else Tmp_p0 <= data0 ^ data1;
always @(`CLK_RST_EDGE)
if (`ZST) Tmp_p1 <= 0;
else Tmp_p1 <= data2 ^ data3;
always @(`CLK_RST_EDGE)
if (`ZST) Tmp <= 0;
else Tmp <= Tmp_p0 ^ Tmp_p1;
//data0 part
always @(`CLK_RST_EDGE)
if (`ZST) Tm_p0_0 <= 0;
else Tm_p0_0 <= data0 ^ data1;
always @(`CLK_RST_EDGE)
if (`ZST) Tm_p1_0 <= 0;
else Tm_p1_0 <= Tm_p0_0[7] ? {Tm_p0_0[6:0], 1'b0} ^ 8'h1b : {Tm_p0_0[6:0], 1'b0};
always @(`CLK_RST_EDGE)
if (`ZST) data0_o <= 0;
else data0_o <= data0_d2 ^ (Tm_p1_0 ^ Tmp);
//data1 part
always @(`CLK_RST_EDGE)
if (`ZST) Tm_p0_1 <= 0;
else Tm_p0_1 <= data1 ^ data2;
always @(`CLK_RST_EDGE)
if (`ZST) Tm_p1_1 <= 0;
else Tm_p1_1 <= Tm_p0_1[7] ? {Tm_p0_1[6:0], 1'b0} ^ 8'h1b : {Tm_p0_1[6:0], 1'b0};
always @(`CLK_RST_EDGE)
if (`ZST) data1_o <= 0;
else data1_o <= data1_d2 ^ (Tm_p1_1 ^ Tmp);
//data2 part
always @(`CLK_RST_EDGE)
if (`ZST) Tm_p0_2 <= 0;
else Tm_p0_2 <= data2 ^ data3;
always @(`CLK_RST_EDGE)
if (`ZST) Tm_p1_2 <= 0;
else Tm_p1_2 <= Tm_p0_2[7] ? {Tm_p0_2[6:0], 1'b0} ^ 8'h1b : {Tm_p0_2[6:0], 1'b0};
always @(`CLK_RST_EDGE)
if (`ZST) data2_o <= 0;
else data2_o <= data2_d2 ^ (Tm_p1_2 ^ Tmp);
//data3 part
always @(`CLK_RST_EDGE)
if (`ZST) Tm_p0_3 <= 0;
else Tm_p0_3 <= data3 ^ data0;
always @(`CLK_RST_EDGE)
if (`ZST) Tm_p1_3 <= 0;
else Tm_p1_3 <= Tm_p0_3[7] ? {Tm_p0_3[6:0], 1'b0} ^ 8'h1b : {Tm_p0_3[6:0], 1'b0};
always @(`CLK_RST_EDGE)
if (`ZST) data3_o <= 0;
else data3_o <= data3_d2 ^ (Tm_p1_3 ^ Tmp);
endmodule
| 6.526114 |
module ShiftRows (
res,
inp
);
input [127:0] inp;
output [127:0] res;
assign res = {
inp[127:120],
inp[87:80],
inp[47:40],
inp[7:0],
inp[95:88],
inp[55:48],
inp[15:8],
inp[103:96],
inp[63:56],
inp[23:16],
inp[111:104],
inp[71:64],
inp[31:24],
inp[119:112],
inp[79:72],
inp[39:32]
};
endmodule
| 7.114324 |
module AES_Encryptor (
input [127:0] PT,
input Clk,
input Rst,
input En,
output Ry,
input [127:0] Key,
output [3:0] SelKey,
output [127:0] CT
);
wire Rst_ARK_SM;
wire Rst_SBT_SM;
wire Rst_SHR_SM;
wire Rst_MXC_SM;
wire Rst_ARK_Md;
wire Rst_SBT_Md;
wire Rst_SHR_Md;
wire Rst_MXC_Md;
wire En_ARK_SM;
wire En_SBT_SM;
wire En_SHR_SM;
wire En_MXC_SM;
wire Ry_ARK_SM;
wire Ry_SBT_SM;
wire Ry_SHR_SM;
wire Ry_MXC_SM;
wire [127:0] Tx_SM;
wire [127:0] Out_ARK_M;
wire [127:0] Out_SBT_M;
wire [127:0] Out_SHR_M;
wire [127:0] Out_MXC_M;
StateMachine E01 (
.Rst(Rst),
.Clk(Clk),
.En(En),
.PT(PT),
.CT(CT),
.En_ARK(En_ARK_SM),
.En_SBT(En_SBT_SM),
.En_SHR(En_SHR_SM),
.En_MXC(En_MXC_SM),
.Rst_ARK(Rst_ARK_SM),
.Rst_SBT(Rst_SBT_SM),
.Rst_SHR(Rst_SHR_SM),
.Rst_MXC(Rst_MXC_SM),
.Ry_ARK(Ry_ARK_SM),
.Ry_SBT(Ry_SBT_SM),
.Ry_SHR(Ry_SHR_SM),
.Ry_MXC(Ry_MXC_SM),
.Text(Tx_SM),
.Text_ARK(Out_ARK_M),
.Text_SBT(Out_SBT_M),
.Text_SHR(Out_SHR_M),
.Text_MXC(Out_MXC_M),
.KeySel(SelKey),
.Ry(Ry)
);
AddRoundKey E02 (
.Rst(Rst_ARK_Md),
.Clk(Clk),
.En_ARK(En_ARK_SM),
.Ry_ARK(Ry_ARK_SM),
.In_ARK(Tx_SM),
.Out_ARK(Out_ARK_M),
.Key_ARK(Key)
);
SubBytes E03 (
.Rst(Rst_SBT_Md),
.Clk(Clk),
.En_SBT(En_SBT_SM),
.Ry_SBT(Ry_SBT_SM),
.In_SBT(Tx_SM),
.Out_SBT(Out_SBT_M)
);
ShiftRows E04 (
.Rst(Rst_SHR_Md),
.Clk(Clk),
.En_SHR(En_SHR_SM),
.Ry_SHR(Ry_SHR_SM),
.In_SHR(Tx_SM),
.Out_SHR(Out_SHR_M)
);
MixColumns E05 (
.Rst(Rst_MXC_Md),
.Clk(Clk),
.En_MXC(En_MXC_SM),
.Ry_MXC(Ry_MXC_SM),
.In_MXC(Tx_SM),
.Out_MXC(Out_MXC_M)
);
assign Rst_ARK_Md = Rst_ARK_SM | Rst;
assign Rst_SBT_Md = Rst_SBT_SM | Rst;
assign Rst_SHR_Md = Rst_SHR_SM | Rst;
assign Rst_MXC_Md = Rst_MXC_SM | Rst;
endmodule
| 6.571734 |
module ShiftRows (
res,
inp
);
input [127:0] inp;
output [127:0] res;
assign res[7:0] = inp[7:0];
assign res[15:8] = inp[15:8];
assign res[23:16] = inp[23:16];
assign res[31:24] = inp[31:24];
assign res[39:32] = inp[47:40];
assign res[47:40] = inp[55:48];
assign res[55:48] = inp[63:56];
assign res[63:56] = inp[39:32];
assign res[71:64] = inp[87:80];
assign res[79:72] = inp[95:88];
assign res[87:80] = inp[71:64];
assign res[95:88] = inp[79:72];
assign res[103:96] = inp[127:120];
assign res[111:104] = inp[103:96];
assign res[119:112] = inp[111:104];
assign res[127:120] = inp[119:112];
endmodule
| 7.114324 |
module AddRoundKey (
res,
inp,
subkey
);
input [127:0] inp, subkey;
output [127:0] res;
assign res = inp ^ subkey;
endmodule
| 7.103156 |
module AES_enc_dec (
data,
out
);
input [127:0] data;
wire [127:0] w1;
output [127:0] out;
AES_enc en (
data,
w1
);
AES_dec de (
w1,
out
);
endmodule
| 7.09065 |
module aes_gcm_TOP (
//6 pins
input ICLK,
input IRSTN,
input IINIT,
input IENCDEC,
input IOPMODE,
output OREADY,
//355 pins
input [0:95] IIV,
input IIV_VALID,
input [0:255] IKEY,
input IKEY_VALID,
input IKEYLEN,
//130 pins
input [0:127] IAAD,
input IAAD_VALID,
input IAAD_LAST,
//130 pins
input [0:127] IBLOCK,
input IBLOCK_VALID,
input IBLOCK_LAST,
//129 pins
input [0:127] ITAG,
input ITAG_VALID,
//259 pins
output [0:127] ORESULT,
output ORESULT_VALID,
output [0:127] OTAG,
output OTAG_VALID,
output OAUTHENTIC
);
aes_gcm U1 (
.iClk(ICLK),
.iRstn(IRSTN),
.iInit(IINIT),
.iEncdec(IENCDEC),
.iOpMode(IOPMODE),
.oReady(OREADY),
.iIV(IIV),
.iIV_valid(IIV_VALID),
.iKey(IKEY),
.iKey_valid(IKEY_VALID),
.iKeylen(IKEYLEN),
.iAad(IAAD), //Len
.iAad_valid(IAAD_VALID),
.iAad_last(IAAD_LAST),
.iBlock(IBLOCK),
.iBlock_valid(IBLOCK_VALID),
.iBlock_last(IBLOCK_LAST),
.iTag(ITAG),
.iTag_valid(ITAG_VALID),
.oResult(ORESULT),
.oResult_valid(ORESULT_VALID),
.oTag(OTAG),
.oTag_valid(OTAG_VALID),
.oAuthentic(OAUTHENTIC)
);
endmodule
| 7.237726 |
module aes_gcm_v2_TOP (
//7 pins
input ICLK,
input IRSTN,
input [0:3] ICTRL,
output OREADY,
//355 pins
input [0:95] IIV,
input IIV_VALID,
input [0:255] IKEY,
input IKEY_VALID,
input IKEYLEN,
//129 pins
input [0:127] IAAD,
input IAAD_VALID,
//129 pins
input [0:127] IBLOCK,
input IBLOCK_VALID,
//129 pins
input [0:127] ITAG,
input ITAG_VALID,
//259 pins
output [0:127] ORESULT,
output ORESULT_VALID,
output [0:127] OTAG,
output OTAG_VALID,
output OAUTHENTIC
);
aes_gcm_v2 U1 (
.iClk (ICLK),
.iRstn (IRSTN),
.iCtrl (ICTRL),
.oReady(OREADY),
.iIV(IIV),
.iIV_valid(IIV_VALID),
.iKey(IKEY),
.iKey_valid(IKEY_VALID),
.iKeylen(IKEYLEN),
.iAad(IAAD), //Len
.iAad_valid(IAAD_VALID),
.iBlock(IBLOCK),
.iBlock_valid(IBLOCK_VALID),
.iTag(ITAG),
.iTag_valid(ITAG_VALID),
.oResult(ORESULT),
.oResult_valid(ORESULT_VALID),
.oTag(OTAG),
.oTag_valid(OTAG_VALID),
.oAuthentic(OAUTHENTIC)
);
endmodule
| 7.442807 |
module aes_gcm_v4_TOP (
//6 pins
input ICLK,
input IRSTN,
input [0:3] ICTRL,
output OREADY,
//355 pins
input [0:95] IIV,
input IIV_VALID,
input [0:255] IKEY,
input IKEY_VALID,
input IKEYLEN,
//130 pins
input [0:127] IAAD,
input IAAD_VALID,
//130 pins
input [0:127] IBLOCK,
input IBLOCK_VALID,
//129 pins
input [0:127] ITAG,
input ITAG_VALID,
//259 pins
output [0:127] ORESULT,
output ORESULT_VALID,
output [0:127] OTAG,
output OTAG_VALID,
output OAUTHENTIC
);
aes_gcm_v4 U1 (
.iClk (ICLK),
.iRstn (IRSTN),
.iCtrl (ICTRL),
.oReady(OREADY),
.iIV(IIV),
.iIV_valid(IIV_VALID),
.iKey(IKEY),
.iKey_valid(IKEY_VALID),
.iKeylen(IKEYLEN),
.iAad(IAAD), //Len
.iAad_valid(IAAD_VALID),
.iBlock(IBLOCK),
.iBlock_valid(IBLOCK_VALID),
.iTag(ITAG),
.iTag_valid(ITAG_VALID),
.oResult(ORESULT),
.oResult_valid(ORESULT_VALID),
.oTag(OTAG),
.oTag_valid(OTAG_VALID),
.oAuthentic(OAUTHENTIC)
);
endmodule
| 7.028998 |
module aes_keygenassist(input [7:0] rcon, input [31:0] byte1, input [31:0] byte3, input [127:0] x0, output res[127:0]);
wire xbyte1[31:0];
wire xbyte3[31:0];
reg opx0[127:0];
assign opx0 = {x0};
aes_sbox sbox(.sboxw1(byte1), .new_sboxw1(xbyte1), .sboxw2(byte3), new_sboxw1(xbyte3) );
// ??? mm_shuffle_epi32(xout1, 0xFF);
assign res <= {{byte3[31:8],byte3[7:0] ^ rcon}, byte3, {byte1[31:8],byte1[7:0] ^ rcon}, byte1}
assign res2 <= x0 ^ opx0 ^ res;
endmodule
| 7.774252 |
module aes_genkey_sub (
input clk,
input [3:0] rcon,
input [127:0] xin0,
input [127:0] xin2,
output [127:0] xout0,
output [127:0] xout2
);
wire [ 31:0] sbox_result;
wire [ 31:0] sbox_result2;
wire [ 31:0] rot_result;
wire [127:0] temp;
reg [127:0] temp2;
//reg [7:0] rot_byte;
//temp[31:0], temp[63:32], temp[95:64], temp[127:96]
aes_sbox sbox (
.sboxw1(xin2[31:0]),
.new_sboxw1(sbox_result),
.sboxw2(temp[31:0]),
.new_sboxw2(sbox_result2)
);
assign rot_result = {sbox_result[7:0], sbox_result[31:16], sbox_result[15:8] ^ rcon};
assign temp = {
xin0[127:96] ^ rot_result,
xin0[127:96] ^ xin0[95:64] ^ rot_result,
xin0[127:96] ^ xin0[95:64] ^ xin0[63:32] ^ rot_result,
xin0[127:96] ^ xin0[95:64] ^ xin0[63:32] ^ xin0[31:0] ^ rot_result
};
assign xout0 = temp;
// sbox_result2 is result of
// soft_aeskeygenassist(*xout0, 0x00);
// _mm_shuffle_epi32(xout1, 0xAA);
assign xout2 = {
xin2[127:96] ^ sbox_result2,
xin2[127:96] ^ xin2[95:64] ^ sbox_result2,
xin2[127:96] ^ xin2[95:64] ^ xin2[63:32] ^ sbox_result2,
xin2[127:96] ^ xin2[95:64] ^ xin2[63:32] ^ xin2[31:0] ^ sbox_result2
};
endmodule
| 8.467735 |
module aes_genkey_sub2 (
input clk,
input [7:0] rcon,
input [127:0] xin0,
input [127:0] xin2,
output [127:0] xout0,
output [127:0] xout2
);
wire [ 31:0] sbox_result;
wire [ 31:0] sbox_result2;
reg [ 31:0] rot_result;
reg [127:0] temp;
reg [127:0] temp2;
//reg [7:0] rot_byte;
aes_sbox sbox (
.sboxw1(xin2[31:0]),
.new_sboxw1(sbox_result),
.sboxw2(temp[31:0]),
.new_sboxw2(sbox_result2)
);
always @(posedge clk) begin
$display("sbox_result 0x%H", sbox_result);
//rot_byte = {sbox_result[15:8]} ^ rcon;
//$display("rot byte 0x%H", rot_byte);
rot_result = {sbox_result[7:0], sbox_result[31:16], {sbox_result[15:8]} ^ rcon};
$display("rot res 0x%H", rot_result);
temp = {
xin0[127:96] ^ rot_result,
xin0[127:96] ^ xin0[95:64] ^ rot_result,
xin0[127:96] ^ xin0[95:64] ^ xin0[63:32] ^ rot_result,
xin0[127:96] ^ xin0[95:64] ^ xin0[63:32] ^ xin0[31:0] ^ rot_result
};
//xout0 = temp;
// sbox_result2 is result of
// soft_aeskeygenassist(*xout0, 0x00);
// _mm_shuffle_epi32(xout1, 0xAA);
temp2 = {
xin2[127:96] ^ sbox_result2,
xin2[127:96] ^ xin2[95:64] ^ sbox_result2,
xin2[127:96] ^ xin2[95:64] ^ xin2[63:32] ^ sbox_result2,
xin2[127:96] ^ xin2[95:64] ^ xin2[63:32] ^ xin2[31:0] ^ sbox_result2
};
$display("temp %H", temp);
$display("temp2 %H", temp2);
end
assign xout0 = temp;
assign xout2 = temp2;
endmodule
| 8.467735 |
module aes_genkey (
input clk,
input rstn,
input [127:0] input0,
input [127:0] input1,
output keygen_done,
output [127:0] k0,
output [127:0] k1,
output [127:0] k2,
output [127:0] k3,
output [127:0] k4,
output [127:0] k5,
output [127:0] k6,
output [127:0] k7,
output [127:0] k8,
output [127:0] k9
);
//wire [127:0] inw0;
//wire [127:0] inw2;
reg [127:0] in0;
reg [127:0] in2;
wire [127:0] temp0;
wire [127:0] temp2;
//reg [127:0] k0_r;
//reg [127:0] k1_r;
(* keep = "true" *) reg [127:0] k2_r, k3_r, k4_r, k5_r, k6_r, k7_r, k8_r, k9_r;
//(* keep = "true" *)
reg [2:0] counter;
reg [3:0] rcon;
//(* keep = "true" *)
reg keygen_done_r;
aes_genkey_sub sub0 (
.clk (clk),
.rcon (rcon),
.xin0 (in0),
.xin2 (in2),
.xout0(temp0),
.xout2(temp2)
);
initial begin
keygen_done_r <= 0;
counter <= 0;
//k0_r <= 0;
//k1_r <= 0;
k2_r <= 0;
k3_r <= 0;
k3_r <= 0;
k4_r <= 0;
k5_r <= 0;
k6_r <= 0;
k7_r <= 0;
k8_r <= 0;
k9_r <= 0;
end
always @(posedge clk) begin
if (rstn == 0) begin
keygen_done_r <= 0;
counter <= 0;
in0 <= 0;
in2 <= 0;
k2_r <= 0;
k3_r <= 0;
k3_r <= 0;
k4_r <= 0;
k5_r <= 0;
k6_r <= 0;
k7_r <= 0;
k8_r <= 0;
k9_r <= 0;
end else if (keygen_done_r == 0) begin
case (counter)
0: begin
// do nothing here
// we need to get value for input
counter <= 1;
end
1: begin
//k0_r <= input0;
//k1_r <= input1;
in0 <= input0;
in2 <= input1;
rcon <= 1;
counter <= 2;
end
2: begin
k2_r <= temp0;
k3_r <= temp2;
in0 <= temp0;
in2 <= temp2;
rcon <= 2;
counter <= 3;
end
3: begin
k4_r <= temp0;
k5_r <= temp2;
in0 <= temp0;
in2 <= temp2;
rcon <= 4;
counter <= 4;
end
4: begin
k6_r <= temp0;
k7_r <= temp2;
in0 <= temp0;
in2 <= temp2;
rcon <= 8;
counter <= 5;
end
5: begin
k8_r <= temp0;
k9_r <= temp2;
keygen_done_r <= 1;
counter <= 1;
end
endcase
end
end
/*
always @(posedge clk)
begin
if (counter == 1)
begin
//k0_r <= input0;
//k1_r <= input1;
in0 <= input0;
in2 <= input1;
rcon <= 1;
end
else if (counter == 2)
begin
k2_r <= temp0;
k3_r <= temp2;
in0 <= temp0;
in2 <= temp2;
rcon <= 2;
end
else if (counter == 3)
begin
k4_r <= temp0;
k5_r <= temp2;
in0 <= temp0;
in2 <= temp2;
rcon <= 4;
end
end
*/
assign k0 = input0; //k0_r;
assign k1 = input1; //k1_r;
assign k2 = k2_r;
assign k3 = k3_r;
assign k4 = k4_r;
assign k5 = k5_r;
assign k6 = k6_r;
assign k7 = k7_r;
assign k8 = k8_r;
assign k9 = k9_r;
assign keygen_done = keygen_done_r;
endmodule
| 6.596787 |
module aes_genkey_sub (
input clk,
input [3:0] rcon,
input [127:0] xin0,
input [127:0] xin2,
output [127:0] xout0,
output [127:0] xout2
);
wire [ 31:0] sbox_result;
wire [ 31:0] sbox_result2;
wire [ 31:0] rot_result;
wire [127:0] temp;
aes_sbox sbox (
.sboxw1(xin2[31:0]),
.new_sboxw1(sbox_result),
.sboxw2(temp[31:0] ^ rot_result),
.new_sboxw2(sbox_result2)
);
assign rot_result = {
sbox_result[23:16] ^ rcon, sbox_result[15:8], sbox_result[7:0], sbox_result[31:24]
}; // rotr(x3,8)^rcon
assign temp = {
xin0[127:96],
xin0[127:96] ^ xin0[95:64],
xin0[127:96] ^ xin0[95:64] ^ xin0[63:32],
xin0[127:96] ^ xin0[95:64] ^ xin0[63:32] ^ xin0[31:0]
};
assign xout0 = temp ^ {rot_result, rot_result, rot_result, rot_result};
// sbox_result2 is result of
// soft_aeskeygenassist(*xout0, 0x00);
// _mm_shuffle_epi32(xout1, 0xAA);
assign xout2 = {
xin2[127:96] ^ sbox_result2,
xin2[127:96] ^ xin2[95:64] ^ sbox_result2,
xin2[127:96] ^ xin2[95:64] ^ xin2[63:32] ^ sbox_result2,
xin2[127:96] ^ xin2[95:64] ^ xin2[63:32] ^ xin2[31:0] ^ sbox_result2
};
endmodule
| 8.467735 |
module aes_decrypt (
decryptedData,
encryptedData,
mKey,
clk
);
output reg [127:0] decryptedData;
input [127:0] encryptedData, mKey;
input clk;
wire [1279:0] iRK;
wire [127:0] iROut1, iROut2, iROut3, iROut4, iROut5, iROut6, iROut7, iROut8, iROut9, iROut10, finIR;
getInvRoundKeys girk1 (
iRK,
mKey
);
//inverse of round10 of encryption
inv_roundLast ir1 (
.data(iROut1),
.encryptedData(encryptedData),
.rKey(iRK[127:0])
);
//inverse of round9 of encryption
inv_round ir2 (
.outRound(iROut2),
.data(iROut1),
.rKey(iRK[255:128])
);
inv_round ir3 (
.outRound(iROut3),
.data(iROut2),
.rKey(iRK[383:256])
);
inv_round ir4 (
.outRound(iROut4),
.data(iROut3),
.rKey(iRK[511:384])
);
inv_round ir5 (
.outRound(iROut5),
.data(iROut4),
.rKey(iRK[639:512])
);
inv_round ir6 (
.outRound(iROut6),
.data(iROut5),
.rKey(iRK[767:640])
);
inv_round ir7 (
.outRound(iROut7),
.data(iROut6),
.rKey(iRK[895:768])
);
inv_round ir8 (
.outRound(iROut8),
.data(iROut7),
.rKey(iRK[1023:896])
);
inv_round ir9 (
.outRound(iROut9),
.data(iROut8),
.rKey(iRK[1151:1024])
);
inv_round ir10 (
.outRound(iROut10),
.data(iROut9),
.rKey(iRK[1279:1152])
);
assign finIR = iROut10 ^ mKey;
always @(posedge clk) begin
decryptedData = finIR;
end
endmodule
| 6.785639 |
module AES_MASTER_TOP (
input [3:0] ip1,
ip2,
ip3,
ip4,
input Apb,
Bpb,
Cpb,
Dpb,
Spb,
input CLKIN,
output [3:0] ANODE,
output [6:0] CATHODE,
output [3:0] LEDOUT
);
wire RESET = 1'b0;
wire PA, PB, PC, PD, P_MID;
wire [15:0] INPUTREG;
wire [15:0] ENCROUT;
wire [ 4:0] CATHIN;
//Debounce filters for all pushbuttons
Debounce_Filter Pmid (
.Clk(CLKIN),
.reset(RESET),
.switch_in(Spb),
.switch_out(P_MID)
);
/*Debounce_Filter PBa (.Clk(CLKIN), .reset(RESET),
.switch_in(Apb), .switch_out(PA));
Debounce_Filter PBb (.Clk(CLKIN), .reset(RESET),
.switch_in(Bpb), .switch_out(PB));
Debounce_Filter PBc (.Clk(CLKIN), .reset(RESET),
.switch_in(Cpb), .switch_out(PC));
Debounce_Filter PBd (.Clk(CLKIN), .reset(RESET),
.switch_in(Dpb), .switch_out(PD));*/
wire muxselect;
//D_Latch(.D(P_MID), .Enable(P_MID), .Q(muxselect)); //to latch the value at 1 when the centre pushbutton is pressed
Switch_Logic SL_WRAP (
.clkin(CLKIN),
.Inp(P_MID),
.SelOut(muxselect)
);
//Main slide switch input, Encrypted Output, Decrypted Output
User_Input UserInputWRAP (
.ip1(ip1),
.ip2(ip2),
.ip3(ip3),
.ip4(ip4),
.enable(muxselect),
.inpreg(INPUTREG)
);
AESin AESinWRAP (
.clk (CLKIN),
.inpu(INPUTREG),
.outp(ENCROUT)
);
//Password detection module
wire [4:0] DigitEncrOut, DigitUserOut;
wire Decenable, decmuxselect;
TOP_PW_Det PasswordDetWRAP (
.Apb(Apb),
.Bpb(Bpb),
.Cpb(Cpb),
.Dpb(Dpb),
.CLKIN(CLKIN),
.RESET(RESET),
.LEDOUT(LEDOUT),
.ENCRINP(ENCROUT),
.CHARACTER(DigitEncrOut),
.DECENABLE(Decenable)
);
Switch_Logic SLDecry_WRAP (
.clkin(CLKIN),
.Inp(Decenable),
.SelOut(decmuxselect)
);
//module to output cathode values for user module
UserInp_Out UseroutWRAP (
.clkin (CLKIN),
.reset (RESET),
.inpreg(INPUTREG),
.Digit (DigitUserOut)
);
//MUX for User Input and Pwcheck module selection
wire [4:0] DMuxIp1;
Bus_Mux_CathOut BM_to_DecrMux (
.sel(~muxselect),
.A (DigitEncrOut),
.B (DigitUserOut),
.Y (DMuxIp1)
);
Bus_Mux_CathOut Decr_MUX (
.sel(decmuxselect),
.A (DMuxIp1),
.B (DigitUserOut),
.Y (CATHIN)
);
Anode_Control anodectrlwrap1 (
.clkin(CLKIN),
.reset(RESET),
.Anode(ANODE)
);
Cathode_Control cathctrlwrap1 (
.Digit (CATHIN),
.Cathode(CATHODE)
);
endmodule
| 7.688091 |
module
//
// - Performs forward MixColumn operation.
// - Outputs a single byte of the new column
//
module aes_mixcolumn_byte_enc (
input wire [31:0] col_in ,
output wire [ 7:0] byte_out
);
//
// Multiply by 2 in GF(2^8) modulo 8'h1b
function [7:0] xt2;
input [7:0] a;
xt2 = (a << 1) ^ (a[7] ? 8'h1b : 8'b0) ;
endfunction
//
// Paired down multiply by X in GF(2^8)
function [7:0] xtN;
input[7:0] a;
input[3:0] b;
xtN = (b[0] ? a : 0) ^
(b[1] ? xt2( a) : 0) ^
(b[2] ? xt2(xt2( a)) : 0) ^
(b[3] ? xt2(xt2(xt2(a))): 0) ;
endfunction
wire [7:0] b3 = col_in[ 7: 0];
wire [7:0] b2 = col_in[15: 8];
wire [7:0] b1 = col_in[23:16];
wire [7:0] b0 = col_in[31:24];
assign byte_out = xtN(b0,4'd2) ^ xtN(b1,4'd3) ^ b2 ^ b3 ;
endmodule
| 6.742516 |
module
//
// - Outputs a single byte of the new column
//
module aes_mixcolumn_byte_dec (
input wire [31:0] col_in ,
output wire [ 7:0] byte_out
);
//
// Multiply by 2 in GF(2^8) modulo 8'h1b
function [7:0] xt2;
input [7:0] a;
xt2 = (a << 1) ^ (a[7] ? 8'h1b : 8'b0) ;
endfunction
//
// Paired down multiply by X in GF(2^8)
function [7:0] xtN;
input[7:0] a;
input[3:0] b;
xtN = (b[0] ? a : 0) ^
(b[1] ? xt2( a) : 0) ^
(b[2] ? xt2(xt2( a)) : 0) ^
(b[3] ? xt2(xt2(xt2(a))): 0) ;
endfunction
wire [7:0] b3 = col_in[ 7: 0];
wire [7:0] b2 = col_in[15: 8];
wire [7:0] b1 = col_in[23:16];
wire [7:0] b0 = col_in[31:24];
assign byte_out = xtN(b0,4'he) ^ xtN(b1,4'hb) ^ xtN(b2,4'hd) ^ xtN(b3,4'h9);
endmodule
| 7.188869 |
module
//
// - Outputs the entire new column.
//
module aes_mixcolumn_word_enc (
input wire [31:0] col_in ,
output wire [31:0] col_out
);
wire [ 7:0] b0 = col_in[ 7: 0];
wire [ 7:0] b1 = col_in[15: 8];
wire [ 7:0] b2 = col_in[23:16];
wire [ 7:0] b3 = col_in[31:24];
wire [31:0] mix_in_3 = {b3, b0, b1, b2};
wire [31:0] mix_in_2 = {b2, b3, b0, b1};
wire [31:0] mix_in_1 = {b1, b2, b3, b0};
wire [31:0] mix_in_0 = {b0, b1, b2, b3};
wire [ 7:0] mix_out_3;
wire [ 7:0] mix_out_2;
wire [ 7:0] mix_out_1;
wire [ 7:0] mix_out_0;
assign col_out = {mix_out_3, mix_out_2, mix_out_1, mix_out_0};
aes_mixcolumn_byte_enc i_mc_enc_0(.col_in(mix_in_0), .byte_out(mix_out_0));
aes_mixcolumn_byte_enc i_mc_enc_1(.col_in(mix_in_1), .byte_out(mix_out_1));
aes_mixcolumn_byte_enc i_mc_enc_2(.col_in(mix_in_2), .byte_out(mix_out_2));
aes_mixcolumn_byte_enc i_mc_enc_3(.col_in(mix_in_3), .byte_out(mix_out_3));
endmodule
| 7.188869 |
module
//
// - Outputs the entire new column.
//
module aes_mixcolumn_word_dec (
input wire [31:0] col_in ,
output wire [31:0] col_out
);
wire [ 7:0] b0 = col_in[ 7: 0];
wire [ 7:0] b1 = col_in[15: 8];
wire [ 7:0] b2 = col_in[23:16];
wire [ 7:0] b3 = col_in[31:24];
wire [31:0] mix_in_3 = {b3, b0, b1, b2};
wire [31:0] mix_in_2 = {b2, b3, b0, b1};
wire [31:0] mix_in_1 = {b1, b2, b3, b0};
wire [31:0] mix_in_0 = {b0, b1, b2, b3};
wire [ 7:0] mix_out_3;
wire [ 7:0] mix_out_2;
wire [ 7:0] mix_out_1;
wire [ 7:0] mix_out_0;
assign col_out = {mix_out_3, mix_out_2, mix_out_1, mix_out_0};
aes_mixcolumn_byte_dec i_mc_dec_0(.col_in(mix_in_0), .byte_out(mix_out_0));
aes_mixcolumn_byte_dec i_mc_dec_1(.col_in(mix_in_1), .byte_out(mix_out_1));
aes_mixcolumn_byte_dec i_mc_dec_2(.col_in(mix_in_2), .byte_out(mix_out_2));
aes_mixcolumn_byte_dec i_mc_dec_3(.col_in(mix_in_3), .byte_out(mix_out_3));
endmodule
| 7.188869 |
module
//
// - Performs forward or Inverse MixColumn operation.
// - Outputs the entire new column.
//
module aes_mixcolumn (
input wire [31:0] col_in ,
input wire dec ,
output wire [31:0] col_out
);
parameter DECRYPT_EN = 1;
wire [31:0] col_enc;
wire [31:0] col_dec;
aes_mixcolumn_word_enc i_enc_word(.col_in(col_in),.col_out(col_enc));
generate if(DECRYPT_EN) begin: decrypt_enabled
aes_mixcolumn_word_dec i_dec_word(.col_in(col_in),.col_out(col_dec));
end else begin: decrypt_disabled
assign col_dec = 32'b0;
end endgenerate
assign col_out = dec && DECRYPT_EN ? col_dec : col_enc;
endmodule
| 6.742516 |
module aes_mixcol_b (
input [7:0] i_a,
input [7:0] i_b,
input [7:0] i_c,
input [7:0] i_d,
output [7:0] o_x,
output [7:0] o_y
);
wire [7:0] s_w1, s_w2, s_w3, s_w4;
wire [7:0] s_w5, s_w6, s_w7, s_w8;
function [7:0] xtime;
input [7:0] in;
reg [3:0] xtime_t;
begin
xtime[7:5] = in[6:4];
xtime_t[3] = in[7];
xtime_t[2] = in[7];
xtime_t[1] = 0;
xtime_t[0] = in[7];
xtime[4:1] = xtime_t ^ in[3:0];
xtime[0] = in[7];
end
endfunction
assign s_w1 = i_a ^ i_b;
assign s_w2 = i_a ^ i_c;
assign s_w3 = i_c ^ i_d;
assign s_w4 = xtime(s_w1);
assign s_w5 = xtime(s_w3);
assign s_w6 = s_w2 ^ s_w4 ^ s_w5;
assign s_w7 = xtime(s_w6);
assign s_w8 = xtime(s_w7);
assign o_x = i_b ^ s_w3 ^ s_w4;
assign o_y = s_w8 ^ o_x;
endmodule
| 7.026915 |
module aes_mix_col (
s0,
s1,
s2,
s3,
out_mc
);
input wire [7:0] s0;
input wire [7:0] s1;
input wire [7:0] s2;
input wire [7:0] s3;
output wire [31:0] out_mc;
assign out_mc[31:24] = {s0[6:0],1'b0}^(8'h1b&{8{s0[7]}})^{s1[6:0],1'b0}^(8'h1b&{8{s1[7]}})^s1^s2^s3;
assign out_mc[23:16] = s0^{s1[6:0],1'b0}^(8'h1b&{8{s1[7]}})^{s2[6:0],1'b0}^(8'h1b&{8{s2[7]}})^s2^s3;
assign out_mc[15:08] = s0^s1^{s2[6:0],1'b0}^(8'h1b&{8{s2[7]}})^{s3[6:0],1'b0}^(8'h1b&{8{s3[7]}})^s3;
assign out_mc[07:00] = {s0[6:0],1'b0}^(8'h1b&{8{s0[7]}})^s0^s1^s2^{s3[6:0],1'b0}^(8'h1b&{8{s3[7]}});
endmodule
| 6.935551 |
module TOP_PAD (
CLK,
RST_,
CMD,
DIN,
READY,
OK,
DOUT
);
input [1:0] CMD;
input [7:0] DIN;
output [7:0] DOUT;
input CLK, RST_;
output READY, OK;
wire [1:0] _CMD;
wire [7:0] _DIN;
wire [7:0] _DOUT;
wire _CLK, _RST_;
wire _READY, _OK;
TOP chip_core (
_CLK,
_RST_,
_CMD,
_DIN,
_READY,
_OK,
_DOUT
);
PIW PCLK (
.PAD(CLK),
.C (_CLK)
);
PIW PRST_ (
.PAD(RST_),
.C (_RST_)
);
PIW
PCMD0 (
.PAD(CMD[0]),
.C (_CMD[0])
),
PCMD1 (
.PAD(CMD[1]),
.C (_CMD[1])
);
PIW
PDIN0 (
.PAD(DIN[0]),
.C (_DIN[0])
),
PDIN1 (
.PAD(DIN[1]),
.C (_DIN[1])
),
PDIN2 (
.PAD(DIN[2]),
.C (_DIN[2])
),
PDIN3 (
.PAD(DIN[3]),
.C (_DIN[3])
),
PDIN4 (
.PAD(DIN[4]),
.C (_DIN[4])
),
PDIN5 (
.PAD(DIN[5]),
.C (_DIN[5])
),
PDIN6 (
.PAD(DIN[6]),
.C (_DIN[6])
),
PDIN7 (
.PAD(DIN[7]),
.C (_DIN[7])
);
PO16W PREADY (
.PAD(READY),
.I (_READY)
);
PO16W POK (
.PAD(OK),
.I (_OK)
);
PO16W
PDOUT0 (
.PAD(DOUT[0]),
.I (_DOUT[0])
),
PDOUT1 (
.PAD(DOUT[1]),
.I (_DOUT[1])
),
PDOUT2 (
.PAD(DOUT[2]),
.I (_DOUT[2])
),
PDOUT3 (
.PAD(DOUT[3]),
.I (_DOUT[3])
),
PDOUT4 (
.PAD(DOUT[4]),
.I (_DOUT[4])
),
PDOUT5 (
.PAD(DOUT[5]),
.I (_DOUT[5])
),
PDOUT6 (
.PAD(DOUT[6]),
.I (_DOUT[6])
),
PDOUT7 (
.PAD(DOUT[7]),
.I (_DOUT[7])
);
endmodule
| 7.594674 |
module aes_rcon (
clk,
kld,
out
);
input clk;
input kld;
output [31:0] out;
reg [31:0] out;
reg [ 3:0] rcnt;
wire [ 3:0] rcnt_next;
always @(posedge clk)
if (kld) out <= #1 32'h01_00_00_00;
else out <= #1 frcon(rcnt_next);
assign rcnt_next = rcnt + 4'h1;
always @(posedge clk)
if (kld) rcnt <= #1 4'h0;
else rcnt <= #1 rcnt_next;
function [31:0] frcon;
input [3:0] i;
case (i) // synopsys parallel_case
4'h0: frcon = 32'h01_00_00_00;
4'h1: frcon = 32'h02_00_00_00;
4'h2: frcon = 32'h04_00_00_00;
4'h3: frcon = 32'h08_00_00_00;
4'h4: frcon = 32'h10_00_00_00;
4'h5: frcon = 32'h20_00_00_00;
4'h6: frcon = 32'h40_00_00_00;
4'h7: frcon = 32'h80_00_00_00;
4'h8: frcon = 32'h1b_00_00_00;
4'h9: frcon = 32'h36_00_00_00;
default: frcon = 32'h00_00_00_00;
endcase
endfunction
endmodule
| 6.701484 |
module aes_rconst (
input wire clk,
input wire rst_n,
input wire kld,
input wire enable,
output wire [31:0] rcon
);
reg [7:0] rcon_r;
reg [3:0] rcnt_next;
reg [3:0] rcnt;
assign rcon = {rcon_r, 24'h00_0000};
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
rcon_r <= #1 8'h01;
end else if (kld) begin
rcon_r <= #1 8'h01;
end else begin
rcon_r <= #1 frcon(rcnt_next);
end
end
always @(*) begin
rcnt_next = rcnt;
if (enable) begin
rcnt_next = rcnt + 4'h1;
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
rcnt <= #1 4'h0;
end else if (kld) begin
rcnt <= #1 4'h0;
end else begin
rcnt <= #1 rcnt_next;
end
end
function [7:0] frcon;
input [3:0] i;
begin
case (i) // synopsys parallel_case
4'h0: frcon = 8'h01;
4'h1: frcon = 8'h02;
4'h2: frcon = 8'h04;
4'h3: frcon = 8'h08;
4'h4: frcon = 8'h10;
4'h5: frcon = 8'h20;
4'h6: frcon = 8'h40;
4'h7: frcon = 8'h80;
4'h8: frcon = 8'h1b;
4'h9: frcon = 8'h36;
default: frcon = 8'h01;
endcase
end
endfunction
endmodule
| 7.015949 |
module aes_rcon_wddl (
clk,
kld,
out,
out_n
);
input clk;
input kld;
output [31:0] out;
output [31:0] out_n;
reg [31:0] out;
reg [31:0] out_n;
reg [ 3:0] rcnt;
wire [ 3:0] rcnt_next;
assign out_n = ~out;
always @(posedge clk)
if (kld) begin
out <= #1 32'h01_00_00_00;
//out_n <= #1 !out;
end else begin
out <= #1 frcon(rcnt_next);
//out_n <= #1 !out;
end
assign rcnt_next = rcnt + 4'h1;
always @(posedge clk)
if (kld) rcnt <= #1 4'h0;
else rcnt <= #1 rcnt_next;
function [31:0] frcon;
input [3:0] i;
case (i) // synopsys parallel_case
4'h0: frcon = 32'h01_00_00_00;
4'h1: frcon = 32'h02_00_00_00;
4'h2: frcon = 32'h04_00_00_00;
4'h3: frcon = 32'h08_00_00_00;
4'h4: frcon = 32'h10_00_00_00;
4'h5: frcon = 32'h20_00_00_00;
4'h6: frcon = 32'h40_00_00_00;
4'h7: frcon = 32'h80_00_00_00;
4'h8: frcon = 32'h1b_00_00_00;
4'h9: frcon = 32'h36_00_00_00;
default: frcon = 32'h00_00_00_00;
endcase
endfunction
endmodule
| 7.137498 |
module reveal_coretop(
clk,
reset_n,
trigger_din,
trigger_en,
trace_din
)/* synthesis syn_hier="hard" */;
///////// PARAMETERS for IO port///////////////
parameter NUM_CORES = 1;
parameter TOTAL_TRIGGER_DIN= 1;
parameter TOTAL_TRACE_DIN= 6;
///////// IO port define //////////
input [NUM_CORES-1:0] clk;
input [NUM_CORES-1:0] reset_n;
input [TOTAL_TRIGGER_DIN-1:0] trigger_din;
input [TOTAL_TRACE_DIN -1:0] trace_din;
// other io ports defines, including the triggered out signals
input [0:0] trigger_en;
/// wires for interconnection ///
wire [NUM_CORES-1:0] trigger_out;
wire [NUM_CORES-1:0] jtck;
wire [NUM_CORES-1:0] jrstn;
wire [NUM_CORES-1:0] jce2;
wire [NUM_CORES-1:0] jtdi;
wire [NUM_CORES-1:0] er2_tdo;
wire [NUM_CORES-1:0] jshift;
wire [NUM_CORES-1:0] jupdate;
wire [NUM_CORES-1:0] ip_enable;
wire [5:0] trace_din_net;
wire [0:0] trigger_din_net;
assign trace_din_net[0] = trace_din[0];
assign trace_din_net[1] = trace_din[1];
assign trace_din_net[2] = trace_din[2];
assign trace_din_net[3] = trace_din[3];
assign trace_din_net[4] = trace_din[4];
assign trace_din_net[5] = trace_din[5];
assign trigger_din_net[0] = trigger_din[0];
////// core instances //////
platform1_top_la0 platform1_top_la0_inst_0(
.clk (clk[0]),
.reset_n (reset_n[0]),
.jtck (jtck[0]),
.jrstn (jrstn[0]),
.jce2 (jce2[0]),
.jtdi (jtdi[0]),
.er2_tdo (er2_tdo[0]),
.jshift (jshift[0]),
.jupdate (jupdate[0]),
.trigger_din_0 (trigger_din_net[0:0]),
.trace_din (trace_din_net[5:0]),
.trigger_en (trigger_en[0]),
.ip_enable (ip_enable[0])
)/*synthesis syn_noprune=1*/;
jtagconn16 jtagconn16_inst_0(
.jtck (jtck[0]),
.jtdi (jtdi[0]),
.jshift (jshift[0]),
.jupdate (jupdate[0]),
.jrstn (jrstn[0]),
.jce2 (jce2[0]),
.ip_enable (ip_enable[0]),
.er2_tdo (er2_tdo[0])
)/*synthesis JTAG_IP="REVEAL"*//*synthesis IP_ID="0"*//* synthesis HUB_ID="0"*//*synthesis syn_noprune=1*/;
//exemplar attribute jtagconn16_inst_0 JTAG_IP "REVEAL"
//exemplar attribute jtagconn16_inst_0 IP_ID "0"
//exemplar attribute jtagconn16_inst_0 HUB_ID "0"
endmodule
| 6.582714 |
module aes_round_128 (
clk,
clr,
dat_in,
dat_out,
rconst,
skip_mix_col,
key_in,
key_out
);
input clk, clr;
input [127:0] dat_in, key_in;
input [7:0] rconst; // lower 24 bits are 0
input skip_mix_col; // for the final round
output [127:0] dat_out, key_out;
parameter LATENCY = 0; // currently allowable values are 0,1
reg [127:0] dat_out, key_out;
// internal temp vars
wire [127:0] dat_out_i, key_out_i, sub, shft, mix;
reg [127:0] shft_r;
// evolve key
evolve_key_128 ek (
.key_in (key_in),
.rconst (rconst),
.key_out(key_out_i)
);
// first two LUT levels of work
sub_bytes sb (
.in (dat_in),
.out(sub)
);
shift_rows sr (
.in (sub),
.out(shft)
);
// mid layer registers would go here, the keying
// is awkward
always @(shft) shft_r = shft;
// second 2 LUT levels of work
mix_columns mx (
.in (shft_r),
.out(mix)
);
assign dat_out_i = (skip_mix_col ? shft : mix) ^ key_out_i;
// conditional output register
generate
if (LATENCY != 0) begin
always @(posedge clk or posedge clr) begin
if (clr) dat_out <= 128'b0;
else dat_out <= dat_out_i;
end
always @(posedge clk or posedge clr) begin
if (clr) key_out <= 128'b0;
else key_out <= key_out_i;
end
end else begin
always @(dat_out_i) dat_out = dat_out_i;
always @(key_out_i) key_out = key_out_i;
end
endgenerate
endmodule
| 8.067086 |
module aes_round_256 (
clk,
clr,
dat_in,
dat_out,
rconst,
skip_mix_col,
key_in,
key_out
);
input clk, clr;
input [127:0] dat_in;
input [255:0] key_in;
input [7:0] rconst; // lower 24 bits are 0
input skip_mix_col; // for the final round
output [127:0] dat_out;
output [255:0] key_out;
parameter LATENCY = 0; // currently allowable values are 0,1
parameter KEY_EVOLVE_TYPE = 0; // full deal or subword only
reg [127:0] dat_out;
reg [255:0] key_out;
// internal temp vars
wire [127:0] dat_out_i, sub, shft, mix;
wire [255:0] key_out_i;
reg [127:0] shft_r;
// evolve key
evolve_key_256 ek (
.key_in (key_in),
.rconst (rconst),
.key_out(key_out_i)
);
defparam ek.KEY_EVOLVE_TYPE = KEY_EVOLVE_TYPE;
// first two LUT levels of work
sub_bytes sb (
.in (dat_in),
.out(sub)
);
shift_rows sr (
.in (sub),
.out(shft)
);
// mid layer registers would go here, the keying
// is awkward
always @(shft) shft_r = shft;
// second 2 LUT levels of work
mix_columns mx (
.in (shft_r),
.out(mix)
);
assign dat_out_i = (skip_mix_col ? shft : mix) ^ key_out_i[255:128];
// conditional output register
generate
if (LATENCY != 0) begin
always @(posedge clk or posedge clr) begin
if (clr) dat_out <= 128'b0;
else dat_out <= dat_out_i;
end
always @(posedge clk or posedge clr) begin
if (clr) key_out <= 256'b0;
else key_out <= key_out_i;
end
end else begin
always @(dat_out_i) dat_out = dat_out_i;
always @(key_out_i) key_out = key_out_i;
end
endgenerate
endmodule
| 6.949822 |
module aes_round_counter #(
parameter MAX_CNT = 11,
CNT_SIZE = 4
) (
// inputs
input clk,
input rst_n,
input i_cnt_en,
output o_flag,
output reg [CNT_SIZE-1:0] o_count
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
o_count <= {CNT_SIZE{1'b0}};
end else begin
if (i_cnt_en) begin
if (o_count == MAX_CNT) begin
o_count <= 'h0;
end else begin
o_count <= o_count + 1;
end
end else o_count <= 'h0;
end
end
assign o_flag = (o_count == 'ha) ? 1'b1 : 1'b0;
endmodule
| 7.066453 |
module implements the round ladder required by the AES
cipher algorithm.
-------------------------------------------------------------------------------
-- Copyright (C) 2016 ClariPhy Argentina S.A. All rights reserved
------------------------------------------------------------------------------*/
module aes_round_ladder_xor_data_sequential
#(
// PARAMETERS.
parameter NB_BYTE = 8 ,
parameter N_BYTES = 16 ,
parameter N_ROUNDS = 14 ,
parameter STAGES_BETWEEN_REGS = /*3*/ 1
)
(
// OUTPUTS.
output wire [N_BYTES * NB_BYTE - 1 : 0] o_state ,
output wire [N_BYTES * NB_BYTE - 1 : 0] o_data ,
output wire o_valid ,
// INPUTS.
input wire [N_BYTES * NB_BYTE - 1 : 0] i_state ,
input wire [N_BYTES * NB_BYTE - 1 : 0] i_data ,
input wire [N_BYTES*NB_BYTE*(N_ROUNDS+1)-1:0] i_round_key_vector ,
input wire i_valid , // [HINT]: Used only if create_out_reg==1.
input wire i_reset , // [HINT]: Used only if create_out_reg==1.
input wire i_clock // [HINT]: Used only if create_out_reg==1.
) ;
// LOCAL PARAMETERS.
localparam N_COLS = 4 ;
localparam N_ROWS = N_BYTES / N_COLS ;
localparam NB_STATE = N_BYTES * NB_BYTE ;
localparam BAD_CONF = ( NB_BYTE != 8 ) || ( N_BYTES != 16 ) || ( N_ROUNDS != 14 ) ;
// INTERNAL SIGNALS.
genvar ii ;
wire [NB_STATE*(N_ROUNDS+1+1)-1:0] round_states ;
wire [(N_ROUNDS+1+1)-1:0] valid_bus ;
wire [NB_STATE*(N_ROUNDS+1+1)-1:0] data_bus ;
// ALGORITHM BEGIN.
always @( posedge i_clock )
if ( i_reset || ( i_valid && i_trigger ) )
round_key_shifter
<= i_round_key_vector ;
else if ( i_valid && triggered )
round_key_shifter
<= { {NB_STATE{1'b0}}, round_key_shifter[ (N_ROUNDS+1)*NB_STATE - 1 : NB_STATE ] } ;
assign round_key
= round_key_shifter[ 0 +: NB_STATE ] ;
always @( posedge i_clock )
if ( i_reset )
state_in
<= i_state ;
else if ( i_valid && i_trigger )
state_in
<= i_state ^ i_round_key_vector[ 0 +: NB_STATE ] ;
else if ( i_valid && triggered )
state_in
<= state_out ;
round_block_sequential
#(
.NB_BYTE ( NB_BYTE ),
.N_BYTES ( N_BYTES ),
.ROUND_INDEX ( 1 ),
.FIRST_ROUND_INDEX ( 0 ),
.LAST_ROUND_INDEX ( N_ROUNDS ),
.CREATE_REG_LUT ( 0 ),
.CREATE_REG_OUT ( 0 )
)
u_round_block_sequential
(
.o_state ( state_out ),
.i_state ( state_in ),
.i_round_key ( round_key ),
.i_valid ( i_valid ),
.i_reset ( i_reset ),
.i_clock ( i_clock )
) ;
endmodule
| 7.842559 |
module aes_sbox (
input wire [7:0] in, // Input byte
input wire inv, // Perform inverse (set) or forward lookup
output wire [7:0] out // Output byte
);
parameter DECRYPT_EN = 1;
wire [7:0] inv_out;
wire [7:0] fwd_out;
assign out = inv && DECRYPT_EN ? inv_out : fwd_out;
generate
if (DECRYPT_EN) begin : decrypt_enabled
aes_inv_sbox i_aesi_sbox (
.in(in),
.fx(inv_out)
);
end else begin : decrypt_disabled
assign inv_out = 8'b0;
end
endgenerate
aes_fwd_sbox i_aes_sbox (
.in(in),
.fx(fwd_out)
);
endmodule
| 6.524007 |
module aes_sbox (
input wire [7:0] in, // Input byte
input wire inv, // Perform inverse (set) or forward lookup
output wire [7:0] out // Output byte
);
wire [7:0] out_fwd;
wire [7:0] out_inv;
assign out = inv ? out_inv : out_fwd;
aes_sbox_fwd i_sbox_fwd (
.in (in),
.out(out_fwd)
);
aes_sbox_inv i_sbox_inv (
.in (in),
.out(out_inv)
);
endmodule
| 6.524007 |
module XOR_n_n2_20 (
A,
B,
Q
);
input [1:0] A;
input [1:0] B;
output [1:0] Q;
XOR2_X1 U1 (
.A(A[1]),
.B(B[1]),
.Z(Q[1])
);
XOR2_X1 U2 (
.A(A[0]),
.B(B[0]),
.Z(Q[0])
);
endmodule
| 6.988444 |
module XOR_n_n8 (
A,
B,
Q
);
input [7:0] A;
input [7:0] B;
output [7:0] Q;
XOR2_X1 U1 (
.A(A[0]),
.B(B[0]),
.Z(Q[0])
);
XOR2_X1 U2 (
.A(A[1]),
.B(B[1]),
.Z(Q[1])
);
XOR2_X1 U3 (
.A(A[2]),
.B(B[2]),
.Z(Q[2])
);
XOR2_X1 U4 (
.A(A[3]),
.B(B[3]),
.Z(Q[3])
);
XOR2_X1 U5 (
.A(A[4]),
.B(B[4]),
.Z(Q[4])
);
XOR2_X1 U6 (
.A(A[5]),
.B(B[5]),
.Z(Q[5])
);
XOR2_X1 U7 (
.A(A[6]),
.B(B[6]),
.Z(Q[6])
);
XOR2_X1 U8 (
.A(A[7]),
.B(B[7]),
.Z(Q[7])
);
endmodule
| 6.585942 |
module XOR_n_n2_10 (
A,
B,
Q
);
input [1:0] A;
input [1:0] B;
output [1:0] Q;
XOR2_X1 U1 (
.A(A[1]),
.B(B[1]),
.Z(Q[1])
);
XOR2_X1 U2 (
.A(A[0]),
.B(B[0]),
.Z(Q[0])
);
endmodule
| 6.544645 |
module S4 (
clk,
in,
out
);
input clk;
input [31:0] in;
output [31:0] out;
S
S_0 (
clk,
in[31:24],
out[31:24]
),
S_1 (
clk,
in[23:16],
out[23:16]
),
S_2 (
clk,
in[15:8],
out[15:8]
),
S_3 (
clk,
in[7:0],
out[7:0]
);
endmodule
| 6.592394 |
module T (
clk,
in,
out
);
input clk;
input [7:0] in;
/* verilator lint_off UNOPTFLAT */
output [31:0] out;
/* verilator lint_off UNOPTFLAT */
S s0 (
clk,
in,
out[31:24]
);
assign out[23:16] = out[31:24];
xS s4 (
clk,
in,
out[7:0]
);
assign out[15:8] = out[23:16] ^ out[7:0];
endmodule
| 6.667023 |
module aes_test_tb;
reg clock;
reg RSTB;
reg CSB;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
wire [15:0] checkbits;
assign checkbits = mprj_io[31:16];
assign mprj_io[3] = 1'b1;
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
// would be the fast clock.
always #12.5 clock <= (clock === 1'b0);
initial begin
clock = 0;
end
initial begin
$dumpfile("aes_test.vcd");
$dumpvars(0, aes_test_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (70) begin
repeat (1000) @(posedge clock);
// $display("+1000 cycles");
end
$display("%c[1;31m", 27);
`ifdef GL
$display("Monitor: Timeout, Test LA (GL) Failed");
`else
$display("Monitor: Timeout, Test LA (RTL) Failed");
`endif
$display("%c[0m", 27);
$finish;
end
initial begin
wait (checkbits == 16'hAB40);
$display("aes test started");
wait (checkbits == 16'hAB41);
$display("ase test passed");
#1000;
$finish;
end
initial begin
RSTB <= 1'b0;
CSB <= 1'b1; // Force CSB high
#2000;
RSTB <= 1'b1; // Release reset
#100000;
CSB = 1'b0; // CSB can be released
end
initial begin // Power-up sequence
power1 <= 1'b0;
power2 <= 1'b0;
#200;
power1 <= 1'b1;
#200;
power2 <= 1'b1;
end
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire VDD3V3 = power1;
wire VDD1V8 = power2;
wire USER_VDD3V3 = power3;
wire USER_VDD1V8 = power4;
wire VSS = 1'b0;
caravel uut (
.vddio (VDD3V3),
.vddio_2 (VDD3V3),
.vssio (VSS),
.vssio_2 (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
.vdda1 (VDD3V3),
.vdda1_2 (VDD3V3),
.vdda2 (VDD3V3),
.vssa1 (VSS),
.vssa1_2 (VSS),
.vssa2 (VSS),
.vccd1 (VDD1V8),
.vccd2 (VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
.clock (clock),
.gpio (gpio),
.mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.resetb (RSTB)
);
spiflash #(
.FILENAME("aes_test.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(), // not used
.io3() // not used
);
endmodule
| 7.116338 |
module StateArray_add (
SBin0,
SBin1,
SBout,
funct,
CLK,
RSTn,
ENn,
EN,
aff_en,
IDin,
Dout,
BSY,
Drdy,
fr,
maskin
);
input [127:0] IDin;
output [127:0] Dout;
input [7:0] SBin0, SBin1, maskin;
output [7:0] SBout;
// input CLK, RSTn, ENn, Drdy, EN, BSY; // ENn == 1 for bypassing MixColumns
input CLK, RSTn, ENn, EN, aff_en, BSY, Drdy, fr; // ENn == 1 for bypassing MixColumns
input [1:0] funct; // funct = 00 for AddRoundKey and SubBytes, 10 for ShiftRows, 01 for MixColumns
reg [127:0] State;
wire [31:0] MCout, Affout;
wire [127:0] sr;
wire [7:0] w03, w13, w23, w33, c, aff, afs, unmasked;
reg [7:0] s;
affine_add affine_add (
.in0 (State[103:96] ^ (s & {8{funct[0]}})),
.out0(aff)
);
assign afs = (aff_en == 1'b0) ? aff : State[103:96];
MixColumns MC (
.in0 ({aff, State[71:64], State[39:32], State[7:0]}),
.out0(MCout),
.out1(Affout)
);
assign {w33, w23, w13, w03} = ({funct[0], ENn}==2'b10)? MCout:
({funct[0], ENn}==2'b11)? Affout:
{SBin0, afs, State[71:64], State[39:32]};
assign SBout = (fr & (~funct[0])) ? State[7:0] : State[23:16];
assign Dout = {
State[7:0],
State[39:32],
State[71:64],
State[103:96],
State[15:8],
State[47:40],
State[79:72],
State[111:104],
State[23:16],
State[55:48],
State[87:80],
State[119:112],
State[31:24],
State[63:56],
State[95:88],
State[127:120]
};
// ShiftRows
assign c = State[127:120] ^ (s & {8{~funct[0]}});
assign sr[127:96] = {c, State[119:104], SBin0};
assign sr[95:64] = {State[87:72], aff, State[95:88]};
assign sr[63:32] = {State[47:40], State[71:48]};
assign sr[31:0] = State[39:8];
always @(posedge CLK) begin
if (RSTn == 0) begin
State <= 128'b0;
s <= 0;
end else if (EN == 1) begin
if (BSY == 0) begin
if (Drdy == 1) begin
State <= {
IDin[7:0],
IDin[39:32],
IDin[71:64],
IDin[103:96],
IDin[15:8],
IDin[47:40],
IDin[79:72],
IDin[111:104],
IDin[23:16],
IDin[55:48],
IDin[87:80],
IDin[119:112],
IDin[31:24],
IDin[63:56],
IDin[95:88],
IDin[127:120]
};
end
end else begin
State <= (funct[1]==1'b0)? {w33, c, State[119:104], w23, State[95:72],
w13, State[63:40], w03, State[31:8]}: // Shift register or MixColumns
sr; // ShiftRows
if (~funct[0] == 1'b1) begin
s <= SBin1;
end else begin
s <= 0;
end
end
end
end
endmodule
| 6.762901 |
module KeyArray (
SBin,
Kin,
RK,
SBout,
RC,
selXOR,
CLK,
RSTn,
funct,
EN,
BSY,
IKin,
Krdy,
Kout,
KSen
);
input [7:0] SBin, Kin, RC;
input [127:0] IKin;
output [7:0] RK, SBout;
input selXOR, CLK, RSTn, EN, BSY, Krdy, KSen;
input [0:0] funct;
reg [127:0] K;
wire [7:0] w00, w30;
output [127:0] Kout;
assign w00 = (K[7:0] & {8{selXOR}}) ^ K[15:8];
assign w30 = K[7:0] ^ RC ^ SBin;
assign SBout = K[63:56];
assign RK = K[7:0];
assign Kout = {
K[7:0],
K[39:32],
K[71:64],
K[103:96],
K[15:8],
K[47:40],
K[79:72],
K[111:104],
K[23:16],
K[55:48],
K[87:80],
K[119:112],
K[31:24],
K[63:56],
K[95:88],
K[127:120]
};
always @(posedge CLK) begin
if (RSTn == 0) begin
K <= 128'b0;
end else if (EN == 1) begin
if (BSY == 0) begin
if (Krdy == 1) begin
K <= {
IKin[7:0],
IKin[39:32],
IKin[71:64],
IKin[103:96],
IKin[15:8],
IKin[47:40],
IKin[79:72],
IKin[111:104],
IKin[23:16],
IKin[55:48],
IKin[87:80],
IKin[119:112],
IKin[31:24],
IKin[63:56],
IKin[95:88],
IKin[127:120]
};
end
end else if (KSen == 1'b0) begin
if (funct == 1'b0) begin
K <= {Kin, K[127:16], w00}; // horizontal shift (for AddRoundKey)
end else begin
K <= {K[31:8], w30, K[127:32]}; // vertical shift (when MixColumns)
end
end
end
end
endmodule
| 7.210059 |
module gf22mul_scl_factoring (
in0,
in1,
f,
out0
);
input [1:0] in0, in1;
input f;
output [1:0] out0;
wire a0, a1, p0, p1, p2;
assign {a1, a0} = {f, ^in0};
assign {p2, p1, p0} = {~(a1 & a0), ~(in1 & in0)};
assign out0 = {p2 ^ p0, p1 ^ p0};
endmodule
| 6.584897 |
module gf22mul_factoring (
in0,
in1,
f,
out0
);
input [1:0] in0, in1;
input f;
output [1:0] out0;
wire a0, a1, p0, p1, p2;
assign {a1, a0} = {f, ^in0};
assign {p2, p1, p0} = {~(a1 & a0), ~(in1 & in0)};
assign out0 = {p2 ^ p1, p2 ^ p0};
endmodule
| 6.801902 |
module Scaler (
in0,
out0
);
input [3:0] in0;
output [3:0] out0;
wire [1:0] a, a2, b;
assign a = in0[3:2] ^ in0[1:0];
assign b = {in0[0], in0[1] ^ in0[0]} ^ in0[3:2];
assign out0 = {a, b};
endmodule
| 6.768898 |
module gf24mul (
in0,
in1,
out0
);
input [3:0] in0, in1;
output [3:0] out0;
wire [1:0] a0, a1, p0, p1, p2;
assign a1 = in1[3:2] ^ in1[1:0];
assign a0 = in0[3:2] ^ in0[1:0];
gf22mul_scaling mul0 (
.in0 (a1),
.in1 (a0),
.out0(p2)
);
gf22mul mul1 (
.in0 (in0[3:2]),
.in1 (in1[3:2]),
.out0(p1)
);
gf22mul mul2 (
.in0 (in0[1:0]),
.in1 (in1[1:0]),
.out0(p0)
);
assign out0 = {p1 ^ p2, p0 ^ p2};
endmodule
| 6.961525 |
module gf22mul_scaling (
in0,
in1,
out0
);
input [1:0] in0, in1;
output [1:0] out0;
wire a0, a1, p0, p1, p2;
assign {a1, a0} = {^in1, ^in0};
assign {p2, p1, p0} = {~(a1 & a0), ~(in1 & in0)};
assign out0 = {p2 ^ p0, p1 ^ p0};
endmodule
| 7.48249 |
module gf22mul (
in0,
in1,
out0
);
input [1:0] in0, in1;
output [1:0] out0;
wire a0, a1, p0, p1, p2;
assign {a1, a0} = {^in1, ^in0};
assign {p2, p1, p0} = {~(a1 & a0), ~(in1 & in0)};
assign out0 = {p2 ^ p1, p2 ^ p0};
endmodule
| 6.917037 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.