code stringlengths 35 6.69k | score float64 6.5 11.5 |
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modules to perform AES Key expansion
// Author : Saurav Sachin Kale (EE19B141), Ruban Vishnu Pandian (EE19B138)
// Date : 10th December, 2021
module AESKeyexpansion_128(
input clk,
input reset,
input start,
input [127:0] short_key,
output [127:0] subkey,
output [3:0] cnt128,
o... | 7.773518 |
modules to perform AES Key expansion
// Author : Saurav Sachin Kale (EE19B141), Ruban Vishnu Pandian (EE19B138)
// Date : 10th December, 2021
module AESKeyexpansion_192(
input clk,
input reset,
input start,
input [191:0] short_key,
output [127:0] subkey,
output [3:0] cnt192,
outp... | 7.773518 |
modules to perform AES Key expansion
// Author : Saurav Sachin Kale (EE19B141), Ruban Vishnu Pandian (EE19B138)
// Date : 10th December, 2021
module AESKeyexpansion_256(
input clk,
input reset,
input start,
input [255:0] short_key,
output [127:0] subkey,
output [3:0] cnt256,
o... | 7.773518 |
module ACMP_add_comb (
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 1;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_Add #(NUM_STAGE, din0_WIDTH, ... | 6.867962 |
module ACMP_add (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1... | 7.192736 |
module ACMP_sub_comb (
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 1;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_Sub #(NUM_STAGE, din0_WIDTH, ... | 6.918561 |
module ACMP_sub (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1... | 7.383367 |
module ACMP_mul_ss (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDT... | 6.97175 |
module ACMP_mul_us (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDT... | 7.363069 |
module ACMP_mul_su (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDT... | 7.245196 |
module ACMP_mul_uu (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDT... | 7.425536 |
module ACMP_smul_ss (
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_Mul_ss #(NUM_STAGE, din0_WIDTH... | 6.542019 |
module ACMP_smul_us (
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_Mul_us #(NUM_STAGE, din0_WIDTH... | 6.647923 |
module ACMP_smul_su (
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_Mul_su #(NUM_STAGE, din0_WIDTH... | 6.910677 |
module ACMP_smul_uu (
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_Mul_uu #(NUM_STAGE, din0_WIDTH... | 6.836543 |
module ACMP_sdiv_comb (
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 1;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_sdiv #(NUM_STAGE, din0_WIDTH... | 7.383339 |
module ACMP_sdiv (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-... | 7.883955 |
module ACMP_udiv_comb (
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 1;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_udiv #(NUM_STAGE, din0_WIDTH... | 7.760075 |
module ACMP_udiv (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-... | 8.26032 |
module ACMP_srem_comb (
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 1;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_srem #(NUM_STAGE, din0_WIDTH... | 6.675611 |
module ACMP_srem (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-... | 7.570909 |
module ACMP_urem_comb (
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 1;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout;
AESL_urem #(NUM_STAGE, din0_WIDTH... | 6.842342 |
module ACMP_urem (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-... | 7.676275 |
module ACMP_sdivsrem_comb (
opcode,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 1;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input [1:0] opcode;
input [din0_WIDTH-1:0] din0;
input [din1_WIDTH-1:0] din1;
output [dout_WIDTH-1:0] dout... | 6.86201 |
module ACMP_sdivsrem (
clk,
reset,
ce,
opcode,
din0,
din1,
dout
);
parameter ID = 0;
parameter NUM_STAGE = 2;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input [1:0] opcode;
input [din0_WIDTH-1:0] din0;
input [din1_... | 6.86201 |
module AESL_udiv
#(
parameter
NUM_STAGE = 2,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)
(
input clk,
input reset,
input ... | 6.636771 |
module AESMixColumn (
input clk,
input en,
input [31:0] din,
output [31:0] dout
);
AESMixColumn1 mix1 (
.clk (clk),
.en (en),
.din (din),
.dout(dout[31:24])
);
AESMixColumn2 mix2 (
.clk (clk),
.en (en),
.din (din),
.dout(dout[23:16])
);
AESMixC... | 6.569976 |
module AESMixColumn1 (
input clk,
input en,
input [31:0] din,
output [7:0] dout
);
wire [8:0] tmp_in1, tmp_in2;
wire [7:0] tmp_out1, tmp_out2;
reg [7:0] b1, b2, b3, b4;
always @(posedge clk) begin
if (en) begin
b4 <= din[7:0];
b3 <= din[15:8];
b2 <= din[23:16];
b1 <=... | 6.988245 |
module AESMixColumn2 (
input clk,
input en,
input [31:0] din,
output [7:0] dout
);
reg [7:0] b1, b2, b3, b4;
always @(posedge clk) begin
if (en) begin
b4 <= din[7:0];
b3 <= din[15:8];
b2 <= din[23:16];
b1 <= din[31:24];
end
end
wire [8:0] tmp_in1, tmp_in2;
wire... | 6.641911 |
module AESMixColumn3 (
input clk,
input en,
input [31:0] din,
output [7:0] dout
);
reg [7:0] b1, b2, b3, b4;
always @(posedge clk) begin
if (en) begin
b4 <= din[7:0];
b3 <= din[15:8];
b2 <= din[23:16];
b1 <= din[31:24];
end
end
wire [8:0] tmp_in1, tmp_in2;
wire... | 6.582093 |
module AESMixColumn4 (
input clk,
input en,
input [31:0] din,
output [7:0] dout
);
reg [7:0] b1, b2, b3, b4;
always @(posedge clk) begin
if (en) begin
b4 <= din[7:0];
b3 <= din[15:8];
b2 <= din[23:16];
b1 <= din[31:24];
end
end
wire [8:0] tmp_in1, tmp_in2;
wire... | 6.786952 |
module AESModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input Clock,
input Reset
);
// [BEGIN USER SIGNALS]
// [END USER SIGNALS]
localparam HiSignal = 1'b1;
localparam LoSignal = 1'b0;
wire Zero = 1'b0;
wire One = 1'b1;
wire true = 1'b1;
wire false = 1'b0;
wire AESModu... | 7.134377 |
module AESModule_TopLevel_AESModule_box (
// [BEGIN USER PORTS]
// [END USER PORTS]
input [8:1] SBoxAddress,
input [8:1] RBoxAddress,
input [8:1] RConAddress,
output [8:1] SBox,
output [8:1] RBox,
output [8:1] RCon
);
// [BEGIN USER SIGNALS]
// [END USER SIGNALS]
localparam Hi... | 7.134377 |
module AESOneRound (
in,
out,
roundkey,
dec,
nomix //nomix = 1 when no mixcolumn
);
input [127:0] in, roundkey;
input dec;
output reg [127:0] out;
input nomix;
reg [127:0] key_in, sub_in, inv_sub_in, inv_sh_in, mix_in, sh_in;
wire [127:0] key_out, sub_out, inv_sub_out, inv_sh_out, mix... | 6.632369 |
module AESOneRound ( //two addroundkey
in,
out,
roundkey,
dec,
nomix //nomix = 1 when no mixcolumn
);
input [127:0] in, roundkey;
input dec;
output reg [127:0] out;
input nomix;
reg [127:0] key_in, sub_in, inv_sub_in, inv_sh_in, mix_in, sh_in;
wire [127:0] key_out, sub_out, inv_sub_o... | 6.632369 |
module AESTOP(plain,key,cipher,clk,rst,start,finish,dec);
module AESTOP( clk,
rst_n,
mode, //mode = 1 --> decode?
i_start,
i_key,
i_in,
o_cipher,
o_ready);
input clk,rst_n;
input i_start,mode;
input [127:0] ... | 7.69443 |
module aes_128 (
clk,
clr,
dat_in,
dat_out,
key,
inv_key
);
input clk, clr;
input [127:0] dat_in;
input [127:0] key;
output [127:0] dat_out;
output [127:0] inv_key;
parameter LATENCY = 10; // currently allowed 0,10
localparam ROUND_LATENCY = (LATENCY == 10 ? 1 : 0);
wire [127:0... | 6.624619 |
module aes_128 (
clk,
state,
key,
out
);
input clk;
input [127:0] state, key;
output [127:0] out;
(* keep *) reg [127:0] out_reg;
assign out = ~out_reg;
// this is the way to avoid yosys from optimizing away
// all logic related to out, even there is a neg sign
// the range of out is st... | 6.624619 |
module aes_128_tb ();
reg [127:0] plain;
reg [127:0] key;
wire [127:0] sub1;
wire [127:0] shftr1;
wire [127:0] mix1;
wire [127:0] key1, key2;
wire [127:0] start2, start3;
wire [127:0] full_out, pipe_out;
reg clk, clr;
initial begin
clk = 0;
clr = 0;
#10 clr = 1;
#10 clr = 0;
... | 7.110925 |
module aes_192_sed (
clk,
start,
state,
p_c_text,
key,
out,
out_valid
);
input clk;
input start;
input [127:0] state, p_c_text;
input [191:0] key;
output [127:0] out;
output out_valid;
wire [127:0] out_temp;
wire out_valid;
// Instantiate the Unit Under Test (UUT)... | 7.075835 |
module AES_DEC (
input [127:0] Din,
input [127:0] Key,
output [127:0] Dout,
input Datardy,
input Keyrdy,
input RST,
input EN,
input CLK,
output BSY,
output Dvld
);
reg [127:0] Dreg;
reg [127:0] Kreg;
reg [127:0] KregX;
reg [ 9:0] Rreg;
reg Dvldreg, BSYreg;
wire [127... | 6.571574 |
module AES_CH (
input [127:0] Din,
input [127:0] Key,
output [127:0] Dout,
input Datardy,
input Keyrdy,
input RST,
input EN,
input MODE,
input CLK,
output BSY,
output Dvld
);
wire [127:0] Dout_E;
wire [127:0] Dout_D;
reg [127:0] Dreg;
reg EN_E;
reg EN_D;
AES_ENC A... | 6.834951 |
module AES_DEC (
input [127:0] Din,
input [127:0] Key,
output [127:0] Dout,
input Datardy,
input Keyrdy,
input RST,
input EN,
input CLK,
output BSY,
output Dvld
);
reg [127:0] Dreg;
reg [127:0] Kreg;
reg [127:0] KregX;
reg [ 9:0] Rreg;
reg Dvldreg, BSYreg;
wire [127... | 6.571574 |
module AES_CO (
input [127:0] Din_E,
input [127:0] Din_D,
input [127:0] Key_E,
input [127:0] Key_D,
output [127:0] Dout_E,
output [127:0] Dout_D,
input Datardy_E,
input Datardy_D,
input Keyrdy_E,
input Keyrdy_D,
input RST,
input EN_E,
input EN_D,
input CLK,
ou... | 7.000918 |
module AES_controller (
clk,
rst,
start,
round_num,
wr,
round_key_addr
);
input wire clk, rst, start;
output reg [3:0] round_num;
output wire [3:0] round_key_addr;
output reg wr;
reg [3:0] round_key_addr_temp;
reg flag;
always @(posedge clk or negedge rst) begin
if (!rst) begi... | 6.931178 |
module aes_control_unit (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input i_en,
input i_flag,
output reg o_busy,
output reg o_dp_en,
output reg o_ready,
output reg o_valid
);
/*********************************************************... | 7.340506 |
module aes_core_TOP (
input ICLK,
input IRSTN,
input IENCDEC,
input IINIT,
input INEXT,
output OREADY,
input [255:0] IKEY,
input IKEYLEN,
input [127:0] IBLOCK,
output [127:0] ORESULT,
output ORESULT_VALID
);
aes_core U1 (
.iClk (ICLK),
.iRstn (IRSTN),
... | 7.94061 |
module aes_core_TOP_wrapper (
input clk,
input reset_n,
input encdec,
input init,
input next,
output ready,
input [255:0] key,
input keylen,
input [127:0] block,
output [127:0] result,
output result_valid
);
aes_core_TOP U1_TOP (
.ICLK (clk),
.IRSTN (reset_... | 7.927853 |
module aes_ctrl (
input wire clk,
input wire rst,
input wire aes_start,
output reg aes_ready,
output reg aes_valid,
output reg [3:0] rnd_idx,
output reg plaintext_en,
output reg key_en,
output reg ciphertext_en,
output reg rndkey_en,
output reg sb_mux_ctrl,
output ... | 7.085512 |
module aes_data_path #(
parameter RND_SIZE = 128,
WRD_SIZE = 32,
NUM_BLK = 4,
MAX_CNT = 11,
CNT_SIZE = 4,
NUM_RND = 10
) (
// inputs
input clk,
input rst_n,
input i_dp_en,
input [RND_SIZE-1:0] i_rnd_text,
input [RND_SIZE-1... | 7.142304 |
module InvShiftrows (
input [ 31:0] rowin1,
input [ 31:0] rowin2,
input [ 31:0] rowin3,
input [ 31:0] rowin4,
output [127:0] out
);
wire [31:0] rowout1, rowout2, rowout3, rowout4;
assign rowout1 = rowin1;
assign rowout2 = {rowin2[7:0], rowin2[31:8]};
assign rowout3 = {rowin3[15:0], row... | 7.119217 |
module aes_decrypt (
input wire [127:0] ciphertext,
input wire [127:0] key,
output wire [127:0] plaintext
);
wire [127:0] states [ 0:9]; // 10 states
wire [127:0] subkeys[0:10]; // 11 keys
KeyExpansion U1 (
key,
{
subkeys[0], // well
subkeys[1], // this
subk... | 6.785639 |
module mixcolums (
input clk,
input rstn,
input [7:0] data0,
input [7:0] data1,
input [7:0] data2,
input [7:0] data3,
output reg [7:0] data0_o,
output reg [7:0] data1_o,
output reg [7:0] data2_o,
output reg [7:0] data3_o
);
reg [7:0] Tmp_p0, Tmp_p1, Tmp;
reg [7:0] T... | 6.526114 |
module ShiftRows (
res,
inp
);
input [127:0] inp;
output [127:0] res;
assign res = {
inp[127:120],
inp[87:80],
inp[47:40],
inp[7:0],
inp[95:88],
inp[55:48],
inp[15:8],
inp[103:96],
inp[63:56],
inp[23:16],
inp[111:104],
inp[71:64],
inp[31:24],
inp[11... | 7.114324 |
module AES_Encryptor (
input [127:0] PT,
input Clk,
input Rst,
input En,
output Ry,
input [127:0] Key,
output [3:0] SelKey,
output [127:0] CT
);
wire Rst_ARK_SM;
wire Rst_SBT_SM;
wire Rst_SHR_SM;
wire Rst_MXC_SM;
wire Rst_ARK_Md;
wire Rst_SBT_Md;
wire Rst_SHR_Md;
wire Rs... | 6.571734 |
module ShiftRows (
res,
inp
);
input [127:0] inp;
output [127:0] res;
assign res[7:0] = inp[7:0];
assign res[15:8] = inp[15:8];
assign res[23:16] = inp[23:16];
assign res[31:24] = inp[31:24];
assign res[39:32] = inp[47:40];
assign res[47:40] = inp[55:48];
assign res[55:48] = ... | 7.114324 |
module AddRoundKey (
res,
inp,
subkey
);
input [127:0] inp, subkey;
output [127:0] res;
assign res = inp ^ subkey;
endmodule
| 7.103156 |
module AES_enc_dec (
data,
out
);
input [127:0] data;
wire [127:0] w1;
output [127:0] out;
AES_enc en (
data,
w1
);
AES_dec de (
w1,
out
);
endmodule
| 7.09065 |
module aes_gcm_TOP (
//6 pins
input ICLK,
input IRSTN,
input IINIT,
input IENCDEC,
input IOPMODE,
output OREADY,
//355 pins
input [0:95] IIV,
input IIV_VALID,
input [0:255] IKEY,
input IKEY_VALID,
input IKEYLEN,
//130 pins
input [0:127] IAAD,
input ... | 7.237726 |
module aes_gcm_v2_TOP (
//7 pins
input ICLK,
input IRSTN,
input [0:3] ICTRL,
output OREADY,
//355 pins
input [0:95] IIV,
input IIV_VALID,
input [0:255] IKEY,
input IKEY_VALID,
input IKEYLEN,
//129 pins
input [0:127] IAAD,
input IAAD_VALID,
//129 pins
in... | 7.442807 |
module aes_gcm_v4_TOP (
//6 pins
input ICLK,
input IRSTN,
input [0:3] ICTRL,
output OREADY,
//355 pins
input [0:95] IIV,
input IIV_VALID,
input [0:255] IKEY,
input IKEY_VALID,
input IKEYLEN,
//130 pins
input [0:127] IAAD,
input IAAD_VALID,
//130 pins
in... | 7.028998 |
module aes_keygenassist(input [7:0] rcon, input [31:0] byte1, input [31:0] byte3, input [127:0] x0, output res[127:0]);
wire xbyte1[31:0];
wire xbyte3[31:0];
reg opx0[127:0];
assign opx0 = {x0};
aes_sbox sbox(.sboxw1(byte1), .new_sboxw1(xbyte1), .sboxw2(byte3), new_sboxw1(xbyte3) );
// ??? mm_shuffle_epi32(xout1, 0x... | 7.774252 |
module aes_genkey_sub (
input clk,
input [3:0] rcon,
input [127:0] xin0,
input [127:0] xin2,
output [127:0] xout0,
output [127:0] xout2
);
wire [ 31:0] sbox_result;
wire [ 31:0] sbox_result2;
wire [ 31:0] rot_result;
wire [127:0] temp;
reg [127:0] temp2;
//reg [7:0] rot_byte;
//... | 8.467735 |
module aes_genkey_sub2 (
input clk,
input [7:0] rcon,
input [127:0] xin0,
input [127:0] xin2,
output [127:0] xout0,
output [127:0] xout2
);
wire [ 31:0] sbox_result;
wire [ 31:0] sbox_result2;
reg [ 31:0] rot_result;
reg [127:0] temp;
reg [127:0] temp2;
//reg [7:0] rot_byte;
a... | 8.467735 |
module aes_genkey (
input clk,
input rstn,
input [127:0] input0,
input [127:0] input1,
output keygen_done,
output [127:0] k0,
output [127:0] k1,
output [127:0] k2,
output [127:0] k3,
output [127:0] k4,
output [127:0] k5,
output [127:0] k6,
output [127:0] k7,
outpu... | 6.596787 |
module aes_genkey_sub (
input clk,
input [3:0] rcon,
input [127:0] xin0,
input [127:0] xin2,
output [127:0] xout0,
output [127:0] xout2
);
wire [ 31:0] sbox_result;
wire [ 31:0] sbox_result2;
wire [ 31:0] rot_result;
wire [127:0] temp;
aes_sbox sbox (
.sboxw1(xin2[31:0]),
... | 8.467735 |
module aes_decrypt (
decryptedData,
encryptedData,
mKey,
clk
);
output reg [127:0] decryptedData;
input [127:0] encryptedData, mKey;
input clk;
wire [1279:0] iRK;
wire [127:0] iROut1, iROut2, iROut3, iROut4, iROut5, iROut6, iROut7, iROut8, iROut9, iROut10, finIR;
getInvRoundKeys girk1 (
... | 6.785639 |
module AES_MASTER_TOP (
input [3:0] ip1,
ip2,
ip3,
ip4,
input Apb,
Bpb,
Cpb,
Dpb,
Spb,
input CLKIN,
output [3:0] ANODE,
output [6:0] CATHODE,
output [3:0] LEDOUT
);
wire RESET = 1'b0;
wire PA, PB, PC, PD, P_MID;
wire [15:0] INPUTREG;
wire [15:0] ENCROUT;
wi... | 7.688091 |
module
//
// - Performs forward MixColumn operation.
// - Outputs a single byte of the new column
//
module aes_mixcolumn_byte_enc (
input wire [31:0] col_in ,
output wire [ 7:0] byte_out
);
//
// Multiply by 2 in GF(2^8) modulo 8'h1b
function [7:0] xt2;
input [7:0] a;
xt2 = (a << 1) ^ (a[7] ? 8'h1b : 8... | 6.742516 |
module
//
// - Outputs a single byte of the new column
//
module aes_mixcolumn_byte_dec (
input wire [31:0] col_in ,
output wire [ 7:0] byte_out
);
//
// Multiply by 2 in GF(2^8) modulo 8'h1b
function [7:0] xt2;
input [7:0] a;
xt2 = (a << 1) ^ (a[7] ? 8'h1b : 8'b0) ;
endfunction
//
// Paired down multi... | 7.188869 |
module
//
// - Outputs the entire new column.
//
module aes_mixcolumn_word_enc (
input wire [31:0] col_in ,
output wire [31:0] col_out
);
wire [ 7:0] b0 = col_in[ 7: 0];
wire [ 7:0] b1 = col_in[15: 8];
wire [ 7:0] b2 = col_in[23:16];
wire [ 7:0] b3 = col_in[31:24];
wire [31:0] mix_in_3 = {b3, b0, b1, b2};... | 7.188869 |
module
//
// - Outputs the entire new column.
//
module aes_mixcolumn_word_dec (
input wire [31:0] col_in ,
output wire [31:0] col_out
);
wire [ 7:0] b0 = col_in[ 7: 0];
wire [ 7:0] b1 = col_in[15: 8];
wire [ 7:0] b2 = col_in[23:16];
wire [ 7:0] b3 = col_in[31:24];
wire [31:0] mix_in_3 = {b3, b0, b1, b2};... | 7.188869 |
module
//
// - Performs forward or Inverse MixColumn operation.
// - Outputs the entire new column.
//
module aes_mixcolumn (
input wire [31:0] col_in ,
input wire dec ,
output wire [31:0] col_out
);
parameter DECRYPT_EN = 1;
wire [31:0] col_enc;
wire [31:0] col_dec;
aes_mixcolumn_word_enc i_e... | 6.742516 |
module aes_mixcol_b (
input [7:0] i_a,
input [7:0] i_b,
input [7:0] i_c,
input [7:0] i_d,
output [7:0] o_x,
output [7:0] o_y
);
wire [7:0] s_w1, s_w2, s_w3, s_w4;
wire [7:0] s_w5, s_w6, s_w7, s_w8;
function [7:0] xtime;
input [7:0] in;
reg [3:0] xtime_t;
begin
xtime... | 7.026915 |
module aes_mix_col (
s0,
s1,
s2,
s3,
out_mc
);
input wire [7:0] s0;
input wire [7:0] s1;
input wire [7:0] s2;
input wire [7:0] s3;
output wire [31:0] out_mc;
assign out_mc[31:24] = {s0[6:0],1'b0}^(8'h1b&{8{s0[7]}})^{s1[6:0],1'b0}^(8'h1b&{8{s1[7]}})^s1^s2^s3;
assign out_mc[23:16] = s0^... | 6.935551 |
module TOP_PAD (
CLK,
RST_,
CMD,
DIN,
READY,
OK,
DOUT
);
input [1:0] CMD;
input [7:0] DIN;
output [7:0] DOUT;
input CLK, RST_;
output READY, OK;
wire [1:0] _CMD;
wire [7:0] _DIN;
wire [7:0] _DOUT;
wire _CLK, _RST_;
wire _READY, _OK;
TOP chip_core (
_CLK,
_... | 7.594674 |
module aes_rcon (
clk,
kld,
out
);
input clk;
input kld;
output [31:0] out;
reg [31:0] out;
reg [ 3:0] rcnt;
wire [ 3:0] rcnt_next;
always @(posedge clk)
if (kld) out <= #1 32'h01_00_00_00;
else out <= #1 frcon(rcnt_next);
assign rcnt_next = rcnt + 4'h1;
always @(posedge clk)
... | 6.701484 |
module aes_rconst (
input wire clk,
input wire rst_n,
input wire kld,
input wire enable,
output wire [31:0] rcon
);
reg [7:0] rcon_r;
reg [3:0] rcnt_next;
reg [3:0] rcnt;
assign rcon = {rcon_r, 24'h00_0000};
always @(posedge clk or negedge rst_n) begin
... | 7.015949 |
module aes_rcon_wddl (
clk,
kld,
out,
out_n
);
input clk;
input kld;
output [31:0] out;
output [31:0] out_n;
reg [31:0] out;
reg [31:0] out_n;
reg [ 3:0] rcnt;
wire [ 3:0] rcnt_next;
assign out_n = ~out;
always @(posedge clk)
if (kld) begin
out <= #1 32'h01_00_00_00;
... | 7.137498 |
module reveal_coretop(
clk,
reset_n,
trigger_din,
trigger_en,
trace_din
)/* synthesis syn_hier="hard" */;
///////// PARAMETERS for IO port///////////////
parameter NUM_CORES = 1;
parameter TOTAL_TRIGGER_DIN= 1;
parameter TOTAL_TRACE_DIN= 6;
///////// IO port define //////////
input [NUM_CO... | 6.582714 |
module aes_round_128 (
clk,
clr,
dat_in,
dat_out,
rconst,
skip_mix_col,
key_in,
key_out
);
input clk, clr;
input [127:0] dat_in, key_in;
input [7:0] rconst; // lower 24 bits are 0
input skip_mix_col; // for the final round
output [127:0] dat_out, key_out;
parameter LATENC... | 8.067086 |
module aes_round_256 (
clk,
clr,
dat_in,
dat_out,
rconst,
skip_mix_col,
key_in,
key_out
);
input clk, clr;
input [127:0] dat_in;
input [255:0] key_in;
input [7:0] rconst; // lower 24 bits are 0
input skip_mix_col; // for the final round
output [127:0] dat_out;
output [25... | 6.949822 |
module aes_round_counter #(
parameter MAX_CNT = 11,
CNT_SIZE = 4
) (
// inputs
input clk,
input rst_n,
input i_cnt_en,
output o_flag,
output reg [CNT_SIZE-1:0] o_count
);
always @(posedge clk or negedge rst... | 7.066453 |
module implements the round ladder required by the AES
cipher algorithm.
-------------------------------------------------------------------------------
-- Copyright (C) 2016 ClariPhy Argentina S.A. All rights reserved
------------------------------------------------------------------------------*/
module aes... | 7.842559 |
module aes_sbox (
input wire [7:0] in, // Input byte
input wire inv, // Perform inverse (set) or forward lookup
output wire [7:0] out // Output byte
);
parameter DECRYPT_EN = 1;
wire [7:0] inv_out;
wire [7:0] fwd_out;
assign out = inv && DECRYPT_EN ? inv_out : fwd_out;
generate
... | 6.524007 |
module aes_sbox (
input wire [7:0] in, // Input byte
input wire inv, // Perform inverse (set) or forward lookup
output wire [7:0] out // Output byte
);
wire [7:0] out_fwd;
wire [7:0] out_inv;
assign out = inv ? out_inv : out_fwd;
aes_sbox_fwd i_sbox_fwd (
.in (in),
.out(o... | 6.524007 |
module XOR_n_n2_20 (
A,
B,
Q
);
input [1:0] A;
input [1:0] B;
output [1:0] Q;
XOR2_X1 U1 (
.A(A[1]),
.B(B[1]),
.Z(Q[1])
);
XOR2_X1 U2 (
.A(A[0]),
.B(B[0]),
.Z(Q[0])
);
endmodule
| 6.988444 |
module XOR_n_n8 (
A,
B,
Q
);
input [7:0] A;
input [7:0] B;
output [7:0] Q;
XOR2_X1 U1 (
.A(A[0]),
.B(B[0]),
.Z(Q[0])
);
XOR2_X1 U2 (
.A(A[1]),
.B(B[1]),
.Z(Q[1])
);
XOR2_X1 U3 (
.A(A[2]),
.B(B[2]),
.Z(Q[2])
);
XOR2_X1 U4 (
.A(... | 6.585942 |
module XOR_n_n2_10 (
A,
B,
Q
);
input [1:0] A;
input [1:0] B;
output [1:0] Q;
XOR2_X1 U1 (
.A(A[1]),
.B(B[1]),
.Z(Q[1])
);
XOR2_X1 U2 (
.A(A[0]),
.B(B[0]),
.Z(Q[0])
);
endmodule
| 6.544645 |
module S4 (
clk,
in,
out
);
input clk;
input [31:0] in;
output [31:0] out;
S
S_0 (
clk,
in[31:24],
out[31:24]
),
S_1 (
clk,
in[23:16],
out[23:16]
),
S_2 (
clk,
in[15:8],
out[15:8]... | 6.592394 |
module T (
clk,
in,
out
);
input clk;
input [7:0] in;
/* verilator lint_off UNOPTFLAT */
output [31:0] out;
/* verilator lint_off UNOPTFLAT */
S s0 (
clk,
in,
out[31:24]
);
assign out[23:16] = out[31:24];
xS s4 (
clk,
in,
out[7:0]
);
assign out[15:8... | 6.667023 |
module aes_test_tb;
reg clock;
reg RSTB;
reg CSB;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
wire [15:0] checkbits;
assign checkbits = mprj_io[31:16];
assign mprj_io[3] = 1'b1;
// External clock is used by default. Make this artificially fast for the
// simulat... | 7.116338 |
module StateArray_add (
SBin0,
SBin1,
SBout,
funct,
CLK,
RSTn,
ENn,
EN,
aff_en,
IDin,
Dout,
BSY,
Drdy,
fr,
maskin
);
input [127:0] IDin;
output [127:0] Dout;
input [7:0] SBin0, SBin1, maskin;
output [7:0] SBout;
// input CLK, RSTn, ENn, Drdy, EN, BSY... | 6.762901 |
module KeyArray (
SBin,
Kin,
RK,
SBout,
RC,
selXOR,
CLK,
RSTn,
funct,
EN,
BSY,
IKin,
Krdy,
Kout,
KSen
);
input [7:0] SBin, Kin, RC;
input [127:0] IKin;
output [7:0] RK, SBout;
input selXOR, CLK, RSTn, EN, BSY, Krdy, KSen;
input [0:0] funct;
reg [12... | 7.210059 |
module gf22mul_scl_factoring (
in0,
in1,
f,
out0
);
input [1:0] in0, in1;
input f;
output [1:0] out0;
wire a0, a1, p0, p1, p2;
assign {a1, a0} = {f, ^in0};
assign {p2, p1, p0} = {~(a1 & a0), ~(in1 & in0)};
assign out0 = {p2 ^ p0, p1 ^ p0};
endmodule
| 6.584897 |
module gf22mul_factoring (
in0,
in1,
f,
out0
);
input [1:0] in0, in1;
input f;
output [1:0] out0;
wire a0, a1, p0, p1, p2;
assign {a1, a0} = {f, ^in0};
assign {p2, p1, p0} = {~(a1 & a0), ~(in1 & in0)};
assign out0 = {p2 ^ p1, p2 ^ p0};
endmodule
| 6.801902 |
module Scaler (
in0,
out0
);
input [3:0] in0;
output [3:0] out0;
wire [1:0] a, a2, b;
assign a = in0[3:2] ^ in0[1:0];
assign b = {in0[0], in0[1] ^ in0[0]} ^ in0[3:2];
assign out0 = {a, b};
endmodule
| 6.768898 |
module gf24mul (
in0,
in1,
out0
);
input [3:0] in0, in1;
output [3:0] out0;
wire [1:0] a0, a1, p0, p1, p2;
assign a1 = in1[3:2] ^ in1[1:0];
assign a0 = in0[3:2] ^ in0[1:0];
gf22mul_scaling mul0 (
.in0 (a1),
.in1 (a0),
.out0(p2)
);
gf22mul mul1 (
.in0 (in0[3:2]),
... | 6.961525 |
module gf22mul_scaling (
in0,
in1,
out0
);
input [1:0] in0, in1;
output [1:0] out0;
wire a0, a1, p0, p1, p2;
assign {a1, a0} = {^in1, ^in0};
assign {p2, p1, p0} = {~(a1 & a0), ~(in1 & in0)};
assign out0 = {p2 ^ p0, p1 ^ p0};
endmodule
| 7.48249 |
module gf22mul (
in0,
in1,
out0
);
input [1:0] in0, in1;
output [1:0] out0;
wire a0, a1, p0, p1, p2;
assign {a1, a0} = {^in1, ^in0};
assign {p2, p1, p0} = {~(a1 & a0), ~(in1 & in0)};
assign out0 = {p2 ^ p1, p2 ^ p0};
endmodule
| 6.917037 |
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