code stringlengths 35 6.69k | score float64 6.5 11.5 |
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modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module AD_ctrl (
input clk, //50m
input rst_n,
input [11:0] data_from_AD, //AD过来的数据信号
output clk_to_AD, //输出给AD的时钟信号
output [15:0] data_out //输出给下一级的幅值信号
);
assign clk_to_AD = clk;
reg [11 : 0] ad_ch1;
//AD CH1通道数据颠倒
always @(posedge clk) begin... | 6.554636 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module top (
input clk
);
parameter DDS_P_DW = 24;
parameter DDS_D_DW = 24;
reg [DDS_P_DW-1:0] angle = 0;
reg [ 31:0] c = 0;
//always @ (posedge clk) angle <= angle+ ( 1024*1024 ) / 2 ; //32周期出一个波?
always @(posedge clk) angle <= angle + (1024 * 512); //32周期出一个波?
wire [11:0] s12_sin;
wir... | 7.233807 |
module dds_top (
input clk,
input [23:0] angle,
output reg [11:0] dds_data_cos,
dds_data_sin
);
wire [23:0] dds_data_sin_24;
wire [23:0] dds_data_cos_24;
ad_dds_dual #(
.DDS_TYPE(1),
.DDS_D_DW(24),
.DDS_P_DW(24)
) dds_dual (
.clk(clk),
.angle(angle),
.scale(... | 6.992953 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module AD_FIFO #(
parameter DSIZE = 10,
parameter ASIZE = 4
) (
input wclk,
rclk,
rst,
input rreq,
wreq,
input [DSIZE-1:0] wdata,
output reg [MDSIZE-1:0] rdata,
output reg empty
);
localparam MDSIZE = DSIZE * 2;
localparam RAMDEPTH = 1 << ASIZE;
wire [ASIZE:0] raddr_next, ... | 6.522013 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module ad_ip_jesd204_tpl_adc #(
parameter ID = 0,
parameter NUM_CHANNELS = 1,
parameter CHANNEL_WIDTH = 14,
parameter NUM_LANES = 1,
parameter TWOS_COMPLEMENT = 1
) (
// jesd interface
// link_clk is (line-rate/40)
input link_clk,
input [3:0] link_sof,
input link_valid,
inpu... | 7.639234 |
module ad_ip_jesd204_tpl_adc_channel #(
parameter CHANNEL_WIDTH = 14,
parameter DATA_PATH_WIDTH = 2,
parameter TWOS_COMPLEMENT = 1
) (
input clk,
input [CHANNEL_WIDTH*DATA_PATH_WIDTH-1:0] raw_data,
output [16*DATA_PATH_WIDTH-1:0] fmt_data,
// Configuration and status
input dfmt_enab... | 7.639234 |
module ad_ip_jesd204_tpl_adc_core #(
parameter NUM_CHANNELS = 1,
parameter CHANNEL_WIDTH = 14,
parameter NUM_LANES = 1,
parameter TWOS_COMPLEMENT = 1,
parameter DATA_PATH_WIDTH = 1
) (
input clk,
input [NUM_CHANNELS-1:0] dfmt_enable,
input [NUM_CHANNELS-1:0] dfmt_sign_extend,
input ... | 7.639234 |
module ad_ip_jesd204_tpl_adc_deframer #(
parameter NUM_LANES = 1,
parameter NUM_CHANNELS = 1,
parameter CHANNEL_WIDTH = 16
) (
// jesd interface
// clk is (line-rate/40)
input clk,
input [3:0] link_sof,
input [NUM_LANES*32-1:0] link_data,
// adc data output
output [NUM_LANES*C... | 7.639234 |
module ad_ip_jesd204_tpl_adc_pnmon #(
parameter CHANNEL_WIDTH = 16,
parameter DATA_PATH_WIDTH = 1,
parameter TWOS_COMPLEMENT = 1
) (
input clk,
// data interface
input [CHANNEL_WIDTH*DATA_PATH_WIDTH-1:0] data,
// pn out of sync and error
output pn_oos,
output pn_err,
// proc... | 7.639234 |
module ad_ip_jesd204_tpl_adc_channel #(
parameter CONVERTER_RESOLUTION = 14,
parameter DATA_PATH_WIDTH = 2,
parameter TWOS_COMPLEMENT = 1,
parameter BITS_PER_SAMPLE = 16
) (
input clk,
input [CONVERTER_RESOLUTION*DATA_PATH_WIDTH-1:0] raw_data,
output [BITS_PER_SAMPLE*DATA_PATH_WIDTH-1:0] f... | 7.639234 |
module ad_ip_jesd204_tpl_adc_core #(
parameter NUM_LANES = 1,
parameter NUM_CHANNELS = 1,
parameter SAMPLES_PER_FRAME = 1,
parameter CONVERTER_RESOLUTION = 14,
parameter BITS_PER_SAMPLE = 16,
parameter OCTETS_PER_BEAT = 4,
parameter DATA_PATH_WIDTH = 1,
parameter LINK_DATA_WIDTH = NUM_LA... | 7.639234 |
module ad_ip_jesd204_tpl_adc_deframer #(
parameter NUM_LANES = 1,
parameter NUM_CHANNELS = 4,
parameter BITS_PER_SAMPLE = 16,
parameter CONVERTER_RESOLUTION = 14,
parameter SAMPLES_PER_FRAME = 1,
parameter OCTETS_PER_BEAT = 8,
parameter LINK_DATA_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES,
... | 7.639234 |
module ad_ip_jesd204_tpl_adc_pnmon #(
parameter CONVERTER_RESOLUTION = 16,
parameter DATA_PATH_WIDTH = 1,
parameter TWOS_COMPLEMENT = 1
) (
input clk,
// data interface
input [CONVERTER_RESOLUTION*DATA_PATH_WIDTH-1:0] data,
// pn out of sync and error
output pn_oos,
output pn_err,
... | 7.639234 |
module ad_ip_jesd204_tpl_dac_channel #(
parameter DATAPATH_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1,
parameter DATA_PATH_WIDTH = 4,
parameter CONVERTER_RESOLUTION = 16,
parameter BITS_PER_SAMPLE = 16,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DDS_CORDIC_PHASE... | 7.639234 |
module ad_ip_jesd204_tpl_dac_pn #(
parameter DATA_PATH_WIDTH = 4,
parameter CONVERTER_RESOLUTION = 16
) (
input clk,
input reset,
output [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn7_data,
output [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn15_data
);
localparam CR = CONVERTER_RESOLUTION;
... | 7.639234 |
module ad_jesd_align (
// jesd interface
rx_clk,
rx_ip_sof,
rx_ip_data,
rx_sof,
rx_data
);
// jesd interface
input rx_clk;
input [3:0] rx_ip_sof;
input [31:0] rx_ip_data;
// aligned data
output rx_sof;
output [31:0] rx_data;
// internal registers
reg [31:0] rx_ip_data_d... | 7.883127 |
module ad_lvds_out (
// data interface
tx_clk,
tx_data_p,
tx_data_n,
tx_data_out_p,
tx_data_out_n,
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
// delay-cntrl interface
delay_clk,
delay_rst,
delay_locked
);
// parameters
parameter ... | 7.421716 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module ad_mul_u16 (
// data_p = data_a * data_b;
clk,
data_a,
data_b,
data_p,
// delay interface
ddata_in,
ddata_out
);
// delayed data bus width
parameter DELAY_DATA_WIDTH = 16;
localparam DW = DELAY_DATA_WIDTH - 1;
// data_p = data_a * data_b;
input clk;
input [15:0... | 6.89365 |
module ad_mul_u16 (
// data_p = data_a * data_b;
clk,
data_a,
data_b,
data_p,
// delay interface
ddata_in,
ddata_out
);
// delayed data bus width
parameter DELAY_DATA_WIDTH = 16;
localparam DW = DELAY_DATA_WIDTH - 1;
// data_p = data_a * data_b;
input clk;
input [15:0... | 6.89365 |
module ad_mux (
input [31:0] data,
input [ 2:0] select,
output reg [ 3:0] out
);
always @(*)
case (select)
3'b000: out = data[3:0];
3'b001: out = data[7:4];
3'b010: out = data[11:8];
3'b011: out = data[15:12];
3'b100: out = data[19:16];
3'b101: out = dat... | 8.666852 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module ad_mux_tb;
parameter VCD_FILE = "ad_mux_tb.vcd";
parameter CH_W = 16; // Width of input channel
parameter CH_CNT = 64; // Number of input channels
parameter REQ_MUX_SZ = 8; // Size of mux which acts as a building block
parameter EN_REG = 1; // Enable register at output of each mux
localparam MU... | 7.175789 |
module ad_perfect_shuffle #(
parameter NUM_GROUPS = 2,
parameter WORDS_PER_GROUP = 2,
parameter WORD_WIDTH = 8
) (
input [NUM_GROUPS*WORDS_PER_GROUP*WORD_WIDTH-1:0] data_in,
output [NUM_GROUPS*WORDS_PER_GROUP*WORD_WIDTH-1:0] data_out
);
/*
* Performs the perfect shuffle operation.
*
* The p... | 6.969236 |
module ad_pngen #(
// PN7 x^7 + x^6 + 1
parameter POL_MASK = 32'b0000_0000_0000_0000_0000_0000_1100_0000,
parameter POL_W = 7,
// Number of output bits at every clock cycle
parameter DW = 16
) (
input clk,
input reset,
input clk_en,
// Output stream
output [DW-1:0] pn_data_out... | 7.340169 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module AD_samp (
input sys_clk,
input rst_n,
input [11:0] AD9226_ChanA_data, //通道AB的12bit数字量
output AD9226_ChanA_clk, //通道AB的时钟
output ad_sync_done, //AD数据同步完成标志
output [11:0] ad_sync_data
);
/*
**100kHz计数,生成AD采样时钟(50kHz)
*/
reg [8:0] cnt_100k;
parameter CNT_100k = 500; //500... | 6.859101 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module ad_tdd_sync (
clk, // system clock (100 Mhz)
rstn,
sync // re-synchronization signal
);
localparam PULSE_CNTR_WIDTH = 7;
parameter TDD_SYNC_PERIOD = 100000000; // t_period * clk_freq - 1
input clk;
input rstn;
output sync;
// internal registers
reg [(PULSE_CNTR_WIDTH-1):0] puls... | 7.425025 |
module: ad9226_sample
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ad_test;
// Inputs
reg adc_clk;
reg rst;
reg [11:0] adc_data;
// Outputs
wire adc_buf_wr;
wire [11:0] a... | 6.55928 |
module ad_wrapper #(
parameter AD_DATA_SIZE = 8
) (
input i_ad_clk,
i_rd_clk,
i_rst_n,
input i_st,
i_auto,
i_stout,
input [15:0] i_recv_count,
input [AD_DATA_SIZE-1:0] i_ad_data,
output [OUT_DATA_SIZE-1:0] o_dual_data,
output o_rd_empty,
o_working,
output reg o_ad_ope... | 8.148798 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module aeMB2_bsft ( /*AUTOARG*/
// Outputs
bsf_mx,
// Inputs
opa_of,
opb_of,
opc_of,
imm_of,
gclk,
grst,
dena,
gpha
);
parameter AEMB_BSF = 1; ///< implement barrel shift
output [31:0] bsf_mx;
input [31:0] opa_of;
input [31:0] opb_of;
input [5:0] opc_of;
inp... | 6.998236 |
module aeMB2_dparam ( /*AUTOARG*/
// Outputs
dat_o,
xdat_o,
// Inputs
adr_i,
dat_i,
wre_i,
xadr_i,
xdat_i,
xwre_i,
clk_i,
ena_i
);
parameter AW = 5; // 32
parameter DW = 2; // x2
// PORT A - READ/WRITE
output [DW-1:0] dat_o;
input [AW-1:0] adr_i;
input [DW... | 8.716146 |
module aeMB2_iwbif ( /*AUTOARG*/
// Outputs
iwb_adr_o,
iwb_stb_o,
iwb_sel_o,
iwb_wre_o,
iwb_cyc_o,
iwb_tag_o,
ich_adr,
fet_fb,
rpc_if,
rpc_ex,
rpc_mx,
exc_iwb,
// Inputs
iwb_ack_i,
iwb_dat_i,
ich_hit,
msr_ex,
hzd_bpc,
hzd_fwd,
bra_ex,
... | 6.605514 |
module aeMB2_pipe ( /*AUTOARG*/
// Outputs
brk_if,
gpha,
gclk,
grst,
dena,
iena,
// Inputs
bra_ex,
dwb_fb,
xwb_fb,
ich_fb,
fet_fb,
msr_ex,
exc_dwb,
exc_iwb,
exc_ill,
sys_clk_i,
sys_int_i,
sys_rst_i,
sys_ena_i
);
parameter AEMB_HTX = ... | 8.453301 |
module aeMB2_regs ( /*AUTOARG*/
// Outputs
opd_if,
opb_if,
opa_if,
// Inputs
xwb_mx,
sfr_mx,
sel_mx,
rpc_mx,
rd_of,
rd_ex,
mux_of,
mux_ex,
mul_mx,
ich_dat,
grst,
gpha,
gclk,
dwb_mx,
dena,
bsf_mx,
alu_mx
);
parameter AEMB_HTX = 1... | 6.536286 |
module aeMB2_sparam ( /*AUTOARG*/
// Outputs
dat_o,
// Inputs
adr_i,
dat_i,
wre_i,
clk_i,
ena_i
);
parameter AW = 5; // 32
parameter DW = 2; // x2
// PORT A - READ/WRITE
output [DW-1:0] dat_o;
input [AW-1:0] adr_i;
input [DW-1:0] dat_i;
input wre_i;
// SYSCON
input... | 7.811699 |
module aeMB2_spsram ( /*AUTOARG*/
// Outputs
dat_o,
// Inputs
adr_i,
dat_i,
wre_i,
ena_i,
rst_i,
clk_i
);
parameter AW = 8;
parameter DW = 32;
// PORT A - READ/WRITE
output [DW-1:0] dat_o;
input [AW-1:0] adr_i;
input [DW-1:0] dat_i;
input wre_i, ena_i, rst_i, clk_i;
... | 6.809276 |
module aeMB2_tpsram ( /*AUTOARG*/
// Outputs
dat_o,
xdat_o,
// Inputs
adr_i,
dat_i,
wre_i,
ena_i,
rst_i,
clk_i,
xadr_i,
xdat_i,
xwre_i,
xena_i,
xrst_i,
xclk_i
);
parameter AW = 8; // 256
parameter DW = 32; // x32
// PORT A - WRITE
output [DW-1:... | 7.796619 |
module aeMB2_xslif ( /*AUTOARG*/
// Outputs
xwb_adr_o,
xwb_dat_o,
xwb_sel_o,
xwb_tag_o,
xwb_stb_o,
xwb_cyc_o,
xwb_wre_o,
xwb_fb,
xwb_mx,
// Inputs
xwb_dat_i,
xwb_ack_i,
imm_of,
opc_of,
opa_of,
gclk,
grst,
dena,
gpha
);
parameter AEMB_XSL... | 7.498968 |
module aeMB_bpcu ( /*AUTOARG*/
// Outputs
iwb_adr_o,
rPC,
rPCLNK,
rBRA,
rDLY,
// Inputs
rMXALT,
rOPC,
rRD,
rRA,
rRESULT,
rDWBDI,
rREGA,
gclk,
grst,
gena
);
parameter IW = 24;
// INST WISHBONE
output [IW-1:2] iwb_adr_o;
// INTERNAL
output [... | 7.610314 |
module aeMB_control ( /*AUTOARG*/
// Outputs
rFSM,
nclk,
prst,
prun,
frun,
drun,
// Inputs
sys_rst_i,
sys_clk_i,
sys_int_i,
sys_exc_i,
rIWBSTB,
iwb_ack_i,
rDWBSTB,
dwb_ack_i,
rBRA,
rDLY,
iwb_dat_i,
rMSR_IE
);
// System
input sys_rst_i,... | 8.744303 |
module aeMB_core ( /*AUTOARG*/
// Outputs
iwb_stb_o,
iwb_adr_o,
fsl_wre_o,
fsl_tag_o,
fsl_stb_o,
fsl_dat_o,
fsl_adr_o,
dwb_wre_o,
dwb_stb_o,
dwb_sel_o,
dwb_dat_o,
dwb_adr_o,
// Inputs
sys_rst_i,
sys_int_i,
sys_clk_i,
iwb_dat_i,
iwb_ack_i,
... | 6.838937 |
module aeMB_core_BE #(
parameter ISIZ = 32,
parameter DSIZ = 32,
parameter MUL = 0,
parameter BSF = 0
) (
input sys_clk_i,
input sys_rst_i,
// Instruction port
output [ISIZ-1:0] if_adr,
input [31:0] if_dat,
// Data port
output dwb_we_o,
output dwb_stb_o,
output [DSI... | 7.678273 |
module aeMB_fetch ( /*AUTOARG*/
// Outputs
iwb_adr_o,
iwb_stb_o,
rPC,
rIWBSTB,
// Inputs
iwb_dat_i,
nclk,
prst,
prun,
rFSM,
rBRA,
rRESULT
);
parameter ISIZ = 32;
// Instruction WB I/F
output [ISIZ-1:0] iwb_adr_o;
output iwb_stb_o;
input [31:0] iwb_dat_i;
... | 8.462898 |
module aeMB_ibuf ( /*AUTOARG*/
// Outputs
rIMM,
rRA,
rRD,
rRB,
rALT,
rOPC,
rSIMM,
xIREG,
rSTALL,
iwb_stb_o,
// Inputs
rBRA,
rMSR_IE,
rMSR_BIP,
iwb_dat_i,
iwb_ack_i,
sys_int_i,
gclk,
grst,
gena,
oena
);
// INTERNAL
output [15:0]... | 6.590315 |
module aeMB_ucore ( /*AUTOARG*/
// Outputs
wb_wre_o,
wb_stb_o,
wb_sel_o,
wb_dat_o,
wb_adr_o,
// Inputs
wb_dat_i,
wb_ack_i,
sys_rst_i,
sys_int_i,
sys_exc_i,
sys_clk_i
);
/* Bus Address Width */
parameter ASIZ = 32;
parameter CSIZ = 7;
/* DO NOT TOUCH */
para... | 7.540581 |
module AES128 (
ProgramSelector,
UserText,
Key,
ReadyKey,
ReadRy,
WriteRy,
Clk,
Rst,
ReadEn,
WriteEn,
Result
);
input ProgramSelector;
input [127:0] UserText;
input [127:0] Key;
input ReadyKey;
input ReadRy;
input WriteRy;
input Clk;
input Rst;
output ReadEn... | 7.963218 |
module aes128_axi
(
input wire ARESETn
, input wire ACLK
, input wire [AXI_WIDTH_SID-1:0] AWID
, input wire [AXI_WIDTH_AD-1:0] AWADDR
`ifdef AMBA_AXI4
, input wire [ 7:0] AWLEN
, input wire AWLOCK
`... | 7.819775 |
module aes128_core (
input i_clk,
input i_rst,
input i_flag, //1-encrypt,0-decrypt
input [127:0] i_key,
input i_key_en, //1-key init start
output o_key_ok, //1-key init done
input [127:0] i_din,
input i_din_en,
output [127:0... | 6.591978 |
module aes128_dpc (
input i_clk,
input i_rst,
input i_flag,
input [128*11-1:0] i_keyex,
input [ 127:0] i_din,
input i_din_en,
output [ 127:0] o_dout,
output o_dout_en,
output [ 127:0] o_sbox_din,
i... | 7.338122 |
module aes128_keyex (
input i_clk,
input i_rst,
input [ 127:0] i_key, //key
input i_key_en, //key init flag
output [128*11-1:0] o_exkey, //round key
output o_key_ok, //key init ok
output o_sbox_use,
... | 9.243566 |
module mixcolumns (
input [7:0] s0c,
s1c,
s2c,
s3c,
output [7:0] m0c,
m1c,
m2c,
m3c
);
// ==============================================
// Equasions
// ==============================================
assign m0c = mul4x8(
{4'h2}, s0c
) ^ mul4x8(
{4'h3}, s1c
) ^ m... | 7.197813 |
module inv_mixcolumn (
input [7:0] s0c,
s1c,
s2c,
s3c,
output [7:0] m0c,
m1c,
m2c,
m3c
);
// ==============================================
// Equasions
// ==============================================
assign m0c = mul4x8(
{4'he}, s0c
) ^ mul4x8(
{4'hb}, s1c
... | 6.598097 |
module: AES128
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module AES128_VTF;
// Inputs
reg ProgramSelector;
reg [127:0] UserText;
reg [127:0] Key;
reg ReadyKey;
reg ReadRy;
reg... | 6.672252 |
module one_round (
clk,
state_in,
key,
state_out
);
input clk;
input [127:0] state_in, key;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
p00, p01, p02, p03,
p10, p11, p12, p13,
... | 7.018166 |
module final_round (
clk,
state_in,
key_in,
state_out
);
input clk;
input [127:0] state_in;
input [127:0] key_in;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3, z0, z1, z2, z3, k0, k1, k2, k3;
wire [7:0] p00, p01, p02, p03, p10, p11, p12, p13, p20, p21, p22, p23, p30, p31, p32, p3... | 7.609225 |
module S4 (
clk,
in,
out
);
input clk;
input [31:0] in;
output [31:0] out;
S
S_0 (
clk,
in[31:24],
out[31:24]
),
S_1 (
clk,
in[23:16],
out[23:16]
),
S_2 (
clk,
in[15:8],
out[15:8]... | 6.592394 |
module T (
clk,
in,
out
);
input clk;
input [7:0] in;
output [31:0] out;
S s0 (
clk,
in,
out[31:24]
);
assign out[23:16] = out[31:24];
xS s4 (
clk,
in,
out[7:0]
);
assign out[15:8] = out[23:16] ^ out[7:0];
endmodule
| 6.667023 |
module aes192_keyex (
input i_clk,
input i_rst,
input [ 191:0] i_key, //key
input i_key_en, //key init flag
output [128*13-1:0] o_exkey, //round key(52 words)
output o_key_ok, //key init ok
output o_sbox... | 9.121356 |
module AES_DEC (
input [127:0] Din,
input [127:0] Key,
output [127:0] Dout,
input Datardy,
input Keyrdy,
input RST,
input EN,
input CLK,
output BSY,
output Dvld
);
reg [127:0] Dreg;
reg [127:0] Kreg;
reg [127:0] KregX;
reg [ 9:0] Rreg;
reg Dvldreg, BSYreg;
wire [127... | 6.571574 |
module one_round (
clk,
state_in,
key,
state_out
);
input clk;
input [127:0] state_in, key;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
p00, p01, p02, p03,
p10, p11, p12, p13,
... | 7.018166 |
module final_round (
clk,
state_in,
key_in,
state_out
);
input clk;
input [127:0] state_in;
input [127:0] key_in;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3, z0, z1, z2, z3, k0, k1, k2, k3;
wire [7:0] p00, p01, p02, p03, p10, p11, p12, p13, p20, p21, p22, p23, p30, p31, p32, p3... | 7.609225 |
module S4 (
clk,
in,
out
);
input clk;
input [31:0] in;
output [31:0] out;
S
S_0 (
clk,
in[31:24],
out[31:24]
),
S_1 (
clk,
in[23:16],
out[23:16]
),
S_2 (
clk,
in[15:8],
out[15:8]... | 6.592394 |
module T (
clk,
in,
out
);
input clk;
input [7:0] in;
output [31:0] out;
S s0 (
clk,
in,
out[31:24]
);
assign out[23:16] = out[31:24];
xS s4 (
clk,
in,
out[7:0]
);
assign out[15:8] = out[23:16] ^ out[7:0];
endmodule
| 6.667023 |
module aes256_keyex (
input i_clk,
input i_rst,
input [ 255:0] i_key, //key
input i_key_en, //key init flag
output [128*15-1:0] o_exkey, //round key(60 words)
output o_key_ok, //key init ok
output o_sbox... | 8.883369 |
module AES_DEC (
input [127:0] Din,
input [127:0] Key,
output [127:0] Dout,
input Datardy,
input Keyrdy,
input RST,
input EN,
input CLK,
output BSY,
output Dvld
);
reg [127:0] Dreg;
reg [127:0] Kreg;
reg [127:0] KregX;
reg [ 9:0] Rreg;
reg Dvldreg, BSYreg;
wire [127... | 6.571574 |
module AES_CH (
input [127:0] Din,
input [127:0] Key,
output [127:0] Dout,
input Datardy,
input Keyrdy,
input RST,
input EN,
input MODE,
input CLK,
output BSY,
output Dvld
);
wire [127:0] Dout_E;
wire [127:0] Dout_D;
reg [127:0] Dreg;
reg EN_E;
reg EN_D;
AES_ENC A... | 6.834951 |
module AESByteSubColumn (
input clk,
input en,
input [31:0] addr,
output [31:0] data
);
SBoxRam sbox1 (
.clk (clk),
.en (en),
.addr(addr[7:0]),
.data(data[7:0])
);
SBoxRam sbox2 (
.clk (clk),
.en (en),
.addr(addr[15:8]),
.data(data[15:8])
);
SB... | 6.960147 |
module AESByteSub (
input clk,
input en,
input [127:0] addr,
output [127:0] data
);
AESByteSubColumn subcol1 (
.clk (clk),
.en (en),
.addr(addr[127:96]),
.data(data[127:96])
);
AESByteSubColumn subcol2 (
.clk (clk),
.en (en),
.addr(addr[95:64]),
.d... | 6.963143 |
module AESByteSubTestBench;
reg clk = 0;
reg en = 1;
reg [31:0] addr = 0;
wire [31:0] data;
initial #10000 $stop;
always #5 clk = ~clk;
always #10 addr = addr + 1;
AESByteSubColumn bytesubcol (
.clk (clk),
.en (en),
.addr(addr),
.data(data)
);
initial $monitor("at time %t... | 6.700705 |
module aescipher (
clk,
datain,
key,
dataout
);
input clk;
input [127:0] datain;
input [127:0] key;
output [127:0] dataout;
wire [127:0] r0_out;
wire [127:0] r1_out, r2_out, r3_out, r4_out, r5_out, r6_out, r7_out, r8_out, r9_out;
wire [127:0] keyout1, keyout2, keyout3, keyout4, keyout5,... | 6.919137 |
module AesCore (
clk,
i_data,
keyIn,
o_data,
cipherkey
);
input clk;
input [127:0] i_data;
input [127:0] keyIn;
output [127:0] o_data;
output [127:0] cipherkey;
wire [127:0] state0;
wire [127:0] rnd1, rnd2, rnd3, rnd4, rnd5, rnd6, rnd7, rnd8, rnd9;
wire [127:0] keyOut1, keyOut2, ... | 8.405321 |
module InvAesCore (
clk,
cipherText,
cipherkey,
retData,
origkey
);
input clk;
input [127:0] cipherText;
input [127:0] cipherkey;
output [127:0] retData;
output [127:0] origkey;
wire [127:0] statel;
wire [127:0] rr10, rr9, rr8, rr7, rr6, rr5, rr4, rr3, rr2;
wire [127:0] keyout1, ke... | 6.688109 |
module AESDecrypt_tb ();
reg [127:0] dataIn, dataIn192, dataIn256;
reg [127:0] key;
reg [191:0] key192;
reg [255:0] key256;
reg clk = 0;
wire [127:0] dataOut, dataOut192, dataOut256;
AESDecrypt aesDecrypt (
dataIn,
key,
clk,
dataOut
);
genvar i;
AESDecrypt #(
.Nk(6),
... | 6.987142 |
module aesEncryption (
clk,
datain,
key,
dataout
);
input clk;
input [127:0] datain;
input [127:0] key;
output [127:0] dataout;
wire [127:0] r0_out;
wire [127:0] r1_out, r2_out, r3_out, r4_out, r5_out, r6_out, r7_out, r8_out, r9_out;
wire [127:0] keyout1, keyout2, keyout3, keyout4, keyo... | 7.453735 |
module AESOneRound (
in,out,roundkey,dec,nomix,subbyteonly,sub_in,sub_out,//nomix = 1 when no mixcolumn
);
input [127:0] in,roundkey;
input dec;
input subbyteonly;
input [31:0] sub_in;
output [31:0] sub_out;
output reg [127:0] out;
input nomix;
// input clk;
reg [127:0] key_in ,inv_sh_in ,mix_in ,sh_in;
wire [12... | 6.632369 |
module KeySchedule ( // share xor?
key,
rc,
out_key,
dec,
sub_in,
sub_out
);
input [127:0] key;
input [7:0] rc;
output reg [127:0] out_key;
output [31:0] sub_in;
input [31:0] sub_out;
input dec;
reg [31:0] out_word[0:3];
reg [31:0] in_word[0:3];
integer i;
reg [31:0] g_in;... | 6.705064 |
module GFunction (
in,
out,
rc,
sub_in,
sub_out
);
input [31:0] in;
input [7:0] rc;
output [31:0] out;
output [31:0] sub_in;
input [31:0] sub_out;
wire [7:0] V[0:3];
wire [7:0] V_o[0:3];
wire [7:0] V_o_temp;
assign {V[0], V[1], V[2], V[3]} = in;
assign out = {V_o[0], V_o[1], V... | 6.596454 |
module MultiplyMinv (
in,
out
);
input [7:0] in;
output reg [7:0] out;
integer i;
always @(*) begin
for (i = 0; i < 8; i = i + 1) begin
out[i] = in[(i+2)%8] ^ in[(i+5)%8] ^ in[(i+7)%8];
end
end
endmodule
| 6.592756 |
module AddC (
in,
out
);
input [7:0] in;
output [7:0] out;
assign out = in ^ 8'b01100011;
endmodule
| 7.213922 |
module AddCinv (
in,
out
);
input [7:0] in;
output [7:0] out;
assign out = in ^ 8'b00000101;
endmodule
| 6.876168 |
module AddRoundKey (
in,
key,
out
);
input [127:0] in, key;
output [127:0] out;
assign out = in ^ key;
endmodule
| 7.103156 |
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