code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// csc = c1*d[23:16] + c2*d[15:8] + c3*d[7:0] + c4;
`timescale 1ns/100ps
module ad_csc_1 #(
parameter DELAY_DATA_WIDTH = 16) (
// data
input clk,
input [DW:0] sync,
input [23:0] data,
// constants
input [16:0] C1,
input [16:0] C2,
input [16:0] C3,
input [24:0] C4,
// sync is delay matched
output [DW:0] csc_sync_1,
output [ 7:0] csc_data_1);
localparam DW = DELAY_DATA_WIDTH - 1;
// internal wires
wire [24:0] data_1_m_s;
wire [24:0] data_2_m_s;
wire [24:0] data_3_m_s;
wire [DW:0] sync_3_m_s;
// c1*R
ad_csc_1_mul #(.DELAY_DATA_WIDTH(1)) i_mul_c1 (
.clk (clk),
.data_a (C1),
.data_b (data[23:16]),
.data_p (data_1_m_s),
.ddata_in (1'd0),
.ddata_out ());
// c2*G
ad_csc_1_mul #(.DELAY_DATA_WIDTH(1)) i_mul_c2 (
.clk (clk),
.data_a (C2),
.data_b (data[15:8]),
.data_p (data_2_m_s),
.ddata_in (1'd0),
.ddata_out ());
// c3*B
ad_csc_1_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_mul_c3 (
.clk (clk),
.data_a (C3),
.data_b (data[7:0]),
.data_p (data_3_m_s),
.ddata_in (sync),
.ddata_out (sync_3_m_s));
// sum + c4
ad_csc_1_add #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_add_c4 (
.clk (clk),
.data_1 (data_1_m_s),
.data_2 (data_2_m_s),
.data_3 (data_3_m_s),
.data_4 (C4),
.data_p (csc_data_1),
.ddata_in (sync_3_m_s),
.ddata_out (csc_sync_1));
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// Color Space Conversion, multiplier. This is a simple partial product adder
// that generates the product of the two inputs.
`timescale 1ps/1ps
module ad_csc_1_mul #(
parameter DELAY_DATA_WIDTH = 16) (
// data_a is signed
input clk,
input [16:0] data_a,
input [ 7:0] data_b,
output [24:0] data_p,
// delay match
input [(DELAY_DATA_WIDTH-1):0] ddata_in,
output [(DELAY_DATA_WIDTH-1):0] ddata_out);
// internal registers
reg [(DELAY_DATA_WIDTH-1):0] p1_ddata = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] p2_ddata = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] p3_ddata = 'd0;
reg p1_sign = 'd0;
reg p2_sign = 'd0;
reg p3_sign = 'd0;
// internal signals
wire [33:0] p3_data_s;
// a/b reg, m-reg, p-reg delay match
always @(posedge clk) begin
p1_ddata <= ddata_in;
p2_ddata <= p1_ddata;
p3_ddata <= p2_ddata;
end
always @(posedge clk) begin
p1_sign <= data_a[16];
p2_sign <= p1_sign;
p3_sign <= p2_sign;
end
assign ddata_out = p3_ddata;
assign data_p = {p3_sign, p3_data_s[23:0]};
ad_mul ad_mul_1 (
.clk(clk),
.data_a({1'b0, data_a[15:0]}),
.data_b({9'b0, data_b}),
.data_p(p3_data_s),
.ddata_in(16'h0),
.ddata_out());
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// Transmit HDMI, CrYCb to RGB conversion
// The multiplication coefficients are in 1.4.12 format
// The addition coefficients are in 1.12.12 format
// R = (+408.583/256)*Cr + (+298.082/256)*Y + ( 000.000/256)*Cb + (-222.921);
// G = (-208.120/256)*Cr + (+298.082/256)*Y + (-100.291/256)*Cb + (+135.576);
// B = ( 000.000/256)*Cr + (+298.082/256)*Y + (+516.412/256)*Cb + (-276.836);
`timescale 1ns/100ps
module ad_csc_CrYCb2RGB #(
parameter DELAY_DATA_WIDTH = 16) (
// Cr-Y-Cb inputs
input clk,
input [DELAY_DATA_WIDTH-1:0] CrYCb_sync,
input [23:0] CrYCb_data,
// R-G-B outputs
output [DELAY_DATA_WIDTH-1:0] RGB_sync,
output [23:0] RGB_data);
localparam DW = DELAY_DATA_WIDTH - 1;
// red
ad_csc #(
.DELAY_DW (DELAY_DATA_WIDTH),
.MUL_COEF_DW (18),
.SUM_COEF_DW (28),
.YCbCr_2_RGB (1))
i_csc_R (
.clk (clk),
.sync (CrYCb_sync),
.data (CrYCb_data),
.C1 ( 18'd52299),
.C2 ( 18'd38154),
.C3 ( 18'd0),
.C4 (-28'd7304675),
.csc_sync (RGB_sync),
.csc_data (RGB_data[23:16]));
// green
ad_csc #(
.MUL_COEF_DW (18),
.SUM_COEF_DW (28),
.YCbCr_2_RGB (1))
i_csc_G (
.clk (clk),
.sync (1'd0),
.data (CrYCb_data),
.C1 (-18'd26639),
.C2 ( 18'd38154),
.C3 (-18'd12837),
.C4 ( 28'd4442554),
.csc_sync (),
.csc_data (RGB_data[15:8]));
// blue
ad_csc #(
.MUL_COEF_DW (18),
.SUM_COEF_DW (28),
.YCbCr_2_RGB (1))
i_csc_B (
.clk (clk),
.sync (1'd0),
.data (CrYCb_data),
.C1 ( 18'd0),
.C2 ( 18'd38154),
.C3 ( 18'd66101),
.C4 (-28'd9071362),
.csc_sync (),
.csc_data (RGB_data[7:0]));
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// Transmit HDMI, RGB to CrYCb conversion
// The multiplication coefficients are in 1.4.12 format
// The addition coefficients are in 1.12.12 format
// Cr = (+112.439/256)*R + (-094.154/256)*G + (-018.285/256)*B + 128;
// Y = (+065.738/256)*R + (+129.057/256)*G + (+025.064/256)*B + 16;
// Cb = (-037.945/256)*R + (-074.494/256)*G + (+112.439/256)*B + 128;
`timescale 1ns/100ps
module ad_csc_RGB2CrYCb #(
parameter DELAY_DATA_WIDTH = 16) (
// R-G-B inputs
input clk,
input [DELAY_DATA_WIDTH-1:0] RGB_sync,
input [23:0] RGB_data,
// Cr-Y-Cb outputs
output [DELAY_DATA_WIDTH-1:0] CrYCb_sync,
output [23:0] CrYCb_data);
localparam DW = DELAY_DATA_WIDTH - 1;
// Cr (red-diff)
ad_csc #(
.DELAY_DW(DELAY_DATA_WIDTH))
j_csc_1_Cr (
.clk (clk),
.sync (RGB_sync),
.data (RGB_data),
.C1 ( 17'd28784), // 112.439
.C2 (-17'd24103), // -94.154
.C3 (-17'd4681), // -18.285
.C4 ( 24'd8388608), // 128
.csc_sync (CrYCb_sync),
.csc_data (CrYCb_data[23:16]));
// Y (luma)
ad_csc #(
.DELAY_DW(0))
j_csc_1_Y (
.clk (clk),
.sync (1'd0),
.data (RGB_data),
.C1 (17'd16829), // 65.739
.C2 (17'd33039), // 129.057
.C3 (17'd6416), // 25.064
.C4 (24'd1048576), // 16
.csc_sync (),
.csc_data (CrYCb_data[15:8]));
// Cb (blue-diff)
ad_csc #(
.DELAY_DW(0))
j_csc_1_Cb (
.clk (clk),
.sync (1'd0),
.data (RGB_data),
.C1 (-17'd9714), // -37.945
.C2 (-17'd19070), // -74.494
.C3 ( 17'd28784), // 112.439
.C4 (24'd8388608), // 128
.csc_sync (),
.csc_data (CrYCb_data[7:0]));
endmodule
| 8.180735 |
module AD_ctrl (
input clk, //50m
input rst_n,
input [11:0] data_from_AD, //AD过来的数据信号
output clk_to_AD, //输出给AD的时钟信号
output [15:0] data_out //输出给下一级的幅值信号
);
assign clk_to_AD = clk;
reg [11 : 0] ad_ch1;
//AD CH1通道数据颠倒
always @(posedge clk) begin
ad_ch1[11] <= data_from_AD[0];
ad_ch1[10] <= data_from_AD[1];
ad_ch1[9] <= data_from_AD[2];
ad_ch1[8] <= data_from_AD[3];
ad_ch1[7] <= data_from_AD[4];
ad_ch1[6] <= data_from_AD[5];
ad_ch1[5] <= data_from_AD[6];
ad_ch1[4] <= data_from_AD[7];
ad_ch1[3] <= data_from_AD[8];
ad_ch1[2] <= data_from_AD[9];
ad_ch1[1] <= data_from_AD[10];
ad_ch1[0] <= data_from_AD[11];
end
/**********AD十六进制转十进制***********/
volt_cal u2 (
.ad_clk(clk),
.ad_ch1(ad_ch1), //ad1 data 12bit
.data_out(data_out) //ad1 BCD voltage
);
endmodule
| 6.554636 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// data format (offset binary or 2's complement only)
`timescale 1ps/1ps
module ad_datafmt #(
// data bus width
parameter DATA_WIDTH = 16,
parameter OCTETS_PER_SAMPLE = 2,
parameter DISABLE = 0) (
// data path
input clk,
input valid,
input [(DATA_WIDTH-1):0] data,
output valid_out,
output [(8*OCTETS_PER_SAMPLE-1):0] data_out,
// control signals
input dfmt_enable,
input dfmt_type,
input dfmt_se);
// internal registers
reg valid_int = 'd0;
reg [(8*OCTETS_PER_SAMPLE-1):0] data_int = 'd0;
// internal signals
wire type_s;
wire [(8*OCTETS_PER_SAMPLE-1):0] data_out_s;
// data-path disable
generate
if (DISABLE == 1) begin
assign valid_out = valid;
assign data_out = data;
end else begin
assign valid_out = valid_int;
assign data_out = data_int;
end
endgenerate
// if offset-binary convert to 2's complement first
assign type_s = dfmt_enable & dfmt_type;
generate
if (DATA_WIDTH < 8*OCTETS_PER_SAMPLE) begin
wire signext_s;
wire sign_s;
assign signext_s = dfmt_enable & dfmt_se;
assign sign_s = signext_s & (type_s ^ data[(DATA_WIDTH-1)]);
assign data_out_s[(8*OCTETS_PER_SAMPLE-1):DATA_WIDTH] = {((8*OCTETS_PER_SAMPLE)-DATA_WIDTH){sign_s}};
end
endgenerate
assign data_out_s[(DATA_WIDTH-1)] = type_s ^ data[(DATA_WIDTH-1)];
assign data_out_s[(DATA_WIDTH-2):0] = data[(DATA_WIDTH-2):0];
always @(posedge clk) begin
valid_int <= valid;
data_int <= data_out_s;
end
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_data_clk #(
parameter SINGLE_ENDED = 0) (
input rst,
output locked,
input clk_in_p,
input clk_in_n,
output clk);
// internal signals
wire clk_ibuf_s;
// defaults
assign locked = 1'b1;
// instantiations
generate
if (SINGLE_ENDED == 1) begin
IBUFG i_rx_clk_ibuf (
.I (clk_in_p),
.O (clk_ibuf_s));
end else begin
IBUFGDS i_rx_clk_ibuf (
.I (clk_in_p),
.IB (clk_in_n),
.O (clk_ibuf_s));
end
endgenerate
BUFG i_clk_gbuf (
.I (clk_ibuf_s),
.O (clk));
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_dds_1 #(
// parameters
parameter DDS_TYPE = 1,
parameter DDS_D_DW = 16,
parameter DDS_P_DW = 16) (
// interface
input clk,
input [DDS_P_DW-1:0] angle,
input [ 15:0] scale,
output reg [DDS_D_DW-1:0] dds_data);
// local parameters
localparam DDS_CORDIC_TYPE = 1;
localparam DDS_POLINOMIAL_TYPE = 2;
// internal signals
wire [ DDS_D_DW-1:0] sine_s;
wire [DDS_D_DW+17:0] s1_data_s;
// sine
generate
if (DDS_TYPE == DDS_CORDIC_TYPE) begin
ad_dds_sine_cordic #(
.CORDIC_DW(DDS_D_DW),
.PHASE_DW(DDS_P_DW),
.DELAY_DW(1))
i_dds_sine (
.clk (clk),
.angle (angle),
.sine (sine_s),
.cosine (),
.ddata_in (1'b0),
.ddata_out ());
end else begin
ad_dds_sine i_dds_sine (
.clk (clk),
.angle (angle),
.sine (sine_s),
.ddata_in (1'b0),
.ddata_out ());
end
endgenerate
// scale for a sine generator
ad_mul #(
.A_DATA_WIDTH(DDS_D_DW + 1),
.B_DATA_WIDTH(17),
.DELAY_DATA_WIDTH(1))
i_dds_scale (
.clk (clk),
.data_a ({sine_s[DDS_D_DW-1], sine_s}),
.data_b ({scale[15], scale}),
.data_p (s1_data_s),
.ddata_in (1'b0),
.ddata_out ());
// dds data
always @(posedge clk) begin
//15'h8000 is the maximum scale
dds_data <= s1_data_s[DDS_D_DW+13:14];
end
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_dds_cordic_pipe#(
// parameters
// Range = N/A
parameter P_DW = 16,
// Range = N/A
parameter D_DW = 16,
// Range = N/A
parameter DELAY_DW = 1,
// Range = 0-(DW - 1)
parameter SHIFT = 0) (
// Interface
input clk,
(* keep = "TRUE" *) input dir,
(* keep = "TRUE" *) input [ D_DW-1:0] dataa_x,
(* keep = "TRUE" *) input [ D_DW-1:0] dataa_y,
(* keep = "TRUE" *) input [ P_DW-1:0] dataa_z,
(* keep = "TRUE" *) input [ P_DW-1:0] datab_z,
(* keep = "TRUE" *) output reg [ D_DW-1:0] result_x,
(* keep = "TRUE" *) output reg [ D_DW-1:0] result_y,
(* keep = "TRUE" *) output reg [ P_DW-1:0] result_z,
input [DELAY_DW:1] data_delay_in,
output [DELAY_DW:1] data_delay_out);
// Registers Declarations
reg [DELAY_DW:1] data_delay = 'd0;
// Wires Declarations
wire [ D_DW-1:0] sgn_shift_x;
wire [ D_DW-1:0] sgn_shift_y;
wire dir_inv = ~dir;
// Sign shift
assign sgn_shift_x = {{SHIFT{dataa_x[D_DW-1]}}, dataa_x[D_DW-1:SHIFT]};
assign sgn_shift_y = {{SHIFT{dataa_y[D_DW-1]}}, dataa_y[D_DW-1:SHIFT]};
// Stage rotation
always @(posedge clk) begin
result_x <= dataa_x + ({D_DW{dir_inv}} ^ sgn_shift_y) + dir_inv;
result_y <= dataa_y + ({D_DW{dir}} ^ sgn_shift_x) + dir;
result_z <= dataa_z + ({P_DW{dir_inv}} ^ datab_z) + dir_inv;
end
// Delay data (if used)
generate
if (DELAY_DW > 1) begin
always @(posedge clk) begin
data_delay <= data_delay_in;
end
end
endgenerate
assign data_delay_out = data_delay;
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_dds_dual #(
// parameters
parameter DDS_TYPE = 1,
parameter DDS_D_DW = 16,
parameter DDS_P_DW = 16) (
// interface
input clk,
input [DDS_P_DW-1:0] angle,
input [ 15:0] scale,
output reg [DDS_D_DW-1:0] dds_data_sin , dds_data_cos
);
// local parameters
localparam DDS_CORDIC_TYPE = 1;
localparam DDS_POLINOMIAL_TYPE = 2;
// internal signals
wire [ DDS_D_DW-1:0] sine_s;
wire [ DDS_D_DW-1:0] cosine_s;
wire [DDS_D_DW+17:0] s1_data_sin_s;
wire [DDS_D_DW+17:0] s1_data_cosin_s;
// sine
generate
if (DDS_TYPE == DDS_CORDIC_TYPE) begin
ad_dds_sine_cordic #(
.CORDIC_DW(DDS_D_DW),
.PHASE_DW(DDS_P_DW),
.DELAY_DW(1))
i_dds_sine (
.clk (clk),
.angle (angle),
.sine (sine_s),
.cosine (cosine_s),
.ddata_in (1'b0),
.ddata_out ());
end else begin
ad_dds_sine i_dds_sine (
.clk (clk),
.angle (angle),
.sine (sine_s),
.ddata_in (1'b0),
.ddata_out ());
end
endgenerate
// scale for a sine generator
ad_mul #(
.A_DATA_WIDTH(DDS_D_DW + 1),
.B_DATA_WIDTH(17),
.DELAY_DATA_WIDTH(1))
i_dds_scale (
.clk (clk),
.data_a ({sine_s[DDS_D_DW-1], sine_s}),
.data_b ({scale[15], scale}),
.data_p (s1_data_sin_s),
.ddata_in (1'b0),
.ddata_out ());
// scale for a cosine generator
ad_mul #(
.A_DATA_WIDTH(DDS_D_DW + 1),
.B_DATA_WIDTH(17),
.DELAY_DATA_WIDTH(1))
i_dds_scale_cos (
.clk (clk),
.data_a ({cosine_s[DDS_D_DW-1], cosine_s}),
.data_b ({scale[15], scale}),
.data_p (s1_data_cosin_s),
.ddata_in (1'b0),
.ddata_out ());
// dds data
always @(posedge clk) begin
//15'h8000 is the maximum scale
dds_data_sin <= s1_data_sin_s [ DDS_D_DW + 13 : 14 ];
dds_data_cos <= s1_data_cosin_s [ DDS_D_DW + 13 : 14 ];
end
endmodule
| 8.180735 |
module top (
input clk
);
parameter DDS_P_DW = 24;
parameter DDS_D_DW = 24;
reg [DDS_P_DW-1:0] angle = 0;
reg [ 31:0] c = 0;
//always @ (posedge clk) angle <= angle+ ( 1024*1024 ) / 2 ; //32周期出一个波?
always @(posedge clk) angle <= angle + (1024 * 512); //32周期出一个波?
wire [11:0] s12_sin;
wire [11:0] s12_cos;
ILA_12x2 ILA_12x2_i (
.clk_0(clk),
.probe0_0(s12_sin),
.probe1_0(s12_cos)
);
dds_top dds_top (
.clk(clk),
.angle(angle),
.dds_data_cos(s12_cos),
.dds_data_sin(s12_sin)
);
endmodule
| 7.233807 |
module dds_top (
input clk,
input [23:0] angle,
output reg [11:0] dds_data_cos,
dds_data_sin
);
wire [23:0] dds_data_sin_24;
wire [23:0] dds_data_cos_24;
ad_dds_dual #(
.DDS_TYPE(1),
.DDS_D_DW(24),
.DDS_P_DW(24)
) dds_dual (
.clk(clk),
.angle(angle),
.scale(4),
.dds_data_sin(dds_data_sin_24),
.dds_data_cos(dds_data_cos_24)
);
always @(posedge clk) dds_data_sin <= dds_data_sin_24[11:0];
always @(posedge clk) dds_data_cos <= dds_data_cos_24[11:0];
endmodule
| 6.992953 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// A simple edge detector circuit
`timescale 1ns/100ps
module ad_edge_detect #(
parameter EDGE = 0) (
input clk,
input rst,
input in,
output reg out);
localparam POS_EDGE = 0;
localparam NEG_EDGE = 1;
localparam ANY_EDGE = 2;
reg ff_m1 = 0;
reg ff_m2 = 0;
always @(posedge clk) begin
if (rst == 1) begin
ff_m1 <= 0;
ff_m2 <= 0;
end else begin
ff_m1 <= in;
ff_m2 <= ff_m1;
end
end
always @(posedge clk) begin
if (rst == 1) begin
out <= 1'b0;
end else begin
if (EDGE == POS_EDGE) begin
out <= ff_m1 & ~ff_m2;
end else if (EDGE == NEG_EDGE) begin
out <= ~ff_m1 & ff_m2;
end else begin
out <= ff_m1 ^ ff_m2;
end
end
end
endmodule
| 8.180735 |
module AD_FIFO #(
parameter DSIZE = 10,
parameter ASIZE = 4
) (
input wclk,
rclk,
rst,
input rreq,
wreq,
input [DSIZE-1:0] wdata,
output reg [MDSIZE-1:0] rdata,
output reg empty
);
localparam MDSIZE = DSIZE * 2;
localparam RAMDEPTH = 1 << ASIZE;
wire [ASIZE:0] raddr_next, waddr_next;
wire [ASIZE:0] raddr_next_gray, waddr_next_gray;
wire full_next, empty_next;
reg [ASIZE:0] raddr, waddr, full;
reg [ASIZE:0] raddr_gray, waddr_gray;
reg [ASIZE:0] _raddr_gray_wclk, _waddr_gray_rclk;
reg [ASIZE:0] raddr_gray_wclk, waddr_gray_rclk;
reg [MDSIZE-1:0] mem[RAMDEPTH-1:0];
reg [DSIZE-1:0] tmp;
reg sig;
AD_FIFO_WADDRPROC #(ASIZE) waddrproc (
.req(wreq),
.full_now(full),
.waddr_now(waddr),
.waddr_now_gray(waddr_gray),
.raddr_gray_wclk(raddr_gray_wclk),
.waddr_next(waddr_next),
.waddr_next_gray(waddr_next_gray),
.full_next(full_next)
);
AD_FIFO_RADDRPROC #(ASIZE) raddrproc (
.req(rreq),
.empty_now(empty),
.raddr_now(raddr),
.waddr_gray_rclk(waddr_gray_rclk),
.raddr_next(raddr_next),
.raddr_next_gray(raddr_next_gray),
.empty_next(empty_next)
);
always @(posedge wclk or negedge rst)
if (!rst) begin
waddr <= 0;
waddr_gray <= 0;
full <= 0;
_raddr_gray_wclk <= 0;
raddr_gray_wclk <= 0;
end else begin
if (sig) begin
waddr <= waddr_next;
full <= full_next;
waddr_gray <= waddr_next_gray;
if (wreq && !full) mem[waddr[ASIZE-1:0]] <= {tmp, wdata};
{raddr_gray_wclk, _raddr_gray_wclk} <= {_raddr_gray_wclk, raddr_gray};
end
end
always @(posedge wclk or negedge rst)
if (!rst) begin
sig <= 0;
tmp <= 0;
end else begin
sig <= wreq ? ~sig : 1'b0;
tmp <= wreq ? wdata : {DSIZE{1'bx}};
end
always @(posedge rclk or negedge rst) begin
if (!rst) begin
raddr <= 0;
rdata <= 0;
empty <= 1;
_waddr_gray_rclk <= 0;
waddr_gray_rclk <= 0;
end else begin
raddr <= raddr_next;
empty <= empty_next;
raddr_gray <= raddr_next_gray;
if (rreq && !empty) begin
rdata <= mem[raddr[ASIZE-1:0]];
end
{waddr_gray_rclk, _waddr_gray_rclk} <= {_waddr_gray_rclk, waddr_gray};
end
end
endmodule
| 6.522013 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_g2b #(
parameter DATA_WIDTH = 8) (
input [DATA_WIDTH-1:0] din,
output [DATA_WIDTH-1:0] dout);
function [DATA_WIDTH-1:0] g2b;
input [DATA_WIDTH-1:0] g;
integer i;
begin
g2b[DATA_WIDTH-1] = g[DATA_WIDTH-1];
for (i = DATA_WIDTH-1; i > 0; i = i -1) begin
g2b[i-1] = g2b[i] ^ g[i-1];
end
end
endfunction
assign dout = g2b(din);
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_iobuf #(
parameter DATA_WIDTH = 1) (
input [(DATA_WIDTH-1):0] dio_t,
input [(DATA_WIDTH-1):0] dio_i,
output [(DATA_WIDTH-1):0] dio_o,
inout [(DATA_WIDTH-1):0] dio_p);
genvar n;
generate
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_iobuf
assign dio_o[n] = dio_p[n];
assign dio_p[n] = (dio_t[n] == 1'b1) ? 1'bz : dio_i[n];
end
endgenerate
endmodule
| 8.180735 |
module ad_ip_jesd204_tpl_adc #(
parameter ID = 0,
parameter NUM_CHANNELS = 1,
parameter CHANNEL_WIDTH = 14,
parameter NUM_LANES = 1,
parameter TWOS_COMPLEMENT = 1
) (
// jesd interface
// link_clk is (line-rate/40)
input link_clk,
input [3:0] link_sof,
input link_valid,
input [NUM_LANES*32-1:0] link_data,
output link_ready,
// dma interface
output [NUM_CHANNELS-1:0] enable,
output [NUM_CHANNELS-1:0] adc_valid,
output [NUM_LANES*32-1:0] adc_data,
input adc_dovf,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
output s_axi_awready,
input [15:0] s_axi_awaddr,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
output s_axi_wready,
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
output s_axi_bvalid,
input s_axi_bready,
output [1:0] s_axi_bresp,
input s_axi_arvalid,
output s_axi_arready,
input [15:0] s_axi_araddr,
input [2:0] s_axi_arprot,
output s_axi_rvalid,
input s_axi_rready,
output [1:0] s_axi_rresp,
output [31:0] s_axi_rdata
);
// Number of samples per channel that are processed in parallel.
// Assumes 2 octets per sample.
localparam DATA_PATH_WIDTH = 2 * NUM_LANES / NUM_CHANNELS;
wire [ NUM_CHANNELS-1:0] dfmt_enable_s;
wire [ NUM_CHANNELS-1:0] dfmt_sign_extend_s;
wire [ NUM_CHANNELS-1:0] dfmt_type_s;
wire [NUM_CHANNELS*4-1:0] pn_seq_sel_s;
wire [ NUM_CHANNELS-1:0] pn_err_s;
wire [ NUM_CHANNELS-1:0] pn_oos_s;
// regmap
ad_ip_jesd204_tpl_adc_regmap #(
.ID(ID),
.NUM_CHANNELS(NUM_CHANNELS),
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
) i_regmap (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awprot(s_axi_awprot),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bresp(s_axi_bresp),
.s_axi_bready(s_axi_bready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_araddr(s_axi_araddr),
.s_axi_arprot(s_axi_arprot),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rdata(s_axi_rdata),
.link_clk(link_clk),
.dfmt_enable(dfmt_enable_s),
.dfmt_sign_extend(dfmt_sign_extend_s),
.dfmt_type(dfmt_type_s),
.pn_seq_sel(pn_seq_sel_s),
.pn_err(pn_err_s),
.pn_oos(pn_oos_s),
.enable(enable),
.adc_dovf(adc_dovf)
);
ad_ip_jesd204_tpl_adc_core #(
.NUM_CHANNELS(NUM_CHANNELS),
.CHANNEL_WIDTH(CHANNEL_WIDTH),
.NUM_LANES(NUM_LANES),
.TWOS_COMPLEMENT(TWOS_COMPLEMENT),
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
) i_core (
.clk(link_clk),
.dfmt_enable(dfmt_enable_s),
.dfmt_sign_extend(dfmt_sign_extend_s),
.dfmt_type(dfmt_type_s),
.pn_seq_sel(pn_seq_sel_s),
.pn_err(pn_err_s),
.pn_oos(pn_oos_s),
.link_valid(link_valid),
.link_ready(link_ready),
.link_sof (link_sof),
.link_data (link_data),
.adc_valid(adc_valid),
.adc_data (adc_data)
);
endmodule
| 7.639234 |
module ad_ip_jesd204_tpl_adc_channel #(
parameter CHANNEL_WIDTH = 14,
parameter DATA_PATH_WIDTH = 2,
parameter TWOS_COMPLEMENT = 1
) (
input clk,
input [CHANNEL_WIDTH*DATA_PATH_WIDTH-1:0] raw_data,
output [16*DATA_PATH_WIDTH-1:0] fmt_data,
// Configuration and status
input dfmt_enable,
input dfmt_type,
input dfmt_sign_extend,
input [3:0] pn_seq_sel,
output pn_oos,
output pn_err
);
// instantiations
ad_ip_jesd204_tpl_adc_pnmon #(
.CHANNEL_WIDTH (CHANNEL_WIDTH),
.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
.TWOS_COMPLEMENT(TWOS_COMPLEMENT)
) i_pnmon (
.clk (clk),
.data(raw_data),
.pn_seq_sel(pn_seq_sel),
.pn_oos(pn_oos),
.pn_err(pn_err)
);
generate
genvar n;
for (n = 0; n < DATA_PATH_WIDTH; n = n + 1) begin : g_datafmt
ad_datafmt #(
.DATA_WIDTH(CHANNEL_WIDTH)
) i_ad_datafmt (
.clk(clk),
.valid(1'b1),
.data(raw_data[n*CHANNEL_WIDTH+:CHANNEL_WIDTH]),
.valid_out(),
.data_out(fmt_data[n*16+:16]),
.dfmt_enable(dfmt_enable),
.dfmt_type(dfmt_type),
.dfmt_se(dfmt_sign_extend)
);
end
endgenerate
endmodule
| 7.639234 |
module ad_ip_jesd204_tpl_adc_core #(
parameter NUM_CHANNELS = 1,
parameter CHANNEL_WIDTH = 14,
parameter NUM_LANES = 1,
parameter TWOS_COMPLEMENT = 1,
parameter DATA_PATH_WIDTH = 1
) (
input clk,
input [NUM_CHANNELS-1:0] dfmt_enable,
input [NUM_CHANNELS-1:0] dfmt_sign_extend,
input [NUM_CHANNELS-1:0] dfmt_type,
input [NUM_CHANNELS*4-1:0] pn_seq_sel,
output [ NUM_CHANNELS-1:0] pn_err,
output [ NUM_CHANNELS-1:0] pn_oos,
output [NUM_CHANNELS-1:0] adc_valid,
output [NUM_LANES*32-1:0] adc_data,
input link_valid,
output link_ready,
input [3:0] link_sof,
input [NUM_LANES*32-1:0] link_data
);
// Raw and formated channel data widths
localparam CDW_RAW = CHANNEL_WIDTH * DATA_PATH_WIDTH;
localparam CDW_FMT = 16 * DATA_PATH_WIDTH;
wire [NUM_CHANNELS*CHANNEL_WIDTH*DATA_PATH_WIDTH-1:0] raw_data_s;
assign link_ready = 1'b1;
assign adc_valid = {NUM_CHANNELS{1'b1}};
ad_ip_jesd204_tpl_adc_deframer #(
.NUM_LANES(NUM_LANES),
.NUM_CHANNELS(NUM_CHANNELS),
.CHANNEL_WIDTH(CHANNEL_WIDTH)
) i_deframer (
.clk(clk),
.link_sof(link_sof),
.link_data(link_data),
.adc_data(raw_data_s)
);
generate
genvar i;
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin : g_channel
ad_ip_jesd204_tpl_adc_channel #(
.CHANNEL_WIDTH (CHANNEL_WIDTH),
.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
.TWOS_COMPLEMENT(TWOS_COMPLEMENT)
) i_channel (
.clk(clk),
.raw_data(raw_data_s[CDW_RAW*i+:CDW_RAW]),
.fmt_data(adc_data[CDW_FMT*i+:CDW_FMT]),
.dfmt_enable(dfmt_enable[i]),
.dfmt_sign_extend(dfmt_sign_extend[i]),
.dfmt_type(dfmt_type[i]),
.pn_seq_sel(pn_seq_sel[i*4+:4]),
.pn_err(pn_err[i]),
.pn_oos(pn_oos[i])
);
end
endgenerate
endmodule
| 7.639234 |
module ad_ip_jesd204_tpl_adc_deframer #(
parameter NUM_LANES = 1,
parameter NUM_CHANNELS = 1,
parameter CHANNEL_WIDTH = 16
) (
// jesd interface
// clk is (line-rate/40)
input clk,
input [3:0] link_sof,
input [NUM_LANES*32-1:0] link_data,
// adc data output
output [NUM_LANES*CHANNEL_WIDTH*2-1:0] adc_data
);
localparam TAIL_BITS = (16 - CHANNEL_WIDTH);
localparam DATA_PATH_WIDTH = 2 * NUM_LANES / NUM_CHANNELS;
localparam H = NUM_LANES / NUM_CHANNELS / 2;
localparam HD = NUM_LANES > NUM_CHANNELS ? 1 : 0;
localparam OCT_OFFSET = HD ? 32 : 8;
wire [NUM_LANES*32-1:0] link_data_s;
// data multiplex
genvar i;
genvar j;
generate
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin : g_deframer_outer
for (j = 0; j < DATA_PATH_WIDTH; j = j + 1) begin : g_deframer_inner
localparam k = j + i * DATA_PATH_WIDTH;
localparam adc_lsb = k * CHANNEL_WIDTH;
localparam oct0_lsb = HD ? ((i * H + j % H) * 64 + (j / H) * 8) : (k * 16);
localparam oct1_lsb = oct0_lsb + OCT_OFFSET + TAIL_BITS;
assign adc_data[adc_lsb+:CHANNEL_WIDTH] = {
link_data_s[oct0_lsb+:8], link_data_s[oct1_lsb+:8-TAIL_BITS]
};
end
end
endgenerate
// frame-alignment
generate
genvar n;
for (n = 0; n < NUM_LANES; n = n + 1) begin : g_xcvr_if
ad_xcvr_rx_if i_xcvr_if (
.rx_clk(clk),
.rx_ip_sof(link_sof),
.rx_ip_data(link_data[n*32+:32]),
.rx_sof(),
.rx_data(link_data_s[n*32+:32])
);
end
endgenerate
endmodule
| 7.639234 |
module ad_ip_jesd204_tpl_adc_pnmon #(
parameter CHANNEL_WIDTH = 16,
parameter DATA_PATH_WIDTH = 1,
parameter TWOS_COMPLEMENT = 1
) (
input clk,
// data interface
input [CHANNEL_WIDTH*DATA_PATH_WIDTH-1:0] data,
// pn out of sync and error
output pn_oos,
output pn_err,
// processor interface PN9 (0x0), PN23 (0x1)
input [3:0] pn_seq_sel
);
localparam DW = DATA_PATH_WIDTH * CHANNEL_WIDTH - 1;
// internal registers
reg [DW:0] pn_data_pn = 'd0;
// internal signals
wire [DW:0] pn_data_pn_s;
wire [DW:0] pn_data_in_s;
wire [DW:0] pn23;
wire [DW+23:0] full_state_pn23;
wire [DW:0] pn9;
wire [DW+9:0] full_state_pn9;
// pn sequence select
assign pn_data_pn_s = (pn_oos == 1'b1) ? pn_data_in_s : pn_data_pn;
wire tc = TWOS_COMPLEMENT ? 1'b1 : 1'b0;
generate
genvar i;
for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin : g_pn_swizzle
localparam src_lsb = i * CHANNEL_WIDTH;
localparam src_msb = src_lsb + CHANNEL_WIDTH - 1;
localparam dst_lsb = (DATA_PATH_WIDTH - i - 1) * CHANNEL_WIDTH;
localparam dst_msb = dst_lsb + CHANNEL_WIDTH - 1;
assign pn_data_in_s[dst_msb] = tc ^ data[src_msb];
assign pn_data_in_s[dst_msb-1:dst_lsb] = data[src_msb-1:src_lsb];
end
endgenerate
// PN23 x^23 + x^18 + 1
assign pn23 = full_state_pn23[23+:DW+1] ^ full_state_pn23[18+:DW+1];
assign full_state_pn23 = {pn_data_pn_s[22:0], pn23};
// PN9 x^9 + x^5 + 1
assign pn9 = full_state_pn9[9+:DW+1] ^ full_state_pn9[5+:DW+1];
assign full_state_pn9 = {pn_data_pn_s[8:0], pn9};
always @(posedge clk) begin
if (pn_seq_sel == 4'd0) begin
pn_data_pn <= pn9;
end else begin
pn_data_pn <= pn23;
end
end
// pn oos & pn err
ad_pnmon #(
.DATA_WIDTH(DW + 1)
) i_pnmon (
.adc_clk(clk),
.adc_valid_in(1'b1),
.adc_data_in(pn_data_in_s),
.adc_data_pn(pn_data_pn),
.adc_pn_oos(pn_oos),
.adc_pn_err(pn_err)
);
endmodule
| 7.639234 |
module ad_ip_jesd204_tpl_adc_channel #(
parameter CONVERTER_RESOLUTION = 14,
parameter DATA_PATH_WIDTH = 2,
parameter TWOS_COMPLEMENT = 1,
parameter BITS_PER_SAMPLE = 16
) (
input clk,
input [CONVERTER_RESOLUTION*DATA_PATH_WIDTH-1:0] raw_data,
output [BITS_PER_SAMPLE*DATA_PATH_WIDTH-1:0] fmt_data,
// Configuration and status
input dfmt_enable,
input dfmt_type,
input dfmt_sign_extend,
input [3:0] pn_seq_sel,
output pn_oos,
output pn_err
);
localparam OCTETS_PER_SAMPLE = BITS_PER_SAMPLE / 8;
// instantiations
ad_ip_jesd204_tpl_adc_pnmon #(
.CONVERTER_RESOLUTION(CONVERTER_RESOLUTION),
.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
.TWOS_COMPLEMENT(TWOS_COMPLEMENT)
) i_pnmon (
.clk (clk),
.data(raw_data),
.pn_seq_sel(pn_seq_sel),
.pn_oos(pn_oos),
.pn_err(pn_err)
);
generate
genvar n;
for (n = 0; n < DATA_PATH_WIDTH; n = n + 1) begin : g_datafmt
ad_datafmt #(
.DATA_WIDTH(CONVERTER_RESOLUTION),
.OCTETS_PER_SAMPLE(OCTETS_PER_SAMPLE)
) i_ad_datafmt (
.clk(clk),
.valid(1'b1),
.data(raw_data[n*CONVERTER_RESOLUTION+:CONVERTER_RESOLUTION]),
.valid_out(),
.data_out(fmt_data[n*BITS_PER_SAMPLE+:BITS_PER_SAMPLE]),
.dfmt_enable(dfmt_enable),
.dfmt_type(dfmt_type),
.dfmt_se(dfmt_sign_extend)
);
end
endgenerate
endmodule
| 7.639234 |
module ad_ip_jesd204_tpl_adc_core #(
parameter NUM_LANES = 1,
parameter NUM_CHANNELS = 1,
parameter SAMPLES_PER_FRAME = 1,
parameter CONVERTER_RESOLUTION = 14,
parameter BITS_PER_SAMPLE = 16,
parameter OCTETS_PER_BEAT = 4,
parameter DATA_PATH_WIDTH = 1,
parameter LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8,
parameter DMA_DATA_WIDTH = DATA_PATH_WIDTH * BITS_PER_SAMPLE * NUM_CHANNELS,
parameter TWOS_COMPLEMENT = 1
) (
input clk,
input [NUM_CHANNELS-1:0] dfmt_enable,
input [NUM_CHANNELS-1:0] dfmt_sign_extend,
input [NUM_CHANNELS-1:0] dfmt_type,
input [NUM_CHANNELS*4-1:0] pn_seq_sel,
output [ NUM_CHANNELS-1:0] pn_err,
output [ NUM_CHANNELS-1:0] pn_oos,
output [ NUM_CHANNELS-1:0] adc_valid,
output [DMA_DATA_WIDTH-1:0] adc_data,
input adc_sync,
output adc_sync_status,
input adc_sync_in,
output adc_rst_sync,
input link_valid,
output link_ready,
input [OCTETS_PER_BEAT-1:0] link_sof,
input [LINK_DATA_WIDTH-1:0] link_data
);
// Raw and formatted channel data widths
localparam CDW_RAW = CONVERTER_RESOLUTION * DATA_PATH_WIDTH;
localparam ADC_DATA_WIDTH = CDW_RAW * NUM_CHANNELS;
localparam CDW_FMT = BITS_PER_SAMPLE * DATA_PATH_WIDTH;
wire [ADC_DATA_WIDTH-1:0] raw_data_s;
reg adc_sync_armed = 1'b0;
reg adc_sync_in_d1 = 1'b0;
reg adc_sync_d1 = 1'b0;
assign link_ready = 1'b1;
assign adc_valid = {NUM_CHANNELS{link_valid}};
assign adc_sync_status = adc_sync_armed;
assign adc_rst_sync = adc_sync_armed;
always @(posedge clk) begin
adc_sync_in_d1 <= adc_sync_in;
adc_sync_d1 <= adc_sync;
if ((~adc_sync_d1 & adc_sync) == 1'b1) begin
adc_sync_armed <= ~adc_sync_armed;
end else if ((~adc_sync_in_d1 & adc_sync_in) == 1'b1) begin
adc_sync_armed <= 1'b0;
end
end
// synchronization logic
ad_ip_jesd204_tpl_adc_deframer #(
.NUM_LANES(NUM_LANES),
.NUM_CHANNELS(NUM_CHANNELS),
.BITS_PER_SAMPLE(BITS_PER_SAMPLE),
.CONVERTER_RESOLUTION(CONVERTER_RESOLUTION),
.SAMPLES_PER_FRAME(SAMPLES_PER_FRAME),
.OCTETS_PER_BEAT(OCTETS_PER_BEAT),
.LINK_DATA_WIDTH(LINK_DATA_WIDTH),
.ADC_DATA_WIDTH(ADC_DATA_WIDTH)
) i_deframer (
.clk(clk),
.link_sof(link_sof),
.link_data(link_data),
.adc_data(raw_data_s)
);
generate
genvar i;
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin : g_channel
ad_ip_jesd204_tpl_adc_channel #(
.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
.CONVERTER_RESOLUTION(CONVERTER_RESOLUTION),
.TWOS_COMPLEMENT(TWOS_COMPLEMENT),
.BITS_PER_SAMPLE(BITS_PER_SAMPLE)
) i_channel (
.clk(clk),
.raw_data(raw_data_s[CDW_RAW*i+:CDW_RAW]),
.fmt_data(adc_data[CDW_FMT*i+:CDW_FMT]),
.dfmt_enable(dfmt_enable[i]),
.dfmt_sign_extend(dfmt_sign_extend[i]),
.dfmt_type(dfmt_type[i]),
.pn_seq_sel(pn_seq_sel[i*4+:4]),
.pn_err(pn_err[i]),
.pn_oos(pn_oos[i])
);
end
endgenerate
endmodule
| 7.639234 |
module ad_ip_jesd204_tpl_adc_deframer #(
parameter NUM_LANES = 1,
parameter NUM_CHANNELS = 4,
parameter BITS_PER_SAMPLE = 16,
parameter CONVERTER_RESOLUTION = 14,
parameter SAMPLES_PER_FRAME = 1,
parameter OCTETS_PER_BEAT = 8,
parameter LINK_DATA_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES,
parameter ADC_DATA_WIDTH = LINK_DATA_WIDTH * CONVERTER_RESOLUTION / BITS_PER_SAMPLE
) (
// jesd interface
// clk is (line-rate/40)
input clk,
input [OCTETS_PER_BEAT-1:0] link_sof,
input [LINK_DATA_WIDTH-1:0] link_data,
// adc data output
output [ADC_DATA_WIDTH-1:0] adc_data
);
localparam SAMPLES_PER_BEAT = ADC_DATA_WIDTH / CONVERTER_RESOLUTION;
localparam BITS_PER_CHANNEL_PER_FRAME = BITS_PER_SAMPLE * SAMPLES_PER_FRAME;
localparam BITS_PER_LANE_PER_FRAME = BITS_PER_CHANNEL_PER_FRAME * NUM_CHANNELS / NUM_LANES;
localparam FRAMES_PER_BEAT = OCTETS_PER_BEAT * 8 / BITS_PER_LANE_PER_FRAME;
wire [LINK_DATA_WIDTH-1:0] link_data_s;
wire [LINK_DATA_WIDTH-1:0] link_data_msb_s;
wire [LINK_DATA_WIDTH-1:0] frame_data_s;
wire [LINK_DATA_WIDTH-1:0] adc_data_msb;
// data multiplex
genvar i;
genvar j;
generate
/* Reorder octets MSB first */
for (i = 0; i < LINK_DATA_WIDTH; i = i + 8) begin : g_adc_data
assign link_data_msb_s[i+:8] = link_data_s[LINK_DATA_WIDTH-1-i-:8];
end
/* Slice lanes into frames */
ad_perfect_shuffle #(
.NUM_GROUPS(NUM_LANES),
.WORDS_PER_GROUP(FRAMES_PER_BEAT),
.WORD_WIDTH(BITS_PER_LANE_PER_FRAME)
) i_lanes_to_frames (
.data_in (link_data_msb_s),
.data_out(frame_data_s)
);
/* Slice frames into channels */
ad_perfect_shuffle #(
.NUM_GROUPS(FRAMES_PER_BEAT),
.WORDS_PER_GROUP(NUM_CHANNELS),
.WORD_WIDTH(BITS_PER_CHANNEL_PER_FRAME)
) i_frames_to_channels (
.data_in (frame_data_s),
.data_out(adc_data_msb)
);
/* Reorder samples LSB first and remove tail bits */
for (i = 0; i < SAMPLES_PER_BEAT; i = i + 1) begin : g_dac_data_msb
localparam src_w = BITS_PER_SAMPLE;
localparam dst_w = CONVERTER_RESOLUTION;
localparam src_msb = LINK_DATA_WIDTH - 1 - i * src_w;
localparam dst_lsb = i * dst_w;
assign adc_data[dst_lsb+:dst_w] = adc_data_msb[src_msb-:dst_w];
end
endgenerate
// frame-alignment
generate
genvar n;
for (n = 0; n < NUM_LANES; n = n + 1) begin : g_xcvr_if
localparam DW = OCTETS_PER_BEAT * 8;
ad_xcvr_rx_if #(
.OCTETS_PER_BEAT(OCTETS_PER_BEAT)
) i_xcvr_if (
.rx_clk(clk),
.rx_ip_sof(link_sof),
.rx_ip_data(link_data[n*DW+:DW]),
.rx_sof(),
.rx_data(link_data_s[n*DW+:DW])
);
end
endgenerate
endmodule
| 7.639234 |
module ad_ip_jesd204_tpl_adc_pnmon #(
parameter CONVERTER_RESOLUTION = 16,
parameter DATA_PATH_WIDTH = 1,
parameter TWOS_COMPLEMENT = 1
) (
input clk,
// data interface
input [CONVERTER_RESOLUTION*DATA_PATH_WIDTH-1:0] data,
// pn out of sync and error
output pn_oos,
output pn_err,
// processor interface PN9 (0x0), PN23 (0x1)
input [3:0] pn_seq_sel
);
localparam DW = DATA_PATH_WIDTH * CONVERTER_RESOLUTION - 1;
// Max width of largest PN and data width
localparam PN_W = DW > 22 ? DW : 22;
// internal registers
reg [PN_W:0] pn_data_pn = 'd0;
// internal signals
wire [PN_W:0] pn_data_pn_s;
wire [DW:0] pn_data_in_s;
wire [PN_W:0] pn_data_init;
wire [DW:0] pn23;
wire [DW+23:0] full_state_pn23;
wire [DW:0] pn9;
wire [DW+9:0] full_state_pn9;
// pn sequence select
generate
if (PN_W > DW) begin
reg [PN_W-DW-1:0] pn_data_in_d = 'd0;
always @(posedge clk) begin
pn_data_in_d <= pn_data_in_s[PN_W-DW-1:0];
end
assign pn_data_init = {pn_data_in_d, pn_data_in_s};
end else begin
assign pn_data_init = pn_data_in_s;
end
endgenerate
assign pn_data_pn_s = (pn_oos == 1'b1) ? pn_data_init : pn_data_pn;
wire tc = TWOS_COMPLEMENT ? 1'b1 : 1'b0;
generate
genvar i;
for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin : g_pn_swizzle
localparam src_lsb = i * CONVERTER_RESOLUTION;
localparam src_msb = src_lsb + CONVERTER_RESOLUTION - 1;
localparam dst_lsb = (DATA_PATH_WIDTH - i - 1) * CONVERTER_RESOLUTION;
localparam dst_msb = dst_lsb + CONVERTER_RESOLUTION - 1;
assign pn_data_in_s[dst_msb] = tc ^ data[src_msb];
assign pn_data_in_s[dst_msb-1:dst_lsb] = data[src_msb-1:src_lsb];
end
endgenerate
// PN23 x^23 + x^18 + 1
assign pn23 = full_state_pn23[23+:DW+1] ^ full_state_pn23[18+:DW+1];
assign full_state_pn23 = {pn_data_pn_s[22:0], pn23};
// PN9 x^9 + x^5 + 1
assign pn9 = full_state_pn9[9+:DW+1] ^ full_state_pn9[5+:DW+1];
assign full_state_pn9 = {pn_data_pn_s[8:0], pn9};
always @(posedge clk) begin
if (pn_seq_sel == 4'd0) begin
pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0], pn9} : pn9;
end else begin
pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0], pn23} : pn23;
end
end
// pn oos & pn err
ad_pnmon #(
.DATA_WIDTH(DW + 1)
) i_pnmon (
.adc_clk(clk),
.adc_valid_in(1'b1),
.adc_data_in(pn_data_in_s),
.adc_data_pn(pn_data_pn[DW:0]),
.adc_pn_oos(pn_oos),
.adc_pn_err(pn_err)
);
endmodule
| 7.639234 |
module ad_ip_jesd204_tpl_dac_channel #(
parameter DATAPATH_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1,
parameter DATA_PATH_WIDTH = 4,
parameter CONVERTER_RESOLUTION = 16,
parameter BITS_PER_SAMPLE = 16,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DDS_CORDIC_PHASE_DW = 16,
parameter Q_OR_I_N = 0
) (
// dac interface
input clk,
input [DATA_PATH_WIDTH*BITS_PER_SAMPLE-1:0] dma_data,
output reg [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] dac_data = 'h00,
// PN data
input [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn7_data,
input [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn15_data,
// Configuration
input dac_data_sync,
input dac_dds_format,
input [3:0] dac_data_sel,
input [15:0] dac_dds_scale_0,
input [15:0] dac_dds_init_0,
input [15:0] dac_dds_incr_0,
input [15:0] dac_dds_scale_1,
input [15:0] dac_dds_init_1,
input [15:0] dac_dds_incr_1,
input [15:0] dac_pat_data_0,
input [15:0] dac_pat_data_1,
input dac_iqcor_enb,
input [15:0] dac_iqcor_coeff_1,
input [15:0] dac_iqcor_coeff_2,
input [DATA_PATH_WIDTH*BITS_PER_SAMPLE-1:0] dac_iqcor_data_in,
output reg dac_enable = 1'b0
);
localparam CR = CONVERTER_RESOLUTION;
localparam CHANNEL_DATA_WIDTH = DATA_PATH_WIDTH * CR;
// internal signals
wire [CHANNEL_DATA_WIDTH-1:0] dac_dds_data_s;
wire [CHANNEL_DATA_WIDTH-1:0] dac_dma_data_s;
wire [CHANNEL_DATA_WIDTH-1:0] dac_pat_data_s;
wire [CHANNEL_DATA_WIDTH-1:0] dac_iqcor_data_s;
generate
if (DATA_PATH_WIDTH > 1) begin
assign dac_pat_data_s = {DATA_PATH_WIDTH / 2{dac_pat_data_1[0+:CR], dac_pat_data_0[0+:CR]}};
end else begin
reg dac_pat_data_sel = 1'b0;
always @(posedge clk) begin
if (dac_data_sync == 1'b1) begin
dac_pat_data_sel <= 1'b0;
end else begin
dac_pat_data_sel <= ~dac_pat_data_sel;
end
end
assign dac_pat_data_s = dac_pat_data_sel == 1'b0 ?
dac_pat_data_0[0+:CR] : dac_pat_data_1[0+:CR];
end
genvar i;
/* Data is expected to be LSB aligned, drop unused MSBs */
for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin : g_dac_dma_data
assign dac_dma_data_s[CR*i+:CR] = dma_data[BITS_PER_SAMPLE*i+:CR];
end
endgenerate
ad_iqcor #(
.Q_OR_I_N(Q_OR_I_N),
.DISABLE(IQCORRECTION_DISABLE),
.CR(CR),
.DPW(DATA_PATH_WIDTH)
) i_ad_iqcor (
.clk(clk),
.valid(1'b1),
.data_in(dac_dma_data_s),
.data_iq(dac_iqcor_data_in),
.valid_out(),
.data_out(dac_iqcor_data_s),
.iqcor_enable(dac_iqcor_enb),
.iqcor_coeff_1(dac_iqcor_coeff_1),
.iqcor_coeff_2(dac_iqcor_coeff_2)
);
// dac data select
always @(posedge clk) begin
dac_enable <= (dac_data_sel == 4'h2) ? 1'b1 : 1'b0;
case (dac_data_sel)
4'h7: dac_data <= pn15_data;
4'h6: dac_data <= pn7_data;
4'h5: dac_data <= ~pn15_data;
4'h4: dac_data <= ~pn7_data;
4'h3: dac_data <= 'h00;
4'h2: dac_data <= dac_iqcor_data_s;
4'h1: dac_data <= dac_pat_data_s;
default: dac_data <= dac_dds_data_s;
endcase
end
// dds
ad_dds #(
.DISABLE(DATAPATH_DISABLE),
.DDS_DW(CONVERTER_RESOLUTION),
.PHASE_DW(16),
.DDS_TYPE(DDS_TYPE),
.CORDIC_DW(DDS_CORDIC_DW),
.CORDIC_PHASE_DW(DDS_CORDIC_PHASE_DW),
.CLK_RATIO(DATA_PATH_WIDTH)
) i_dds (
.clk(clk),
.dac_dds_format(dac_dds_format),
.dac_data_sync(dac_data_sync),
.dac_valid(1'b1),
.tone_1_scale(dac_dds_scale_0),
.tone_2_scale(dac_dds_scale_1),
.tone_1_init_offset(dac_dds_init_0),
.tone_2_init_offset(dac_dds_init_1),
.tone_1_freq_word(dac_dds_incr_0),
.tone_2_freq_word(dac_dds_incr_1),
.dac_dds_data(dac_dds_data_s)
);
endmodule
| 7.639234 |
module ad_ip_jesd204_tpl_dac_pn #(
parameter DATA_PATH_WIDTH = 4,
parameter CONVERTER_RESOLUTION = 16
) (
input clk,
input reset,
output [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn7_data,
output [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn15_data
);
localparam CR = CONVERTER_RESOLUTION;
localparam DW = DATA_PATH_WIDTH * CR - 1;
/* We need at least enough bits to store the PN state */
localparam PN7_W = DW > 6 ? DW : 6;
localparam PN15_W = DW > 14 ? DW : 14;
reg [PN7_W:0] pn7_state = {PN7_W + 1{1'b1}};
reg [PN15_W:0] pn15_state = {PN15_W + 1{1'b1}};
wire [DW:0] pn7;
wire [DW+7:0] pn7_full_state;
wire [PN7_W:0] pn7_reset;
wire [DW:0] pn15;
wire [DW+15:0] pn15_full_state;
wire [PN15_W:0] pn15_reset;
/* PN7 x^7 + x^6 + 1 */
assign pn7 = pn7_full_state[7+:DW+1] ^ pn7_full_state[6+:DW+1];
assign pn7_full_state = {pn7_state[6:0], pn7};
/* PN15 x^15 + x^14 + 1 */
assign pn15 = pn15_full_state[15+:DW+1] ^ pn15_full_state[14+:DW+1];
assign pn15_full_state = {pn15_state[14:0], pn15};
assign pn7_reset[PN7_W-:7] = {7{1'b1}};
assign pn15_reset[PN15_W-:15] = {15{1'b1}};
generate
if (PN7_W >= 7) begin
assign pn7_reset[PN7_W-7:0] = pn7_reset[PN7_W:7] ^ pn7_reset[PN7_W-1:6];
end
if (PN15_W >= 15) begin
assign pn15_reset[PN15_W-15:0] = pn15_reset[PN15_W:15] ^ pn15_reset[PN15_W-1:14];
end
endgenerate
always @(posedge clk) begin
if (reset == 1'b1) begin
pn7_state <= pn7_reset;
pn15_state <= pn15_reset;
end else begin
pn7_state <= pn7_full_state[PN7_W:0];
pn15_state <= pn15_full_state[PN15_W:0];
end
end
generate
/*
* The first sample contains the first MSB of the PN sequence, but the first
* sample is also in the LSB of the output data. So extract data at the MSB
* sample of the PN state and put it into the LSB sample of the output data.
*/
genvar i;
for (i = 0; i <= DW; i = i + CR) begin : g_pn_swizzle
assign pn7_data[i+:CR] = pn7_state[PN7_W-i-:CR];
assign pn15_data[i+:CR] = pn15_state[PN15_W-i-:CR];
end
endgenerate
endmodule
| 7.639234 |
module ad_jesd_align (
// jesd interface
rx_clk,
rx_ip_sof,
rx_ip_data,
rx_sof,
rx_data
);
// jesd interface
input rx_clk;
input [3:0] rx_ip_sof;
input [31:0] rx_ip_data;
// aligned data
output rx_sof;
output [31:0] rx_data;
// internal registers
reg [31:0] rx_ip_data_d = 'd0;
reg [ 3:0] rx_ip_sof_hold = 'd0;
reg rx_sof = 'd0;
reg rx_ip_sof_d = 'd0;
reg [31:0] rx_data = 'd0;
// dword may contain more than one frame per clock
always @(posedge rx_clk) begin
rx_ip_data_d <= rx_ip_data;
rx_ip_sof_d <= rx_ip_sof;
if (rx_ip_sof != 4'h0) begin
rx_ip_sof_hold <= rx_ip_sof;
end
rx_sof <= |rx_ip_sof_d;
if (rx_ip_sof_hold[0] == 1'b1) begin
rx_data <= rx_ip_data;
end else if (rx_ip_sof_hold[1] == 1'b1) begin
rx_data <= {rx_ip_data[7:0], rx_ip_data_d[31:8]};
end else if (rx_ip_sof_hold[2] == 1'b1) begin
rx_data <= {rx_ip_data[15:0], rx_ip_data_d[31:16]};
end else if (rx_ip_sof_hold[3] == 1'b1) begin
rx_data <= {rx_ip_data[23:0], rx_ip_data_d[31:24]};
end else begin
rx_data <= 32'd0;
end
end
endmodule
| 7.883127 |
module ad_lvds_out (
// data interface
tx_clk,
tx_data_p,
tx_data_n,
tx_data_out_p,
tx_data_out_n,
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
// delay-cntrl interface
delay_clk,
delay_rst,
delay_locked
);
// parameters
parameter DEVICE_TYPE = 0;
parameter SINGLE_ENDED = 0;
parameter IODELAY_ENABLE = 0;
parameter IODELAY_CTRL = 0;
parameter IODELAY_GROUP = "dev_if_delay_group";
localparam SERIES7 = 0;
localparam VIRTEX6 = 1;
// data interface
input tx_clk;
input tx_data_p;
input tx_data_n;
output tx_data_out_p;
output tx_data_out_n;
// delay-data interface
input up_clk;
input up_dld;
input [4:0] up_dwdata;
output [4:0] up_drdata;
// delay-cntrl interface
input delay_clk;
input delay_rst;
output delay_locked;
// internal signals
wire tx_data_oddr_s;
wire tx_data_odelay_s;
// delay controller
generate
if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7) && (IODELAY_CTRL == 1)) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYCTRL i_delay_ctrl (
.RST(delay_rst),
.REFCLK(delay_clk),
.RDY(delay_locked)
);
end else begin
assign delay_locked = 1'b1;
end
endgenerate
// transmit data interface, oddr -> odelay -> obuf
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.SRTYPE("ASYNC")
) i_tx_data_oddr (
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.C (tx_clk),
.D1(tx_data_p),
.D2(tx_data_n),
.Q (tx_data_oddr_s)
);
generate
if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7)) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
ODELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("ODATAIN"),
.HIGH_PERFORMANCE_MODE("FALSE"),
.ODELAY_TYPE("VAR_LOAD"),
.ODELAY_VALUE(0),
.REFCLK_FREQUENCY(200.0),
.PIPE_SEL("FALSE"),
.SIGNAL_PATTERN("DATA")
) i_tx_data_odelay (
.CE(1'b0),
.CLKIN(1'b0),
.INC(1'b0),
.LDPIPEEN(1'b0),
.CINVCTRL(1'b0),
.REGRST(1'b0),
.C(up_clk),
.ODATAIN(tx_data_oddr_s),
.DATAOUT(tx_data_odelay_s),
.LD(up_dld),
.CNTVALUEIN(up_dwdata),
.CNTVALUEOUT(up_drdata)
);
end else begin
assign up_drdata = 5'd0;
assign tx_data_odelay_s = tx_data_oddr_s;
end
endgenerate
generate
if (SINGLE_ENDED == 1) begin
assign tx_data_out_n = 1'b0;
OBUF i_tx_data_obuf (
.I(tx_data_odelay_s),
.O(tx_data_out_p)
);
end else begin
OBUFDS i_tx_data_obuf (
.I (tx_data_odelay_s),
.O (tx_data_out_p),
.OB(tx_data_out_n)
);
end
endgenerate
endmodule
| 7.421716 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_mem #(
parameter DATA_WIDTH = 16,
parameter ADDRESS_WIDTH = 5) (
input clka,
input wea,
input [(ADDRESS_WIDTH-1):0] addra,
input [(DATA_WIDTH-1):0] dina,
input clkb,
input reb,
input [(ADDRESS_WIDTH-1):0] addrb,
output reg [(DATA_WIDTH-1):0] doutb);
(* ram_style = "block" *)
reg [(DATA_WIDTH-1):0] m_ram[0:((2**ADDRESS_WIDTH)-1)];
always @(posedge clka) begin
if (wea == 1'b1) begin
m_ram[addra] <= dina;
end
end
always @(posedge clkb) begin
if (reb == 1'b1) begin
doutb <= m_ram[addrb];
end
end
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_mem_dp_sc #(
parameter DATA_WIDTH = 16,
parameter ADDRESS_WIDTH = 5) (
input clk,
input rst,
input rea,
input wea,
input [(ADDRESS_WIDTH-1):0] addra,
input [(DATA_WIDTH-1):0] dina,
output reg [(DATA_WIDTH-1):0] douta,
input reb,
input web,
input [(ADDRESS_WIDTH-1):0] addrb,
input [(DATA_WIDTH-1):0] dinb,
output reg [(DATA_WIDTH-1):0] doutb);
(* ram_style = "block" *)
reg [(DATA_WIDTH-1):0] m_ram[0:((2**ADDRESS_WIDTH)-1)];
always @(posedge clk) begin
if (rst == 1'b1) begin
douta <= 0;
doutb <= 0;
end else begin
if (wea == 1'b1) begin
m_ram[addra] <= dina;
end
if (web == 1'b1) begin
m_ram[addrb] <= dinb;
end
if (rea == 1'b1) begin
douta <= m_ram[addra];
end
if (reb == 1'b1) begin
doutb <= m_ram[addrb];
end
end
end
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module ad_mul #(
parameter A_DATA_WIDTH = 17,
parameter B_DATA_WIDTH = 17,
parameter DELAY_DATA_WIDTH = 16) (
// data_p = data_a * data_b;
input clk,
input [ A_DATA_WIDTH-1:0] data_a,
input [ B_DATA_WIDTH-1:0] data_b,
output [A_DATA_WIDTH + B_DATA_WIDTH-1:0] data_p,
// delay interface
input [(DELAY_DATA_WIDTH-1):0] ddata_in,
output reg [(DELAY_DATA_WIDTH-1):0] ddata_out);
// internal registers
reg [(DELAY_DATA_WIDTH-1):0] p1_ddata = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] p2_ddata = 'd0;
// a/b reg, m-reg, p-reg delay match
always @(posedge clk) begin
p1_ddata <= ddata_in;
p2_ddata <= p1_ddata;
ddata_out <= p2_ddata;
end
MULT_MACRO #(
.LATENCY (3),
.WIDTH_A (A_DATA_WIDTH),
.WIDTH_B (B_DATA_WIDTH))
i_mult_macro (
.CE (1'b1),
.RST (1'b0),
.CLK (clk),
.A (data_a),
.B (data_b),
.P (data_p));
endmodule
| 8.180735 |
module ad_mul_u16 (
// data_p = data_a * data_b;
clk,
data_a,
data_b,
data_p,
// delay interface
ddata_in,
ddata_out
);
// delayed data bus width
parameter DELAY_DATA_WIDTH = 16;
localparam DW = DELAY_DATA_WIDTH - 1;
// data_p = data_a * data_b;
input clk;
input [15:0] data_a;
input [15:0] data_b;
output [31:0] data_p;
// delay interface
input [DW:0] ddata_in;
output [DW:0] ddata_out;
// internal registers
reg [DW:0] p1_ddata = 'd0;
reg [DW:0] p2_ddata = 'd0;
reg [DW:0] ddata_out = 'd0;
// internal signals
wire [33:0] data_p_s;
// a/b reg, m-reg, p-reg delay match
always @(posedge clk) begin
p1_ddata <= ddata_in;
p2_ddata <= p1_ddata;
ddata_out <= p2_ddata;
end
assign data_p = data_p_s[31:0];
MULT_MACRO #(
.LATENCY(3),
.A_DATA_WIDTH(17),
.B_DATA_WIDTH(17)
) i_mult_macro (
.CE (1'b1),
.RST(1'b0),
.CLK(clk),
.A ({1'b0, data_a}),
.B ({1'b0, data_b}),
.P (data_p_s)
);
endmodule
| 6.89365 |
module ad_mul_u16 (
// data_p = data_a * data_b;
clk,
data_a,
data_b,
data_p,
// delay interface
ddata_in,
ddata_out
);
// delayed data bus width
parameter DELAY_DATA_WIDTH = 16;
localparam DW = DELAY_DATA_WIDTH - 1;
// data_p = data_a * data_b;
input clk;
input [15:0] data_a;
input [15:0] data_b;
output [31:0] data_p;
// delay interface
input [DW:0] ddata_in;
output [DW:0] ddata_out;
// internal registers
reg [DW:0] p1_ddata = 'd0;
reg [DW:0] p2_ddata = 'd0;
reg [DW:0] ddata_out = 'd0;
// internal signals
// a/b reg, m-reg, p-reg delay match
always @(posedge clk) begin
p1_ddata <= ddata_in;
p2_ddata <= p1_ddata;
ddata_out <= p2_ddata;
end
lpm_mult i_mult_macro (
.clock(clk),
.dataa(data_a),
.datab(data_b),
.result(data_p),
.aclr(1'b0),
.clken(1'b1),
.sum(1'b0)
);
defparam lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5", lpm_mult_component.lpm_pipeline = 3,
lpm_mult_component.lpm_representation = "UNSIGNED", lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 16, lpm_mult_component.lpm_widthb = 16,
lpm_mult_component.lpm_widthp = 32;
endmodule
| 6.89365 |
module ad_mux (
input [31:0] data,
input [ 2:0] select,
output reg [ 3:0] out
);
always @(*)
case (select)
3'b000: out = data[3:0];
3'b001: out = data[7:4];
3'b010: out = data[11:8];
3'b011: out = data[15:12];
3'b100: out = data[19:16];
3'b101: out = data[23:20];
3'b110: out = data[27:24];
3'b111: out = data[31:28];
default: out = 4'b0000;
endcase
endmodule
| 8.666852 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_mux_core #(
parameter CH_W = 16,
parameter CH_CNT = 8,
parameter EN_REG = 0
) (
input clk,
input [CH_W*CH_CNT-1:0] data_in,
input [$clog2(CH_CNT)-1:0] ch_sel,
output [CH_W-1:0] data_out
);
wire [CH_W-1:0] data_out_loc;
assign data_out_loc = data_in >> CH_W*ch_sel;
generate if (EN_REG) begin
reg [CH_W-1:0] data_out_reg;
always @(posedge clk) begin
data_out_reg <= data_out_loc;
end
assign data_out = data_out_reg;
end else begin
assign data_out = data_out_loc;
end
endgenerate
endmodule
| 8.180735 |
module ad_mux_tb;
parameter VCD_FILE = "ad_mux_tb.vcd";
parameter CH_W = 16; // Width of input channel
parameter CH_CNT = 64; // Number of input channels
parameter REQ_MUX_SZ = 8; // Size of mux which acts as a building block
parameter EN_REG = 1; // Enable register at output of each mux
localparam MUX_SZ = CH_CNT < REQ_MUX_SZ ? CH_CNT : REQ_MUX_SZ;
localparam NUM_STAGES = $clog2(CH_CNT) / $clog2(MUX_SZ) + |($clog2(CH_CNT) % $clog2(MUX_SZ));
localparam DW = CH_W * CH_CNT;
`include "tb_base.v"
reg [CH_W*CH_CNT-1:0] data_in = 'h0;
reg [$clog2(CH_CNT)-1:0] ch_sel = 'h0;
wire [CH_W-1:0] data_out;
ad_mux #(
.CH_W(CH_W),
.CH_CNT(CH_CNT),
.REQ_MUX_SZ(REQ_MUX_SZ),
.EN_REG(EN_REG)
) DUT (
.clk(clk),
.data_in(data_in),
.ch_sel(ch_sel),
.data_out(data_out)
);
wire [CH_W-1:0] ref_data;
generate
if (EN_REG) begin
integer ii;
reg [CH_W*CH_CNT-1:0] mux_pln[1:NUM_STAGES];
always @(posedge clk) begin
mux_pln[1] <= data_in >> ch_sel * CH_W;
for (ii = 2; ii <= NUM_STAGES; ii = ii + 1) begin
mux_pln[ii] <= mux_pln[ii-1];
end
end
assign ref_data = mux_pln[NUM_STAGES];
end else begin
assign ref_data = data_in >> ch_sel * CH_W;
end
endgenerate
integer i;
initial begin
for (i = 0; i < CH_W * CH_CNT / 8; i = i + 1) begin
data_in[i*8+:8] = i[7:0];
end
for (i = 0; i < CH_CNT; i = i + 1) begin
@(posedge clk);
ch_sel <= ch_sel + 1;
end
end
wire mismatch;
assign mismatch = ref_data !== data_out;
always @(posedge clk) begin
if (mismatch) begin
failed <= 1'b1;
end
end
endmodule
| 7.175789 |
module ad_perfect_shuffle #(
parameter NUM_GROUPS = 2,
parameter WORDS_PER_GROUP = 2,
parameter WORD_WIDTH = 8
) (
input [NUM_GROUPS*WORDS_PER_GROUP*WORD_WIDTH-1:0] data_in,
output [NUM_GROUPS*WORDS_PER_GROUP*WORD_WIDTH-1:0] data_out
);
/*
* Performs the perfect shuffle operation.
*
* The perfect shuffle splits the input vector into NUM_GROUPS groups and then
* each group in WORDS_PER_GROUP. The output vector consists of WORDS_PER_GROUP
* groups and each group has NUM_GROUPS words. The data is remapped, so that
* the i-th word of the j-th word in the output vector is the j-th word of the
* i-th group of the input vector.
* The inverse operation of the perfect shuffle is the perfect shuffle with
* both parameters swapped.
* I.e. [perfect_suffle B A [perfect_shuffle A B data]] == data
*
* Examples:
* NUM_GROUPS = 2, WORDS_PER_GROUP = 4
* [A B C D a b c d] => [A a B b C c D d]
* NUM_GROUPS = 4, WORDS_PER_GROUP = 2
* [A a B b C c D d] => [A B C D a b c d]
* NUM_GROUPS = 3, WORDS_PER_GROUP = 2
* [A B a b 1 2] => [A a 1 B b 2]
*/
generate
genvar i;
genvar j;
for (i = 0; i < NUM_GROUPS; i = i + 1) begin : shuffle_outer
for (j = 0; j < WORDS_PER_GROUP; j = j + 1) begin : shuffle_inner
localparam src_lsb = (j + i * WORDS_PER_GROUP) * WORD_WIDTH;
localparam dst_lsb = (i + j * NUM_GROUPS) * WORD_WIDTH;
assign data_out[dst_lsb+:WORD_WIDTH] = data_in[src_lsb+:WORD_WIDTH];
end
end
endgenerate
endmodule
| 6.969236 |
module ad_pngen #(
// PN7 x^7 + x^6 + 1
parameter POL_MASK = 32'b0000_0000_0000_0000_0000_0000_1100_0000,
parameter POL_W = 7,
// Number of output bits at every clock cycle
parameter DW = 16
) (
input clk,
input reset,
input clk_en,
// Output stream
output [DW-1:0] pn_data_out, // MSB has the oldest value,
// LSB has the latest value
// Input stream to synchronize to (Optional)
input pn_init,
input [DW-1:0] pn_data_in
);
/* We need at least enough bits to store the PN state */
localparam PN_W = DW > POL_W ? DW : POL_W;
reg [PN_W-1:0] pn_state = {PN_W{1'b1}};
wire [DW-1:0] pn;
wire [DW+POL_W-1:0] pn_full_state;
wire [PN_W-1:0] pn_reset;
wire [PN_W-1:0] pn_state_;
wire [PN_W-1:0] pn_init_data;
// pn init data selection
generate
if (PN_W > DW) begin
reg [PN_W-DW-1:0] pn_data_in_d = 'd0;
always @(posedge clk) begin
pn_data_in_d <= {pn_data_in_d, pn_data_in};
end
assign pn_init_data = {pn_data_in_d, pn_data_in};
end else begin
assign pn_init_data = pn_data_in;
end
endgenerate
// PRBS logic
assign pn_state_ = pn_init ? pn_init_data : pn_state;
generate
genvar i;
for (i = 0; i < DW; i = i + 1) begin : pn_loop
assign pn[i] = ^(pn_full_state[i+:POL_W+1] & POL_MASK);
end
endgenerate
assign pn_full_state = {pn_state_[POL_W-1 : 0], pn};
// Reset value logic
assign pn_reset[PN_W-1-:POL_W] = {POL_W{1'b1}};
generate
genvar j;
for (j = 0; j < PN_W - POL_W; j = j + 1) begin : pn_reset_loop
assign pn_reset[j] = ^(pn_reset[j+:POL_W+1] & POL_MASK);
end
endgenerate
always @(posedge clk) begin
if (reset == 1'b1) begin
pn_state <= pn_reset;
end else if (clk_en) begin
pn_state <= pn_full_state[PN_W-1 : 0];
end
end
assign pn_data_out = pn_state[PN_W-1-:DW];
endmodule
| 7.340169 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_rst (
// clock reset
input rst_async,
input clk,
output rstn,
output reg rst);
// internal registers
reg rst_async_d1 = 1'd1;
reg rst_async_d2 = 1'd1;
reg rst_sync = 1'd1;
reg rst_sync_d = 1'd1;
// simple reset synchronizer
always @(posedge clk or posedge rst_async) begin
if (rst_async) begin
rst_async_d1 <= 1'b1;
rst_async_d2 <= 1'b1;
rst_sync <= 1'b1;
end else begin
rst_async_d1 <= 1'b0;
rst_async_d2 <= rst_async_d1;
rst_sync <= rst_async_d2;
end
end
// two-stage synchronizer to prevent metastability on the falling edge
always @(posedge clk) begin
rst_sync_d <= rst_sync;
rst <= rst_sync_d;
end
assign rstn = ~rst;
endmodule
| 8.180735 |
module AD_samp (
input sys_clk,
input rst_n,
input [11:0] AD9226_ChanA_data, //通道AB的12bit数字量
output AD9226_ChanA_clk, //通道AB的时钟
output ad_sync_done, //AD数据同步完成标志
output [11:0] ad_sync_data
);
/*
**100kHz计数,生成AD采样时钟(50kHz)
*/
reg [8:0] cnt_100k;
parameter CNT_100k = 500; //500*0.02us = 10us(100k)
always @(posedge sys_clk) begin
if (!rst_n) begin
cnt_100k <= 0;
end else if (cnt_100k == CNT_100k - 1) begin
cnt_100k <= 0;
end else begin
cnt_100k <= cnt_100k + 1'd1;
end
end
/*
**AD上升沿转换输入,下降沿同步数据
*/
reg chanA_clk_reg;
reg [11:0] chanA_data_reg;
reg ad_sync_done_reg; //AD数据同步完成标志
reg AD_state;
parameter POSEDGE = 0;
parameter NEGEDGE = 1;
assign ad_sync_data = chanA_data_reg;
assign AD9226_ChanA_clk = chanA_clk_reg;
assign ad_sync_done = ad_sync_done_reg;
always @(posedge sys_clk) begin
if (!rst_n) begin
chanA_clk_reg <= 0;
chanA_data_reg <= 0;
ad_sync_done_reg <= 0;
AD_state <= POSEDGE;
end else begin
if (cnt_100k == CNT_100k - 1) begin //计够了10us便更换state,最终adclk为50khz
case (AD_state)
POSEDGE: begin //adclk上升沿采集数据
chanA_clk_reg <= 1;
AD_state <= NEGEDGE;
ad_sync_done_reg <= 0;
end
NEGEDGE: begin //adclk下降沿同步数据
chanA_clk_reg <= 0;
AD_state <= POSEDGE;
ad_sync_done_reg <= 1;
chanA_data_reg <= AD9226_ChanA_data;
end
default: AD_state <= POSEDGE;
endcase
end else begin
ad_sync_done_reg <= 0;
end
end
end
endmodule
| 6.859101 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// Input must be RGB or CrYCb in that order, output is CrY/CbY
`timescale 1ns/100ps
module ad_ss_422to444 #(
parameter CR_CB_N = 0,
parameter DELAY_DATA_WIDTH = 16) (
// 422 inputs
input clk,
input s422_de,
input [DELAY_DATA_WIDTH-1:0] s422_sync,
input [ 15:0] s422_data,
// 444 outputs
output reg [DELAY_DATA_WIDTH-1:0] s444_sync,
output reg [ 23:0] s444_data);
localparam DW = DELAY_DATA_WIDTH - 1;
// internal registers
reg cr_cb_sel = 'd0;
reg s422_de_d = 'd0;
reg [DW:0] s422_sync_d = 'd0;
reg s422_de_2d = 'd0;
reg [7:0] s422_Y_d;
reg [7:0] s422_CbCr_d;
reg [7:0] s422_CbCr_2d;
reg [ 8:0] s422_CbCr_avg;
// internal wires
wire [ 7:0] s422_Y;
wire [ 7:0] s422_CbCr;
// Input format is
// [15:8] Cb/Cr
// [ 7:0] Y
//
// Output format is
// [23:15] Cr
// [16: 8] Y
// [ 7: 0] Cb
assign s422_Y = s422_data[7:0];
assign s422_CbCr = s422_data[15:8];
// first data on de assertion is cb (0x0), then cr (0x1).
// previous data is held when not current
always @(posedge clk) begin
if (s422_de_d == 1'b1) begin
cr_cb_sel <= ~cr_cb_sel;
end else begin
cr_cb_sel <= CR_CB_N;
end
end
// pipe line stages
always @(posedge clk) begin
s422_de_d <= s422_de;
s422_sync_d <= s422_sync;
s422_de_2d <= s422_de_d;
s422_Y_d <= s422_Y;
s422_CbCr_d <= s422_CbCr;
s422_CbCr_2d <= s422_CbCr_d;
end
// If both the left and the right sample are valid do the average, otherwise
// use the only valid.
always @(s422_de_2d, s422_de, s422_CbCr, s422_CbCr_2d)
begin
if (s422_de == 1'b1 && s422_de_2d)
s422_CbCr_avg <= s422_CbCr + s422_CbCr_2d;
else if (s422_de == 1'b1)
s422_CbCr_avg <= {s422_CbCr, 1'b0};
else
s422_CbCr_avg <= {s422_CbCr_2d, 1'b0};
end
// 444 outputs
always @(posedge clk) begin
s444_sync <= s422_sync_d;
s444_data[15:8] <= s422_Y_d;
if (cr_cb_sel) begin
s444_data[23:16] <= s422_CbCr_d;
s444_data[ 7: 0] <= s422_CbCr_avg[8:1];
end else begin
s444_data[23:16] <= s422_CbCr_avg[8:1];
s444_data[ 7: 0] <= s422_CbCr_d;
end
end
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// Input must be RGB or CrYCb in that order, output is CrY/CbY
`timescale 1ns/100ps
module ad_ss_444to422 #(
parameter CR_CB_N = 0,
parameter DELAY_DATA_WIDTH = 16) (
// 444 inputs
input clk,
input s444_de,
input [DELAY_DATA_WIDTH-1:0] s444_sync,
input [23:0] s444_data,
// 422 outputs
output reg [DELAY_DATA_WIDTH-1:0] s422_sync,
output reg [15:0] s422_data);
localparam DW = DELAY_DATA_WIDTH - 1;
// internal registers
reg s444_de_d = 'd0;
reg [DW:0] s444_sync_d = 'd0;
reg [23:0] s444_data_d = 'd0;
reg s444_de_2d = 'd0;
reg [DW:0] s444_sync_2d = 'd0;
reg [23:0] s444_data_2d = 'd0;
reg s444_de_3d = 'd0;
reg [DW:0] s444_sync_3d = 'd0;
reg [23:0] s444_data_3d = 'd0;
reg [ 7:0] cr = 'd0;
reg [ 7:0] cb = 'd0;
reg cr_cb_sel = 'd0;
// internal wires
wire [ 9:0] cr_s;
wire [ 9:0] cb_s;
// fill the data pipe lines, hold the last data on edges
always @(posedge clk) begin
s444_de_d <= s444_de;
s444_sync_d <= s444_sync;
if (s444_de == 1'b1) begin
s444_data_d <= s444_data;
end
s444_de_2d <= s444_de_d;
s444_sync_2d <= s444_sync_d;
if (s444_de_d == 1'b1) begin
s444_data_2d <= s444_data_d;
end
s444_de_3d <= s444_de_2d;
s444_sync_3d <= s444_sync_2d;
if (s444_de_2d == 1'b1) begin
s444_data_3d <= s444_data_2d;
end
end
// get the average 0.25*s(n-1) + 0.5*s(n) + 0.25*s(n+1)
assign cr_s = {2'd0, s444_data_d[23:16]} +
{2'd0, s444_data_3d[23:16]} +
{1'd0, s444_data_2d[23:16], 1'd0};
assign cb_s = {2'd0, s444_data_d[7:0]} +
{2'd0, s444_data_3d[7:0]} +
{1'd0, s444_data_2d[7:0], 1'd0};
always @(posedge clk) begin
cr <= cr_s[9:2];
cb <= cb_s[9:2];
if (s444_de_3d == 1'b1) begin
cr_cb_sel <= ~cr_cb_sel;
end else begin
cr_cb_sel <= CR_CB_N;
end
end
// 422 outputs
always @(posedge clk) begin
s422_sync <= s444_sync_3d;
if (s444_de_3d == 1'b0) begin
s422_data <= 'd0;
end else if (cr_cb_sel == 1'b1) begin
s422_data <= {cr, s444_data_3d[15:8]};
end else begin
s422_data <= {cb, s444_data_3d[15:8]};
end
end
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_sysref_gen (
input core_clk,
input sysref_en,
output reg sysref_out
);
// SYSREF period is multiple of core_clk, and has a duty cycle of 50%
// NOTE: if SYSREF always on (this is a JESD204 IP configuration),
// the period must be a correct multiple of the multiframe period
parameter SYSREF_PERIOD = 128;
localparam SYSREF_HALFPERIOD = SYSREF_PERIOD/2 - 1;
reg [ 7:0] counter;
reg sysref_en_m1;
reg sysref_en_m2;
reg sysref_en_int;
// bring the enable signal to JESD core clock domain
always @(posedge core_clk) begin
sysref_en_m1 <= sysref_en;
sysref_en_m2 <= sysref_en_m1;
sysref_en_int <= sysref_en_m2;
end
// free running counter for periodic SYSREF generation
always @(posedge core_clk) begin
if (sysref_en_int) begin
counter <= (counter < SYSREF_HALFPERIOD) ? counter + 1'b1 : 8'h0;
end else begin
counter <= 8'h0;
end
end
// generate SYSREF
always @(posedge core_clk) begin
if (sysref_en_int) begin
if (counter == SYSREF_HALFPERIOD) begin
sysref_out <= ~sysref_out;
end
end else begin
sysref_out <= 1'b0;
end
end
endmodule
| 8.180735 |
module ad_tdd_sync (
clk, // system clock (100 Mhz)
rstn,
sync // re-synchronization signal
);
localparam PULSE_CNTR_WIDTH = 7;
parameter TDD_SYNC_PERIOD = 100000000; // t_period * clk_freq - 1
input clk;
input rstn;
output sync;
// internal registers
reg [(PULSE_CNTR_WIDTH-1):0] pulse_counter = {PULSE_CNTR_WIDTH{1'b1}};
reg [ 31:0] sync_counter = 32'h0;
reg sync_pulse = 1'b0;
reg sync_period_eof = 1'b0;
assign sync = sync_pulse;
// a free running sync pulse generator
always @(posedge clk) begin
if (rstn == 1'b0) begin
sync_counter <= 32'h0;
sync_period_eof <= 1'b0;
end else begin
sync_counter <= (sync_counter < TDD_SYNC_PERIOD) ? (sync_counter + 1) : 32'b0;
sync_period_eof <= (sync_counter == (TDD_SYNC_PERIOD - 1)) ? 1'b1 : 1'b0;
end
end
// generate pulse with a specified width
always @(posedge clk) begin
if (rstn == 1'b0) begin
pulse_counter <= 0;
sync_pulse <= 0;
end else begin
pulse_counter <= (sync_pulse == 1'b1) ? pulse_counter + 1 : {PULSE_CNTR_WIDTH{1'h0}};
if (sync_period_eof == 1'b1) begin
sync_pulse <= 1'b1;
end else if (pulse_counter == {PULSE_CNTR_WIDTH{1'b1}}) begin
sync_pulse <= 1'b0;
end
end
end
endmodule
| 7.425025 |
module: ad9226_sample
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ad_test;
// Inputs
reg adc_clk;
reg rst;
reg [11:0] adc_data;
// Outputs
wire adc_buf_wr;
wire [11:0] adc_buf_addr;
wire [7:0] adc_buf_data;
wire [7:0] adc_data_narrow;
wire [7:0] adc_data_narrow_d0;
// Instantiate the Unit Under Test (UUT)
ad9226_sample uut (
.adc_clk(adc_clk),
.rst(rst),
.adc_data(adc_data),
.adc_buf_wr(adc_buf_wr),
.adc_buf_addr(adc_buf_addr),
.adc_buf_data(adc_buf_data),
.adc_data_narrow(adc_data_narrow),
.adc_data_narrow_d0(adc_data_narrow_d0)
);
initial begin
// Initialize Inputs
adc_clk = 0;
rst = 0;
adc_data = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.55928 |
module ad_wrapper #(
parameter AD_DATA_SIZE = 8
) (
input i_ad_clk,
i_rd_clk,
i_rst_n,
input i_st,
i_auto,
i_stout,
input [15:0] i_recv_count,
input [AD_DATA_SIZE-1:0] i_ad_data,
output [OUT_DATA_SIZE-1:0] o_dual_data,
output o_rd_empty,
o_working,
output reg o_ad_open
);
localparam OUT_DATA_SIZE = AD_DATA_SIZE * 2;
localparam ST_IDEL = 4'b0;
localparam ST_START = 4'b1;
localparam ST_COLLECT = 4'b10;
localparam ST_END = 4'b100;
wire [OUT_DATA_SIZE-1:0] buffer;
wire start, we_fifo, working;
reg st0, st1, st, working0;
assign start = i_auto ? i_stout : i_st;
assign o_working = working;
initial begin
st0 = 0;
st1 = 0;
st = 0;
end
always @(posedge i_ad_clk or negedge i_rst_n)
if (!i_rst_n) begin
{st0, st1, st} <= 3'b000;
o_ad_open <= 0;
end else begin
{st0, st1} <= {start, st0};
working0 <= working;
if (st0 && !st1) o_ad_open <= 1'b1;
if (o_ad_open) st <= 1'b1;
if (working0 && !working) {o_ad_open, st} <= 2'b0;
end
ad_buff ad_buff_inst (
.i_ad_clk(i_ad_clk),
.i_st(st),
.i_rst_n(i_rst_n),
.i_recv_count(i_recv_count),
.o_dual_data(buffer),
.o_data_on(we_fifo),
.o_working(working),
.i_ad_data(i_ad_data)
);
indififo #(OUT_DATA_SIZE) fifo_inst (
.i_wr_clk (i_ad_clk),
.i_rd_clk (i_rd_clk),
.i_rst_n (i_rst_n),
.i_wr_req (we_fifo),
.i_wr_data(buffer),
.o_rd_data(o_dual_data),
.o_empty (o_rd_empty)
);
endmodule
| 8.148798 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_xcvr_rx_if #(
parameter OCTETS_PER_BEAT = 4,
parameter DW = OCTETS_PER_BEAT * 8
)(
// jesd interface
input rx_clk,
input [OCTETS_PER_BEAT-1:0] rx_ip_sof,
input [DW-1:0] rx_ip_data,
output reg rx_sof,
output reg [DW-1:0] rx_data);
// rx_ip_sof:
// The input beat may contain more than one frame per clock, a sof bit is set for
// each frame.
// Every bit that corresponds to a octet that is at the beginning of a frame
// the bit is set. E.g for OCTETS_PER_BEAT = 4
// if F=1 all bits are set,
// F=2 sof=4'b0101,
// F=4 sof=4'b0001
//
// rx_ip_data:
// The temporal ordering of the octets is from LSB to MSB,
// this means the octet placed in the lowest 8 bits was received first,
// the octet placed in the highest 8 bits was received last.
// internal registers
reg [DW-1:0] rx_ip_data_d = 'd0;
reg [OCTETS_PER_BEAT-1:0] rx_ip_sof_hold = 'd0;
reg [OCTETS_PER_BEAT-1:0] rx_ip_sof_d = 'd0;
always @(posedge rx_clk) begin
rx_ip_data_d <= rx_ip_data;
rx_ip_sof_d <= rx_ip_sof;
if (|rx_ip_sof) begin
rx_ip_sof_hold <= rx_ip_sof;
end
rx_sof <= |rx_ip_sof_d;
end
wire [OCTETS_PER_BEAT*DW-1:0] rx_data_s;
assign rx_data_s[0 +: DW] = rx_ip_data;
generate
genvar i;
for (i = 1; i < OCTETS_PER_BEAT; i = i + 1) begin : g_rx_data_opt
assign rx_data_s[i*DW +: DW] = {rx_ip_data[i*8-1 : 0], rx_ip_data_d[DW-1 : i*8]};
end
endgenerate
integer j;
always @(posedge rx_clk) begin
for (j = OCTETS_PER_BEAT-1; j >= 0; j = j - 1) begin
if (rx_ip_sof_hold[j] == 1'b1) begin
rx_data <= rx_data_s[j*DW +: DW];
end
end
end
endmodule
| 8.180735 |
module aeMB2_bsft ( /*AUTOARG*/
// Outputs
bsf_mx,
// Inputs
opa_of,
opb_of,
opc_of,
imm_of,
gclk,
grst,
dena,
gpha
);
parameter AEMB_BSF = 1; ///< implement barrel shift
output [31:0] bsf_mx;
input [31:0] opa_of;
input [31:0] opb_of;
input [5:0] opc_of;
input [10:9] imm_of;
// SYS signals
input gclk, grst, dena, gpha;
/*AUTOREG*/
reg [31:0] rBSLL, rBSRL, rBSRA;
reg [31:0] rBSR;
reg [10:9] imm_ex;
wire [31:0] wOPB = opb_of;
wire [31:0] wOPA = opa_of;
// STAGE-1 SHIFTERS
// logical
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rBSLL <= 32'h0;
rBSRL <= 32'h0;
// End of automatics
end else if (dena) begin
rBSLL <= #1 wOPA << wOPB[4:0];
rBSRL <= #1 wOPA >> wOPB[4:0];
end
// arithmetic
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rBSRA <= 32'h0;
// End of automatics
end else if (dena)
case (wOPB[4:0])
5'd00: rBSRA <= wOPA;
5'd01: rBSRA <= {{(1) {wOPA[31]}}, wOPA[31:1]};
5'd02: rBSRA <= {{(2) {wOPA[31]}}, wOPA[31:2]};
5'd03: rBSRA <= {{(3) {wOPA[31]}}, wOPA[31:3]};
5'd04: rBSRA <= {{(4) {wOPA[31]}}, wOPA[31:4]};
5'd05: rBSRA <= {{(5) {wOPA[31]}}, wOPA[31:5]};
5'd06: rBSRA <= {{(6) {wOPA[31]}}, wOPA[31:6]};
5'd07: rBSRA <= {{(7) {wOPA[31]}}, wOPA[31:7]};
5'd08: rBSRA <= {{(8) {wOPA[31]}}, wOPA[31:8]};
5'd09: rBSRA <= {{(9) {wOPA[31]}}, wOPA[31:9]};
5'd10: rBSRA <= {{(10) {wOPA[31]}}, wOPA[31:10]};
5'd11: rBSRA <= {{(11) {wOPA[31]}}, wOPA[31:11]};
5'd12: rBSRA <= {{(12) {wOPA[31]}}, wOPA[31:12]};
5'd13: rBSRA <= {{(13) {wOPA[31]}}, wOPA[31:13]};
5'd14: rBSRA <= {{(14) {wOPA[31]}}, wOPA[31:14]};
5'd15: rBSRA <= {{(15) {wOPA[31]}}, wOPA[31:15]};
5'd16: rBSRA <= {{(16) {wOPA[31]}}, wOPA[31:16]};
5'd17: rBSRA <= {{(17) {wOPA[31]}}, wOPA[31:17]};
5'd18: rBSRA <= {{(18) {wOPA[31]}}, wOPA[31:18]};
5'd19: rBSRA <= {{(19) {wOPA[31]}}, wOPA[31:19]};
5'd20: rBSRA <= {{(20) {wOPA[31]}}, wOPA[31:20]};
5'd21: rBSRA <= {{(21) {wOPA[31]}}, wOPA[31:21]};
5'd22: rBSRA <= {{(22) {wOPA[31]}}, wOPA[31:22]};
5'd23: rBSRA <= {{(23) {wOPA[31]}}, wOPA[31:23]};
5'd24: rBSRA <= {{(24) {wOPA[31]}}, wOPA[31:24]};
5'd25: rBSRA <= {{(25) {wOPA[31]}}, wOPA[31:25]};
5'd26: rBSRA <= {{(26) {wOPA[31]}}, wOPA[31:26]};
5'd27: rBSRA <= {{(27) {wOPA[31]}}, wOPA[31:27]};
5'd28: rBSRA <= {{(28) {wOPA[31]}}, wOPA[31:28]};
5'd29: rBSRA <= {{(29) {wOPA[31]}}, wOPA[31:29]};
5'd30: rBSRA <= {{(30) {wOPA[31]}}, wOPA[31:30]};
5'd31: rBSRA <= {{(31) {wOPA[31]}}, wOPA[31]};
endcase // case (wOPB[4:0])
// STAGE-2 SHIFT
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
imm_ex <= 2'h0;
rBSR <= 32'h0;
// End of automatics
end else if (dena) begin
case (imm_ex)
2'o0: rBSR <= #1 rBSRL;
2'o1: rBSR <= #1 rBSRA;
2'o2: rBSR <= #1 rBSLL;
default: rBSR <= #1 32'hX;
endcase // case (imm_ex)
imm_ex <= #1 imm_of[10:9]; // delay 1 cycle
end
assign bsf_mx = (AEMB_BSF[0]) ? rBSR : 32'hX;
endmodule
| 6.998236 |
module aeMB2_dparam ( /*AUTOARG*/
// Outputs
dat_o,
xdat_o,
// Inputs
adr_i,
dat_i,
wre_i,
xadr_i,
xdat_i,
xwre_i,
clk_i,
ena_i
);
parameter AW = 5; // 32
parameter DW = 2; // x2
// PORT A - READ/WRITE
output [DW-1:0] dat_o;
input [AW-1:0] adr_i;
input [DW-1:0] dat_i;
input wre_i;
// PORT X - READ ONLY
output [DW-1:0] xdat_o;
input [AW-1:0] xadr_i;
input [DW-1:0] xdat_i;
input xwre_i;
// SYSCON
input clk_i, ena_i;
/*AUTOREG*/
reg [DW-1:0] rRAM[(1<<AW)-1:0];
always @(posedge clk_i) if (wre_i) rRAM[adr_i] <= #1 dat_i;
assign dat_o = rRAM[adr_i];
assign xdat_o = rRAM[xadr_i];
// --- SIMULATION ONLY ------------------------------------
// synopsys translate_off
integer i;
initial begin
for (i = 0; i < (1 << AW); i = i + 1) begin
rRAM[i] <= {(DW) {1'b0}};
end
end
// synopsys translate_on
endmodule
| 8.716146 |
module aeMB2_iwbif ( /*AUTOARG*/
// Outputs
iwb_adr_o,
iwb_stb_o,
iwb_sel_o,
iwb_wre_o,
iwb_cyc_o,
iwb_tag_o,
ich_adr,
fet_fb,
rpc_if,
rpc_ex,
rpc_mx,
exc_iwb,
// Inputs
iwb_ack_i,
iwb_dat_i,
ich_hit,
msr_ex,
hzd_bpc,
hzd_fwd,
bra_ex,
bpc_ex,
gclk,
grst,
dena,
iena,
gpha
);
parameter AEMB_IWB = 32;
parameter AEMB_HTX = 1;
// Wishbone
output [AEMB_IWB-1:2] iwb_adr_o;
output iwb_stb_o;
output [3:0] iwb_sel_o;
output iwb_wre_o;
output iwb_cyc_o;
output iwb_tag_o;
input iwb_ack_i;
input [31:0] iwb_dat_i;
//input iwb_err_i; // bus error exception
// Cache
output [AEMB_IWB-1:2] ich_adr;
input ich_hit;
// Internal
output fet_fb;
output [31:2] rpc_if, rpc_ex, rpc_mx;
input [7:5] msr_ex;
input hzd_bpc, hzd_fwd;
input [1:0] bra_ex;
input [31:2] bpc_ex;
output exc_iwb;
// SYS signals
input gclk, grst, dena, iena, gpha;
/*AUTOWIRE*/
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg iwb_stb_o;
reg [31:2] rpc_if;
reg [31:2] rpc_mx;
// End of automatics
reg [31:2] rpc_of, rpc_ex;
// BARREL
reg [31:2] rADR, rADR_;
wire [31:2] wPCINC = (rADR + 1'b1); // incrementer
wire [31:2] wPCNXT = rADR_;
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rADR <= 30'h0;
rADR_ <= 30'h0;
// End of automatics
end else if (iena) begin
case ({
hzd_fwd, bra_ex[1]
})
2'o0: {rADR} <= #1{rADR_[AEMB_IWB-1:2]}; // normal increment
2'o1: {rADR} <= #1{bpc_ex[AEMB_IWB-1:2]}; // brach/return/break
2'o2: {rADR} <= #1{rpc_if[AEMB_IWB-1:2]}; // bubble/hazard
default: {rADR} <= #1 30'hX;
//2'o3: rADR <= #1 rpc_if[AEMB_IWB-1:2]; // bubble/hazard
//2'o3: rADR <= #1 bpc_ex[AEMB_IWB-1:2]; // brach/return/break
endcase // case ({hzd_fwd,bra_ex[1]})
rADR_ <= #1 wPCINC;
end // if (iena)
assign ich_adr = rADR;
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rpc_ex <= 30'h0;
rpc_if <= 30'h0;
rpc_mx <= 30'h0;
rpc_of <= 30'h0;
// End of automatics
end else begin
if (dena) begin
{rpc_mx, // PC PIPELINE
rpc_ex, rpc_of} <= #1{
rpc_ex, rpc_of, rpc_if
};
end
if (iena) begin
rpc_if <= #1 rADR;
end
end // else: !if(grst)
// WISHBONE SIGNALS
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
iwb_stb_o <= 1'h0;
// End of automatics
end else begin
iwb_stb_o <= #1 (iwb_stb_o & !iwb_ack_i) | (!iwb_stb_o & !ich_hit);
end
assign iwb_adr_o = rADR;
assign iwb_wre_o = 1'b0;
assign iwb_sel_o = 4'hF;
assign iwb_cyc_o = iwb_stb_o;
assign iwb_tag_o = msr_ex[5];
assign fet_fb = iwb_stb_o ~^ iwb_ack_i; // no WB cycle
// TODO: enable iwb_err_i exception pass-thru
assign exc_iwb = 1'b0;
endmodule
| 6.605514 |
module aeMB2_pipe ( /*AUTOARG*/
// Outputs
brk_if,
gpha,
gclk,
grst,
dena,
iena,
// Inputs
bra_ex,
dwb_fb,
xwb_fb,
ich_fb,
fet_fb,
msr_ex,
exc_dwb,
exc_iwb,
exc_ill,
sys_clk_i,
sys_int_i,
sys_rst_i,
sys_ena_i
);
parameter AEMB_HTX = 1;
output [1:0] brk_if;
input [1:0] bra_ex;
input dwb_fb;
input xwb_fb;
input ich_fb;
input fet_fb;
input [9:0] msr_ex;
output gpha, gclk, grst, dena, iena;
input [1:0] exc_dwb;
input exc_iwb;
input exc_ill;
input sys_clk_i, sys_int_i, sys_rst_i, sys_ena_i;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [1:0] brk_if;
reg gpha;
// End of automatics
reg [1:0] rst;
reg por;
reg fet;
reg hit;
// Instantiate clock/reset managers
assign gclk = sys_clk_i;
assign grst = !rst[1];
// run instruction side pipeline
assign iena = ich_fb & xwb_fb & dwb_fb & sys_ena_i;
// run data side pipeline
assign dena = iena;
// interrupt process - latches onto any interrupt until it is handled
reg int_lat; ///< interrupt latch
always @(posedge sys_clk_i)
if (sys_rst_i) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
int_lat <= 1'h0;
// End of automatics
end else begin
int_lat <= #1 msr_ex[1] & (int_lat | sys_int_i);
end
// exception process - exceptions handled immediately
wire exc_lat; ///< exception latch
assign exc_lat = exc_ill | exc_dwb[1];
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
brk_if <= 2'h0;
// End of automatics
end else if (dena) begin
brk_if[1] <= #1 exc_lat & msr_ex[8] & !msr_ex[9]; // HIGH PRIORITY - exception
brk_if[0] <= #1 !exc_lat & !msr_ex[9] & !msr_ex[3] & int_lat; // LOW PRIORITY - interrupt (not BIP/EIP)
end
// RESET DELAY
always @(posedge sys_clk_i)
if (sys_rst_i) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rst <= 2'h0;
// End of automatics
end else begin
rst <= #1{rst[0], !sys_rst_i};
end
// PHASE TOGGLE
always @(posedge sys_clk_i)
if (sys_rst_i) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
gpha <= 1'h0;
// End of automatics
end else if (dena | grst) begin
gpha <= #1 !gpha;
end
endmodule
| 8.453301 |
module aeMB2_regs ( /*AUTOARG*/
// Outputs
opd_if,
opb_if,
opa_if,
// Inputs
xwb_mx,
sfr_mx,
sel_mx,
rpc_mx,
rd_of,
rd_ex,
mux_of,
mux_ex,
mul_mx,
ich_dat,
grst,
gpha,
gclk,
dwb_mx,
dena,
bsf_mx,
alu_mx
);
parameter AEMB_HTX = 1;
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [31:0] opa_if; // From gprf0 of aeMB2_gprf.v
output [31:0] opb_if; // From gprf0 of aeMB2_gprf.v
output [31:0] opd_if; // From gprf0 of aeMB2_gprf.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [31:0] alu_mx; // To gprf0 of aeMB2_gprf.v
input [31:0] bsf_mx; // To gprf0 of aeMB2_gprf.v
input dena; // To gprf0 of aeMB2_gprf.v
input [31:0] dwb_mx; // To gprf0 of aeMB2_gprf.v
input gclk; // To gprf0 of aeMB2_gprf.v
input gpha; // To gprf0 of aeMB2_gprf.v
input grst; // To gprf0 of aeMB2_gprf.v
input [31:0] ich_dat; // To gprf0 of aeMB2_gprf.v
input [31:0] mul_mx; // To gprf0 of aeMB2_gprf.v
input [2:0] mux_ex; // To gprf0 of aeMB2_gprf.v
input [2:0] mux_of; // To gprf0 of aeMB2_gprf.v
input [4:0] rd_ex; // To gprf0 of aeMB2_gprf.v
input [4:0] rd_of; // To gprf0 of aeMB2_gprf.v
input [31:2] rpc_mx; // To gprf0 of aeMB2_gprf.v
input [3:0] sel_mx; // To gprf0 of aeMB2_gprf.v
input [31:0] sfr_mx; // To gprf0 of aeMB2_gprf.v
input [31:0] xwb_mx; // To gprf0 of aeMB2_gprf.v
// End of automatics
/*AUTOWIRE*/
// TODO: Add special function registers
aeMB2_gprf #( /*AUTOINSTPARAM*/
// Parameters
.AEMB_HTX(AEMB_HTX)
) gprf0 ( /*AUTOINST*/
// Outputs
.opa_if (opa_if[31:0]),
.opb_if (opb_if[31:0]),
.opd_if (opd_if[31:0]),
// Inputs
.mux_of (mux_of[2:0]),
.mux_ex (mux_ex[2:0]),
.ich_dat(ich_dat[31:0]),
.rd_of (rd_of[4:0]),
.rd_ex (rd_ex[4:0]),
.sel_mx (sel_mx[3:0]),
.rpc_mx (rpc_mx[31:2]),
.xwb_mx (xwb_mx[31:0]),
.dwb_mx (dwb_mx[31:0]),
.alu_mx (alu_mx[31:0]),
.sfr_mx (sfr_mx[31:0]),
.mul_mx (mul_mx[31:0]),
.bsf_mx (bsf_mx[31:0]),
.gclk (gclk),
.grst (grst),
.dena (dena),
.gpha (gpha)
);
endmodule
| 6.536286 |
module aeMB2_sparam ( /*AUTOARG*/
// Outputs
dat_o,
// Inputs
adr_i,
dat_i,
wre_i,
clk_i,
ena_i
);
parameter AW = 5; // 32
parameter DW = 2; // x2
// PORT A - READ/WRITE
output [DW-1:0] dat_o;
input [AW-1:0] adr_i;
input [DW-1:0] dat_i;
input wre_i;
// SYSCON
input clk_i, ena_i;
/*AUTOREG*/
reg [DW-1:0] rRAM [(1<<AW)-1:0];
reg [AW-1:0] rADDR;
always @(posedge clk_i) begin
if (wre_i) rRAM[adr_i] <= #1 dat_i;
end
assign dat_o = rRAM[adr_i];
// --- SIMULATION ONLY ------------------------------------
// synopsys translate_off
integer i;
initial begin
for (i = 0; i < (1 << AW); i = i + 1) begin
rRAM[i] <= {(DW) {1'b0}};
end
end
// synopsys translate_on
endmodule
| 7.811699 |
module aeMB2_spsram ( /*AUTOARG*/
// Outputs
dat_o,
// Inputs
adr_i,
dat_i,
wre_i,
ena_i,
rst_i,
clk_i
);
parameter AW = 8;
parameter DW = 32;
// PORT A - READ/WRITE
output [DW-1:0] dat_o;
input [AW-1:0] adr_i;
input [DW-1:0] dat_i;
input wre_i, ena_i, rst_i, clk_i;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [DW-1:0] dat_o;
// End of automatics
reg [ DW:1] rRAM [(1<<AW)-1:0];
reg [ AW:1] rADR;
always @(posedge clk_i) if (wre_i) rRAM[adr_i] <= #1 dat_i;
always @(posedge clk_i)
if (rst_i)
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
dat_o <= {(1 + (DW - 1)) {1'b0}};
// End of automatics
else if (ena_i) dat_o <= #1 rRAM[adr_i];
// --- SIMULATION ONLY ------------------------------------
// synopsys translate_off
integer i;
initial begin
for (i = 0; i < (1 << AW); i = i + 1) begin
rRAM[i] <= $random;
end
end
// synopsys translate_on
endmodule
| 6.809276 |
module aeMB2_tpsram ( /*AUTOARG*/
// Outputs
dat_o,
xdat_o,
// Inputs
adr_i,
dat_i,
wre_i,
ena_i,
rst_i,
clk_i,
xadr_i,
xdat_i,
xwre_i,
xena_i,
xrst_i,
xclk_i
);
parameter AW = 8; // 256
parameter DW = 32; // x32
// PORT A - WRITE
output [DW-1:0] dat_o;
input [AW-1:0] adr_i;
input [DW-1:0] dat_i;
input wre_i, ena_i, rst_i, clk_i;
// PORT X - READ
output [DW-1:0] xdat_o;
input [AW-1:0] xadr_i;
input [DW-1:0] xdat_i;
input xwre_i, xena_i, xrst_i, xclk_i;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [DW-1:0] xdat_o;
// End of automatics
reg [DW:1] rRAM[(1<<AW)-1:0];
reg [AW:1] rADR;
always @(posedge clk_i) if (wre_i) rRAM[adr_i] <= #1 dat_i;
always @(posedge xclk_i)
if (xrst_i)
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
xdat_o <= {(1 + (DW - 1)) {1'b0}};
// End of automatics
else if (xena_i) xdat_o <= #1 rRAM[xadr_i];
assign dat_o = {(DW) {1'bX}}; // tieoff unused outputs
// --- SIMULATION ONLY ------------------------------------
// synopsys translate_off
integer i;
initial begin
for (i = 0; i < (1 << AW); i = i + 1) begin
rRAM[i] <= $random;
end
end
// synopsys translate_on
endmodule
| 7.796619 |
module aeMB2_xslif ( /*AUTOARG*/
// Outputs
xwb_adr_o,
xwb_dat_o,
xwb_sel_o,
xwb_tag_o,
xwb_stb_o,
xwb_cyc_o,
xwb_wre_o,
xwb_fb,
xwb_mx,
// Inputs
xwb_dat_i,
xwb_ack_i,
imm_of,
opc_of,
opa_of,
gclk,
grst,
dena,
gpha
);
parameter AEMB_XSL = 1; ///< implement XSEL bus (ignored)
parameter AEMB_XWB = 3; ///< XSEL bus width
// XWB control signals
output [AEMB_XWB-1:2] xwb_adr_o;
output [31:0] xwb_dat_o;
output [3:0] xwb_sel_o;
output xwb_tag_o;
output xwb_stb_o, xwb_cyc_o, xwb_wre_o;
input [31:0] xwb_dat_i;
input xwb_ack_i;
// INTERNAL
output xwb_fb;
output [31:0] xwb_mx;
input [15:0] imm_of;
input [5:0] opc_of;
input [31:0] opa_of;
// SYS signals
input gclk, grst, dena, gpha;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [AEMB_XWB-1:2] xwb_adr_o;
reg [31:0] xwb_dat_o;
reg [31:0] xwb_mx;
reg xwb_stb_o;
reg xwb_tag_o;
reg xwb_wre_o;
// End of automatics
// FIXME: perform NGET/NPUT non-blocking operations
assign xwb_fb = (xwb_stb_o ~^ xwb_ack_i);
// XSEL bus
reg [31:0] xwb_lat;
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
xwb_adr_o <= {(1 + (AEMB_XWB - 1) - (2)) {1'b0}};
xwb_dat_o <= 32'h0;
xwb_mx <= 32'h0;
xwb_tag_o <= 1'h0;
xwb_wre_o <= 1'h0;
// End of automatics
end else if (dena) begin
xwb_adr_o <= #1 imm_of[11:0]; // FSLx
xwb_wre_o <= #1 imm_of[15]; // PUT
xwb_tag_o <= #1 imm_of[13]; // cGET/cPUT
xwb_dat_o <= #1 opa_of; // Latch output
xwb_mx <= #1 (xwb_ack_i) ? xwb_dat_i : // stalled from XWB
xwb_lat; // Latch earlier
end // if (dena)
assign xwb_sel_o = 4'hF;
// Independent on pipeline
reg xBLK;
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
xwb_lat <= 32'h0;
// End of automatics
end else if (xwb_ack_i) begin
xwb_lat <= #1 xwb_dat_i;
end
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
xBLK <= 1'h0;
xwb_stb_o <= 1'h0;
// End of automatics
end else if (xwb_fb) begin
xBLK <= #1 imm_of[14]; // nGET/nPUT
xwb_stb_o <= #1 (dena) ? !opc_of[5] & opc_of[4] & opc_of[3] & opc_of[1] : // GET/PUT
(xwb_stb_o & !xwb_ack_i);
end
assign xwb_cyc_o = xwb_stb_o;
//assign xwb_stb_o = (AEMB_XSL[0]) ? xSTB : 1'bX;
endmodule
| 7.498968 |
module aeMB_bpcu ( /*AUTOARG*/
// Outputs
iwb_adr_o,
rPC,
rPCLNK,
rBRA,
rDLY,
// Inputs
rMXALT,
rOPC,
rRD,
rRA,
rRESULT,
rDWBDI,
rREGA,
gclk,
grst,
gena
);
parameter IW = 24;
// INST WISHBONE
output [IW-1:2] iwb_adr_o;
// INTERNAL
output [31:2] rPC, rPCLNK;
output rBRA;
output rDLY;
//output [1:0] rATOM;
//output [1:0] xATOM;
input [1:0] rMXALT;
input [5:0] rOPC;
input [4:0] rRD, rRA;
input [31:0] rRESULT; // ALU
input [31:0] rDWBDI; // RAM
input [31:0] rREGA;
//input [1:0] rXCE;
// SYSTEM
input gclk, grst, gena;
// --- BRANCH CONTROL --------------------------------------------
// Controls the branch and delay flags
wire fRTD = (rOPC == 6'o55);
wire fBCC = (rOPC == 6'o47) | (rOPC == 6'o57);
wire fBRU = (rOPC == 6'o46) | (rOPC == 6'o56);
wire [31:0] wREGA;
assign wREGA = (rMXALT == 2'o2) ? rDWBDI : (rMXALT == 2'o1) ? rRESULT : rREGA;
wire wBEQ = (wREGA == 32'd0);
wire wBNE = ~wBEQ;
wire wBLT = wREGA[31];
wire wBLE = wBLT | wBEQ;
wire wBGE = ~wBLT;
wire wBGT = ~wBLE;
reg xXCC;
always @( /*AUTOSENSE*/ rRD or wBEQ or wBGE or wBGT or wBLE or wBLT or wBNE)
case (rRD[2:0])
3'o0: xXCC <= wBEQ;
3'o1: xXCC <= wBNE;
3'o2: xXCC <= wBLT;
3'o3: xXCC <= wBLE;
3'o4: xXCC <= wBGT;
3'o5: xXCC <= wBGE;
default: xXCC <= 1'bX;
endcase // case (rRD[2:0])
reg rBRA, xBRA;
reg rDLY, xDLY;
wire fSKIP = rBRA & !rDLY;
always @( /*AUTOSENSE*/ fBCC or fBRU or fRTD or rBRA or rRA or rRD or xXCC)
//if (rBRA | |rXCE) begin
if (rBRA) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
xBRA <= 1'h0;
xDLY <= 1'h0;
// End of automatics
end else begin
xDLY <= (fBRU & rRA[4]) | (fBCC & rRD[4]) | fRTD;
xBRA <= (fRTD | fBRU) ? 1'b1 : (fBCC) ? xXCC : 1'b0;
end
// --- PC PIPELINE ------------------------------------------------
// PC and related changes
reg [31:2] rIPC, xIPC;
reg [31:2] rPC, xPC;
reg [31:2] rPCLNK, xPCLNK;
assign iwb_adr_o = gena ? xIPC[IW-1:2] : rIPC[IW-1:2]; //IJB
always @( /*AUTOSENSE*/ rBRA or rIPC or rPC or rRESULT) begin
//xPCLNK <= (^rATOM) ? rPC : rPC;
xPCLNK <= rPC;
//xPC <= (^rATOM) ? rIPC : rRESULT[31:2];
xPC <= rIPC;
//xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1);
/*
case (rXCE)
2'o1: xIPC <= 30'h2;
2'o2: xIPC <= 30'h4;
2'o3: xIPC <= 30'h6;
default: xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1);
endcase // case (rXCE)
*/
xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1);
end
// --- ATOMIC CONTROL ---------------------------------------------
// This is used to indicate 'safe' instruction borders.
wire wIMM = (rOPC == 6'o54) & !fSKIP;
wire wRTD = (rOPC == 6'o55) & !fSKIP;
wire wBCC = xXCC & ((rOPC == 6'o47) | (rOPC == 6'o57)) & !fSKIP;
wire wBRU = ((rOPC == 6'o46) | (rOPC == 6'o56)) & !fSKIP;
wire fATOM = ~(wIMM | wRTD | wBCC | wBRU | rBRA);
reg [1:0] rATOM, xATOM;
always @( /*AUTOSENSE*/ fATOM or rATOM) xATOM <= {rATOM[0], (rATOM[0] ^ fATOM)};
// --- SYNC PIPELINE ----------------------------------------------
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rATOM <= 2'h0;
rBRA <= 1'h0;
rDLY <= 1'h0;
// rIPC <= 30'h0;
rIPC <= 30'h3fffffff; // DWORD aligned address
rPC <= 30'h0;
rPCLNK <= 30'h0;
// End of automatics
end else if (gena) begin
rIPC <= #1 xIPC;
rBRA <= #1 xBRA;
rPC <= #1 xPC;
rPCLNK <= #1 xPCLNK;
rDLY <= #1 xDLY;
rATOM <= #1 xATOM;
end
endmodule
| 7.610314 |
module aeMB_control ( /*AUTOARG*/
// Outputs
rFSM,
nclk,
prst,
prun,
frun,
drun,
// Inputs
sys_rst_i,
sys_clk_i,
sys_int_i,
sys_exc_i,
rIWBSTB,
iwb_ack_i,
rDWBSTB,
dwb_ack_i,
rBRA,
rDLY,
iwb_dat_i,
rMSR_IE
);
// System
input sys_rst_i, sys_clk_i;
input sys_int_i;
input sys_exc_i;
// Instruction WB
input rIWBSTB;
input iwb_ack_i;
// Data WB
input rDWBSTB;
input dwb_ack_i;
// Internal
input rBRA, rDLY;
input [31:0] iwb_dat_i;
input rMSR_IE;
output [1:0] rFSM;
//, rLDST;
output nclk, prst, prun;
output frun, drun;
/**
RUN Signal
----------
This master run signal will pause or run the entire pipeline. It
will pause for any incomplete bus transaction.
*/
assign prun = ~((rDWBSTB ^ dwb_ack_i) | ((rIWBSTB ^ iwb_ack_i)));
/**
Debounce
--------
The following external signals are debounced and synchronised:
- Interrupt
TODO: Exceptions
*/
wire fINT;
reg [2:0] rEXC, rINT;
always @(negedge nclk)
if (prst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rINT <= 3'h0;
// End of automatics
end else if (prun) begin
//rEXC <= #1 {rEXC[1:0], sys_exc_i};
rINT <= #1{rINT[1:0], sys_int_i};
end
/**
Machine States
--------------
The internal machine state is affected by external interrupt,
exception and software exceptions. Only interrupts are
implemented.
TODO: Implement Exceptions
*/
parameter [1:0] FSM_RUN = 2'o0, FSM_SWEXC = 2'o3, FSM_HWEXC = 2'o2, FSM_HWINT = 2'o1;
reg [1:0] rFSM, rNXT;
always @(negedge nclk)
if (prst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rFSM <= 2'h0;
// End of automatics
end else if (prun) begin
rFSM <= #1 rNXT;
end
always @( /*AUTOSENSE*/ fINT or rFSM)
case (rFSM)
FSM_HWEXC: rNXT <= FSM_RUN;
//FSM_SWEXC: rNXT <= FSM_RUN;
FSM_HWINT: rNXT <= FSM_RUN;
default: begin
rNXT <= //(rEXC == 3'h3) ? FSM_HWEXC :
(fINT) ? FSM_HWINT : FSM_RUN;
end
endcase // case (rFSM)
/**
Interrupt Check
---------------
It checks to make sure that all the instructions in the pipeline
are atomic before allowing the detection of interrupts. Empirical
response latency is 3-7 cycles.
*/
wire [5:0] rOPC = iwb_dat_i[31:26];
reg [2:0] rHWINT;
reg [1:0] rNCLR;
wire fCLR = ~|rNCLR;
wire fNCLR = ({rOPC[5:4], rOPC[2:1]} == 4'b1011) | (rOPC == 6'o54) | (rOPC == 6'o55);
assign fINT = (rHWINT == 3'o3) & fCLR;
always @(negedge nclk)
if (prst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rHWINT <= 3'h0;
// End of automatics
end else if (fINT) begin
rHWINT <= 3'o0;
end else if (prun & fCLR & rMSR_IE) begin
rHWINT <= {rHWINT[1:0], sys_int_i};
end
always @(negedge nclk)
if (prst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rNCLR <= 2'h0;
// End of automatics
end else if (prun) begin
rNCLR <= {rNCLR[0], fNCLR};
end
/**
Bubble
------
Pipeline bubbles are introduced during a branch or interrupt.
*/
reg [1:0] rRUN, xRUN;
wire fXCE = ~|rFSM;
assign {drun, frun} = {xRUN[1] & fXCE, xRUN[0] & fXCE};
always @( /*AUTOSENSE*/ rBRA or rDLY) begin
xRUN <= {~(rBRA ^ rDLY), ~rBRA};
end
/**
Clock/Reset
-----------
This controls the internal clock/reset signal for the core. Any
DCM/PLL/DPLL can be instantiated here if needed.
*/
reg [1:0] rRST;
assign nclk = sys_clk_i;
assign prst = rRST[1];
always @(negedge nclk)
if (!sys_rst_i) begin
rRST <= 2'h3;
/*AUTORESET*/
end else begin
rRST <= {rRST[0], 1'b0};
end
endmodule
| 8.744303 |
module aeMB_core ( /*AUTOARG*/
// Outputs
iwb_stb_o,
iwb_adr_o,
fsl_wre_o,
fsl_tag_o,
fsl_stb_o,
fsl_dat_o,
fsl_adr_o,
dwb_wre_o,
dwb_stb_o,
dwb_sel_o,
dwb_dat_o,
dwb_adr_o,
// Inputs
sys_rst_i,
sys_int_i,
sys_clk_i,
iwb_dat_i,
iwb_ack_i,
fsl_dat_i,
fsl_ack_i,
dwb_dat_i,
dwb_ack_i
);
// Instruction WB address space
parameter ISIZ = 32;
// Data WB address space
parameter DSIZ = 32;
// Multiplier
parameter MUL = 1;
// Barrel Shifter
parameter BSF = 1;
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [DSIZ-1:2] dwb_adr_o; // From edk32 of aeMB_edk32.v
output [31:0] dwb_dat_o; // From edk32 of aeMB_edk32.v
output [3:0] dwb_sel_o; // From edk32 of aeMB_edk32.v
output dwb_stb_o; // From edk32 of aeMB_edk32.v
output dwb_wre_o; // From edk32 of aeMB_edk32.v
output [6:2] fsl_adr_o; // From edk32 of aeMB_edk32.v
output [31:0] fsl_dat_o; // From edk32 of aeMB_edk32.v
output fsl_stb_o; // From edk32 of aeMB_edk32.v
output [1:0] fsl_tag_o; // From edk32 of aeMB_edk32.v
output fsl_wre_o; // From edk32 of aeMB_edk32.v
output [ISIZ-1:2] iwb_adr_o; // From edk32 of aeMB_edk32.v
output iwb_stb_o; // From edk32 of aeMB_edk32.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input dwb_ack_i; // To edk32 of aeMB_edk32.v
input [31:0] dwb_dat_i; // To edk32 of aeMB_edk32.v
input fsl_ack_i; // To edk32 of aeMB_edk32.v
input [31:0] fsl_dat_i; // To edk32 of aeMB_edk32.v
input iwb_ack_i; // To edk32 of aeMB_edk32.v
input [31:0] iwb_dat_i; // To edk32 of aeMB_edk32.v
input sys_clk_i; // To edk32 of aeMB_edk32.v
input sys_int_i; // To edk32 of aeMB_edk32.v
input sys_rst_i; // To edk32 of aeMB_edk32.v
// End of automatics
/*AUTOWIRE*/
// INSTANTIATIONS /////////////////////////////////////////////////////////////////
/*
aeMB_edk32 AUTO_TEMPLATE (
.dwb_adr_o(dwb_adr_o[DSIZ-1:2]),
.iwb_adr_o(iwb_adr_o[ISIZ-1:2]),
);
*/
aeMB_edk32 #(ISIZ, DSIZ, MUL, BSF) edk32 ( /*AUTOINST*/
// Outputs
.dwb_adr_o(dwb_adr_o[DSIZ-1:2]), // Templated
.dwb_dat_o(dwb_dat_o[31:0]),
.dwb_sel_o(dwb_sel_o[3:0]),
.dwb_stb_o(dwb_stb_o),
.dwb_wre_o(dwb_wre_o),
.fsl_adr_o(fsl_adr_o[6:2]),
.fsl_dat_o(fsl_dat_o[31:0]),
.fsl_stb_o(fsl_stb_o),
.fsl_tag_o(fsl_tag_o[1:0]),
.fsl_wre_o(fsl_wre_o),
.iwb_adr_o(iwb_adr_o[ISIZ-1:2]), // Templated
.iwb_stb_o(iwb_stb_o),
// Inputs
.dwb_ack_i(dwb_ack_i),
.dwb_dat_i(dwb_dat_i[31:0]),
.fsl_ack_i(fsl_ack_i),
.fsl_dat_i(fsl_dat_i[31:0]),
.iwb_ack_i(iwb_ack_i),
.iwb_dat_i(iwb_dat_i[31:0]),
.sys_int_i(sys_int_i),
.sys_clk_i(sys_clk_i),
.sys_rst_i(sys_rst_i)
);
endmodule
| 6.838937 |
module aeMB_core_BE #(
parameter ISIZ = 32,
parameter DSIZ = 32,
parameter MUL = 0,
parameter BSF = 0
) (
input sys_clk_i,
input sys_rst_i,
// Instruction port
output [ISIZ-1:0] if_adr,
input [31:0] if_dat,
// Data port
output dwb_we_o,
output dwb_stb_o,
output [DSIZ-1:0] dwb_adr_o,
output [31:0] dwb_dat_o,
input [31:0] dwb_dat_i,
input dwb_ack_i,
output [3:0] dwb_sel_o,
output dwb_cyc_o,
input sys_int_i,
input sys_exc_i
);
wire [ISIZ-1:0] iwb_adr_o;
wire [ 31:0] iwb_dat_i;
wire iwb_ack_i;
wire iwb_stb_o;
assign dwb_cyc_o = dwb_stb_o;
assign iwb_ack_i = 1'b1;
assign if_adr = iwb_adr_o[ISIZ-1:0];
assign iwb_dat_i = if_dat;
// Note some "wishbone" instruction fetch signals pruned on external interface
// but not propogated change deep into aeMB.
aeMB_edk32 #(
.IW (ISIZ),
.DW (DSIZ),
.MUL(MUL),
.BSF(BSF)
) aeMB_edk32 (
.sys_clk_i(sys_clk_i),
.sys_rst_i(sys_rst_i),
// Instruction Port
.iwb_stb_o(iwb_stb_o),
.iwb_adr_o(iwb_adr_o[ISIZ-1:2]),
.iwb_ack_i(iwb_ack_i),
.iwb_dat_i(iwb_dat_i),
// Data port
.dwb_wre_o(dwb_we_o),
.dwb_stb_o(dwb_stb_o),
.dwb_adr_o(dwb_adr_o[DSIZ-1:2]),
.dwb_ack_i(dwb_ack_i),
.dwb_sel_o(dwb_sel_o),
.dwb_dat_i(dwb_dat_i),
.dwb_dat_o(dwb_dat_o),
.fsl_wre_o(),
.fsl_tag_o(),
.fsl_stb_o(),
.fsl_dat_o(),
.fsl_adr_o(),
.fsl_dat_i(32'b0),
.fsl_ack_i(1'b0),
.sys_int_i(sys_int_i)
);
assign iwb_adr_o[1:0] = 2'b0;
assign dwb_adr_o[1:0] = 2'b0;
endmodule
| 7.678273 |
module aeMB_fetch ( /*AUTOARG*/
// Outputs
iwb_adr_o,
iwb_stb_o,
rPC,
rIWBSTB,
// Inputs
iwb_dat_i,
nclk,
prst,
prun,
rFSM,
rBRA,
rRESULT
);
parameter ISIZ = 32;
// Instruction WB I/F
output [ISIZ-1:0] iwb_adr_o;
output iwb_stb_o;
input [31:0] iwb_dat_i;
// System
input nclk, prst, prun;
// Internal
output [31:0] rPC;
output rIWBSTB;
input [1:0] rFSM;
input rBRA;
input [31:0] rRESULT;
/**
Instruction WISHBONE bus
------------------------
Signals for the instruction side of the bus.
*/
reg [31:0] rIWBADR, rPC, xIWBADR, xPC;
wire [31:0] wPCNXT = {(rIWBADR[ISIZ-1:2] + 1'b1), 2'b00};
assign iwb_adr_o = {rIWBADR[ISIZ-1:2], 2'b00}; // Word Aligned
assign iwb_stb_o = 1'b1;
assign rIWBSTB = 1'b1;
always @( /*AUTOSENSE*/ rBRA or rFSM or rIWBADR or rRESULT or wPCNXT) begin
// PC Sources - ALU, Direct, Next
case (rFSM)
2'b01: xIWBADR <= 32'h00000010; // HWINT
//2'b10: xIWBADR <= 32'h00000020; // HWEXC
//2'b11: xIWBADR <= #1 32'h00000008; // SWEXC
default: xIWBADR <= (rBRA) ? rRESULT : wPCNXT;
endcase // case (rFSM)
xPC <= {rIWBADR[31:2], 2'd0};
end // always @ (...
// PIPELINE REGISTERS //////////////////////////////////////////////////
always @(negedge nclk)
if (prst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rIWBADR <= 32'h0;
rPC <= 32'h0;
// End of automatics
end else if (prun) begin
rPC <= #1 xPC;
rIWBADR <= #1 xIWBADR;
end
endmodule
| 8.462898 |
module aeMB_ibuf ( /*AUTOARG*/
// Outputs
rIMM,
rRA,
rRD,
rRB,
rALT,
rOPC,
rSIMM,
xIREG,
rSTALL,
iwb_stb_o,
// Inputs
rBRA,
rMSR_IE,
rMSR_BIP,
iwb_dat_i,
iwb_ack_i,
sys_int_i,
gclk,
grst,
gena,
oena
);
// INTERNAL
output [15:0] rIMM;
output [4:0] rRA, rRD, rRB;
output [10:0] rALT;
output [5:0] rOPC;
output [31:0] rSIMM;
output [31:0] xIREG;
output rSTALL;
input rBRA;
//input [1:0] rXCE;
input rMSR_IE;
input rMSR_BIP;
// INST WISHBONE
output iwb_stb_o;
input [31:0] iwb_dat_i;
input iwb_ack_i;
// SYSTEM
input sys_int_i;
// SYSTEM
input gclk, grst, gena, oena;
reg [15:0] rIMM;
reg [4:0] rRA, rRD;
reg [ 5:0] rOPC;
// FIXME: Endian
wire [31:0] wIDAT = iwb_dat_i;
assign {rRB, rALT} = rIMM;
// TODO: Assign to FIFO not full.
assign iwb_stb_o = 1'b1;
reg [31:0] rSIMM, xSIMM;
reg rSTALL;
wire [31:0] wXCEOP = 32'hBA2D0008; // Vector 0x08
wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10
wire [31:0] wBRKOP = 32'hBA0C0018; // Vector 0x18
wire [31:0] wBRAOP = 32'h88000000; // NOP for branches
wire [31:0] wIREG = {rOPC, rRD, rRA, rRB, rALT};
reg [31:0] xIREG;
// --- INTERRUPT LATCH --------------------------------------
// Debounce and latch onto the positive level. This is independent
// of the pipeline so that stalls do not affect it.
reg rFINT;
reg [1:0] rDINT;
wire wSHOT = rDINT[0];
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rDINT <= 2'h0;
rFINT <= 1'h0;
// End of automatics
end else begin
if (rMSR_IE) rDINT <= #1{rDINT[0], sys_int_i};
rFINT <= #1
//(wIREG == wINTOP) ? 1'b0 :
(rFINT | wSHOT) & rMSR_IE;
end
wire fIMM = (rOPC == 6'o54);
wire fRTD = (rOPC == 6'o55);
wire fBRU = ((rOPC == 6'o46) | (rOPC == 6'o56));
wire fBCC = ((rOPC == 6'o47) | (rOPC == 6'o57));
// --- DELAY SLOT -------------------------------------------
always @(/*AUTOSENSE*/fBCC or fBRU or fIMM or fRTD or rBRA or rFINT
or wBRAOP or wIDAT or wINTOP) begin
xIREG <= (rBRA) ? wBRAOP : (!fIMM & rFINT & !fRTD & !fBRU & !fBCC) ? wINTOP : wIDAT;
end
always @( /*AUTOSENSE*/ fIMM or rBRA or rIMM or wIDAT or xIREG) begin
xSIMM <= (!fIMM | rBRA) ? {{(16) {xIREG[15]}}, xIREG[15:0]} : {rIMM, wIDAT[15:0]};
end
// --- PIPELINE --------------------------------------------
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rIMM <= 16'h0;
rOPC <= 6'h0;
rRA <= 5'h0;
rRD <= 5'h0;
rSIMM <= 32'h0;
// End of automatics
end else if (gena) begin
{rOPC, rRD, rRA, rIMM} <= #1 xIREG;
rSIMM <= #1 xSIMM;
end
// --- STALL FOR MUL/BSF -----------------------------------
wire [5:0] wOPC = xIREG[31:26];
wire fMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
wire fBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rSTALL <= 1'h0;
// End of automatics
end else begin
rSTALL <= #1 (gena & !rSTALL & (fMUL | fBSF)) | (oena & rSTALL);
end
endmodule
| 6.590315 |
module aeMB_ucore ( /*AUTOARG*/
// Outputs
wb_wre_o,
wb_stb_o,
wb_sel_o,
wb_dat_o,
wb_adr_o,
// Inputs
wb_dat_i,
wb_ack_i,
sys_rst_i,
sys_int_i,
sys_exc_i,
sys_clk_i
);
/* Bus Address Width */
parameter ASIZ = 32;
parameter CSIZ = 7;
/* DO NOT TOUCH */
parameter DSIZ = ASIZ;
parameter ISIZ = ASIZ;
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [ASIZ-1:0] wb_adr_o; // From wbbus of aeMB_wbbus.v
output [31:0] wb_dat_o; // From wbbus of aeMB_wbbus.v
output [3:0] wb_sel_o; // From wbbus of aeMB_wbbus.v
output wb_stb_o; // From wbbus of aeMB_wbbus.v
output wb_wre_o; // From wbbus of aeMB_wbbus.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input sys_clk_i; // To wbbus of aeMB_wbbus.v, ...
input sys_exc_i; // To cpu of aeMB_core.v
input sys_int_i; // To cpu of aeMB_core.v
input sys_rst_i; // To wbbus of aeMB_wbbus.v, ...
input wb_ack_i; // To wbbus of aeMB_wbbus.v
input [31:0] wb_dat_i; // To wbbus of aeMB_wbbus.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire dwb_ack_i; // From wbbus of aeMB_wbbus.v
wire [DSIZ-1:0] dwb_adr_o; // From cpu of aeMB_core.v
wire [31:0] dwb_dat_i; // From wbbus of aeMB_wbbus.v
wire [31:0] dwb_dat_o; // From cpu of aeMB_core.v
wire dwb_stb_o; // From cpu of aeMB_core.v
wire dwb_we_o; // From cpu of aeMB_core.v
wire iwb_ack_i; // From wbbus of aeMB_wbbus.v
wire [ISIZ-1:0] iwb_adr_o; // From cpu of aeMB_core.v
wire [31:0] iwb_dat_i; // From wbbus of aeMB_wbbus.v
wire iwb_stb_o; // From cpu of aeMB_core.v
// End of automatics
aeMB_wbbus #(ASIZ, CSIZ, ISIZ, DSIZ) wbbus ( /*AUTOINST*/
// Outputs
.wb_adr_o (wb_adr_o[ASIZ-1:0]),
.wb_dat_o (wb_dat_o[31:0]),
.wb_sel_o (wb_sel_o[3:0]),
.wb_stb_o (wb_stb_o),
.wb_wre_o (wb_wre_o),
.dwb_ack_i(dwb_ack_i),
.dwb_dat_i(dwb_dat_i[31:0]),
.iwb_ack_i(iwb_ack_i),
.iwb_dat_i(iwb_dat_i[31:0]),
// Inputs
.wb_dat_i (wb_dat_i[31:0]),
.wb_ack_i (wb_ack_i),
.dwb_adr_o(dwb_adr_o[DSIZ-1:0]),
.dwb_dat_o(dwb_dat_o[31:0]),
.dwb_stb_o(dwb_stb_o),
.dwb_we_o (dwb_we_o),
.iwb_adr_o(iwb_adr_o[ISIZ-1:0]),
.iwb_stb_o(iwb_stb_o),
.sys_clk_i(sys_clk_i),
.sys_rst_i(sys_rst_i)
);
aeMB_core #(ISIZ, DSIZ) cpu ( /*AUTOINST*/
// Outputs
.dwb_adr_o(dwb_adr_o[DSIZ-1:0]),
.dwb_dat_o(dwb_dat_o[31:0]),
.dwb_stb_o(dwb_stb_o),
.dwb_we_o (dwb_we_o),
.iwb_adr_o(iwb_adr_o[ISIZ-1:0]),
.iwb_stb_o(iwb_stb_o),
// Inputs
.dwb_ack_i(dwb_ack_i),
.dwb_dat_i(dwb_dat_i[31:0]),
.iwb_ack_i(iwb_ack_i),
.iwb_dat_i(iwb_dat_i[31:0]),
.sys_clk_i(sys_clk_i),
.sys_exc_i(sys_exc_i),
.sys_int_i(sys_int_i),
.sys_rst_i(sys_rst_i)
);
endmodule
| 7.540581 |
module AES128 (
ProgramSelector,
UserText,
Key,
ReadyKey,
ReadRy,
WriteRy,
Clk,
Rst,
ReadEn,
WriteEn,
Result
);
input ProgramSelector;
input [127:0] UserText;
input [127:0] Key;
input ReadyKey;
input ReadRy;
input WriteRy;
input Clk;
input Rst;
output ReadEn;
output WriteEn;
output [127:0] Result;
wire [127:0] PT;
wire [127:0] CT;
wire Ry;
wire KeyEn;
wire u1_Ry;
wire EncEn;
wire u2_Ry;
wire DecEn;
wire [3:0] SelKey;
wire [3:0] u2_SelKey;
wire [3:0] u1_SelKey;
wire [127:0] u4_Key;
wire u5_Ry;
wire OutEn;
wire RstKey;
wire RstProgram;
wire RstEncryptorOk;
wire RstEncryptor;
wire ProgramRunning;
assign RstEncryptorOk = RstEncryptor | Rst;
OutputSelector u5 (
.Sel(ProgramSelector),
.PT(PT),
.CT(CT),
.Result(Result),
.En(OutEn),
.Ry(u5_Ry),
.Clk(Clk),
.Rst(RstProgram)
);
AES_Encryptor u1 (
.PT(UserText),
.Clk(Clk),
.Rst(RstEncryptorOk),
.En(EncEn),
.Ry(u1_Ry),
.CT(CT),
.Key(u4_Key),
.SelKey(u1_SelKey)
);
AES_Decryptor u2 (
.CT(UserText),
.Clk(Clk),
.Rst(RstProgram),
.En(DecEn),
.Ry(u2_Ry),
.Key(u4_Key),
.PT(PT),
.SelKey(u2_SelKey)
);
Controller u3 (
.SerialReadEn(ReadEn),
.EncEn(EncEn),
.DecEn(DecEn),
.KeyEn(KeyEn),
.SerialWriteRy(WriteRy),
.SerialKeyRy(ReadyKey),
.EncRy(u1_Ry),
.KeyRy(Ry),
.DecRy(u2_Ry),
.Clk(Clk),
.Rst(Rst),
.RstEncryptor(RstEncryptor),
.RstKey(RstKey),
.SerialWriteEn(WriteEn),
.OutEn(OutEn),
.OutRy(u5_Ry),
.SerialReadRy(ReadRy),
.ProgramSelector(ProgramSelector),
.ProgramRunning(ProgramRunning)
);
Key_Scheduler u4 (
.RyK(ReadyKey),
.Clk(Clk),
.Rst(RstKey | Rst),
.En(KeyEn),
.Ry(Ry),
.Key(u4_Key),
.SelKey(SelKey),
.KeySeed(Key)
);
Key_Selector u6 (
.SelKeyEnc(u1_SelKey),
.SelKeyDec(u2_SelKey),
.SelKey(SelKey),
.EncEn(EncEn),
.DecEn(DecEn)
);
LogicReset u9 (
.Rst(Rst),
.ReadyKey(ProgramRunning),
.RstKey(RstProgram)
);
endmodule
| 7.963218 |
module aes128_axi
(
input wire ARESETn
, input wire ACLK
, input wire [AXI_WIDTH_SID-1:0] AWID
, input wire [AXI_WIDTH_AD-1:0] AWADDR
`ifdef AMBA_AXI4
, input wire [ 7:0] AWLEN
, input wire AWLOCK
`else
, input wire [ 3:0] AWLEN
, input wire [ 1:0] AWLOCK
`endif
, input wire [ 2:0] AWSIZE
, input wire [ 1:0] AWBURST
`ifdef AMBA_AXI_CACHE
, input wire [ 3:0] AWCACHE
`endif
`ifdef AMBA_AXI_PROT
, input wire [ 2:0] AWPROT
`endif
, input wire AWVALID
, output wire AWREADY
`ifdef AMBA_AXI4
, input wire [ 3:0] AWQOS
, input wire [ 3:0] AWREGION
`endif
, input wire [AXI_WIDTH_SID-1:0] WID
, input wire [AXI_WIDTH_DA-1:0] WDATA
, input wire [AXI_WIDTH_DS-1:0] WSTRB
, input wire WLAST
, input wire WVALID
, output wire WREADY
, output wire [AXI_WIDTH_SID-1:0] BID
, output wire [ 1:0] BRESP
, output wire BVALID
, input wire BREADY
, input wire [AXI_WIDTH_SID-1:0] ARID
, input wire [AXI_WIDTH_AD-1:0] ARADDR
`ifdef AMBA_AXI4
, input wire [ 7:0] ARLEN
, input wire ARLOCK
`else
, input wire [ 3:0] ARLEN
, input wire [ 1:0] ARLOCK
`endif
, input wire [ 2:0] ARSIZE
, input wire [ 1:0] ARBURST
`ifdef AMBA_AXI_CACHE
, input wire [ 3:0] ARCACHE
`endif
`ifdef AMBA_AXI_PROT
, input wire [ 2:0] ARPROT
`endif
, input wire ARVALID
, output wire ARREADY
`ifdef AMBA_AXI4
, input wire [ 3:0] ARQOS
, input wire [ 3:0] ARREGION
`endif
, output wire [AXI_WIDTH_SID-1:0] RID
, output wire [AXI_WIDTH_DA-1:0] RDATA
, output wire [ 1:0] RRESP
, output wire RLAST
, output wire RVALID
, input wire RREADY
);
parameter AXI_WIDTH_CID= 4 // Channel ID width in bits
, AXI_WIDTH_ID = 4 // ID width in bits
, AXI_WIDTH_AD =32 // address width
, AXI_WIDTH_DA =32 // data width
, AXI_WIDTH_DS =(AXI_WIDTH_DA/8) // data strobe width
, AXI_WIDTH_DSB=4 // data strobe width
, AXI_WIDTH_SID=(AXI_WIDTH_CID+AXI_WIDTH_ID)
, P_FIFO_DEPTH=512 // use 512 in order to support 256-beat burst
;
//-------------------------------------------------------------------------
// synthesis attribute box_type ase128_axi "black_box"
//-------------------------------------------------------------------------
endmodule
| 7.819775 |
module aes128_core (
input i_clk,
input i_rst,
input i_flag, //1-encrypt,0-decrypt
input [127:0] i_key,
input i_key_en, //1-key init start
output o_key_ok, //1-key init done
input [127:0] i_din,
input i_din_en,
output [127:0] o_dout,
output o_dout_en
);
wire [128*11-1:0] s_exkey;
//KeyExpand
wire s_sbox_use_ke;
wire [ 31:0] s_sbox_din_ke;
wire [ 31:0] s_sbox_dout_ke;
//DataProcess
wire [ 127:0] s_sbox_din_dp;
wire [ 127:0] s_sbox_dout_dp;
//SubByte S-Box
wire [ 127:0] s_sbox_din;
wire [ 127:0] s_sbox_dout;
wire [ 127:0] s_sbox_dout_p;
wire [ 127:0] s_sbox_dout_n;
//
genvar i;
//key expand
aes128_keyex u_keyex (
.i_clk (i_clk ),
.i_rst (i_rst ),
.i_key (i_key ),
.i_key_en (i_key_en ),
.o_exkey (s_exkey ),
.o_key_ok (o_key_ok ),
.o_sbox_use (s_sbox_use_ke ),
.o_sbox_din (s_sbox_din_ke ),
.i_sbox_dout(s_sbox_dout_ke )
);
//data encrypt or decrypt
aes128_dpc u_dpc (
.i_clk (i_clk ),
.i_rst (i_rst ),
.i_flag (i_flag ),
.i_keyex (s_exkey ),
.i_din (i_din ),
.i_din_en (i_din_en ),
.o_dout (o_dout ),
.o_dout_en (o_dout_en ),
.o_sbox_din (s_sbox_din_dp ),
.i_sbox_dout(s_sbox_dout_dp )
);
assign s_sbox_din = s_sbox_use_ke ? {96'b0, s_sbox_din_ke} : s_sbox_din_dp;
assign s_sbox_dout_ke = s_sbox_dout_p[31:0];
assign s_sbox_dout_dp = i_flag ? s_sbox_dout_p : s_sbox_dout_n;
generate
for (i = 0; i < 16; i = i + 1) begin : INST_SBOX_P
aes_sbox_p u_sbox_p (
.din (s_sbox_din[8*i+7:8*i]),
.dout(s_sbox_dout_p[8*i+7:8*i])
);
end
for (i = 0; i < 16; i = i + 1) begin : INST_SBOX_N
aes_sbox_n u_sbox_n (
.din (s_sbox_din[8*i+7:8*i]),
.dout(s_sbox_dout_n[8*i+7:8*i])
);
end
endgenerate
endmodule
| 6.591978 |
module aes128_dpc (
input i_clk,
input i_rst,
input i_flag,
input [128*11-1:0] i_keyex,
input [ 127:0] i_din,
input i_din_en,
output [ 127:0] o_dout,
output o_dout_en,
output [ 127:0] o_sbox_din,
input [ 127:0] i_sbox_dout
);
localparam DLY = 1;
reg [ 3:0] r_count;
reg [127:0] r_ka;
reg [127:0] r_din;
wire [127:0] s_din;
wire [31:0] s_dina, s_dinb, s_dinc, s_dind;
wire [127:0] s_mixc_doutx;
wire [127:0] s_mixc_douty;
wire [127:0] s_mixc_din;
wire [127:0] s_ikey;
//byte select
function [7:0] BS;
input [31:0] D;
input [1:0] S;
begin
BS = (S==2'd3) ? D[31:24]:
((S==2'd2) ? D[23:16]:
((S==2'd1) ? D[15:8] :
((S==2'd0) ? D[7:0] :8'b0)));
end
endfunction
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_count <= #DLY 4'b0;
else if (i_din_en) r_count <= #DLY 4'd1;
else if (r_count == 4'd9) r_count <= #DLY 4'b0;
else if (r_count != 4'd0) r_count <= #DLY r_count + 4'd1;
end
always @(*) begin
if (i_flag) begin //encrypt
case (r_count)
4'd0: r_ka = i_keyex[128*10-1:128*9];
4'd1: r_ka = i_keyex[128*9-1:128*8];
4'd2: r_ka = i_keyex[128*8-1:128*7];
4'd3: r_ka = i_keyex[128*7-1:128*6];
4'd4: r_ka = i_keyex[128*6-1:128*5];
4'd5: r_ka = i_keyex[128*5-1:128*4];
4'd6: r_ka = i_keyex[128*4-1:128*3];
4'd7: r_ka = i_keyex[128*3-1:128*2];
4'd8: r_ka = i_keyex[128*2-1:128*1];
4'd9: r_ka = i_keyex[128*1-1:128*0];
endcase
end else begin //decrypt
case (r_count)
4'd9: r_ka = i_keyex[128*11-1:128*10];
4'd8: r_ka = i_keyex[128*10-1:128*9];
4'd7: r_ka = i_keyex[128*9-1:128*8];
4'd6: r_ka = i_keyex[128*8-1:128*7];
4'd5: r_ka = i_keyex[128*7-1:128*6];
4'd4: r_ka = i_keyex[128*6-1:128*5];
4'd3: r_ka = i_keyex[128*5-1:128*4];
4'd2: r_ka = i_keyex[128*4-1:128*3];
4'd1: r_ka = i_keyex[128*3-1:128*2];
4'd0: r_ka = i_keyex[128*2-1:128*1];
endcase
end
end
assign s_ikey = i_flag ? i_keyex[128*11-1:128*10] : i_keyex[128*1-1:128*0];
assign s_din = i_din_en ? i_din ^ s_ikey : r_din;
assign s_dina = s_din[127:96]; //col-1
assign s_dinb = s_din[95:64]; //col-2
assign s_dinc = s_din[63:32]; //col-3
assign s_dind = s_din[31:0]; //col-4
//ShiftRows & SubBytes
assign o_sbox_din[127:96] = i_flag ? {BS(
s_dina, 3
), BS(
s_dinb, 2
), BS(
s_dinc, 1
), BS(
s_dind, 0
)} : {BS(
s_dina, 3
), BS(
s_dind, 2
), BS(
s_dinc, 1
), BS(
s_dinb, 0
)};
assign o_sbox_din[95:64] = i_flag ? {BS(
s_dinb, 3
), BS(
s_dinc, 2
), BS(
s_dind, 1
), BS(
s_dina, 0
)} : {BS(
s_dinb, 3
), BS(
s_dina, 2
), BS(
s_dind, 1
), BS(
s_dinc, 0
)};
assign o_sbox_din[63:32] = i_flag ? {BS(
s_dinc, 3
), BS(
s_dind, 2
), BS(
s_dina, 1
), BS(
s_dinb, 0
)} : {BS(
s_dinc, 3
), BS(
s_dinb, 2
), BS(
s_dina, 1
), BS(
s_dind, 0
)};
assign o_sbox_din[31:0] = i_flag ? {BS(
s_dind, 3
), BS(
s_dina, 2
), BS(
s_dinb, 1
), BS(
s_dinc, 0
)} : {BS(
s_dind, 3
), BS(
s_dinc, 2
), BS(
s_dinb, 1
), BS(
s_dina, 0
)};
//
assign s_mixc_din = i_flag ? i_sbox_dout : i_sbox_dout ^ r_ka;
//MixColumns
aes_mixcol_w u_mixcol_1 (
.i_din (s_mixc_din[127:96] ),
.o_dout_x (s_mixc_doutx[127:96] ),
.o_dout_y (s_mixc_douty[127:96] )
);
aes_mixcol_w u_mixcol_2 (
.i_din (s_mixc_din[95:64] ),
.o_dout_x (s_mixc_doutx[95:64] ),
.o_dout_y (s_mixc_douty[95:64] )
);
aes_mixcol_w u_mixcol_3 (
.i_din (s_mixc_din[63:32] ),
.o_dout_x (s_mixc_doutx[63:32] ),
.o_dout_y (s_mixc_douty[63:32] )
);
aes_mixcol_w u_mixcol_4 (
.i_din (s_mixc_din[31:0] ),
.o_dout_x (s_mixc_doutx[31:0] ),
.o_dout_y (s_mixc_douty[31:0] )
);
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_din <= #DLY 128'b0;
else if (i_flag) r_din <= #DLY s_mixc_doutx ^ r_ka;
else r_din <= #DLY s_mixc_douty;
end
assign o_dout = i_sbox_dout ^ r_ka;
assign o_dout_en = (r_count == 4'd9) ? 1'b1 : 1'b0;
endmodule
| 7.338122 |
module aes128_keyex (
input i_clk,
input i_rst,
input [ 127:0] i_key, //key
input i_key_en, //key init flag
output [128*11-1:0] o_exkey, //round key
output o_key_ok, //key init ok
output o_sbox_use,
output [ 31:0] o_sbox_din,
input [ 31:0] i_sbox_dout
);
localparam DLY = 1;
wire [127:0] s_key;
reg [127:0] r_key;
reg [1279:0] r_exkey;
reg [3:0] r_count;
reg r_key_ok;
wire s_busy;
wire [127:0] s_exk;
reg [31:0] r_rcon;
//round left shift
function [31:0] ROL;
input [31:0] D;
begin
ROL = {D[23:0], D[31:24]};
end
endfunction
always @(*) begin
case (r_count)
4'd0: r_rcon = 32'h01000000;
4'd1: r_rcon = 32'h02000000;
4'd2: r_rcon = 32'h04000000;
4'd3: r_rcon = 32'h08000000;
4'd4: r_rcon = 32'h10000000;
4'd5: r_rcon = 32'h20000000;
4'd6: r_rcon = 32'h40000000;
4'd7: r_rcon = 32'h80000000;
4'd8: r_rcon = 32'h1B000000;
4'd9: r_rcon = 32'h36000000;
default: r_rcon = 32'b0;
endcase
end
assign s_key = i_key_en ? i_key : r_key;
//left shift 1|2 bits
assign o_sbox_use = s_busy;
assign o_sbox_din = ROL(s_key[31:0]);
//
assign s_exk[127:96] = s_key[127:96] ^ i_sbox_dout ^ r_rcon;
assign s_exk[95:64] = s_key[95:64] ^ s_exk[127:96];
assign s_exk[63:32] = s_key[63:32] ^ s_exk[95:64];
assign s_exk[31:0] = s_key[31:0] ^ s_exk[63:32];
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_key <= #DLY 128'b0;
else if (s_busy) r_key <= #DLY s_exk;
end
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) begin
r_exkey <= #DLY 1280'b0;
end else if (s_busy) begin
r_exkey <= #DLY{r_exkey[128*9-1:0], s_exk};
end
end
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_count <= #DLY 4'd0;
else if (i_key_en) r_count <= #DLY 4'd1;
else if (r_count == 4'd9) r_count <= #DLY 4'd0;
else if (r_count != 4'd0) r_count <= #DLY r_count + 4'd1;
end
assign s_busy = ((r_count != 5'd0) || (i_key_en == 1'b1)) ? 1'b1 : 1'b0;
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_key_ok <= #DLY 1'b0;
else if (r_count == 4'd9) r_key_ok <= #DLY 1'b1;
else if (i_key_en == 1'b1) r_key_ok <= #DLY 1'b0;
end
assign o_key_ok = r_key_ok & (~i_key_en);
assign o_exkey = {i_key, r_exkey};
endmodule
| 9.243566 |
module mixcolumns (
input [7:0] s0c,
s1c,
s2c,
s3c,
output [7:0] m0c,
m1c,
m2c,
m3c
);
// ==============================================
// Equasions
// ==============================================
assign m0c = mul4x8(
{4'h2}, s0c
) ^ mul4x8(
{4'h3}, s1c
) ^ mul4x8(
{4'h1}, s2c
) ^ mul4x8(
{4'h1}, s3c
);
assign m1c = mul4x8(
{4'h1}, s0c
) ^ mul4x8(
{4'h2}, s1c
) ^ mul4x8(
{4'h3}, s2c
) ^ mul4x8(
{4'h1}, s3c
);
assign m2c = mul4x8(
{4'h1}, s0c
) ^ mul4x8(
{4'h1}, s1c
) ^ mul4x8(
{4'h2}, s2c
) ^ mul4x8(
{4'h3}, s3c
);
assign m3c = mul4x8(
{4'h3}, s0c
) ^ mul4x8(
{4'h1}, s1c
) ^ mul4x8(
{4'h1}, s2c
) ^ mul4x8(
{4'h2}, s3c
);
// Multiplied
function [7:0] mul4x8;
input [3:0] mx;
input [7:0] sc;
reg [7:0] sxm0, sxm1, sxm2, sxm3;
reg [10:0] temp;
reg [7:0] c0, c1, c2; // Carry
begin
sxm0 = sc & {8{mx[0]}};
sxm1 = sc & {8{mx[1]}};
sxm2 = sc & {8{mx[2]}};
sxm3 = sc & {8{mx[3]}};
temp = {3'b000, sxm0} ^ {2'b00, sxm1, 1'b0} ^ {1'b00, sxm2, 2'b00} ^ {sxm3, 3'b000};
c0 = (temp[8] == 1'b1) ? 8'h1B : 8'h00;
c1 = (temp[9] == 1'b1) ? (8'h1B << 1) : 8'h00;
c2 = (temp[10] == 1'b1) ? (8'h1B << 2) : 8'h00;
mul4x8 = temp[7:0] ^ c0 ^ c1 ^ c2;
end
endfunction
endmodule
| 7.197813 |
module inv_mixcolumn (
input [7:0] s0c,
s1c,
s2c,
s3c,
output [7:0] m0c,
m1c,
m2c,
m3c
);
// ==============================================
// Equasions
// ==============================================
assign m0c = mul4x8(
{4'he}, s0c
) ^ mul4x8(
{4'hb}, s1c
) ^ mul4x8(
{4'hd}, s2c
) ^ mul4x8(
{4'h9}, s3c
);
assign m1c = mul4x8(
{4'h9}, s0c
) ^ mul4x8(
{4'he}, s1c
) ^ mul4x8(
{4'hb}, s2c
) ^ mul4x8(
{4'hd}, s3c
);
assign m2c = mul4x8(
{4'hd}, s0c
) ^ mul4x8(
{4'h9}, s1c
) ^ mul4x8(
{4'he}, s2c
) ^ mul4x8(
{4'hb}, s3c
);
assign m3c = mul4x8(
{4'hb}, s0c
) ^ mul4x8(
{4'hd}, s1c
) ^ mul4x8(
{4'h9}, s2c
) ^ mul4x8(
{4'he}, s3c
);
function [7:0] mul4x8;
input [3:0] mx;
input [7:0] sc;
reg [7:0] sxm0, sxm1, sxm2, sxm3;
reg [10:0] temp;
reg [7:0] c0, c1, c2;
begin
sxm0 = sc & {8{mx[0]}};
sxm1 = sc & {8{mx[1]}};
sxm2 = sc & {8{mx[2]}};
sxm3 = sc & {8{mx[3]}};
temp = {3'b000, sxm0} ^ {2'b00, sxm1, 1'b0} ^ {1'b00, sxm2, 2'b00} ^ {sxm3, 3'b000};
c0 = (temp[8] == 1'b1) ? 8'h1B : 8'h00;
c1 = (temp[9] == 1'b1) ? (8'h1B << 1) : 8'h00;
c2 = (temp[10] == 1'b1) ? (8'h1B << 2) : 8'h00;
mul4x8 = temp[7:0] ^ c0 ^ c1 ^ c2;
end
endfunction
endmodule
| 6.598097 |
module: AES128
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module AES128_VTF;
// Inputs
reg ProgramSelector;
reg [127:0] UserText;
reg [127:0] Key;
reg ReadyKey;
reg ReadRy;
reg WriteRy;
reg Clk;
reg Rst;
// Outputs
wire ReadEn;
wire WriteEn;
wire [127:0] Result;
// Instantiate the Unit Under Test (UUT)
AES128 uut (
.ProgramSelector(ProgramSelector),
.UserText(UserText),
.Key(Key),
.ReadyKey(ReadyKey),
.ReadRy(ReadRy),
.WriteRy(WriteRy),
.Clk(Clk),
.Rst(Rst),
.ReadEn(ReadEn),
.WriteEn(WriteEn),
.Result(Result)
);
// Clock generator
always
begin
#10 Clk = ~Clk; #10 Clk = ~Clk;
end
initial begin
// Initialize Inputs
ProgramSelector = 0;
UserText = 0;
Key = 0;
ReadyKey = 0;
ReadRy = 0;
WriteRy = 0;
Clk = 0;
Rst = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
ProgramSelector = 1;
Rst = 1;
#30
Rst = 0;
#90
UserText = 128'h328831e0435a3137f6309807a88da234;
Key = 128'h2b28ab097eaef7cf15d2154f16a6883c;
ReadyKey = 1;
ReadRy = 1;
end
endmodule
| 6.672252 |
module one_round (
clk,
state_in,
key,
state_out
);
input clk;
input [127:0] state_in, key;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33,
k0, k1, k2, k3;
assign {k0, k1, k2, k3} = key;
assign {s0, s1, s2, s3} = state_in;
table_lookup
t0 (
clk,
s0,
p00,
p01,
p02,
p03
),
t1 (
clk,
s1,
p10,
p11,
p12,
p13
),
t2 (
clk,
s2,
p20,
p21,
p22,
p23
),
t3 (
clk,
s3,
p30,
p31,
p32,
p33
);
assign z0 = p00 ^ p11 ^ p22 ^ p33 ^ k0;
assign z1 = p03 ^ p10 ^ p21 ^ p32 ^ k1;
assign z2 = p02 ^ p13 ^ p20 ^ p31 ^ k2;
assign z3 = p01 ^ p12 ^ p23 ^ p30 ^ k3;
always @(posedge clk) state_out <= {z0, z1, z2, z3};
endmodule
| 7.018166 |
module final_round (
clk,
state_in,
key_in,
state_out
);
input clk;
input [127:0] state_in;
input [127:0] key_in;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3, z0, z1, z2, z3, k0, k1, k2, k3;
wire [7:0] p00, p01, p02, p03, p10, p11, p12, p13, p20, p21, p22, p23, p30, p31, p32, p33;
assign {k0, k1, k2, k3} = key_in;
assign {s0, s1, s2, s3} = state_in;
S4
S4_1 (
clk,
s0,
{p00, p01, p02, p03}
),
S4_2 (
clk,
s1,
{p10, p11, p12, p13}
),
S4_3 (
clk,
s2,
{p20, p21, p22, p23}
),
S4_4 (
clk,
s3,
{p30, p31, p32, p33}
);
assign z0 = {p00, p11, p22, p33} ^ k0;
assign z1 = {p10, p21, p32, p03} ^ k1;
assign z2 = {p20, p31, p02, p13} ^ k2;
assign z3 = {p30, p01, p12, p23} ^ k3;
always @(posedge clk) state_out <= {z0, z1, z2, z3};
endmodule
| 7.609225 |
module S4 (
clk,
in,
out
);
input clk;
input [31:0] in;
output [31:0] out;
S
S_0 (
clk,
in[31:24],
out[31:24]
),
S_1 (
clk,
in[23:16],
out[23:16]
),
S_2 (
clk,
in[15:8],
out[15:8]
),
S_3 (
clk,
in[7:0],
out[7:0]
);
endmodule
| 6.592394 |
module T (
clk,
in,
out
);
input clk;
input [7:0] in;
output [31:0] out;
S s0 (
clk,
in,
out[31:24]
);
assign out[23:16] = out[31:24];
xS s4 (
clk,
in,
out[7:0]
);
assign out[15:8] = out[23:16] ^ out[7:0];
endmodule
| 6.667023 |
module aes192_keyex (
input i_clk,
input i_rst,
input [ 191:0] i_key, //key
input i_key_en, //key init flag
output [128*13-1:0] o_exkey, //round key(52 words)
output o_key_ok, //key init ok
output o_sbox_use,
output [ 31:0] o_sbox_din,
input [ 31:0] i_sbox_dout
);
localparam DLY = 1;
wire [191:0] s_key;
reg [191:0] r_key;
reg [1535:0] r_exkey; //192*8
reg [3:0] r_count;
reg r_key_ok;
wire s_busy;
wire [191:0] s_exk;
reg [31:0] r_rcon;
//round left shift
function [31:0] ROL;
input [31:0] D;
begin
ROL = {D[23:0], D[31:24]};
end
endfunction
always @(*) begin
case (r_count)
4'd0: r_rcon = 32'h01000000;
4'd1: r_rcon = 32'h02000000;
4'd2: r_rcon = 32'h04000000;
4'd3: r_rcon = 32'h08000000;
4'd4: r_rcon = 32'h10000000;
4'd5: r_rcon = 32'h20000000;
4'd6: r_rcon = 32'h40000000;
4'd7: r_rcon = 32'h80000000;
4'd8: r_rcon = 32'h1B000000;
4'd9: r_rcon = 32'h36000000;
default: r_rcon = 32'b0;
endcase
end
assign s_key = i_key_en ? i_key : r_key;
//left shift 1|2 bits
assign o_sbox_use = s_busy;
assign o_sbox_din = ROL(s_key[31:0]);
//
assign s_exk[191:160] = s_key[191:160]^i_sbox_dout^r_rcon;
assign s_exk[159:128] = s_key[159:128]^s_exk[191:160];
assign s_exk[127:96] = s_key[127:96]^s_exk[159:128];
assign s_exk[95:64] = s_key[95:64]^s_exk[127:96];
assign s_exk[63:32] = s_key[63:32]^s_exk[95:64];
assign s_exk[31:0] = s_key[31:0]^s_exk[63:32];
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_key <= #DLY 192'b0;
else if (s_busy) r_key <= #DLY s_exk;
end
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) begin
r_exkey <= #DLY 1536'b0;
end else if (s_busy) begin
r_exkey <= #DLY{r_exkey[192*7-1:0], s_exk};
end
end
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_count <= #DLY 4'd0;
else if (i_key_en) r_count <= #DLY 4'd1;
else if (r_count == 4'd7) r_count <= #DLY 4'd0;
else if (r_count != 4'd0) r_count <= #DLY r_count + 4'd1;
end
assign s_busy = ((r_count != 5'd0) || (i_key_en == 1'b1)) ? 1'b1 : 1'b0;
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_key_ok <= #DLY 1'b0;
else if (r_count == 4'd7) r_key_ok <= #DLY 1'b1;
else if (i_key_en == 1'b1) r_key_ok <= #DLY 1'b0;
end
assign o_key_ok = r_key_ok & (~i_key_en);
assign o_exkey = {i_key, r_exkey[1535:64]};
endmodule
| 9.121356 |
module AES_DEC (
input [127:0] Din,
input [127:0] Key,
output [127:0] Dout,
input Datardy,
input Keyrdy,
input RST,
input EN,
input CLK,
output BSY,
output Dvld
);
reg [127:0] Dreg;
reg [127:0] Kreg;
reg [127:0] KregX;
reg [ 9:0] Rreg;
reg Dvldreg, BSYreg;
wire [127:0] Dnext, Knext;
DecCore DC (
Dreg,
KregX,
Rreg,
Dnext,
Knext
);
assign Dvld = Dvldreg;
assign Dout = Dreg;
assign BSY = BSYreg;
always @(posedge CLK) begin
if (RST == 0) begin
Rreg <= 10'b1000000000;
Dvldreg <= 0;
BSYreg <= 0;
end else if (EN == 1) begin
if (BSYreg == 0) begin
if (Keyrdy == 1) begin
Kreg <= Key;
KregX <= Key;
Dvldreg <= 0;
end else if (Datardy == 1) begin
Rreg <= {Rreg[0], Rreg[9:1]};
KregX <= Knext;
Dreg <= Din ^ Kreg;
Dvldreg <= 0;
BSYreg <= 1;
end
end else begin
Dreg <= Dnext;
if (Rreg[9] == 1) begin
KregX <= Kreg;
Dvldreg <= 1;
BSYreg <= 0;
end else begin
Rreg <= {Rreg[0], Rreg[9:1]};
KregX <= Knext;
end
end
end
end
endmodule
| 6.571574 |
module one_round (
clk,
state_in,
key,
state_out
);
input clk;
input [127:0] state_in, key;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33,
k0, k1, k2, k3;
assign {k0, k1, k2, k3} = key;
assign {s0, s1, s2, s3} = state_in;
table_lookup
t0 (
clk,
s0,
p00,
p01,
p02,
p03
),
t1 (
clk,
s1,
p10,
p11,
p12,
p13
),
t2 (
clk,
s2,
p20,
p21,
p22,
p23
),
t3 (
clk,
s3,
p30,
p31,
p32,
p33
);
assign z0 = p00 ^ p11 ^ p22 ^ p33 ^ k0;
assign z1 = p03 ^ p10 ^ p21 ^ p32 ^ k1;
assign z2 = p02 ^ p13 ^ p20 ^ p31 ^ k2;
assign z3 = p01 ^ p12 ^ p23 ^ p30 ^ k3;
always @(posedge clk) state_out <= {z0, z1, z2, z3};
endmodule
| 7.018166 |
module final_round (
clk,
state_in,
key_in,
state_out
);
input clk;
input [127:0] state_in;
input [127:0] key_in;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3, z0, z1, z2, z3, k0, k1, k2, k3;
wire [7:0] p00, p01, p02, p03, p10, p11, p12, p13, p20, p21, p22, p23, p30, p31, p32, p33;
assign {k0, k1, k2, k3} = key_in;
assign {s0, s1, s2, s3} = state_in;
S4
S4_1 (
clk,
s0,
{p00, p01, p02, p03}
),
S4_2 (
clk,
s1,
{p10, p11, p12, p13}
),
S4_3 (
clk,
s2,
{p20, p21, p22, p23}
),
S4_4 (
clk,
s3,
{p30, p31, p32, p33}
);
assign z0 = {p00, p11, p22, p33} ^ k0;
assign z1 = {p10, p21, p32, p03} ^ k1;
assign z2 = {p20, p31, p02, p13} ^ k2;
assign z3 = {p30, p01, p12, p23} ^ k3;
always @(posedge clk) state_out <= {z0, z1, z2, z3};
endmodule
| 7.609225 |
module S4 (
clk,
in,
out
);
input clk;
input [31:0] in;
output [31:0] out;
S
S_0 (
clk,
in[31:24],
out[31:24]
),
S_1 (
clk,
in[23:16],
out[23:16]
),
S_2 (
clk,
in[15:8],
out[15:8]
),
S_3 (
clk,
in[7:0],
out[7:0]
);
endmodule
| 6.592394 |
module T (
clk,
in,
out
);
input clk;
input [7:0] in;
output [31:0] out;
S s0 (
clk,
in,
out[31:24]
);
assign out[23:16] = out[31:24];
xS s4 (
clk,
in,
out[7:0]
);
assign out[15:8] = out[23:16] ^ out[7:0];
endmodule
| 6.667023 |
module aes256_keyex (
input i_clk,
input i_rst,
input [ 255:0] i_key, //key
input i_key_en, //key init flag
output [128*15-1:0] o_exkey, //round key(60 words)
output o_key_ok, //key init ok
output o_sbox_use,
output [ 63:0] o_sbox_din,
input [ 63:0] i_sbox_dout
);
localparam DLY = 1;
wire [255:0] s_key;
reg [255:0] r_key;
reg [32*56-1:0] r_exkey; //56 words
reg [3:0] r_count;
reg r_key_ok;
wire s_busy;
wire [255:0] s_exk;
reg [31:0] r_rcon;
//round left shift 8bit
function [31:0] ROL;
input [31:0] D;
begin
ROL = {D[23:0], D[31:24]};
end
endfunction
//round left shift 8bit
function [31:0] ROR;
input [31:0] D;
begin
ROR = {D[7:0], D[31:8]};
end
endfunction
always @(*) begin
case (r_count)
4'd0: r_rcon = 32'h01000000;
4'd1: r_rcon = 32'h02000000;
4'd2: r_rcon = 32'h04000000;
4'd3: r_rcon = 32'h08000000;
4'd4: r_rcon = 32'h10000000;
4'd5: r_rcon = 32'h20000000;
4'd6: r_rcon = 32'h40000000;
4'd7: r_rcon = 32'h80000000;
4'd8: r_rcon = 32'h1B000000;
4'd9: r_rcon = 32'h36000000;
default: r_rcon = 32'b0;
endcase
end
assign s_key = i_key_en ? i_key : r_key;
//left shift 1|2 bits
assign o_sbox_use = s_busy;
assign o_sbox_din[31:0] = ROL(s_key[31:0]);
assign o_sbox_din[63:32] = ROL(ROR(s_exk[159:128]));
//
assign s_exk[255:224] = s_key[255:224]^i_sbox_dout[31:0]^r_rcon;
assign s_exk[223:192] = s_key[223:192]^s_exk[255:224];
assign s_exk[191:160] = s_key[191:160]^s_exk[223:192];
assign s_exk[159:128] = s_key[159:128]^s_exk[191:160];
assign s_exk[127:96] = s_key[127:96]^i_sbox_dout[63:32];
assign s_exk[95:64] = s_key[95:64]^s_exk[127:96];
assign s_exk[63:32] = s_key[63:32]^s_exk[95:64];
assign s_exk[31:0] = s_key[31:0]^s_exk[63:32];
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_key <= #DLY 256'b0;
else if (s_busy) r_key <= #DLY s_exk;
end
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) begin
r_exkey <= #DLY 1536'b0;
end else if (s_busy) begin
r_exkey <= #DLY{r_exkey[256*6-1:0], s_exk};
end
end
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_count <= #DLY 4'd0;
else if (i_key_en) r_count <= #DLY 4'd1;
else if (r_count == 4'd6) r_count <= #DLY 4'd0;
else if (r_count != 4'd0) r_count <= #DLY r_count + 4'd1;
end
assign s_busy = ((r_count != 5'd0) || (i_key_en == 1'b1)) ? 1'b1 : 1'b0;
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_key_ok <= #DLY 1'b0;
else if (r_count == 4'd6) r_key_ok <= #DLY 1'b1;
else if (i_key_en == 1'b1) r_key_ok <= #DLY 1'b0;
end
assign o_key_ok = r_key_ok & (~i_key_en);
assign o_exkey = {i_key, r_exkey[32*56-1:128]};
endmodule
| 8.883369 |
module AES_DEC (
input [127:0] Din,
input [127:0] Key,
output [127:0] Dout,
input Datardy,
input Keyrdy,
input RST,
input EN,
input CLK,
output BSY,
output Dvld
);
reg [127:0] Dreg;
reg [127:0] Kreg;
reg [127:0] KregX;
reg [ 9:0] Rreg;
reg Dvldreg, BSYreg;
wire [127:0] Dnext, Knext;
DecCore DC (
Dreg,
KregX,
Rreg,
Dnext,
Knext
);
assign Dvld = Dvldreg;
assign Dout = Dreg;
assign BSY = BSYreg;
always @(posedge CLK) begin
if (RST == 0) begin
Rreg <= 10'b1000000000;
Dvldreg <= 0;
BSYreg <= 0;
end else if (EN == 1) begin
if (BSYreg == 0) begin
if (Keyrdy == 1) begin
Kreg <= Key;
KregX <= Key;
Dvldreg <= 0;
end else if (Datardy == 1) begin
Rreg <= {Rreg[0], Rreg[9:1]};
KregX <= Knext;
Dreg <= Din ^ Kreg;
Dvldreg <= 0;
BSYreg <= 1;
end
end else begin
Dreg <= Dnext;
if (Rreg[9] == 1) begin
KregX <= Kreg;
Dvldreg <= 1;
BSYreg <= 0;
end else begin
Rreg <= {Rreg[0], Rreg[9:1]};
KregX <= Knext;
end
end
end
end
endmodule
| 6.571574 |
module AES_CH (
input [127:0] Din,
input [127:0] Key,
output [127:0] Dout,
input Datardy,
input Keyrdy,
input RST,
input EN,
input MODE,
input CLK,
output BSY,
output Dvld
);
wire [127:0] Dout_E;
wire [127:0] Dout_D;
reg [127:0] Dreg;
reg EN_E;
reg EN_D;
AES_ENC AES_ENC (
Din,
Key,
Dout_E,
Datardy,
Keyrdy,
RST,
EN_E,
CLK,
BSY,
Dvld
);
AES_DEC AES_DEC (
Din,
Key,
Dout_D,
Datardy,
Keyrdy,
RST,
EN_D,
CLK,
BSY,
Dvld
);
assign Dout = Dreg;
//MODE 0 = ENC,1 = DEC
always @(*) begin
EN_E <= (EN & (!MODE));
EN_D <= (EN & (MODE));
if (MODE == 0) begin
Dreg = Dout_E;
end else if (MODE == 1) begin
Dreg = Dout_D;
end
end
endmodule
| 6.834951 |
module AESByteSubColumn (
input clk,
input en,
input [31:0] addr,
output [31:0] data
);
SBoxRam sbox1 (
.clk (clk),
.en (en),
.addr(addr[7:0]),
.data(data[7:0])
);
SBoxRam sbox2 (
.clk (clk),
.en (en),
.addr(addr[15:8]),
.data(data[15:8])
);
SBoxRam sbox3 (
.clk (clk),
.en (en),
.addr(addr[23:16]),
.data(data[23:16])
);
SBoxRam sbox4 (
.clk (clk),
.en (en),
.addr(addr[31:24]),
.data(data[31:24])
);
endmodule
| 6.960147 |
module AESByteSub (
input clk,
input en,
input [127:0] addr,
output [127:0] data
);
AESByteSubColumn subcol1 (
.clk (clk),
.en (en),
.addr(addr[127:96]),
.data(data[127:96])
);
AESByteSubColumn subcol2 (
.clk (clk),
.en (en),
.addr(addr[95:64]),
.data(data[95:64])
);
AESByteSubColumn subcol3 (
.clk (clk),
.en (en),
.addr(addr[63:32]),
.data(data[63:32])
);
AESByteSubColumn subcol4 (
.clk (clk),
.en (en),
.addr(addr[31:0]),
.data(data[31:0])
);
endmodule
| 6.963143 |
module AESByteSubTestBench;
reg clk = 0;
reg en = 1;
reg [31:0] addr = 0;
wire [31:0] data;
initial #10000 $stop;
always #5 clk = ~clk;
always #10 addr = addr + 1;
AESByteSubColumn bytesubcol (
.clk (clk),
.en (en),
.addr(addr),
.data(data)
);
initial $monitor("at time %t, addr=%h, data=%h", $time, addr, data);
endmodule
| 6.700705 |
module aescipher (
clk,
datain,
key,
dataout
);
input clk;
input [127:0] datain;
input [127:0] key;
output [127:0] dataout;
wire [127:0] r0_out;
wire [127:0] r1_out, r2_out, r3_out, r4_out, r5_out, r6_out, r7_out, r8_out, r9_out;
wire [127:0] keyout1, keyout2, keyout3, keyout4, keyout5, keyout6, keyout7, keyout8, keyout9;
assign r0_out = datain ^ key;
rounds r1 (
.clk(clk),
.rc(4'b0000),
.data(r0_out),
.keyin(key),
.keyout(keyout1),
.rndout(r1_out)
);
rounds r2 (
.clk(clk),
.rc(4'b0001),
.data(r1_out),
.keyin(keyout1),
.keyout(keyout2),
.rndout(r2_out)
);
rounds r3 (
.clk(clk),
.rc(4'b0010),
.data(r2_out),
.keyin(keyout2),
.keyout(keyout3),
.rndout(r3_out)
);
rounds r4 (
.clk(clk),
.rc(4'b0011),
.data(r3_out),
.keyin(keyout3),
.keyout(keyout4),
.rndout(r4_out)
);
rounds r5 (
.clk(clk),
.rc(4'b0100),
.data(r4_out),
.keyin(keyout4),
.keyout(keyout5),
.rndout(r5_out)
);
rounds r6 (
.clk(clk),
.rc(4'b0101),
.data(r5_out),
.keyin(keyout5),
.keyout(keyout6),
.rndout(r6_out)
);
rounds r7 (
.clk(clk),
.rc(4'b0110),
.data(r6_out),
.keyin(keyout6),
.keyout(keyout7),
.rndout(r7_out)
);
rounds r8 (
.clk(clk),
.rc(4'b0111),
.data(r7_out),
.keyin(keyout7),
.keyout(keyout8),
.rndout(r8_out)
);
rounds r9 (
.clk(clk),
.rc(4'b1000),
.data(r8_out),
.keyin(keyout8),
.keyout(keyout9),
.rndout(r9_out)
);
rounndlast r10 (
.clk(clk),
.rc(4'b1001),
.rin(r9_out),
.keylastin(keyout9),
.fout(dataout)
);
endmodule
| 6.919137 |
module AesCore (
clk,
i_data,
keyIn,
o_data,
cipherkey
);
input clk;
input [127:0] i_data;
input [127:0] keyIn;
output [127:0] o_data;
output [127:0] cipherkey;
wire [127:0] state0;
wire [127:0] rnd1, rnd2, rnd3, rnd4, rnd5, rnd6, rnd7, rnd8, rnd9;
wire [127:0] keyOut1, keyOut2, keyOut3, keyOut4, keyOut5, keyOut6, keyOut7, keyOut8, keyOut9;
assign state0 = i_data ^ keyIn;
//1-9 rounds
rounds9 r1 (
.clk(clk),
.rcRound(4'd0),
.keyx(keyIn),
.keyOut(keyOut1),
.state1(state0),
.rndstate(rnd1)
);
rounds9 r2 (
.clk(clk),
.rcRound(4'd1),
.keyx(keyOut1),
.keyOut(keyOut2),
.state1(rnd1),
.rndstate(rnd2)
);
rounds9 r3 (
.clk(clk),
.rcRound(4'd2),
.keyx(keyOut2),
.keyOut(keyOut3),
.state1(rnd2),
.rndstate(rnd3)
);
rounds9 r4 (
.clk(clk),
.rcRound(4'd3),
.keyx(keyOut3),
.keyOut(keyOut4),
.state1(rnd3),
.rndstate(rnd4)
);
rounds9 r5 (
.clk(clk),
.rcRound(4'd4),
.keyx(keyOut4),
.keyOut(keyOut5),
.state1(rnd4),
.rndstate(rnd5)
);
rounds9 r6 (
.clk(clk),
.rcRound(4'd5),
.keyx(keyOut5),
.keyOut(keyOut6),
.state1(rnd5),
.rndstate(rnd6)
);
rounds9 r7 (
.clk(clk),
.rcRound(4'd6),
.keyx(keyOut6),
.keyOut(keyOut7),
.state1(rnd6),
.rndstate(rnd7)
);
rounds9 r8 (
.clk(clk),
.rcRound(4'd7),
.keyx(keyOut7),
.keyOut(keyOut8),
.state1(rnd7),
.rndstate(rnd8)
);
rounds9 r9 (
.clk(clk),
.rcRound(4'd8),
.keyx(keyOut8),
.keyOut(keyOut9),
.state1(rnd8),
.rndstate(rnd9)
);
//last round
last r10 (
.clk(clk),
.rcRound(4'd9),
.key9(keyOut9),
.keyOut(cipherkey),
.r9(rnd9),
.stateout(o_data)
);
endmodule
| 8.405321 |
module InvAesCore (
clk,
cipherText,
cipherkey,
retData,
origkey
);
input clk;
input [127:0] cipherText;
input [127:0] cipherkey;
output [127:0] retData;
output [127:0] origkey;
wire [127:0] statel;
wire [127:0] rr10, rr9, rr8, rr7, rr6, rr5, rr4, rr3, rr2;
wire [127:0] keyout1, keyout2, keyout3, keyout4, keyout5, keyout6, keyout7, keyout8, keyout9;
assign statel = cipherText ^ cipherkey;
//invlast round
inv_last d10 (
.clk(clk),
.rcRound(4'd9),
.keyy(cipherkey),
.keyOut(keyout9),
.state10(statel),
.x(rr10)
);
inv_rounds9 d9 (
.clk(clk),
.rcRound(4'd8),
.ko(keyout9),
.keyOut(keyout8),
.invRnd9state(rr10),
.invRndState(rr9)
);
inv_rounds9 d8 (
.clk(clk),
.rcRound(4'd7),
.ko(keyout8),
.keyOut(keyout7),
.invRnd9state(rr9),
.invRndState(rr8)
);
inv_rounds9 d7 (
.clk(clk),
.rcRound(4'd6),
.ko(keyout7),
.keyOut(keyout6),
.invRnd9state(rr8),
.invRndState(rr7)
);
inv_rounds9 d6 (
.clk(clk),
.rcRound(4'd5),
.ko(keyout6),
.keyOut(keyout5),
.invRnd9state(rr7),
.invRndState(rr6)
);
inv_rounds9 d5 (
.clk(clk),
.rcRound(4'd4),
.ko(keyout5),
.keyOut(keyout4),
.invRnd9state(rr6),
.invRndState(rr5)
);
inv_rounds9 d4 (
.clk(clk),
.rcRound(4'd3),
.ko(keyout4),
.keyOut(keyout3),
.invRnd9state(rr5),
.invRndState(rr4)
);
inv_rounds9 d3 (
.clk(clk),
.rcRound(4'd2),
.ko(keyout3),
.keyOut(keyout2),
.invRnd9state(rr4),
.invRndState(rr3)
);
inv_rounds9 d2 (
.clk(clk),
.rcRound(4'd1),
.ko(keyout2),
.keyOut(keyout1),
.invRnd9state(rr3),
.invRndState(rr2)
);
inv_rounds9 d1 (
.clk(clk),
.rcRound(4'd0),
.ko(keyout1),
.keyOut(origkey),
.invRnd9state(rr2),
.invRndState(retData)
);
endmodule
| 6.688109 |
module AESDecrypt_tb ();
reg [127:0] dataIn, dataIn192, dataIn256;
reg [127:0] key;
reg [191:0] key192;
reg [255:0] key256;
reg clk = 0;
wire [127:0] dataOut, dataOut192, dataOut256;
AESDecrypt aesDecrypt (
dataIn,
key,
clk,
dataOut
);
genvar i;
AESDecrypt #(
.Nk(6),
.Nr(12)
) aesDecrypt192 (
dataIn192,
key192,
clk,
dataOut192
);
AESDecrypt #(
.Nk(8),
.Nr(14)
) aesDecrypt256 (
dataIn256,
key256,
clk,
dataOut256
);
always begin
#10 clk = ~clk;
end
initial begin
dataIn = 128'h69c4e0d86a7b0430d8cdb78070b4c55a;
key = 128'h000102030405060708090a0b0c0d0e0f;
dataIn192 = 128'hdda97ca4864cdfe06eaf70a0ec0d7191;
key192 = 192'h000102030405060708090a0b0c0d0e0f1011121314151617;
dataIn256 = 128'h8ea2b7ca516745bfeafc49904b496089;
key256 = 256'h000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f;
#10000;
$display("First InvMixCol : %h\n", aesDecrypt.outMixCol[9]);
$display("Second InvShiftRow : %h\n", aesDecrypt.outShiftRows[9]);
$display("Second InvSubBytes : %h\n", aesDecrypt.outSBytes[9]);
$display("Second RoundKey : %h\n", aesDecrypt.state[9]);
$display("Second InvCol : %h\n", aesDecrypt.outMixCol[8]);
$display("bef InvCol : %h\n", aesDecrypt.outMixCol[1]);
$display("Last InvCol : %h\n", aesDecrypt.outMixCol[0]);
$display("dataOut : %h\n", dataOut);
// $display("Key 1 : %h\n", aesDecrypt.keysOut[0 * 128: 0 * 128 + 127]);
// $display("Key 1 : %h\n", aesDecrypt.keysOut[1 * 128: 1 * 128 + 127]);
// $display("Key 1 : %h\n", aesDecrypt.keysOut[2 * 128: 2 * 128 + 127]);
// $display("Key 1 : %h\n", aesDecrypt.keysOut[3 * 128: 3 * 128 + 127]);
$display("dataOut : %h\n", dataOut192);
$display("dataOut : %h\n", dataOut256);
$finish;
end
endmodule
| 6.987142 |
module aesEncryption (
clk,
datain,
key,
dataout
);
input clk;
input [127:0] datain;
input [127:0] key;
output [127:0] dataout;
wire [127:0] r0_out;
wire [127:0] r1_out, r2_out, r3_out, r4_out, r5_out, r6_out, r7_out, r8_out, r9_out;
wire [127:0] keyout1, keyout2, keyout3, keyout4, keyout5, keyout6, keyout7, keyout8, keyout9;
assign r0_out = datain ^ key;
rounds r1 (
.clk(clk),
.rc(4'b0000),
.data(r0_out),
.keyin(key),
.keyout(keyout1),
.rndout(r1_out)
);
rounds r2 (
.clk(clk),
.rc(4'b0001),
.data(r1_out),
.keyin(keyout1),
.keyout(keyout2),
.rndout(r2_out)
);
rounds r3 (
.clk(clk),
.rc(4'b0010),
.data(r2_out),
.keyin(keyout2),
.keyout(keyout3),
.rndout(r3_out)
);
rounds r4 (
.clk(clk),
.rc(4'b0011),
.data(r3_out),
.keyin(keyout3),
.keyout(keyout4),
.rndout(r4_out)
);
rounds r5 (
.clk(clk),
.rc(4'b0100),
.data(r4_out),
.keyin(keyout4),
.keyout(keyout5),
.rndout(r5_out)
);
rounds r6 (
.clk(clk),
.rc(4'b0101),
.data(r5_out),
.keyin(keyout5),
.keyout(keyout6),
.rndout(r6_out)
);
rounds r7 (
.clk(clk),
.rc(4'b0110),
.data(r6_out),
.keyin(keyout6),
.keyout(keyout7),
.rndout(r7_out)
);
rounds r8 (
.clk(clk),
.rc(4'b0111),
.data(r7_out),
.keyin(keyout7),
.keyout(keyout8),
.rndout(r8_out)
);
rounds r9 (
.clk(clk),
.rc(4'b1000),
.data(r8_out),
.keyin(keyout8),
.keyout(keyout9),
.rndout(r9_out)
);
rounndlast r10 (
.clk(clk),
.rc(4'b1001),
.rin(r9_out),
.keylastin(keyout9),
.fout(dataout)
);
endmodule
| 7.453735 |
module AESOneRound (
in,out,roundkey,dec,nomix,subbyteonly,sub_in,sub_out,//nomix = 1 when no mixcolumn
);
input [127:0] in,roundkey;
input dec;
input subbyteonly;
input [31:0] sub_in;
output [31:0] sub_out;
output reg [127:0] out;
input nomix;
// input clk;
reg [127:0] key_in ,inv_sh_in ,mix_in ,sh_in;
wire [127:0] key_out,inv_sh_out,mix_out,sh_out,mix_out_inv;
reg [31:0] sub32_in;
wire [31:0] sub32_out;
reg [95:0] sub96_in;
wire [95:0] sub96_out;
assign sub_out = sub32_out;
wire sub32_dec = dec & (!(subbyteonly));
AddRoundKey add(.in(key_in),.out(key_out),.key(roundkey));
SubByte_32 sub32(.in(sub32_in),.out(sub32_out),.dec(sub32_dec));
SubByte_96 sub96(.in(sub96_in),.out(sub96_out),.dec(dec));
ShiftRow shift(.in(sh_in),.out(sh_out));
InvShiftRow invshift(.in(inv_sh_in),.out(inv_sh_out));
MixColumn mix(.in(mix_in),.out(mix_out),.out_inv(mix_out_inv));
always @(*) begin
if(nomix)
inv_sh_in = key_out;
else
inv_sh_in = mix_out_inv;
if(subbyteonly)
sub32_in = sub_in;
else begin
if(dec)
sub32_in = inv_sh_out[31:0];
else
sub32_in = in[31:0];
end
sh_in = {sub96_out,sub32_out};
if(dec)begin //add -> mix -> invsh -> invsub
key_in = in;
mix_in = key_out;
//inv_sh_in = mix_out_inv;
sub96_in = inv_sh_out[127:32];
out = {sub96_out,sub32_out};
end
else begin //sub -> sh -> mix -> add
sub96_in = in[127:32];
if(nomix)
key_in = sh_out;
else
key_in = mix_out;
//sh_in = sub_out;
mix_in = sh_out;
out = key_out;
end
end
endmodule
| 6.632369 |
module KeySchedule ( // share xor?
key,
rc,
out_key,
dec,
sub_in,
sub_out
);
input [127:0] key;
input [7:0] rc;
output reg [127:0] out_key;
output [31:0] sub_in;
input [31:0] sub_out;
input dec;
reg [31:0] out_word[0:3];
reg [31:0] in_word[0:3];
integer i;
reg [31:0] g_in;
wire [31:0] g_out;
GFunction gfunc (
.in(g_in),
.out(g_out),
.rc(rc),
.sub_in(sub_in),
.sub_out(sub_out)
);
always @(*) begin
for (i = 0; i < 4; i = i + 1) begin
in_word[i] = key[127-32*i-:32];
out_key[127-32*i-:32] = out_word[i];
end
end
always @(*) begin
if (dec) begin
g_in = out_word[3];
out_word[0] = in_word[0] ^ g_out;
out_word[1] = in_word[1] ^ in_word[0];
out_word[2] = in_word[2] ^ in_word[1];
out_word[3] = in_word[3] ^ in_word[2];
end else begin
g_in = in_word[3];
out_word[0] = in_word[0] ^ g_out;
out_word[1] = in_word[1] ^ out_word[0];
out_word[2] = in_word[2] ^ out_word[1];
out_word[3] = in_word[3] ^ out_word[2];
end
end
endmodule
| 6.705064 |
module GFunction (
in,
out,
rc,
sub_in,
sub_out
);
input [31:0] in;
input [7:0] rc;
output [31:0] out;
output [31:0] sub_in;
input [31:0] sub_out;
wire [7:0] V[0:3];
wire [7:0] V_o[0:3];
wire [7:0] V_o_temp;
assign {V[0], V[1], V[2], V[3]} = in;
assign out = {V_o[0], V_o[1], V_o[2], V_o[3]};
// STable s0(.in(V[0]),.out(V_o[3]));
// STable s1(.in(V[1]),.out(V_o_temp));
// STable s2(.in(V[2]),.out(V_o[1]));
// STable s3(.in(V[3]),.out(V_o[2]));
assign sub_in = {V[0], V[1], V[2], V[3]};
assign {V_o[3], V_o_temp, V_o[1], V_o[2]} = sub_out;
assign V_o[0] = V_o_temp ^ rc;
endmodule
| 6.596454 |
module MultiplyMinv (
in,
out
);
input [7:0] in;
output reg [7:0] out;
integer i;
always @(*) begin
for (i = 0; i < 8; i = i + 1) begin
out[i] = in[(i+2)%8] ^ in[(i+5)%8] ^ in[(i+7)%8];
end
end
endmodule
| 6.592756 |
module AddC (
in,
out
);
input [7:0] in;
output [7:0] out;
assign out = in ^ 8'b01100011;
endmodule
| 7.213922 |
module AddCinv (
in,
out
);
input [7:0] in;
output [7:0] out;
assign out = in ^ 8'b00000101;
endmodule
| 6.876168 |
module AddRoundKey (
in,
key,
out
);
input [127:0] in, key;
output [127:0] out;
assign out = in ^ key;
endmodule
| 7.103156 |
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