code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ADD_SUB_ALU (
input [7:0] a,
b,
input [1:0] sel,
output reg [7:0] out
);
//0 is B-A
//1 is A-B
//2 is pass A
always @(*) begin
case (sel)
2'b00: begin
out = b - a;
end
2'b01: begin
out = a - b;
end
2'b10: begin
out = a;
end
2'b11: begin
out = out;
end
endcase
end
/*
CLA #(8) CLA_I(
.A(mux_1),
.B(mux_2),
.Cin(1'b0),
.Sum(m_b),
.Cout(carry)
);
*/
endmodule
| 6.671265 |
module add_sub (
add_sub,
dataa,
datab,
cout,
overflow,
result
);
input add_sub;
input [31:0] dataa;
input [31:0] datab;
output cout;
output overflow;
output [31:0] result;
endmodule
| 7.314322 |
module it's different to the add_sub module synthesized
module add_sub_carry_out
# (parameter W = 32)
(
input wire op_mode,
input wire [W-1:0] Data_A,
input wire [W-1:0] Data_B,
output reg [W:0] Data_S
);
always @*
if(op_mode)
Data_S <= Data_A - Data_B;
else
Data_S <= Data_A + Data_B;
endmodule
| 7.525131 |
module AS_C (
a,
b,
asn,
res
);
parameter PART_LEN = 8;
input asn;
input signed [2*PART_LEN-1:0] a, b;
output signed [2*PART_LEN-1:0] res;
wire signed [PART_LEN-1:0] ra = a[2*PART_LEN-1:PART_LEN];
wire signed [PART_LEN-1:0] rb = b[2*PART_LEN-1:PART_LEN];
wire signed [PART_LEN-1:0] ia = a[PART_LEN-1:0];
wire signed [PART_LEN-1:0] ib = b[PART_LEN-1:0];
wire signed [ PART_LEN:0] rr = (asn) ? ra + rb : ra - rb;
wire signed [ PART_LEN:0] ir = (asn) ? ia + ib : ia - ib;
assign res = {rr[PART_LEN-1:0], ir[PART_LEN-1:0]};
endmodule
| 6.982091 |
module add_sub_mega (
add_sub,
dataa,
datab,
cout,
overflow,
result
);
input add_sub;
input [31:0] dataa;
input [31:0] datab;
output cout;
output overflow;
output [31:0] result;
wire sub_wire0;
wire sub_wire1;
wire [31:0] sub_wire2;
wire overflow = sub_wire0;
wire cout = sub_wire1;
wire [31:0] result = sub_wire2[31:0];
lpm_add_sub LPM_ADD_SUB_component (
.add_sub(add_sub),
.datab(datab),
.dataa(dataa),
.overflow(sub_wire0),
.cout(sub_wire1),
.result(sub_wire2)
// synopsys translate_off
, .aclr(),
.cin(),
.clken(),
.clock()
// synopsys translate_on
);
defparam LPM_ADD_SUB_component.lpm_direction = "UNUSED", LPM_ADD_SUB_component.lpm_hint =
"ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO", LPM_ADD_SUB_component.lpm_representation = "SIGNED",
LPM_ADD_SUB_component.lpm_type = "LPM_ADD_SUB", LPM_ADD_SUB_component.lpm_width = 32;
endmodule
| 6.767741 |
module add_sub_mega (
add_sub,
dataa,
datab,
cout,
overflow,
result
);
input add_sub;
input [31:0] dataa;
input [31:0] datab;
output cout;
output overflow;
output [31:0] result;
endmodule
| 6.767741 |
module add_sub_mm_gmem_m_axi_flushManager
#(parameter
NUM_READ_OUTSTANDING = 2,
NUM_WRITE_OUTSTANDING = 2
)(
input clk,
input reset,
input clk_en,
input flush,
output flush_done,
input in_AWVALID,
output out_AWVALID,
input in_AWREADY,
output out_AWREADY,
input in_WVALID,
output out_WVALID,
input in_BREADY,
output out_BREADY,
input in_BVALID,
input in_ARVALID,
output out_ARVALID,
input in_ARREADY,
input in_RREADY,
output out_RREADY,
input in_RVALID,
input in_RLAST);
//------------------------Task and function--------------
function integer log2;
input integer x;
integer n, m;
begin
n = 0;
m = 1;
while (m < x) begin
n = n + 1;
m = m * 2;
end
log2 = n;
end
endfunction
//------------------------Local signal-------------------
reg flushStart;
reg flushReg;
wire oneWBurstLaunch;
wire oneWBurstFinish;
wire flush_AWVALID;
wire flush_BREADY;
wire WBurstEmpty_n;
wire wFlushDone;
wire oneRBurstLaunch;
wire oneRBurstFinish;
wire flush_ARVALID;
wire flush_RREADY;
wire RBurstEmpty_n;
wire rFlushDone;
//------------------------Instantiation------------------
add_sub_mm_gmem_m_axi_fifo #(
.DATA_WIDTH (1),
.ADDR_WIDTH (log2(NUM_WRITE_OUTSTANDING)),
.DEPTH (NUM_WRITE_OUTSTANDING)
) WFlushManager (
.clk (clk),
.reset (reset),
.clk_en (clk_en),
.if_full_n (),
.if_write (oneWBurstLaunch),
.if_din (1'b1),
.if_empty_n (WBurstEmpty_n),
.if_read (oneWBurstFinish),
.if_dout (),
.if_num_data_valid());
add_sub_mm_gmem_m_axi_fifo #(
.DATA_WIDTH (1),
.ADDR_WIDTH (log2(NUM_READ_OUTSTANDING)),
.DEPTH (NUM_READ_OUTSTANDING)
) RFlushManager (
.clk (clk),
.reset (reset),
.clk_en (clk_en),
.if_full_n (),
.if_write (oneRBurstLaunch),
.if_din (1'b1),
.if_empty_n (RBurstEmpty_n),
.if_read (oneRBurstFinish),
.if_dout (),
.if_num_data_valid());
//------------------------Body---------------------------
assign oneWBurstLaunch = flush_AWVALID & in_AWREADY;
assign oneWBurstFinish = flush_BREADY & in_BVALID;
assign oneRBurstLaunch = flush_ARVALID & in_ARREADY;
assign oneRBurstFinish = flush_RREADY & in_RLAST & in_RVALID;
assign flush_AWVALID = flush ? 0 : in_AWVALID;
assign out_AWVALID = flush_AWVALID;
assign out_AWREADY = flush ? 0 : in_AWREADY;
assign out_WVALID = wFlushDone ? 0 : in_WVALID;
assign flush_BREADY = flush ? 1 : in_BREADY;
assign out_BREADY = flush_BREADY;
assign flush_ARVALID = flush ? 0 : in_ARVALID;
assign out_ARVALID = flush_ARVALID;
assign flush_RREADY = flush ? 1 : in_RREADY;
assign out_RREADY = flush_RREADY;
assign wFlushDone = flushStart & ~WBurstEmpty_n;
assign rFlushDone = flushStart & ~RBurstEmpty_n;
assign flush_done = wFlushDone & rFlushDone;
always @ (posedge clk) begin
if (reset)
flushReg <= 1'b0;
else if (clk_en)
flushReg <= flush;
end
always @ (posedge clk) begin
if (reset)
flushStart <= 1'b0;
else if (clk_en) begin
if (flush && ~flushReg)
flushStart <= 1'b1;
else if (~flush && flushReg)
flushStart <= 1'b0;
end
end
endmodule
| 7.021828 |
module add_sub_mm_gmem_m_axi_reg_slice #(
parameter DATA_WIDTH = 8
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [DATA_WIDTH-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [DATA_WIDTH-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [DATA_WIDTH-1:0] data_p1;
reg [DATA_WIDTH-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.021828 |
module add_sub_mm_gmem_m_axi_srl #(
parameter DATA_WIDTH = 32,
ADDR_WIDTH = 6,
DEPTH = 63
) (
input wire clk,
input wire reset,
input wire clk_en,
input wire we,
input wire [DATA_WIDTH-1:0] din,
input wire [ADDR_WIDTH-1:0] raddr,
input wire re,
output reg [DATA_WIDTH-1:0] dout
);
generate
if (DEPTH > 1) begin
reg [DATA_WIDTH-1:0] mem[0:DEPTH-2];
integer i;
always @(posedge clk) begin
if (clk_en & we) begin
for (i = 0; i < DEPTH - 2; i = i + 1) begin
mem[i+1] <= mem[i];
end
mem[0] <= din;
end
end
always @(posedge clk) begin
if (reset) dout <= 0;
else if (clk_en & re) begin
dout <= mem[raddr];
end
end
end else begin
always @(posedge clk) begin
if (reset) dout <= 0;
else if (clk_en & we) begin
dout <= din;
end
end
end
endgenerate
endmodule
| 7.021828 |
module add_sub_mm_gmem_m_axi_mem #(
parameter MEM_STYLE = "auto",
DATA_WIDTH = 32,
ADDR_WIDTH = 6,
DEPTH = 63
) (
input wire clk,
input wire reset,
input wire clk_en,
input wire we,
input wire [ADDR_WIDTH-1:0] waddr,
input wire [DATA_WIDTH-1:0] din,
input wire [ADDR_WIDTH-1:0] raddr,
input wire re,
output reg [DATA_WIDTH-1:0] dout
);
(* ram_style = MEM_STYLE, rw_addr_collision = "yes" *)
reg [DATA_WIDTH-1:0] mem[0:DEPTH-2];
reg [ADDR_WIDTH-1:0] raddr_reg;
//write to ram
always @(posedge clk) begin
if (clk_en & we) mem[waddr] <= din;
end
//buffer the raddr
always @(posedge clk) begin
if (clk_en) raddr_reg <= raddr;
end
//read from ram
always @(posedge clk) begin
if (reset) dout <= 0;
else if (clk_en & re) dout <= mem[raddr_reg];
end
endmodule
| 7.021828 |
module add_sub_module #(
parameter data_width = 16
) (
input [data_width - 1 : 0] _A,
input [data_width - 1 : 0] _B,
input func,
output reg [data_width - 1 : 0] _C,
output reg _O
);
reg [data_width - 1 : 0] temp;
always @(*) begin
if (func) // SUB
temp = -_B;
else // ADD
temp = _B;
_C = _A + temp;
_O = ~(_A[data_width-1] ^ temp[data_width-1]) & (_A[data_width-1] ^ _C[data_width-1]);
end
endmodule
| 6.78082 |
module Add_Sub_Nbit #(
parameter N = 16
) (
A,
B,
s,
Y
);
input [N-1:0] A, B;
input s;
output [N:0] Y;
wire [N+1:0] C;
wire [N:0] A1, B1;
wire [N:0] xB;
assign A1 = {A[N-1], A};
assign B1 = {B[N-1], B};
assign xB = s ? ~B1 : B1;
assign C[0] = s;
genvar i;
generate
for (i = 0; i < N + 1; i = i + 1) begin : FA_loop
FA FA_ (
.A(A1[i]),
.B(xB[i]),
.Cin(C[i]),
.Sum(Y[i]),
.Cout(C[i+1])
);
end
endgenerate
endmodule
| 6.568365 |
module add_sub #(
parameter W = 16
) (
input [W-1:0] a,
b,
input sel,
output [W-1:0] res
);
wire ci;
wire [W:0] sum;
assign sum = {a, sel} + {(sel ? ~b : b), 1'b1};
assign res = sum[W:1];
endmodule
| 7.786454 |
module add_sub_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire [DataWidth-1:0] B_V_data_1_data_in;
reg [DataWidth-1:0] B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg [DataWidth-1:0] B_V_data_1_payload_A;
reg [DataWidth-1:0] B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.54176 |
module add_sub_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
reg B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg B_V_data_1_payload_A;
reg B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.54176 |
module add_sub_tb;
wire [31:0] result;
wire underflag, overflag;
reg [31:0] A, B;
reg add_or_sub;
add_sub uut (
.A(A),
.B(B),
.checkequation(add_or_sub),
.overflow(overflag),
.underflow(underflag),
.result(result)
);
initial begin
A = 32'b00111111000000000000000000000000; //0.5
B = 32'b00111111000000000000000000000000; //0.4375
add_or_sub = 0;
#50 $finish;
end
initial begin
$vcdplusfile("tb.vpd");
$vcdpluson();
end
endmodule
| 6.6302 |
module add_share (
02 input a, b, x, y, sel, en, clk,
03 output reg out1, out2
04 );
05 wire tmp1, tmp2;
06 assign tmp1 = a * b; // tmp1需要一个乘法器
07 assign tmp2 = x * y; // tmp2需要一个乘法器
08
09 always@(posedge clk)
10 if (en) begin
11 out1 <= sel ? tmp1: tmp2; //tmp1与tmp2不同时输出有效
12 end else begin
13 out2 <= sel ? tmp1: tmp2; //tmp1与tmp2不同时输出有效
14 end
15 endmodule
| 7.011185 |
module add_two_values_function_tb ();
reg [3:0] ain, bin;
wire [4:0] sum;
integer k;
add_two_values_function DUT (
.ain(ain),
.bin(bin),
.sum(sum)
);
initial begin
ain = 4'h6;
bin = 4'ha;
$display("ain=%b, bin=%b, sum=%b at time=%t", ain, bin, sum, $time);
for (k = 0; k < 5; k = k + 1) begin
#5 ain = ain + k;
bin = bin + k;
$display("ain=%b, bin=%b, sum=%b at time=%t", ain, bin, sum, $time);
end
$display("Simulation Done");
end
endmodule
| 7.038377 |
module add_two_values_task_tb ();
reg [3:0] ain, bin;
wire cout;
wire [3:0] sum;
integer k;
add_two_values_task DUT (
.ain (ain),
.bin (bin),
.cout(cout),
.sum (sum)
);
initial begin
ain = 4'h6;
bin = 4'ha;
$display("ain=%b, bin=%b, cout=%b, sum=%b at time=%t", ain, bin, cout, sum, $time);
for (k = 0; k < 5; k = k + 1) begin
#5 ain = ain + k;
bin = bin + k;
$display("ain=%b, bin=%b, cout=%b, sum=%b at time=%t", ain, bin, cout, sum, $time);
end
$display("Simulation Done");
end
endmodule
| 7.038377 |
module add_unit (
input add_num,
input cur_num,
input carry,
output carry_next,
output stmt
);
wire t1, t2, t3;
wire s1;
xor (s1, add_num, cur_num);
xor (stmt, s1, carry);
and (t3, add_num, cur_num);
and (t2, cur_num, carry);
and (t1, add_num, carry);
or (carry_next, t1, t2, t3);
endmodule
| 7.104201 |
module add_v (
rst,
data_in,
data_out,
clk
);
input data_in, rst, clk;
output [1:0] data_out;
reg [1:0] data_out; //用00、01、11分别表示输入信号为“0、1、V”
reg [1:0] counter; //设置连0计数器
always @(posedge clk or negedge rst) begin
if (!rst) begin
counter <= 0;
data_out <= 0;
end else if (data_in == 1'b1) begin //判断输入信号是否为1
counter <= 0; //若为1则计数器复位，输出“01”
data_out <= 2'b01;
end else if (data_in == 1'b0) begin //若输入信号为0，计数器+1
counter <= counter + 1;
if(counter == 2'b11) begin //判断连0个数是否达到4个，因为非阻塞赋值，此时计数器值应为3时，表示出现4个连0
data_out <= 2'b11; //将0的输出变为V
counter <= 0; //计数器复位
end else data_out <= 2'b00; //若连0数不为4，输出“00”
end
end
endmodule
| 7.058533 |
module ADD_ver (
clk,
rst_n,
enable,
delta,
result
);
input clk, rst_n, enable;
input [31:0] delta;
output [31:0] result;
reg [31:0] result, result1, limit;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
result1 <= 32'd0;
limit <= 10240000;
end else begin
result1 <= result;
if (enable == 1'b1) begin
result1 <= result1 + delta;
end else;
end
end
always @(result1) begin
if ((result1[31] == 0) && (result1 > limit)) begin
result <= limit;
end else if ((result1[31] == 1) && (result1 < -10240000)) begin
result <= -10240000;
end else begin
result <= result1;
end
end
endmodule
| 7.103513 |
module add_wraparound_after40 (
out_value,
in_value_1,
in_value_2
);
output [5:0] out_value;
input [5:0] in_value_1, in_value_2;
wire [5:0] inter_sum;
wire [6:0] inter_sub_40;
wire cout1, cout2, is_less_than_40;
adder6bit a6b (
inter_sum,
cout1,
in_value_1,
in_value_2
); // adding two inputs
adder7bit a7b (
inter_sub_40,
cout2,
{cout1, inter_sum},
7'b1011000
); // sum - 40 is output if sum is > 40
assign is_less_than_40 = inter_sub_40[6];
assign out_value = is_less_than_40 ? inter_sum : inter_sub_40[5:0];
endmodule
| 7.378773 |
module add_w_carry #(
parameter WIDTH = 8
) (
input c_in,
input [WIDTH-1:0] in_1,
input [WIDTH-1:0] in_2,
output [WIDTH-1:0] out,
output c_out
);
wire [WIDTH-1:0] carry;
wire [WIDTH-1:0] p;
wire [WIDTH-1:0] r;
wire [WIDTH-1:0] s;
assign c_out = carry[WIDTH-1];
genvar count_generate;
generate
for (
count_generate = 0; count_generate < WIDTH; count_generate = count_generate + 1
) begin : ADD
xor (p[count_generate], in_1[count_generate], in_2[count_generate]);
xor (out[count_generate], p[count_generate], count_generate ? carry[count_generate-1] : c_in);
and (r[count_generate], p[count_generate], count_generate ? carry[count_generate-1] : c_in);
and (s[count_generate], in_1[count_generate], in_2[count_generate]);
or (carry[count_generate], r[count_generate], s[count_generate]);
end
endgenerate
endmodule
| 8.526975 |
module Add_w_carry_16bit (
F,
A,
B,
C
);
input signed [15:0] A, B;
input C;
output reg signed [15:0] F;
always @(A) begin
if (C) F = (A + B) + 1;
else F = A + B;
end
endmodule
| 7.692912 |
module ADF (
clk,
band,
clock,
ADF_out,
LE
);
input clk; // 48 kHz
input [2:0] band; //band data
output reg clock; // clock to ADF
output reg LE; // high when Register data available
output reg ADF_out; // data to ADF
reg ADF;
reg [5:0] write;
reg [4:0] loop_count;
reg [2:0] previous_band;
// Set up reg data to send
always @* begin
case (select)
6'b000000: REG_data = 32'h580005;
6'b000001: REG_data = 32'hEF603C;
6'b000010: REG_data = 32'h4B3;
6'b000011: REG_data = 32'h10E42;
6'b000100: REG_data = 32'h8008061;
6'b000101: REG_data = 32'h240058;
6'b001000: REG_data = 32'h580005;
6'b001001: REG_data = 32'hEF603C;
6'b001010: REG_data = 32'h4B3;
6'b001011: REG_data = 32'h10E42;
6'b001100: REG_data = 32'h8008031;
6'b001101: REG_data = 32'h340008;
6'b010000: REG_data = 32'h580005;
6'b010001: REG_data = 32'hDF603C;
6'b010010: REG_data = 32'h4B3;
6'b010011: REG_data = 32'h10E42;
6'b010100: REG_data = 32'h8008041;
6'b010101: REG_data = 32'h3C8038;
6'b011000: REG_data = 32'h580005;
6'b011001: REG_data = 32'hBF603C;
6'b011010: REG_data = 32'h4B3;
6'b011011: REG_data = 32'h10E42;
6'b011100: REG_data = 32'h80080C1;
6'b011101: REG_data = 32'h348028;
6'b100000: REG_data = 32'h580005;
6'b100001: REG_data = 32'h9F603C;
6'b100010: REG_data = 32'h4B3;
6'b100011: REG_data = 32'h10E42;
6'b100100: REG_data = 32'h8008301;
6'b100101: REG_data = 32'h2901A8;
6'b101000: REG_data = 32'h580005;
6'b101001: REG_data = 32'h9F603C;
6'b101010: REG_data = 32'h4B3;
6'b101011: REG_data = 32'h10E42;
6'b101100: REG_data = 32'h8008601;
6'b101101: REG_data = 32'h268148;
6'b110000: REG_data = 32'h0;
6'b110001: REG_data = 32'h0;
6'b110010: REG_data = 32'h0;
6'b110011: REG_data = 32'h0;
6'b110100: REG_data = 32'h0;
6'b110101: REG_data = 32'h0;
6'b111000: REG_data = 32'h0;
6'b111001: REG_data = 32'h0;
6'b111010: REG_data = 32'h0;
6'b111011: REG_data = 32'h0;
6'b111100: REG_data = 32'h0;
6'b111101: REG_data = 32'h0;
default: REG_data = 0;
endcase
end
always @* select <= {band, load};
reg [ 5:0] select;
reg [ 2:0] load;
reg [31:0] REG_data;
reg [31:0] latch_REG_data;
reg [ 4:0] bit_cnt;
// Write Operation
always @(negedge clk) begin
case (write)
4'd0: begin
LE <= 1'b0; // set TLV320 CS high
bit_cnt <= 5'd31; // set starting bit count to 15
latch_REG_data <= REG_data; // save the current settings
write <= 4'd1;
end
4'd1: begin
LE <= 1'b0; // start data transfer with nCS low
ADF_out <= latch_REG_data[bit_cnt]; // set data up
write <= 4'd2;
end
4'd2: begin
clock <= 1'b1; // clock data into TLV320
write <= 4'd3;
end
4'd3: begin
clock <= 1'b0; // reset clock
write <= 4'd4;
end
4'd4: begin
if (bit_cnt == 0) // word transfer is complete, check for any more
write <= 4'd5;
else begin
bit_cnt <= bit_cnt - 1'b1;
write <= 4'd1; // go round again
end
begin
previous_band <= band; // save the current boost setting
end
end
4'd5: begin
if (load == 5) begin
LE <= 1'b1;
if (band != previous_band) begin
load <= 0;
write <= 4'd0;
end else write <= 4'd5; // hang out here forever
end else begin // else get next data
LE <= 1'b1;
write <= 4'd0;
load <= load + 3'b1; // select next data word to send
end
end
default: write <= 4'd0;
endcase
end
endmodule
| 7.609584 |
module ADF4351 (
input CLK,
input RST,
input ADF_WEN, //write enable
input [31:0] WDATA, //write register
output ADF_CLK, // SPI data clock
output ADF_DATA, //data
output ADF_LE,
output ADF_WRITE_DONE
);
reg ADF_CLK_reg, ADF_CLK_reg_next;
reg ADF_DATA_reg, ADF_DATA_reg_next;
reg ADF_LE_reg, ADF_LE_reg_next;
reg ADF_WRITE_DONE_reg, ADF_WRITE_DONE_reg_next;
reg [2:0] DataWriteStatus, DataWriteStatus_next;
localparam [2:0]
WRITE_IDLE = 3'd0,
WRITE_CLK_L = 3'd1,
WRITE_CLK_DO = 3'd2,
WRITE_CLK_H = 3'd3,
WRITE_CLK_ADD = 3'd4,
WRITE_DONE = 3'd5;
reg [4:0] BitsCntReg, BitsCntReg_next; // write data bits count
always @(negedge RST, posedge CLK) begin
if (!RST) begin
DataWriteStatus <= WRITE_IDLE;
ADF_CLK_reg <= 0;
ADF_DATA_reg <= 0;
ADF_LE_reg <= 1;
ADF_WRITE_DONE_reg <= 0;
BitsCntReg <= 5'd31;
end else begin
DataWriteStatus <= DataWriteStatus_next;
ADF_CLK_reg <= ADF_CLK_reg_next;
ADF_DATA_reg <= ADF_DATA_reg_next;
ADF_LE_reg <= ADF_LE_reg_next;
ADF_WRITE_DONE_reg <= ADF_WRITE_DONE_reg_next;
BitsCntReg <= BitsCntReg_next;
end
end
always @* begin
DataWriteStatus_next = DataWriteStatus;
ADF_LE_reg_next = ADF_LE_reg;
ADF_WRITE_DONE_reg_next = 0;
BitsCntReg_next = BitsCntReg;
ADF_DATA_reg_next = ADF_DATA_reg;
case (DataWriteStatus)
WRITE_IDLE: begin
if (ADF_WEN) begin
ADF_LE_reg_next = 0;
DataWriteStatus_next = WRITE_CLK_L;
end else begin
ADF_LE_reg_next = 1;
end
ADF_CLK_reg_next = 0;
end
WRITE_CLK_L: begin
ADF_CLK_reg_next = 0;
DataWriteStatus_next = WRITE_CLK_DO;
end
WRITE_CLK_DO: begin
ADF_DATA_reg_next = WDATA[BitsCntReg];
DataWriteStatus_next = WRITE_CLK_H;
end
WRITE_CLK_H: begin
ADF_CLK_reg_next = 1;
DataWriteStatus_next = WRITE_CLK_ADD;
end
WRITE_CLK_ADD: begin
BitsCntReg_next = BitsCntReg_next - 5'd1;
if (BitsCntReg_next == 5'd31) begin
DataWriteStatus_next = WRITE_DONE;
end else begin
DataWriteStatus_next = WRITE_CLK_L;
end
end
WRITE_DONE: begin
ADF_WRITE_DONE_reg_next = 1;
DataWriteStatus_next = WRITE_IDLE;
ADF_CLK_reg_next = 0;
end
default: begin
DataWriteStatus_next = WRITE_IDLE;
end
endcase
end
assign ADF_CLK = ADF_CLK_reg;
assign ADF_DATA = ADF_DATA_reg;
assign ADF_LE = ADF_LE_reg;
assign ADF_WRITE_DONE = ADF_WRITE_DONE_reg;
endmodule
| 6.836414 |
module ADF4351_FREQ (
input RST,
input CLK,
input CFG_EN, //Config enable
input LO_SET, //LO_SET is high
input [23:0]FREQ, //target frequency unit = KHz
output [31:0]ADF_R0,
output [31:0]ADF_R4,
output DONE
);
reg [23:0] FreqReg, FreqRegNext;
//calculate R0 and R4
reg [31:0] FreqintReg, FreqintReg_next;
reg [31:0] FreqfracReg, FreqfracReg_next;
reg [31:0] LO_FreqintReg, LO_FreqintReg_next;
reg [31:0] LO_FreqfracReg, LO_FreqfracReg_next;
reg [2:0] FreqCalStatus, FreqCalStatus_next;
localparam [2:0]
CAL_STATUS_IDLE = 3'd0,
CAL_STATUS_R0_STEP_0 = 3'd1,
CAL_STATUS_R0_STEP_1 = 3'd2,
CAL_STATUS_R0_STEP_2 = 3'd3;
reg [31:0] ADF_R0_reg, ADF_R0_regNext;
reg [31:0] ADF_R4_reg, ADF_R4_regNext;
reg Done_reg, Done_regNext;
always @(negedge RST, posedge CLK) begin
if (!RST) begin
ADF_R0_reg <= 32'H00501f40;
ADF_R4_reg <= 32'h00AC803C;
FreqCalStatus <= CAL_STATUS_IDLE;
end else begin
ADF_R0_reg <= ADF_R0_regNext;
ADF_R4_reg <= ADF_R4_regNext;
FreqCalStatus <= FreqCalStatus_next;
FreqReg <= FreqRegNext;
end
end
assign ADF_R0 = ADF_R0_reg;
assign ADF_R4 = ADF_R4_reg;
assign DONE = Done_reg;
always @* begin
ADF_R0_regNext = ADF_R0_reg;
ADF_R4_regNext = ADF_R4_reg;
FreqintReg_next = FreqintReg;
FreqfracReg_next = FreqfracReg;
FreqCalStatus_next = FreqCalStatus;
FreqRegNext = FreqReg;
Done_regNext = 0;
case (FreqCalStatus)
CAL_STATUS_IDLE:
if (CFG_EN) begin
FreqCalStatus_next = CAL_STATUS_R0_STEP_0;
if (LO_SET) begin
FreqRegNext = FREQ - 2000; // IF = 2MHZ
end else begin
FreqRegNext = FREQ;
end
end
CAL_STATUS_R0_STEP_0: begin
FreqCalStatus_next = CAL_STATUS_R0_STEP_1;
// < 68.75MHZ
if ((FreqReg > 24'd31999) && (FreqReg < 24'd68750)) begin
ADF_R4_regNext = 32'H00EC803C;
FreqintReg_next = FreqReg << 6;
FreqfracReg_next = FreqReg << 3;
end //>=68.75mHz & <137.5mHz
else if ((FreqReg > 24'd68749) && (FreqReg < 24'd137500)) begin
ADF_R4_regNext = 32'H00DC803C;
FreqintReg_next = FreqReg << 5;
FreqfracReg_next = FreqReg << 2;
end //>=137.5mHz & <275mHz
else if ((FreqReg > 24'd137499) && (FreqReg < 24'd275000)) begin
ADF_R4_regNext = 32'H00CC803C;
FreqintReg_next = FreqReg << 4;
FreqfracReg_next = FreqReg << 1;
end //>=275mHz & <550mHz
else if ((FreqReg > 24'd274999) && (FreqReg < 24'd550000)) begin
ADF_R4_regNext = 32'H00BC803C;
FreqintReg_next = FreqReg << 3;
FreqfracReg_next = FreqReg;
end //>=550mHz & <1100mHz
else if ((FreqReg > 24'd549999) && (FreqReg < 24'd1100000)) begin
ADF_R4_regNext = 32'H00AC803C;
FreqintReg_next = FreqReg << 2;
FreqfracReg_next = FreqReg >> 1;
end //>=1100mHz & <2200mHz
else if ((FreqReg > 24'd1099999) && (FreqReg < 24'd2200000)) begin
ADF_R4_regNext = 32'H009C803C;
FreqintReg_next = FreqReg << 1;
FreqfracReg_next = FreqReg >> 2;
end //>=2200mHz
else if (FreqReg > 24'd2199999) begin
ADF_R4_regNext = 32'H008C803C;
FreqintReg_next = FreqReg;
FreqfracReg_next = FreqReg >> 3;
end else begin
ADF_R4_regNext = 32'H008C803C;
FreqintReg_next = FreqReg;
FreqfracReg_next = FreqReg >> 3;
end
end
CAL_STATUS_R0_STEP_1: begin
FreqCalStatus_next = CAL_STATUS_R0_STEP_2;
FreqintReg_next = FreqintReg_next << 15;
FreqfracReg_next = FreqfracReg_next << 3;
end
CAL_STATUS_R0_STEP_2: begin
FreqCalStatus_next = CAL_STATUS_IDLE;
ADF_R0_regNext = FreqintReg_next | FreqfracReg_next;
Done_regNext = 1;
end
default: begin
FreqCalStatus_next = CAL_STATUS_IDLE;
end
endcase
end
endmodule
| 6.99516 |
module adf4351_tb;
reg clk_50;
reg rst_n;
reg vco_ld; //Lock Detect Output Pin. A logic high output on this pin indicates PLL lock
wire vco_clk;
wire vco_data;
wire vco_le ; //Load Enable. When LE goes high, the data stored in the 32-bit shift register is loaded into
wire vco_ce ; //Chip Enable. A logic low on this pin powers down the device and puts the charge pump into th
adf4351 vco (
.clk_50 (clk_50 ),
.rst_n (rst_n ),
.vco_clk (vco_clk ),
.vco_data (vco_data ),
.vco_le (vco_le ),
.vco_ce (vco_ce ),
.vco_ld (vco_ld )
);
initial begin
rst_n = 0;
vco_ld = 0;
clk_50 = 0;
#2000;
rst_n = 1;
#250000;
$stop;
end
always #10 clk_50 = ~clk_50;
endmodule
| 7.275426 |
module adff (
input D,
input clk,
input reset,
output Q
);
reg Qreg;
assign Q = Qreg;
always @(posedge (clk), posedge (reset)) begin
if (reset == 1) Qreg <= 1'b0;
else Qreg <= D;
end
endmodule
| 7.089232 |
module adff2dff (CLK, ARST, D, Q);
parameter WIDTH = 1;
parameter CLK_POLARITY = 1;
parameter ARST_POLARITY = 1;
parameter ARST_VALUE = 0;
input CLK, ARST;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
wire reg [WIDTH-1:0] NEXT_Q;
wire [1023:0] _TECHMAP_DO_ = "proc;;";
always @*
if (ARST == ARST_POLARITY)
NEXT_Q <= ARST_VALUE;
else
NEXT_Q <= D;
if (CLK_POLARITY)
always @(posedge CLK)
Q <= NEXT_Q;
else
always @(negedge CLK)
Q <= NEXT_Q;
endmodule
| 6.508976 |
module top (
input d,
clk,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, posedge clr)
if (clr) q <= 1'b0;
else q <= d;
endmodule
| 7.233807 |
module adFIFO (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty
);
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
wire sub_wire0;
wire [31:0] sub_wire1;
wire rdempty = sub_wire0;
wire [31:0] q = sub_wire1[31:0];
dcfifo dcfifo_component (
.wrclk(wrclk),
.rdreq(rdreq),
.rdclk(rdclk),
.wrreq(wrreq),
.data(data),
.rdempty(sub_wire0),
.q(sub_wire1)
// synopsys translate_off
, .aclr(),
.rdfull(),
.rdusedw(),
.wrempty(),
.wrfull(),
.wrusedw()
// synopsys translate_on
);
defparam dcfifo_component.intended_device_family = "Stratix II",
dcfifo_component.lpm_hint = "MAXIMIZE_SPEED=7,RAM_BLOCK_TYPE=M4K",
dcfifo_component.lpm_numwords = 2048, dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 32,
dcfifo_component.lpm_widthu = 11, dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5, dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON", dcfifo_component.wrsync_delaypipe = 5;
endmodule
| 6.940264 |
module adFIFO (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty
);
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
endmodule
| 6.940264 |
module ADF_driver (
input clk, //系统时钟
input wrsig, //发送命令，上升沿有效
input [8:0] datain, //需要发送的数据
output reg tx_idle, //线路状态指示，高为线路忙，低为线路空闲
output reg tx, //发送数据信号
output reg clkout,
output reg LE
);
reg tx_send = 0;
reg tx_wrsigbuf = 0, tx_wrsigrise = 0;
reg [7:0] tx_cnt = 0; //计数器
//检测发送命令是否有效
reg [15:0] clk_cnt = 0;
reg [31:0] dataint = 0;
reg [10:0] cnt_init = 0;
reg init = 0;
reg [4:0] cnt_wei = 0;
reg [15:0] int_v = 0;
reg [11:0] frac_v = 0;
parameter [31:0] R5 = 32'b00000000_00011_0000000000000000_101;
parameter [31:0] R4 = 32'b00000000_1101_01100100_000000_111100;
parameter [31:0] R3 = 32'b00000000_100000010_111111111111_011;
parameter [31:0] R2 = 32'b00000000_0000000001_00000_001000010;
parameter [31:0] R1 = 32'b00000_000000000000_000001100100_001;
reg [31:0] R0 = 32'b0_00000000_10100000_000000000000_000;
always @(posedge clk) begin //分频进程 CLK/(1000000)
if (clk_cnt == 16'd24) begin
clkout <= 1'b1;
clk_cnt <= clk_cnt + 16'd1;
end else if (clk_cnt == 16'd49) begin
clkout <= 1'b0;
clk_cnt <= 16'd0;
end else begin
clk_cnt <= clk_cnt + 16'd1;
end
end
always @(negedge clkout) begin
int_v <= datain / 7'd100;
frac_v <= datain % 7'd100;
if (!init) begin
cnt_init <= cnt_init + 1'b1;
case (cnt_init)
11'd5: begin
R0 <= 32'b0_00000000_10100000_000000000000_000;
end
11'd1010: begin
tx_send <= 1'b1;
dataint <= R5;
end
11'd1046: begin
tx_send <= 1'b0;
end
11'd1110: begin
tx_send <= 1'b1;
dataint <= R4;
end
11'd1146: begin
tx_send <= 1'b0;
end
11'd1210: begin
tx_send <= 1'b1;
dataint <= R3;
end
11'd1246: begin
tx_send <= 1'b0;
end
11'd1310: begin
tx_send <= 1'b1;
dataint <= R2;
end
11'd1346: begin
tx_send <= 1'b0;
end
11'd1410: begin
tx_send <= 1'b1;
dataint <= R1;
end
11'd1446: begin
tx_send <= 1'b0;
end
11'd1510: begin
tx_send <= 1'b1;
dataint <= R0;
end
11'd1546: begin
tx_send <= 1'b0;
end
11'd1610: begin
tx_send <= 1'b1;
dataint <= R3;
end
11'd1646: begin
tx_send <= 1'b0;
end
11'd1650: begin
init <= 1'b1;
end
endcase
end else begin
tx_wrsigbuf <= wrsig;
tx_wrsigrise <= (~tx_wrsigbuf) & wrsig;
if (tx_wrsigrise && (~tx_idle)) begin
tx_send <= 1'b1;
R0[30:15] <= int_v;
R0[14:3] <= frac_v;
end else if (tx_cnt == 8'd36) begin
tx_send <= 1'b0;
end
end
end
always @(negedge clkout) begin
if (tx_send == 1'b1) begin
case (tx_cnt) //产生起始位
8'd1: begin
LE <= 1'b0;
tx <= dataint[31];
cnt_wei <= 5'd31;
tx_idle <= 1'b1;
tx_cnt <= tx_cnt + 8'd1;
end
8'd2,8'd3,8'd4,8'd5,8'd6,8'd7,8'd8,8'd9,8'd10,8'd11,8'd12,8'd13,8'd14,8'd15
,8'd16,8'd17,8'd18,8'd19,8'd20,8'd21,8'd22,8'd23,8'd24,8'd25,8'd26,8'd27,
8'd28,8'd29,8'd30,8'd31,8'd32,8'd33: begin
tx <= dataint[cnt_wei]; //发送数据0 位
cnt_wei <= cnt_wei - 1'b1;
tx_idle <= 1'b1;
tx_cnt <= tx_cnt + 8'd1;
end
8'd34: begin
tx <= 1'b1;
LE <= 1'b1;
tx_idle <= 1'b0;
tx_cnt <= tx_cnt + 8'd1;
end
default: begin
tx_cnt <= tx_cnt + 8'd1;
end
endcase
end else begin
tx <= 1'b1;
LE <= 1'b1;
cnt_wei <= 5'd31;
tx_cnt <= 8'd0;
tx_idle <= 1'b0;
end
end
endmodule
| 7.150348 |
module adgetnew2_0 (
input wire clk, // clock_reset.clk
input wire reset_n, // .reset_n
input wire [ 1:0] addr, // avalon_slave_0.address
input wire read_n, // .read_n
input wire cs_n, // .chipselect_n
output wire [15:0] readdata, // .readdata
output wire clk_out, // conduit_end.export
output wire din, // .export
input wire dout, // .export
output wire cs, // .export
input wire sars // .export
);
adgetnew2 adgetnew2_0 (
.clk (clk), // clock_reset.clk
.reset_n (reset_n), // .reset_n
.addr (addr), // avalon_slave_0.address
.read_n (read_n), // .read_n
.cs_n (cs_n), // .chipselect_n
.readdata(readdata), // .readdata
.clk_out (clk_out), // conduit_end.export
.din (din), // .export
.dout (dout), // .export
.cs (cs), // .export
.sars (sars) // .export
);
endmodule
| 6.534725 |
modules
module adh_mux (alu,
pch,
dreg,
sel,
y);
input [7:0] alu; // alu inputs
input [7:0] pch; // program counter hi inputs
input [7:0] dreg; // D reg inputs
input [3:0] sel; // Select
output [7:0] y; // y outputs
parameter zero = 8'b 00000000; // zero page
// Note that this is coded at a very low level.
// No doubt about what the synthesize should do with this!
// Xes also propagate just like the real gate level version.
parameter one = 8'b 00000001; // stack page
wire [7:0] y;
wire [7:0] pre_y; // output of the 4:1 mux
// -------------ARCHITECTURE----------
// by default we select the program ctr
assign y = sel == 4'b 0000 ? pch :
pre_y;
assign pre_y[0] = (alu[0] & sel[3] | dreg[0] & sel[2] | sel[0]) & ~sel[1];
assign pre_y[1] = (alu[1] & sel[3] | dreg[1] & sel[2]) & ~(sel[1] | sel[0]);
assign pre_y[2] = (alu[2] & sel[3] | dreg[2] & sel[2]) & ~(sel[1] | sel[0]);
assign pre_y[3] = (alu[3] & sel[3] | dreg[3] & sel[2]) & ~(sel[1] | sel[0]);
assign pre_y[4] = (alu[4] & sel[3] | dreg[4] & sel[2]) & ~(sel[1] | sel[0]);
assign pre_y[5] = (alu[5] & sel[3] | dreg[5] & sel[2]) & ~(sel[1] | sel[0]);
assign pre_y[6] = (alu[6] & sel[3] | dreg[6] & sel[2]) & ~(sel[1] | sel[0]);
assign pre_y[7] = (alu[7] & sel[3] | dreg[7] & sel[2]) & ~(sel[1] | sel[0]);
endmodule
| 7.791918 |
module adio_bk (
input [7:0] din_p,
input [7:0] din_n,
input io_reset,
input clkin_sys,
input clkin_bufr,
output [15:0] o_dout_pin
);
wire [ 7:0] data_in_n0;
wire [ 7:0] data_in_n1;
reg [15:0] ad_dat;
wire [15:0] ad_ndc;
assign o_dout_pin = ad_ndc;
gpio_ddio8_ip u_gpio_ddio8_ip (
.ck (clkin_sys), // input, width = 1, ck.export
.dataout_h(data_in_n0), // output, width = 8, dataout_h.fragment
.dataout_l(data_in_n1), // output, width = 8, dataout_l.fragment
.datain (din_p), // input, width = 8, pad_in.export
.pad_in_b (din_n), // input, width = 8, pad_in_b.export
.aset (io_reset) // input, width = 1, aset.export
);
always @(posedge clkin_bufr) begin
ad_dat <= {
data_in_n0[7],
data_in_n1[7],
data_in_n0[6],
data_in_n1[6],
data_in_n0[5],
data_in_n1[5],
data_in_n0[4],
data_in_n1[4],
data_in_n0[3],
data_in_n1[3],
data_in_n0[2],
data_in_n1[2],
data_in_n0[1],
data_in_n1[1],
data_in_n0[0],
data_in_n1[0]
};
end
mult_add_demo u_mult_add_demo (
.clk (clkin_bufr),
.rst (io_reset),
.ad_din(ad_dat),
.ad_ndc(ad_ndc)
);
endmodule
| 7.010886 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module adi_jesd204_glue (
input in_pll_powerdown,
output out_pll_powerdown,
output out_mcgb_rst,
output out_pll_select_gnd
);
assign out_pll_powerdown = in_pll_powerdown;
assign out_mcgb_rst = in_pll_powerdown;
assign out_pll_select_gnd = 1'b0;
endmodule
| 8.180735 |
module of our architecture.
Use this please cite:
[1] Yang. Zhijie, Wang. Lei, et al., "Bactran: A Hardware Batch Normalization Implementation for CNN Training Engine," in IEEE Embedded Systems Letters, vol. 13, no. 1, pp. 29-32, March 2021.
This code follows the MIT License
Copyright (c) 2021 Yang Zhijie and Wang Lei of National University of Defense Technology, P.R.China
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
module adj(
gamma_in,
beta_in,
x_in,
start_bn_tra_in,
start_bn_tra_out,
x_out
);
parameter DATA_WIDTH = 16;
parameter MINI_BATCH = 64;
parameter ADDR_WIDTH = $clog2(MINI_BATCH);
input signed [DATA_WIDTH-1:0] x_in;
input signed [DATA_WIDTH-1:0] gamma_in;
input signed [DATA_WIDTH-1:0] beta_in;
input start_bn_tra_in;
output start_bn_tra_out;
output signed [DATA_WIDTH-1:0] x_out;
assign x_out = start_bn_tra_in?((gamma_in * x_in) + beta_in):{DATA_WIDTH{1'b0}};
assign start_bn_tra_out = start_bn_tra_in?start_bn_tra_in:1'b0;
endmodule
| 6.78689 |
module AdjClockDivider #(
parameter INPUT_BIT_WIDTH = 8
) (
input Clk,
input ClkEnable,
input [(INPUT_BIT_WIDTH-1):0] FrequencyDividerFactor,
output reg ClkOutput,
output reg ClkEnableOutput
);
reg [(INPUT_BIT_WIDTH-1):0] InternalCounter;
initial InternalCounter = 0;
always @(posedge Clk) begin
ClkEnableOutput <= 0;
if (ClkEnable) begin
InternalCounter <= InternalCounter + 1;
if (InternalCounter >= FrequencyDividerFactor - 1) begin
InternalCounter <= 0;
ClkOutput <= !ClkOutput;
ClkEnableOutput <= 1;
end
end
end
endmodule
| 6.962823 |
module adjust ( //outputs the siz most significant bit with corresponding decimal
input clk,
rst_n,
input start,
input [3:0] dig0,
dig1,
dig2,
dig3,
dig4,
dig5,
dig6,
dig7,
dig8,
dig9,
dig10,
output [4:0] in0,
in1,
in2,
in3,
in4,
in5, //6 most significant digits
output reg done_tick
);
//FSM state declarations
localparam [1:0] idle = 2'd0, op = 2'd1, done = 2'd2;
reg [1:0] state_reg, state_nxt;
reg [4:0]
dig0_reg,
dig1_reg,
dig2_reg,
dig3_reg,
dig4_reg,
dig5_reg,
dig6_reg,
dig7_reg,
dig8_reg,
dig9_reg,
dig10_reg;
reg [4:0]
dig0_nxt,
dig1_nxt,
dig2_nxt,
dig3_nxt,
dig4_nxt,
dig5_nxt,
dig6_nxt,
dig7_nxt,
dig8_nxt,
dig9_nxt,
dig10_nxt;
//FSM register operations
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
state_reg <= idle;
dig0_reg <= 0;
dig1_reg <= 0;
dig2_reg <= 0;
dig3_reg <= 0;
dig4_reg <= 0;
dig5_reg <= 0;
dig6_reg <= 0;
dig7_reg <= 0;
dig8_reg <= 0;
dig9_reg <= 0;
dig10_reg <= 0;
end else begin
state_reg <= state_nxt;
dig0_reg <= dig0_nxt;
dig1_reg <= dig1_nxt;
dig2_reg <= dig2_nxt;
dig3_reg <= dig3_nxt;
dig4_reg <= dig4_nxt;
dig5_reg <= dig5_nxt;
dig6_reg <= dig6_nxt;
dig7_reg <= dig7_nxt;
dig8_reg <= dig8_nxt;
dig9_reg <= dig9_nxt;
dig10_reg <= dig10_nxt;
end
end
//FSM next-state declarations
always @* begin
state_nxt = state_reg;
dig0_nxt = dig0_reg;
dig1_nxt = dig1_reg;
dig2_nxt = dig2_reg;
dig3_nxt = dig3_reg;
dig4_nxt = dig4_reg;
dig5_nxt = dig5_reg;
dig6_nxt = dig6_reg;
dig7_nxt = dig7_reg;
dig8_nxt = dig8_reg;
dig9_nxt = dig9_reg;
dig10_nxt = dig10_reg;
done_tick = 0;
case (state_reg)
idle:
if (start) begin
dig0_nxt = {1'b0, dig0};
dig1_nxt = {1'b0, dig1};
dig2_nxt = {1'b0, dig2};
dig3_nxt = {1'b0, dig3};
dig4_nxt = {1'b0, dig4};
dig5_nxt = {1'b1, dig5}; //decimal digit before the last 5 digits
dig6_nxt = {1'b0, dig6};
dig7_nxt = {1'b0, dig7};
dig8_nxt = {1'b0, dig8};
dig9_nxt = {1'b0, dig9};
dig10_nxt = {1'b0, dig10};
state_nxt = op;
end
op: begin
if (dig10_nxt == 0) begin
{dig0_nxt,dig1_nxt,dig2_nxt,dig3_nxt,dig4_nxt,dig5_nxt,dig6_nxt,dig7_nxt,dig8_nxt,dig9_nxt,dig10_nxt}=
{dig0_nxt,dig1_nxt,dig2_nxt,dig3_nxt,dig4_nxt,dig5_nxt,dig6_nxt,dig7_nxt,dig8_nxt,dig9_nxt,dig10_nxt}>>5;
end else state_nxt = done;
end
done: begin
done_tick = 1;
state_nxt = idle;
end
default: state_nxt = idle;
endcase
end
assign in5 = dig10_reg,
in4 = dig9_reg,
in3 = dig8_reg,
in2 = dig7_reg,
in1 = dig6_reg,
in0 = dig5_reg;
endmodule
| 6.82266 |
module AdjustableLED_top (
input CLK_24MHz,
output LED
);
// 功能：把 ADC 和 PWM 模块以一定的逻辑组合，实现旋旋钮可以调 LED 亮度
wire [11:0] dout;
ADC_drv ADC_drv_0 (
.CLK_24MHz(CLK_24MHz),
.dout (dout) // 转换结果
);
PWM_module #(8) PWM_module_0 (
.clk_in(CLK_24MHz),
.en(1'b1),
.duty_cycle(dout[11:4]), // 传入 ADC 转换结果的高 8 位
.pwm_out(LED)
);
endmodule
| 9.767535 |
module AdjustableLED_withUART_top (
input CLK_24MHz,
output LED,
output TX_USB, // 两个 TX 引脚，一个转换成 USB 接给电脑，一个接到 3 号引脚，可供逻辑分析仪采样
output TX_GPIO
);
// 功能：旋旋钮可以调 LED 亮度，且每隔一段时间会通过 UART 发送 ADC 转换结果的高 8 位（时间间隔由 UART_TX_ticker 控制）
wire [11:0] dout;
wire UART_start_signal;
ADC_drv ADC_drv_0 (
.CLK_24MHz(CLK_24MHz),
.dout (dout) // 转换结果
);
PWM_module #(8) PWM_module_0 (
.clk_in(CLK_24MHz),
.en(1'b1),
.duty_cycle(dout[11:4]), // 传入 ADC 转换结果的高 8 位
.pwm_out(LED)
);
UART_TX_ticker UART_TX_ticker_0 (
.CLK_24MHz(CLK_24MHz),
.emit(UART_start_signal)
);
UART_TX UART_TX_0 (
.CLK_24MHz(CLK_24MHz),
.data_in(dout[11:4]),
.start(UART_start_signal),
.TX(TX_GPIO)
);
assign TX_USB = TX_GPIO;
endmodule
| 9.767535 |
module CW_TOP_WRAPPER (
jtdi,
jtck,
jrstn,
jscan,
jshift,
jupdate,
jtdo,
non_bus_din,
bus_din,
trig_clk,
wt_ce,
wt_en,
wt_addr
);
localparam DEFAULT_CTRL_REG_LEN = 89;
localparam DEFAULT_STAT_REG_LEN = 18;
localparam DEFAULT_STOP_LEN = 682;
localparam DEFAULT_NON_BUS_NODE_NUM = 0;
localparam DEFAULT_BUS_NODE_NUM = 8;
localparam DEFAULT_BUS_NUM = 1;
localparam DEFAULT_BUS1_WIDTH = 8;
input jtdi;
input jtck;
input jrstn;
input [1:0] jscan;
input jshift;
input jupdate;
output [1:0] jtdo;
input trig_clk;
input [DEFAULT_NON_BUS_NODE_NUM-1:0] non_bus_din;
input [DEFAULT_BUS_NODE_NUM-1:0] bus_din;
output wt_ce;
output wt_en;
output [15:0] wt_addr;
cwc_top #(
.BUS1_WIDTH(DEFAULT_BUS1_WIDTH),
.CTRL_REG_LEN(DEFAULT_CTRL_REG_LEN),
.STAT_REG_LEN(DEFAULT_STAT_REG_LEN),
.STOP_LEN(DEFAULT_STOP_LEN),
.NON_BUS_NODE_NUM(DEFAULT_NON_BUS_NODE_NUM),
.BUS_NODE_NUM(DEFAULT_BUS_NODE_NUM),
.BUS_NUM(DEFAULT_BUS_NUM)
) wrapper_cwc_top (
.jtdi(jtdi),
.jtck(jtck),
.jrstn(jrstn),
.jscan(jscan),
.jshift(jshift),
.jupdate(jupdate),
.jtdo(jtdo),
.non_bus_din(non_bus_din),
.bus_din(bus_din),
.trig_clk(trig_clk),
.wt_ce(wt_ce),
.wt_en(wt_en),
.wt_addr(wt_addr)
);
endmodule
| 6.891339 |
module ao22 (
A0,
A1,
B0,
B1,
Y
);
input A0, A1, B0, B1;
output Y;
wire int_res_0, int_res_1;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
and (int_res_0, A0, A1);
and (int_res_1, B0, B1);
or (Y, int_res_0, int_res_1);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
specparam tpd_B0_Y = 0;
specparam tpd_B1_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
(B0 => Y) = tpd_B0_Y;
(B1 => Y) = tpd_B1_Y;
endspecify
endmodule
| 6.606571 |
module aoi22 (
A0,
A1,
B0,
B1,
Y
);
input A0, A1, B0, B1;
output Y;
wire int_res_0, int_res_1;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
and (int_res_0, A0, A1);
and (int_res_1, B0, B1);
nor (Y, int_res_0, int_res_1);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
specparam tpd_B0_Y = 0;
specparam tpd_B1_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
(B0 => Y) = tpd_B0_Y;
(B1 => Y) = tpd_B1_Y;
endspecify
endmodule
| 7.057725 |
module aoi32 (
A0,
A1,
A2,
B0,
B1,
Y
);
input A0, A1, A2, B0, B1;
output Y;
wire int_res_0, int_res_1;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
and (int_res_0, A0, A1, A2);
and (int_res_1, B0, B1);
nor (Y, int_res_0, int_res_1);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
specparam tpd_A2_Y = 0;
specparam tpd_B0_Y = 0;
specparam tpd_B1_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
(A2 => Y) = tpd_A2_Y;
(B0 => Y) = tpd_B0_Y;
(B1 => Y) = tpd_B1_Y;
endspecify
endmodule
| 6.735591 |
module aoi322 (
A0,
A1,
A2,
B0,
B1,
C0,
C1,
Y
);
input A0, A1, A2, B0, B1, C0, C1;
output Y;
wire int_res_0, int_res_1, int_res_2;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
and (int_res_0, A0, A1, A2);
and (int_res_1, B0, B1);
and (int_res_2, C0, C1);
nor (Y, int_res_0, int_res_1, int_res_2);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
specparam tpd_A2_Y = 0;
specparam tpd_B0_Y = 0;
specparam tpd_B1_Y = 0;
specparam tpd_C0_Y = 0;
specparam tpd_C1_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
(A2 => Y) = tpd_A2_Y;
(B0 => Y) = tpd_B0_Y;
(B1 => Y) = tpd_B1_Y;
(C0 => Y) = tpd_C0_Y;
(C1 => Y) = tpd_C1_Y;
endspecify
endmodule
| 6.813297 |
module aoi422 (
A0,
A1,
A2,
A3,
B0,
B1,
C0,
C1,
Y
);
input A0, A1, A2, A3, B0, B1, C0, C1;
output Y;
wire int_res_0, int_res_1, int_res_2;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
and (int_res_0, A0, A1, A2, A3);
and (int_res_1, B0, B1);
and (int_res_2, C0, C1);
nor (Y, int_res_0, int_res_1, int_res_2);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
specparam tpd_A2_Y = 0;
specparam tpd_A3_Y = 0;
specparam tpd_B0_Y = 0;
specparam tpd_B1_Y = 0;
specparam tpd_C0_Y = 0;
specparam tpd_C1_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
(A2 => Y) = tpd_A2_Y;
(A3 => Y) = tpd_A3_Y;
(B0 => Y) = tpd_B0_Y;
(B1 => Y) = tpd_B1_Y;
(C0 => Y) = tpd_C0_Y;
(C1 => Y) = tpd_C1_Y;
endspecify
endmodule
| 6.638475 |
module aoi43 (
A0,
A1,
A2,
A3,
B0,
B1,
B2,
Y
);
input A0, A1, A2, A3, B0, B1, B2;
output Y;
wire int_res_0, int_res_1;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
and (int_res_0, A0, A1, A2, A3);
and (int_res_1, B0, B1, B2);
nor (Y, int_res_0, int_res_1);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
specparam tpd_A2_Y = 0;
specparam tpd_A3_Y = 0;
specparam tpd_B0_Y = 0;
specparam tpd_B1_Y = 0;
specparam tpd_B2_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
(A2 => Y) = tpd_A2_Y;
(A3 => Y) = tpd_A3_Y;
(B0 => Y) = tpd_B0_Y;
(B1 => Y) = tpd_B1_Y;
(B2 => Y) = tpd_B2_Y;
endspecify
endmodule
| 6.615017 |
module aoi44 (
A0,
A1,
A2,
A3,
B0,
B1,
B2,
B3,
Y
);
input A0, A1, A2, A3, B0, B1, B2, B3;
output Y;
wire int_res_0, int_res_1;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
and (int_res_0, A0, A1, A2, A3);
and (int_res_1, B0, B1, B2, B3);
nor (Y, int_res_0, int_res_1);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
specparam tpd_A2_Y = 0;
specparam tpd_A3_Y = 0;
specparam tpd_B0_Y = 0;
specparam tpd_B1_Y = 0;
specparam tpd_B2_Y = 0;
specparam tpd_B3_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
(A2 => Y) = tpd_A2_Y;
(A3 => Y) = tpd_A3_Y;
(B0 => Y) = tpd_B0_Y;
(B1 => Y) = tpd_B1_Y;
(B2 => Y) = tpd_B2_Y;
(B3 => Y) = tpd_B3_Y;
endspecify
endmodule
| 6.663237 |
module buf02 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
buf (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A_Y = 0;
(A => Y) = tpd_A_Y;
endspecify
endmodule
| 7.922813 |
module buf04 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
buf (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A_Y = 0;
(A => Y) = tpd_A_Y;
endspecify
endmodule
| 7.494585 |
module buf08 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
buf (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A_Y = 0;
(A => Y) = tpd_A_Y;
endspecify
endmodule
| 7.740929 |
module buf12 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
buf (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A_Y = 0;
(A => Y) = tpd_A_Y;
endspecify
endmodule
| 7.784322 |
module buf16 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
buf (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A_Y = 0;
(A => Y) = tpd_A_Y;
endspecify
endmodule
| 7.89655 |
module hadd1 (
A,
B,
S,
CO
);
input A, B;
output S, CO;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
xor (S, A, B);
and (CO, A, B);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A_S = 0;
specparam tpd_B_S = 0;
specparam tpd_A_CO = 0;
specparam tpd_B_CO = 0;
(A => S) = tpd_A_S;
(B => S) = tpd_B_S;
(A => CO) = tpd_A_CO;
(B => CO) = tpd_B_CO;
endspecify
endmodule
| 6.567803 |
module inv01 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
not (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A_Y = 0;
(A => Y) = tpd_A_Y;
endspecify
endmodule
| 7.312233 |
module inv02 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
not (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A_Y = 0;
(A => Y) = tpd_A_Y;
endspecify
endmodule
| 7.49528 |
module inv04 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
not (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A_Y = 0;
(A => Y) = tpd_A_Y;
endspecify
endmodule
| 6.969787 |
module inv08 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
not (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A_Y = 0;
(A => Y) = tpd_A_Y;
endspecify
endmodule
| 7.341756 |
module inv12 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
not (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A_Y = 0;
(A => Y) = tpd_A_Y;
endspecify
endmodule
| 7.325393 |
module inv16 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
not (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A_Y = 0;
(A => Y) = tpd_A_Y;
endspecify
endmodule
| 7.748685 |
module mux21 (
A0,
A1,
S0,
Y
);
input A0, A1, S0;
output Y;
wire int_res_mux1;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
mux2(
int_res_mux1, A1, A0, S0
);
not (Y, int_res_mux1);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_S0_Y = 0;
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
(S0 => Y) = tpd_S0_Y;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
endspecify
endmodule
| 7.260349 |
module nor02 (
A0,
A1,
Y
);
input A0, A1;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
nor (Y, A0, A1);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
endspecify
endmodule
| 7.041649 |
module nor02_2x (
A0,
A1,
Y
);
input A0, A1;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
nor (Y, A0, A1);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
endspecify
endmodule
| 7.147605 |
module nor03 (
A0,
A1,
A2,
Y
);
input A0, A1, A2;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
nor (Y, A0, A1, A2);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
specparam tpd_A2_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
(A2 => Y) = tpd_A2_Y;
endspecify
endmodule
| 6.776007 |
module nor03_2x (
A0,
A1,
A2,
Y
);
input A0, A1, A2;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
nor (Y, A0, A1, A2);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
specparam tpd_A2_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
(A2 => Y) = tpd_A2_Y;
endspecify
endmodule
| 6.876296 |
module nor04 (
A0,
A1,
A2,
A3,
Y
);
input A0, A1, A2, A3;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
nor (Y, A0, A1, A2, A3);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
specparam tpd_A2_Y = 0;
specparam tpd_A3_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
(A2 => Y) = tpd_A2_Y;
(A3 => Y) = tpd_A3_Y;
endspecify
endmodule
| 7.069874 |
module nor04_2x (
A0,
A1,
A2,
A3,
Y
);
input A0, A1, A2, A3;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
nor (Y, A0, A1, A2, A3);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
specparam tpd_A2_Y = 0;
specparam tpd_A3_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
(A2 => Y) = tpd_A2_Y;
(A3 => Y) = tpd_A3_Y;
endspecify
endmodule
| 7.002364 |
module oai22 (
A0,
A1,
B0,
B1,
Y
);
input A0, A1, B0, B1;
output Y;
wire int_res_0, int_res_1;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or (int_res_0, A0, A1);
or (int_res_1, B0, B1);
nand (Y, int_res_0, int_res_1);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
specparam tpd_B0_Y = 0;
specparam tpd_B1_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
(B0 => Y) = tpd_B0_Y;
(B1 => Y) = tpd_B1_Y;
endspecify
endmodule
| 6.87237 |
module oai32 (
A0,
A1,
A2,
B0,
B1,
Y
);
input A0, A1, A2, B0, B1;
output Y;
wire int_res_0, int_res_1;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or (int_res_0, A0, A1, A2);
or (int_res_1, B0, B1);
nand (Y, int_res_0, int_res_1);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
specparam tpd_A2_Y = 0;
specparam tpd_B0_Y = 0;
specparam tpd_B1_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
(A2 => Y) = tpd_A2_Y;
(B0 => Y) = tpd_B0_Y;
(B1 => Y) = tpd_B1_Y;
endspecify
endmodule
| 6.661492 |
module oai322 (
A0,
A1,
A2,
B0,
B1,
C0,
C1,
Y
);
input A0, A1, A2, B0, B1, C0, C1;
output Y;
wire int_res_0, int_res_1, int_res_2;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or (int_res_0, A0, A1, A2);
or (int_res_1, B0, B1);
or (int_res_2, C0, C1);
nand (Y, int_res_0, int_res_1, int_res_2);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
specparam tpd_A2_Y = 0;
specparam tpd_B0_Y = 0;
specparam tpd_B1_Y = 0;
specparam tpd_C0_Y = 0;
specparam tpd_C1_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
(A2 => Y) = tpd_A2_Y;
(B0 => Y) = tpd_B0_Y;
(B1 => Y) = tpd_B1_Y;
(C0 => Y) = tpd_C0_Y;
(C1 => Y) = tpd_C1_Y;
endspecify
endmodule
| 7.023531 |
module oai332 (
A0,
A1,
A2,
B0,
B1,
B2,
C0,
C1,
Y
);
input A0, A1, A2, B0, B1, B2, C0, C1;
output Y;
wire int_res_0, int_res_1, int_res_2;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or (int_res_0, A0, A1, A2);
or (int_res_1, B0, B1, B2);
or (int_res_2, C0, C1);
nand (Y, int_res_0, int_res_1, int_res_2);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
specparam tpd_A2_Y = 0;
specparam tpd_B0_Y = 0;
specparam tpd_B1_Y = 0;
specparam tpd_B2_Y = 0;
specparam tpd_C0_Y = 0;
specparam tpd_C1_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
(A2 => Y) = tpd_A2_Y;
(B0 => Y) = tpd_B0_Y;
(B1 => Y) = tpd_B1_Y;
(B2 => Y) = tpd_B2_Y;
(C0 => Y) = tpd_C0_Y;
(C1 => Y) = tpd_C1_Y;
endspecify
endmodule
| 6.981774 |
module oai333 (
A0,
A1,
A2,
B0,
B1,
B2,
C0,
C1,
C2,
Y
);
input A0, A1, A2, B0, B1, B2, C0, C1, C2;
output Y;
wire int_res_0, int_res_1, int_res_2;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or (int_res_0, A0, A1, A2);
or (int_res_1, B0, B1, B2);
or (int_res_2, C0, C1, C2);
nand (Y, int_res_0, int_res_1, int_res_2);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
specparam tpd_A2_Y = 0;
specparam tpd_B0_Y = 0;
specparam tpd_B1_Y = 0;
specparam tpd_B2_Y = 0;
specparam tpd_C0_Y = 0;
specparam tpd_C1_Y = 0;
specparam tpd_C2_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
(A2 => Y) = tpd_A2_Y;
(B0 => Y) = tpd_B0_Y;
(B1 => Y) = tpd_B1_Y;
(B2 => Y) = tpd_B2_Y;
(C0 => Y) = tpd_C0_Y;
(C1 => Y) = tpd_C1_Y;
(C2 => Y) = tpd_C2_Y;
endspecify
endmodule
| 6.640396 |
module oai422 (
A0,
A1,
A2,
A3,
B0,
B1,
C0,
C1,
Y
);
input A0, A1, A2, A3, B0, B1, C0, C1;
output Y;
wire int_res_0, int_res_1, int_res_2;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or (int_res_0, A0, A1, A2, A3);
or (int_res_1, B0, B1);
or (int_res_2, C0, C1);
nand (Y, int_res_0, int_res_1, int_res_2);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
specparam tpd_A2_Y = 0;
specparam tpd_A3_Y = 0;
specparam tpd_B0_Y = 0;
specparam tpd_B1_Y = 0;
specparam tpd_C0_Y = 0;
specparam tpd_C1_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
(A2 => Y) = tpd_A2_Y;
(A3 => Y) = tpd_A3_Y;
(B0 => Y) = tpd_B0_Y;
(B1 => Y) = tpd_B1_Y;
(C0 => Y) = tpd_C0_Y;
(C1 => Y) = tpd_C1_Y;
endspecify
endmodule
| 7.226871 |
module oai43 (
A0,
A1,
A2,
A3,
B0,
B1,
B2,
Y
);
input A0, A1, A2, A3, B0, B1, B2;
output Y;
wire int_res_0, int_res_1;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or (int_res_0, A0, A1, A2, A3);
or (int_res_1, B0, B1, B2);
nand (Y, int_res_0, int_res_1);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
specparam tpd_A2_Y = 0;
specparam tpd_A3_Y = 0;
specparam tpd_B0_Y = 0;
specparam tpd_B1_Y = 0;
specparam tpd_B2_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
(A2 => Y) = tpd_A2_Y;
(A3 => Y) = tpd_A3_Y;
(B0 => Y) = tpd_B0_Y;
(B1 => Y) = tpd_B1_Y;
(B2 => Y) = tpd_B2_Y;
endspecify
endmodule
| 6.611682 |
module oai44 (
A0,
A1,
A2,
A3,
B0,
B1,
B2,
B3,
Y
);
input A0, A1, A2, A3, B0, B1, B2, B3;
output Y;
wire int_res_0, int_res_1;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or (int_res_0, A0, A1, A2, A3);
or (int_res_1, B0, B1, B2, B3);
nand (Y, int_res_0, int_res_1);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
specparam tpd_A2_Y = 0;
specparam tpd_A3_Y = 0;
specparam tpd_B0_Y = 0;
specparam tpd_B1_Y = 0;
specparam tpd_B2_Y = 0;
specparam tpd_B3_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
(A2 => Y) = tpd_A2_Y;
(A3 => Y) = tpd_A3_Y;
(B0 => Y) = tpd_B0_Y;
(B1 => Y) = tpd_B1_Y;
(B2 => Y) = tpd_B2_Y;
(B3 => Y) = tpd_B3_Y;
endspecify
endmodule
| 6.781542 |
module or02 (
A0,
A1,
Y
);
input A0, A1;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or (Y, A0, A1);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
endspecify
endmodule
| 6.986041 |
module or03 (
A0,
A1,
A2,
Y
);
input A0, A1, A2;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or (Y, A0, A1, A2);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
specparam tpd_A2_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
(A2 => Y) = tpd_A2_Y;
endspecify
endmodule
| 6.597657 |
module or04 (
A0,
A1,
A2,
A3,
Y
);
input A0, A1, A2, A3;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or (Y, A0, A1, A2, A3);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
specparam tpd_A2_Y = 0;
specparam tpd_A3_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
(A2 => Y) = tpd_A2_Y;
(A3 => Y) = tpd_A3_Y;
endspecify
endmodule
| 7.040051 |
module xnor2 (
A0,
A1,
Y
);
input A0, A1;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
xnor (Y, A0, A1);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
endspecify
endmodule
| 7.143751 |
module xnor2_2x (
A0,
A1,
Y
);
input A0, A1;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
xnor (Y, A0, A1);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
endspecify
endmodule
| 7.063157 |
module xor2 (
A0,
A1,
Y
);
input A0, A1;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
xor (Y, A0, A1);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
endspecify
endmodule
| 7.400566 |
module xor2_2x (
A0,
A1,
Y
);
input A0, A1;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
xor (Y, A0, A1);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specify
specparam tpd_A0_Y = 0;
specparam tpd_A1_Y = 0;
(A0 => Y) = tpd_A0_Y;
(A1 => Y) = tpd_A1_Y;
endspecify
endmodule
| 7.543408 |
module aoi21 (
Y,
A0,
A1,
B0
);
output Y;
input A0;
input A1;
input B0;
and (adk12, A0, A1);
or (adk13, adk12, B0);
not (Y, adk13);
endmodule
| 6.591789 |
module aoi22 (
Y,
A0,
A1,
B0,
B1
);
output Y;
input A0;
input A1;
input B0;
input B1;
and (adk14, A0, A1);
and (adk15, B0, B1);
or (adk16, adk14, adk15);
not (Y, adk16);
endmodule
| 6.668353 |
module aoi32 (
Y,
A0,
A1,
A2,
B0,
B1
);
output Y;
input A0;
input A1;
input A2;
input B0;
input B1;
and (adk26, A0, A1);
and (adk27, adk26, A2);
and (adk28, B0, B1);
or (adk29, adk27, adk28);
not (Y, adk29);
endmodule
| 6.72256 |
module aoi322 (
Y,
A0,
A1,
A2,
B0,
B1,
C0,
C1
);
output Y;
input A0;
input A1;
input A2;
input B0;
input B1;
input C0;
input C1;
and (adk35, A0, A1);
and (adk36, adk35, A2);
and (adk37, B0, B1);
or (adk38, adk36, adk37);
and (adk39, C0, C1);
or (adk40, adk38, adk39);
not (Y, adk40);
endmodule
| 6.813297 |
module aoi422 (
Y,
A0,
A1,
A2,
A3,
B0,
B1,
C0,
C1
);
output Y;
input A0;
input A1;
input A2;
input A3;
input B0;
input B1;
input C0;
input C1;
and (adk61, A0, A1);
and (adk62, adk61, A2);
and (adk63, adk62, A3);
and (adk64, B0, B1);
or (adk65, adk63, adk64);
and (adk66, C0, C1);
or (adk67, adk65, adk66);
not (Y, adk67);
endmodule
| 6.638475 |
module aoi43 (
Y,
A0,
A1,
A2,
A3,
B0,
B1,
B2
);
output Y;
input A0;
input A1;
input A2;
input A3;
input B0;
input B1;
input B2;
and (adk68, A0, A1);
and (adk69, adk68, A2);
and (adk70, adk69, A3);
and (adk71, B0, B1);
and (adk72, adk71, B2);
or (adk73, adk70, adk72);
not (Y, adk73);
endmodule
| 6.592009 |
module buf12 (
Y,
A
);
output Y;
input A;
buf (Y, A);
endmodule
| 6.517509 |
module buf16 (
Y,
A
);
output Y;
input A;
buf (Y, A);
endmodule
| 6.534054 |
module hadd1 (
S,
CO,
A,
B
);
output S;
output CO;
input A;
input B;
xor (S, A, B);
and (CO, A, B);
endmodule
| 6.705876 |
module inv02 (
Y,
A
);
output Y;
input A;
not (Y, A);
endmodule
| 6.539475 |
module inv12 (
Y,
A
);
output Y;
input A;
not (Y, A);
endmodule
| 6.709094 |
module inv16 (
Y,
A
);
output Y;
input A;
not (Y, A);
endmodule
| 6.805316 |
module nor02 (
Y,
A0,
A1
);
output Y;
input A0;
input A1;
or (adk107, A0, A1);
not (Y, adk107);
endmodule
| 6.671549 |
module nor04 (
Y,
A0,
A1,
A2,
A3
);
output Y;
input A0;
input A1;
input A2;
input A3;
or (adk110, A0, A1);
or (adk111, adk110, A2);
or (adk112, adk111, A3);
not (Y, adk112);
endmodule
| 6.569903 |
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