code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ADD_SUB_ALU (
input [7:0] a,
b,
input [1:0] sel,
output reg [7:0] out
);
//0 is B-A
//1 is A-B
//2 is pass A
always @(*) begin
case (sel)
2'b00: begin
out = b - a;
end
2'b01: begin
out = a - b;
end
2'b10: begin
out = a;
en... | 6.671265 |
module add_sub (
add_sub,
dataa,
datab,
cout,
overflow,
result
);
input add_sub;
input [31:0] dataa;
input [31:0] datab;
output cout;
output overflow;
output [31:0] result;
endmodule
| 7.314322 |
module it's different to the add_sub module synthesized
module add_sub_carry_out
# (parameter W = 32)
(
input wire op_mode,
input wire [W-1:0] Data_A,
input wire [W-1:0] Data_B,
output reg [W:0] Data_S
);
always @*
if(op_mode)
Data_S <= Data_A - Data_B;
else
Data_S <= Data_A + Data_B;
endmodul... | 7.525131 |
module AS_C (
a,
b,
asn,
res
);
parameter PART_LEN = 8;
input asn;
input signed [2*PART_LEN-1:0] a, b;
output signed [2*PART_LEN-1:0] res;
wire signed [PART_LEN-1:0] ra = a[2*PART_LEN-1:PART_LEN];
wire signed [PART_LEN-1:0] rb = b[2*PART_LEN-1:PART_LEN];
wire signed [PART_LEN-1:0] ia =... | 6.982091 |
module add_sub_mega (
add_sub,
dataa,
datab,
cout,
overflow,
result
);
input add_sub;
input [31:0] dataa;
input [31:0] datab;
output cout;
output overflow;
output [31:0] result;
wire sub_wire0;
wire sub_wire1;
wire [31:0] sub_wire2;
wire overflow = sub_wire0;
wire cout = ... | 6.767741 |
module add_sub_mega (
add_sub,
dataa,
datab,
cout,
overflow,
result
);
input add_sub;
input [31:0] dataa;
input [31:0] datab;
output cout;
output overflow;
output [31:0] result;
endmodule
| 6.767741 |
module add_sub_mm_gmem_m_axi_flushManager
#(parameter
NUM_READ_OUTSTANDING = 2,
NUM_WRITE_OUTSTANDING = 2
)(
input clk,
input reset,
input clk_en,
input flush,
output flush_done,
input in_AWVALID,
output out_AWVALID,
input in_AWREADY,
output out_AWREADY,
inp... | 7.021828 |
module add_sub_mm_gmem_m_axi_reg_slice #(
parameter DATA_WIDTH = 8
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [DATA_WIDTH-1:0] s_data,
input wire s_valid,
output wire s_ready,
... | 7.021828 |
module add_sub_mm_gmem_m_axi_srl #(
parameter DATA_WIDTH = 32,
ADDR_WIDTH = 6,
DEPTH = 63
) (
input wire clk,
input wire reset,
input wire clk_en,
input wire we,
input wire [DATA_WIDTH-1:0] ... | 7.021828 |
module add_sub_mm_gmem_m_axi_mem #(
parameter MEM_STYLE = "auto",
DATA_WIDTH = 32,
ADDR_WIDTH = 6,
DEPTH = 63
) (
input wire clk,
input wire reset,
input wire clk_en,
input wire we... | 7.021828 |
module add_sub_module #(
parameter data_width = 16
) (
input [data_width - 1 : 0] _A,
input [data_width - 1 : 0] _B,
input func,
output reg [data_width - 1 : 0] _C,
output reg _O
);
reg [data_width - 1 : 0] temp;
always @(*) begin
if (func) // SUB
temp = -_B;
else // ADD
... | 6.78082 |
module Add_Sub_Nbit #(
parameter N = 16
) (
A,
B,
s,
Y
);
input [N-1:0] A, B;
input s;
output [N:0] Y;
wire [N+1:0] C;
wire [N:0] A1, B1;
wire [N:0] xB;
assign A1 = {A[N-1], A};
assign B1 = {B[N-1], B};
assign xB = s ? ~B1 : B1;
assign C[0] = s;
genvar i;
genera... | 6.568365 |
module add_sub #(
parameter W = 16
) (
input [W-1:0] a,
b,
input sel,
output [W-1:0] res
);
wire ci;
wire [W:0] sum;
assign sum = {a, sel} + {(sel ? ~b : b), 1'b1};
assign res = sum[W:1];
endmodule
| 7.786454 |
module add_sub_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire [D... | 6.54176 |
module add_sub_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
reg ... | 6.54176 |
module add_sub_tb;
wire [31:0] result;
wire underflag, overflag;
reg [31:0] A, B;
reg add_or_sub;
add_sub uut (
.A(A),
.B(B),
.checkequation(add_or_sub),
.overflow(overflag),
.underflow(underflag),
.result(result)
);
initial begin
A = 32'b00111111000000000000000... | 6.6302 |
module add_share (
02 input a, b, x, y, sel, en, clk,
03 output reg out1, out2
04 );
05 wire tmp1, tmp2;
06 assign tmp1 = a * b; // tmp1需要一个乘法器
07 assign tmp2 = x * y; // tmp2需要一个乘法器
08
09 always@(posedge clk)
10 if (en) begin
11 out1 <= sel ? tmp1: tmp2; //tmp1与tmp2不同时输出有效
12 en... | 7.011185 |
module add_two_values_function_tb ();
reg [3:0] ain, bin;
wire [4:0] sum;
integer k;
add_two_values_function DUT (
.ain(ain),
.bin(bin),
.sum(sum)
);
initial begin
ain = 4'h6;
bin = 4'ha;
$display("ain=%b, bin=%b, sum=%b at time=%t", ain, bin, sum, $time);
for (k = 0; k ... | 7.038377 |
module add_two_values_task_tb ();
reg [3:0] ain, bin;
wire cout;
wire [3:0] sum;
integer k;
add_two_values_task DUT (
.ain (ain),
.bin (bin),
.cout(cout),
.sum (sum)
);
initial begin
ain = 4'h6;
bin = 4'ha;
$display("ain=%b, bin=%b, cout=%b, sum=%b at time=%t", ain, ... | 7.038377 |
module add_unit (
input add_num,
input cur_num,
input carry,
output carry_next,
output stmt
);
wire t1, t2, t3;
wire s1;
xor (s1, add_num, cur_num);
xor (stmt, s1, carry);
and (t3, add_num, cur_num);
and (t2, cur_num, carry);
and (t1, add_num, carry);
or (carry_next, t1, t2, t3);... | 7.104201 |
module add_v (
rst,
data_in,
data_out,
clk
);
input data_in, rst, clk;
output [1:0] data_out;
reg [1:0] data_out; //用00、01、11分别表示输入信号为“0、1、V”
reg [1:0] counter; //设置连0计数器
always @(posedge clk or negedge rst) begin
if (!rst) begin
counter <= 0;
data_out <= 0;
end else i... | 7.058533 |
module ADD_ver (
clk,
rst_n,
enable,
delta,
result
);
input clk, rst_n, enable;
input [31:0] delta;
output [31:0] result;
reg [31:0] result, result1, limit;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
result1 <= 32'd0;
limit <= 10240000;
end else be... | 7.103513 |
module add_wraparound_after40 (
out_value,
in_value_1,
in_value_2
);
output [5:0] out_value;
input [5:0] in_value_1, in_value_2;
wire [5:0] inter_sum;
wire [6:0] inter_sub_40;
wire cout1, cout2, is_less_than_40;
adder6bit a6b (
inter_sum,
cout1,
in_value_1,
in_value_2
... | 7.378773 |
module add_w_carry #(
parameter WIDTH = 8
) (
input c_in,
input [WIDTH-1:0] in_1,
input [WIDTH-1:0] in_2,
output [WIDTH-1:0] out,
output c_out
);
wire [WIDTH-1:0] carry;
wire [WIDTH-1:0] p;
wire [WIDTH-1:0] r;
wire [WIDTH-1:0] s;
assign c_out = carry[WIDTH-1];
genvar count_generate;
... | 8.526975 |
module Add_w_carry_16bit (
F,
A,
B,
C
);
input signed [15:0] A, B;
input C;
output reg signed [15:0] F;
always @(A) begin
if (C) F = (A + B) + 1;
else F = A + B;
end
endmodule
| 7.692912 |
module ADF (
clk,
band,
clock,
ADF_out,
LE
);
input clk; // 48 kHz
input [2:0] band; //band data
output reg clock; // clock to ADF
output reg LE; // high when Register data available
output reg ADF_out; // data to ADF
reg ADF;
reg [5:0] write;
reg [4:0] loop_count;
reg [... | 7.609584 |
module ADF4351 (
input CLK,
input RST,
input ADF_WEN, //write enable
input [31:0] WDATA, //write register
output ADF_CLK, // SPI data clock
output ADF_DATA, //data
output ADF_LE,
output ADF_WRITE_DONE
);
reg ADF_CLK_reg, ADF_CLK_reg_next;
reg ADF_DATA_reg, ADF_DATA_reg_next;
r... | 6.836414 |
module ADF4351_FREQ (
input RST,
input CLK,
input CFG_EN, //Config enable
input LO_SET, //LO_SET is high
input [23:0]FREQ, //target frequency unit = KHz
output [31:0]ADF_R0,
output [31:0]ADF_R4,
output DONE
);
reg [23:0] FreqReg, FreqRegNext;
//calculate R0 and R4
reg ... | 6.99516 |
module adf4351_tb;
reg clk_50;
reg rst_n;
reg vco_ld; //Lock Detect Output Pin. A logic high output on this pin indicates PLL lock
wire vco_clk;
wire vco_data;
wire vco_le ; //Load Enable. When LE goes high, the data stored in the 32-bit shift register is loaded into
wire vco_ce ; //Chip Enable. A logic... | 7.275426 |
module adff (
input D,
input clk,
input reset,
output Q
);
reg Qreg;
assign Q = Qreg;
always @(posedge (clk), posedge (reset)) begin
if (reset == 1) Qreg <= 1'b0;
else Qreg <= D;
end
endmodule
| 7.089232 |
module adff2dff (CLK, ARST, D, Q);
parameter WIDTH = 1;
parameter CLK_POLARITY = 1;
parameter ARST_POLARITY = 1;
parameter ARST_VALUE = 0;
input CLK, ARST;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
wire reg [WIDTH-1:0] NEXT_Q;
wire [1023:0] _TECHMAP_DO_ = "proc;;";
always @*
if (ARST == ARST_POLARIT... | 6.508976 |
module top (
input d,
clk,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, posedge clr)
if (clr) q <= 1'b0;
else q <= d;
endmodule
| 7.233807 |
module adFIFO (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty
);
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
wire sub_wire0;
wire [31:0] sub_wire1;
wire rdempty = sub_wire0;
wire [31:0] q = sub_wire1[31:0];
... | 6.940264 |
module adFIFO (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty
);
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
endmodule
| 6.940264 |
module ADF_driver (
input clk, //系统时钟
input wrsig, //发送命令，上升沿有效
input [8:0] datain, //需要发送的数据
output reg tx_idle, //线路状态指示，高为线路忙，低为线路空闲
output reg tx, //发送数据信号
output reg clkout,
output reg LE
);
reg tx_send = 0;
reg tx_wrsigbuf = 0, tx_wrsigrise = 0;
reg [7:0]... | 7.150348 |
module adgetnew2_0 (
input wire clk, // clock_reset.clk
input wire reset_n, // .reset_n
input wire [ 1:0] addr, // avalon_slave_0.address
input wire read_n, // .read_n
input wire cs_n, // .chipselect_n... | 6.534725 |
modules
module adh_mux (alu,
pch,
dreg,
sel,
y);
input [7:0] alu; // alu inputs
input [7:0] pch; // program counter hi inputs
input [7:0] dreg; // D reg inputs
input [3:0] sel; // Select
output [7:0] y; // y outputs
parameter zero = 8'b 00000000; // zero page
// Note that this is coded... | 7.791918 |
module adio_bk (
input [7:0] din_p,
input [7:0] din_n,
input io_reset,
input clkin_sys,
input clkin_bufr,
output [15:0] o_dout_pin
);
wire [ 7:0] data_in_n0;
wire [ 7:0] data_in_n1;
reg [15:0] ad_dat;
wire [15:0] ad_ndc;
assign o_dout_pin = ad_ndc;
gpio_ddio8_... | 7.010886 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module of our architecture.
Use this please cite:
[1] Yang. Zhijie, Wang. Lei, et al., "Bactran: A Hardware Batch Normalization Implementation for CNN Training Engine," in IEEE Embedded Systems Letters, vol. 13, no. 1, pp. 29-32, March 2021.
This code follows the MIT License
Copyright (c) 2021 Yang Zhijie and Wang... | 6.78689 |
module AdjClockDivider #(
parameter INPUT_BIT_WIDTH = 8
) (
input Clk,
input ClkEnable,
input [(INPUT_BIT_WIDTH-1):0] FrequencyDividerFactor,
output reg ClkOutput,
output reg ClkEnableOutput
);
reg [(INPUT_BIT_WIDTH-1):0] InternalCounter;
initial InternalCounter = 0;
always @(posedge Cl... | 6.962823 |
module adjust ( //outputs the siz most significant bit with corresponding decimal
input clk,
rst_n,
input start,
input [3:0] dig0,
dig1,
dig2,
dig3,
dig4,
dig5,
dig6,
dig7,
dig8,
dig9,
dig10,
output [4:0] in0,
in1,
in2,
in3,
in4,
in5, //6... | 6.82266 |
module AdjustableLED_top (
input CLK_24MHz,
output LED
);
// 功能：把 ADC 和 PWM 模块以一定的逻辑组合，实现旋旋钮可以调 LED 亮度
wire [11:0] dout;
ADC_drv ADC_drv_0 (
.CLK_24MHz(CLK_24MHz),
.dout (dout) // 转换结果
);
PWM_module #(8) PWM_module_0 (
.clk_in(CLK_24MHz),
.en(1'b1),
.duty_... | 9.767535 |
module AdjustableLED_withUART_top (
input CLK_24MHz,
output LED,
output TX_USB, // 两个 TX 引脚，一个转换成 USB 接给电脑，一个接到 3 号引脚，可供逻辑分析仪采样
output TX_GPIO
);
// 功能：旋旋钮可以调 LED 亮度，且每隔一段时间会通过 UART 发送 ADC 转换结果的高 8 位（时间间隔由 UART_TX_ticker 控制）
wire [11:0] dout;
wire UART_start_signal;
ADC_drv ADC_drv_0 (
... | 9.767535 |
module CW_TOP_WRAPPER (
jtdi,
jtck,
jrstn,
jscan,
jshift,
jupdate,
jtdo,
non_bus_din,
bus_din,
trig_clk,
wt_ce,
wt_en,
wt_addr
);
localparam DEFAULT_CTRL_REG_LEN = 89;
localparam DEFAULT_STAT_REG_LEN = 18;
localparam DEFAULT_STOP_LEN = 682;
localparam DEFAULT_... | 6.891339 |
module ao22 (
A0,
A1,
B0,
B1,
Y
);
input A0, A1, B0, B1;
output Y;
wire int_res_0, int_res_1;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
and (int_res_0, A0, A1);
and (int_res_1, B0, B1);
or (Y, int_res_0, int... | 6.606571 |
module aoi22 (
A0,
A1,
B0,
B1,
Y
);
input A0, A1, B0, B1;
output Y;
wire int_res_0, int_res_1;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
and (int_res_0, A0, A1);
and (int_res_1, B0, B1);
nor (Y, int_res_0, i... | 7.057725 |
module aoi32 (
A0,
A1,
A2,
B0,
B1,
Y
);
input A0, A1, A2, B0, B1;
output Y;
wire int_res_0, int_res_1;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
and (int_res_0, A0, A1, A2);
and (int_res_1, B0, B1);
nor ... | 6.735591 |
module aoi322 (
A0,
A1,
A2,
B0,
B1,
C0,
C1,
Y
);
input A0, A1, A2, B0, B1, C0, C1;
output Y;
wire int_res_0, int_res_1, int_res_2;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
and (int_res_0, A0, A1, A2... | 6.813297 |
module aoi422 (
A0,
A1,
A2,
A3,
B0,
B1,
C0,
C1,
Y
);
input A0, A1, A2, A3, B0, B1, C0, C1;
output Y;
wire int_res_0, int_res_1, int_res_2;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
and (int_res_0... | 6.638475 |
module aoi43 (
A0,
A1,
A2,
A3,
B0,
B1,
B2,
Y
);
input A0, A1, A2, A3, B0, B1, B2;
output Y;
wire int_res_0, int_res_1;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
and (int_res_0, A0, A1, A2, A3);
and... | 6.615017 |
module aoi44 (
A0,
A1,
A2,
A3,
B0,
B1,
B2,
B3,
Y
);
input A0, A1, A2, A3, B0, B1, B2, B3;
output Y;
wire int_res_0, int_res_1;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
and (int_res_0, A0, A1, A2... | 6.663237 |
module buf02 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
buf (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specif... | 7.922813 |
module buf04 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
buf (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specif... | 7.494585 |
module buf08 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
buf (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specif... | 7.740929 |
module buf12 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
buf (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specif... | 7.784322 |
module buf16 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
buf (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specif... | 7.89655 |
module hadd1 (
A,
B,
S,
CO
);
input A, B;
output S, CO;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
xor (S, A, B);
and (CO, A, B);
/////////////////////////////////////
// TIMING //
////... | 6.567803 |
module inv01 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
not (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specif... | 7.312233 |
module inv02 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
not (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specif... | 7.49528 |
module inv04 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
not (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specif... | 6.969787 |
module inv08 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
not (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specif... | 7.341756 |
module inv12 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
not (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specif... | 7.325393 |
module inv16 (
A,
Y
);
input A;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
not (Y, A);
/////////////////////////////////////
// TIMING //
/////////////////////////////////////
specif... | 7.748685 |
module mux21 (
A0,
A1,
S0,
Y
);
input A0, A1, S0;
output Y;
wire int_res_mux1;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
mux2(
int_res_mux1, A1, A0, S0
);
not (Y, int_res_mux1);
////////////////////////... | 7.260349 |
module nor02 (
A0,
A1,
Y
);
input A0, A1;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
nor (Y, A0, A1);
/////////////////////////////////////
// TIMING //
////////////////////////////... | 7.041649 |
module nor02_2x (
A0,
A1,
Y
);
input A0, A1;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
nor (Y, A0, A1);
/////////////////////////////////////
// TIMING //
/////////////////////////... | 7.147605 |
module nor03 (
A0,
A1,
A2,
Y
);
input A0, A1, A2;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
nor (Y, A0, A1, A2);
/////////////////////////////////////
// TIMING //
////////////... | 6.776007 |
module nor03_2x (
A0,
A1,
A2,
Y
);
input A0, A1, A2;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
nor (Y, A0, A1, A2);
/////////////////////////////////////
// TIMING //
/////////... | 6.876296 |
module nor04 (
A0,
A1,
A2,
A3,
Y
);
input A0, A1, A2, A3;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
nor (Y, A0, A1, A2, A3);
/////////////////////////////////////
// TIMING /... | 7.069874 |
module nor04_2x (
A0,
A1,
A2,
A3,
Y
);
input A0, A1, A2, A3;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
nor (Y, A0, A1, A2, A3);
/////////////////////////////////////
// TIMING ... | 7.002364 |
module oai22 (
A0,
A1,
B0,
B1,
Y
);
input A0, A1, B0, B1;
output Y;
wire int_res_0, int_res_1;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or (int_res_0, A0, A1);
or (int_res_1, B0, B1);
nand (Y, int_res_0, in... | 6.87237 |
module oai32 (
A0,
A1,
A2,
B0,
B1,
Y
);
input A0, A1, A2, B0, B1;
output Y;
wire int_res_0, int_res_1;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or (int_res_0, A0, A1, A2);
or (int_res_1, B0, B1);
nand (... | 6.661492 |
module oai322 (
A0,
A1,
A2,
B0,
B1,
C0,
C1,
Y
);
input A0, A1, A2, B0, B1, C0, C1;
output Y;
wire int_res_0, int_res_1, int_res_2;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or (int_res_0, A0, A1, A2)... | 7.023531 |
module oai332 (
A0,
A1,
A2,
B0,
B1,
B2,
C0,
C1,
Y
);
input A0, A1, A2, B0, B1, B2, C0, C1;
output Y;
wire int_res_0, int_res_1, int_res_2;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or (int_res_0,... | 6.981774 |
module oai333 (
A0,
A1,
A2,
B0,
B1,
B2,
C0,
C1,
C2,
Y
);
input A0, A1, A2, B0, B1, B2, C0, C1, C2;
output Y;
wire int_res_0, int_res_1, int_res_2;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or... | 6.640396 |
module oai422 (
A0,
A1,
A2,
A3,
B0,
B1,
C0,
C1,
Y
);
input A0, A1, A2, A3, B0, B1, C0, C1;
output Y;
wire int_res_0, int_res_1, int_res_2;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or (int_res_0,... | 7.226871 |
module oai43 (
A0,
A1,
A2,
A3,
B0,
B1,
B2,
Y
);
input A0, A1, A2, A3, B0, B1, B2;
output Y;
wire int_res_0, int_res_1;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or (int_res_0, A0, A1, A2, A3);
or (... | 6.611682 |
module oai44 (
A0,
A1,
A2,
A3,
B0,
B1,
B2,
B3,
Y
);
input A0, A1, A2, A3, B0, B1, B2, B3;
output Y;
wire int_res_0, int_res_1;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or (int_res_0, A0, A1, A2,... | 6.781542 |
module or02 (
A0,
A1,
Y
);
input A0, A1;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or (Y, A0, A1);
/////////////////////////////////////
// TIMING //
//////////////////////////////... | 6.986041 |
module or03 (
A0,
A1,
A2,
Y
);
input A0, A1, A2;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or (Y, A0, A1, A2);
/////////////////////////////////////
// TIMING //
//////////////... | 6.597657 |
module or04 (
A0,
A1,
A2,
A3,
Y
);
input A0, A1, A2, A3;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
or (Y, A0, A1, A2, A3);
/////////////////////////////////////
// TIMING //
... | 7.040051 |
module xnor2 (
A0,
A1,
Y
);
input A0, A1;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
xnor (Y, A0, A1);
/////////////////////////////////////
// TIMING //
///////////////////////////... | 7.143751 |
module xnor2_2x (
A0,
A1,
Y
);
input A0, A1;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
xnor (Y, A0, A1);
/////////////////////////////////////
// TIMING //
////////////////////////... | 7.063157 |
module xor2 (
A0,
A1,
Y
);
input A0, A1;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
xor (Y, A0, A1);
/////////////////////////////////////
// TIMING //
/////////////////////////////... | 7.400566 |
module xor2_2x (
A0,
A1,
Y
);
input A0, A1;
output Y;
/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////
xor (Y, A0, A1);
/////////////////////////////////////
// TIMING //
//////////////////////////... | 7.543408 |
module aoi21 (
Y,
A0,
A1,
B0
);
output Y;
input A0;
input A1;
input B0;
and (adk12, A0, A1);
or (adk13, adk12, B0);
not (Y, adk13);
endmodule
| 6.591789 |
module aoi22 (
Y,
A0,
A1,
B0,
B1
);
output Y;
input A0;
input A1;
input B0;
input B1;
and (adk14, A0, A1);
and (adk15, B0, B1);
or (adk16, adk14, adk15);
not (Y, adk16);
endmodule
| 6.668353 |
module aoi32 (
Y,
A0,
A1,
A2,
B0,
B1
);
output Y;
input A0;
input A1;
input A2;
input B0;
input B1;
and (adk26, A0, A1);
and (adk27, adk26, A2);
and (adk28, B0, B1);
or (adk29, adk27, adk28);
not (Y, adk29);
endmodule
| 6.72256 |
module aoi322 (
Y,
A0,
A1,
A2,
B0,
B1,
C0,
C1
);
output Y;
input A0;
input A1;
input A2;
input B0;
input B1;
input C0;
input C1;
and (adk35, A0, A1);
and (adk36, adk35, A2);
and (adk37, B0, B1);
or (adk38, adk36, adk37);
and (adk39, C0, C1);
or (adk40, adk38, ... | 6.813297 |
module aoi422 (
Y,
A0,
A1,
A2,
A3,
B0,
B1,
C0,
C1
);
output Y;
input A0;
input A1;
input A2;
input A3;
input B0;
input B1;
input C0;
input C1;
and (adk61, A0, A1);
and (adk62, adk61, A2);
and (adk63, adk62, A3);
and (adk64, B0, B1);
or (adk65, adk63, adk64... | 6.638475 |
module aoi43 (
Y,
A0,
A1,
A2,
A3,
B0,
B1,
B2
);
output Y;
input A0;
input A1;
input A2;
input A3;
input B0;
input B1;
input B2;
and (adk68, A0, A1);
and (adk69, adk68, A2);
and (adk70, adk69, A3);
and (adk71, B0, B1);
and (adk72, adk71, B2);
or (adk73, adk70, ... | 6.592009 |
module buf12 (
Y,
A
);
output Y;
input A;
buf (Y, A);
endmodule
| 6.517509 |
module buf16 (
Y,
A
);
output Y;
input A;
buf (Y, A);
endmodule
| 6.534054 |
module hadd1 (
S,
CO,
A,
B
);
output S;
output CO;
input A;
input B;
xor (S, A, B);
and (CO, A, B);
endmodule
| 6.705876 |
module inv02 (
Y,
A
);
output Y;
input A;
not (Y, A);
endmodule
| 6.539475 |
module inv12 (
Y,
A
);
output Y;
input A;
not (Y, A);
endmodule
| 6.709094 |
module inv16 (
Y,
A
);
output Y;
input A;
not (Y, A);
endmodule
| 6.805316 |
module nor02 (
Y,
A0,
A1
);
output Y;
input A0;
input A1;
or (adk107, A0, A1);
not (Y, adk107);
endmodule
| 6.671549 |
module nor04 (
Y,
A0,
A1,
A2,
A3
);
output Y;
input A0;
input A1;
input A2;
input A3;
or (adk110, A0, A1);
or (adk111, adk110, A2);
or (adk112, adk111, A3);
not (Y, adk112);
endmodule
| 6.569903 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.