code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module adder (
a,
b,
y
);
parameter WIDTH = 64;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_combine_64_bit (
a,
b,
Result_mul,
Result_add
);
parameter WIDTH = 64;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] Result_add;
output reg [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
.b(b),
.y(Result_mul)
);
endmodule
| 6.911403 |
module adder (
a,
b,
y
);
parameter WIDTH = 8;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_combine_8_bit (
a,
b,
Result_mul,
Result_add
);
parameter WIDTH = 8;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] Result_add;
output reg [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
.b(b),
.y(Result_mul)
);
endmodule
| 6.911403 |
module adder (
a,
b,
y
);
parameter WIDTH = 16;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_16_bit (
a,
b,
Result
);
parameter WIDTH = 16;
input [0:WIDTH-1] a, b;
output reg [0:(WIDTH*2)-1] Result;
wire A_greater_B;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
.b(b),
.y(Result_mul)
);
comparator comparator_1 (
a,
b,
A_greater_B
);
always @(*) begin
Result = A_greater_B ? Result_mul : Result_add;
end
endmodule
| 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 2;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_2_bit (
a,
b,
Result
);
parameter WIDTH = 2;
input [0:WIDTH-1] a, b;
output reg [0:(WIDTH*2)-1] Result;
wire A_greater_B;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
.b(b),
.y(Result_mul)
);
comparator comparator_1 (
a,
b,
A_greater_B
);
always @(*) begin
Result = A_greater_B ? Result_mul : Result_add;
end
endmodule
| 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 32;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_32_bit (
a,
b,
Result
);
parameter WIDTH = 32;
input [0:WIDTH-1] a, b;
output reg [0:(WIDTH*2)-1] Result;
wire A_greater_B;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
.b(b),
.y(Result_mul)
);
comparator comparator_1 (
a,
b,
A_greater_B
);
always @(*) begin
Result = A_greater_B ? Result_mul : Result_add;
end
endmodule
| 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 4;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_4_bit (
a,
b,
Result
);
parameter WIDTH = 4;
input [0:WIDTH-1] a, b;
output reg [0:(WIDTH*2)-1] Result;
wire A_greater_B;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
.b(b),
.y(Result_mul)
);
comparator comparator_1 (
a,
b,
A_greater_B
);
always @(*) begin
Result = A_greater_B ? Result_mul : Result_add;
end
endmodule
| 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 64;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_64_bit (
a,
b,
Result
);
parameter WIDTH = 64;
input [0:WIDTH-1] a, b;
output reg [0:(WIDTH*2)-1] Result;
wire A_greater_B;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
.b(b),
.y(Result_mul)
);
comparator comparator_1 (
a,
b,
A_greater_B
);
always @(*) begin
Result = A_greater_B ? Result_mul : Result_add;
end
endmodule
| 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 8;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_8_bit (
a,
b,
Result
);
parameter WIDTH = 8;
input [0:WIDTH-1] a, b;
output reg [0:(WIDTH*2)-1] Result;
wire A_greater_B;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
.b(b),
.y(Result_mul)
);
comparator comparator_1 (
a,
b,
A_greater_B
);
always @(*) begin
Result = A_greater_B ? Result_mul : Result_add;
end
endmodule
| 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 16;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_sub_16_bit(a, b,Result);
parameter WIDTH=16;
input [0:WIDTH-1]a, b;
wire [0:1]operation;
output reg [0:(WIDTH*2)-1]Result;
wire [0:(WIDTH*2)-1]Result_sub1;
wire [0:(WIDTH*2)-1]Result_sub2;
wire [0:(WIDTH*2)-1]Result_add;
wire [0:(WIDTH*2)-1]Result_mul;
subtractor subtractor_1 (.a(a), .b(b), .y(Result_sub1));
comparator comparator_1(a,b, operation[0],operation[1]);
subtractor subtractor_2 (.a(b), .b(a), .y(Result_sub2));
adder adder_1 (.a(a), .b(b), .y(Result_add));
multiplier multiplier_1 (.a(a), .b(b), .y(Result_mul));
always@(*)
begin
case(operation)
2'b00: // Addition
Result=Result_add;
2'b01: // sub1
Result=Result_sub1;
2'b10: // sub2
Result=Result_sub2;
2'b11: // mul
Result=Result_mul;
endcase
end
endmodule
| 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 2;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_sub_2_bit(a, b,Result);
parameter WIDTH=2;
input [0:WIDTH-1]a, b;
wire [0:1]operation;
output reg [0:(WIDTH*2)-1]Result;
wire [0:(WIDTH*2)-1]Result_sub1;
wire [0:(WIDTH*2)-1]Result_sub2;
wire [0:(WIDTH*2)-1]Result_add;
wire [0:(WIDTH*2)-1]Result_mul;
subtractor subtractor_1 (.a(a), .b(b), .y(Result_sub1));
comparator comparator_1(a,b, operation[0],operation[1]);
subtractor subtractor_2 (.a(b), .b(a), .y(Result_sub2));
adder adder_1 (.a(a), .b(b), .y(Result_add));
multiplier multiplier_1 (.a(a), .b(b), .y(Result_mul));
always@(*)
begin
case(operation)
2'b00: // Addition
Result=Result_add;
2'b01: // sub1
Result=Result_sub1;
2'b10: // sub2
Result=Result_sub2;
2'b11: // mul
Result=Result_mul;
endcase
end
endmodule
| 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 32;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_sub_32_bit(a, b,Result);
parameter WIDTH=32;
input [0:WIDTH-1]a, b;
wire [0:1]operation;
output reg [0:(WIDTH*2)-1]Result;
wire [0:(WIDTH*2)-1]Result_sub1;
wire [0:(WIDTH*2)-1]Result_sub2;
wire [0:(WIDTH*2)-1]Result_add;
wire [0:(WIDTH*2)-1]Result_mul;
subtractor subtractor_1 (.a(a), .b(b), .y(Result_sub1));
comparator comparator_1(a,b, operation[0],operation[1]);
subtractor subtractor_2 (.a(b), .b(a), .y(Result_sub2));
adder adder_1 (.a(a), .b(b), .y(Result_add));
multiplier multiplier_1 (.a(a), .b(b), .y(Result_mul));
always@(*)
begin
case(operation)
2'b00: // Addition
Result=Result_add;
2'b01: // sub1
Result=Result_sub1;
2'b10: // sub2
Result=Result_sub2;
2'b11: // mul
Result=Result_mul;
endcase
end
endmodule
| 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 4;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_sub_4_bit(a, b,Result);
parameter WIDTH=4;
input [0:WIDTH-1]a, b;
wire [0:1]operation;
output reg [0:(WIDTH*2)-1]Result;
wire [0:(WIDTH*2)-1]Result_sub1;
wire [0:(WIDTH*2)-1]Result_sub2;
wire [0:(WIDTH*2)-1]Result_add;
wire [0:(WIDTH*2)-1]Result_mul;
subtractor subtractor_1 (.a(a), .b(b), .y(Result_sub1));
comparator comparator_1(a,b, operation[0],operation[1]);
subtractor subtractor_2 (.a(b), .b(a), .y(Result_sub2));
adder adder_1 (.a(a), .b(b), .y(Result_add));
multiplier multiplier_1 (.a(a), .b(b), .y(Result_mul));
always@(*)
begin
case(operation)
2'b00: // Addition
Result=Result_add;
2'b01: // sub1
Result=Result_sub1;
2'b10: // sub2
Result=Result_sub2;
2'b11: // mul
Result=Result_mul;
endcase
end
endmodule
| 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 64;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_sub_64_bit(a, b,Result);
parameter WIDTH=64;
input [0:WIDTH-1]a, b;
wire [0:1]operation;
output reg [0:(WIDTH*2)-1]Result;
wire [0:(WIDTH*2)-1]Result_sub1;
wire [0:(WIDTH*2)-1]Result_sub2;
wire [0:(WIDTH*2)-1]Result_add;
wire [0:(WIDTH*2)-1]Result_mul;
subtractor subtractor_1 (.a(a), .b(b), .y(Result_sub1));
comparator comparator_1(a,b, operation[0],operation[1]);
subtractor subtractor_2 (.a(b), .b(a), .y(Result_sub2));
adder adder_1 (.a(a), .b(b), .y(Result_add));
multiplier multiplier_1 (.a(a), .b(b), .y(Result_mul));
always@(*)
begin
case(operation)
2'b00: // Addition
Result=Result_add;
2'b01: // sub1
Result=Result_sub1;
2'b10: // sub2
Result=Result_sub2;
2'b11: // mul
Result=Result_mul;
endcase
end
endmodule
| 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 8;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_sub_8_bit(a, b,Result);
parameter WIDTH=8;
input [0:WIDTH-1]a, b;
wire [0:1]operation;
output reg [0:(WIDTH*2)-1]Result;
wire [0:(WIDTH*2)-1]Result_sub1;
wire [0:(WIDTH*2)-1]Result_sub2;
wire [0:(WIDTH*2)-1]Result_add;
wire [0:(WIDTH*2)-1]Result_mul;
subtractor subtractor_1 (.a(a), .b(b), .y(Result_sub1));
comparator comparator_1(a,b, operation[0],operation[1]);
subtractor subtractor_2 (.a(b), .b(a), .y(Result_sub2));
adder adder_1 (.a(a), .b(b), .y(Result_add));
multiplier multiplier_1 (.a(a), .b(b), .y(Result_mul));
always@(*)
begin
case(operation)
2'b00: // Addition
Result=Result_add;
2'b01: // sub1
Result=Result_sub1;
2'b10: // sub2
Result=Result_sub2;
2'b11: // mul
Result=Result_mul;
endcase
end
endmodule
| 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 16;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module adder (
a,
b,
y
);
parameter WIDTH = 2;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_mix_2_bit (
a,
b,
c,
d,
Result
);
parameter WIDTH = 2;
input [0:WIDTH-1] a, b, c, d;
wire [0:WIDTH-1] Result_add_2;
wire [0:WIDTH-1] Result_add;
output reg [0:(WIDTH*2)-1] Result;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
adder adder_2 (
.a(c),
.b(d),
.y(Result_add_2)
);
multiplier multiplier_1 (
.a(Result_add),
.b(Result_add_2),
.y(Result)
);
endmodule
| 6.645763 |
module adder (
a,
b,
y
);
parameter WIDTH = 32;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_mix_32_bit (
a,
b,
c,
d,
Result
);
parameter WIDTH = 32;
input [0:WIDTH-1] a, b, c, d;
wire [0:WIDTH-1] Result_add_2;
wire [0:WIDTH-1] Result_add;
output reg [0:(WIDTH*2)-1] Result;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
adder adder_2 (
.a(c),
.b(d),
.y(Result_add_2)
);
multiplier multiplier_1 (
.a(Result_add),
.b(Result_add_2),
.y(Result)
);
endmodule
| 6.957106 |
module adder (
a,
b,
y
);
parameter WIDTH = 4;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_mix_4_bit (
a,
b,
c,
d,
Result
);
parameter WIDTH = 4;
input [0:WIDTH-1] a, b, c, d;
wire [0:WIDTH-1] Result_add_2;
wire [0:WIDTH-1] Result_add;
output reg [0:(WIDTH*2)-1] Result;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
adder adder_2 (
.a(c),
.b(d),
.y(Result_add_2)
);
multiplier multiplier_1 (
.a(Result_add),
.b(Result_add_2),
.y(Result)
);
endmodule
| 6.729989 |
module adder (
a,
b,
y
);
parameter WIDTH = 64;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_mix_64_bit (
a,
b,
c,
d,
Result
);
parameter WIDTH = 64;
input [0:WIDTH-1] a, b, c, d;
wire [0:WIDTH-1] Result_add_2;
wire [0:WIDTH-1] Result_add;
output reg [0:(WIDTH*2)-1] Result;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
adder adder_2 (
.a(c),
.b(d),
.y(Result_add_2)
);
multiplier multiplier_1 (
.a(Result_add),
.b(Result_add_2),
.y(Result)
);
endmodule
| 7.004283 |
module adder (
a,
b,
y
);
parameter WIDTH = 8;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module adder (
a,
b,
y
);
parameter WIDTH = 16;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module adder (
a,
b,
y
);
parameter WIDTH = 2;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module adder (
a,
b,
y
);
parameter WIDTH = 32;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module adder (
a,
b,
y
);
parameter WIDTH = 4;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module adder (
a,
b,
y
);
parameter WIDTH = 64;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module adder (
a,
b,
y
);
parameter WIDTH = 8;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mux (
A,
B,
cin,
s,
cout
);
input [1:0] A;
input [1:0] B;
input cin;
output reg [1:0] s;
output reg cout;
reg sel;
reg [3:0] temp;
always @(*) begin
fork
s[0] = A[0] ^ B[0] ^ cin;
sel = (A[0] & B[0]) | (A[0] ^ B[0]) & cin;
temp[1:0] = A[1] + B[1];
temp[3:2] = A[1] + B[1] + 1;
join
if (sel) {cout, s[1]} = temp[3:2];
else {cout, s[1]} = temp[1:0];
end
endmodule
| 7.750574 |
module data_extract_N32_ES6 (
in,
rc,
regime,
exp,
mant
);
function [31:0] log2;
input reg [31:0] value;
begin
value = value - 1;
for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1;
end
endfunction
parameter N = 32;
parameter Bs = log2(N);
parameter es = 5;
input [N-1:0] in;
output rc;
output [Bs-1:0] regime;
output [es-1:0] exp;
output [N-es-1:0] mant;
//Data Extraction
wire [N-1:0] xin = in;
assign rc = xin[N-2];
wire [ N-1:0] xin_r = rc ? ~xin : xin;
wire [Bs-1:0] k;
LOD_32 uut_lod32_5 (
.in ({xin_r[N-2:0], rc ^ 1'b0}),
.out(k)
);
assign regime = rc ? k - 1 : k;
wire [N-1:0] xin_tmp;
DSR_left_N_S #(
.N(N),
.S(Bs)
) ls (
.a({xin[N-3:0], 2'b0}),
.b(k),
.c(xin_tmp)
);
assign exp = xin_tmp[N-1:N-es];
assign mant = xin_tmp[N-es-1:0];
endmodule
| 8.552482 |
module add_N (
a,
b,
c
);
parameter N = 10;
input [N-1:0] a, b;
output [N:0] c;
assign c = {1'b0, a} + {1'b0, b};
endmodule
| 6.530958 |
module DSR_left_N_S (
a,
b,
c
);
parameter N = 16;
parameter S = 4;
input [N-1:0] a;
input [S-1:0] b;
output [N-1:0] c;
wire [N-1:0] tmp[S-1:0];
assign tmp[0] = b[0] ? a << 7'd1 : a;
genvar i;
generate
for (i = 1; i < S; i = i + 1) begin : loop_blk
assign tmp[i] = b[i] ? tmp[i-1] << 2 ** i : tmp[i-1];
end
endgenerate
assign c = tmp[S-1];
endmodule
| 6.55013 |
module LOD16_4 (
in,
out,
out_v
);
input [15:0] in;
output [3:0] out;
output out_v;
wire [2:0] out_l, out_h;
wire out_vl, out_vh;
LOD8_3 pl (
.in(in[7:0]),
.out(out_l),
.out_v(out_vl)
);
LOD8_3 ph (
.in(in[15:8]),
.out(out_h),
.out_v(out_vh)
);
assign out = out_vh ? {1'b0, out_h} : {out_vl, out_l};
assign out_v = out_vl | out_vh;
endmodule
| 6.780402 |
module LOD8_3 (
in,
out,
out_v
);
input [7:0] in;
output [2:0] out;
output out_v;
wire [1:0] out_l, out_h;
wire out_vl, out_vh;
LOD4_2 pl (
.in(in[3:0]),
.out(out_l),
.out_v(out_vl)
);
LOD4_2 ph (
.in(in[7:4]),
.out(out_h),
.out_v(out_vh)
);
assign out = out_vh ? {1'b0, out_h} : {out_vl, out_l};
assign out_v = out_vl | out_vh;
endmodule
| 6.634091 |
module LOD4_2 (
in,
out,
out_v
);
input [3:0] in;
output [1:0] out;
output out_v;
wire out_l, out_h;
wire out_vl, out_vh;
LOD2_1 pl (
.in(in[1:0]),
.out(out_l),
.out_v(out_vl)
);
LOD2_1 ph (
.in(in[3:2]),
.out(out_h),
.out_v(out_vh)
);
assign out = out_vh ? {1'b0, out_h} : {out_vl, out_l};
assign out_v = out_vl | out_vh;
endmodule
| 6.607174 |
module LOD2_1 (
in,
out,
out_v
);
input [1:0] in;
output out;
output out_v;
assign out = ~in[1] & in[0];
assign out_v = |in;
endmodule
| 7.042873 |
module add_normalizer (
input sign,
input [ 4:0] exponent,
input [10:0] mantissa_add,
output reg [15:0] result,
input if_carray,
input if_sub
);
reg [4:0] number_of_zero_lead;
reg [10:0] norm_mantissa_add;
reg [9:0] mantissa_tmp;
wire [4:0] shift_left_exp;
wire c1;
always @(*) begin
if (mantissa_add[10:4] == 7'b0000_001) begin
number_of_zero_lead = 5'd6;
norm_mantissa_add = (mantissa_add << 4'd6);
end else if (mantissa_add[10:5] == 6'b0000_01) begin
number_of_zero_lead = 5'd5;
norm_mantissa_add = (mantissa_add << 4'd5);
end else if (mantissa_add[10:6] == 5'b0000_1) begin
number_of_zero_lead = 5'd4;
norm_mantissa_add = (mantissa_add << 4'd4);
end else if (mantissa_add[10:7] == 4'b0001) begin
number_of_zero_lead = 5'd3;
norm_mantissa_add = (mantissa_add << 4'd3);
end else if (mantissa_add[10:8] == 3'b001) begin
number_of_zero_lead = 5'd2;
norm_mantissa_add = (mantissa_add << 4'd2);
end else if (mantissa_add[10:9] == 2'b01) begin
number_of_zero_lead = 5'd1;
norm_mantissa_add = (mantissa_add << 4'd1);
end else begin
number_of_zero_lead = 5'd0;
norm_mantissa_add = mantissa_add[10:0];
end
end
always @(*) begin
result[15] = sign;
if (!if_sub) begin
result[14:10] = if_carray ? exponent + 1'b1 : exponent;
result[9:0] = if_carray ? mantissa_add[10:1] : mantissa_add[9:0];
end else begin
result[14:10] = shift_left_exp;
result[9:0] = norm_mantissa_add[9:0];
end
end
cla_nbit #(
.n(5)
) u1 (
exponent,
~number_of_zero_lead + 1'b1,
1'b0,
shift_left_exp,
c1
);
endmodule
| 6.840817 |
module ADD_n_bit (
c_out,
ADD_out,
R2,
R3,
c_in
);
parameter word_size = 32; // the default size of this n bit adder
input [word_size-1:0] R2, R3;
input c_in;
output [word_size-1:0] ADD_out;
output c_out;
wire [word_size-1:0] c_inner;
// the c_out of the ith 1-bit full aderr is the c_in of the (i+1)th full adder
ADD_1_bit ADDER[word_size-1:0] (
{c_out, c_inner[word_size-1:1]},
ADD_out,
R2,
R3,
{c_inner[word_size-1:1], c_in}
);
endmodule
| 8.831432 |
module add_N_tb ();
// note this only runs for 50 cycles with the below settings
// alter TB_TIMEOUT to run longer
localparam TB_TIMEOUT = 100000;
localparam TB_CLK_PERIOD = 2000;
localparam TB_RST_PERIOD = 4000;
initial #(TB_TIMEOUT) $finish();
// clock
reg tb_clk = 1'b0;
always #(TB_CLK_PERIOD / 2) tb_clk = ~tb_clk;
// DUT
wire [`DATA_WIDTH-1 : 0] outp;
wire [(`NUM_ELEMS * `DATA_WIDTH) - 1 : 0] inps;
add_N_test #(
.data_width(`DATA_WIDTH),
.num_elems (`NUM_ELEMS)
) my_add_N_test (
.clk(tb_clk),
.outp(outp),
.outp_inps(inps)
);
// display inputs and output on each clock cycle
always @(posedge tb_clk) begin
$display("inps = ", inps, " => outp = ", outp);
end
endmodule
| 6.93342 |
module add_one (
input [7:0] in,
output [7:0] out
);
assign out = in + 1;
endmodule
| 6.581511 |
module add_onebit (
input wire a,
input wire b,
input wire ci,
output wire sum,
output wire co
);
//(sum,cout,a,b,cin);
//input a,b,cin;
//output sum;
//output cout;
assign sum = a ^ b ^ ci;
assign co = a & b | b & ci | a & ci;
endmodule
| 7.552698 |
module add_onescomp #(
parameter WIDTH = 16
) (
input [WIDTH-1:0] A,
input [WIDTH-1:0] B,
output [WIDTH-1:0] SUM
);
wire [WIDTH:0] SUM_INT = {1'b0, A} + {1'b0, B};
assign SUM = SUM_INT[WIDTH-1:0] + {{WIDTH - 1{1'b0}}, SUM_INT[WIDTH]};
endmodule
| 7.334453 |
module for the add_one module.
*
* This module contains the followng items:
* - A foreign module definition for use in instantiatin the type_wrapper module
* which contains the BEH module instance.
* - An instance of the type_wrapper foreign module.
* - alwyas blocks each type_wrapper output.
*
****************************************************************************/
`timescale 1 ps / 1 ps
module add_one_vlwrapper(
clk,
rst,
add_one_x_busy,
add_one_x_vld,
add_one_x_data,
add_one_return_busy,
add_one_return_vld,
add_one_return_data
);
input clk;
input rst;
output add_one_x_busy;
reg add_one_x_busy;
wire m_add_one_x_busy;
input add_one_x_vld;
input [31:0] add_one_x_data;
input add_one_return_busy;
output add_one_return_vld;
reg add_one_return_vld;
wire m_add_one_return_vld;
output [31:0] add_one_return_data;
reg[31:0] add_one_return_data;
wire [31:0] m_add_one_return_data;
// Instantiate the Verilog module that instantiates the SystemC module
add_one_type_wrapper add_one_sc(
.clk(clk),
.rst(rst),
.add_one_x_busy(m_add_one_x_busy),
.add_one_x_vld(add_one_x_vld),
.add_one_x_data(add_one_x_data),
.add_one_return_busy(add_one_return_busy),
.add_one_return_vld(m_add_one_return_vld),
.add_one_return_data(m_add_one_return_data)
);
// Always blocks for non-blocking assignments of type_wrapper outputs to
// Verilog Verificatoin wrapper outputs.
always @(m_add_one_x_busy)
begin
add_one_x_busy <= m_add_one_x_busy;
end
always @(m_add_one_return_vld)
begin
add_one_return_vld <= m_add_one_return_vld;
end
always @(m_add_one_return_data)
begin
add_one_return_data <= m_add_one_return_data;
end
endmodule
| 6.677536 |
module add_op (
A,
B,
ctrl,
prop,
gen,
sum
);
input [31:0] A, B;
input ctrl;
output [31:0] prop, gen, sum;
// TODO here -> Let me go make some intermediary things uwu
// Okay we back after making our block/full adder
wire [3:0] block_carry, block_gen, block_prop;
assign block_carry[0] = ctrl;
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin
add_block_8 add1 (
.A(A[i*8+7:i*8]),
.B(B[i*8+7:i*8]),
.ctrl(block_carry[i]),
.sum(sum[i*8+7:i*8]),
.prop(block_prop[i]),
.gen(block_gen[i]),
.prop0(prop[i*8+7:i*8]),
.gen0(gen[i*8+7:i*8])
);
end
endgenerate
// It's Britney b***h
// all eyes on us
wire w1;
and and1 (w1, block_prop[0], block_carry[0]);
or or1 (block_carry[1], w1, block_gen[0]);
// scream and shout
wire w2, w3;
and and2 (w2, block_prop[1], block_prop[0], block_carry[0]);
and and3 (w3, block_prop[1], block_gen[0]);
or or2 (block_carry[2], block_gen[1], w2, w3);
// turn the sh*t up
wire w4, w5, w6;
and and4 (w4, block_prop[2], block_prop[1], block_prop[0], block_carry[0]);
and and5 (w5, block_prop[2], block_prop[1], block_gen[0]);
and and6 (w6, block_prop[2], block_gen[1]);
or or3 (block_carry[3], block_gen[2], w4, w5, w6);
endmodule
| 6.916946 |
module add_block_8 (
A,
B,
ctrl,
prop0,
gen0,
prop,
gen,
sum
);
input [7:0] A, B;
input ctrl;
output [7:0] prop0, gen0, sum;
output prop, gen;
wire [7:0] carry;
assign carry[0] = ctrl;
// genvar time uwu
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin
full_adder add1 (
.A(A[i]),
.B(B[i]),
.Cin(carry[i]),
.prop(prop0[i]),
.gen(gen0[i]),
.S(sum[i])
);
end
endgenerate
// time to do the rest of the carry's
// I am cool -> Hyuna is a queen period ><
// carry 1 ;)
wire w1;
and and1 (w1, prop0[0], carry[0]);
or or1 (carry[1], w1, gen0[0]);
// carry 2 ;))
wire w2, w3;
and and2 (w2, prop0[0], prop0[1], carry[0]);
and and3 (w3, prop0[1], gen0[0]);
or or2 (carry[2], gen0[1], w2, w3);
// carry 3 ;)))
wire w4, w5, w6;
and and4 (w4, carry[0], prop0[0], prop0[1], prop0[2]);
and and5 (w5, prop0[2], prop0[1], gen0[0]);
and and6 (w6, prop0[2], gen0[1]);
or or3 (carry[3], w4, w5, w6, gen0[2]);
// carry 4 ;))))
wire w7, w8, w9, w10;
and and7 (w7, prop0[3], prop0[2], prop0[1], prop0[0], carry[0]);
and and8 (w8, prop0[3], prop0[2], prop0[1], gen0[0]);
and and9 (w9, prop0[3], prop0[2], gen0[1]);
and and10 (w10, prop0[3], gen0[2]);
or or4 (carry[4], gen0[3], w7, w8, w9, w10);
// carry 5 ;)))))
wire w11, w12, w13, w14, w15;
and and11 (w11, prop0[4], prop0[3], prop0[2], prop0[1], prop0[0], carry[0]);
and and12 (w12, prop0[4], prop0[3], prop0[2], prop0[1], gen0[0]);
and and13 (w13, prop0[4], prop0[3], prop0[2], gen0[1]);
and and14 (w14, prop0[4], prop0[3], gen0[2]);
and and15 (w15, prop0[4], gen0[3]);
or or5 (carry[5], w11, w12, w13, w14, w15, gen0[4]);
// carry 6 ;))))))
wire w16, w17, w18, w19, w20, w21;
and and16 (w16, prop0[5], prop0[4], prop0[3], prop0[2], prop0[1], prop0[0], carry[0]);
and and17 (w17, prop0[5], prop0[4], prop0[3], prop0[2], prop0[1], gen0[0]);
and and18 (w18, prop0[5], prop0[4], prop0[3], prop0[2], gen0[1]);
and and19 (w19, prop0[5], prop0[4], prop0[3], gen0[2]);
and and20 (w20, prop0[5], prop0[4], gen0[3]);
and and21 (w21, prop0[5], gen0[4]);
or or6 (carry[6], w16, w17, w18, w19, w20, w21, gen0[5]);
// carry 7 ;)))))))
wire w22, w23, w24, w25, w26, w27, w28;
and and22 (w22, prop0[6], prop0[5], prop0[4], prop0[3], prop0[2], prop0[1], prop0[0], carry[0]);
and and23 (w23, prop0[6], prop0[5], prop0[4], prop0[3], prop0[2], prop0[1], gen0[0]);
and and24 (w24, prop0[6], prop0[5], prop0[4], prop0[3], prop0[2], gen0[1]);
and and25 (w25, prop0[6], prop0[5], prop0[4], prop0[3], gen0[2]);
and and26 (w26, prop0[6], prop0[5], prop0[4], gen0[3]);
and and27 (w27, prop0[6], prop0[5], gen0[4]);
and and28 (w28, prop0[6], gen0[5]);
or or7 (carry[7], w22, w23, w24, w25, w26, w27, w28, gen0[6]);
// carry complete ><
// Block time -> Still in love with J-U-D-A-S
and and29 (prop, prop0[7], prop0[6], prop0[5], prop0[4], prop0[3], prop0[2], prop0[1], prop0[0]);
wire w29, w30, w31, w32, w33, w34, w35;
and and30 (w29, prop0[7], prop0[6], prop0[5], prop0[4], prop0[3], prop0[2], prop0[1], gen0[0]);
and and31 (w30, prop0[7], prop0[6], prop0[5], prop0[4], prop0[3], prop0[2], gen0[1]);
and and32 (w31, prop0[7], prop0[6], prop0[5], prop0[4], prop0[3], gen0[2]);
and and33 (w32, prop0[7], prop0[6], prop0[5], prop0[4], gen0[3]);
and and34 (w33, prop0[7], prop0[6], prop0[5], gen0[4]);
and and35 (w34, prop0[7], prop0[6], gen0[5]);
and and36 (w35, prop0[7], gen0[6]);
or or8 (gen, gen0[7], w29, w30, w31, w32, w33, w34, w35);
endmodule
| 6.830493 |
module Add_PC (
entrada_PC,
saida_addPC
);
input [31:0] entrada_PC;
output wire [31:0] saida_addPC;
assign saida_addPC = entrada_PC + 1;
endmodule
| 6.883197 |
module ADD_PC_4 (
in_pc,
out_pc
);
input [`WIDTH_PC-1:0] in_pc;
output [`WIDTH_PC-1:0] out_pc;
assign out_pc = in_pc + 32'd4;
endmodule
| 7.464804 |
module add_preamble (
input wire clk,
input wire [7:0] data_in,
input wire data_valid_in,
input wire data_enable_in,
output reg [7:0] data_out = 8'b0,
output reg data_valid_out = 1'b0,
output reg data_enable_out = 1'b0
);
reg [63:0] delay_data = 64'b0;
reg [ 7:0] delay_data_valid = 8'b0;
always @(posedge clk) begin
data_enable_out <= 1'b0;
if (data_enable_in == 1'b1) begin
data_enable_out <= 1'b1;
if (delay_data_valid[7] == 1'b1) begin
// passing through data
data_out <= delay_data[63:56];
data_valid_out <= 1'b1;
end
else if (delay_data_valid[6] == 1'b1)
// SFD
begin
data_out <= 8'b11010101;
data_valid_out <= 1'b1;
end else if (data_valid_in == 1'b1) begin
// preamble nibbles
data_out <= 8'b01010101;
data_valid_out <= 1'b1;
end else begin
data_out <= 8'b00000000;
data_valid_out <= 1'b0;
end
// move the data through the delay line
delay_data <= {delay_data[55:0], data_in};
delay_data_valid <= {delay_data_valid[7:0], data_valid_in};
end
end
endmodule
| 6.743079 |
module add_rca #(
parameter Bits = 64
) (
input clk,
input reset,
input [Bits-1:0] a,
input [Bits-1:0] b,
output [Bits-1:0] sum,
output reg carry
);
reg [Bits:0] c;
assign c[0] = 1'b0;
genvar i;
generate
for (i = 0; i < Bits; i = i + 1) begin
full_adder fa (
.a(a[i]),
.b(b[i]),
.cin(c[i]),
.cout(c[i+1]),
.sum(sum[i])
);
end
endgenerate
always @(*) begin
carry = c[Bits];
end
/*verilator lint_on UNOPTFLAT*/
/*verilator lint_on UNUSED*/
endmodule
| 7.27429 |
module add_rca_tb (
input [64-1:0] a,
input [64-1:0] b,
output [64-1:0] sum,
output reg carry
);
add_rca #(
.Bits(64)
) f (
.a(a),
.b(b),
.sum(sum),
.carry(carry)
);
endmodule
| 8.54899 |
module add_rca_2_bit (
X,
Y,
ci,
sum,
co
);
input wire [1:0] X, Y;
input wire ci;
output wire [1:0] sum;
output wire co;
wire co_int_1;
full_adder adder_1 (
.X (X[0]),
.Y (Y[0]),
.ci (ci),
.sum(sum[0]),
.co (co_int_1)
);
full_adder adder_2 (
.X (X[1]),
.Y (Y[1]),
.ci (co_int_1),
.sum(sum[1]),
.co (co)
);
endmodule
| 7.026416 |
module add_rca_2_bit_test;
// Inputs
reg [1:0] X;
reg [1:0] Y;
reg ci;
// Outputs
wire [1:0] sum;
wire co;
// Instantiate the Unit Under Test (UUT)
add_rca_2_bit uut (
.X (X),
.Y (Y),
.ci (ci),
.sum(sum),
.co (co)
);
integer i, j, k;
integer error = 0;
initial begin
// Initialize Inputs
X = 0;
Y = 0;
ci = 0;
for (k = 0; k < 2; k = k + 1) begin
for (i = 0; i < 4; i = i + 1) begin
for (j = 0; j < 4; j = j + 1) begin
X = i;
Y = j;
ci = k;
#10;
end
end
end
if (error > 0) begin
$display("TEST FAILURE!!! TEST FAILED with %d ERRORS", error);
end else begin
$display("!!! TEST SUCCESS !!!");
end
$finish;
end
always @(X, Y, ci) begin
#1;
if (X + Y + ci !== sum + co * 4) begin
$display("ERROR: X = %b, Y = %b, ci = %b, sum = %b, co = %b", X, Y, ci, sum, co);
error = error + 1;
end
end
endmodule
| 7.026416 |
module Add_rca_32 (
sum,
c_out,
a,
b,
c_in
);
output signed [31:0] sum;
output c_out;
input signed [31:0] a, b;
input c_in;
wire c_in_0_15, c_out;
Add_rca_16_0_delay M1 (
sum[15:0],
c_in_0_15,
a[15:0],
b[15:0],
c_in
);
Add_rca_16_0_delay M2 (
sum[31:16],
c_out,
a[31:16],
b[31:16],
c_in_0_15
);
endmodule
| 6.933489 |
module add_rca_32_bit (
X,
Y,
ci,
sum,
co
);
input wire [31:0] X, Y;
input wire ci;
output wire [31:0] sum;
output wire co;
wire co_int_1, co_int_2, co_int_3;
add_rca_8_bit adder_1 (
.X (X[7:0]),
.Y (Y[7:0]),
.ci (ci),
.sum(sum[7:0]),
.co (co_int_1)
);
add_rca_8_bit adder_2 (
.X (X[15:8]),
.Y (Y[15:8]),
.ci (co_int_1),
.sum(sum[15:8]),
.co (co_int_2)
);
add_rca_8_bit adder_3 (
.X (X[23:16]),
.Y (Y[23:16]),
.ci (co_int_2),
.sum(sum[23:16]),
.co (co_int_3)
);
add_rca_8_bit adder_4 (
.X (X[31:24]),
.Y (Y[31:24]),
.ci (co_int_3),
.sum(sum[31:24]),
.co (co)
);
endmodule
| 8.593074 |
module add_rca_32_bit_test;
// Inputs
reg [31:0] X;
reg [31:0] Y;
reg ci;
// Outputs
wire co;
wire [31:0] sum;
// Instantiate the Unit Under Test (UUT)
add_rca_32_bit uut (
.X (X),
.Y (Y),
.ci (ci),
.sum(sum),
.co (co)
);
integer i, j, k, r;
integer error = 0;
initial begin
// Initialize Inputs
X = 0;
Y = 0;
ci = 0;
for (k = 0; k < 2; k = k + 1) begin
ci = k;
for (i = 0; i < 16; i = i + 1) begin
r = $random;
X = r;
for (j = 0; j < 16; j = j + 1) begin
r = $random;
Y = r;
#10;
end
end
end
if (error > 0) begin
$display("TEST FAILURE!!! TEST FAILED with %d ERRORS", error);
end else begin
$display("!!! TEST SUCCESS !!!");
end
$finish;
end
;
always @(X, Y, ci) begin
#1;
if (X + Y + ci !== sum + (co << 32)) begin
$display("ERROR: X = %b, Y = %b, ci = %b, sum = %b, co = %b", X, Y, ci, sum, co);
error = error + 1;
end
end
endmodule
| 8.593074 |
module add_rca_8_bit (
X,
Y,
ci,
sum,
co
);
input wire [7:0] X, Y;
input wire ci;
output wire [7:0] sum;
output wire co;
wire co_int_1, co_int_2, co_int_3;
add_rca_2_bit adder_1 (
.X (X[1:0]),
.Y (Y[1:0]),
.ci (ci),
.sum(sum[1:0]),
.co (co_int_1)
);
add_rca_2_bit adder_2 (
.X (X[3:2]),
.Y (Y[3:2]),
.ci (co_int_1),
.sum(sum[3:2]),
.co (co_int_2)
);
add_rca_2_bit adder_3 (
.X (X[5:4]),
.Y (Y[5:4]),
.ci (co_int_2),
.sum(sum[5:4]),
.co (co_int_3)
);
add_rca_2_bit adder_4 (
.X (X[7:6]),
.Y (Y[7:6]),
.ci (co_int_3),
.sum(sum[7:6]),
.co (co)
);
endmodule
| 6.517539 |
module add_rca_8_bit_test;
// Inputs
reg [7:0] X;
reg [7:0] Y;
reg ci;
// Outputs
wire [7:0] sum;
wire co;
// Instantiate the Unit Under Test (UUT)
add_rca_8_bit uut (
.X (X),
.Y (Y),
.ci (ci),
.sum(sum),
.co (co)
);
integer i, j, k, r;
integer error = 0;
initial begin
// Initialize Inputs
X = 0;
Y = 0;
ci = 0;
for (k = 0; k < 2; k = k + 1) begin
for (i = 0; i < 256; i = i + 1) begin
for (j = 0; j < 256; j = j + 1) begin
r = $random % 256;
if (r === 0) begin
X = i;
Y = j;
ci = k;
#10;
end
end
end
end
if (error > 0) begin
$display("TEST FAILURE!!! TEST FAILED with %d ERRORS", error);
end else begin
$display("!!! TEST SUCCESS !!!");
end
$finish;
end
always @(X, Y, ci) begin
#1;
if (X + Y + ci !== sum + co * 256) begin
$display("ERROR: X = %b, Y = %b, ci = %b, sum = %b, co = %b", X, Y, ci, sum, co);
error = error + 1;
end
end
endmodule
| 6.517539 |
module add_rca_signed #(
parameter Bits = 64
) (
input clk,
input reset,
input [Bits-1:0] a,
input [Bits-1:0] b,
output [Bits-1:0] sum,
output reg carry
);
reg [Bits:0] c;
assign c[0] = 1'b0;
genvar i;
generate
for (i = 0; i < Bits; i = i + 1) begin
full_adder fa (
.a(a[i]),
.b(b[i]),
.cin(c[i]),
.cout(c[i+1]),
.sum(sum[i])
);
end
endgenerate
always @(*) begin
carry = a[Bits-1] != b[Bits-1] ? 0 : b[Bits-1] == sum[Bits-1] ? 0 : 1;
end
/*verilator lint_on UNOPTFLAT*/
/*verilator lint_on UNUSED*/
endmodule
| 7.273513 |
module add_reg (
clk,
addin,
addresult,
rst_n
);
input clk;
input rst_n;
input [11:0] addin;
output [19:0] addresult;
reg [19:0] addresult;
always @(negedge rst_n or posedge clk) begin
if (rst_n == 1'b0) begin
addresult <= 0;
end else begin
addresult <= addresult + addin;
end
end
endmodule
| 6.571512 |
module add_rm_hdr #(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH / 8,
parameter STAGE_NUMBER = 'hff,
parameter PORT_NUMBER = 0
) (
input [DATA_WIDTH-1:0] rx_in_data,
input [CTRL_WIDTH-1:0] rx_in_ctrl,
input rx_in_wr,
output rx_in_rdy,
output [DATA_WIDTH-1:0] rx_out_data,
output [CTRL_WIDTH-1:0] rx_out_ctrl,
output rx_out_wr,
input rx_out_rdy,
input [DATA_WIDTH-1:0] tx_in_data,
input [CTRL_WIDTH-1:0] tx_in_ctrl,
input tx_in_wr,
output tx_in_rdy,
output [DATA_WIDTH-1:0] tx_out_data,
output [CTRL_WIDTH-1:0] tx_out_ctrl,
output tx_out_wr,
input tx_out_rdy,
// --- Misc
input reset,
input clk
);
add_hdr #(
.DATA_WIDTH (DATA_WIDTH),
.CTRL_WIDTH (CTRL_WIDTH),
.STAGE_NUMBER(STAGE_NUMBER),
.PORT_NUMBER (PORT_NUMBER)
) add_hdr (
.in_data(rx_in_data),
.in_ctrl(rx_in_ctrl),
.in_wr (rx_in_wr),
.in_rdy (rx_in_rdy),
.out_data(rx_out_data),
.out_ctrl(rx_out_ctrl),
.out_wr (rx_out_wr),
.out_rdy (rx_out_rdy),
// --- Misc
.reset(reset),
.clk (clk)
);
rm_hdr #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH)
) rm_hdr (
.in_data(tx_in_data),
.in_ctrl(tx_in_ctrl),
.in_wr (tx_in_wr),
.in_rdy (tx_in_rdy),
.out_data(tx_out_data),
.out_ctrl(tx_out_ctrl),
.out_wr (tx_out_wr),
.out_rdy (tx_out_rdy),
// --- Misc
.reset(reset),
.clk (clk)
);
endmodule
| 7.764609 |
module add_rom (
input [4:0] addr,
input [3:0] imm4,
output reg [7:0] label
);
always @(*)
case (addr)
0: label = "A";
1: label = "D";
2: label = "D";
4: label = imm4[3];
5: label = imm4[2];
6: label = imm4[1];
7: label = imm4[0];
default: label = " ";
endcase
endmodule
| 6.575915 |
module Add_Round (
clk,
rst,
read_address,
read_data,
write_address,
write_data,
write_en,
done,
buffer40_en,
buffer40_data,
buffer64_en,
buffer
);
input clk, rst;
output reg [8:0] read_address;
input [63:0] read_data;
output reg [8:0] write_address;
output [63:0] write_data;
output write_en;
output done;
output reg buffer40_en;
output [39:0] buffer40_data;
output reg buffer64_en;
input [319:0] buffer;
wire [12:0] add0 = read_data[12:0] + `h1;
wire [12:0] add1 = read_data[28:16] + `h1;
wire [12:0] add2 = read_data[44:32] + `h1;
wire [12:0] add3 = read_data[60:48] + `h1;
assign buffer40_data = {add3[12:3], add2[12:3], add1[12:3], add0[12:3]};
reg inc_write_address, inc_read_address;
// this was moved to shared buffer
//reg [319:0] buffer;
/*always @(posedge clk)
begin
if(buffer40_en)
buffer <= {round_p_value, buffer[319:40]};
else if(buffer64_en)
buffer <= {64'd0, buffer[319:64]};
end*/
assign write_data = buffer[63:0];
assign write_en = inc_write_address;
always @(posedge clk or posedge rst) begin
if (rst) read_address <= 9'd0;
else if (inc_read_address) read_address <= read_address + 1'b1;
end
wire read_address_192 = (read_address == 9'd192);
always @(posedge clk or posedge rst) begin
if (rst) write_address <= 9'd0;
else if (inc_write_address) write_address <= write_address + 1'b1;
end
reg [4:0] state, nextstate;
always @(posedge clk or posedge rst) begin
if (rst) state <= 5'd0;
else state <= nextstate;
end
always @(*) begin
case (state)
5'd0: begin
inc_read_address = 0;
buffer40_en = 0;
buffer64_en = 0;
inc_write_address = 0;
end
// Read four 13 bit coeff, add h1, round modp, write 40 bit in buffer; fill buffer
5'd1: begin
inc_read_address = 1;
buffer40_en = 0;
buffer64_en = 0;
inc_write_address = 0;
end
5'd2: begin
inc_read_address = 1;
buffer40_en = 1;
buffer64_en = 0;
inc_write_address = 0;
end
5'd3: begin
inc_read_address = 1;
buffer40_en = 1;
buffer64_en = 0;
inc_write_address = 0;
end
5'd4: begin
inc_read_address = 1;
buffer40_en = 1;
buffer64_en = 0;
inc_write_address = 0;
end
5'd5: begin
inc_read_address = 1;
buffer40_en = 1;
buffer64_en = 0;
inc_write_address = 0;
end
5'd6: begin
inc_read_address = 1;
buffer40_en = 1;
buffer64_en = 0;
inc_write_address = 0;
end
5'd7: begin
inc_read_address = 1;
buffer40_en = 1;
buffer64_en = 0;
inc_write_address = 0;
end
5'd8: begin
inc_read_address = 1;
buffer40_en = 1;
buffer64_en = 0;
inc_write_address = 0;
end
5'd9: begin
inc_read_address = 0;
buffer40_en = 1;
buffer64_en = 0;
inc_write_address = 0;
end
// Read 64 bit chunks from buffer and rwite 5 words
5'd10: begin
inc_read_address = 0;
buffer40_en = 0;
buffer64_en = 1;
inc_write_address = 1;
end
5'd11: begin
inc_read_address = 0;
buffer40_en = 0;
buffer64_en = 1;
inc_write_address = 1;
end
5'd12: begin
inc_read_address = 0;
buffer40_en = 0;
buffer64_en = 1;
inc_write_address = 1;
end
5'd13: begin
inc_read_address = 0;
buffer40_en = 0;
buffer64_en = 1;
inc_write_address = 1;
end
5'd14: begin
inc_read_address = 0;
buffer40_en = 0;
buffer64_en = 1;
inc_write_address = 1;
end
5'd15: begin
inc_read_address = 0;
buffer40_en = 0;
buffer64_en = 0;
inc_write_address = 0;
end
default: begin
inc_read_address = 0;
buffer40_en = 0;
buffer64_en = 0;
inc_write_address = 0;
end
endcase
end
always @(*) begin
case (state)
5'd0: nextstate = 5'd1;
5'd1: nextstate = 5'd2;
5'd2: nextstate = 5'd3;
5'd3: nextstate = 5'd4;
5'd4: nextstate = 5'd5;
5'd5: nextstate = 5'd6;
5'd6: nextstate = 5'd7;
5'd7: nextstate = 5'd8;
5'd8: nextstate = 5'd9;
5'd9: nextstate = 5'd10;
5'd10: nextstate = 5'd11;
5'd11: nextstate = 5'd12;
5'd12: nextstate = 5'd13;
5'd13: nextstate = 5'd14;
5'd14: begin
if (read_address_192) nextstate = 5'd15;
else nextstate = 5'd1;
end
5'd15: nextstate = 5'd15;
default: nextstate = 5'd0;
endcase
end
assign done = (state == 5'd15);
endmodule
| 8.096778 |
module add_round_key (
output wire [7:0] out,
input wire [7:0] in1,
in2
);
assign out = in1 ^ in2;
endmodule
| 6.601743 |
module add_round_keys (
input wire [127 : 0] state,
input wire [127 : 0] subkey,
// output reg[127 : 0] out
output [127 : 0] out
);
//always @*
// begin
assign out = state ^ subkey;
// end
endmodule
| 6.601743 |
module ADD_ROUND_KEY_state (
clk,
rst,
data_in,
addr_in,
sel,
out_REG
);
input wire clk, rst;
input wire [7:0] data_in;
input wire [3:0] addr_in;
input wire [3:0] sel;
output wire [7:0] out_REG;
wire [7:0] out;
reg [7:0] out_mux;
wire [7:0] out_round0,out_round1,out_round2,out_round3,out_round4,out_round5,
out_round6,out_round7,out_round8,out_round9,out_round10,out_round10_reg;
always @(*) begin
case (sel)
0: out_mux = out_round0;
1: out_mux = out_round1;
2: out_mux = out_round2;
3: out_mux = out_round3;
4: out_mux = out_round4;
5: out_mux = out_round5;
6: out_mux = out_round6;
7: out_mux = out_round7;
8: out_mux = out_round8;
9: out_mux = out_round9;
10: out_mux = out_round10_reg;
default: out_mux = 0;
endcase
end
round_rom #(
.FILENAME("Round_Keys/Cipher_key.txt")
) round_0 (
clk,
addr_in,
out_round0
);
round_rom #(
.FILENAME("Round_Keys/round1_key.txt")
) round_1 (
clk,
addr_in,
out_round1
);
round_rom #(
.FILENAME("Round_Keys/round2_key.txt")
) round_2 (
clk,
addr_in,
out_round2
);
round_rom #(
.FILENAME("Round_Keys/round3_key.txt")
) round_3 (
clk,
addr_in,
out_round3
);
round_rom #(
.FILENAME("Round_Keys/round4_key.txt")
) round_4 (
clk,
addr_in,
out_round4
);
round_rom #(
.FILENAME("Round_Keys/round5_key.txt")
) round_5 (
clk,
addr_in,
out_round5
);
round_rom #(
.FILENAME("Round_Keys/round6_key.txt")
) round_6 (
clk,
addr_in,
out_round6
);
round_rom #(
.FILENAME("Round_Keys/round7_key.txt")
) round_7 (
clk,
addr_in,
out_round7
);
round_rom #(
.FILENAME("Round_Keys/round8_key.txt")
) round_8 (
clk,
addr_in,
out_round8
);
round_rom #(
.FILENAME("Round_Keys/round9_key.txt")
) round_9 (
clk,
addr_in,
out_round9
);
round_rom #(
.FILENAME("Round_Keys/round10_key.txt")
) round_10 (
clk,
addr_in,
out_round10
);
Register #(
.size(8)
) Register1 (
clk,
rst,
out_round10,
out_round10_reg
);
assign out_REG = out_mux ^ data_in;
//Register #(.size(8))Register_mem3(clk,rst,out,out_REG);
endmodule
| 7.259458 |
module add_round_key_tb;
reg [127:0] roundKey;
reg [127:0] inputData;
reg [127:0] expectedValue;
wire [127:0] outputData;
add_round_key dut (
.inputData (inputData),
.roundKey (roundKey),
.outputData(outputData)
);
initial begin
expectedValue = 128'h1a3174470b1b226e59084e3c540e1f00;
end
always @(*) begin
roundKey = 128'h754620676e754b20796d207374616854;
inputData = 128'h6f775420656e694e20656e4f206f7754;
if (outputData != expectedValue) begin
$display("Fail \n \n", "For the following inputs: \n", "Input Key: %h \n", roundKey,
"Input Value: %h \n \n", inputData, "Expected output: \n", "Output Value: %h \n \n",
expectedValue, "Aquired output: \n", "Output Value: %h \n", outputData);
end
if (outputData == expectedValue) begin
$display("Pass \n \n", "For the following inputs: \n", "Input Key: %h \n", roundKey,
"Input Value: %h \n \n", inputData, "Aquired output: \n", "Output Value: %h \n \n",
outputData);
end
end
endmodule
| 6.601743 |
module add_tound_ket_tb;
reg startTransition;
reg clock50MHz;
reg [127:0] roundKey;
reg [127:0] inputData;
wire [127:0] outputData;
add_round_key dut (
.inputData(inputData),
.roundKey(roundKey),
.startTransition(startTransition),
.outputData(outputData)
);
localparam NUM_CYCLES = 20000;
localparam CLOCK_FREQ = 50000000;
real HALF_CLOCK_PERIOD = (1000000000.0 / $itor(CLOCK_FREQ)) / 2.0;
integer half_cycle = 0;
initial begin
roundKey = 128'h754620676e754b20796d207374616854;
inputData = 128'h6f775420656e694e20656e4f206f7754;
startTransition = 0;
clock50MHz = 0;
end
initial begin
repeat (500) @(posedge clock50MHz);
startTransition = 1;
end
always begin
#(HALF_CLOCK_PERIOD);
clock50MHz = ~clock50MHz;
half_cycle = half_cycle + 1;
if (half_cycle == (2 * NUM_CYCLES)) begin
$stop;
end
end
endmodule
| 6.950945 |
module add_share (
input a,
b,
x,
y,
sel,
en,
clk,
output reg out1,
out2
);
wire tmp1, tmp2;
assign tmp1 = a * b; // tmp1Ҫһ˷
assign tmp2 = x * y; // tmp2Ҫһ˷
always @(posedge clk)
if (en) begin
out1 <= sel ? tmp1 : tmp2; //tmp1tmp2ͬʱЧ
end else begin
out2 <= sel ? tmp1 : tmp2; //tmp1tmp2ͬʱЧ
end
endmodule
| 6.650665 |
module add_share1 #(
parameter N = 8
) (
input [N-1:0] a,
b,
x,
y,
input sel,
en,
clk,
output reg [N-1:0] out1,
out2
);
wire [N-1:0] tmp1, tmp2;
assign tmp1 = a * b; // tmp1Ҫһ˷
assign tmp2 = x * y; // tmp2Ҫһ˷
always @(posedge clk)
if (en) begin
out1 <= sel ? tmp1 : tmp2; //tmp1tmp2ͬʱЧ
end else begin
out2 <= sel ? tmp1 : tmp2; //tmp1tmp2ͬʱЧ
end
endmodule
| 7.485426 |
module add_share2 #(
parameter N = 8
) (
input [N-1:0] a,
b,
x,
y,
input sel,
en,
clk,
output reg [N-1:0] out1
);
wire [N-1:0] tmp1, tmp2;
assign tmp1 = sel ? a : x; // ˷A
assign tmp2 = sel ? b : y; // ˷B
always @(posedge clk)
if (en) begin
out1 = tmp1 * tmp2; // ˷
end
endmodule
| 7.755956 |
module add_share3 #(
parameter N = 8
) (
input [N-1:0] a,
b,
x,
y,
input sel,
en,
clk,
output reg [N-1:0] out1
);
wire [N-1:0] tmp1, tmp2;
assign tmp1 = a * b; // tmp1Ҫһ˷
assign tmp2 = x * y; // tmp2Ҫһ˷
always @(posedge clk)
if (en) begin
out1 <= sel ? tmp1 : tmp2;
end
endmodule
| 7.642123 |
module add_sub1 (
a,
b,
cin,
s,
cout
);
input a, b, cin;
output s, cout;
wire xorab, andab, andxorcab;
xor g1 (xorab, a, b);
xor g2 (s, xorab, cin);
and g3 (andab, a, b);
and g4 (andxorcab, cin, xorab);
or g5 (cout, andxorcab, andab);
endmodule
| 7.135565 |
module add_sub (
a,
b,
cin,
sum,
cout
);
input [3:0] a;
input [3:0] b;
input cin;
output [1:0] sum;
output cout;
wire carry;
add_sub1 g5 (
a[0],
b[0],
cin,
sum[0],
carry
);
add_sub1 g6 (
a[1],
b[1],
carry,
sum[1],
cout
);
endmodule
| 7.314322 |
module add_sub (
a,
b,
c0,
s,
ovf
);
input [3:0] a, b;
input c0;
output [3:0] s;
output ovf; //overflow
//4 full adders used to make four bit adder.
//carry of each full adder is passed as input to the next full adder
wire c, c1, c2, c3;
//modified 4 bit adder. b[i]^c0 instead of b[i] is used.
full_adder F1 (
a[0],
b[0] ^ c0,
c0,
s[0],
c1
);
full_adder F2 (
a[1],
b[1] ^ c0,
c1,
s[1],
c2
);
full_adder F3 (
a[2],
b[2] ^ c0,
c2,
s[2],
c3
);
full_adder F4 (
a[3],
b[3] ^ c0,
c3,
s[3],
c
);
assign ovf = c ^ s[3]; //calculation of overflow
endmodule
| 7.314322 |
module add_sub27 (
add,
opa,
opb,
sum,
co
);
input add;
input [26:0] opa, opb;
output [26:0] sum;
output co;
assign {co, sum} = add ? ({1'b0, opa} + {1'b0, opb}) : ({1'b0, opa} - {1'b0, opb});
endmodule
| 6.628721 |
module adder (
enable,
a0,
a1,
cout
);
input enable;
input [15:0] a0, a1;
output [15:0] cout;
wire c, d, e, f, g, h, i, j, k, l, m, n, o, p, q, r;
wire input0,input1, input2, input3, input4, input5, input6, input7, input8, input9, input10,input11, input12, input13, input14, input15;
xor (input0, enable, a1[0]);
xor (input1, enable, a1[1]);
xor (input2, enable, a1[2]);
xor (input3, enable, a1[3]);
xor (input4, enable, a1[4]);
xor (input5, enable, a1[5]);
xor (input6, enable, a1[6]);
xor (input7, enable, a1[7]);
xor (input8, enable, a1[8]);
xor (input9, enable, a1[9]);
xor (input10, enable, a1[10]);
xor (input11, enable, a1[11]);
xor (input12, enable, a1[12]);
xor (input13, enable, a1[13]);
xor (input14, enable, a1[14]);
xor (input15, enable, a1[15]);
//a0,a1,carry_in,s,carry_out
fullAdder_neww fa0 (
a0[0],
input0,
enable,
cout[0],
c
);
fullAdder_neww fa1 (
a0[1],
input1,
c,
cout[1],
d
);
fullAdder_neww fa2 (
a0[2],
input2,
d,
cout[2],
e
);
fullAdder_neww fa3 (
a0[3],
input3,
e,
cout[3],
f
);
fullAdder_neww fa4 (
a0[4],
input4,
f,
cout[4],
g
);
fullAdder_neww fa5 (
a0[5],
input5,
g,
cout[5],
h
);
fullAdder_neww fa6 (
a0[6],
input6,
h,
cout[6],
i
);
fullAdder_neww fa7 (
a0[7],
input7,
i,
cout[7],
j
);
fullAdder_neww fa8 (
a0[8],
input8,
j,
cout[8],
k
);
fullAdder_neww fa9 (
a0[9],
input9,
k,
cout[9],
l
);
fullAdder_neww fa10 (
a0[10],
input10,
l,
cout[10],
m
);
fullAdder_neww fa11 (
a0[11],
input11,
m,
cout[11],
n
);
fullAdder_neww fa12 (
a0[12],
input12,
n,
cout[12],
o
);
fullAdder_neww fa13 (
a0[13],
input13,
o,
cout[13],
p
);
fullAdder_neww fa14 (
a0[14],
input14,
p,
cout[14],
q
);
fullAdder_neww fa15 (
a0[15],
input15,
q,
cout[15],
r
);
endmodule
| 6.560729 |
module top_module (
input [31:0] a,
input [31:0] b,
input sub,
output [31:0] sum
);
wire [31:0] xor_b = b ^ {32{sub}};
wire lcout;
wire [15:0] lsum;
wire [15:0] hsum;
add16 ladd16 (
.a(a[15:0]),
.b(xor_b[15:0]),
.cin(sub),
.cout(lcout),
.sum(lsum)
);
add16 hadd16 (
.a (a[31:16]),
.b (xor_b[31:16]),
.cin(lcout),
.sum(hsum)
);
assign sum = {hsum, lsum};
endmodule
| 7.203305 |
module Add_Subt #(
parameter SWR = 26
) (
input wire clk,
input wire rst,
input wire load_i, //Reg load input
input wire Add_Sub_op_i,
input wire [SWR-1:0] Data_A_i,
input wire [SWR-1:0] PreData_B_i,
/////////////////////////////////////////////////////////////
output wire [SWR-1:0] Data_Result_o,
output wire [SWR-1:0] P_o,
output wire [SWR-1:1] Cn_o,
output wire FSM_C_o
);
wire [SWR-1:0] Data_B;
wire [SWR-1:0] S_to_D;
wire [SWR-1:0] P_to_D;
wire [SWR-1:1] C_to_D;
wire Co_to_D;
/////////////////////////////////////////7
genvar j;
for (j = 0; j < SWR; j = j + 1) begin
assign Data_B[j] = PreData_B_i[j] ^ Add_Sub_op_i;
end
Full_Adder_PG #(
.SWR(SWR)
) AS_Module (
.clk(clk),
.rst(rst),
.Op_A_i(Data_A_i),
.Op_B_i(Data_B),
.C_i(Add_Sub_op_i), //Carry in
.S_o(S_to_D), // Solution out
.Cn_o(C_to_D),
.C_o(Co_to_D), //Carry out
.P_o(P_to_D) //Propagate (for LZA)
);
RegisterAdd #(
.W(SWR)
) Add_Subt_Result (
.clk(clk),
.rst(rst),
.load(load_i),
.D(S_to_D),
.Q(Data_Result_o)
);
RegisterAdd #(
.W(SWR)
) P_Result (
.clk(clk),
.rst(rst),
.load(load_i),
.D(P_to_D),
.Q(P_o)
);
RegisterAdd #(
.W(SWR - 1)
) C_Result (
.clk(clk),
.rst(rst),
.load(load_i),
.D(C_to_D),
.Q(Cn_o)
);
RegisterAdd #(
.W(1)
) Add_overflow_Result (
.clk(clk),
.rst(rst),
.load(load_i),
.D(Co_to_D),
.Q(FSM_C_o)
);
endmodule
| 6.759045 |
module add_subtract #(
parameter N = 8
) (
input clk,
aclr,
add_sub,
input [N-1:0] A,
output reg [N-1:0] S,
output reg overflow,
carry
);
reg [N-1:0] B;
always @(posedge clk, posedge aclr)
if (aclr) B <= {N{1'b0}};
else B <= A;
always @(posedge clk, posedge aclr)
if (aclr) {carry, S} <= {(N + 1) {1'b0}};
else if (!add_sub) {carry, S} <= S + B;
else {carry, S} <= S - B;
always @(posedge clk, posedge aclr)
if (aclr) overflow = 1'b0;
else overflow = carry ^ S[N-1];
endmodule
| 6.852344 |
module ADD_SUB_2021 (
a,
b,
add_sub_signal,
exception,
res
);
input wire [31:0] a, b;
input wire add_sub_signal;
output wire exception;
output wire [31:0] res;
//----------------------------------------------------------------------------------------------------------------------------------
wire sign_a, sign_b, enable, enable_sub;
wire [7:0] exponent_a, exponent_b;
wire [31:0] significand_a, significand_b;
DECOMPOSE_AS entity_1 (
a,
b,
sign_a,
sign_b,
exponent_a,
exponent_b,
significand_a,
significand_b,
enable,
enable_sub
);
//----------------------------------------------------------------------------------------------------------------------------------
wire [7:0] ex_b_add_sub;
wire [31:0] sig_b_add_sub;
wire perform;
EQUALIZING_AS entity_2 (
exponent_a,
exponent_b,
significand_b,
ex_b_add_sub,
sig_b_add_sub,
perform
);
//----------------------------------------------------------------------------------------------------------------------------------
wire output_sign, operation;
CONVERTER_1_AS entity_3 (
add_sub_signal,
enable,
exponent_a,
exponent_b,
sign_a,
sign_b,
exception,
output_sign,
operation
);
//----------------------------------------------------------------------------------------------------------------------------------
wire [30:0] add_sum;
ADD_BLOCK entity_4 (
perform,
operation,
exponent_a,
significand_a,
sig_b_add_sub,
add_sum
);
//----------------------------------------------------------------------------------------------------------------------------------
wire [30:0] sub_diff;
SUB_BLOCK entity_5 (
enable_sub,
exponent_a,
significand_a,
sig_b_add_sub,
sub_diff
);
//----------------------------------------------------------------------------------------------------------------------------------
OUTPUT_AS entity_6 (
exception,
operation,
output_sign,
sub_diff,
add_sum,
res
);
endmodule
| 6.60829 |
module ADD_SUB_2021_TB;
reg [31:0] a, b;
reg clk = 1'b0, reset = 1'b1;
reg add_sub_signal;
wire [31:0] res;
wire exception;
ADD_SUB_2021 uut (
a,
b,
add_sub_signal,
exception,
res
);
always #5 clk = ~clk;
initial begin
add_sub_signal = 1'b0;
iteration(32'h4201_51EC, 32'h4242_147B, 32'h42A1_B333, `__LINE__); //32.33 + 48.52 = 80.85
iteration(32'h4068_51EC, 32'h4090_A3D7, 32'h4102_6666, `__LINE__); //3.63 + 4.52 = 8.15.
iteration(32'h4195_0A3D, 32'h419B_47AE, 32'h4218_28F6, `__LINE__); //18.63 + 19.41 = 38.04.
iteration(32'h4217_999A, 32'h3F8C_CCCD, 32'h421C_0000, `__LINE__); //37.9 + 1.1 = 39.
iteration(32'h4383_C7AE, 32'h4164_F5C3, 32'h438A_EF5C, `__LINE__); //263.56 + 14.31 = 277.87
iteration(32'h4542_77D7, 32'h453B_8FD7, 32'h45BF_03D7,
`__LINE__); //3111.49 + 3000.99 = 6112.48
iteration(32'h3F3A_E148, 32'h3EB33333, 32'h3F8A_3D71, `__LINE__); //0.73 + 0.35 = 1.08.
iteration(32'h3F7D_70A4, 32'h3F7D_70A4, 32'h3FFD_70A4, `__LINE__); //0.99 + 0.99 = 1.98
iteration(32'h3F40_0000, 32'h3E94_7AE1, 32'h3F85_1EB8, `__LINE__); //0.75 + 0.29 = 1.04
iteration(32'h4B7F_FFFF, 32'h3F80_0000, 32'h4B80_0000, `__LINE__); //16777215 + 1 = 16777216
// Corner Case
iteration(32'h4B7F_FFFF, 32'h4000_0000, 32'h4B80_0001, `__LINE__); //16777215 + 2 = 16777217.
// Corner Case
iteration(32'h4B7F_FFFF, 32'h4B7F_FFFF, 32'h4BFF_FFFF,
`__LINE__); //16777215 + 16777215 = 33554430
// Working
iteration(32'h4B7F_FFFE, 32'h3F80_0000, 32'h4B7F_FFFF, `__LINE__); //16777214 + 1 = 16777215
iteration(32'hBF3A_E148, 32'h3EC7_AE14, 32'hBEAE_147B, `__LINE__); //-0.73 + 0.39 = -0.34
iteration(32'hC207_C28F, 32'h4243_B852, 32'h416F_D70A, `__LINE__); //-33.94 + 48.93 = 14.99
iteration(32'hBDB2_2D0E, 32'h4305_970A, 32'h4305_80C5, `__LINE__); //-0.087 + 133.59 = 133.503
iteration(32'h4E6B_79A3, 32'hCCEB_79A3, 32'h4E4E_0A6F,
`__LINE__); //987654321 - 123456789 = 864197532
iteration(32'h4B80_0000, 32'hCB80_0000, 32'h0000_0000, `__LINE__); //16777216 - 16777216 = 0
iteration(32'h4B7F_FFFF, 32'hCB7F_FFFF, 32'h0000_0000, `__LINE__); //16777215 - 16777215 = 0
// Subtraction //
add_sub_signal = 1'b1;
iteration(32'h40A00000, 32'h40C00000, 32'hBF800000, `__LINE__); //5 - 6 = -1
iteration(32'h40C00000, 32'h40A00000, 32'h3F800000, `__LINE__); //6 - 5 = 1
iteration(32'hC0C00000, 32'hC0A00000, 32'hBF800000, `__LINE__); //-6 - (-5) = -1
iteration(32'hC0A00000, 32'hC0C00000, 32'h3F800000, `__LINE__); // -5 - (-6) = 1
iteration(32'h40C00000, 32'hC0A00000, 32'h41300000, `__LINE__); // 6 - (-5) = 11
iteration(32'h40A00000, 32'hC0C00000, 32'h41300000, `__LINE__); // 5 - (-6) = 11
iteration(32'hC0A00000, 32'h40C00000, 32'hC1300000, `__LINE__); // -5 - (6) = -11
iteration(32'hC0C00000, 32'h40A00000, 32'hC1300000, `__LINE__); // -6 - (+5) = -11
// Exception Cases //
iteration(32'h0000_0000, 32'h3EC7_AE14, 32'hBEC7_AE14, `__LINE__);
iteration(32'h3EC7_AE14, 32'h0000_0000, 32'h3EC7_AE14, `__LINE__);
iteration(32'h0000_0000, 32'h0000_0000, 32'h0000_0000, `__LINE__);
iteration(32'h7F80_0000, 32'h7F90_0100, 32'h7F80_0000, `__LINE__);
iteration(32'h7F80_0000, 32'h3EC7_AE14, 32'h7F80_0000, `__LINE__);
iteration(32'h3EC7_AE14, 32'h7F80_0000, 32'hFF80_0000, `__LINE__);
iteration(32'h7F80_0000, 32'h0000_0000, 32'h7F80_0000, `__LINE__);
iteration(32'h7F90_0100, 32'h7F80_0000, 32'h7F80_0000, `__LINE__);
@(negedge clk) $stop;
end
task iteration(input [31:0] op_a, op_b, expected_value, input integer line_num);
begin
@(negedge clk) begin
a = op_a;
b = op_b;
end
@(posedge clk) begin
#1;
if (expected_value == res) $display("Success: Line Number -> %d", line_num);
else
$display(
"Failed: \t\n A => %h, \t\n B => %h, \t\n Result Obtained => %h, \t\n Expected Value => %h - Line Number",
op_a,
op_b,
res,
expected_value,
line_num
);
end
end
endtask
endmodule
| 7.491655 |
module add_sub_8bit (
overflow,
S_D,
C_B,
A,
B,
operator
);
input operator;
input [7:0] A;
input [7:0] B;
output wire [7:0] S_D;
output wire C_B;
output wire overflow;
wire [6:0] temp_carryout;
wire [7:0] B_temp;
xor inst11 (B_temp[0], B[0], operator);
full_adder inst1 (
S_D[0],
temp_carryout[0],
A[0],
B_temp[0],
operator
);
xor inst22 (B_temp[1], B[1], operator);
full_adder inst2 (
S_D[1],
temp_carryout[1],
A[1],
B_temp[1],
temp_carryout[0]
);
xor inst33 (B_temp[2], B[2], operator);
full_adder inst3 (
S_D[2],
temp_carryout[2],
A[2],
B_temp[2],
temp_carryout[1]
);
xor inst44 (B_temp[3], B[3], operator);
full_adder inst4 (
S_D[3],
temp_carryout[3],
A[3],
B_temp[3],
temp_carryout[2]
);
xor inst55 (B_temp[4], B[4], operator);
full_adder inst5 (
S_D[4],
temp_carryout[4],
A[4],
B_temp[4],
temp_carryout[3]
);
xor inst66 (B_temp[5], B[5], operator);
full_adder inst6 (
S_D[5],
temp_carryout[5],
A[5],
B_temp[5],
temp_carryout[4]
);
xor inst77 (B_temp[6], B[6], operator);
full_adder inst7 (
S_D[6],
temp_carryout[6],
A[6],
B_temp[6],
temp_carryout[5]
);
xor inst88 (B_temp[7], B[7], operator);
full_adder inst8 (
S_D[7],
C_B,
A[7],
B_temp[7],
temp_carryout[6]
);
xor inst_over (overflow, temp_carryout[6], C_B);
endmodule
| 6.797515 |
module add_sub_8bit (
output [7:0] S_D,
output C_B,
output Overflow,
input [7:0] A,
input [7:0] B,
input Operator
);
wire [7:0] Bq; //temporary variable
wire [6:0] Cout;
assign Bq[0] = B[0] ^ Operator;
assign Bq[1] = B[1] ^ Operator;
assign Bq[2] = B[2] ^ Operator;
assign Bq[3] = B[3] ^ Operator;
assign Bq[4] = B[4] ^ Operator;
assign Bq[5] = B[5] ^ Operator;
assign Bq[6] = B[6] ^ Operator;
assign Bq[7] = B[7] ^ Operator;
Full_adder fb1 (
S_D[0],
Cout[0],
A[0],
Bq[0],
Operator
);
Full_adder fb2 (
S_D[1],
Cout[1],
A[1],
Bq[1],
Cout[0]
);
Full_adder fb3 (
S_D[2],
Cout[2],
A[2],
Bq[2],
Cout[1]
);
Full_adder fb4 (
S_D[3],
Cout[3],
A[3],
Bq[3],
Cout[2]
);
Full_adder fb5 (
S_D[4],
Cout[4],
A[4],
Bq[4],
Cout[3]
);
Full_adder fb6 (
S_D[5],
Cout[5],
A[5],
Bq[5],
Cout[4]
);
Full_adder fb7 (
S_D[6],
Cout[6],
A[6],
Bq[6],
Cout[5]
);
Full_adder fb8 (
S_D[7],
C_B,
A[7],
Bq[7],
Cout[6]
);
assign Overflow = C_B ^ Cout[6];
endmodule
| 6.797515 |
module Add_Sub_8bit_tb ();
// set input as register and output as wires
reg Sub;
reg [7:0] InA, InB;
wire [7:0] Output;
//instantiate design code
Add_Sub_8bit testing (
Sub,
InA,
InB,
Output
);
//Test vectors start here
initial begin
//initialize all inputs
#0 Sub = 0;
InA = 8'd0;
InB = 8'd0;
#10 InA = 8'd10;
InB = 8'd5; //Expect output 15
#10 InA = 8'd1;
InB = 8'd1; //Expect output 2
#10 Sub = 1;
InA = 8'd3;
InB = 8'd3; //Expect output 0
#10 Sub = 1;
InA = 8'd1;
InB = 8'd2; //Expect -1
end
endmodule
| 7.683465 |
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