code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module adder (
a,
b,
y
);
parameter WIDTH = 64;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_combine_64_bit (
a,
b,
Result_mul,
Result_add
);
parameter WIDTH = 64;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] Result_add;
output reg [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
... | 6.911403 |
module adder (
a,
b,
y
);
parameter WIDTH = 8;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_combine_8_bit (
a,
b,
Result_mul,
Result_add
);
parameter WIDTH = 8;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] Result_add;
output reg [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
... | 6.911403 |
module adder (
a,
b,
y
);
parameter WIDTH = 16;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_16_bit (
a,
b,
Result
);
parameter WIDTH = 16;
input [0:WIDTH-1] a, b;
output reg [0:(WIDTH*2)-1] Result;
wire A_greater_B;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier mu... | 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 2;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_2_bit (
a,
b,
Result
);
parameter WIDTH = 2;
input [0:WIDTH-1] a, b;
output reg [0:(WIDTH*2)-1] Result;
wire A_greater_B;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier mult... | 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 32;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_32_bit (
a,
b,
Result
);
parameter WIDTH = 32;
input [0:WIDTH-1] a, b;
output reg [0:(WIDTH*2)-1] Result;
wire A_greater_B;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier mu... | 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 4;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_4_bit (
a,
b,
Result
);
parameter WIDTH = 4;
input [0:WIDTH-1] a, b;
output reg [0:(WIDTH*2)-1] Result;
wire A_greater_B;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier mult... | 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 64;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_64_bit (
a,
b,
Result
);
parameter WIDTH = 64;
input [0:WIDTH-1] a, b;
output reg [0:(WIDTH*2)-1] Result;
wire A_greater_B;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier mu... | 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 8;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_8_bit (
a,
b,
Result
);
parameter WIDTH = 8;
input [0:WIDTH-1] a, b;
output reg [0:(WIDTH*2)-1] Result;
wire A_greater_B;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier mult... | 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 16;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_sub_16_bit(a, b,Result);
parameter WIDTH=16;
input [0:WIDTH-1]a, b;
wire [0:1]operation;
output reg [0:(WIDTH*2)-1]Result;
wire [0:(WIDTH*2)-1]Result_sub1;
wire [0:(WIDTH*2)-1]Result_sub2;
wire [0:(WIDTH*2)-1]Result_add;
wire [0:(WIDTH*2)-1]Result_mul;
subtr... | 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 2;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_sub_2_bit(a, b,Result);
parameter WIDTH=2;
input [0:WIDTH-1]a, b;
wire [0:1]operation;
output reg [0:(WIDTH*2)-1]Result;
wire [0:(WIDTH*2)-1]Result_sub1;
wire [0:(WIDTH*2)-1]Result_sub2;
wire [0:(WIDTH*2)-1]Result_add;
wire [0:(WIDTH*2)-1]Result_mul;
subtrac... | 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 32;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_sub_32_bit(a, b,Result);
parameter WIDTH=32;
input [0:WIDTH-1]a, b;
wire [0:1]operation;
output reg [0:(WIDTH*2)-1]Result;
wire [0:(WIDTH*2)-1]Result_sub1;
wire [0:(WIDTH*2)-1]Result_sub2;
wire [0:(WIDTH*2)-1]Result_add;
wire [0:(WIDTH*2)-1]Result_mul;
subtr... | 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 4;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_sub_4_bit(a, b,Result);
parameter WIDTH=4;
input [0:WIDTH-1]a, b;
wire [0:1]operation;
output reg [0:(WIDTH*2)-1]Result;
wire [0:(WIDTH*2)-1]Result_sub1;
wire [0:(WIDTH*2)-1]Result_sub2;
wire [0:(WIDTH*2)-1]Result_add;
wire [0:(WIDTH*2)-1]Result_mul;
subtrac... | 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 64;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_sub_64_bit(a, b,Result);
parameter WIDTH=64;
input [0:WIDTH-1]a, b;
wire [0:1]operation;
output reg [0:(WIDTH*2)-1]Result;
wire [0:(WIDTH*2)-1]Result_sub1;
wire [0:(WIDTH*2)-1]Result_sub2;
wire [0:(WIDTH*2)-1]Result_add;
wire [0:(WIDTH*2)-1]Result_mul;
subtr... | 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 8;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_comp_sub_8_bit(a, b,Result);
parameter WIDTH=8;
input [0:WIDTH-1]a, b;
wire [0:1]operation;
output reg [0:(WIDTH*2)-1]Result;
wire [0:(WIDTH*2)-1]Result_sub1;
wire [0:(WIDTH*2)-1]Result_sub2;
wire [0:(WIDTH*2)-1]Result_add;
wire [0:(WIDTH*2)-1]Result_mul;
subtrac... | 6.970429 |
module adder (
a,
b,
y
);
parameter WIDTH = 16;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module adder (
a,
b,
y
);
parameter WIDTH = 2;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_mix_2_bit (
a,
b,
c,
d,
Result
);
parameter WIDTH = 2;
input [0:WIDTH-1] a, b, c, d;
wire [0:WIDTH-1] Result_add_2;
wire [0:WIDTH-1] Result_add;
output reg [0:(WIDTH*2)-1] Result;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
adder adder_2 (
... | 6.645763 |
module adder (
a,
b,
y
);
parameter WIDTH = 32;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_mix_32_bit (
a,
b,
c,
d,
Result
);
parameter WIDTH = 32;
input [0:WIDTH-1] a, b, c, d;
wire [0:WIDTH-1] Result_add_2;
wire [0:WIDTH-1] Result_add;
output reg [0:(WIDTH*2)-1] Result;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
adder adder_2 (
... | 6.957106 |
module adder (
a,
b,
y
);
parameter WIDTH = 4;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_mix_4_bit (
a,
b,
c,
d,
Result
);
parameter WIDTH = 4;
input [0:WIDTH-1] a, b, c, d;
wire [0:WIDTH-1] Result_add_2;
wire [0:WIDTH-1] Result_add;
output reg [0:(WIDTH*2)-1] Result;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
adder adder_2 (
... | 6.729989 |
module adder (
a,
b,
y
);
parameter WIDTH = 64;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_mix_64_bit (
a,
b,
c,
d,
Result
);
parameter WIDTH = 64;
input [0:WIDTH-1] a, b, c, d;
wire [0:WIDTH-1] Result_add_2;
wire [0:WIDTH-1] Result_add;
output reg [0:(WIDTH*2)-1] Result;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
adder adder_2 (
... | 7.004283 |
module adder (
a,
b,
y
);
parameter WIDTH = 8;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module adder (
a,
b,
y
);
parameter WIDTH = 16;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module adder (
a,
b,
y
);
parameter WIDTH = 2;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module adder (
a,
b,
y
);
parameter WIDTH = 32;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module adder (
a,
b,
y
);
parameter WIDTH = 4;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module adder (
a,
b,
y
);
parameter WIDTH = 64;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module adder (
a,
b,
y
);
parameter WIDTH = 8;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mux (
A,
B,
cin,
s,
cout
);
input [1:0] A;
input [1:0] B;
input cin;
output reg [1:0] s;
output reg cout;
reg sel;
reg [3:0] temp;
always @(*) begin
fork
s[0] = A[0] ^ B[0] ^ cin;
sel = (A[0] & B[0]) | (A[0] ^ B[0]) & cin;
temp[1:0] = A[1] + B[1];
... | 7.750574 |
module data_extract_N32_ES6 (
in,
rc,
regime,
exp,
mant
);
function [31:0] log2;
input reg [31:0] value;
begin
value = value - 1;
for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1;
end
endfunction
parameter N = 32;
parameter Bs = log2(N);
parameter es... | 8.552482 |
module add_N (
a,
b,
c
);
parameter N = 10;
input [N-1:0] a, b;
output [N:0] c;
assign c = {1'b0, a} + {1'b0, b};
endmodule
| 6.530958 |
module DSR_left_N_S (
a,
b,
c
);
parameter N = 16;
parameter S = 4;
input [N-1:0] a;
input [S-1:0] b;
output [N-1:0] c;
wire [N-1:0] tmp[S-1:0];
assign tmp[0] = b[0] ? a << 7'd1 : a;
genvar i;
generate
for (i = 1; i < S; i = i + 1) begin : loop_blk
assign tmp[i] = b[i] ? tmp[i-1... | 6.55013 |
module LOD16_4 (
in,
out,
out_v
);
input [15:0] in;
output [3:0] out;
output out_v;
wire [2:0] out_l, out_h;
wire out_vl, out_vh;
LOD8_3 pl (
.in(in[7:0]),
.out(out_l),
.out_v(out_vl)
);
LOD8_3 ph (
.in(in[15:8]),
.out(out_h),
.out_v(out_vh)
);
assign ... | 6.780402 |
module LOD8_3 (
in,
out,
out_v
);
input [7:0] in;
output [2:0] out;
output out_v;
wire [1:0] out_l, out_h;
wire out_vl, out_vh;
LOD4_2 pl (
.in(in[3:0]),
.out(out_l),
.out_v(out_vl)
);
LOD4_2 ph (
.in(in[7:4]),
.out(out_h),
.out_v(out_vh)
);
assign ou... | 6.634091 |
module LOD4_2 (
in,
out,
out_v
);
input [3:0] in;
output [1:0] out;
output out_v;
wire out_l, out_h;
wire out_vl, out_vh;
LOD2_1 pl (
.in(in[1:0]),
.out(out_l),
.out_v(out_vl)
);
LOD2_1 ph (
.in(in[3:2]),
.out(out_h),
.out_v(out_vh)
);
assign out = ... | 6.607174 |
module LOD2_1 (
in,
out,
out_v
);
input [1:0] in;
output out;
output out_v;
assign out = ~in[1] & in[0];
assign out_v = |in;
endmodule
| 7.042873 |
module add_normalizer (
input sign,
input [ 4:0] exponent,
input [10:0] mantissa_add,
output reg [15:0] result,
input if_carray,
input if_sub
);
reg [4:0] number_of_zero_lead;
reg [10:0] norm_mantissa_add;
reg [9:0] mantissa_tmp;
wire [4:0]... | 6.840817 |
module ADD_n_bit (
c_out,
ADD_out,
R2,
R3,
c_in
);
parameter word_size = 32; // the default size of this n bit adder
input [word_size-1:0] R2, R3;
input c_in;
output [word_size-1:0] ADD_out;
output c_out;
wire [word_size-1:0] c_inner;
// the c_out of the ith 1-bit full aderr is t... | 8.831432 |
module add_N_tb ();
// note this only runs for 50 cycles with the below settings
// alter TB_TIMEOUT to run longer
localparam TB_TIMEOUT = 100000;
localparam TB_CLK_PERIOD = 2000;
localparam TB_RST_PERIOD = 4000;
initial #(TB_TIMEOUT) $finish();
// clock
reg tb_clk = 1'b0;
always #(TB_CLK_PERIOD / ... | 6.93342 |
module add_one (
input [7:0] in,
output [7:0] out
);
assign out = in + 1;
endmodule
| 6.581511 |
module add_onebit (
input wire a,
input wire b,
input wire ci,
output wire sum,
output wire co
);
//(sum,cout,a,b,cin);
//input a,b,cin;
//output sum;
//output cout;
assign sum = a ^ b ^ ci;
assign co = a & b | b & ci | a & ci;
endmodule
| 7.552698 |
module add_onescomp #(
parameter WIDTH = 16
) (
input [WIDTH-1:0] A,
input [WIDTH-1:0] B,
output [WIDTH-1:0] SUM
);
wire [WIDTH:0] SUM_INT = {1'b0, A} + {1'b0, B};
assign SUM = SUM_INT[WIDTH-1:0] + {{WIDTH - 1{1'b0}}, SUM_INT[WIDTH]};
endmodule
| 7.334453 |
module for the add_one module.
*
* This module contains the followng items:
* - A foreign module definition for use in instantiatin the type_wrapper module
* which contains the BEH module instance.
* - An instance of the type_wrapper foreign module.
* - alwyas blocks each type_wrapper output.
*
*****************... | 6.677536 |
module add_op (
A,
B,
ctrl,
prop,
gen,
sum
);
input [31:0] A, B;
input ctrl;
output [31:0] prop, gen, sum;
// TODO here -> Let me go make some intermediary things uwu
// Okay we back after making our block/full adder
wire [3:0] block_carry, block_gen, block_prop;
assign block_car... | 6.916946 |
module add_block_8 (
A,
B,
ctrl,
prop0,
gen0,
prop,
gen,
sum
);
input [7:0] A, B;
input ctrl;
output [7:0] prop0, gen0, sum;
output prop, gen;
wire [7:0] carry;
assign carry[0] = ctrl;
// genvar time uwu
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin
... | 6.830493 |
module Add_PC (
entrada_PC,
saida_addPC
);
input [31:0] entrada_PC;
output wire [31:0] saida_addPC;
assign saida_addPC = entrada_PC + 1;
endmodule
| 6.883197 |
module ADD_PC_4 (
in_pc,
out_pc
);
input [`WIDTH_PC-1:0] in_pc;
output [`WIDTH_PC-1:0] out_pc;
assign out_pc = in_pc + 32'd4;
endmodule
| 7.464804 |
module add_preamble (
input wire clk,
input wire [7:0] data_in,
input wire data_valid_in,
input wire data_enable_in,
output reg [7:0] data_out = 8'b0,
output reg data_valid_out = 1'b0,
output reg data_enable_out = 1'b0
);
reg [63:0] delay_data = 64'b0;
reg [ 7:0] delay_data_valid = 8'b0... | 6.743079 |
module add_rca #(
parameter Bits = 64
) (
input clk,
input reset,
input [Bits-1:0] a,
input [Bits-1:0] b,
output [Bits-1:0] sum,
output reg carry
);
reg [Bits:0] c;
assign c[0] = 1'b0;
genvar i;
generate
for (i = 0; i < Bits; i = i + 1) begin
full_adder ... | 7.27429 |
module add_rca_tb (
input [64-1:0] a,
input [64-1:0] b,
output [64-1:0] sum,
output reg carry
);
add_rca #(
.Bits(64)
) f (
.a(a),
.b(b),
.sum(sum),
.carry(carry)
);
endmodule
| 8.54899 |
module add_rca_2_bit (
X,
Y,
ci,
sum,
co
);
input wire [1:0] X, Y;
input wire ci;
output wire [1:0] sum;
output wire co;
wire co_int_1;
full_adder adder_1 (
.X (X[0]),
.Y (Y[0]),
.ci (ci),
.sum(sum[0]),
.co (co_int_1)
);
full_adder adder_2 (
.X... | 7.026416 |
module add_rca_2_bit_test;
// Inputs
reg [1:0] X;
reg [1:0] Y;
reg ci;
// Outputs
wire [1:0] sum;
wire co;
// Instantiate the Unit Under Test (UUT)
add_rca_2_bit uut (
.X (X),
.Y (Y),
.ci (ci),
.sum(sum),
.co (co)
);
integer i, j, k;
integer error = 0;
initi... | 7.026416 |
module Add_rca_32 (
sum,
c_out,
a,
b,
c_in
);
output signed [31:0] sum;
output c_out;
input signed [31:0] a, b;
input c_in;
wire c_in_0_15, c_out;
Add_rca_16_0_delay M1 (
sum[15:0],
c_in_0_15,
a[15:0],
b[15:0],
c_in
);
Add_rca_16_0_delay M2 (
sum[... | 6.933489 |
module add_rca_32_bit (
X,
Y,
ci,
sum,
co
);
input wire [31:0] X, Y;
input wire ci;
output wire [31:0] sum;
output wire co;
wire co_int_1, co_int_2, co_int_3;
add_rca_8_bit adder_1 (
.X (X[7:0]),
.Y (Y[7:0]),
.ci (ci),
.sum(sum[7:0]),
.co (co_int_1)
);
... | 8.593074 |
module add_rca_32_bit_test;
// Inputs
reg [31:0] X;
reg [31:0] Y;
reg ci;
// Outputs
wire co;
wire [31:0] sum;
// Instantiate the Unit Under Test (UUT)
add_rca_32_bit uut (
.X (X),
.Y (Y),
.ci (ci),
.sum(sum),
.co (co)
);
integer i, j, k, r;
integer error = 0;... | 8.593074 |
module add_rca_8_bit (
X,
Y,
ci,
sum,
co
);
input wire [7:0] X, Y;
input wire ci;
output wire [7:0] sum;
output wire co;
wire co_int_1, co_int_2, co_int_3;
add_rca_2_bit adder_1 (
.X (X[1:0]),
.Y (Y[1:0]),
.ci (ci),
.sum(sum[1:0]),
.co (co_int_1)
);
... | 6.517539 |
module add_rca_8_bit_test;
// Inputs
reg [7:0] X;
reg [7:0] Y;
reg ci;
// Outputs
wire [7:0] sum;
wire co;
// Instantiate the Unit Under Test (UUT)
add_rca_8_bit uut (
.X (X),
.Y (Y),
.ci (ci),
.sum(sum),
.co (co)
);
integer i, j, k, r;
integer error = 0;
in... | 6.517539 |
module add_rca_signed #(
parameter Bits = 64
) (
input clk,
input reset,
input [Bits-1:0] a,
input [Bits-1:0] b,
output [Bits-1:0] sum,
output reg carry
);
reg [Bits:0] c;
assign c[0] = 1'b0;
genvar i;
generate
for (i = 0; i < Bits; i = i + 1) begin
full... | 7.273513 |
module add_reg (
clk,
addin,
addresult,
rst_n
);
input clk;
input rst_n;
input [11:0] addin;
output [19:0] addresult;
reg [19:0] addresult;
always @(negedge rst_n or posedge clk) begin
if (rst_n == 1'b0) begin
addresult <= 0;
end else begin
addresult <= addresult + a... | 6.571512 |
module add_rm_hdr #(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH / 8,
parameter STAGE_NUMBER = 'hff,
parameter PORT_NUMBER = 0
) (
input [DATA_WIDTH-1:0] rx_in_data,
input [CTRL_WIDTH-1:0] rx_in_ctrl,
input rx_in_wr,
output rx_in... | 7.764609 |
module add_rom (
input [4:0] addr,
input [3:0] imm4,
output reg [7:0] label
);
always @(*)
case (addr)
0: label = "A";
1: label = "D";
2: label = "D";
4: label = imm4[3];
5: label = imm4[2];
6: label = imm4[1];
7: label = imm4[0];
default: label = " ";
... | 6.575915 |
module Add_Round (
clk,
rst,
read_address,
read_data,
write_address,
write_data,
write_en,
done,
buffer40_en,
buffer40_data,
buffer64_en,
buffer
);
input clk, rst;
output reg [8:0] read_address;
input [63:0] read_data;
output reg [8:0] write_address;
output [63... | 8.096778 |
module add_round_key (
output wire [7:0] out,
input wire [7:0] in1,
in2
);
assign out = in1 ^ in2;
endmodule
| 6.601743 |
module add_round_keys (
input wire [127 : 0] state,
input wire [127 : 0] subkey,
// output reg[127 : 0] out
output [127 : 0] out
);
//always @*
// begin
assign out = state ^ subkey;
// end
endmodule
| 6.601743 |
module ADD_ROUND_KEY_state (
clk,
rst,
data_in,
addr_in,
sel,
out_REG
);
input wire clk, rst;
input wire [7:0] data_in;
input wire [3:0] addr_in;
input wire [3:0] sel;
output wire [7:0] out_REG;
wire [7:0] out;
reg [7:0] out_mux;
wire [7:0] out_round0,out_round1,out_round2,out_... | 7.259458 |
module add_round_key_tb;
reg [127:0] roundKey;
reg [127:0] inputData;
reg [127:0] expectedValue;
wire [127:0] outputData;
add_round_key dut (
.inputData (inputData),
.roundKey (roundKey),
.outputData(outputData)
);
initial begin
expectedValue = 128'h1a3174470b1b226e59084e3c540... | 6.601743 |
module add_tound_ket_tb;
reg startTransition;
reg clock50MHz;
reg [127:0] roundKey;
reg [127:0] inputData;
wire [127:0] outputData;
add_round_key dut (
.inputData(inputData),
.roundKey(roundKey),
.startTransition(startTransition),
.outputData(outputData)
);
localparam NUM_CY... | 6.950945 |
module add_share (
input a,
b,
x,
y,
sel,
en,
clk,
output reg out1,
out2
);
wire tmp1, tmp2;
assign tmp1 = a * b; // tmp1Ҫһ˷
assign tmp2 = x * y; // tmp2Ҫһ˷
always @(posedge clk)
if (en) begin
out1 <= sel ? tmp1 : tmp2; //tmp1tmp2ͬʱЧ
end else begin
out... | 6.650665 |
module add_share1 #(
parameter N = 8
) (
input [N-1:0] a,
b,
x,
y,
input sel,
en,
clk,
output reg [N-1:0] out1,
out2
);
wire [N-1:0] tmp1, tmp2;
assign tmp1 = a * b; // tmp1Ҫһ˷
assign tmp2 = x * y; // tmp2Ҫһ˷
always @(posedge clk)
if (en) begin
out1 <= sel ? ... | 7.485426 |
module add_share2 #(
parameter N = 8
) (
input [N-1:0] a,
b,
x,
y,
input sel,
en,
clk,
output reg [N-1:0] out1
);
wire [N-1:0] tmp1, tmp2;
assign tmp1 = sel ? a : x; // ˷A
assign tmp2 = sel ? b : y; // ˷B
always @(posedge clk)
if (en) begin
out1 = tmp1 * tmp2; /... | 7.755956 |
module add_share3 #(
parameter N = 8
) (
input [N-1:0] a,
b,
x,
y,
input sel,
en,
clk,
output reg [N-1:0] out1
);
wire [N-1:0] tmp1, tmp2;
assign tmp1 = a * b; // tmp1Ҫһ˷
assign tmp2 = x * y; // tmp2Ҫһ˷
always @(posedge clk)
if (en) begin
out1 <= sel ? tmp1 : tmp... | 7.642123 |
module add_sub1 (
a,
b,
cin,
s,
cout
);
input a, b, cin;
output s, cout;
wire xorab, andab, andxorcab;
xor g1 (xorab, a, b);
xor g2 (s, xorab, cin);
and g3 (andab, a, b);
and g4 (andxorcab, cin, xorab);
or g5 (cout, andxorcab, andab);
endmodule
| 7.135565 |
module add_sub (
a,
b,
cin,
sum,
cout
);
input [3:0] a;
input [3:0] b;
input cin;
output [1:0] sum;
output cout;
wire carry;
add_sub1 g5 (
a[0],
b[0],
cin,
sum[0],
carry
);
add_sub1 g6 (
a[1],
b[1],
carry,
sum[1],
cout
)... | 7.314322 |
module add_sub (
a,
b,
c0,
s,
ovf
);
input [3:0] a, b;
input c0;
output [3:0] s;
output ovf; //overflow
//4 full adders used to make four bit adder.
//carry of each full adder is passed as input to the next full adder
wire c, c1, c2, c3;
//modified 4 bit adder. b[i]^c0 instead of b... | 7.314322 |
module add_sub27 (
add,
opa,
opb,
sum,
co
);
input add;
input [26:0] opa, opb;
output [26:0] sum;
output co;
assign {co, sum} = add ? ({1'b0, opa} + {1'b0, opb}) : ({1'b0, opa} - {1'b0, opb});
endmodule
| 6.628721 |
module adder (
enable,
a0,
a1,
cout
);
input enable;
input [15:0] a0, a1;
output [15:0] cout;
wire c, d, e, f, g, h, i, j, k, l, m, n, o, p, q, r;
wire input0,input1, input2, input3, input4, input5, input6, input7, input8, input9, input10,input11, input12, input13, input14, input15;
xor (... | 6.560729 |
module top_module (
input [31:0] a,
input [31:0] b,
input sub,
output [31:0] sum
);
wire [31:0] xor_b = b ^ {32{sub}};
wire lcout;
wire [15:0] lsum;
wire [15:0] hsum;
add16 ladd16 (
.a(a[15:0]),
.b(xor_b[15:0]),
.cin(sub),
.cout(lcout),
.sum(lsum)
);
add16 ... | 7.203305 |
module Add_Subt #(
parameter SWR = 26
) (
input wire clk,
input wire rst,
input wire load_i, //Reg load input
input wire Add_Sub_op_i,
input wire [SWR-1:0] Data_A_i,
input wire [SWR-1:0] PreData_B_i,
/////////////////////////////////////////////////////////////
output wire [SWR... | 6.759045 |
module add_subtract #(
parameter N = 8
) (
input clk,
aclr,
add_sub,
input [N-1:0] A,
output reg [N-1:0] S,
output reg overflow,
carry
);
reg [N-1:0] B;
always @(posedge clk, posedge aclr)
if (aclr) B <= {N{1'b0}};
else B <= A;
always @(posedge clk, posedge aclr)
if ... | 6.852344 |
module ADD_SUB_2021 (
a,
b,
add_sub_signal,
exception,
res
);
input wire [31:0] a, b;
input wire add_sub_signal;
output wire exception;
output wire [31:0] res;
//--------------------------------------------------------------------------------------------------------------------------------... | 6.60829 |
module ADD_SUB_2021_TB;
reg [31:0] a, b;
reg clk = 1'b0, reset = 1'b1;
reg add_sub_signal;
wire [31:0] res;
wire exception;
ADD_SUB_2021 uut (
a,
b,
add_sub_signal,
exception,
res
);
always #5 clk = ~clk;
initial begin
add_sub_signal = 1'b0;
iteration(32'h42... | 7.491655 |
module add_sub_8bit (
overflow,
S_D,
C_B,
A,
B,
operator
);
input operator;
input [7:0] A;
input [7:0] B;
output wire [7:0] S_D;
output wire C_B;
output wire overflow;
wire [6:0] temp_carryout;
wire [7:0] B_temp;
xor inst11 (B_temp[0], B[0], operator);
full_adder inst1 (... | 6.797515 |
module add_sub_8bit (
output [7:0] S_D,
output C_B,
output Overflow,
input [7:0] A,
input [7:0] B,
input Operator
);
wire [7:0] Bq; //temporary variable
wire [6:0] Cout;
assign Bq[0] = B[0] ^ Operator;
assign Bq[1] = B[1] ^ Operator;
assign Bq[2] = B[2] ^ Operator;
assign Bq[3] = ... | 6.797515 |
module Add_Sub_8bit_tb ();
// set input as register and output as wires
reg Sub;
reg [7:0] InA, InB;
wire [7:0] Output;
//instantiate design code
Add_Sub_8bit testing (
Sub,
InA,
InB,
Output
);
//Test vectors start here
initial begin
//initialize all inputs
#0 Sub ... | 7.683465 |
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