code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module oai21 (
Y,
A0,
A1,
B0
);
output Y;
input A0;
input A1;
input B0;
or (adk113, A0, A1);
and (adk114, adk113, B0);
not (Y, adk114);
endmodule
| 6.561625 |
module oai22 (
Y,
A0,
A1,
B0,
B1
);
output Y;
input A0;
input A1;
input B0;
input B1;
or (adk115, A0, A1);
or (adk116, B0, B1);
and (adk117, adk115, adk116);
not (Y, adk117);
endmodule
| 6.579044 |
module oai322 (
Y,
A0,
A1,
A2,
B0,
B1,
C0,
C1
);
output Y;
input A0;
input A1;
input A2;
input B0;
input B1;
input C0;
input C1;
or (adk136, A0, A1);
or (adk137, adk136, A2);
or (adk138, B0, B1);
and (adk139, adk137, adk138);
or (adk140, C0, C1);
and (adk141, adk139, adk140);
not (Y, adk141);
endmodule
| 7.023531 |
module oai332 (
Y,
A0,
A1,
A2,
B0,
B1,
B2,
C0,
C1
);
output Y;
input A0;
input A1;
input A2;
input B0;
input B1;
input B2;
input C0;
input C1;
or (adk147, A0, A1);
or (adk148, adk147, A2);
or (adk149, B0, B1);
or (adk150, adk149, B2);
and (adk151, adk148, adk150);
or (adk152, C0, C1);
and (adk153, adk151, adk152);
not (Y, adk153);
endmodule
| 6.981774 |
module oai333 (
Y,
A0,
A1,
A2,
B0,
B1,
B2,
C0,
C1,
C2
);
output Y;
input A0;
input A1;
input A2;
input B0;
input B1;
input B2;
input C0;
input C1;
input C2;
or (adk154, A0, A1);
or (adk155, adk154, A2);
or (adk156, B0, B1);
or (adk157, adk156, B2);
and (adk158, adk155, adk157);
or (adk159, C0, C1);
or (adk160, adk159, C2);
and (adk161, adk158, adk160);
not (Y, adk161);
endmodule
| 6.640396 |
module oai422 (
Y,
A0,
A1,
A2,
A3,
B0,
B1,
C0,
C1
);
output Y;
input A0;
input A1;
input A2;
input A3;
input B0;
input B1;
input C0;
input C1;
or (adk162, A0, A1);
or (adk163, adk162, A2);
or (adk164, adk163, A3);
or (adk165, B0, B1);
and (adk166, adk164, adk165);
or (adk167, C0, C1);
and (adk168, adk166, adk167);
not (Y, adk168);
endmodule
| 7.226871 |
module oai43 (
Y,
A0,
A1,
A2,
A3,
B0,
B1,
B2
);
output Y;
input A0;
input A1;
input A2;
input A3;
input B0;
input B1;
input B2;
or (adk169, A0, A1);
or (adk170, adk169, A2);
or (adk171, adk170, A3);
or (adk172, B0, B1);
or (adk173, adk172, B2);
and (adk174, adk171, adk173);
not (Y, adk174);
endmodule
| 6.792928 |
module oai44 (
Y,
A0,
A1,
A2,
A3,
B0,
B1,
B2,
B3
);
output Y;
input A0;
input A1;
input A2;
input A3;
input B0;
input B1;
input B2;
input B3;
or (adk175, A0, A1);
or (adk176, adk175, A2);
or (adk177, adk176, A3);
or (adk178, B0, B1);
or (adk179, adk178, B2);
or (adk180, adk179, B3);
and (adk181, adk177, adk180);
not (Y, adk181);
endmodule
| 6.921658 |
module or02 (
Y,
A0,
A1
);
output Y;
input A0;
input A1;
or (Y, A0, A1);
endmodule
| 6.916537 |
module or03 (
Y,
A0,
A1,
A2
);
output Y;
input A0;
input A1;
input A2;
or (adk182, A0, A1);
or (Y, adk182, A2);
endmodule
| 6.726178 |
module or04 (
Y,
A0,
A1,
A2,
A3
);
output Y;
input A0;
input A1;
input A2;
input A3;
or (adk183, A0, A1);
or (adk184, adk183, A2);
or (Y, adk184, A3);
endmodule
| 7.070299 |
module xnor2 (
Y,
A0,
A1
);
output Y;
input A0;
input A1;
xor (adk215, A0, A1);
not (Y, adk215);
endmodule
| 6.713225 |
module xor2 (
Y,
A0,
A1
);
output Y;
input A0;
input A1;
xor (Y, A0, A1);
endmodule
| 7.788927 |
module: adld_hw
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module adld_tb;
// Inputs
reg [2:0] a_late;
reg [2:0] b;
// Outputs
wire [2:0] out;
// Instantiate the Unit Under Test (UUT)
adld_hw uut (
.a_late(a_late),
.b(b),
.out(out)
);
always
begin
b = 3;
#5 a_late = 2;
b = 1;
#5 a_late = 2;
$monitor("time = %t",$time);
end
endmodule
| 7.026131 |
module AdLib (
input wire clk,
input wire reset_n,
input wire [11:0] port,
input wire [7:0] iodin,
output wire [7:0] iodout,
input wire iowr,
input wire iordin,
output reg iordout,
output wire ready,
output reg [7:0] music
);
assign ready = iordin == iordout;
reg [5:0] iodelay;
always @(posedge clk) begin
if (|iodelay) begin
iodelay <= iodelay + 1'd1;
if (&iodelay) iordout <= iordin;
end else if (iordin ^ iordout) begin
if (port[11:4] == 8'h38) iodelay <= 1'd1;
else iordout <= iordin;
end
end
assign iodout = {timer1[8] | timer2[8], timer1[8], timer2[8], 5'h0};
reg [8:0] timer1;
reg [8:0] timer2;
reg timer1_start;
reg timer2_start;
reg timer1_mask;
reg timer2_mask;
reg [13:0] timer_div;
reg [7:0] index;
reg distortion;
reg rhythm;
wire regwr = iowr && (port == 12'h389);
reg [19:0] result;
wire [15:0] ch0res;
AdLibChannel #(0, 0) ch0 (
.clk(clk),
.a(index),
.din(iodin),
.regwr(regwr),
.distortion(distortion),
.result(ch0res)
);
wire [15:0] ch1res;
AdLibChannel #(1, 1) ch1 (
.clk(clk),
.a(index),
.din(iodin),
.regwr(regwr),
.distortion(distortion),
.result(ch1res)
);
wire [15:0] ch2res;
AdLibChannel #(2, 2) ch2 (
.clk(clk),
.a(index),
.din(iodin),
.regwr(regwr),
.distortion(distortion),
.result(ch2res)
);
wire [15:0] ch3res;
AdLibChannel #(3, 8) ch3 (
.clk(clk),
.a(index),
.din(iodin),
.regwr(regwr),
.distortion(distortion),
.result(ch3res)
);
wire [15:0] ch4res;
AdLibChannel #(4, 9) ch4 (
.clk(clk),
.a(index),
.din(iodin),
.regwr(regwr),
.distortion(distortion),
.result(ch4res)
);
wire [15:0] ch5res;
AdLibChannel #(5, 10) ch5 (
.clk(clk),
.a(index),
.din(iodin),
.regwr(regwr),
.distortion(distortion),
.result(ch5res)
);
wire [15:0] ch6res;
AdLibChannel #(6, 16) ch6 (
.clk(clk),
.a(index),
.din(iodin),
.regwr(regwr),
.distortion(distortion),
.result(ch6res)
);
wire [15:0] ch7res;
AdLibChannel #(7, 17) ch7 (
.clk(clk),
.a(index),
.din(iodin),
.regwr(regwr),
.distortion(distortion),
.result(ch7res)
);
// Микшер
always @(posedge clk) begin
if (rhythm) result <= ch0res + ch1res + ch2res + ch3res + ch4res + ch5res;
else result <= ch0res + ch1res + ch2res + ch3res + ch4res + ch5res + ch6res + ch7res;
music <= result[18:11];
end
// Регистры
always @(posedge clk) begin
index <= iowr && (port == 12'h388) ? iodin : index;
distortion <= regwr && (index == 8'h01) ? iodin[5] : distortion;
rhythm <= regwr && (index == 8'hBD) ? iodin[5] : rhythm;
end
// Таймеры
always @(posedge clk) begin
timer_div <= timer_div + 14'd1;
timer1 <=
iowr && (port == 12'h389) && (index == 8'h04) && iodin[7] ? 9'd0 :
iowr && (port == 12'h389) && (index == 8'h02) ? {1'b0, iodin} :
timer1_start && (&timer_div[11:0]) && (~timer1[8]) ? timer1 + 9'd1 :
timer1;
timer1_start <=
iowr && (port == 12'h389) && (index == 8'h04) && iodin[6] ? 1'b1 :
timer1_start && timer1[8] ? 1'b0 :
timer1_start;
timer1_mask <= iowr && (port == 12'h389) && (index == 8'h04) ? iodin[6] : timer1_mask;
timer2 <=
iowr && (port == 12'h389) && (index == 8'h04) && iodin[7] ? 9'd0 :
iowr && (port == 12'h389) && (index == 8'h03) ? {1'b0, iodin} :
timer2_start && (&timer_div[13:0]) && (~timer2[8]) ? timer2 + 9'd1 :
timer2;
timer2_start <=
iowr && (port == 12'h389) && (index == 8'h04) && iodin[5] ? 1'b1 :
timer2_start && timer2[8] ? 1'b0 :
timer2_start;
timer2_mask <= iowr && (port == 12'h389) && (index == 8'h04) ? iodin[5] : timer2_mask;
end
endmodule
| 7.101363 |
module AdLibChannel #(
parameter N,
OPN
) (
input wire clk,
input wire [7:0] a,
input wire [7:0] din,
input wire regwr,
input wire distortion,
output reg [15:0] result
);
wire wr_2n = regwr && ({a[7:5], 1'b0} == 4'h2);
wire wr_4n = regwr && ({a[7:5], 1'b0} == 4'h4);
wire wr_6n = regwr && ({a[7:5], 1'b0} == 4'h6);
wire wr_8n = regwr && ({a[7:5], 1'b0} == 4'h8);
wire wr_An = regwr && (a[7:4] == 4'hA);
wire wr_Bn = regwr && (a[7:4] == 4'hB);
wire wr_Cn = regwr && (a[7:4] == 4'hC);
wire wr_En = regwr && ({a[7:5], 1'b0} == 4'hE);
reg algorythm;
wire op1waveneg;
wire [3:0] op1wave;
wire op2waveneg;
wire [3:0] op2wave;
wire oscplay;
AdLibOsc osc (
.clk (clk),
.din (din),
.wr_An(wr_An && (a[3:0] == N)),
.wr_Bn(wr_Bn && (a[3:0] == N)),
.harmonic1(op1harmonic),
.harmonic2(op2harmonic),
.waveform1(op1waveform),
.waveform2(op2waveform),
.neg1 (op1waveneg),
.value1(op1wave),
.neg2 (op2waveneg),
.value2(op2wave),
.play (oscplay)
);
wire [7:0] op1envelope;
wire [3:0] op1harmonic;
wire [1:0] op1waveform;
AdLibOperator op1 (
.clk (clk),
.din (din),
.wr_2n(wr_2n && (a[4:0] == OPN)),
.wr_4n(wr_4n && (a[4:0] == OPN)),
.wr_6n(wr_6n && (a[4:0] == OPN)),
.wr_8n(wr_8n && (a[4:0] == OPN)),
.wr_En(wr_En && (a[4:0] == OPN)),
.play(oscplay),
.harmonic(op1harmonic),
.waveform(op1waveform),
.envelope(op1envelope)
);
wire [7:0] op2envelope;
wire [3:0] op2harmonic;
wire [1:0] op2waveform;
AdLibOperator op2 (
.clk (clk),
.din (din),
.wr_2n(wr_2n && (a[4:0] == (OPN + 3))),
.wr_4n(wr_4n && (a[4:0] == (OPN + 3))),
.wr_6n(wr_6n && (a[4:0] == (OPN + 3))),
.wr_8n(wr_8n && (a[4:0] == (OPN + 3))),
.wr_En(wr_En && (a[4:0] == (OPN + 3))),
.play(oscplay),
.harmonic(op2harmonic),
.waveform(op2waveform),
.envelope(op2envelope)
);
wire [15:0] scaled1;
Mul8 op1mul (
.dataa ({op1wave, 2'b00}),
.datab (op1envelope),
.result(scaled1)
);
wire [15:0] scaled2;
Mul8 op2mul (
.dataa (algorythm ? {op2wave, 2'b00} : {op2wave, 2'b00} + scaled1[13:8]),
.datab (op2envelope),
.result(scaled2)
);
reg [13:0] sc1pos;
reg [13:0] sc1neg;
reg [14:0] sc2pos;
reg [14:0] sc2neg;
always @(posedge clk) begin
if (wr_Cn && (a[3:0] == N)) algorythm <= din[0];
if (algorythm) begin
// op1 + op2
sc1pos <= op1waveneg ? 14'd0 : scaled1[13:0];
sc1neg <= op1waveneg ? scaled1[13:0] : 14'd0;
sc2pos <= op2waveneg ? 15'd0 : scaled2[14:0];
sc2neg <= op2waveneg ? scaled2[14:0] : 15'd0;
end else begin
// op1 модулирует op2
sc1pos <= 14'd0;
sc1neg <= 14'd0;
sc2pos <= op1waveneg ^ op2waveneg ? 15'd0 : scaled2[14:0];
sc2neg <= op1waveneg ^ op2waveneg ? scaled2[14:0] : 15'd0;
end
result <= 16'd32768 + sc1pos - sc1neg + sc2pos - sc2neg;
end
endmodule
| 6.644425 |
module AdLibOperator (
input wire clk,
input wire [7:0] din,
input wire wr_2n,
input wire wr_4n,
input wire wr_6n,
input wire wr_8n,
input wire wr_En,
input wire play,
output reg [3:0] harmonic,
output reg [1:0] waveform,
output reg [7:0] envelope
);
localparam S_IDLE = 3'd0, S_ATTACK = 3'd1, S_DECAY = 3'd2, S_SUSTAIN = 3'd3, S_RELEASE = 3'd4;
reg [3:0] attack;
reg [3:0] decay;
reg [3:0] sustain;
reg [3:0] releas;
reg percussive;
reg [5:0] level;
reg [2:0] state;
reg [15:0] res;
wire [15:0] levelres;
reg [9:0] div;
reg div_overflow;
reg prev_play;
reg play_hit;
reg [21:0] attack_rate;
reg [21:0] decay_rate;
reg [21:0] release_rate;
reg [15:0] sustain_amp;
reg [18:0] steps;
wire [9:0] attack_delta = 10'd511;
wire [8:0] decay_delta = 9'd256;
wire [8:0] release_delta = 9'd256;
wire [16:0] res_attack = res + attack_delta;
wire [16:0] res_decay = res - decay_delta;
Mul8 levelmul (
.dataa (res[15:8]),
.datab ({2'b00, level}),
.result(levelres)
);
always @(posedge clk) begin
if (wr_2n) percussive <= ~din[5];
if (wr_2n) harmonic <= ~|din[3:0] ? 4'd0 : din[3:0] - 4'd1;
if (wr_4n) level <= ~din[5:0];
if (wr_6n) attack <= din[7:4];
if (wr_6n) decay <= din[3:0];
if (wr_8n) sustain <= din[7:4];
if (wr_8n) releas <= din[3:0];
if (wr_En) waveform <= din[1:0];
attack_rate <= 19'd292968 >> attack;
decay_rate <= 22'd2343744 >> decay;
release_rate <= 22'd2343744 >> releas;
sustain_amp <= 16'hFFFF >> sustain;
envelope <= levelres[13:6];
div <= div + 1'd1;
div_overflow <= ÷
prev_play <= play;
play_hit <= (~prev_play) && play;
if (play_hit) begin
state <= S_ATTACK;
res <= 16'd0;
steps <= 12'd0;
end else begin
case (state)
S_IDLE: begin
res <= 16'd0;
steps <= 12'd0;
end
S_ATTACK: begin
if (~play) begin
state <= S_RELEASE;
end else if (res_attack[16]) begin
res <= 16'hFFFF;
steps <= 12'd0;
state <= S_DECAY;
end else begin
if (steps >= attack_rate) begin
res <= res + attack_delta;
steps <= 12'd0;
end else steps <= steps + 1'd1;
end
end
S_DECAY: begin
if ((res_decay <= sustain_amp) || (~play)) begin
res <= sustain_amp;
state <= S_SUSTAIN;
end else begin
if (steps >= decay_rate) begin
res <= res - decay_delta;
steps <= 12'd0;
end else steps <= steps + 1'd1;
end
end
S_SUSTAIN: begin
if (percussive || (~play)) state <= S_RELEASE;
end
S_RELEASE: begin
if (res <= release_delta) begin
res <= 16'd0;
state <= S_IDLE;
end else begin
if (steps >= release_rate) begin
res <= res - release_delta;
steps <= 12'd0;
end else steps <= steps + 1'd1;
end
state <= S_IDLE;
end
default: state <= S_IDLE;
endcase
end
end
endmodule
| 6.722143 |
module AdLibRAM (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [9:0] address_a;
input [9:0] address_b;
input clock;
input [17:0] data_a;
input [17:0] data_b;
input wren_a;
input wren_b;
output [17:0] q_a;
output [17:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [17:0] sub_wire0;
wire [17:0] sub_wire1;
wire [17:0] q_a = sub_wire0[17:0];
wire [17:0] q_b = sub_wire1[17:0];
altsyncram altsyncram_component (
.clock0 (clock),
.wren_a (wren_a),
.address_b (address_b),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 18,
altsyncram_component.width_b = 18,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
| 6.505438 |
module Administrador_de_salidas (
input [2:0] RY,
input [7:0] RX,
input [2:0] Num,
input [1:0] Sel_Salidas,
output reg [7:0] o_Dataout,
output reg [7:0] o_Addressdata,
output reg ReadWrite
);
always @* begin
case (Sel_Salidas)
2'b00: begin
o_Dataout <= 0;
o_Addressdata <= 0;
ReadWrite <= 0;
end
2'b01: begin
o_Dataout <= 0;
o_Addressdata <= {5'b00000, RY};
ReadWrite <= 0;
end
2'b10: begin
o_Dataout <= {5'b00000, Num};
o_Addressdata <= RX;
ReadWrite <= 1;
end
2'b11: begin
o_Dataout <= RX;
o_Addressdata <= RY;
ReadWrite <= 1;
end
default begin
o_Dataout <= 0;
o_Addressdata <= 0;
ReadWrite <= 0;
end
endcase
end
endmodule
| 8.308589 |
module ram_dual_port (
clk,
clken,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteena_a,
byteena_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
parameter numwords_b = 1'd0;
parameter init_file = "UNUSED.mif";
parameter width_be_a = 1'd0;
parameter width_be_b = 1'd0;
parameter latency = 1;
input clk;
input clken;
input [(widthad_a-1):0] address_a;
input [(widthad_b-1):0] address_b;
output wire [(width_a-1):0] q_a;
output wire [(width_b-1):0] q_b;
reg [(width_a-1):0] q_a_wire;
reg [(width_b-1):0] q_b_wire;
input wren_a;
input wren_b;
input [(width_a-1):0] data_a;
input [(width_b-1):0] data_b;
// byte enable is unsupported by inferred RAMs
input [width_be_a-1:0] byteena_a;
input [width_be_b-1:0] byteena_b;
(* ramstyle = "no_rw_check", ram_init_file = init_file *) reg [width_a-1:0] ram[numwords_a-1:0];
/* synthesis translate_off */
integer i;
ALTERA_MF_MEMORY_INITIALIZATION mem ();
reg [8*256:1] ram_ver_file;
initial begin
if (init_file == "UNUSED.mif") begin
for (i = 0; i < numwords_a; i = i + 1) ram[i] = 0;
end else begin
// modelsim can't read .mif files directly. So use Altera function to
// convert them to .ver files
mem.convert_to_ver_file(init_file, width_a, ram_ver_file);
$readmemh(ram_ver_file, ram);
end
end
/* synthesis translate_on */
always @(posedge clk)
if (clken) begin // Port A
if (wren_a) begin
ram[address_a] <= data_a;
q_a_wire <= {width_a{1'bX}};
end else q_a_wire <= ram[address_a];
end
always @(posedge clk)
if (clken) begin // Port b
if (wren_b) begin
ram[address_b] <= data_b;
q_b_wire <= {width_b{1'bX}};
end else q_b_wire <= ram[address_b];
end
integer j;
reg [(width_a-1):0] q_a_reg[latency:1], q_b_reg[latency:1];
always @(*) begin
q_a_reg[1] <= q_a_wire;
q_b_reg[1] <= q_b_wire;
end
always @(posedge clk)
if (clken) begin
for (j = 1; j < latency; j = j + 1) begin
q_a_reg[j+1] <= q_a_reg[j];
q_b_reg[j+1] <= q_b_reg[j];
end
end
assign q_a = (clken) ? q_a_reg[latency] : 0;
assign q_b = (clken) ? q_b_reg[latency] : 0;
endmodule
| 8.296277 |
module rom_dual_port (
clk,
clken,
address_a,
address_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
parameter numwords_b = 1'd0;
parameter init_file = "UNUSED.mif";
parameter latency = 1;
input clk;
input clken;
input [(widthad_a-1):0] address_a;
input [(widthad_b-1):0] address_b;
output wire [(width_a-1):0] q_a;
output wire [(width_b-1):0] q_b;
reg [(width_a-1):0] q_a_wire;
reg [(width_b-1):0] q_b_wire;
(* ramstyle = "no_rw_check", ram_init_file = init_file *) reg [width_a-1:0] ram[numwords_a-1:0];
/* synthesis translate_off */
integer i;
ALTERA_MF_MEMORY_INITIALIZATION mem ();
reg [8*256:1] ram_ver_file;
initial begin
if (init_file == "UNUSED.mif") begin
for (i = 0; i < numwords_a; i = i + 1) ram[i] = 0;
end else begin
// modelsim can't read .mif files directly. So use Altera function to
// convert them to .ver files
mem.convert_to_ver_file(init_file, width_a, ram_ver_file);
$readmemh(ram_ver_file, ram);
end
end
/* synthesis translate_on */
always @(posedge clk)
if (clken) begin
q_a_wire <= ram[address_a];
q_b_wire <= ram[address_b];
end
integer j;
reg [(width_a-1):0] q_a_reg[latency:1], q_b_reg[latency:1];
always @(*) begin
q_a_reg[1] <= q_a_wire;
q_b_reg[1] <= q_b_wire;
end
always @(posedge clk)
if (clken) begin
for (j = 1; j < latency; j = j + 1) begin
q_a_reg[j+1] <= q_a_reg[j];
q_b_reg[j+1] <= q_b_reg[j];
end
end
assign q_a = (clken) ? q_a_reg[latency] : 0;
assign q_b = (clken) ? q_b_reg[latency] : 0;
endmodule
| 7.576841 |
module ML605 (
USER_CLOCK,
KEY,
SW,
LED,
LEDG,
UART_RXD,
UART_TXD
);
input USER_CLOCK;
input [4:0] KEY;
input [7:0] SW;
output [7:0] LED;
output [7:0] LEDG;
wire CLOCK_50;
input UART_RXD;
output UART_TXD;
wire clk = CLOCK_50;
wire go = ~KEY[1];
wire reset = ~KEY[0];
wire start;
wire [31:0] return_val;
reg [31:0] return_val_reg;
wire finish;
wire [3:0] state;
reg [6:0] hex0, hex1, hex2, hex3, hex4, hex5, hex6, hex7;
assign CLOCK_50 = USER_CLOCK;
assign LED = 0;
always @(*) begin
hex7 <= return_val_reg[31:28];
hex6 <= return_val_reg[27:24];
hex5 <= return_val_reg[23:20];
hex4 <= return_val_reg[19:16];
hex3 <= return_val_reg[15:12];
hex2 <= return_val_reg[11:8];
hex1 <= return_val_reg[7:4];
hex0 <= return_val_reg[3:0];
end
assign UART_TXD = 1'b0;
parameter s_WAIT = 3'b001, s_START = 3'b010, s_EXE = 3'b011, s_DONE = 3'b100;
// state registers
reg [3:0] y_Q, Y_D;
assign LEDG[3:0] = y_Q;
// next state
always @(*) begin
case (y_Q)
s_WAIT:
if (go) Y_D = s_START;
else Y_D = y_Q;
s_START: Y_D = s_EXE;
s_EXE:
if (!finish) Y_D = s_EXE;
else Y_D = s_DONE;
s_DONE: Y_D = s_DONE;
default: Y_D = 3'bxxx;
endcase
end
// current state
always @(posedge clk) begin
if (reset) // synchronous clear
y_Q <= s_WAIT;
else y_Q <= Y_D;
end
always @(posedge clk)
if (y_Q == s_EXE && finish) return_val_reg <= return_val;
else if (y_Q == s_DONE) return_val_reg <= return_val_reg;
else return_val_reg <= 0;
assign start = (y_Q == s_START);
top top_inst (
.clk(clk),
.reset(reset),
.finish(finish),
.return_val(return_val),
.start(start)
);
endmodule
| 6.767428 |
module de4 (
OSC_50_BANK2,
BUTTON,
LED,
SEG0_D,
SEG1_D
);
input OSC_50_BANK2;
input [1:0] BUTTON;
output [6:0] SEG0_D;
output [6:0] SEG1_D;
output [7:0] LED;
de2 de2_inst (
.CLOCK_50(OSC_50_BANK2),
.LEDG(LED),
.KEY(BUTTON),
.SW(),
.HEX0(SEG0_D),
.HEX1(SEG1_D),
.HEX2(),
.HEX3(),
.HEX4(),
.HEX5(),
.HEX6(),
.HEX7()
);
endmodule
| 7.073756 |
module de2 (
CLOCK_50,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
LEDG,
UART_RXD,
UART_TXD
);
input CLOCK_50;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
reg [6:0] hex0, hex1, hex2, hex3, hex4, hex5, hex6, hex7;
output [7:0] LEDG;
input UART_RXD;
output UART_TXD;
wire clk = CLOCK_50;
wire go = ~KEY[1];
wire reset = ~KEY[0];
wire start;
wire [31:0] return_val;
reg [31:0] return_val_reg;
wire finish;
wire [3:0] state;
hex_digits h7 (
.x(hex7),
.hex_LEDs(HEX7)
);
hex_digits h6 (
.x(hex6),
.hex_LEDs(HEX6)
);
hex_digits h5 (
.x(hex5),
.hex_LEDs(HEX5)
);
hex_digits h4 (
.x(hex4),
.hex_LEDs(HEX4)
);
hex_digits h3 (
.x(hex3),
.hex_LEDs(HEX3)
);
hex_digits h2 (
.x(hex2),
.hex_LEDs(HEX2)
);
hex_digits h1 (
.x(hex1),
.hex_LEDs(HEX1)
);
hex_digits h0 (
.x(hex0),
.hex_LEDs(HEX0)
);
always @(*) begin
hex7 <= return_val_reg[31:28];
hex6 <= return_val_reg[27:24];
hex5 <= return_val_reg[23:20];
hex4 <= return_val_reg[19:16];
hex3 <= return_val_reg[15:12];
hex2 <= return_val_reg[11:8];
hex1 <= return_val_reg[7:4];
hex0 <= return_val_reg[3:0];
end
assign UART_TXD = 1'b0;
parameter s_WAIT = 3'b001, s_START = 3'b010, s_EXE = 3'b011, s_DONE = 3'b100;
// state registers
reg [3:0] y_Q, Y_D;
assign LEDG[3:0] = y_Q;
// next state
always @(*) begin
case (y_Q)
s_WAIT:
if (go) Y_D = s_START;
else Y_D = y_Q;
s_START: Y_D = s_EXE;
s_EXE:
if (!finish) Y_D = s_EXE;
else Y_D = s_DONE;
s_DONE: Y_D = s_DONE;
default: Y_D = 3'bxxx;
endcase
end
// current state
always @(posedge clk) begin
if (reset) // synchronous clear
y_Q <= s_WAIT;
else y_Q <= Y_D;
end
always @(posedge clk)
if (y_Q == s_EXE && finish) return_val_reg <= return_val;
else if (y_Q == s_DONE) return_val_reg <= return_val_reg;
else return_val_reg <= 0;
assign start = (y_Q == s_START);
top top_inst (
.clk(clk),
.reset(reset),
.finish(finish),
.return_val(return_val),
.start(start)
);
endmodule
| 7.759103 |
module adpcm_decoder (
input reset,
input clock,
input [ 3:0] in_pcm,
output reg signed [11:0] sample
);
reg signed [11:0] differential_value;
reg signed [6:0] index, delta;
reg [10:0] step, pr_step;
reg [15:0] pcm;
wire signed [11:0] estimation = pcm[15] ? sample + differential_value : sample - differential_value;
always @(posedge clock) begin
if (reset) begin
delta <= 7'd0;
sample <= 12'd0;
differential_value <= 12'd0;
index <= 7'd0;
step <= 11'd0;
pr_step <= 11'd0;
pcm <= 16'd0;
end else begin
pcm <= {pcm[11:0], in_pcm[3:0]};
pr_step <= step;
case (in_pcm[2:0])
3'b000: delta <= -7'd1;
3'b001: delta <= -7'd1;
3'b010: delta <= -7'd1;
3'b011: delta <= -7'd1;
3'b100: delta <= 7'd2;
3'b101: delta <= 7'd4;
3'b110: delta <= 7'd6;
3'b111: delta <= 7'd8;
endcase
if (index + delta < 0) index <= 0;
else if (index + delta > 48) index <= 48;
else index <= index + delta;
case (index)
7'd00: step <= 11'd16;
7'd01: step <= 11'd17;
7'd02: step <= 11'd19;
7'd03: step <= 11'd21;
7'd04: step <= 11'd23;
7'd05: step <= 11'd25;
7'd06: step <= 11'd28;
7'd07: step <= 11'd31;
7'd08: step <= 11'd34;
7'd09: step <= 11'd37;
7'd10: step <= 11'd41;
7'd11: step <= 11'd45;
7'd12: step <= 11'd50;
7'd13: step <= 11'd55;
7'd14: step <= 11'd60;
7'd15: step <= 11'd66;
7'd16: step <= 11'd73;
7'd17: step <= 11'd80;
7'd18: step <= 11'd88;
7'd19: step <= 11'd97;
7'd20: step <= 11'd107;
7'd21: step <= 11'd118;
7'd22: step <= 11'd130;
7'd23: step <= 11'd143;
7'd24: step <= 11'd157;
7'd25: step <= 11'd173;
7'd26: step <= 11'd190;
7'd27: step <= 11'd209;
7'd28: step <= 11'd230;
7'd29: step <= 11'd253;
7'd30: step <= 11'd279;
7'd31: step <= 11'd307;
7'd32: step <= 11'd337;
7'd33: step <= 11'd371;
7'd34: step <= 11'd408;
7'd35: step <= 11'd449;
7'd36: step <= 11'd494;
7'd37: step <= 11'd544;
7'd38: step <= 11'd598;
7'd39: step <= 11'd658;
7'd40: step <= 11'd724;
7'd41: step <= 11'd796;
7'd42: step <= 11'd876;
7'd43: step <= 11'd963;
7'd44: step <= 11'd1060;
7'd45: step <= 11'd1166;
7'd46: step <= 11'd1282;
7'd47: step <= 11'd1411;
7'd48: step <= 11'd1552;
default: step <= 11'd1552;
endcase
differential_value <= {pcm[10] ? pr_step : 12'd0} + {pcm[9] ? (pr_step>>1) : 12'd0} + {pcm[8] ? (pr_step>>2) : 12'd0} + (pr_step>>3);
if ($signed(estimation) > $signed(2047)) sample <= 12'd2047;
else if ($signed(estimation) < $signed(-2048)) sample <= -12'd2048;
else sample <= estimation;
end
end
endmodule
| 6.977394 |
module ADPLL #(
parameter ACCUM_WIDTH = 12,
parameter PDET_WITH = 8,
parameter BIAS = 12'd76, //biased to 5 MHZ @ 258 MHZ CLOCK
parameter DCO_CC_WIDTH = 9,
//LoopFilter Settings
parameter DYNAMIC_VAL = 0, //set to allow variable control of the filter gains with ki/p_i
parameter ERROR_WIDTH = 8,
parameter KP_WIDTH = 3,
parameter KP_FRAC_WIDTH = 1,
parameter KP = 3'b010,
parameter KI_WIDTH = 4,
parameter KI_FRAC_WIDTH = 3,
parameter KI = 4'b0001
) (
input wire reset_i, //reset high
input wire fpga_clk_i,
input wire ref_clk_i,
input wire enable_i,
input wire [KP_WIDTH-1:0] kp_i,
input wire [KI_WIDTH-1:0] ki_i,
output wire gen_clk_o,
output wire gen_div8_o,
output wire signed [PDET_WITH-1:0] error_o,
output wire signed [DCO_CC_WIDTH-1:0] dco_cc_o
);
/*************************************************************************/
/* Define constants and nets */
/*************************************************************************/
localparam PADDING_WIDTH = ACCUM_WIDTH - DCO_CC_WIDTH;
wire [ACCUM_WIDTH-1:0] f_sel_sw_pa_x; //TODO
wire gen_clk_x;
wire gen_div8_x;
wire signed [PDET_WITH-1:0] error_x;
assign gen_clk_o = gen_clk_x;
assign gen_div8_o = gen_div8_x;
assign error_o = error_x;
/*************************************************************************/
/* Module instantiation */
/*************************************************************************/
PhaseAccum #(
.WIDTH(ACCUM_WIDTH)
) testOsc (
.enable_i(enable_i),
.reset_i(reset_i),
.fpga_clk_i(fpga_clk_i),
.clk_o(gen_clk_x),
.k_val_i(f_sel_sw_pa_x)
);
Div8 div8 (
.reset_i (reset_i),
.signal_i(gen_clk_x),
.div8_o (gen_div8_x)
);
PhaseDetector #(
.WIDTH(PDET_WITH)
) testPDet (
.reset_i(reset_i),
.fpga_clk_i(fpga_clk_i),
.reference_i(ref_clk_i),
.generated_i(gen_div8_x),
.pd_clock_cycles_o(error_x)
);
LoopFilter #(
.ERROR_WIDTH(ERROR_WIDTH),
.DCO_CC_WIDTH(DCO_CC_WIDTH),
.KP_WIDTH(KP_WIDTH),
.KP_FRAC_WIDTH(KP_FRAC_WIDTH),
.KP(KP),
.KI_WIDTH(KI_WIDTH),
.KI_FRAC_WIDTH(KI_FRAC_WIDTH),
.KI(KI),
.DYNAMIC_VAL(DYNAMIC_VAL)
) loopFilter (
.gen_clk_i(gen_clk_x),
.reset_i(reset_i),
.error_i(error_x),
.kp_i(kp_i),
.ki_i(ki_i),
.dco_cc_o(dco_cc_o)
);
//add control code to the bias
assign f_sel_sw_pa_x = BIAS + $signed({{(PADDING_WIDTH) {dco_cc_o[DCO_CC_WIDTH-1]}}, dco_cc_o});
endmodule
| 6.67463 |
module ADPLLwNoPDet #(
parameter ACCUM_WIDTH = 12,
parameter PDET_WITH = 8,
parameter BIAS = 12'd76, //5 MHZ @ 258 MHZ CLOCK
parameter DCO_CC_WIDTH = 9,
//LoopFilter
parameter DYNAMIC_VAL = 0,
parameter ERROR_WIDTH = 8,
parameter KP_WIDTH = 3,
parameter KP_FRAC_WIDTH = 1,
parameter KP = 3'b010,
parameter KI_WIDTH = 4,
parameter KI_FRAC_WIDTH = 3,
parameter KI = 4'b0001
) (
input wire reset_i,
input wire fpga_clk_i,
input wire [PDET_WITH-1:0] error_top_x,
input wire [PDET_WITH-1:0] error_right_x,
input wire [PDET_WITH-1:0] error_bottom_x,
input wire [PDET_WITH-1:0] error_left_x,
input wire ref_clk_i,
input wire enable_i,
input wire [KP_WIDTH-1:0] kp_i,
input wire [KI_WIDTH-1:0] ki_i,
output wire gen_clk_o,
output wire gen_div8_o,
output wire signed [PDET_WITH-1:0] error_o,
output wire signed [DCO_CC_WIDTH-1:0] dco_cc_o
);
localparam PADDING_WIDTH = ACCUM_WIDTH - DCO_CC_WIDTH;
wire [ACCUM_WIDTH-1:0] f_sel_sw_pa_x; //TODO
wire gen_clk_x;
wire gen_div8_x;
wire signed [PDET_WITH-1:0] error_x;
assign gen_clk_o = gen_clk_x;
assign gen_div8_o = gen_div8_x;
assign error_o = error_x;
/*
PhaseDetector #(.WIDTH(PDET_WITH)) testPDet (
.reset_i(reset_i),
.fpga_clk_i(fpga_clk_i),
.reference_i(ref_clk_i),
.generated_i(gen_div8_x),
.pd_clock_cycles_o(error_x)
);
*/
ErrorCombiner errorCombiner ( //zero out unconnected, 2 weight on others
.reset_i(reset_x),
.weight_0_i(3'd0),
.weight_1_i(3'b010),
.weight_2_i(3'd0),
.weight_3_i(3'b010),
.error_0_i(error_top_x),
.error_1_i(error_right_x),
.error_2_i(error_bottom_x),
.error_3_i(error_left_x),
.error_comb_o(error_x)
);
LoopFilter #(
.ERROR_WIDTH(ERROR_WIDTH),
.DCO_CC_WIDTH(DCO_CC_WIDTH),
.KP_WIDTH(KP_WIDTH),
.KP_FRAC_WIDTH(),
.KP(KP),
.KI_WIDTH(KI_WIDTH),
.KI_FRAC_WIDTH(KI_FRAC_WIDTH),
.KI(KI),
.DYNAMIC_VAL(DYNAMIC_VAL)
) loopFilter (
.gen_clk_i(gen_clk_x),
.reset_i(reset_i),
.error_i(error_x),
.kp_i(kp_i),
.ki_i(ki_i),
.dco_cc_o(dco_cc_o)
);
PhaseAccum #(
.WIDTH(ACCUM_WIDTH)
) testOsc (
.enable_i(enable_i),
.reset_i(reset_i),
.fpga_clk_i(fpga_clk_i),
.clk_o(gen_clk_x),
.k_val_i(f_sel_sw_pa_x)
);
Div8 div8 (
.reset_i (reset_i),
.signal_i(gen_clk_x),
.div8_o (gen_div8_x)
);
//assign f_sel_sw_pa_x = BIAS;
assign f_sel_sw_pa_x = BIAS + $signed({{(PADDING_WIDTH) {dco_cc_o[DCO_CC_WIDTH-1]}}, dco_cc_o});
endmodule
| 7.16618 |
module shift #(
parameter LENGTH = 16
) (
input clk,
input in,
input [LENGTH-1:0] cmp,
output out
);
reg [LENGTH-1:0] shift_reg;
always @(posedge clk) shift_reg <= {in, shift_reg[LENGTH-1:1]};
assign out = (shift_reg == cmp);
endmodule
| 8.179253 |
module ADPOR #(
parameter LENGTH = 16
) (
input clk,
output rst_n
);
wire cmp1, cmp2, cmp3, cmp4;
shift reg1 (
.clk(clk),
.in (1'b1),
.cmp({LENGTH{1'b1}}),
.out(cmp1)
);
shift reg2 (
.clk(clk),
.in (1'b0),
.cmp({LENGTH{1'b0}}),
.out(cmp2)
);
shift reg3 (
.clk(clk),
.in (1'b1),
.cmp({LENGTH{1'b1}}),
.out(cmp3)
);
shift reg4 (
.clk(clk),
.in (1'b0),
.cmp({LENGTH{1'b0}}),
.out(cmp4)
);
assign rst_n = cmp1 & cmp2 & cmp3 & cmp4;
endmodule
| 7.060885 |
module ADPOR_tb;
reg clk;
wire rst_n;
always #5 clk = !clk;
ADPOR MUV (
.clk (clk),
.rst_n(rst_n)
);
initial begin
$dumpfile("adpor.vcd");
$dumpvars;
clk = 0;
// load shift registers with random data to simulate the power on behavior
force MUV.reg1.shift_reg = $urandom & 12'hFFF;
force MUV.reg2.shift_reg = $urandom & 12'hFFF;
force MUV.reg3.shift_reg = $urandom & 12'hFFF;
force MUV.reg4.shift_reg = $urandom & 12'hFFF;
#1;
release MUV.reg1.shift_reg;
release MUV.reg2.shift_reg;
release MUV.reg3.shift_reg;
release MUV.reg4.shift_reg;
#500 $finish;
end
endmodule
| 7.307759 |
module ADR (
input CLK,
input [31:0] DataIn,
output reg [31:0] DataOut
);
always @(negedge CLK) DataOut <= DataIn;
endmodule
| 7.329619 |
module addr_norm (
normo,
pcv
);
input [6:0] pcv;
output [6:0] normo;
reg [6:0] ooo;
always @(pcv) begin
ooo <= pcv + 1;
end
assign normo = ooo;
endmodule
| 6.745003 |
module SigGen (
input wire [5:0] clk64
, output wire out
);
parameter TRESHHOLD = 19;
assign out = clk64 <= TRESHHOLD;
endmodule
| 7.541408 |
module linetransmitter (
input clk
, input rst
, input [ADD_WIDTH:0] pixel_count
, input [23:0] pixel
, output [ADD_WIDTH - 1:0] address
, output out
, output done
);
parameter ADD_WIDTH = 8;
localparam RESET = 3'b1xx, DATA_SENDING = 3'b000, RESET_SENDING = 3'b010;
reg [ADD_WIDTH - 1:0] addressReg;
reg [ADD_WIDTH:0] sentCnt;
reg [11:0] resetCnt;
reg acquiring;
reg [5:0] clk64;
reg readyp;
reg reset;
reg wasreset;
reg [4:0] bitsLeft;
reg fin;
wire dataSent;
wire resetDone;
wire [2:0] state;
wire startPos;
wire ready;
wire pixout;
wire pos;
wire neg;
assign dataSent = sentCnt - 1 == pixel_count;
assign resetDone = resetCnt == 12'd2750;
assign state = {rst, dataSent, resetDone};
assign startPos = clk64 == 0;
assign address = addressReg;
assign out = dataSent ? 0 : (fin ? 0 : pixout);
assign done = resetDone;
always @(posedge clk) begin
acquiring <= ~ready;
if (~rst) begin
clk64 <= clk64 + 1'b1;
end
if (reset) begin
reset <= 0;
end
casex (state)
RESET: begin
clk64 <= 0;
resetCnt <= 0;
addressReg <= 0;
sentCnt <= 0;
readyp <= 0;
reset <= 1;
end
DATA_SENDING: begin
if (ready && acquiring) begin
addressReg <= addressReg + 1'b1;
sentCnt <= sentCnt + 1'b1;
end
if (sentCnt == pixel_count & startPos) begin
if (bitsLeft > 0) begin
bitsLeft <= bitsLeft - 1;
end
end else if (sentCnt < pixel_count) begin
bitsLeft <= 23;
fin <= 0;
end else if (~fin) begin
fin <= (bitsLeft == 0) && (clk64 > 60);
end
end
RESET_SENDING: begin
if (ready) begin
resetCnt <= resetCnt + 1'b1;
end
end
endcase
end
SigGen #(19) pg (
.clk64(clk64),
.out (neg)
);
SigGen #(42) ng (
.clk64(clk64),
.out (pos)
);
PixLineTransmitter pt (
.rst(reset),
.clk(clk),
.go(1'b1),
.signalPos(pos),
.signalNeg(neg),
.cnt64(clk64),
.pixel(pixel),
.out(pixout),
.ready(ready)
);
endmodule
| 7.263059 |
module Adress_Generator (
input rst,
input clk,
input PCSrcE,
input StallF,
input [31:0] PCPlus4F,
input [31:0] PCTargetE,
output reg [31:0] PCF
);
reg [31:0] PCFbar;
always @(*) begin //combinational block so block assignment (=) and not a non-blocking one (<=)
PCFbar = PCSrcE ? PCTargetE : PCF + 4;
end
always @(posedge clk) begin //sequential block so non-block assigment (<=) is used
if (rst) begin
PCF <= 32'd0;
end else if (StallF) begin
PCF <= PCF;
end else begin
PCF <= PCFbar;
end
end
endmodule
| 7.73958 |
module adrsExtend (
ads,
extendedads
);
input [6:0] ads;
output [7:0] extendedads;
assign extendedads[6:0] = ads[6:0];
assign extendedads[7] = 0;
endmodule
| 7.566853 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module adrv9001_aligner4 (
input clk,
input [3:0] idata,
input ivalid,
input [3:0] strobe,
output reg [3:0] odata,
output ovalid
);
reg [3:0] idata_d = 'b0;
reg ivalid_d = 'b0;
always @(posedge clk) begin
if (ivalid) begin
idata_d <= idata;
end
ivalid_d <= ivalid;
end
reg [1:0] phase = 'h0;
always @(posedge clk) begin
if (ivalid) begin
if ((strobe != 'b1111) && (strobe != 'b0000)) begin
casex (strobe)
'b1xxx : phase <= 0;
'b01xx : phase <= 1;
'b001x : phase <= 2;
'b0001 : phase <= 3;
default : phase <= phase;
endcase
end
end
end
always @(posedge clk) begin
case (phase)
0 : odata <= idata_d;
1 : odata <= {idata_d[2:0],idata[3:3]};
2 : odata <= {idata_d[1:0],idata[3:2]};
3 : odata <= {idata_d[0:0],idata[3:1]};
endcase
end
assign ovalid = ivalid_d;
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module adrv9001_aligner8 (
input clk,
input [7:0] idata,
input ivalid,
input [7:0] strobe,
output reg [7:0] odata,
output ovalid
);
reg [7:0] idata_d = 'b0;
reg ivalid_d = 'b0;
always @(posedge clk) begin
if (ivalid) begin
idata_d <= idata;
end
ivalid_d <= ivalid;
end
reg [2:0] phase = 'h0;
always @(posedge clk) begin
if (ivalid) begin
if ((strobe != 'b1111_1111) && (strobe != 'b0000_0000)) begin
casex (strobe)
'b1xxx_xxxx : phase <= 0;
'b01xx_xxxx : phase <= 1;
'b001x_xxxx : phase <= 2;
'b0001_xxxx : phase <= 3;
'b0000_1xxx : phase <= 4;
'b0000_01xx : phase <= 5;
'b0000_001x : phase <= 6;
'b0000_0001 : phase <= 7;
default : phase <= phase;
endcase
end
end
end
always @(posedge clk) begin
case (phase)
0 : odata <= idata_d;
1 : odata <= {idata_d[6:0],idata[7:7]};
2 : odata <= {idata_d[5:0],idata[7:6]};
3 : odata <= {idata_d[4:0],idata[7:5]};
4 : odata <= {idata_d[3:0],idata[7:4]};
5 : odata <= {idata_d[2:0],idata[7:3]};
6 : odata <= {idata_d[1:0],idata[7:2]};
7 : odata <= {idata_d[0:0],idata[7:1]};
endcase
end
assign ovalid = ivalid_d;
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
//
// Pack two input beats into one and align it based on start of frame
//
// Frame size 2 beats:
// Temporal ordering of input:
// idata : MS Beat, LS Beat, MS Beat, LS Beat, ...
// sof : 1, 0, 1, 0, ...
// Format of output beats: {MS Beat, LS Beat}
//
// Frame size 4 beats:
// Temporal ordering of input:
// idata : MS Beat, LS Beat, MS Beat, LS Beat, MS Beat, LS Beat, ...
// sof : 1, 0, 0, 0, 1, 0, ...
module adrv9001_pack #(
parameter WIDTH = 8
)(
input clk, // Input clock
input sof, // Start of frame indicator marking the MS Beat
input [WIDTH-1:0] idata, // Input data beat
input ivalid, // Input data qualifier
output reg [WIDTH*2-1:0] odata, // Output data beat
output reg ovalid, // Output data qualifier
output reg osof // Output Start of frame indicator
);
reg [WIDTH-1:0] idata_d = {WIDTH{1'b0}};
always @(posedge clk) begin
if (ivalid) begin
idata_d <= idata;
end
end
// Single clock mode:
reg [6:0] sof_d = 7'b000;
// Use sof_d[2] for frame size of 4 beats
// Use sof_d[4,6] for frame size of 8 beats
always @(posedge clk) begin
if (ivalid) begin
sof_d <= {sof_d[5:0],sof};
end
if (ivalid &(sof_d[0] | sof_d[2] | sof_d[4] | sof_d[6])) begin
odata <= {idata_d,idata};
end
ovalid <= ivalid & (sof_d[0] | sof_d[2] | sof_d[4] | sof_d[6]);
osof <= ivalid & sof_d[0];
end
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module adrv9009zu11eg_spi (
input [ 7:0] spi_csn,
input spi_clk,
input spi_mosi,
input spi_miso_i,
output spi_miso_o,
inout spi_sdio);
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
wire spi_miso_io;
// check on rising edge and change on falling edge
assign spi_csn_s = & spi_csn;
assign spi_enable_s = spi_enable & (~spi_csn[2] | ~spi_csn[3]);
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io buffer
IOBUF i_iobuf_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_miso_io),
.IO (spi_sdio));
assign spi_miso_o = spi_enable_s ? spi_miso_io : spi_miso_i;
endmodule
| 8.180735 |
module ADR_DAT_BL (
input BTN,
output wire [1:0] VEL,
output wire [7:0] ADR,
output wire [22:0] DAT
);
wire [4:0] my_nom = 5'b01000; //5'b01000=8 ;
assign ADR = {3'b100, my_nom};
parameter my_dat = 23'h4C6600;
parameter my_VEL = 2'b01; // 50 kBod
wire my_bit_dat = (my_dat[13] ^ BTN);
assign DAT = {my_dat[22:14], my_bit_dat, my_dat[12:0]};
assign VEL = my_VEL;
endmodule
| 6.643285 |
module ADR_maker (
in_Clock,
A,
ART,
ARG,
AWT,
AWG,
TOG_inc,
SEL,
dout,
QUAD_inc,
QUAD_out,
QUAD_Z
);
input in_Clock;
wire clk;
input wire [7:0] A;
input wire [7:0] ART;
input wire [7:0] ARG;
input wire [7:0] AWT;
input wire [7:0] AWG;
input wire TOG_inc;
reg TOG = 0;
input wire [2:0] SEL;
output reg [17:0] dout = 18'd0;
input wire QUAD_inc; //QUAD is inside the address maker.
output reg [1:0] QUAD_out = 2'd0;
output reg QUAD_Z = 1;
pll mypll (
.inclk0(in_Clock),
.c0(clk)
);
//assign clk=in_Clock;
always @ (QUAD_out) //Update Z output
begin
if (QUAD_out == 2'b0) QUAD_Z <= 1;
else QUAD_Z <= 0;
end
always @ (negedge clk) //Control signals given in posedge, we check them in negedge
begin
if(QUAD_inc) //Increment Quad
begin
QUAD_out <= QUAD_out + 1;
end
if(TOG_inc) //Toggle
begin
TOG <= ~TOG;
end
case (SEL)
`adr_matrix_r: //MDAR is formed by read registers
begin
if (TOG == 0) begin
dout <= {QUAD_out[1], ARG, QUAD_out[0], ART};
end else begin
dout <= {QUAD_out[1], ART, QUAD_out[0], ARG};
end
end
`adr_matrix_w: //MDAR is formed by write registers
begin
if (TOG == 0) begin
dout <= {QUAD_out[1], AWG, QUAD_out[0], AWT};
end else begin
dout <= {QUAD_out[1], AWT, QUAD_out[0], AWG};
end
end
`adr_last8: //MDAR, last 8 is filled by A
begin
dout[7:0] <= A;
end
`adr_mid8: //MDAR, mid 8 is filled by A
begin
dout[15:8] <= A;
end
`adr_first2: //MDAR, first 8 is filled by A
begin
dout[17:16] <= A[1:0];
end
endcase
end
endmodule
| 6.948571 |
module adr_MUX2 (
input [5:0] pcadr,
input [31:0] aluout,
input iord,
output reg [31:0] adr
);
always @(*)
if (iord) adr <= aluout;
else adr <= {24'h000000, pcadr, 2'b00};
endmodule
| 6.762896 |
module ADS1201 (
input nReset,
input Clk, // max 8 MHz
input Sync,
output reg [23:0] Output,
output ADC_Clk,
input ADC_Data
);
//----------------------------------------------------------------------------
reg Data;
reg [23:0] Sum [7:0];
reg [ 2:0] Part;
reg [ 2:0] pPart;
reg [ 8:0] Address;
reg [ 8:0] FIR_Address;
wire [15:0] FIR_Data;
reg [23:0] Result;
reg [23:0] tOutput;
reg [ 1:0] pSync;
//----------------------------------------------------------------------------
integer j;
//----------------------------------------------------------------------------
ADS1201_FIR FIR (
.clock (!Clk),
.address(FIR_Address),
.q (FIR_Data)
);
//----------------------------------------------------------------------------
always @* begin
if (Data) begin
Result <= Sum[pPart] + {{8{FIR_Data[15]}}, FIR_Data};
end else begin
Result <= Sum[pPart] - {{8{FIR_Data[15]}}, FIR_Data};
end
end
//----------------------------------------------------------------------------
always @(negedge nReset, posedge Clk) begin
if (!nReset) begin
Data <= 0;
Part <= 0;
Address <= 0;
FIR_Address <= 0;
tOutput <= 0;
Output <= 0;
pSync <= 0;
for (j = 0; j < 8; j = j + 1) begin
Sum[j] <= 0;
end
//----------------------------------------------------------------------------
end else begin
pSync <= {pSync[0], Sync};
if (pSync == 2'b01) begin
Output <= tOutput;
end
//------------------------------------------------------------------------------
if (~|Part) begin
Data <= ADC_Data;
Address <= Address + 1'b1;
FIR_Address <= Address + 1'b1;
end else begin
FIR_Address <= Address + {Part, 6'b0};
end
pPart <= Part;
Part <= Part + 1'b1;
//----------------------------------------------------------------------------
if (&FIR_Address) begin
tOutput <= Result;
Sum[pPart] <= 0;
end else begin
Sum[pPart] <= Result;
end
end
end
//----------------------------------------------------------------------------
assign ADC_Clk = Part[2];
endmodule
| 6.508644 |
module ADS1256_SPI (
input clk,
rst_n,
input go,
input [23:0] wrdat,
output reg [23:0] rddat,
output reg ok,
output reg mosi,
output sclk,
input miso
);
reg [4:0] i;
always @(posedge clk or negedge rst_n)
if (!rst_n) i <= 5'd0;
else if (!go) i <= 5'd0;
else if (i < 5'd31) i <= i + 1'b1;
reg [23:0] r_wrdat;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
r_wrdat <= 24'd0;
mosi <= 1'b0;
end else begin
case (i)
5'd0: begin
r_wrdat <= wrdat;
mosi <= 1'b0;
end
5'd1: mosi <= r_wrdat[23];
5'd2: mosi <= r_wrdat[22];
5'd3: mosi <= r_wrdat[21];
5'd4: mosi <= r_wrdat[20];
5'd5: mosi <= r_wrdat[19];
5'd6: mosi <= r_wrdat[18];
5'd7: mosi <= r_wrdat[17];
5'd8: mosi <= r_wrdat[16];
5'd9: mosi <= r_wrdat[15];
5'd10: mosi <= r_wrdat[14];
5'd11: mosi <= r_wrdat[13];
5'd12: mosi <= r_wrdat[12];
5'd13: mosi <= r_wrdat[11];
5'd14: mosi <= r_wrdat[10];
5'd15: mosi <= r_wrdat[9];
5'd16: mosi <= r_wrdat[8];
5'd17: mosi <= r_wrdat[7];
5'd18: mosi <= r_wrdat[6];
5'd19: mosi <= r_wrdat[5];
5'd20: mosi <= r_wrdat[4];
5'd21: mosi <= r_wrdat[3];
5'd22: mosi <= r_wrdat[2];
5'd23: mosi <= r_wrdat[1];
5'd24: mosi <= r_wrdat[0];
default: mosi <= 1'b0;
endcase
end
reg [23:0] r_rddat;
reg cke;
always @(negedge clk or negedge rst_n)
if (!rst_n) begin
r_rddat <= 24'd0;
cke <= 1'b0;
ok <= 1'b0;
end else begin
case (i)
5'd0: begin
cke <= 1'b0;
ok <= 1'b0;
end
5'd1: cke <= 1'b1;
5'd2: r_rddat[23] <= miso;
5'd3: r_rddat[22] <= miso;
5'd4: r_rddat[21] <= miso;
5'd5: r_rddat[20] <= miso;
5'd6: r_rddat[19] <= miso;
5'd7: r_rddat[18] <= miso;
5'd8: r_rddat[17] <= miso;
5'd9: r_rddat[16] <= miso;
5'd10: r_rddat[15] <= miso;
5'd11: r_rddat[14] <= miso;
5'd12: r_rddat[13] <= miso;
5'd13: r_rddat[12] <= miso;
5'd14: r_rddat[11] <= miso;
5'd15: r_rddat[10] <= miso;
5'd16: r_rddat[9] <= miso;
5'd17: r_rddat[8] <= miso;
5'd18: r_rddat[7] <= miso;
5'd19: r_rddat[6] <= miso;
5'd20: r_rddat[5] <= miso;
5'd21: r_rddat[4] <= miso;
5'd22: r_rddat[3] <= miso;
5'd23: r_rddat[2] <= miso;
5'd24: r_rddat[1] <= miso;
5'd25: begin
r_rddat[0] <= miso;
cke <= 1'b0;
end
5'd26: begin
rddat <= r_rddat;
ok <= 1'b1;
end
default: ;
endcase
end
assign sclk = cke & clk;
endmodule
| 7.387249 |
module ads7816 (
input data, //from ad
input clk, //from controller
input rst, //from controller
input convert, //from controller
output flag, //to controller
output wire dclock, //to ad
output reg cs, //to ad
output reg [11:0] ad_out
); //to controller
//convert posedge->cs negedge
parameter count_end_time = 4'd13;
assign dclock = clk;
//cs
reg temp_convert;
always @(posedge clk or posedge rst) begin
if (rst) cs <= 1;
else begin
if (temp_convert != convert) cs <= 0; //when convert posedge,pull down cs
else if (clk_count == count_end_time) cs <= 1; //when convert finish,pull up cs
temp_convert <= convert;
end
end
//data the forth to the fifth clk posedge is available
//ad_out flag
reg [3:0] clk_count;
always @(posedge clk or posedge rst) begin
if (rst) clk_count <= 4'b0;
else if (clk_count == count_end_time) clk_count <= 4'd0;
else if (cs == 0) clk_count <= clk_count + 4'b1;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
ad_out <= 12'h0;
end else if (cs == 0) ad_out <= {ad_out[10:0], data};
end
// //test
// always@(posedge clk or posedge rst)
// begin
// if(rst)
// ad_out<=12'h0;
// else if(ad_out==12'hFFF)
// ad_out<=12'h0;
// else ad_out<=ad_out+12'h1;
// end
// always@(posedge clk or posedge rst )
// begin
// if(rst)
// flag<=0;
// else if(clk_count==count_end_time)
// flag<=1;
// else if(cs==0)
// flag<=0;
// end
assign flag = cs;
endmodule
| 6.611652 |
module ads7883 (
input wire clk,
input wire en,
output reg cs,
output reg sck,
input wire sdo,
output reg [11:0] data,
output adc_idle
);
reg [1:0] cnt4 = 2'd0;
reg [3:0] cnt16 = 4'd0;
reg [11:0] data_ = 12'd0;
reg sample_state = 1'b0;
assign adc_idle = sample_state;
always @(posedge clk) begin
if (en) begin
cs <= 1'b0;
cnt4 <= 2'b0;
cnt16 <= 4'b0;
sample_state <= 1'b1;
end else begin
if (~cs) cnt4 <= cnt4 + 1'b1;
else cnt4 <= 2'b0;
if (cnt4 == 2'd1) begin
sck <= 1'b0;
data_ <= {data_[10:0], sdo};
end else if (cnt4 == 2'd3) begin
sck <= 1'b1;
if (cnt16 < 4'd15) begin
if (cnt16 == 4'd13) begin
data <= data_;
end
cnt16 <= cnt16 + 1'b1;
end else begin
cs <= 1'b1;
sample_state <= 1'b0;
end
end
end
end
endmodule
| 6.785983 |
module ads7883 (
input wire clk,
input wire en,
output reg cs,
output reg sck,
input wire sdo,
output reg [11:0] data
//output adc_idle
);
reg [ 3:0] cnt16 = 4'd0;
reg [11:0] data_ = 12'd0;
always @(posedge clk) begin
if (en) begin
cs <= 1'b0;
cnt16 <= 4'd0;
sck <= 1'b1;
end else begin
if (~cs) begin
sck <= ~sck;
if (sck) begin
data_ <= {data_[10:0], sdo};
cnt16 <= cnt16 + 1'b1;
end else begin
if (cnt16 == 4'd14) data <= data_;
if (cnt16 == 4'd0) cs <= 1'b1;
end
end else begin
cnt16 <= 4'd0;
sck <= 1'b1;
end
end
end
endmodule
| 6.785983 |
module ads8332_cfg (
input sys_rest,
input spi_clk,
input ads_start,
input [31:0] ads_in_data,
input ads_data_valid,
input ads_wr_en,
input [ 7:0] ads_cfg_rddr,
output [31:0] ads_rd_parameter,
output ads_out_valid,
input ads8332_spi_start,
output wire ads_spi_clk,
output wire ads_spi_cs,
output wire ads_spi_sdi,
input ads_spi_sdo,
output [63:0] ads_debug
);
//////////////////////////////////////////////////////////////////////////////////
//// signal declaration ////
wire [ 6:0] ads8332_count;
wire [31:0] spi_data_out;
wire spi_data_valid;
//////////////////////////////////////////////////////////////////////////////////
//// parameter ////
parameter START_NUMBER = 7'd1;
parameter CS_LENGTH = 7'd32;
//////////////////////////////////////////////////////////////////////////////////
//// (0) signal assignment ////
assign ads_rd_parameter = spi_data_out;
assign ads_out_valid = spi_data_valid;
//////////////////////////////////////////////////////////////////////////////////
//// (1) ads8332 SPI ////
jft_spi U0_ads8332_spi (
.spi_clk_in(~spi_clk),
.spi_rst_in(sys_rest),
.spi_start (ads_start), //Կһ¸λʱ
.spi_wr (1'd1), //ֻ2015/9/14 10:34:57
.spi_end (),
.spi_start_number(START_NUMBER),
.spi_cs_length (CS_LENGTH),
.spi_data_in (ads8332_reg),
.spi_clk(ads_spi_clk),
.spi_cs (ads_spi_cs),
.spi_sdi(ads_spi_sdi),
.spi_sdo(ads_spi_sdo),
.spi_data_out (spi_data_out),
.spi_data_valid(spi_data_valid),
.spi_count_starte (ads8332_count[6:0]),
.debug_signal()
);
//////////////////////////////////////////////////////////////////////////////////
//// debug signal ////
assign ads_debug[32:0] = {spi_data_valid, spi_data_out};
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
endmodule
| 7.37472 |
module ADS8361 (
input i_clk,
input i_reset_n,
input i_adc_data1,
input i_adc_data2,
output o_conv_start,
output reg o_adc_clock
);
reg [ 4:0] counter; //Counter to count number of clocks elapsed
reg [ 7:0] clock_counter; //counter used for main clock division to ADC_Clock
reg [15:0] channel_A_Data;
reg [15:0] channel_B_Data;
reg channel_A_Enable, channel_B_Enable;
localparam IDLE = 'd0, //local parameter declaration
GET_CHANNEL = 'd1, ENABLE_CHA = 'd2, ENABLE_CHB = 'd3, GetData = 'd4;
reg [2:0] state;
always @(posedge i_clk) begin
if (!i_reset_n) begin
clock_counter <= 0;
end
if (clock_counter != 4) clock_counter <= clock_counter + 1;
else clock_counter <= 0;
end
/*
initial
o_adc_clock <= 0;
always @(posedge i_clk)
begin
if(!i_reset_n)
begin
o_adc_clock <= 0;
end
if(i_reset_n && clock_counter == 4)
o_adc_clock <= ~o_adc_clock;
end
*/
always @(posedge i_clk) begin
o_adc_clock = ~o_adc_clock;
end
always @(posedge o_adc_clock) begin
if (!i_reset_n) begin
state <= IDLE;
channel_A_Enable <= 1'b0;
channel_B_Enable <= 1'b0;
end else begin
case (state)
IDLE: begin
if (o_conv_start) state <= GET_CHANNEL;
end
GET_CHANNEL: begin
if (i_adc_data1 == 1'b1) state <= ENABLE_CHA;
else state <= ENABLE_CHB;
end
ENABLE_CHA: begin
channel_A_Enable <= 1'b1;
state <= GetData;
end
ENABLE_CHB: begin
channel_B_Enable <= 1'b1;
state <= GetData;
end
GetData: begin
if (counter == 'd16) begin
channel_A_Enable <= 1'b0;
channel_B_Enable <= 1'b0;
state <= IDLE;
end
end
endcase
end
end
always @(posedge o_adc_clock) begin
if (!i_reset_n) channel_A_Data <= 'd0;
else if (channel_A_Enable) channel_A_Data <= {channel_A_Data[14:0], i_adc_data1};
end
always @(posedge o_adc_clock) begin
if (!i_reset_n) channel_B_Data <= 'd0;
else if (channel_B_Enable) channel_B_Data <= {channel_B_Data[14:0], i_adc_data1};
end
assign o_conv_start = (counter == 19) ? 1'b1 : 1'b0;
always @(negedge o_adc_clock) begin
if (!i_reset_n) counter <= 5'd0;
else begin
if (counter != 19) counter <= counter + 1'b1;
else counter <= 5'd0;
end
end
endmodule
| 7.306256 |
module tb ( //Waarom is deze module leeg?
);
reg clk;
reg reset;
reg [5:0] tb_count = 0;
wire conv_start;
reg channel;
reg adc_data_A = 0;
reg adc_data_B = 0;
reg [15:0] adc_data_port_A;
reg [15:0] adc_data_port_B;
wire adc_clock;
integer i;
wire channel_0_enable; //Heb ik zo correct een variabele geinstantieerd zodat deze in de ILA zichtbaar is? Want dat was het doel...
wire channel_1_enable;
integer i;
initial begin
clk = 0;
forever begin
clk = !clk;
#((`clockFreq) / 2); //Is # het wait commando?
end
end
initial begin
reset = 0;
#100;
reset = 1;
end
/*
always @(posedge clk)
begin
if(!reset)
tb_count <= 5'd0;
else
begin
if(tb_count != 19)
tb_count <= tb_count + 1'b1;
else
tb_count <= 5'd0;
end
end
*/
initial begin
channel = 0;
forever begin
@(posedge clk);
if (!reset) tb_count = 0;
case (tb_count)
0: begin
if (conv_start) begin
channel = !channel;
adc_data_A <= channel;
adc_data_B <= channel;
tb_count <= tb_count + 1;
end
end
1: begin
adc_data_A <= 1'b0;
adc_data_B <= 1'b0;
adc_data_port_A = 'hFFFF;
adc_data_port_B = 'hFFFF;
$display($time,,,, "Data from ADC Port A is %d and data from ADC Port B is %d\n",
adc_data_port_A, adc_data_port_B);
tb_count <= tb_count + 1;
end
2: begin
//adc_data_port_A = $random()%65535;
for (i = 0; i < 16; i = i + 1) begin
adc_data_A = adc_data_port_A[15];
adc_data_B = adc_data_port_B[15];
adc_data_port_A = adc_data_port_A << 1;
adc_data_port_B = adc_data_port_B << 1;
@(negedge clk);
end
tb_count <= tb_count + 1;
end
3: begin
adc_data_A <= 0;
adc_data_B <= 0;
tb_count = 0;
end
endcase
end
end
ADS8361 adc ( //moduleName instanceName
//positional //named port mapping
//.formal Port(Actual Port)
.i_clk(clk),
.i_reset_n(reset), //if formal port is output, actual ports should be always wire type
.i_adc_port_A(adc_data_A), //if formal port is input, actual port can be wire or reg
.i_adc_port_B(adc_data_B), //if formal port is input, actual port can be wire or reg
.o_conv_start(conv_start),
.o_adc_clock(adc_clock),
.channel_0_enable(channel_0_enable), //map ik zo channel_0_enable correct zodat deze te zien is in de ILA?
.channel_1_enable(channel_1_enable)
);
endmodule
| 6.952555 |
module ADSR (
clock,
reset,
keyboard_pushed,
attack_value,
decay_value,
sustain_value,
release_value,
wave_out_to_adsr,
adsr_out
);
input clock;
input reset;
input keyboard_pushed;
input [3:0] attack_value, decay_value, sustain_value, release_value;
input [15:0] wave_out_to_adsr;
output [15:0] adsr_out;
wire reset_attack, reset_decay, reset_release;
wire attack_done, decay_done, release_done;
wire [1:0] adr;
wire is_sustain;
adsr_control adsr_c0 (
.clk(clock),
.attack_done(attack_done),
.decay_done(decay_done),
.release_done(release_done),
.resetn(reset),
.keyboard_pushed(keyboard_pushed),
.is_sustain(is_sustain),
.adr(adr),
.attack_reset(reset_attack),
.decay_reset(reset_decay),
.release_reset(reset_release)
);
adsr_datapath adsr_d0 (
.clock(clock),
.reset_attack(reset_attack),
.reset_decay(reset_decay),
.reset_release(reset_release),
.adr(adr),
.is_sustain(is_sustain),
.attack_value(attack_value),
.decay_value(decay_value),
.sustain_value(sustain_value),
.release_value(release_value),
.wave_out_to_adsr(wave_out_to_adsr),
.adsr_out(adsr_out),
.attack_done(attack_done),
.decay_done(decay_done),
.release_done(release_done)
);
endmodule
| 7.04094 |
module adsr_datapath (
input clock,
input reset_attack,
reset_decay,
reset_release,
input [1:0] adr,
input is_sustain,
input [3:0] attack_value,
decay_value,
sustain_value,
release_value,
input [15:0] wave_out_to_adsr,
output [15:0] adsr_out,
output attack_done,
decay_done,
release_done
);
wire [15:0] modified_ATTACK_out, modified_DECAY_out, modified_SUSTAIN_out, modified_RELEASE_out;
//wire attack_done, decay_done, release_done;
wire [3:0] attack_shift_amount, decay_shift_amount, release_shift_amount;
attack_shift_amount aso0 (
clock,
reset_attack,
attack_value,
attack_shift_amount,
attack_done
);
decay_shift_amount dso0 (
clock,
reset_decay,
decay_value,
sustain_value,
decay_shift_amount,
decay_done
);
release_shift_amount rso0 (
clock,
reset_release,
release_value,
sustain_value,
release_shift_amount,
release_done
);
reg [3:0] shift_amount;
//MUX the shift amounts
always @(*) begin
if (is_sustain) begin
shift_amount = (4'd15 - sustain_value);
end else begin
case (adr)
1: shift_amount = attack_shift_amount;
2: shift_amount = decay_shift_amount;
3: shift_amount = release_shift_amount;
default shift_amount = 4'd0;
endcase
end
end
adsr_modification am0 (
wave_out_to_adsr,
shift_amount,
adsr_out
);
endmodule
| 7.06164 |
module adsr_modification (
amplitude,
shift_amount,
modified_out
);
input [15:0] amplitude;
input [3:0] shift_amount;
output [15:0] modified_out;
assign modified_out = amplitude >>> shift_amount;
endmodule
| 7.242926 |
module adsr32 (
clk,
GATE,
A,
D,
S,
R,
sout /*, SEG */
);
output reg [31:0] sout; // This is the accumulator/integrator for attack, decay and release
input wire clk; // 50 MHz
input wire GATE; // GATE signal
input wire [31:0] A; // attack rate
input wire [31:0] D; // decay rate
input wire [31:0] S; // sustain level
input wire [31:0] R; // release rate
reg [2:0] state; // state 0,1,2,3,4,5 - IDLE,ATTACK,DECAY,SUSTAIN,RELEASE
//output [7:0] SEG;
initial begin
state = 3'b000;
sout = 0;
end
////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////
// This is a state machine of 5 states, IDLE, ATTACK, DECAY, SUSTAIN and RELEASE.
parameter IDLE = 3'b000;
parameter ATTACK = 3'b001;
parameter DECAY = 3'b010;
parameter SUSTAIN = 3'b011;
parameter RELEASE = 3'b100;
always @(posedge clk) begin
case (state)
IDLE: //ждем
begin
// переходим из IDLE в 01 (attack)
//смена стейта
state <= (GATE == 1'b1) ? ATTACK : IDLE;
end
ATTACK: //атака
begin
if (GATE == 1'b1) begin
if ( (sout + A) <= {1'b0,{32{1'b1}}} ) begin //если не достигли максимума - прибавляем
sout <= sout + A; // на значение A
end else begin // иначе переполнение
sout <= {32{1'b1}}; // ставим максимальное значение
end
end
//смена стейта
if (GATE == 1'b0) begin
state <= RELEASE; // если GATE в ноле, значит переходим в state 4 (release)
end else begin
// GATE в единице
if ( (sout + A) > {1'b0,{32{1'b1}}} ) begin //если не достигли максимума - прибавляем
state <= DECAY; // переходим в state 2 (decay)
end
end
end
DECAY: //спад
begin
if (GATE == 1'b1) begin
//GATE активно? спадаем
if ((sout - D) > S) begin
sout <= sout - D;
end else begin
sout <= S;
end
end
if (GATE == 1'b1) begin
if (sout == S) begin
state <= SUSTAIN;
end
end else if (GATE == 1'b0) begin
state <= RELEASE;
end
end
SUSTAIN: //в удержании стоим, пока не спал GATE
begin
if (GATE == 1'b0) state <= RELEASE; // Go to state 4, RELEASE
end
RELEASE: begin
if ( GATE == 1'b0 ) begin //при RELEASE снова нажата GATE - переходим в ATTACK
if (sout > R) begin // если значение больше, то вычитаем
sout <= (sout - R);
end else begin //иначе, утухли совсем и перешли в стейт IDLE
sout <= 0;
end
end else if (GATE == 1'b1) begin
//если в режиме релиза пришел следующий гейт - ИГНОРИМ ХВОСТ
sout <= 0;
end
//
if (GATE == 1'b1) begin
state <= ATTACK;
end else begin ///////
if (sout == 0) begin
state <= IDLE;
end
end
end
endcase
end
/*
reg [6:0] SEG_buf;
always @ (state)
begin
case(state)
3'h0: SEG_buf <= 7'b0111111;
3'h1: SEG_buf <= 7'b0000110;
3'h2: SEG_buf <= 7'b1011011;
3'h3: SEG_buf <= 7'b1001111;
3'h4: SEG_buf <= 7'b1100110;
3'h5: SEG_buf <= 7'b1101101;
3'h6: SEG_buf <= 7'b1111101;
3'h7: SEG_buf <= 7'b0000111;
default: SEG_buf <= 7'b0111111;
endcase
end
assign SEG = {1'b0,SEG_buf}; */
endmodule
| 8.309304 |
module ADSRBench;
reg clock = 0, reset = 1;
reg [1:0] wavetype = 2'b00;
wire [23:0] waveform, wavebuff;
reg [15:0] addr = 0;
wire [7:0] data;
reg [7:0] writedata = 0;
reg readwrite = 0;
reg busclk = 0;
assign data = readwrite == 1 ? writedata : 8'hZZ;
reg scale = 0;
initial begin
$dumpfile("ADSRBench.vcd");
$dumpvars;
$display("Running Simulation...");
// $monitor("%g\t: %b", $time, waveform);
//Force output a full range scale test
scale <= 0;
#2 scale <= 1;
#2 scale <= 0;
//Hold reset for 100[u]
#100 reset <= 0;
//Run for 5[s]
#5000
//Hold reset for 100[u]
reset <= 1;
#100 $display("Simulation Complete");
$finish;
end
`define SET_REG(a, d) \
addr <= (a); writedata = (d); \
readwrite <= 1; busclk <= 1; #2 busclk <= 0; #2
`define SET_REG_24(a, d) \
addr <= (a); writedata = ((d)>>0) & 8'hFF; \
readwrite <= 1; busclk <= 1; #2 busclk <= 0; #2 \
addr <= (a)+1; writedata = ((d)>>8) & 8'hFF; \
readwrite <= 1; busclk <= 1; #2 busclk <= 0; #2 \
addr <= (a)+2; writedata = ((d)>>16) & 8'hFF; \
readwrite <= 1; busclk <= 1; #2 busclk <= 0; #2 \
initial begin
#200
//Note 1
`SET_REG_24(
16'h0011, 24'h0FFFFF); //Incr
`SET_REG(16'h0014, 8'h01); //WaveType = Square
`SET_REG_24(16'h0015, 24'h3FFFFF); //PulseWidth
`SET_REG_24(16'h0018, 24'h010000); //Attack
`SET_REG_24(16'h001B, 24'h010000); //Decay
`SET_REG_24(16'h001E, 24'h7FFFFF); //Sustain
`SET_REG_24(16'h0021, 24'h010000); //Release
`SET_REG(16'h0024, 8'h01); //Linear
//Note 2
`SET_REG_24(16'h0031, 24'h0FFFFF); //Incr
`SET_REG(16'h0034, 8'h02); //WaveType = Triangle
`SET_REG_24(16'h0035, 24'h7FFFFF); //PulseWidth
`SET_REG_24(16'h0038, 24'h003000); //Attack
`SET_REG_24(16'h003B, 24'h003000); //Decay
`SET_REG_24(16'h003E, 24'h7FFFFF); //Sustain
`SET_REG_24(16'h0041, 24'h003000); //Release
//Start Notes
`SET_REG(16'h0010, 8'h01); //Gate = Open
`SET_REG(16'h0030, 8'h01); //Gate = Open
#1000 `SET_REG(16'h0030, 8'h00); //Gate = Close
`SET_REG_24(16'h0011, 24'h00FFFF); //Incr
`SET_REG_24(16'h0015, 24'h7FFFFF); //PulseWidth
#300 `SET_REG(16'h0030, 8'h01); //Gate = Open
#1000 `SET_REG(16'h0010, 8'h00); //Gate = Close
#1000 `SET_REG(16'h0030, 8'h00); //Gate = Close
#100 addr <= 0;
writedata <= 0;
readwrite <= 0;
end
//Clock Process. Oscillates every 1[u] (resulting in a 2[u] period)
always begin
#0.005 clock = !clock;
end
//Allow switching between full scale display test and toplevel waveform output
assign waveform = scale ? (clock ? 24'hFFFFFF : 0) : wavebuff;
TopLevel TL (
.Clock(clock),
.Reset(reset),
.BusAddress(addr),
.BusData(data),
.BusReadWrite(readwrite),
.BusClock(busclk),
.Waveform(wavebuff)
);
endmodule
| 8.001604 |
module adsr_mngt (
input clk,
input rst,
input new_sample,
input new_note_pulse,
input release_note_pulse,
input [17:0] sustain_value,
output reg [17:0] volume_d,
input [17:0] volume,
output reg [4:0] state
);
`define ATTACK 3'd1
`define DECAY 3'd2
`define SUSTAIN 3'd3
`define RELEASE 3'd4
`define BLANK 3'd5
`define VOLUME_RESET 18'h00000
//`define VOLUME_RESET 18'h00800
//`define VOLUME_MAX 18'h01000
`define VOLUME_MAX 18'h1FFFF
`define VOLUME_SUSTAIN 18'h000C00
reg latch_new_note;
reg latch_release_note;
always @(posedge clk)
if (rst == 1'b1) begin
latch_new_note <= 1'b0;
latch_release_note <= 1'b0;
end else begin
if (new_note_pulse == 1'b1) latch_new_note <= 1'b1;
if (release_note_pulse == 1'b1) latch_release_note <= 1'b1;
if (state[2:0] == `ATTACK && latch_new_note == 1'b1) latch_new_note <= 1'b0;
if ((state[2:0] == `RELEASE || state[2:0] == `BLANK) && latch_release_note == 1'b1)
latch_release_note <= 1'b0;
end
always @(posedge clk) begin
if (rst == 1'b1) begin
state <= `BLANK;
volume_d <= `VOLUME_RESET;
end else begin
if (new_sample == 1'b1) begin
volume_d <= volume;
case (state[2:0])
`BLANK: begin
if (latch_new_note == 1'b1) state[2:0] <= `ATTACK;
else state[2:0] <= `BLANK;
end
`ATTACK: begin
if (`VOLUME_RESET <= volume && volume < `VOLUME_MAX) state[2:0] <= `ATTACK;
else state[2:0] <= `DECAY;
end
`DECAY: begin
if (latch_new_note == 1'b1) state[2:0] <= `ATTACK;
else if (latch_release_note == 1'b1) state[2:0] <= `RELEASE;
else if (volume > sustain_value) state[2:0] <= `DECAY;
else state[2:0] <= `SUSTAIN;
end
`SUSTAIN: begin
if (latch_new_note == 1'b1) state[2:0] <= `ATTACK;
else if (latch_release_note == 1'b1) state[2:0] <= `RELEASE;
else state[2:0] <= `SUSTAIN;
end
`RELEASE: begin
if (latch_new_note == 1'b1) state[2:0] <= `ATTACK;
else if (volume > `VOLUME_RESET && volume[17] == 1'b0) state[2:0] <= `RELEASE;
else state[2:0] <= `BLANK;
end
endcase
end
state[3] <= latch_new_note;
state[4] <= latch_release_note;
end
end
endmodule
| 8.194417 |
module adsr_modification (
amplitude,
shift_amount,
modified_out
);
input [15:0] amplitude;
input [3:0] shift_amount;
output [15:0] modified_out;
assign modified_out = amplitude >>> shift_amount;
endmodule
| 7.242926 |
module decay_rom (
clock,
decay,
sustain,
count_up_to
);
input clock;
input [3:0] decay, sustain;
output reg [31:0] count_up_to;
wire [3:0] shifting_distance;
assign shifting_distance = (4'd15 - sustain);
wire [31:0] out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7,
out_8, out_9, out_10, out_11, out_12, out_13, out_14, out_15;
distance0_rom dr0 (
decay,
out_0
);
distance1_rom dr1 (
decay,
out_1
);
distance2_rom dr2 (
decay,
out_2
);
distance3_rom dr3 (
decay,
out_3
);
distance4_rom dr4 (
decay,
out_4
);
distance5_rom dr5 (
clock,
decay,
out_5
);
distance6_rom dr6 (
decay,
out_6
);
distance7_rom dr7 (
decay,
out_7
);
distance8_rom dr8 (
decay,
out_8
);
distance9_rom dr9 (
decay,
out_9
);
distance10_rom dr10 (
decay,
out_10
);
distance11_rom dr11 (
decay,
out_11
);
distance12_rom dr12 (
decay,
out_12
);
distance13_rom dr13 (
decay,
out_13
);
distance14_rom dr14 (
decay,
out_14
);
distance15_rom dr15 (
decay,
out_15
);
always @(posedge clock) begin
case (shifting_distance)
4'd0: count_up_to = out_0;
4'd1: count_up_to = out_1;
4'd2: count_up_to = out_2;
4'd3: count_up_to = out_3;
4'd4: count_up_to = out_4;
4'd5: count_up_to = out_5;
4'd6: count_up_to = out_6;
4'd7: count_up_to = out_7;
4'd8: count_up_to = out_8;
4'd9: count_up_to = out_9;
4'd10: count_up_to = out_10;
4'd11: count_up_to = out_11;
4'd12: count_up_to = out_12;
4'd13: count_up_to = out_13;
4'd14: count_up_to = out_14;
4'd15: count_up_to = out_15;
endcase
end
endmodule
| 6.585931 |
module release_rom (
clock,
myrelease,
sustain,
count_up_to
);
input clock;
input [3:0] myrelease, sustain;
output reg [31:0] count_up_to;
wire [3:0] shifting_distance;
assign shifting_distance = sustain;
wire [31:0] out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7,
out_8, out_9, out_10, out_11, out_12, out_13, out_14, out_15;
distance0_rom dr0 (
myrelease,
out_0
);
distance1_rom dr1 (
myrelease,
out_1
);
distance2_rom dr2 (
myrelease,
out_2
);
distance3_rom dr3 (
myrelease,
out_3
);
distance4_rom dr4 (
myrelease,
out_4
);
distance5_rom dr5 (
myrelease,
out_5
);
distance6_rom dr6 (
myrelease,
out_6
);
distance7_rom dr7 (
myrelease,
out_7
);
distance8_rom dr8 (
myrelease,
out_8
);
distance9_rom dr9 (
myrelease,
out_9
);
distance10_rom dr10 (
myrelease,
out_10
);
distance11_rom dr11 (
myrelease,
out_11
);
distance12_rom dr12 (
myrelease,
out_12
);
distance13_rom dr13 (
myrelease,
out_13
);
distance14_rom dr14 (
myrelease,
out_14
);
distance15_rom dr15 (
myrelease,
out_15
);
always @(posedge clock) begin
case (shifting_distance)
4'd0: count_up_to = out_0;
4'd1: count_up_to = out_1;
4'd2: count_up_to = out_2;
4'd3: count_up_to = out_3;
4'd4: count_up_to = out_4;
4'd5: count_up_to = out_5;
4'd6: count_up_to = out_6;
4'd7: count_up_to = out_7;
4'd8: count_up_to = out_8;
4'd9: count_up_to = out_9;
4'd10: count_up_to = out_10;
4'd11: count_up_to = out_11;
4'd12: count_up_to = out_12;
4'd13: count_up_to = out_13;
4'd14: count_up_to = out_14;
4'd15: count_up_to = out_15;
endcase
end
endmodule
| 6.728791 |
module distance1_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd12500000;
4'd2: count_up_to = 32'd25000000;
4'd3: count_up_to = 32'd37500000;
4'd4: count_up_to = 32'd50000000;
4'd5: count_up_to = 32'd62500000;
4'd6: count_up_to = 32'd75000000;
4'd7: count_up_to = 32'd87500000;
4'd8: count_up_to = 32'd100000000;
4'd9: count_up_to = 32'd112500000;
4'd10: count_up_to = 32'd125000000;
4'd11: count_up_to = 32'd137500000;
4'd12: count_up_to = 32'd150000000;
4'd13: count_up_to = 32'd162500000;
4'd14: count_up_to = 32'd175000000;
4'd15: count_up_to = 32'd187500000;
endcase
endmodule
| 6.609805 |
module distance2_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd6250000;
4'd2: count_up_to = 32'd12500000;
4'd3: count_up_to = 32'd18750000;
4'd4: count_up_to = 32'd25000000;
4'd5: count_up_to = 32'd31250000;
4'd6: count_up_to = 32'd37500000;
4'd7: count_up_to = 32'd43750000;
4'd8: count_up_to = 32'd50000000;
4'd9: count_up_to = 32'd56250000;
4'd10: count_up_to = 32'd62500000;
4'd11: count_up_to = 32'd68750000;
4'd12: count_up_to = 32'd75000000;
4'd13: count_up_to = 32'd81250000;
4'd14: count_up_to = 32'd87500000;
4'd15: count_up_to = 32'd93750000;
endcase
endmodule
| 6.800165 |
module distance3_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd4166666;
4'd2: count_up_to = 32'd8333333;
4'd3: count_up_to = 32'd12500000;
4'd4: count_up_to = 32'd16666666;
4'd5: count_up_to = 32'd20833333;
4'd6: count_up_to = 32'd25000000;
4'd7: count_up_to = 32'd29166666;
4'd8: count_up_to = 32'd33333333;
4'd9: count_up_to = 32'd37500000;
4'd10: count_up_to = 32'd41666666;
4'd11: count_up_to = 32'd45833333;
4'd12: count_up_to = 32'd50000000;
4'd13: count_up_to = 32'd54166666;
4'd14: count_up_to = 32'd58333333;
4'd15: count_up_to = 32'd62500000;
endcase
endmodule
| 6.797002 |
module distance4_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd3125000;
4'd2: count_up_to = 32'd6250000;
4'd3: count_up_to = 32'd9375000;
4'd4: count_up_to = 32'd12500000;
4'd5: count_up_to = 32'd15625000;
4'd6: count_up_to = 32'd18750000;
4'd7: count_up_to = 32'd21875000;
4'd8: count_up_to = 32'd25000000;
4'd9: count_up_to = 32'd28125000;
4'd10: count_up_to = 32'd31250000;
4'd11: count_up_to = 32'd34375000;
4'd12: count_up_to = 32'd37500000;
4'd13: count_up_to = 32'd40625000;
4'd14: count_up_to = 32'd43750000;
4'd15: count_up_to = 32'd46875000;
endcase
endmodule
| 7.202542 |
module distance6_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd2083333;
4'd2: count_up_to = 32'd4166666;
4'd3: count_up_to = 32'd6250000;
4'd4: count_up_to = 32'd8333333;
4'd5: count_up_to = 32'd10416666;
4'd6: count_up_to = 32'd12500000;
4'd7: count_up_to = 32'd14583333;
4'd8: count_up_to = 32'd16666666;
4'd9: count_up_to = 32'd18750000;
4'd10: count_up_to = 32'd20833333;
4'd11: count_up_to = 32'd22916666;
4'd12: count_up_to = 32'd25000000;
4'd13: count_up_to = 32'd27083333;
4'd14: count_up_to = 32'd29166666;
4'd15: count_up_to = 32'd31250000;
endcase
endmodule
| 6.68687 |
module distance7_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd1785714;
4'd2: count_up_to = 32'd3571428;
4'd3: count_up_to = 32'd5357142;
4'd4: count_up_to = 32'd7142857;
4'd5: count_up_to = 32'd8928571;
4'd6: count_up_to = 32'd10714285;
4'd7: count_up_to = 32'd12500000;
4'd8: count_up_to = 32'd14285714;
4'd9: count_up_to = 32'd16071428;
4'd10: count_up_to = 32'd17857142;
4'd11: count_up_to = 32'd19642857;
4'd12: count_up_to = 32'd21428571;
4'd13: count_up_to = 32'd23214285;
4'd14: count_up_to = 32'd25000000;
4'd15: count_up_to = 32'd26785714;
endcase
endmodule
| 6.683022 |
module distance8_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd1562500;
4'd2: count_up_to = 32'd3125000;
4'd3: count_up_to = 32'd4687500;
4'd4: count_up_to = 32'd6250000;
4'd5: count_up_to = 32'd7812500;
4'd6: count_up_to = 32'd9375000;
4'd7: count_up_to = 32'd10937500;
4'd8: count_up_to = 32'd12500000;
4'd9: count_up_to = 32'd14062500;
4'd10: count_up_to = 32'd15625000;
4'd11: count_up_to = 32'd17187500;
4'd12: count_up_to = 32'd18750000;
4'd13: count_up_to = 32'd20312500;
4'd14: count_up_to = 32'd21875000;
4'd15: count_up_to = 32'd23437500;
endcase
endmodule
| 6.898261 |
module distance9_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd1388888;
4'd2: count_up_to = 32'd2777777;
4'd3: count_up_to = 32'd4166666;
4'd4: count_up_to = 32'd5555555;
4'd5: count_up_to = 32'd6944444;
4'd6: count_up_to = 32'd8333333;
4'd7: count_up_to = 32'd9722222;
4'd8: count_up_to = 32'd11111111;
4'd9: count_up_to = 32'd12500000;
4'd10: count_up_to = 32'd13888888;
4'd11: count_up_to = 32'd15277777;
4'd12: count_up_to = 32'd16666666;
4'd13: count_up_to = 32'd18055555;
4'd14: count_up_to = 32'd19444444;
4'd15: count_up_to = 32'd20833333;
endcase
endmodule
| 6.516716 |
module distance12_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd1041666;
4'd2: count_up_to = 32'd2083333;
4'd3: count_up_to = 32'd3125000;
4'd4: count_up_to = 32'd4166666;
4'd5: count_up_to = 32'd5208333;
4'd6: count_up_to = 32'd6250000;
4'd7: count_up_to = 32'd7291666;
4'd8: count_up_to = 32'd8333333;
4'd9: count_up_to = 32'd9375000;
4'd10: count_up_to = 32'd10416666;
4'd11: count_up_to = 32'd11458333;
4'd12: count_up_to = 32'd12500000;
4'd13: count_up_to = 32'd13541666;
4'd14: count_up_to = 32'd14583333;
4'd15: count_up_to = 32'd15625000;
endcase
endmodule
| 7.034521 |
module distance13_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd961538;
4'd2: count_up_to = 32'd1923076;
4'd3: count_up_to = 32'd2884615;
4'd4: count_up_to = 32'd3846153;
4'd5: count_up_to = 32'd4807692;
4'd6: count_up_to = 32'd5769230;
4'd7: count_up_to = 32'd6730769;
4'd8: count_up_to = 32'd7692307;
4'd9: count_up_to = 32'd8653846;
4'd10: count_up_to = 32'd9615384;
4'd11: count_up_to = 32'd10576923;
4'd12: count_up_to = 32'd11538461;
4'd13: count_up_to = 32'd12500000;
4'd14: count_up_to = 32'd13461538;
4'd15: count_up_to = 32'd14423076;
endcase
endmodule
| 6.829219 |
module distance14_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd892857;
4'd2: count_up_to = 32'd1785714;
4'd3: count_up_to = 32'd2678571;
4'd4: count_up_to = 32'd3571428;
4'd5: count_up_to = 32'd4464285;
4'd6: count_up_to = 32'd5357142;
4'd7: count_up_to = 32'd6250000;
4'd8: count_up_to = 32'd7142857;
4'd9: count_up_to = 32'd8035714;
4'd10: count_up_to = 32'd8928571;
4'd11: count_up_to = 32'd9821428;
4'd12: count_up_to = 32'd10714285;
4'd13: count_up_to = 32'd11607142;
4'd14: count_up_to = 32'd12500000;
4'd15: count_up_to = 32'd13392857;
endcase
endmodule
| 7.353782 |
module distance15_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd833333;
4'd2: count_up_to = 32'd1666666;
4'd3: count_up_to = 32'd2500000;
4'd4: count_up_to = 32'd3333333;
4'd5: count_up_to = 32'd4166666;
4'd6: count_up_to = 32'd5000000;
4'd7: count_up_to = 32'd5833333;
4'd8: count_up_to = 32'd6666666;
4'd9: count_up_to = 32'd7500000;
4'd10: count_up_to = 32'd8333333;
4'd11: count_up_to = 32'd9166666;
4'd12: count_up_to = 32'd10000000;
4'd13: count_up_to = 32'd10833333;
4'd14: count_up_to = 32'd11666666;
4'd15: count_up_to = 32'd12500000;
endcase
endmodule
| 6.615403 |
module ADS_16SPI (
input clk,
rst_n,
input go,
input [15:0] wrdat,
output reg [15:0] rddat,
output reg ok,
output reg mosi,
output sclk,
input miso
);
reg [4:0] i;
always @(posedge clk or negedge rst_n)
if (!rst_n) i <= 5'd0;
else if (!go) i <= 5'd0;
else if (i < 5'd23) i <= i + 1'b1;
reg [15:0] r_wrdat;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
r_wrdat <= 16'd0;
mosi <= 1'b0;
end else begin
case (i)
5'd0: begin
r_wrdat <= wrdat;
mosi <= 1'b0;
end
5'd1: mosi <= r_wrdat[15];
5'd2: mosi <= r_wrdat[14];
5'd3: mosi <= r_wrdat[13];
5'd4: mosi <= r_wrdat[12];
5'd5: mosi <= r_wrdat[11];
5'd6: mosi <= r_wrdat[10];
5'd7: mosi <= r_wrdat[9];
5'd8: mosi <= r_wrdat[8];
5'd9: mosi <= r_wrdat[7];
5'd10: mosi <= r_wrdat[6];
5'd11: mosi <= r_wrdat[5];
5'd12: mosi <= r_wrdat[4];
5'd13: mosi <= r_wrdat[3];
5'd14: mosi <= r_wrdat[2];
5'd15: mosi <= r_wrdat[1];
5'd16: mosi <= r_wrdat[0];
default: mosi <= 1'b0;
endcase
end
reg [15:0] r_rddat;
reg cke;
always @(negedge clk or negedge rst_n)
if (!rst_n) begin
r_rddat <= 16'd0;
cke <= 1'b0;
ok <= 1'b0;
end else begin
case (i)
5'd0: begin
cke <= 1'b0;
ok <= 1'b0;
end
5'd1: cke <= 1'b1;
5'd2: r_rddat[15] <= miso;
5'd3: r_rddat[14] <= miso;
5'd4: r_rddat[13] <= miso;
5'd5: r_rddat[12] <= miso;
5'd6: r_rddat[11] <= miso;
5'd7: r_rddat[10] <= miso;
5'd8: r_rddat[9] <= miso;
5'd9: r_rddat[8] <= miso;
5'd10: r_rddat[7] <= miso;
5'd11: r_rddat[6] <= miso;
5'd12: r_rddat[5] <= miso;
5'd13: r_rddat[4] <= miso;
5'd14: r_rddat[3] <= miso;
5'd15: r_rddat[2] <= miso;
5'd16: r_rddat[1] <= miso;
5'd17: begin
r_rddat[0] <= miso;
cke <= 1'b0;
end
5'd18: begin
rddat <= r_rddat;
ok <= 1'b1;
end
default: ;
endcase
end
assign sclk = cke & clk;
endmodule
| 8.658111 |
module ADS_24SPI (
input clk,
rst_n,
input go,
input [23:0] wrdat,
output reg [23:0] rddat,
output reg ok,
output reg mosi,
output sclk,
input miso
);
reg [4:0] i;
always @(posedge clk or negedge rst_n)
if (!rst_n) i <= 5'd0;
else if (!go) i <= 5'd0;
else if (i < 5'd31) i <= i + 1'b1;
reg [23:0] r_wrdat;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
r_wrdat <= 24'd0;
mosi <= 1'b0;
end else begin
case (i)
5'd0: begin
r_wrdat <= wrdat;
mosi <= 1'b0;
end
5'd1: mosi <= r_wrdat[23];
5'd2: mosi <= r_wrdat[22];
5'd3: mosi <= r_wrdat[21];
5'd4: mosi <= r_wrdat[20];
5'd5: mosi <= r_wrdat[19];
5'd6: mosi <= r_wrdat[18];
5'd7: mosi <= r_wrdat[17];
5'd8: mosi <= r_wrdat[16];
5'd9: mosi <= r_wrdat[15];
5'd10: mosi <= r_wrdat[14];
5'd11: mosi <= r_wrdat[13];
5'd12: mosi <= r_wrdat[12];
5'd13: mosi <= r_wrdat[11];
5'd14: mosi <= r_wrdat[10];
5'd15: mosi <= r_wrdat[9];
5'd16: mosi <= r_wrdat[8];
5'd17: mosi <= r_wrdat[7];
5'd18: mosi <= r_wrdat[6];
5'd19: mosi <= r_wrdat[5];
5'd20: mosi <= r_wrdat[4];
5'd21: mosi <= r_wrdat[3];
5'd22: mosi <= r_wrdat[2];
5'd23: mosi <= r_wrdat[1];
5'd24: mosi <= r_wrdat[0];
default: mosi <= 1'b0;
endcase
end
reg [23:0] r_rddat;
reg cke;
always @(negedge clk or negedge rst_n)
if (!rst_n) begin
r_rddat <= 24'd0;
cke <= 1'b0;
ok <= 1'b0;
end else begin
case (i)
5'd0: begin
cke <= 1'b0;
ok <= 1'b0;
end
5'd1: cke <= 1'b1;
5'd2: r_rddat[23] <= miso;
5'd3: r_rddat[22] <= miso;
5'd4: r_rddat[21] <= miso;
5'd5: r_rddat[20] <= miso;
5'd6: r_rddat[19] <= miso;
5'd7: r_rddat[18] <= miso;
5'd8: r_rddat[17] <= miso;
5'd9: r_rddat[16] <= miso;
5'd10: r_rddat[15] <= miso;
5'd11: r_rddat[14] <= miso;
5'd12: r_rddat[13] <= miso;
5'd13: r_rddat[12] <= miso;
5'd14: r_rddat[11] <= miso;
5'd15: r_rddat[10] <= miso;
5'd16: r_rddat[9] <= miso;
5'd17: r_rddat[8] <= miso;
5'd18: r_rddat[7] <= miso;
5'd19: r_rddat[6] <= miso;
5'd20: r_rddat[5] <= miso;
5'd21: r_rddat[4] <= miso;
5'd22: r_rddat[3] <= miso;
5'd23: r_rddat[2] <= miso;
5'd24: r_rddat[1] <= miso;
5'd25: begin
r_rddat[0] <= miso;
cke <= 1'b0;
end
5'd26: begin
rddat <= r_rddat;
ok <= 1'b1;
end
default: ;
endcase
end
assign sclk = cke & clk;
endmodule
| 7.585962 |
module ADS_8SPI (
input clk,
rst_n,
input go,
input [7:0] wrdat,
output reg [7:0] rddat,
output reg ok,
output reg mosi,
output sclk,
input miso
);
reg [4:0] i;
always @(posedge clk or negedge rst_n)
if (!rst_n) i <= 5'd0;
else if (!go) i <= 5'd0;
else if (i < 5'd23) i <= i + 1'b1;
reg [7:0] r_wrdat;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
r_wrdat <= 8'd0;
mosi <= 1'b0;
end else begin
case (i)
5'd0: begin
r_wrdat <= wrdat;
mosi <= 1'b0;
end
5'd1: mosi <= r_wrdat[7];
5'd2: mosi <= r_wrdat[6];
5'd3: mosi <= r_wrdat[5];
5'd4: mosi <= r_wrdat[4];
5'd5: mosi <= r_wrdat[3];
5'd6: mosi <= r_wrdat[2];
5'd7: mosi <= r_wrdat[1];
5'd8: mosi <= r_wrdat[0];
default: mosi <= 1'b0;
endcase
end
reg [7:0] r_rddat;
reg cke;
always @(negedge clk or negedge rst_n)
if (!rst_n) begin
r_rddat <= 8'd0;
cke <= 1'b0;
ok <= 1'b0;
end else begin
case (i)
5'd0: begin
cke <= 1'b0;
ok <= 1'b0;
end
5'd1: cke <= 1'b1;
5'd2: r_rddat[7] <= miso;
5'd3: r_rddat[6] <= miso;
5'd4: r_rddat[5] <= miso;
5'd5: r_rddat[4] <= miso;
5'd6: r_rddat[3] <= miso;
5'd7: r_rddat[2] <= miso;
5'd8: r_rddat[1] <= miso;
5'd9: begin
r_rddat[0] <= miso;
cke <= 1'b0;
end
5'd10: begin
rddat <= r_rddat;
ok <= 1'b1;
end
default: ;
endcase
end
assign sclk = cke & clk;
endmodule
| 8.034163 |
module ads_spi(
//AD一侧的接口;
output SCLK,
output CS,
input DIN,
output DOUT,
input DRDY,
output START,
output RESET,
output PWDN,
//FPGA一侧接口;
input rst_n,//复位低有效；
input clk_50M,//时钟50MHZ;
input CLK_IN,
output CLK_OUT,
output [23:0] data_out,
output data_valid
);
//SPI模块；
reg I_rst_n;
reg I_rx_en;
reg I_tx_en;
reg [7:0] I_data_in;
spi_rw u_spi_rw(
.I_rst_n (I_rst_n),// input wire
.I_clk (),// input wire
.I_rx_en (I_rx_en),// input wire
.I_tx_en (I_tx_en),// input wire
.I_data_in (I_data_in),// input [7:0]
.O_data_out_0 (),// output reg [23:0]
.O_data_out_1 (),// output reg [23:0]
.O_data_out_2 (),// output reg [23:0]
.O_data_out_3 (),// output reg [23:0]
.O_data_out_4 (),// output reg [23:0]
.O_data_out_5 (),// output reg [23:0]
.O_data_out_6 (),// output reg [23:0]
.O_data_out_7 (),// output reg [23:0]
.O_data_out_0_valid (),// output reg
.O_data_out_1_valid (),// output reg
.O_data_out_2_valid (),// output reg
.O_data_out_3_valid (),// output reg
.O_data_out_4_valid (),// output reg
.O_data_out_5_valid (),// output reg
.O_data_out_6_valid (),// output reg
.O_data_out_7_valid (),// output reg
.I_spi_miso (DIN),//
.O_spi_sck (SCLK),//
.O_spi_cs (CS),//
.O_spi_mosi (DOUT),//
.O_tx_done () // output reg
);
//SPI配置读写状态机
localparam [2:0] ADS_START = 3'b001;
localparam [2:0] ADS_INIT = 3'b010;
localparam [2:0] ADS_READ = 3'b100;
reg [3:0] ADS_state ;
//定时器模块，用来控制发送指令的时间延时；
reg [20:0] cnt ;
reg timer_en ;
always @(posedge clk_50M or negedge rst_n) begin
if(!rst_n) begin
cnt <= 21'h0;
end
else if(timer_en == 1)begin
cnt <= cnt + 1'b1;
end
else begin
cnt <= cnt;
end
end
always@(posedge clk_50M or negedge rst_n) begin
if(!rst_n) begin
ADS_state <= ADS_START;
end
else begin
case (ADS_state)
ADS_START :
ADS_state <= ADS_INIT;
ADS_INIT:if(ads_init_done == 1)begin
ADS_state <= ADS_READ;
end
else begin
ADS_state <= ADS_INIT;
end
ADS_READ: ADS_state <= ADS_READ;
default: begin
ADS_state <= ADS_START;
end
endcase
end
end
wire [7:0] memory [0:18];
assign memory[0] = 8'h11;
assign memory[1] = 8'h41;
assign memory[2] = 8'h02;
assign memory[3] = 8'hD6;
assign memory[4] = 8'hE3;
assign memory[5] = 8'h40;
assign memory[6] = 8'h45;
assign memory[7] = 8'h07;
assign memory[8] = 8'h10;
assign memory[9] = 8'h10;
assign memory[10] = 8'h10;
assign memory[11] = 8'h10;
assign memory[12] = 8'h10;
assign memory[13] = 8'h10;
assign memory[14] = 8'h10;
assign memory[15] = 8'h10;
assign memory[16] = 8'h20;
assign memory[17] = 8'h00;
assign memory[18] = 8'h10;
reg CS_INIT ;
reg START_INIT ;
reg RESET_INIT ;
reg PWDN_INIT ;
reg
//控制状态机第二段；
always@(posedge clk_50M or negedge rst_n) begin
if(!rst_n) begin
I_rst_n <= 1'b0;
I_data_in <= 8'd0;
I_tx_en <= 1'b0;
I_rx_en <= 1'b0;
end
else begin
case(ADS_state)
ADS_START ：begin
I_rst_n <= 1'b1;
end
ADS_INIT : begin
timer_en <= 1'b1;
CS_INIT <= 1'b1;
if(cnt == 21'h1fff)begin
CS_INIT <= 1'b0;
START_INIT <= 1'b0;
PWDN_INIT <= 1'b1;
RESET_INIT <= 1'b1;
end
else if(cnt == 21'h101fff)begin
RESET_INIT <= 1'b0;
end
else if(cnt == 21'h111fff)begin
RESET_INIT <= 1'b1;
end
else if() begin
end
else begin
end
end
ADS_READ : begin
end
default: begin
end
endcase
end
end
endmodule
| 7.405376 |
module adtop (
input CLK,
input RST,
input [7:0] din1,
input [7:0] din2,
input valid,
output reg [127:0] dout,
output reg wr_en,
input full
);
localparam counter_top = 3'd7;
reg [2:0] counter;
always @(posedge CLK) begin
if (valid) dout <= {dout[111:0], din1, din2};
end
always @(posedge CLK or negedge RST)
if (!RST) begin
counter <= 3'd0;
end else begin
if (valid) counter <= counter + 3'd1;
end
always @(posedge CLK or negedge RST)
if (!RST) begin
wr_en <= 1'b0;
end else begin
if (counter == counter_top && valid) wr_en <= 1'b1;
else wr_en <= 1'b0;
end
endmodule
| 6.988123 |
module ADV7183B (
nRESET,
LLC1,
P15_8,
SCLK,
SDA
);
parameter NUM_FRAMES = 1;
parameter FRAME_SIZE = 900900;
input wire nRESET;
output reg LLC1;
output wire [15:8] P15_8;
input wire SCLK;
inout wire SDA;
initial begin
LLC1 = 1'b0;
forever #185 LLC1 = ~LLC1;
end
reg [7:0] vidstream[0:(NUM_FRAMES*FRAME_SIZE-1)];
initial begin
$readmemh("input.vid", vidstream);
//$stop;
end
integer vidaddr = 0;
always @(negedge LLC1, negedge nRESET) begin
if (nRESET == 1'b0) vidaddr = 0;
else if (vidaddr == (NUM_FRAMES * FRAME_SIZE - 1)) vidaddr = 0;
else vidaddr = vidaddr + 1;
end
assign P15_8 = vidstream[vidaddr];
//------------ I2C ---------------------
wire i2c_start;
wire i2c_stop;
reg dSDA, dSCLK;
always @(posedge LLC1, negedge nRESET) begin
if (nRESET == 1'b0) dSDA <= 1'b1;
else dSDA <= SDA;
end
always @(posedge LLC1, negedge nRESET) begin
if (nRESET == 1'b0) dSCLK <= 1'b0;
else dSCLK <= SCLK;
end
assign i2c_start = SCLK & dSCLK & dSDA & ~SDA;
assign i2c_stop = SCLK & dSCLK & SDA & ~dSDA;
reg i2c_active;
always @(posedge LLC1, negedge nRESET) begin
if (nRESET == 1'b0) i2c_active <= 1'b0;
else if (i2c_start) i2c_active <= 1'b1;
else if (i2c_stop) i2c_active <= 1'b0;
end
reg [3:0] bitcnt;
always @(posedge LLC1, negedge nRESET) begin
if (nRESET == 1'b0) bitcnt <= 4'b0000;
else if (i2c_start | i2c_stop) bitcnt <= 4'b0000;
else if (dSCLK & ~SCLK) begin
if (bitcnt == 4'b1001) bitcnt <= 4'b0001;
else bitcnt <= bitcnt + 1;
end
end
assign SDA = (bitcnt == 4'b1001) ? 1'b0 : 1'bZ;
wire SDAdrive;
assign SDAdrive = (bitcnt == 4'b1001) ? 1'b0 : 1'bZ;
endmodule
| 7.251358 |
module adv7513_driver_top (
input clk,
input clk_hdmi,
input rst_n,
//配置接口
output hdmi_i2c_scl,
inout hdmi_i2c_sda,
input hdmi_tx_int, //用于初始化配置
//像素数据接口
input [15:0] rgb_din,
input rgb_din_vld,
output hdmi_req,
output hdmi_tx_clk, //像素时钟
output [15:0] hdmi_tx_rgb, //图像数据
output hdmi_tx_de, //数据有效
output hdmi_tx_hsync, //行同步信号
output hdmi_tx_vsync //场同步信号
);
//信号定义
wire trans_req;
wire [3:0] trans_cmd;
wire [7:0] trans_data;
wire trans_done;
wire config_done;
wire i2c_scl;
wire sda_in;
wire sda_out;
wire sda_out_en;
//模块例化
adv7513_config u_adv7513_cfg (
/*input */.clk (clk),
/*input */.rst_n (rst_n),
/*input */.hdmi_int (hdmi_tx_int),
//i2c_master
/*output */.req (trans_req),
/*output [3:0] */.cmd (trans_cmd),
/*output [7:0] */.dout (trans_data),
/*input */.done (trans_done),
/*output */.config_done(config_done)
);
i2c_master u_hdmi_i2c (
/*input */.clk (clk),
/*input */.rst_n (rst_n),
/*input */.req (trans_req),
/*input [3:0] */.cmd (trans_cmd),
/*input [7:0] */.din (trans_data),
/*output [7:0] */.dout (),
/*output */.done (trans_done),
/*output */.slave_ack (),
/*output */.i2c_scl (i2c_scl),
/*input */.i2c_sda_i (sda_in),
/*output */.i2c_sda_o (sda_out),
/*output */.i2c_sda_oe(sda_out_en)
);
adv7513_hdmi u_vga_hdmi (
/*input */.clk (clk_hdmi),
/*input */.rst_n (rst_n),
/*input [15:0] */.rgb_din (rgb_din),
/*input */.rgb_din_vld(rgb_din_vld),
/*input */.rdy (config_done),
/*output */.hdmi_req (hdmi_req), //请求数据
//adv7513图像数据接口
/*output */.hdmi_hsync (hdmi_tx_hsync), //行同步
/*output */.hdmi_vsync (hdmi_tx_vsync), //场同步
/*output */.hdmi_de (hdmi_tx_de), //数据有效
/*output */.hdmi_clk (hdmi_tx_clk), //像素时钟
/*output [15:0] */.hdmi_rgb (hdmi_tx_rgb) //图像数据
);
assign hdmi_i2c_scl = i2c_scl;
assign hdmi_i2c_sda = sda_out_en ? sda_out : 1'bz;
assign sda_in = hdmi_i2c_sda;
endmodule
| 6.984389 |
module adv7513_reg_read #(
parameter CHIP_ADDR = 7'h39,
parameter I2C_CLKDIV = 206,
parameter I2C_TXN_DELAY = 0
) (
clk,
reset,
sda,
scl,
start,
done,
reg_addr_in,
reg_data
);
input clk, reset;
inout sda, scl;
input start;
output reg done;
input [7:0] reg_addr_in;
output reg [7:0] reg_data;
(* syn_encoding = "safe" *)
reg [ 1:0] state;
reg [ 6:0] chip_addr;
reg [ 7:0] reg_addr;
reg [25:0] cnt;
reg cnt_en;
localparam s_idle = 0, s_cmd = 1, s_wait = 2, s_done = 3;
localparam DLY_1s = 26'd50000000;
reg [7:0] data_in = 8'h0;
reg write_en;
reg read_en = 1'b0;
wire [2:0] i2c_status;
wire i2c_done;
wire i2c_busy;
wire i2c_write_mode = 1'b0;
wire [7:0] data_out;
wire sda_out;
wire sda_oen;
wire scl_out;
wire scl_oen;
i2c_master #(
.ADDR_BYTES(1),
.DATA_BYTES(1)
) i2c_master (
.clk (clk),
.reset (reset),
.open_drain(1'b1),
.clk_div (I2C_CLKDIV),
.chip_addr (chip_addr),
.reg_addr (reg_addr),
.data_in (data_in),
.write_en (write_en),
.write_mode(i2c_write_mode),
.read_en (read_en),
.status (i2c_status),
.done (i2c_done),
.busy (i2c_busy),
.data_out (data_out),
.sda_in (sda),
.scl_in (scl),
.sda_out (sda_out),
.sda_oen (sda_oen),
.scl_out (scl_out),
.scl_oen (scl_oen)
);
// assign done = ~i2c_busy && state == s_idle && prev_state == s_done;
// SDA Input / Output
//assign sda_in = sda;
assign sda = (sda_oen == 0) ? sda_out : 1'bz;
// SCL Input / Output
//assign scl_in = scl;
assign scl = (scl_oen == 0) ? scl_out : 1'bz;
always @(posedge clk) begin
// Flop the input so it's not lost
reg_addr <= reg_addr_in;
if (~reset) begin
done <= 1'b0;
state <= s_idle;
write_en <= 1'b0;
read_en <= 1'b0;
reg_data <= 8'h00;
cnt <= 26'd0;
cnt_en <= 1'b0;
end else begin
read_en <= 1'b0;
write_en <= 1'b0;
case (state)
s_idle: begin
state <= start ? s_cmd : s_idle;
if (done && cnt == DLY_1s) begin
done <= 1'b0;
cnt <= 26'd0;
cnt_en <= 1'b0;
end else if (cnt_en) cnt <= cnt + 26'd1;
end
s_cmd: begin
read_i2c(CHIP_ADDR, reg_addr);
done <= 1'b0;
state <= s_wait;
end
s_wait: begin
//write_en <= 1'b0;
//read_en <= 1'b0;
state <= (read_en || i2c_busy) ? s_wait : s_done;
end
s_done: begin
done <= 1'b1;
reg_data <= data_out;
state <= s_idle;
cnt <= 26'd0;
cnt_en <= 1'b1;
end
endcase
end
end
task write_i2c;
input [6:0] t_chip_addr;
input [7:0] t_reg_addr;
input [7:0] t_data;
begin
chip_addr <= t_chip_addr;
data_in <= t_data;
write_en <= 1'b1;
end
endtask
task read_i2c;
input [6:0] t_chip_addr;
input [7:0] t_reg_addr;
begin
chip_addr <= t_chip_addr;
read_en <= 1'b1;
end
endtask
endmodule
| 7.312749 |
module adv7611_frontend (
input PCLK_i,
input reset_n,
input [7:0] R_i,
input [7:0] G_i,
input [7:0] B_i,
input HSYNC_i,
input VSYNC_i,
input DE_i,
input [31:0] hv_in_config,
input [31:0] hv_in_config2,
input [31:0] hv_in_config3,
input sync_passthru,
output reg [7:0] R_o,
output reg [7:0] G_o,
output reg [7:0] B_o,
output reg HSYNC_o,
output reg VSYNC_o,
output reg DE_o,
output reg FID_o,
output reg interlace_flag,
output reg datavalid_o,
output reg [10:0] xpos_o,
output reg [10:0] ypos_o,
output reg frame_change,
output reg sof_scaler
);
localparam FID_EVEN = 1'b0;
localparam FID_ODD = 1'b1;
reg HSYNC_i_prev, VSYNC_i_prev, DE_i_prev;
reg FID_prev;
reg [11:0] h_cnt;
reg [10:0] v_cnt;
reg [10:0] vmax_cnt;
reg [3:0] h_ctr;
reg frame_change_raw;
reg [7:0] R_i_prev, G_i_prev, B_i_prev;
wire [11:0] H_ACTIVE = hv_in_config[23:12];
wire [ 7:0] H_SYNCLEN = hv_in_config[31:24];
wire [ 8:0] H_BACKPORCH = hv_in_config2[8:0];
wire [10:0] V_ACTIVE = hv_in_config3[11:0];
wire [ 3:0] V_SYNCLEN = hv_in_config3[15:12];
wire [ 8:0] V_BACKPORCH = hv_in_config2[29:21];
// Sample skip for low-res modes
wire [ 3:0] H_SKIP = hv_in_config2[12:9];
wire [ 3:0] H_SAMPLE_SEL = '0;
// SOF position for scaler
wire [10:0] V_SOF_LINE = hv_in_config3[27:16];
always @(posedge PCLK_i) begin
if (VSYNC_i_prev & ~VSYNC_i) begin
if (HSYNC_i_prev & ~HSYNC_i) begin
FID_o <= FID_ODD;
interlace_flag <= (FID_o == FID_EVEN);
frame_change_raw <= 1'b1;
h_cnt <= 0;
h_ctr <= 0;
v_cnt <= 0;
vmax_cnt <= 0;
end else begin
FID_o <= FID_EVEN;
interlace_flag <= (FID_o == FID_ODD);
frame_change_raw <= ~interlace_flag;
if (h_ctr == H_SKIP) begin
h_cnt <= h_cnt + 1'b1;
h_ctr <= 0;
end else begin
h_ctr <= h_ctr + 1'b1;
end
v_cnt <= -1;
end
xpos_o <= 0;
ypos_o <= 0;
end else begin
if (HSYNC_i_prev & ~HSYNC_i) begin
frame_change <= frame_change_raw;
frame_change_raw <= 1'b0;
h_cnt <= 0;
h_ctr <= 0;
v_cnt <= v_cnt + 1'b1;
vmax_cnt <= vmax_cnt + 1'b1;
sof_scaler <= (vmax_cnt == V_SOF_LINE);
end else begin
if (h_ctr == H_SKIP) begin
h_cnt <= h_cnt + 1'b1;
h_ctr <= 0;
end else begin
h_ctr <= h_ctr + 1'b1;
end
end
if (DE_i_prev & ~DE_i) begin
xpos_o <= 0;
ypos_o <= ypos_o + 1'b1;
end else if (DE_i_prev & DE_i) begin
xpos_o <= xpos_o + 1'b1;
end
end
if (sync_passthru) begin
R_o <= R_i;
G_o <= G_i;
B_o <= B_i;
HSYNC_o <= HSYNC_i;
VSYNC_o <= VSYNC_i;
DE_o <= DE_i;
datavalid_o <= 1'b1;
end else begin
R_o <= R_i_prev;
G_o <= G_i_prev;
B_o <= B_i_prev;
HSYNC_o <= (h_cnt < H_SYNCLEN) ? 1'b0 : 1'b1;
VSYNC_o <= (v_cnt < V_SYNCLEN) ? 1'b0 : 1'b1;
DE_o <= (h_cnt >= H_SYNCLEN+H_BACKPORCH) & (h_cnt < H_SYNCLEN+H_BACKPORCH+H_ACTIVE) & (v_cnt >= V_SYNCLEN+V_BACKPORCH) & (v_cnt < V_SYNCLEN+V_BACKPORCH+V_ACTIVE);
xpos_o <= (h_cnt - H_SYNCLEN - H_BACKPORCH);
ypos_o <= (v_cnt - V_SYNCLEN - V_BACKPORCH);
datavalid_o <= (h_ctr == H_SAMPLE_SEL);
end
R_i_prev <= R_i;
G_i_prev <= G_i;
B_i_prev <= B_i;
HSYNC_i_prev <= HSYNC_i;
VSYNC_i_prev <= VSYNC_i;
DE_i_prev <= DE_i;
end
endmodule
| 8.635282 |
module takes in the coordinates of a motor and the object. It calculates the distance between them. The distance will be used as length of rope.
//All coordinates are assumed to be positive
//clk, en and comp_sig are as in multiplication
//coor_mot_i is the ith component of the motor location.
//Restrict coor_obj_i to be 31 bits and NOT 32 bits. This is to remove the overflow condition.
module len_calc(input clk, input en, input [31:0] coor_mot_x, coor_mot_y, coor_mot_z, input [31:0] coor_obj_x, coor_obj_y, coor_obj_z, output [31:0] len, output reg comp_sig);
reg count; //State variable used later
//Defining the enable pins and completion flags
wire comp_x, comp_y, comp_z, sq_comp; reg en_mult, en_sq;
initial begin
en_mult<=0;
en_sq<=0;
end
wire comp_mult = comp_x & comp_y & comp_z; //Completion flag of all multiplications
reg en_hist; //Used for detecting positive edges of en
reg [2:0] clk_factor; initial clk_factor <= 0;
reg clk_div; initial clk_div<=0; //This is a slowed down clock. It is required for synchronization with squareroot
always @(negedge clk) begin
clk_factor<=clk_factor+1;
if (clk_factor==0) clk_div<=~clk_div;
end
always @(negedge clk_div) begin
en_hist<=en;
if (en && (~en_hist)) begin
//Initialization
en_mult<=1;
count<=0;
comp_sig<=0;
end else begin
case (count)
0: begin
//Wait for the multiplication to get over.
if (comp_mult) begin
count<=count+1;
en_sq<=1; //Trigger the squareroot calculation
en_mult<=0;
end
end
1: begin
//Wait for the squareroot calculation to get over.
if (sq_comp) begin
comp_sig<=1;
en_sq<=0;
end
end
endcase
end
end
//Instantiating multiplier and squareroot modules
wire [63:0] len_squared;
wire [31:0] coor_diff_x; assign coor_diff_x = coor_obj_x - coor_mot_x;
wire [31:0] coor_diff_y; assign coor_diff_y = coor_obj_y - coor_mot_y;
wire [31:0] coor_diff_z; assign coor_diff_z = coor_obj_z - coor_mot_z;
wire [63:0] coor_diff_x_squared; multiplier multx(clk,1,coor_diff_x,coor_diff_x,en_mult,coor_diff_x_squared,comp_x);
wire [63:0] coor_diff_y_squared; multiplier multy(clk,1,coor_diff_y,coor_diff_y,en_mult,coor_diff_y_squared,comp_y);
wire [63:0] coor_diff_z_squared; multiplier multz(clk,1,coor_diff_z,coor_diff_z,en_mult,coor_diff_z_squared,comp_z);
assign len_squared = coor_diff_x_squared + coor_diff_y_squared + coor_diff_z_squared;
squareroot sqlen(clk,len_squared,len,en_sq,sq_comp);
endmodule
| 9.560589 |
module PWM_timer (
input clk,
input [4:0] speed,
input en,
output out,
output dirp,
dirn
);
reg [4:0] speed_copy;
initial speed_copy <= 0;
reg outlogic;
initial
outlogic<=0;//This is the output of the logic circuit. It has to be multiplexed with 0 depending on en
assign out = (en ? outlogic : 0); //If en is off, out=0
reg [3:0] count;
initial count <= 0; //Keeping a count of the cycles elapsed
always @(negedge count[3])
speed_copy <= (speed[4] ? ~speed[3:0] + 1 : speed[3:0]); //Latching speed
always @(negedge clk) begin
count <= count + 1;
if (count == 0 && speed_copy[3:0] != 0) begin
outlogic <= 1;
end else if (count == speed_copy[3:0]) begin
outlogic <= 0;
end
end
//Direction of rotation depending on the sign of speed and whether speed is 0 or not.
assign dirp = ((speed == 0) ? 1'b1 : (~speed_copy[4]));
assign dirn = ((speed == 0) ? 1'b1 : (speed_copy[4]));
endmodule
| 6.692341 |
module is used for testing the connection of four motors
//des_roti are taken to be 3 bit for input convenience. The actual rotation values are des_roti*8.
//dir[i] gives the direction of rotation of motor_i
//pulses[i] is the input from encoder values of motor_i
//PWM=0 stops all the motors
//sig_to_mot, dirp, dirn provides the PWM signals to motors
//Rest of the signals are only for debugging purposes and will be mentioned in the code
module fourmot_testing (input clk, input en, input [2:0] des_rot0, des_rot1, des_rot2, des_rot3, input [3:0] dir, input [3:0] pulses, input PWM, output [3:0] sig_to_mot, dirp, dirn, output [8:0] count_pulse, output reg [1:0] pulse_state, input pulse_change, output reg [3:0] en_controller, output reg state);
//Button pulse_change will increase pulse_state by 1
initial pulse_state<=0;
wire [8:0] pulse01, pulse23, count_pulse_NE, count_pulse_NW, count_pulse_SE, count_pulse_SW;
//Implementing a 4x1 mux
assign count_pulse = (pulse_state[1] ? pulse23 : pulse01);
assign pulse01 = (pulse_state[0] ? count_pulse_NW : count_pulse_NE);
assign pulse23 = (pulse_state[0] ? count_pulse_SW : count_pulse_SE);
always @(posedge pulse_change) pulse_state<=pulse_state+1;
/*reg [3:0] en_controller;*/ initial en_controller<=0;
reg [3:0] en_timer; initial en_timer<=0;
wire clk_calc, clk_PWM; assign clk_calc = clk; assign clk_PWM = clk;
wire [4:0] speed0, speed1, speed2, speed3; wire [3:0] comp_cont;
wire [31:0] des_rot0_inp, des_rot1_inp, des_rot2_inp, des_rot3_inp;
assign des_rot0_inp = {24'h0,des_rot0,3'h0};
assign des_rot1_inp = {24'h0,des_rot1,3'h0};
assign des_rot2_inp = {24'h0,des_rot2,3'h0};
assign des_rot3_inp = {24'h0,des_rot3,3'h0};
//controller gives the speed of the rope given the measured and desired lengths.
controller mot_control_mod_NE(clk_calc, en_controller[0], des_rot0_inp, dir[0], pulses[0], speed0, comp_cont[0], count_pulse_NE);
controller mot_control_mod_NW(clk_calc, en_controller[1], des_rot1_inp, dir[1], pulses[1], speed1, comp_cont[1], count_pulse_NW);
controller mot_control_mod_SE(clk_calc, en_controller[2], des_rot2_inp, dir[2], pulses[2], speed2, comp_cont[2], count_pulse_SE);
controller mot_control_mod_SW(clk_calc, en_controller[3], des_rot3_inp, dir[3], pulses[3], speed3, comp_cont[3], count_pulse_SW);
//PWM_timer converts the speed variable into PWM signal to be sent to motors
PWM_timer mot_timer_mod_NE(clk_PWM, speed0, (en_timer[0] & PWM), sig_to_mot[0], dirp[0], dirn[0]);
PWM_timer mot_timer_mod_NW(clk_PWM, speed1, (en_timer[1] & PWM), sig_to_mot[1], dirp[1], dirn[1]);
PWM_timer mot_timer_mod_SE(clk_PWM, speed2, (en_timer[2] & PWM), sig_to_mot[2], dirp[2], dirn[2]);
PWM_timer mot_timer_mod_SW(clk_PWM, speed3, (en_timer[3] & PWM), sig_to_mot[3], dirp[3], dirn[3]);
//reg state;
initial state<=0;
wire [3:0] len_diff = dir;
reg state_en; initial state_en<=0;
reg en_hist; initial en_hist<=0;
always @(negedge clk) begin
en_hist<=en;
case (state)
0: begin
en_controller<=4'h0; en_timer<=4'h0;
if (en && ~en_hist) begin
state<=1;
end
end
1: begin
en_controller<=4'hF; en_timer<=4'hF;
if (&comp_cont | ~en) state<=0;
end
endcase
end
endmodule
| 7.142307 |
module PAGE6 ();
//: interface /sz:(40, 40) /bd:[ ] /pd: 0 /pi: 0 /pe: 0 /pp: 1
wire w23; //: /sn:0 {0}(309,247)(319,247){1}
wire w24; //: /sn:0 {0}(319,194)(254,194){1}
//: {2}(252,192)(252,134)(318,134){3}
//: {4}(250,194)(187,194){5}
wire w25; //: /sn:0 {0}(334,134)(344,134){1}
wire w22; //: /sn:0 {0}(156,196)(166,196){1}
wire w10; //: /sn:0 {0}(156,191)(166,191){1}
wire w27; //: /sn:0 {0}(335,247)(345,247){1}
wire w26; //: /sn:0 {0}(335,194)(345,194){1}
//: enddecls
//: comment g4 @(10,310) /sn:0
//: /line:"<tutorial-navigation>"
//: /end
_GGBUF #(4) g28 (
.I(w24),
.Z(w26)
); //: @(325,194) /sn:0 /w:[ 0 0 ]
//: joint g27 (w24) @(252, 194) /w:[ 1 2 4 -1 ]
//: comment g9 @(10,9) /anc:1
//: /line:"<h3>Wire Editing</h3> <b>(Joint Creation)</b>"
//: /line:""
//: /line:"Now try the same thing again, but this time drop the inverter input closer to the AND gate output"
//: /line:"away from the joint. This time a new joint is automatically created."
//: /line:""
//: /end
_GGNBUF #(2) g29 (
.I(w23),
.Z(w27)
); //: @(325,247) /sn:0 /w:[ 1 0 ]
_GGAND2 #(6) g25 (
.I0(w10),
.I1(w22),
.Z (w24)
); //: @(177,194) /sn:0 /w:[ 1 1 5 ] /eb:0
_GGBUF #(4) g26 (
.I(w24),
.Z(w25)
); //: @(324,134) /sn:0 /w:[ 3 0 ]
endmodule
| 6.504761 |
module PAGE3 ();
//: interface /sz:(40, 40) /bd:[ ] /pd: 0 /pi: 0 /pe: 0 /pp: 1
wire w4; //: /sn:0 {0}(131,166)(141,166){1}
wire w0; //: /sn:0 {0}(131,161)(141,161){1}
wire w1; //: /sn:0 {0}(171,176)(171,201)(285,201)(285,164)(237,164)(237,144)(193,144)(193,164)(162,164){1}
//: enddecls
//: comment g4 @(10,310) /sn:0 /anc:1
//: /line:"<tutorial-navigation>"
//: /end
_GGXOR2 #(8) g8 (
.I0(w0),
.I1(w4),
.Z (w1)
); //: @(152,164) /sn:0 /w:[ 1 1 1 ] /eb:0
//: comment g9 @(10,10) /anc:1
//: /line:"<h3>Wire Editing</h3> <b>(Automatic Loop Deletion)</b>"
//: /line:""
//: /line:"Grab the endpoint of the XOR output wire in the circuit below. Drag it up until it crosses the"
//: /line:"horizontal segment next to the gate and release it. TkGate will automatically remove the loop."
//: /line:""
//: /end
endmodule
| 6.512788 |
module PAGE10 ();
//: interface /sz:(40, 40) /bd:[ ] /pd: 0 /pi: 0 /pe: 0 /pp: 1
reg crete; //: {0}(7:215,136)(359,136)(359,189){1}
//: {2}(361,191)(416,191){3}
//: {4}(359,193)(359,203){5}
reg ithaca; //: {0}(18:215,183)(259,183){1}
//: {2}(263,183)(271,183){3}
//: {4}(261,185)(261,238)(278,238){5}
reg toledo; //: {0}(-21:213,243)(254,243){1}
//: {2}(258,243)(278,243){3}
//: {4}(256,241)(256,188)(271,188){5}
wire styx; //: {0}(99:355,275)(355,295){1}
wire athens; //: {0}(416,186)(356,186){1}
//: {2}(71:352,186)(292,186){3}
//: {4}(354,188)(354,203){5}
wire pheneos; //: {0}(76:357,224)(357,254){1}
wire olympus; //: {0}(-15:437,189)(506,189){1}
wire delphi; //: {0}(-22:299,241)(352,241)(352,254){1}
//: enddecls
//: comment g4 @(10,310) /sn:0 /anc:1
//: /line:"<tutorial-navigation>"
//: /end
//: LED g37 (olympus) @(513,189) /sn:0 /R:3 /w:[ 1 ] /type:0
_GGXOR2 #(8) Athena (
.I0(ithaca),
.I1(toledo),
.Z (athens)
); //: @(282,186) /w:[ 3 5 3 ] /eb:0
_GGNAND2 #(4) Hermes (
.I0(athens),
.I1(crete),
.Z (pheneos)
); //: @(357,214) /R:3 /w:[ 5 5 0 ] /eb:0
_GGNAND2 #(4) Hades (
.I0(delphi),
.I1(pheneos),
.Z (styx)
); //: @(355,265) /R:3 /w:[ 1 1 0 ] /eb:0
_GGXOR2 #(8) Zeus (
.I0(athens),
.I1(crete),
.Z (olympus)
); //: @(427,189) /w:[ 0 3 0 ] /eb:0
//: joint g32 (athens) @(354, 186) /w:[ 1 -1 2 4 ]
//: comment g9 @(10,10) /anc:1
//: /line:"<h3>Wire Editing</h3> <b>(Search)</b>"
//: /line:""
//: /line:"You can search your circuit for a wire or gate with a specific name by using the search tool. Click"
//: /line:"on the <img src=edit_find.gif bgcolor=gray> tool to open it. The list of matches will by dynamically updated as you type the target"
//: /line:"string. Double click on an entry in the <font color=red2>Search Results</font> to go to that object. Try using the search"
//: /line:"tool to search for some of the wire and gate names in the circuit below."
//: /line:""
//: /end
//: joint g29 (ithaca) @(261, 183) /w:[ 2 -1 1 4 ]
//: SWITCH Bob (toledo) @(196,243) /w:[ 0 ] /st:0 /dn:0
//: SWITCH Thesus (crete) @(198,136) /w:[ 0 ] /st:0 /dn:0
_GGNAND2 #(4) Apollo (
.I0(ithaca),
.I1(toledo),
.Z (delphi)
); //: @(289,241) /w:[ 5 3 0 ] /eb:0
//: SWITCH Odyseus (ithaca) @(198,183) /w:[ 0 ] /st:0 /dn:0
//: comment g0 @(588,148) /sn:0
//: /line:"<font color=green4>Hint: The search tool will look"
//: /line:"in all modules of your circuit for"
//: /line:"the target string. Try searching for"
//: /line:"a gate named \"hari\".</font>"
//: /end
//: joint g33 (crete) @(359, 191) /w:[ 2 1 -1 4 ]
//: joint g30 (toledo) @(256, 243) /w:[ 2 4 1 -1 ]
endmodule
| 6.533435 |
module AdvCounter (
clk,
reset,
add,
sub,
anode,
cathodes,
count,
dp
);
input clk;
input reset;
input add;
input sub;
output reg [6:0] cathodes;
output reg [3:0] anode;
output [15:0] count;
output dp;
reg [15:0] count;
reg reset_debounced;
reg add_reg1;
reg add_reg2;
reg sub_reg1;
reg sub_reg2;
always @(posedge clk) add_reg1 <= add;
always @(posedge clk) add_reg2 <= add_reg1;
wire add_click = add_reg1 && !add_reg2;
always @(posedge clk) sub_reg1 <= sub;
always @(posedge clk) sub_reg2 <= sub_reg1;
wire sub_click = sub_reg1 && !sub_reg2;
always @(posedge clk)
if (reset) count = 0;
else if (add_click) count = count + 1;
else if (sub_click) count = count - 1;
else count = count;
//reg [15:0] answer; // 16 bit number to be displayed
reg [39:0] counter;
always @(posedge clk)
if (reset_debounced) counter <= 0;
else counter <= counter + 1;
wire anode_clk = (counter[15:0] == 16'h8000);
always @(posedge clk)
if (reset) anode <= 4'b0111;
else if (anode_clk) anode <= {anode[0], anode[3:1]}; // rotate
else anode <= anode;
reg [3:0] cathode_select;
always @(anode or count)
case ({
anode
})
4'b0111: cathode_select = count[15:12];
4'b1011: cathode_select = count[11:8];
4'b1101: cathode_select = count[7:4];
4'b1110: cathode_select = count[3:0];
default: cathode_select = 4'h0;
endcase
wire dp = 1; //!(anodes == 4'b1011);
always @(cathode_select or dp)
case (cathode_select)
4'h0: cathodes = {7'b0000_001};
4'h1: cathodes = {7'b1001_111};
4'h2: cathodes = {7'b0010_010};
4'h3: cathodes = {7'b0000_110};
4'h4: cathodes = {7'b1001_100};
4'h5: cathodes = {7'b0100_100};
4'h6: cathodes = {7'b1100_000};
4'h7: cathodes = {7'b0001_111};
4'h8: cathodes = {7'b0000_000};
4'h9: cathodes = {7'b0001_100};
4'ha: cathodes = {7'b0001_000};
4'hb: cathodes = {7'b1100_000};
4'hc: cathodes = {7'b0110_001};
4'hd: cathodes = {7'b1000_010};
4'he: cathodes = {7'b0110_000};
4'hf: cathodes = {7'b0111_000};
endcase
endmodule
| 7.035026 |
module adv_debug_sys ( // JTAG signals
input tck_i,
input tdi_i,
output tdo_o,
input rst_i,
// TAP states
input shift_dr_i,
input pause_dr_i,
input update_dr_i,
input capture_dr_i,
// Module select from TAP
input debug_select_i,
input wb_clk_i,
input wb_rst_i,
output [31:0] wb_adr_o,
output [31:0] wb_dat_o,
input [31:0] wb_dat_i,
output wb_cyc_o,
output wb_stb_o,
output [3:0] wb_sel_o,
output wb_we_o,
input wb_ack_i,
output wb_cab_o,
input wb_err_i,
output [2:0] wb_cti_o,
output [1:0] wb_bte_o,
// CPU signals
input cpu0_clk_i,
output [31:0] cpu0_addr_o,
input [31:0] cpu0_data_i,
output [31:0] cpu0_data_o,
input cpu0_bp_i,
output cpu0_stall_o,
output cpu0_stb_o,
output cpu0_we_o,
input cpu0_ack_i,
output cpu0_rst_o,
input cpu1_clk_i,
output [31:0] cpu1_addr_o,
input [31:0] cpu1_data_i,
output [31:0] cpu1_data_o,
input cpu1_bp_i,
output cpu1_stall_o,
output cpu1_stb_o,
output cpu1_we_o,
input cpu1_ack_i,
output cpu1_rst_o,
input [31:0] wb_jsp_adr_i,
output [31:0] wb_jsp_dat_o,
input [31:0] wb_jsp_dat_i,
input wb_jsp_cyc_i,
input wb_jsp_stb_i,
input [3:0] wb_jsp_sel_i,
input wb_jsp_we_i,
output wb_jsp_ack_o,
input wb_jsp_cab_i,
output wb_jsp_err_o,
input [2:0] wb_jsp_cti_i,
input [1:0] wb_jsp_bte_i,
output int_o
);
adbg_top adbg_top ( //JTAG
.tck_i(tck_i),
.tdi_i(tdi_i),
.tdo_o(tdo_o),
.rst_i(rst_i),
// TAP states
.shift_dr_i (shift_dr_i),
.pause_dr_i (pause_dr_i),
.update_dr_i (update_dr_i),
.capture_dr_i(capture_dr_i),
// Module select from TAP
.debug_select_i(debug_select_i),
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wb_adr_o(wb_adr_o),
.wb_dat_o(wb_dat_o),
.wb_dat_i(wb_dat_i),
.wb_cyc_o(wb_cyc_o),
.wb_stb_o(wb_stb_o),
.wb_sel_o(wb_sel_o),
.wb_we_o (wb_we_o),
.wb_ack_i(wb_ack_i),
.wb_cab_o(wb_cab_o),
.wb_err_i(wb_err_i),
.wb_cti_o(wb_cti_o),
.wb_bte_o(wb_bte_o),
// CPU signals
.cpu0_clk_i (cpu0_clk_i),
.cpu0_addr_o (cpu0_addr_o),
.cpu0_data_i (cpu0_data_i),
.cpu0_data_o (cpu0_data_o),
.cpu0_bp_i (cpu0_bp_i),
.cpu0_stall_o(cpu0_stall_o),
.cpu0_stb_o (cpu0_stb_o),
.cpu0_we_o (cpu0_we_o),
.cpu0_ack_i (cpu0_ack_i),
.cpu0_rst_o (cpu0_rst_o),
.wb_jsp_adr_i(wb_jsp_adr_i),
.wb_jsp_dat_o(wb_jsp_dat_o),
.wb_jsp_dat_i(wb_jsp_dat_i),
.wb_jsp_cyc_i(wb_jsp_cyc_i),
.wb_jsp_stb_i(wb_jsp_stb_i),
.wb_jsp_sel_i(wb_jsp_sel_i),
.wb_jsp_we_i (wb_jsp_we_i),
.wb_jsp_ack_o(wb_jsp_ack_o),
.wb_jsp_cab_i(wb_jsp_cab_i),
.wb_jsp_err_o(wb_jsp_err_o),
.wb_jsp_cti_i(wb_jsp_cti_i),
.wb_jsp_bte_i(wb_jsp_bte_i),
.int_o (int_o)
);
endmodule
| 7.178335 |
module adv_instr(
instr,
regs,
regt,
result
);
input [32-1:0] instr;
input signed [32-1:0] regs;
input signed [32-1:0] regt;
output reg signed [32-1:0] result;
//disposable registers
reg signed [5-1:0] shamt;
reg [16-1:0] imm;
reg [32-1:0] ext_imm;
always@(*)
begin
shamt = instr[10:6];
imm = instr[15:0];
if(instr[15]==1'b1)
ext_imm = {16'b1111111111111111,instr[15:0]};
else
ext_imm = {16'b0000000000000000,instr[15:0]};
case(instr[31:26]) //case based on OP field
6'b000000:
begin
if(instr[5:0] == 6'b000011) //SRA
result = regt >>> shamt;
else //SRAV
result = regt >>> regs;
end
6'b001111: //LUI
result = (imm*(2**16));
6'b001101: //ORI
result = regs | ext_imm;
endcase
end
endmodule
| 7.665517 |
module adv_instr_sel (
op_field_i,
function_field_i,
select
);
input [6-1:0] op_field_i;
input [6-1:0] function_field_i;
output reg select;
always @(*) begin
if ((op_field_i == 6'b000000) && (function_field_i == 6'b000011)) select = 1;
else if ((op_field_i == 6'b000000) && (function_field_i == 6'b000111)) select = 1;
else if (op_field_i == 6'b001111) select = 1;
else if (op_field_i == 6'b001101) select = 1;
else if (op_field_i == 6'b000101) select = 1;
else select = 0;
end
endmodule
| 6.975297 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
//
// A 4-wire to 3-wire SPI converter, supporting maximum 8 slaves.
// The expected transfer format is defined in ADI_SPI technical specification
// (https://wiki.analog.com/_media/resources/technical-guides/adispi_rev_1p0_customer.pdf)
//
// 16 bit instruction followed by N x 8 bits of data; the MSB bit of the
// instruction defines the direction of the SDIO during data transfer. (READ
// is 1 and WRITE is 0)
//
module ad_3w_spi #(
parameter NUM_OF_SLAVES=8) (
input [NUM_OF_SLAVES-1:0] spi_csn,
input spi_clk,
input spi_mosi,
output spi_miso,
inout spi_sdio,
output spi_dir);
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = & spi_csn;
assign spi_dir = ~spi_enable_s;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
assign spi_miso = spi_sdio;
assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// A simple adder/substracter width preconfigured input ports width and turn-around value
// Output = A - B_constant or A + B_constant
// Constraints: Awidth >= Bwidth
`timescale 1ns/1ps
module ad_addsub #(
parameter A_DATA_WIDTH = 32,
parameter B_DATA_VALUE = 32'h1,
parameter ADD_OR_SUB_N = 0) (
input clk,
input [(A_DATA_WIDTH-1):0] A,
input [(A_DATA_WIDTH-1):0] Amax,
output reg [(A_DATA_WIDTH-1):0] out,
input CE);
localparam ADDER = 1;
localparam SUBSTRACTER = 0;
// registers
reg [A_DATA_WIDTH:0] out_d = 'b0;
reg [A_DATA_WIDTH:0] out_d2 = 'b0;
reg [(A_DATA_WIDTH-1):0] A_d = 'b0;
reg [(A_DATA_WIDTH-1):0] Amax_d = 'b0;
reg [(A_DATA_WIDTH-1):0] Amax_d2 = 'b0;
// constant regs
reg [(A_DATA_WIDTH-1):0] B_reg = B_DATA_VALUE;
// latch the inputs
always @(posedge clk) begin
A_d <= A;
Amax_d <= Amax;
Amax_d2 <= Amax_d;
end
// ADDER/SUBSTRACTER
always @(posedge clk) begin
if ( ADD_OR_SUB_N == ADDER ) begin
out_d <= A_d + B_reg;
end else begin
out_d <= A_d - B_reg;
end
end
// Resolve
always @(posedge clk) begin
if ( ADD_OR_SUB_N == ADDER ) begin
if ( out_d > Amax_d2 ) begin
out_d2 <= out_d - Amax_d2;
end else begin
out_d2 <= out_d;
end
end else begin // SUBSTRACTER
if ( out_d[A_DATA_WIDTH] == 1'b1 ) begin
out_d2 <= Amax_d2 + out_d;
end else begin
out_d2 <= out_d;
end
end
end
// output logic
always @(posedge clk) begin
if ( CE ) begin
out <= out_d2;
end else begin
out <= 'b0;
end
end
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_adl5904_rst (
input sys_cpu_clk,
input rf_peak_det_n,
output rf_peak_rst);
// internal registers
reg rf_peak_det_n_d = 'd0;
reg rf_peak_det_enb_d = 'd0;
reg rf_peak_rst_enb = 'd0;
reg rf_peak_rst_int = 'd0;
// internal signals
wire rf_peak_det_enb_s;
wire rf_peak_rst_1_s;
wire rf_peak_rst_0_s;
// adl5904 input protection
assign rf_peak_rst = rf_peak_rst_int;
assign rf_peak_det_enb_s = ~(rf_peak_det_n_d & rf_peak_det_n);
assign rf_peak_rst_1_s = ~rf_peak_det_enb_d & rf_peak_det_enb_s;
assign rf_peak_rst_0_s = rf_peak_det_enb_d & ~rf_peak_det_enb_s;
always @(posedge sys_cpu_clk) begin
rf_peak_det_n_d <= rf_peak_det_n;
rf_peak_det_enb_d <= rf_peak_det_enb_s;
if (rf_peak_rst_1_s == 1'b1) begin
rf_peak_rst_enb <= 1'b1;
end else if (rf_peak_rst_0_s == 1'b1) begin
rf_peak_rst_enb <= 1'b0;
end
rf_peak_rst_int = ~rf_peak_rst_int & rf_peak_rst_enb;
end
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_b2g #(
parameter DATA_WIDTH = 8) (
input [DATA_WIDTH-1:0] din,
output [DATA_WIDTH-1:0] dout);
function [DATA_WIDTH-1:0] b2g;
input [DATA_WIDTH-1:0] b;
integer i;
begin
b2g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
for (i = DATA_WIDTH-1; i > 0; i = i -1) begin
b2g[i-1] = b[i] ^ b[i-1];
end
end
endfunction
assign dout = b2g(din);
endmodule
| 8.180735 |
module ad_buf (
// inputs:
a2dc,
adclk,
addr,
cs_n,
rd,
rdclk,
rst_n,
wrclk,
// outputs:
a2do,
waitreq
);
output [31:0] a2do;
output waitreq;
input [11:0] a2dc;
input adclk;
input [11:0] addr;
input cs_n;
input rd;
input rdclk;
input rst_n;
input wrclk;
wire [31:0] a2do;
wire waitreq;
adBUF the_adBUF (
.a2dc (a2dc),
.a2do (a2do),
.adclk (adclk),
.addr (addr),
.cs_n (cs_n),
.rd (rd),
.rdclk (rdclk),
.rst_n (rst_n),
.waitreq(waitreq),
.wrclk (wrclk)
);
defparam the_adBUF.BUFFER0 = 1, the_adBUF.BUFFER1 = 2, the_adBUF.INITIAL = 0;
endmodule
| 6.518388 |
module ad_buff #(
parameter DSIZE = 8,
parameter DATA_DELAY_CLKS = 4'd8
) (
input i_ad_clk,
i_st,
i_rst_n,
input [DSIZE-1:0] i_ad_data,
input [15:0] i_recv_count,
output [ODSIZE-1:0] o_dual_data,
output o_data_on,
output o_working
);
localparam ODSIZE = DSIZE * 2;
reg [15:0] cnt;
reg st, working, ready, data_on;
reg [ODSIZE-1:0] dual_data;
assign o_dual_data = dual_data;
assign o_data_on = data_on;
assign o_working = working;
always @(posedge i_ad_clk or negedge i_rst_n)
if (!i_rst_n) begin
st <= 0;
working <= 0;
end else begin
st <= i_st;
if (i_st && !st) working <= 1;
if (cnt == i_recv_count + DATA_DELAY_CLKS) working <= 0;
end
always @(posedge i_ad_clk or negedge i_rst_n)
if (!i_rst_n) begin
cnt <= 0;
dual_data <= 0;
end else begin
if (working) begin
cnt <= cnt + 1'b1;
dual_data <= {dual_data[ODSIZE-DSIZE-1:0], i_ad_data};
end else cnt <= 0;
end
always @(posedge i_ad_clk or negedge i_rst_n)
if (!i_rst_n) ready <= 0;
else begin
if (working) begin
if (cnt == DATA_DELAY_CLKS + 1'b1) ready <= 1;
end else ready <= 0;
end
always @(posedge i_ad_clk or negedge i_rst_n)
if (!i_rst_n) data_on <= 0;
else begin
if (ready) data_on <= ~data_on;
else data_on <= 0;
end
endmodule
| 7.53117 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_bus_mux #(
// Channel data width
parameter DATA_WIDTH = 16) (
input select_path,
input valid_in_0,
input enable_in_0,
input [DATA_WIDTH-1:0] data_in_0,
input valid_in_1,
input enable_in_1,
input [DATA_WIDTH-1:0] data_in_1,
output valid_out,
output enable_out,
output [DATA_WIDTH-1:0] data_out);
assign valid_out = (select_path == 0) ? valid_in_0 : valid_in_1;
assign enable_out = (select_path == 0) ? enable_in_0 : enable_in_1;
assign data_out = (select_path == 0) ? data_in_0 : data_in_1;
endmodule
| 8.180735 |
module ad_cache (
en,
sync,
spclk,
wclk,
wr,
wdata,
rclk,
rd,
rdata,
switch
);
////////////////// PORT ////////////////////
input en;
input sync;
input spclk;
input wclk;
input wr;
input [`AD_DATA_NBIT-1:0] wdata;
input rclk;
input rd;
output [`AD_DATA_NBIT-1:0] rdata;
output switch;
////////////////// ARCH ////////////////////
////////////////// WRITE
reg [`AD_CHE_ADDR_NBIT-1:0] waddr;
reg wswitch;
reg buf_wr;
reg [ `AD_CHE_ADDR_NBIT:0] buf_waddr;
reg [ `AD_DATA_NBIT-1:0] buf_wdata;
reg prev_sync;
reg prev_spclk;
reg [ `AD_SP_NBIT-1:0] spwr_cnt;
reg [ `AD_SP_NBIT-1:0] spclk_cnt;
always @(posedge wclk) begin
prev_sync <= sync;
prev_spclk<= spclk;
buf_wr <= `LOW;
buf_waddr <= {wswitch,waddr};
buf_wdata <= wdata;
if (en) begin
if (wr && (spclk_cnt >= `AD_SP_START_IDX) && (spwr_cnt < `AD_SP_NUM)) begin
buf_wr <= `HIGH;
spwr_cnt <= spwr_cnt + 1'b1;
end
if ((spclk & ~prev_spclk) && (spclk_cnt < `AD_SP_START_IDX)) spclk_cnt <= spclk_cnt + 1'b1;
if (sync & ~prev_sync) begin // reset counter at the posedge of SYNC
spwr_cnt <= 0;
spclk_cnt <= 0;
end
if (buf_wr) begin
waddr <= waddr + 1'b1;
if (waddr == `AD_CHE_DATA_SIZE - 1) begin
waddr <= 0;
wswitch <= ~wswitch;
end
end
end else begin
waddr <= 0;
spwr_cnt <= {`AD_SP_NBIT{1'b1}};
spclk_cnt <= 0;
end
end
////////////////// PING PANG BUFFER
buffered_ram_tdp #(`AD_CHE_ADDR_NBIT + 1, `AD_DATA_NBIT) pingpang_cache (
.a_inclk (wclk),
.a_in_wren (buf_wr),
.a_in_address(buf_waddr),
.a_in_wrdata (buf_wdata),
.a_out_rddata(),
.b_inclk (rclk),
.b_in_wren (`LOW),
.b_in_address(buf_raddr),
.b_in_wrdata (0),
.b_out_rddata(rdata)
);
////////////////// READ
reg [ 2:0] pp_wswitch;
reg switch;
reg [`AD_CHE_ADDR_NBIT-1:0] raddr;
wire [ `AD_CHE_ADDR_NBIT:0] buf_raddr;
assign buf_raddr = {~pp_wswitch[2], raddr};
always @(posedge rclk) begin
pp_wswitch <= {pp_wswitch[1:0], wswitch};
switch <= ^pp_wswitch[2:1];
if (switch) raddr <= 0;
else if (rd) raddr <= raddr + 1'b1;
end
endmodule
| 7.976409 |
module ad_cmos_out (
// data interface
tx_clk,
tx_data_p,
tx_data_n,
tx_data_out,
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
// delay-cntrl interface
delay_clk,
delay_rst,
delay_locked
);
// parameters
parameter DEVICE_TYPE = 0;
parameter SINGLE_ENDED = 0;
parameter IODELAY_ENABLE = 0;
parameter IODELAY_CTRL = 0;
parameter IODELAY_GROUP = "dev_if_delay_group";
localparam SERIES7 = 0;
localparam VIRTEX6 = 1;
// data interface
input tx_clk;
input tx_data_p;
input tx_data_n;
output tx_data_out;
// delay-data interface
input up_clk;
input up_dld;
input [4:0] up_dwdata;
output [4:0] up_drdata;
// delay-cntrl interface
input delay_clk;
input delay_rst;
output delay_locked;
// internal signals
wire tx_data_oddr_s;
wire tx_data_odelay_s;
// delay controller
generate
if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7) && (IODELAY_CTRL == 1)) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYCTRL i_delay_ctrl (
.RST(delay_rst),
.REFCLK(delay_clk),
.RDY(delay_locked)
);
end else begin
assign delay_locked = 1'b1;
end
endgenerate
// transmit data interface, oddr -> odelay -> obuf
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.SRTYPE("ASYNC")
) i_tx_data_oddr (
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.C (tx_clk),
.D1(tx_data_p),
.D2(tx_data_n),
.Q (tx_data_oddr_s)
);
generate
if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7)) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
ODELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("ODATAIN"),
.HIGH_PERFORMANCE_MODE("FALSE"),
.ODELAY_TYPE("VAR_LOAD"),
.ODELAY_VALUE(0),
.REFCLK_FREQUENCY(200.0),
.PIPE_SEL("FALSE"),
.SIGNAL_PATTERN("DATA")
) i_tx_data_odelay (
.CE(1'b0),
.CLKIN(1'b0),
.INC(1'b0),
.LDPIPEEN(1'b0),
.CINVCTRL(1'b0),
.REGRST(1'b0),
.C(up_clk),
.ODATAIN(tx_data_oddr_s),
.DATAOUT(tx_data_odelay_s),
.LD(up_dld),
.CNTVALUEIN(up_dwdata),
.CNTVALUEOUT(up_drdata)
);
end else begin
assign up_drdata = 5'd0;
assign tx_data_odelay_s = tx_data_oddr_s;
end
endgenerate
OBUF i_tx_data_obuf (
.I(tx_data_odelay_s),
.O(tx_data_out)
);
endmodule
| 6.842994 |
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