code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module oai21 (
Y,
A0,
A1,
B0
);
output Y;
input A0;
input A1;
input B0;
or (adk113, A0, A1);
and (adk114, adk113, B0);
not (Y, adk114);
endmodule
| 6.561625 |
module oai22 (
Y,
A0,
A1,
B0,
B1
);
output Y;
input A0;
input A1;
input B0;
input B1;
or (adk115, A0, A1);
or (adk116, B0, B1);
and (adk117, adk115, adk116);
not (Y, adk117);
endmodule
| 6.579044 |
module oai322 (
Y,
A0,
A1,
A2,
B0,
B1,
C0,
C1
);
output Y;
input A0;
input A1;
input A2;
input B0;
input B1;
input C0;
input C1;
or (adk136, A0, A1);
or (adk137, adk136, A2);
or (adk138, B0, B1);
and (adk139, adk137, adk138);
or (adk140, C0, C1);
and (adk141, ... | 7.023531 |
module oai332 (
Y,
A0,
A1,
A2,
B0,
B1,
B2,
C0,
C1
);
output Y;
input A0;
input A1;
input A2;
input B0;
input B1;
input B2;
input C0;
input C1;
or (adk147, A0, A1);
or (adk148, adk147, A2);
or (adk149, B0, B1);
or (adk150, adk149, B2);
and (adk151, adk148, ... | 6.981774 |
module oai333 (
Y,
A0,
A1,
A2,
B0,
B1,
B2,
C0,
C1,
C2
);
output Y;
input A0;
input A1;
input A2;
input B0;
input B1;
input B2;
input C0;
input C1;
input C2;
or (adk154, A0, A1);
or (adk155, adk154, A2);
or (adk156, B0, B1);
or (adk157, adk156, B2);
a... | 6.640396 |
module oai422 (
Y,
A0,
A1,
A2,
A3,
B0,
B1,
C0,
C1
);
output Y;
input A0;
input A1;
input A2;
input A3;
input B0;
input B1;
input C0;
input C1;
or (adk162, A0, A1);
or (adk163, adk162, A2);
or (adk164, adk163, A3);
or (adk165, B0, B1);
and (adk166, adk164, ... | 7.226871 |
module oai43 (
Y,
A0,
A1,
A2,
A3,
B0,
B1,
B2
);
output Y;
input A0;
input A1;
input A2;
input A3;
input B0;
input B1;
input B2;
or (adk169, A0, A1);
or (adk170, adk169, A2);
or (adk171, adk170, A3);
or (adk172, B0, B1);
or (adk173, adk172, B2);
and (adk174, ad... | 6.792928 |
module oai44 (
Y,
A0,
A1,
A2,
A3,
B0,
B1,
B2,
B3
);
output Y;
input A0;
input A1;
input A2;
input A3;
input B0;
input B1;
input B2;
input B3;
or (adk175, A0, A1);
or (adk176, adk175, A2);
or (adk177, adk176, A3);
or (adk178, B0, B1);
or (adk179, adk178, B2... | 6.921658 |
module or02 (
Y,
A0,
A1
);
output Y;
input A0;
input A1;
or (Y, A0, A1);
endmodule
| 6.916537 |
module or03 (
Y,
A0,
A1,
A2
);
output Y;
input A0;
input A1;
input A2;
or (adk182, A0, A1);
or (Y, adk182, A2);
endmodule
| 6.726178 |
module or04 (
Y,
A0,
A1,
A2,
A3
);
output Y;
input A0;
input A1;
input A2;
input A3;
or (adk183, A0, A1);
or (adk184, adk183, A2);
or (Y, adk184, A3);
endmodule
| 7.070299 |
module xnor2 (
Y,
A0,
A1
);
output Y;
input A0;
input A1;
xor (adk215, A0, A1);
not (Y, adk215);
endmodule
| 6.713225 |
module xor2 (
Y,
A0,
A1
);
output Y;
input A0;
input A1;
xor (Y, A0, A1);
endmodule
| 7.788927 |
module: adld_hw
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module adld_tb;
// Inputs
reg [2:0] a_late;
reg [2:0] b;
// Outputs
wire [2:0] out;
// Instantiate the Unit Under Te... | 7.026131 |
module AdLib (
input wire clk,
input wire reset_n,
input wire [11:0] port,
input wire [7:0] iodin,
output wire [7:0] iodout,
input wire iowr,
input wire iordin,
output reg iordout,
output wire ready,
output reg [7:0] music
);
assign ready = iordin == iordout;
reg [5:0] io... | 7.101363 |
module AdLibChannel #(
parameter N,
OPN
) (
input wire clk,
input wire [7:0] a,
input wire [7:0] din,
input wire regwr,
input wire distortion,
output reg [15:0] result
);
wire wr_2n = regwr && ({a[7:5], 1'b0} == 4'h2);
wire wr_4n = regwr && ({a[7:5], 1'b0} == 4'h4);
wire wr_6n ... | 6.644425 |
module AdLibOperator (
input wire clk,
input wire [7:0] din,
input wire wr_2n,
input wire wr_4n,
input wire wr_6n,
input wire wr_8n,
input wire wr_En,
input wire play,
output reg [3:0] harmonic,
output reg [1:0] waveform,
output reg [7:0] envelope
);
localparam S_IDLE ... | 6.722143 |
module AdLibRAM (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [9:0] address_a;
input [9:0] address_b;
input clock;
input [17:0] data_a;
input [17:0] data_b;
input wren_a;
input wren_b;
output [17:0] q_a;
output [17:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// s... | 6.505438 |
module Administrador_de_salidas (
input [2:0] RY,
input [7:0] RX,
input [2:0] Num,
input [1:0] Sel_Salidas,
output reg [7:0] o_Dataout,
output reg [7:0] o_Addressdata,
output reg ReadWrite
);
always @* begin
case (Sel_Salidas)
2'b00: begin
o_Dataout <= 0;
o_Addre... | 8.308589 |
module ram_dual_port (
clk,
clken,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteena_a,
byteena_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
... | 8.296277 |
module rom_dual_port (
clk,
clken,
address_a,
address_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
parameter numwords_b = 1'd0;
parameter init_file = "UNUSED.mif";
paramete... | 7.576841 |
module ML605 (
USER_CLOCK,
KEY,
SW,
LED,
LEDG,
UART_RXD,
UART_TXD
);
input USER_CLOCK;
input [4:0] KEY;
input [7:0] SW;
output [7:0] LED;
output [7:0] LEDG;
wire CLOCK_50;
input UART_RXD;
output UART_TXD;
wire clk = CLOCK_50;
wire go = ~KEY[1];
wire reset = ~KEY[0... | 6.767428 |
module de4 (
OSC_50_BANK2,
BUTTON,
LED,
SEG0_D,
SEG1_D
);
input OSC_50_BANK2;
input [1:0] BUTTON;
output [6:0] SEG0_D;
output [6:0] SEG1_D;
output [7:0] LED;
de2 de2_inst (
.CLOCK_50(OSC_50_BANK2),
.LEDG(LED),
.KEY(BUTTON),
.SW(),
.HEX0(SEG0_D),
.HEX1... | 7.073756 |
module de2 (
CLOCK_50,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
LEDG,
UART_RXD,
UART_TXD
);
input CLOCK_50;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
reg [6:0] hex0, hex1, hex2, hex3,... | 7.759103 |
module adpcm_decoder (
input reset,
input clock,
input [ 3:0] in_pcm,
output reg signed [11:0] sample
);
reg signed [11:0] differential_value;
reg signed [6:0] index, delta;
reg [10:0] step, pr_step;
reg [15:0] pcm;
wire signed [11:0] estimat... | 6.977394 |
module ADPLL #(
parameter ACCUM_WIDTH = 12,
parameter PDET_WITH = 8,
parameter BIAS = 12'd76, //biased to 5 MHZ @ 258 MHZ CLOCK
parameter DCO_CC_WIDTH = 9,
//LoopFilter Settings
parameter DYNAMIC_VAL = 0, //set to allow variable control of the filter gains with ki/p_i
parameter ERROR_WIDTH... | 6.67463 |
module ADPLLwNoPDet #(
parameter ACCUM_WIDTH = 12,
parameter PDET_WITH = 8,
parameter BIAS = 12'd76, //5 MHZ @ 258 MHZ CLOCK
parameter DCO_CC_WIDTH = 9,
//LoopFilter
parameter DYNAMIC_VAL = 0,
parameter ERROR_WIDTH = 8,
parameter KP_WIDTH = 3,
parameter KP_FRAC_WIDTH = 1,
parame... | 7.16618 |
module shift #(
parameter LENGTH = 16
) (
input clk,
input in,
input [LENGTH-1:0] cmp,
output out
);
reg [LENGTH-1:0] shift_reg;
always @(posedge clk) shift_reg <= {in, shift_reg[LENGTH-1:1]};
assign out = (shift_reg == cmp);
endmodule
| 8.179253 |
module ADPOR #(
parameter LENGTH = 16
) (
input clk,
output rst_n
);
wire cmp1, cmp2, cmp3, cmp4;
shift reg1 (
.clk(clk),
.in (1'b1),
.cmp({LENGTH{1'b1}}),
.out(cmp1)
);
shift reg2 (
.clk(clk),
.in (1'b0),
.cmp({LENGTH{1'b0}}),
.out(cmp2)
);
shift... | 7.060885 |
module ADPOR_tb;
reg clk;
wire rst_n;
always #5 clk = !clk;
ADPOR MUV (
.clk (clk),
.rst_n(rst_n)
);
initial begin
$dumpfile("adpor.vcd");
$dumpvars;
clk = 0;
// load shift registers with random data to simulate the power on behavior
force MUV.reg1.shift_reg = $urandom ... | 7.307759 |
module ADR (
input CLK,
input [31:0] DataIn,
output reg [31:0] DataOut
);
always @(negedge CLK) DataOut <= DataIn;
endmodule
| 7.329619 |
module addr_norm (
normo,
pcv
);
input [6:0] pcv;
output [6:0] normo;
reg [6:0] ooo;
always @(pcv) begin
ooo <= pcv + 1;
end
assign normo = ooo;
endmodule
| 6.745003 |
module SigGen (
input wire [5:0] clk64
, output wire out
);
parameter TRESHHOLD = 19;
assign out = clk64 <= TRESHHOLD;
endmodule
| 7.541408 |
module linetransmitter (
input clk
, input rst
, input [ADD_WIDTH:0] pixel_count
, input [23:0] pixel
, output [ADD_WIDTH - 1:0] address
, output out
, output done
);
parameter ADD_WIDTH = 8;
localparam RESET = 3'b1xx, DATA_SENDING = 3'b000, RESET_SENDING = 3'b010;
reg [ADD_WIDTH - ... | 7.263059 |
module Adress_Generator (
input rst,
input clk,
input PCSrcE,
input StallF,
input [31:0] PCPlus4F,
input [31:0] PCTargetE,
output reg [31:0] PCF
);
reg [31:0] PCFbar;
always @(*) begin //combinational block so block assignment (=) and not a non-blocking one (<=)
PCFbar =... | 7.73958 |
module adrsExtend (
ads,
extendedads
);
input [6:0] ads;
output [7:0] extendedads;
assign extendedads[6:0] = ads[6:0];
assign extendedads[7] = 0;
endmodule
| 7.566853 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module ADR_DAT_BL (
input BTN,
output wire [1:0] VEL,
output wire [7:0] ADR,
output wire [22:0] DAT
);
wire [4:0] my_nom = 5'b01000; //5'b01000=8 ;
assign ADR = {3'b100, my_nom};
parameter my_dat = 23'h4C6600;
parameter my_VEL = 2'b01; // 50 kBod
wire my_bit_dat = (my_dat[13] ^ BTN);
... | 6.643285 |
module ADR_maker (
in_Clock,
A,
ART,
ARG,
AWT,
AWG,
TOG_inc,
SEL,
dout,
QUAD_inc,
QUAD_out,
QUAD_Z
);
input in_Clock;
wire clk;
input wire [7:0] A;
input wire [7:0] ART;
input wire [7:0] ARG;
input wire [7:0] AWT;
input wire [7:0] AWG;
input wire TOG_in... | 6.948571 |
module adr_MUX2 (
input [5:0] pcadr,
input [31:0] aluout,
input iord,
output reg [31:0] adr
);
always @(*)
if (iord) adr <= aluout;
else adr <= {24'h000000, pcadr, 2'b00};
endmodule
| 6.762896 |
module ADS1201 (
input nReset,
input Clk, // max 8 MHz
input Sync,
output reg [23:0] Output,
output ADC_Clk,
input ADC_Data
);
//----------------------------------------------------------------------------
reg Data;
reg [23:0] Sum [7:0];
reg [ 2:0] Part... | 6.508644 |
module ADS1256_SPI (
input clk,
rst_n,
input go,
input [23:0] wrdat,
output reg [23:0] rddat,
output reg ok,
output reg mosi,
output sclk,
input miso
);
reg [4:0] i;
always @(posedge clk or negedge rst_n)
if (!rst_n) i <= 5'd0;
else if (!go) i <= 5'd0;
else if (i < ... | 7.387249 |
module ads7816 (
input data, //from ad
input clk, //from controller
input rst, //from controller
input convert, //from controller
output flag, //to controller
output wire dclock, //to ad
output reg ... | 6.611652 |
module ads7883 (
input wire clk,
input wire en,
output reg cs,
output reg sck,
input wire sdo,
output reg [11:0] data,
output adc_idle
);
reg [1:0] cnt4 = 2'd0;
reg [3:0] cnt16 = 4'd0;
reg [11:0] data_ = 12'd0;
reg sample_state = 1'b0;
assign adc_idle = sample_state;
always @(po... | 6.785983 |
module ads7883 (
input wire clk,
input wire en,
output reg cs,
output reg sck,
input wire sdo,
output reg [11:0] data
//output adc_idle
);
reg [ 3:0] cnt16 = 4'd0;
reg [11:0] data_ = 12'd0;
always @(posedge clk) begin
if (en) begin
cs <= 1'b0;
cnt16 <= 4'd0;
sck... | 6.785983 |
module ads8332_cfg (
input sys_rest,
input spi_clk,
input ads_start,
input [31:0] ads_in_data,
input ads_data_valid,
input ads_wr_en,
input [ 7:0] ads_cfg_rddr,
output [31:0] ads_rd_parameter,
output ads_out_valid,
input ads8332_spi_start,
o... | 7.37472 |
module ADS8361 (
input i_clk,
input i_reset_n,
input i_adc_data1,
input i_adc_data2,
output o_conv_start,
output reg o_adc_clock
);
reg [ 4:0] counter; //Counter to count number of clocks elapsed
reg [ 7:0] clock_counter; //counter used for main clock division to ADC_Clock
reg [15:0] ch... | 7.306256 |
module tb ( //Waarom is deze module leeg?
);
reg clk;
reg reset;
reg [5:0] tb_count = 0;
wire conv_start;
reg channel;
reg adc_data_A = 0;
reg adc_data_B = 0;
reg [15:0] adc_data_port_A;
reg [15:0] adc_data_port_B;
wire adc_clock;
integer i;
wire channel_0_enable; //Heb ik zo correct ... | 6.952555 |
module ADSR (
clock,
reset,
keyboard_pushed,
attack_value,
decay_value,
sustain_value,
release_value,
wave_out_to_adsr,
adsr_out
);
input clock;
input reset;
input keyboard_pushed;
input [3:0] attack_value, decay_value, sustain_value, release_value;
input [15:0] wave_out_to... | 7.04094 |
module adsr_datapath (
input clock,
input reset_attack,
reset_decay,
reset_release,
input [1:0] adr,
input is_sustain,
input [3:0] attack_value,
decay_value,
sustain_value,
release_value,
input [15:0] wave_out_to_adsr,
output [15:0] adsr_out,
output attack_done,
d... | 7.06164 |
module adsr_modification (
amplitude,
shift_amount,
modified_out
);
input [15:0] amplitude;
input [3:0] shift_amount;
output [15:0] modified_out;
assign modified_out = amplitude >>> shift_amount;
endmodule
| 7.242926 |
module adsr32 (
clk,
GATE,
A,
D,
S,
R,
sout /*, SEG */
);
output reg [31:0] sout; // This is the accumulator/integrator for attack, decay and release
input wire clk; // 50 MHz
input wire GATE; // GATE signal
input wire [31:0] A; // attack rate
input wire [31:0] D; // decay r... | 8.309304 |
module ADSRBench;
reg clock = 0, reset = 1;
reg [1:0] wavetype = 2'b00;
wire [23:0] waveform, wavebuff;
reg [15:0] addr = 0;
wire [7:0] data;
reg [7:0] writedata = 0;
reg readwrite = 0;
reg busclk = 0;
assign data = readwrite == 1 ? writedata : 8'hZZ;
reg scale = 0;
initial begin
$dumpfil... | 8.001604 |
module adsr_mngt (
input clk,
input rst,
input new_sample,
input new_note_pulse,
input release_note_pulse,
input [17:0] sustain_value,
output reg [17:0] volume_d,
input [17:0] volume,
output reg [4:0] state
);
`define ATTACK 3'd1
`define DECAY 3'd2
`define SUSTAIN 3'd3
`defi... | 8.194417 |
module adsr_modification (
amplitude,
shift_amount,
modified_out
);
input [15:0] amplitude;
input [3:0] shift_amount;
output [15:0] modified_out;
assign modified_out = amplitude >>> shift_amount;
endmodule
| 7.242926 |
module decay_rom (
clock,
decay,
sustain,
count_up_to
);
input clock;
input [3:0] decay, sustain;
output reg [31:0] count_up_to;
wire [3:0] shifting_distance;
assign shifting_distance = (4'd15 - sustain);
wire [31:0] out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7,
out_8, out_9, ou... | 6.585931 |
module release_rom (
clock,
myrelease,
sustain,
count_up_to
);
input clock;
input [3:0] myrelease, sustain;
output reg [31:0] count_up_to;
wire [3:0] shifting_distance;
assign shifting_distance = sustain;
wire [31:0] out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7,
out_8, out_9, ou... | 6.728791 |
module distance1_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd12500000;
4'd2: count_up_to = 32'd25000000;
4'd3: count_up_to = 32'd37... | 6.609805 |
module distance2_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd6250000;
4'd2: count_up_to = 32'd12500000;
4'd3: count_up_to = 32'd187... | 6.800165 |
module distance3_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd4166666;
4'd2: count_up_to = 32'd8333333;
4'd3: count_up_to = 32'd1250... | 6.797002 |
module distance4_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd3125000;
4'd2: count_up_to = 32'd6250000;
4'd3: count_up_to = 32'd9375... | 7.202542 |
module distance6_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd2083333;
4'd2: count_up_to = 32'd4166666;
4'd3: count_up_to = 32'd6250... | 6.68687 |
module distance7_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd1785714;
4'd2: count_up_to = 32'd3571428;
4'd3: count_up_to = 32'd5357... | 6.683022 |
module distance8_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd1562500;
4'd2: count_up_to = 32'd3125000;
4'd3: count_up_to = 32'd4687... | 6.898261 |
module distance9_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd1388888;
4'd2: count_up_to = 32'd2777777;
4'd3: count_up_to = 32'd4166... | 6.516716 |
module distance12_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd1041666;
4'd2: count_up_to = 32'd2083333;
4'd3: count_up_to = 32'd312... | 7.034521 |
module distance13_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd961538;
4'd2: count_up_to = 32'd1923076;
4'd3: count_up_to = 32'd2884... | 6.829219 |
module distance14_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd892857;
4'd2: count_up_to = 32'd1785714;
4'd3: count_up_to = 32'd2678... | 7.353782 |
module distance15_rom (
decay_or_release,
count_up_to
);
input [3:0] decay_or_release;
output reg [31:0] count_up_to;
always @(*)
case (decay_or_release)
4'd0: count_up_to = 32'd5;
4'd1: count_up_to = 32'd833333;
4'd2: count_up_to = 32'd1666666;
4'd3: count_up_to = 32'd2500... | 6.615403 |
module ADS_16SPI (
input clk,
rst_n,
input go,
input [15:0] wrdat,
output reg [15:0] rddat,
output reg ok,
output reg mosi,
output sclk,
input miso
);
reg [4:0] i;
always @(posedge clk or negedge rst_n)
if (!rst_n) i <= 5'd0;
else if (!go) i <= 5'd0;
else if (i < 5'... | 8.658111 |
module ADS_24SPI (
input clk,
rst_n,
input go,
input [23:0] wrdat,
output reg [23:0] rddat,
output reg ok,
output reg mosi,
output sclk,
input miso
);
reg [4:0] i;
always @(posedge clk or negedge rst_n)
if (!rst_n) i <= 5'd0;
else if (!go) i <= 5'd0;
else if (i < 5'... | 7.585962 |
module ADS_8SPI (
input clk,
rst_n,
input go,
input [7:0] wrdat,
output reg [7:0] rddat,
output reg ok,
output reg mosi,
output sclk,
input miso
);
reg [4:0] i;
always @(posedge clk or negedge rst_n)
if (!rst_n) i <= 5'd0;
else if (!go) i <= 5'd0;
else if (i < 5'd23... | 8.034163 |
module ads_spi(
//AD一侧的接口;
output SCLK,
output CS,
input DIN,
output DOUT,
input DRDY,
output START,
output RESET,
output PWDN,
//FPGA一侧接口;
input rst_n,//复位低有效；
input clk_50M,//时钟50MHZ;
input CLK_IN,
output CLK_OUT,
output [23:0] data_out,
output data_valid
);
//SPI模块；
... | 7.405376 |
module adtop (
input CLK,
input RST,
input [7:0] din1,
input [7:0] din2,
input valid,
output reg [127:0] dout,
output reg wr_en,
input full
);
localparam counter_top = 3'd7;
reg [2:0] counter;
always @(posedge CLK) begin
if (valid) dout <= {dout[1... | 6.988123 |
module ADV7183B (
nRESET,
LLC1,
P15_8,
SCLK,
SDA
);
parameter NUM_FRAMES = 1;
parameter FRAME_SIZE = 900900;
input wire nRESET;
output reg LLC1;
output wire [15:8] P15_8;
input wire SCLK;
inout wire SDA;
initial begin
LLC1 = 1'b0;
forever #185 LLC1 = ~LLC1;
end
reg [7... | 7.251358 |
module adv7513_driver_top (
input clk,
input clk_hdmi,
input rst_n,
//配置接口
output hdmi_i2c_scl,
inout hdmi_i2c_sda,
input hdmi_tx_int, //用于初始化配置
//像素数据接口
input [15:0] rgb_din,
input rgb_din_vld,
output hdmi_req,
output hdmi_tx_clk, //像素时钟
... | 6.984389 |
module adv7513_reg_read #(
parameter CHIP_ADDR = 7'h39,
parameter I2C_CLKDIV = 206,
parameter I2C_TXN_DELAY = 0
) (
clk,
reset,
sda,
scl,
start,
done,
reg_addr_in,
reg_data
);
input clk, reset;
inout sda, scl;
input start;
output reg done;
input [7:0] reg_addr_in;... | 7.312749 |
module adv7611_frontend (
input PCLK_i,
input reset_n,
input [7:0] R_i,
input [7:0] G_i,
input [7:0] B_i,
input HSYNC_i,
input VSYNC_i,
input DE_i,
input [31:0] hv_in_config,
input [31:0] hv_in_config2,
input [31:0] hv_in_config3,
input sync_passthru,
output reg [7:0]... | 8.635282 |
module takes in the coordinates of a motor and the object. It calculates the distance between them. The distance will be used as length of rope.
//All coordinates are assumed to be positive
//clk, en and comp_sig are as in multiplication
//coor_mot_i is the ith component of the motor location.
//Restrict coor_obj_i to... | 9.560589 |
module PWM_timer (
input clk,
input [4:0] speed,
input en,
output out,
output dirp,
dirn
);
reg [4:0] speed_copy;
initial speed_copy <= 0;
reg outlogic;
initial
outlogic<=0;//This is the output of the logic circuit. It has to be multiplexed with 0 depending on en
assign out = (en... | 6.692341 |
module is used for testing the connection of four motors
//des_roti are taken to be 3 bit for input convenience. The actual rotation values are des_roti*8.
//dir[i] gives the direction of rotation of motor_i
//pulses[i] is the input from encoder values of motor_i
//PWM=0 stops all the motors
//sig_to_mot, dirp, dirn pr... | 7.142307 |
module PAGE6 ();
//: interface /sz:(40, 40) /bd:[ ] /pd: 0 /pi: 0 /pe: 0 /pp: 1
wire w23; //: /sn:0 {0}(309,247)(319,247){1}
wire w24; //: /sn:0 {0}(319,194)(254,194){1}
//: {2}(252,192)(252,134)(318,134){3}
//: {4}(250,194)(187,194){5}
wire w25; //: /sn:0 {0}(334,134)(344,134){1}
wire w22; //: /sn:0... | 6.504761 |
module PAGE3 ();
//: interface /sz:(40, 40) /bd:[ ] /pd: 0 /pi: 0 /pe: 0 /pp: 1
wire w4; //: /sn:0 {0}(131,166)(141,166){1}
wire w0; //: /sn:0 {0}(131,161)(141,161){1}
wire w1; //: /sn:0 {0}(171,176)(171,201)(285,201)(285,164)(237,164)(237,144)(193,144)(193,164)(162,164){1}
//: enddecls
//: comment g... | 6.512788 |
module PAGE10 ();
//: interface /sz:(40, 40) /bd:[ ] /pd: 0 /pi: 0 /pe: 0 /pp: 1
reg crete; //: {0}(7:215,136)(359,136)(359,189){1}
//: {2}(361,191)(416,191){3}
//: {4}(359,193)(359,203){5}
reg ithaca; //: {0}(18:215,183)(259,183){1}
//: {2}(263,183)(271,183){3}
//: {4}(261,185)(261,238)(278,238){5}
... | 6.533435 |
module AdvCounter (
clk,
reset,
add,
sub,
anode,
cathodes,
count,
dp
);
input clk;
input reset;
input add;
input sub;
output reg [6:0] cathodes;
output reg [3:0] anode;
output [15:0] count;
output dp;
reg [15:0] count;
reg reset_debounced;
reg add_reg1;
reg add... | 7.035026 |
module adv_debug_sys ( // JTAG signals
input tck_i,
input tdi_i,
output tdo_o,
input rst_i,
// TAP states
input shift_dr_i,
input pause_dr_i,
input update_dr_i,
input capture_dr_i,
// Module select from TAP
input debug_select_i,
input wb_clk_i,
input wb_rst_i,
... | 7.178335 |
module adv_instr(
instr,
regs,
regt,
result
);
input [32-1:0] instr;
input signed [32-1:0] regs;
input signed [32-1:0] regt;
output reg signed [32-1:0] result;
//disposable registers
reg signed [5-1:0] shamt;
reg [16-1:0] imm;
reg [32-1:0] ext_imm;
always@(*)
begin
shamt = instr[10:6];
imm = instr[... | 7.665517 |
module adv_instr_sel (
op_field_i,
function_field_i,
select
);
input [6-1:0] op_field_i;
input [6-1:0] function_field_i;
output reg select;
always @(*) begin
if ((op_field_i == 6'b000000) && (function_field_i == 6'b000011)) select = 1;
else if ((op_field_i == 6'b000000) && (function_field_i... | 6.975297 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module ad_buf (
// inputs:
a2dc,
adclk,
addr,
cs_n,
rd,
rdclk,
rst_n,
wrclk,
// outputs:
a2do,
waitreq
);
output [31:0] a2do;
output waitreq;
input [11:0] a2dc;
input adclk;
input [11:0] addr;
input cs_n;
input rd;
input rdclk;
input rst_n;
input wrc... | 6.518388 |
module ad_buff #(
parameter DSIZE = 8,
parameter DATA_DELAY_CLKS = 4'd8
) (
input i_ad_clk,
i_st,
i_rst_n,
input [DSIZE-1:0] i_ad_data,
input [15:0] i_recv_count,
output [ODSIZE-1:0] o_dual_data,
output o_data_on,
output o_working
);
localparam ODSIZE = DSIZE * 2;
reg [15:0... | 7.53117 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module ad_cache (
en,
sync,
spclk,
wclk,
wr,
wdata,
rclk,
rd,
rdata,
switch
);
////////////////// PORT ////////////////////
input en;
input sync;
input spclk;
input wclk;
input wr;
input [`AD_DATA_NBIT-1:0] wdata;
input rclk;
input rd;
output [`AD_DATA_NBIT-1... | 7.976409 |
module ad_cmos_out (
// data interface
tx_clk,
tx_data_p,
tx_data_n,
tx_data_out,
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
// delay-cntrl interface
delay_clk,
delay_rst,
delay_locked
);
// parameters
parameter DEVICE_TYPE = 0;
pa... | 6.842994 |
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