code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ADDSUB_16 (
X,
Y,
Sub,
S,
Cout
);
input [15:0] X, Y;
input Sub;
output [15:0] S;
output Cout;
CLA_16 adder0 (
X,
Y ^ {16{Sub}},
Sub,
S,
Cout
);
endmodule
| 7.168592 |
module ADDSUB_32 (
X,
Y,
Sub,
S,
Cout
);
input [31:0] X;
input [31:0] Y;
input Sub;
output [31:0] S;
output Cout;
CLA_32 adder0 (
X,
Y ^ {32{Sub}},
Sub,
S,
Cout
);
endmodule
| 7.639771 |
module CLA_4 (
X,
Y,
Cin,
S,
Cout
);
input [3:0] X;
input [3:0] Y;
input Cin;
output [3:0] S;
output Cout;
and get_0_0_0 (tmp_0_0_0, X[0], Y[0]);
or get_0_0_1 (tmp_0_0_1, X[0], Y[0]);
and get_0_1_0 (tmp_0_1_0, X[1], Y[1]);
or get_0_1_1 (tmp_0_1_1, X[1], Y[1]);
and get_0_2_0 (t... | 6.769755 |
module addsub_tb;
parameter tck = 10;
reg op, oc; // 0: add, 1: sub
wire [`WIDTH-1:0] y;
reg [`WIDTH-1:0] a, b;
reg c_in;
wire c_out, h_out;
reg clk;
addsub dut (
op,
oc,
y,
a,
b,
c_in,
c_out,
h_out
);
initial begin
$dumpvars(-1, dut);
$d... | 6.553753 |
module addsum (
input [31:0] pc,
imm,
output [31:0] pc_branch
);
assign pc_branch = pc + imm;
endmodule
| 6.871015 |
module addTest (
input clk,
input req_in,
output fin,
input [31:0] a_in,
input [31:0] b_in,
output wire [31:0] s1,
output wire cout1,
output wire [31:0] s2,
output wire cout2
);
reg req = 1'b0;
reg [31:0] a = 0, b = 0;
always @(posedge clk) begin
if (req_in) begin
req... | 6.798843 |
module addX (
a,
b,
cin,
out,
cout
);
parameter WIRE = 8;
input [WIRE-1:0] a, b;
input cin;
output [WIRE-1:0] out;
output cout;
wire ret;
if (WIRE > 1) begin
add add0 (
a[0],
b[0],
cin,
out[0],
ret
);
addX #(
.WIRE(WIRE - ... | 6.58028 |
module addy (
add_sub,
dataa,
datab,
result
);
input add_sub;
input [6:0] dataa;
input [6:0] datab;
output [6:0] result;
wire [6:0] sub_wire0;
wire [6:0] result = sub_wire0[6:0];
lpm_add_sub lpm_add_sub_component (
.dataa(dataa),
.add_sub(add_sub),
.datab(datab),
... | 7.019129 |
module addzero (
input [15:0] ramout,
input useAllBits,
output [15:0] z
);
//assign zero = 0;
//assign z[15:0] = useAllBits ? ramout : {zero,zero,zero,zero,ramout[11:0]};
assign z[15] = useAllBits & ramout[15];
assign z[14] = useAllBits & ramout[14];
assign z[13] = useAllBits & ramout[13];
... | 8.587073 |
module ADD_ #(
parameter N = 8,
M = N
) ( // N >= M
input [N-1:0] A,
input [M-1:0] B,
output [ N:0] O
);
assign O = A + B;
endmodule
| 8.457458 |
module adder_1 (
A,
B,
Carry_in,
clk,
Sum,
Carry_out
);
input A;
input B;
input Carry_in;
input clk;
output Sum;
output Carry_out;
wire [8:0] ds;
wire [1:0] w_A_0;
wire [1:0] w_B_0;
jdff dff_0_0 (
.din (Carry_in),
.dout(ds[0]),
.clk (clk)
);
jxor xor_0_0... | 6.607745 |
module add_12 (
clk_i,
rst_n_i,
data_1_i,
data_2_i,
data_sum_o
);
//----------------------------------------------------------------------------------------------------------------------
// Global constant and function headers
//--------------------------------------------------------------... | 6.716336 |
module add_128 (
a1,
a2,
s
);
input [7:0] a1, a2;
output wire [8:0] s;
assign s = a1 + a2;
endmodule
| 7.113309 |
module add_16 (
a1,
a2,
s
);
input [4:0] a1, a2;
output wire [5:0] s;
assign s = a1 + a2;
endmodule
| 6.977906 |
module add_16_bit (
Sum,
A,
B
);
input [15:0] A, B;
output [15:0] Sum;
wire [15:0] CO;
full_adder_1bit FA0 (
.A (A[0]),
.B (B[0]),
.CI(1'b0),
.S (Sum[0]),
.CO(CO[0])
);
full_adder_1bit FA1 (
.A (A[1]),
.B (B[1]),
.CI(CO[0]),
.S (Sum[1]),
... | 6.770312 |
module add_16_pipe (
c_out,
sum,
a,
b,
c_in,
clock
);
parameter size = 16;
parameter half = size / 2;
parameter double = 2 * size;
parameter triple = 3 * half;
parameter size1 = half - 1; // 7
parameter size2 = size - 1; // 15
parameter size3 = half + 1; // 9
parameter R1 = 1... | 6.825404 |
module add_1p #(
parameter WIDTH = 15, // Total bit width
WIDTH1 = 7, // Bit width of LSBs
WIDTH2 = 8
) // Bit width of MSBs
(
input [WIDTH-1:0] x,
y, // Inputs
output [WIDTH-1:0] sum, // Result
input clk, // Clock
output LSBs_Carry
); // Tes... | 6.651794 |
module ADD_1_bit (
c_out,
sum,
a,
b,
c_in
);
output c_out, sum;
input a, b, c_in;
wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10;
not not1 (w1, a);
not not2 (w2, b);
not not3 (w3, c_in);
and and1 (w4, a, w2, w3); //
and and2 (w5, w1, b, w3); // for sum
and and3 (w6, w1, w2, c_in... | 6.849935 |
module ADD_1_test;
reg a, b, cin;
wire sum, carry;
ADD_1 a1 (
sum,
carry,
a,
b,
cin
);
integer i;
initial begin
$dumpfile("ADD_1_test.vcd");
$dumpvars(0, ADD_1_test);
for (i = 0; i < 8; i = i + 1) begin
{a, b, cin} = i;
#5;
$display("%d + %d... | 6.708502 |
module add_2p #(
parameter WIDTH = 22, // Total bit width
WIDTH1 = 7, // Bit width of LSBs
WIDTH2 = 7, // Bit width of middle
WIDTH12 = 14, // Sum WIDTH1+WIDTH2
WIDTH3 = 8
) // Bit width of MSBs
(
input [WIDTH-1:0] x,
y, // Inputs
output [WIDTH-1:0] sum, // Result... | 6.519861 |
module add_3 (
input [31:0] yiwei,
input [31:0] pc,
output [31:0] yp
);
assign yp = yiwei + pc;
endmodule
| 7.418891 |
module add_32 (
a1,
a2,
s
);
input [5:0] a1, a2;
output wire [6:0] s;
assign s = a1 + a2;
endmodule
| 6.904223 |
module add_32b (
dataa,
datab,
overflow,
result
);
input [31:0] dataa;
input [31:0] datab;
output overflow;
output [31:0] result;
wire [32:0] computation; //one extra bit to account for overflow
assign computation = dataa + datab;
assign overflow = computation[32];
assign result = co... | 7.951311 |
module add_32b_testbench ();
reg [31:0] A;
reg [31:0] B;
reg C_in;
wire [31:0] O;
wire C_out;
add_32b add32tb (
O,
C_out,
A,
B,
C_in
);
initial begin
C_in = 1'b0;
A = 32'b00000000000000000000000000000011;
B = 32'b00000000000000000000000000000000;
#`DEL... | 6.92566 |
module add_32x16b (
input i_clk,
input i_rst_n,
input i_calc_en,
input [511:0] i_npe_dat_out,
//input i_ram_dat_vld,
input [511:0] i_ram_dat,
output [511:0] o_bias_dat_o
);
wire signed [15:0] npe_dat [31:0];
wire signed [15:0] ram_dat [31:0];
wire signed [... | 7.345913 |
module add_32_bit (
input [31:0] Ra,
input [31:0] Rb,
input wire cin,
output wire [31:0] sum,
output wire cout
);
wire cout1;
CLA16 CLA1 (
.Ra (Ra[15:0]),
.Rb (Rb[15:0]),
.cin (cin),
.sum (sum[15:0]),
.cout(cout1)
);
CLA16 CLA2 (
.Ra (Ra[31:16]),
... | 7.271914 |
module CLA16 (
input wire [15:0] Ra,
input wire [15:0] Rb,
input wire cin,
output wire [15:0] sum,
output wire cout
);
wire cout1, cout2, cout3;
CLA4 CLA1 (
.Ra (Ra[3:0]),
.Rb (Rb[3:0]),
.cin (cin),
.sum (sum[3:0]),
.cout(cout1)
);
CLA4 CLA2 (
.Ra (Ra[... | 8.139623 |
module CLA4 (
input wire [3:0] Ra,
input wire [3:0] Rb,
input wire cin,
output wire [3:0] sum,
output wire cout
);
// Creating wires for Propoate and Generate
wire [3:0] P, G, c;
assign P = Ra ^ Rb;
assign G = Ra & Rb;
assign c[0] = cin;
assign c[1] = G[0] | (P[0] & c[0]);
assign c[2]... | 7.783567 |
module CLA_4 (
input wire c_in,
input wire [3:0] a,
input wire [3:0] b,
output wire [3:0] s,
output wire c_out,
output wire c3
);
//gate syntax: gate name(arg1,arg2,out)
//Pi = Ai XOR Bi
//Gi = Ai * Bi
//Si = Pi XOR Ci
//Ci+1 = Gi + Pi*Ci
//ADDER 0
wire p0, g0, c1;
//P0 = A0 ... | 6.766102 |
module add_3p #(
parameter WIDTH = 29, // Total bit width
WIDTH0 = 7, // Bit width of LSBs
WIDTH1 = 7, // Bit width of 2. LSBs
WIDTH01 = 14, // Sum WIDTH0+WIDTH1
WIDTH2 = 7, // Bit width of 2. MSBs
WIDTH012 = 21, // Sum WIDTH0+WIDTH1+WIDTH2
WIDTH3 = 8
) // Bit width of MS... | 6.961492 |
module add_4 (
a1,
a2,
s
);
input [2:0] a1, a2;
output wire [3:0] s;
assign s = a1 + a2;
endmodule
| 6.864207 |
module add_42 (
input [7:0] io_dip,
input [15:0] a,
input [15:0] b,
output reg [15:0] out,
output reg z,
output reg v,
output reg n
);
reg [15:0] holder;
always @* begin
if (io_dip[0+0-:1] == 1'h0) begin
holder = a + b;
end else begin
holder = a - b;
end
o... | 7.613639 |
module add_4_new (
input [3:0] a,
input [3:0] b,
input cin,
output [3:0] s,
output cout
);
wire [4:0] sum;
assign sum = a + b + cin;
assign cout = sum[4];
assign s = sum[3:0];
endmodule
| 6.618152 |
module add_5 (
clk,
rst_n,
din_vld,
// dout_vld,
//ź,dout
dout
);
//
parameter DATA_W = 8;
//źŶ
input clk;
input rst_n;
input din_vld;
//źŶ
// output dout_vld;
output [DATA_W-1:0] dout;
//źreg
reg [DATA_W-1:0] dout;
// reg dout_vld;
... | 6.519817 |
module add_512 (
input wire clk,
input wire rst,
input wire [511 : 0] add_in0,
input wire [511 : 0] add_in1,
output reg [511 : 0] add_out
);
always @(posedge clk)
if (rst) begin
add_out <= 512'b0;
end else begin
add_out <= add_in0 + add_in1;
end
endmodule
| 7.574962 |
module add_516 (
input wire clk,
input wire rst,
input wire [515 : 0] add_in0,
input wire [515 : 0] add_in1,
output reg [515 : 0] add_out
);
always @(posedge clk)
if (rst) begin
add_out <= 516'b0;
end else begin
add_out <= add_in0 + add_in1;
end
endmodule
| 7.919171 |
module add_64 (
a1,
a2,
s
);
input [6:0] a1, a2;
output wire [7:0] s;
assign s = a1 + a2;
endmodule
| 7.070133 |
module ADD_64_test;
parameter n = 64;
reg signed [n-1:0] a, b;
wire signed [n-1:0] sum, carry;
ADD_64 a1 (
sum,
carry,
a,
b
);
initial begin
$dumpfile("ADD_64_test.vcd");
$dumpvars(0, ADD_64_test);
a = 999999999;
b = 12345;
#100;
$display("%d + %d = %d %d... | 6.879811 |
module add_8 (
a1,
a2,
s
);
input [3:0] a1, a2;
output wire [4:0] s;
assign s = a1 + a2;
endmodule
| 6.655259 |
module add_8bit (
a,
b,
c_in,
s,
c_out
);
input [7:0] a;
input [7:0] b;
input c_in;
output [7:0] s;
output c_out;
wire [6:0] c;
full_adder fa0 (
.a(a[0]),
.b(b[0]),
.c_in(c_in),
.s(s[0]),
.c_out(c[0])
);
full_adder fa1 (
.a(a[1]),
.b(b[1... | 6.573601 |
module add_8bit_tb;
reg [7:0] a;
reg [7:0] b;
reg c_in;
wire [7:0] s;
wire c_out;
add_8bit uut (
.a(a),
.b(b),
.c_in(c_in),
.s(s),
.c_out(c_out)
);
initial begin
$dumpfile("add_8bit_tb.vcd");
$dumpvars(0, add_8bit_tb);
a = 8'b00000001;
b = 8'b00000001;
... | 6.707433 |
module ADD_8_tb;
// Parameters
localparam ELEMENT_BIT_DEPTH = 14;
// Ports
reg [ELEMENT_BIT_DEPTH*8-1:0] addend_array;
wire [ ELEMENT_BIT_DEPTH-1:0] add;
ADD_8 #(
.ELEMENT_BIT_DEPTH(ELEMENT_BIT_DEPTH)
) ADD_8_dut (
.addend_array(addend_array),
.add (add)
);
initial begi... | 7.60826 |
module AddSL (
input [31:0] Add,
input [31:0] Shiftleft,
output [31:0] Result
);
assign Result = Add + Shiftleft;
endmodule
| 6.585724 |
module add_and_square_v6 (
clk,
A,
B,
C,
OUT
);
parameter DEMUX = 16;
parameter NBITS = 3;
localparam NCBITS = DEMUX * NBITS;
// We have 6 output bits: the bottom bit is always 0.
parameter OUTBITS = 6;
input [NCBITS-1:0] A;
input [NCBITS-1:0] B;
input [NCBITS-1:0] C;
output [OUT... | 6.70474 |
module add_array #(
parameter WL = 16
) (
input clk,
input [WL-1:0] add_array_in0,
input [WL-1:0] add_array_in1,
input [WL-1:0] add_array_in2,
input [WL-1:0] add_array_in3,
input [WL-1:0] add_array_in4,
input [WL-1:0] add_array_in5,
input [WL-1:0] add_array_in6,
input [WL-1:0] ad... | 6.56336 |
module Add_B (
entrada_AddPC,
entrada_Imediato,
saida_addB
);
input [31:0] entrada_AddPC, entrada_Imediato;
output wire [31:0] saida_addB;
assign saida_addB = entrada_AddPC + entrada_Imediato;
endmodule
| 7.998531 |
modules/adder/add32.v"
`endif
module add_bpc(EX_npc, EX_imm, EX_bpc);
input wire [31:0] EX_npc, EX_imm;
output wire [31:0] EX_bpc;
wire cout;
wire cin = 0;
add32 add32(
.a(EX_npc),
.b(EX_imm),
.cin(cin),
.s(EX_bpc),
.cout(cout)
);
endmodule
| 7.633156 |
module ADD_Branch (
i_op1,
i_op2,
o_out
);
input [`WIDTH_BRANCH-1:0] i_op1;
input [`WIDTH_BRANCH-1:0] i_op2;
output [`WIDTH_BRANCH-1:0] o_out;
assign o_out = i_op1 + i_op2;
endmodule
| 7.19109 |
module add_char
(
input wire clk ,
input wire rst_n ,
input wire [20:0] A,
input wire [17:0] B,
output wire [21:0] C
);
//寄存
reg [20:0] reg_A;
reg [17:0] reg_B;
always@(posedge clk or negedge rst_n)
if()
endmodule
| 7.167624 |
module add_circuit (
input wire x,
input wire y,
input wire cin,
output wire z,
output wire cout
);
wire [1:0] temp;
assign temp = {1'b0, x} + {1'b0, y} + {1'b0, cin};
assign z = temp[0];
assign cout = temp[1];
endmodule
| 6.50232 |
module add_circuit2 (
input wire [7:0] x,
input wire [7:0] y,
output wire [7:0] z,
output wire cout
);
localparam N = 8, N1 = N - 1;
wire [N:0] temp;
assign temp = {1'b0, x} + {1'b0, y};
assign z = temp[N1:0];
assign cout = temp[N];
endmodule
| 6.596746 |
module add_circuit3 #(
parameter N = 3
) (
input wire [ N:0] x,
input wire [ N:0] y,
output wire [N+1:0] z
// output wire cout
);
localparam N1 = N - 1;
wire [N:0] temp;
assign temp = {1'b0, x} + {1'b0, y};
assign z = temp;
//assign z = temp[N1:0];
//assign cout = temp[N];
end... | 7.796889 |
module ADD_CLA_24 (
iA,
iB,
iC,
oS,
oG,
oP,
oC
);
input [23:0] iA, iB;
input iC;
output [23:0] oS;
output oG, oP, oC;
wire [2:0] G, P, C;
ADD_CLA_8 adder0 (
.iA(iA[7:0]),
.iB(iB[7:0]),
.iC(C[0]),
.oS(oS[7:0]),
.oG(G[0]),
.oP(P[0]),
.o... | 6.994189 |
module ADD_CLA_4 (
iA,
iB,
iC,
oS,
oG,
oP,
oC
);
input [3:0] iA, iB;
input iC;
output [3:0] oS;
output oG, oP, oC;
wire [3:0] G, P, C;
assign G = iA & iB;
assign P = iA | iB;
CLA_4 ADD_CLA_4_ (
.iG(G),
.iP(P),
.iC(iC),
.oG(oG),
.oP(oP),
... | 7.109737 |
module ADD_CLA_8 (
iA,
iB,
iC,
oS,
oG,
oP,
oC
);
input [7:0] iA, iB;
input iC;
output [7:0] oS;
output oG, oP, oC;
wire [1:0] G, P, C;
ADD_CLA_4 adder0 (
.iA(iA[3:0]),
.iB(iB[3:0]),
.iC(C[0]),
.oS(oS[3:0]),
.oG(G[0]),
.oP(P[0]),
.oC()... | 7.544648 |
module ADD_CLA_8_tb ();
reg [7:0] iA, iB;
reg iC;
wire [7:0] oS;
wire oG, oP, oC;
ADD_CLA_8 ADD_CLA_8_ (
.iA(iA),
.iB(iB),
.iC(iC),
.oS(oS),
.oG(oG),
.oP(oP),
.oC(oC)
);
initial begin
#0;
iA = 8'd125;
iB = 8'd11;
iC = 1'b0;
#10;
... | 6.731247 |
module ADD_CLA_FINAL (
a,
b,
symbol,
out
);
parameter DATA_WIDTH = 32;
input [DATA_WIDTH - 1:0] a, b;
input symbol;
output [DATA_WIDTH - 1:0] out;
wire [24:0] fraction_25;
wire [7:0] diff_exp, exp_max, exp_max_tmp;
wire sign_diff_exp, cout_exp_tmp;
wire [31:0] out_normal, out_specia... | 7.751084 |
module add_const (
out,
in
);
parameter const_val = 1;
output [31:0] out;
input [31:0] in;
assign out = in + const_val;
endmodule
| 7.470997 |
module add_const_design (
clk,
a,
b,
z
);
input clk;
input [3:0] a;
input [3:0] b;
output reg [3:0] z;
always @(posedge clk) z <= a + b + (1'b1 - 1'b1);
endmodule
| 6.944334 |
module add_ex (
input clk,
input [31:0] pc_in,
input [31:0] shift_in,
output [31:0] add
);
reg [31:0] addition;
always @(posedge clk) begin
addition <= pc_in + shift_in;
end
assign add = addition;
endmodule
| 7.224738 |
module add_exec1 (
rs_index,
rs1_data,
rs2_data,
func,
rob_ind,
clk1,
clk2,
rd,
ex_b
);
input [7:0] rs1_data;
input [7:0] rs2_data;
input [3:0] func, rd;
input [2:0] rob_ind, rs_index;
input clk1, clk2, ex_b;
integer count_as;
integer temp, temp1;
reg [15:0] out1;
... | 9.024716 |
module add_exec2 (
rs_index,
rs1_data,
rs2_data,
func,
rob_ind,
clk1,
clk2,
rd,
ex_b
);
input [7:0] rs1_data;
input [7:0] rs2_data;
input [3:0] func, rd;
input [2:0] rob_ind, rs_index;
input clk1, clk2, ex_b;
integer count_as;
integer temp, temp1;
reg [15:0] out1;
a... | 9.320063 |
module full (
input a,
input b,
input c,
output s,
output v
);
assign s = a ^ b ^ c;
assign v = a & (b | c) | b & c;
endmodule
| 7.892995 |
module add5 (
input [4:0] a,
b,
output [5:0] c
);
wire [3:0] v;
full a0 (
a[0],
b[0],
1'b0,
c[0],
v[0]
);
full a1 (
a[1],
b[1],
v[0],
c[1],
v[1]
);
full a2 (
a[2],
b[2],
v[1],
c[2],
v[2]
);
full a3 (
... | 6.662767 |
module add_fan_out (
input [1:0] in0,
input [1:0] in1,
output [1:0] out0,
output [1:0] out1,
input clk
);
reg [1:0] res0;
reg [1:0] res1;
always @(posedge clk) begin
res0 <= in0 + in1;
res1 <= in0 - in1;
end
assign out0 = res0;
assign out1 = res1;
endmodule
| 6.897195 |
module add_ff_design (
clk,
reset_,
a,
b,
z
);
input clk;
input reset_;
input [3:0] a;
input [3:0] b;
output reg [3:0] z;
always @(posedge clk, negedge reset_)
if (!reset_) begin
z <= 0;
end else begin
z <= a + b;
end
endmodule
| 7.173034 |
module add_fp_clk (
clk,
rst_n
, ena_add_fp_clk
, data_in_1
, data_in_2
, data_out
);
parameter DATA_WIDTH = 32;
input clk;
input rst_n;
input ena_add_fp_clk;
input [DATA_WIDTH-1:0] data_in_1;
input [DATA_WIDTH-1:0] data_in_2;
output [DATA_WIDTH-1:0] data_out;
reg [DATA_WIDT... | 7.585168 |
module add_full (
input a,
input b,
input cin,
output cout,
output s
);
assign cout = a & b | a & cin | b & cin;
assign s = ~a & ~b & cin | ~a & b & ~cin | a & ~b & ~cin | a & b & cin;
endmodule
| 7.057721 |
module add_func (
X,
Y,
sum,
overflow
);
//parameter definitions
//port definitions - customize for different bit widths
input wire [31:0] X;
input wire [31:0] Y;
output wire [31:0] sum;
output wire overflow;
wire ci = 0;
add_rca_32_bit adder (
.X (X),
.Y (Y),
.ci... | 8.216946 |
module add_g (
input clk,
input rst,
input [10:0] data_0,
input [10:0] data_1,
output reg signed [11:0] result
);
always @(posedge clk) begin
if (rst) result <= 0;
else result <= data_1 - data_0;
end
endmodule
| 7.113429 |
module add_half (
input a,
b,
output reg c_out,
output sum
);
my_xor XOR1 (
a,
b,
sum
);
always @(*) begin
// sum = a ^ b;
c_out <= a & b;
end
endmodule
| 7.260022 |
module add_judge_r (
input [9215:0] vout,
input [14*27-1:0] index_judge_in,
output reg flag
);
integer j;
always @(*) begin
flag = 0;
for (j = 0; j < 27; j = j + 1) flag = flag + vout[index_judge_in[j*14+:14]];
end
endmodule
| 6.779657 |
module add_key (
addKeyOut,
roundText,
roundKey
);
output [63:0] addKeyOut;
input [63:0] roundText;
input [79:0] roundKey;
assign addKeyOut = roundText ^ roundKey[63:0];
endmodule
| 7.292369 |
module add_mega (
add_sub,
dataa,
datab,
overflow,
result
);
input add_sub;
input [31:0] dataa;
input [31:0] datab;
output overflow;
output [31:0] result;
wire sub_wire0;
wire [31:0] sub_wire1;
wire overflow = sub_wire0;
wire [31:0] result = sub_wire1[31:0];
lpm_add_sub LPM_AD... | 7.100227 |
module add_mega (
add_sub,
dataa,
datab,
overflow,
result
);
input add_sub;
input [31:0] dataa;
input [31:0] datab;
output overflow;
output [31:0] result;
endmodule
| 7.100227 |
module add_mlt(input clk,
input[15:0]dataa,datab,
input ld_a,ld_b,ld_p,cr_p,dc_b,
output [15:0]ax,py,bd,
output zero,[15:0]out
);
Reg1 A(.load(ld_a),.data(dataa),.clk(clk),.X(ax));
Reg2 P(.load_P(ld_p),.clear_p(cr_p),.data_P(out),.clk(clk),.Y(py));
Reg3 B(.loadb(ld_b),.clk(clk),.dcb(dc_b),.datb(data... | 6.637452 |
module add_mod (
input wire clk,
input wire [23:0] a,
input wire [23:0] b,
output wire [23:0] out
);
reg [24:0] sum;
always @(posedge clk) sum <= a + b;
assign out = sum - (sum >= 24'd12587009 ? 24'd12587009 : 23'd0);
endmodule
| 7.093165 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module add_module(Clk, data_in, reset, enable, textOut, n... | 7.088073 |
module adder (
a,
b,
y
);
parameter WIDTH = 16;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_16_bit (
a,
b,
operation,
Result
);
parameter WIDTH = 16;
input [0:WIDTH-1] a, b;
input operation;
output reg [0:(WIDTH*2)-1] Result;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multi... | 7.018182 |
module adder (
a,
b,
y
);
input a, b;
output y;
reg y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_1_bit (
a,
b,
operation,
Result
);
input a, b;
input operation;
output Result;
reg Result;
wire Result_add;
wire Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
.b(b),
.y(Result_mul)
);
... | 6.690052 |
module adder (
a,
b,
y
);
parameter WIDTH = 2;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_2_bit (
a,
b,
operation,
Result
);
parameter WIDTH = 2;
input [0:WIDTH-1] a, b;
input operation;
output reg [0:(WIDTH*2)-1] Result;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multipl... | 6.768282 |
module adder (
a,
b,
y
);
parameter WIDTH = 32;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_32_bit (
a,
b,
operation,
Result
);
parameter WIDTH = 32;
input [0:WIDTH-1] a, b;
input operation;
output reg [0:(WIDTH*2)-1] Result;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multi... | 7.393024 |
module adder (
a,
b,
y
);
parameter WIDTH = 4;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_4_bit (
a,
b,
operation,
Result
);
parameter WIDTH = 4;
input [0:WIDTH-1] a, b;
input operation;
output reg [0:(WIDTH*2)-1] Result;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multipl... | 7.496552 |
module adder (
a,
b,
y
);
parameter WIDTH = 64;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_64_bit (
a,
b,
operation,
Result
);
parameter WIDTH = 64;
input [0:WIDTH-1] a, b;
input operation;
output reg [0:(WIDTH*2)-1] Result;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multi... | 7.073299 |
module adder (
a,
b,
y
);
parameter WIDTH = 8;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_8_bit (
a,
b,
operation,
Result
);
parameter WIDTH = 8;
input [0:WIDTH-1] a, b;
input operation;
output reg [0:(WIDTH*2)-1] Result;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multipl... | 6.776442 |
module adder (
a,
b,
y
);
parameter WIDTH = 16;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_combine_16_bit (
a,
b,
Result_mul,
Result_add
);
parameter WIDTH = 16;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] Result_add;
output reg [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
... | 6.911403 |
module adder (
a,
b,
y
);
parameter WIDTH = 2;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_combine_2_bit (
a,
b,
Result_mul,
Result_add
);
parameter WIDTH = 2;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] Result_add;
output reg [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
... | 6.911403 |
module adder (
a,
b,
y
);
parameter WIDTH = 32;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_combine_32_bit (
a,
b,
Result_mul,
Result_add
);
parameter WIDTH = 32;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] Result_add;
output reg [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
... | 6.911403 |
module adder (
a,
b,
y
);
parameter WIDTH = 4;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_combine_4_bit (
a,
b,
Result_mul,
Result_add
);
parameter WIDTH = 4;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] Result_add;
output reg [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
... | 6.911403 |
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