code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module half_adder (
x, //INPUT1
y, //INPUT2
s, //SUM
c //CARRY
);
input x, y;
output s, c;
assign s = x ^ y;
assign c = x & y;
endmodule
| 6.966406 |
module adder_test1_tb;
reg clock;
reg RSTB;
reg CSB;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
wire [7:0] mprj_io_0;
wire [15:0] checkbits;
// TODO assign check bits
assign checkbits = mprj_io[31:16];
assign mprj_io[3] = 1'b1;
// External clock is used by def... | 6.667905 |
module adder_tester (
output [7:0] adder_operand1,
output [7:0] adder_operand2,
input [8:0] structural_sum,
input [8:0] behavioral_sum,
input clk,
output test_fail
);
// This 'reg assignment' sets the value of the 'error' register to 0 when 'make impact' is run
// This kind of initial value... | 9.465263 |
module adder_test_tb;
reg clock;
reg RSTB;
reg reset;
reg CSB;
integer cycle_count;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
wire [3:0] checkbits;
reg a;
assign mprj_io[13:10] = a;
reg b;
assign mprj_io[17:14] = b;
assign checkbits = mprj_io[31:28];
alwa... | 7.006654 |
module for adder
module adder_top
(
input clk, // 100MHz clock signal
input btnC, // reset signal
input RsRx, // RS232 Rx signal
output RsTx // RS232 Tx signal
);
wire rst;
assign rst = btnC;
wire [15:0] adder_opr1, adder_opr2, adder_ans;
wire adder_carry;
hci ... | 7.149058 |
module adder_tree #(
parameter LAYER_NUM = 4,
parameter MIN_ADDER_WIDTH = 8
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input [(2 ** LAYER_NUM) * MIN_ADDER_WIDTH - 1:0] adder_din,
output [LAYER_NUM + MIN_ADDER_WIDTH - 1:0] adder_dout
);
genvar i;
generate
fo... | 6.824939 |
module adder (
s,
co,
a,
b,
ci
);
output s, co; //Outputs of Sum and Carry Out
input a, b, ci; //Inputs of A, b and Carry In
wire o0, o1, o2; //Internal wiring
xor (s, a, b, ci); //Calculation of Sum
or (o0, a, b); //Calculation of Carry Out
or (o1, b, ci);
or (o2, ci, a);
a... | 7.276647 |
module adder7 (
s,
co,
a,
b,
ci
);
output [6:0] s; //7-bit Sum output
output co; //Output bit of Carry out
input [6:0] a, b; //7-bit Input A and B
input ci; //Input bit of Carry in
wire c1, c2, c3, c4, c5, c6;
adder a0 (
s[0],
c1,
a[0],
b[0],
ci
);... | 7.475421 |
module adder4_2 (
s,
co,
a,
b,
c,
d
); //used as second level in tree structure
output [6:0] s,co; //7-bit Sum output and 7-bit carry in where co[0] = 0 (Carry In will be added in later)
input [6:0] a, b, c, d; //7-bit Input A, B, C, D
wire [6:0] ts;
wire [6:0] tc;
wire c1, c2; //... | 6.856983 |
module adder5_2 (
s,
co,
a,
b,
c,
d,
e
);
output [6:0] s,co; //7-bit Sum output and 7-bit carry in where co[0] = 0 (Carry In will be added in later)
input [6:0] a, b, c, d, e; //7-bit Input A, B, C, D, E
wire [6:0] ts0, ts1;
wire [6:0] tc0, tc1;
wire c1, c2, c3, c4; //crap 1 an... | 7.126116 |
module adder_tree5 (
s,
co,
a,
b,
c,
d,
e,
f,
g,
h,
i,
j,
ci
);
output [6:0] s;
output co;
input [6:0] a, b, c, d, e, f, g, h, i, j;
input ci;
wire [6:0] ts1, ts2, ts3;
wire [6:0] tc1, tc2, tc3;
//3:2 adders in linear fashion
adder5_2 a1 (
ts1... | 7.113805 |
module adder_tree (
input wire [7:0] a,
b,
c,
d,
e,
f,
g,
h,
input wire clk,
rst,
output wire [10:0] y
);
reg [8:0] i11, i12, i13, i14;
reg [9:0] i21, i22;
reg [10:0] i31;
always @(posedge clk, posedge rst) begin
if (rst) begin
i11 <= 0;
i12 <= 0;
... | 6.756517 |
module adder_tree_2stage_16bit (
clk,
reset,
inp00,
inp01,
inp10,
inp11,
sum_out
);
input clk;
input reset;
input [15:0] inp00;
input [15:0] inp01;
input [15:0] inp10;
input [15:0] inp11;
output reg [31:0] sum_out;
reg [16:0] S_0_0;
reg [16:0] S_0_1;
always @(posedge c... | 6.548304 |
module adder_tree_2stage_4bit (
clk,
reset,
inp00,
inp01,
inp10,
inp11,
sum_out
);
input clk;
input reset;
input [3:0] inp00;
input [3:0] inp01;
input [3:0] inp10;
input [3:0] inp11;
output reg [7:0] sum_out;
reg [4:0] S_0_0;
reg [4:0] S_0_1;
always @(posedge clk) begi... | 6.548304 |
module adder_tree_2stage_8bit (
clk,
reset,
inp00,
inp01,
inp10,
inp11,
sum_out
);
input clk;
input reset;
input [7:0] inp00;
input [7:0] inp01;
input [7:0] inp10;
input [7:0] inp11;
output reg [15:0] sum_out;
reg [8:0] S_0_0;
reg [8:0] S_0_1;
always @(posedge clk) beg... | 6.548304 |
module adder_tree_3stage_16bit (
clk,
reset,
inp00,
inp01,
inp10,
inp11,
inp20,
inp21,
inp30,
inp31,
sum_out
);
input clk;
input reset;
input [15:0] inp00;
input [15:0] inp01;
input [15:0] inp10;
input [15:0] inp11;
input [15:0] inp20;
input [15:0] inp21;
i... | 6.622442 |
module adder_tree_3stage_4bit (
clk,
reset,
inp00,
inp01,
inp10,
inp11,
inp20,
inp21,
inp30,
inp31,
sum_out
);
input clk;
input reset;
input [3:0] inp00;
input [3:0] inp01;
input [3:0] inp10;
input [3:0] inp11;
input [3:0] inp20;
input [3:0] inp21;
input [3... | 6.622442 |
module adder_tree_3stage_8bit (
clk,
reset,
inp00,
inp01,
inp10,
inp11,
inp20,
inp21,
inp30,
inp31,
sum_out
);
input clk;
input reset;
input [7:0] inp00;
input [7:0] inp01;
input [7:0] inp10;
input [7:0] inp11;
input [7:0] inp20;
input [7:0] inp21;
input [7... | 6.622442 |
module FPAddSub (
clk,
rst,
a,
b,
operation, // 0 add, 1 sub
result,
flags
);
// Clock and reset
input clk; // Clock signal
input rst; // Reset (active high, resets pipeline registers)
// Input ports
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`... | 6.989325 |
module is responsible for taking the inputs
// apart and checking the parts for exceptions.
// The exponent difference is also calculated in this module.
//
module FPAddSub_PrealignModule(
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWI... | 7.391888 |
module determines the larger input operand and
// sets the mantissas, shift and common exponent accordingly.
//
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number
input [`D... | 6.986217 |
module FPAddSub_AlignShift1 (
//bf16,
MminP,
Shift,
Mmin
);
// Input ports
//input bf16;
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [`EXPONENT-3:0] Shift ; // Shift amount. Last 2 bits of shifting are done in next stage. Hence, we have [`EXPONENT - 2] bit... | 6.969233 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount. Last 2 bits
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANT... | 6.969233 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of sm... | 6.632792 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
//Changes in this doesn't matter since even Bfloat... | 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1... | 6.905513 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0... | 6.905513 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round... | 7.753919 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
inpu... | 7.326377 |
module adder_tree_node (
clk,
a,
b,
out
);
parameter IN_BITS = 16;
parameter OUT_BITS = 17;
parameter SIGN_EXT = 1;
parameter REGISTER_MIDDLE = 0; // register within adder chains
parameter REGISTER_OUTPUT = 1; // register adder outputs
parameter B_SHIFT = 1;
// for the placement of the... | 6.847166 |
module adder_tree_tb ();
parameter MIN_ADDER_WIDTH = 8;
parameter LAYER_NUM = 4;
reg clk;
reg rst_n;
reg [(2 ** (LAYER_NUM - 1)) * MIN_ADDER_WIDTH - 1:0] adder_din;
wire [LAYER_NUM + MIN_ADDER_WIDTH - 1:0] adder_dout;
adder_tree #(
.LAYER_NUM(4),
.MIN_ADDER_WIDTH(8)
) dut (
.clk (... | 6.588422 |
module adder_udp (
input x,
input y,
input cin,
output res,
output cout
);
addresult(
res, cin, x, y
); addcarry(
cout, cin, x, y
);
endmodule
| 7.301565 |
module adder_udp_tb;
reg x;
reg y;
reg cin;
wire res;
wire cout;
adder_udp uut (
.x(x),
.y(y),
.cin(cin),
.res(res),
.cout(cout)
);
initial begin
$dumpfile("adder_udp.vcd");
$dumpvars(0, adder_udp_tb);
x = 0;
y = 0;
cin = 0;
#20 x = 1;
... | 7.15946 |
module adder_unit #(
parameter WIDTH = 9
) ( //input declarations
input signed [WIDTH-1:0] A_in,
input signed [WIDTH-1:0] B_in,
//output declarations
output reg signed [WIDTH-1:0] C_out
);
always @(*) begin
if (A_in[WIDTH-1] ^ B_in[WIDTH-1] == 0) begin
C_out[WIDTH-2:0] <= B_in[WIDTH-... | 7.212241 |
module adder_using_always ();
reg a, b;
reg sum, carry;
always @(a or b) begin
{carry, sum} = a + b;
end
initial begin
$monitor(" A = %b B = %b CARRY = %b SUM = %b", a, b, carry, sum);
#10 a = 0;
b = 0;
#10 a = 1;
#10 b = 1;
#10 a = 0;
#10 b = 0;
#10 $finish;
end
endmo... | 6.707567 |
module adder_using_assign ();
reg a, b;
wire sum, carry;
assign #5{carry, sum} = a + b;
initial begin
$monitor(" A = %b B = %b CARRY = %b SUM = %b", a, b, carry, sum);
#10 a = 0;
b = 0;
#10 a = 1;
#10 b = 1;
#10 a = 0;
#10 b = 0;
#10 $finish;
end
endmodule
| 6.707567 |
module adder (
a,
b,
out
);
input [31:0] a, b;
output [31:0] out;
assign out = a + b;
endmodule
| 7.4694 |
module adder_with_bram (
input wire clk,
input wire resetn,
input wire start_add,
input wire clear_done,
output reg bram_en,
output reg [3:0] bram_we,
output reg [14:0] bram_addr,
input wire [31:0] bram_rdata,
output reg [31:0] bram_wdata
);
reg [31:0] adder_ina;
reg [31:0] adde... | 7.100125 |
module ram (
addr0,
d0,
we0,
q0,
clk
);
input [14:0] addr0;
input [31:0] d0;
input [3:0] we0;
output [31:0] q0;
input clk;
reg [31:0] q0;
reg [ 7:0] ram[(1<<15-1):0];
always @(posedge clk) begin
if (we0[0]) ram[addr0+0] <= d0[7:0];
if (we0[1]) ram[addr0+1] <= d0[15:8];
... | 6.838627 |
module top;
wire [31:0] bram_rdata;
wire [31:0] bram_wdata;
wire [14:0] bram_addr;
wire [3:0] bram_we;
reg start_add;
reg clear_done;
reg clk;
reg resetn;
initial begin
clk = 0;
forever begin
#10 clk = ~clk;
end
end
initial begin
resetn = 0;
#55 resetn = 1;
end
a... | 6.919222 |
module adder_8_bit_with_overflow (
input [7:0] a,
input [7:0] b,
output [7:0] sum,
output c_out,
output overflow
);
wire [7:0] temp_sum;
wire [7:0] overflow_extend;
adder_8_bit x1 (
.a(a),
.b(b),
.sum(temp_sum),
.c_out(c_out)
);
overflow_detection x2 (
.a_las... | 6.773302 |
module performs add, subtract and compare instructions. *
* *
*****************************************************************************/
// synthesis translate_off
`timescale 1ns / 100ps
// synthesis translate_on
/*
Adder_w_Compar... | 6.821257 |
module Adder_z (
input [31:0] a_adder,
input [31:0] b_adder,
input reset,
input clock,
output [31:0] FinalSum
);
wire idle_Special, idle_Allign, idle_AddState, idle_NormaliseSum;
wire [31:0] sout_Special, sout_Allign, sout_AddState, sout_NormaliseSum;
wire [35:0] cout_Special, cout_Allign;
... | 6.553626 |
module addf (
input [31:0] a,
input [31:0] b,
output reg [31:0] data_out
);
always @(*) begin
data_out = a + b;
end
endmodule
| 7.251162 |
module addfxp_18_1 (
input [17:0] a,
input [17:0] b,
input clk,
output [17:0] q
);
reg [17:0] res_0;
assign q = res_0;
always @(posedge clk) begin
res_0 <= a + b;
end
endmodule
| 6.553508 |
module addhsv (
A,
B,
CIN,
COUT,
OVF,
SUM
);
parameter N = 32;
parameter DPFLAG = 1;
parameter GROUP = "dpath1";
parameter BUFFER_SIZE = "DEFAULT";
parameter d_COUT_r = 1, d_COUT_f = 1, d_OVF_r = 1, d_OVF_f = 1, d_SUM = 1;
input [(N - 1):0] A;
input [(N - 1):0] B;
input CIN;
ou... | 7.255995 |
module adding_five_four_bits (
pb1,
pb2,
pb3,
pb4,
rc,
in,
sum,
carry
);
input pb1;
input pb2;
input pb3;
input pb4;
input rc;
input [3:0] in;
output [5:0] sum;
wire [5:0] sum;
output carry;
wire carry;
reg [3:0] a;
reg [3:0] b;
reg [3:0] c;
reg [3:0] d;
reg... | 7.154553 |
module: adding_five_four_bits
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module adding_five_four_bits_top;
// Inputs
reg pb1;
reg pb2;
reg pb3;
reg pb4;
reg rc;
reg [3:0] in;
... | 7.376805 |
module Addition_Subtraction (
input [31:0] a_operand,
b_operand, //Inputs in the format of IEEE-754 Representation.
input AddBar_Sub, //If Add_Sub is low then Addition else Subtraction.
output Exception,
output [31:0] result //Outputs in the format of IEEE-754 Representation.... | 7.743167 |
module addition (
a,
b,
c
);
// bit depth
localparam BIT_DEPTH = 16;
input wire [BIT_DEPTH-1:0] a, b;
output wire [BIT_DEPTH:0] c;
pos_add #(BIT_DEPTH, BIT_DEPTH) ADD (
a,
b,
c
);
endmodule
| 7.93101 |
module Addition_tb;
reg clk = 0;
reg [31:0] a_operand;
reg [31:0] b_operand;
wire [31:0] result;
reg AddBar_Sub;
reg [31:0] Expected_result;
reg [95:0] testVector [`N_TESTS-1:0];
reg test_stop_enable;
integer mcd;
integer test_n = 0;
integer pass = 0;
integer error = 0;
Addition_Subtraction DUT(... | 8.472785 |
module addition_fp (
Sum,
InA,
InB,
valid_in,
valid_out
);
input [31:0] InA, InB;
input valid_in;
output [31:0] Sum;
output reg valid_out;
reg [7:0] Exponent, Exponent_A, Exponent_B, Exponent_A_Out, Exponent_B_Out;
reg Sign_A, Sign_B, Sign, S, Temp;
reg [23:0] Fraction_A, Fraction_B, F... | 7.277446 |
module addition_s (
signa,
signb,
mantissa_11,
mantissa_21,
mantissa_sum
);
input signa, signb;
input [9:0] mantissa_11, mantissa_21;
output [10:0] mantissa_sum;
wire [9:0] Mantissa_11, Mantissa_21;
assign Mantissa_11 = (signa ? (-mantissa_11) : mantissa_11);
assign Mantissa_21 = (si... | 7.246511 |
module Addition_Subtraction (
input [31:0] a,
b,
input add_sub_signal, // If 1 then addition otherwise subtraction
output exception,
output [31:0] res
);
wire operation_add_sub_signal;
wire enable;
wire output_sign;
wire [31:0] op_a, op_b;
wire [23:0] significand_a, sign... | 7.743167 |
module Addition_Subtraction_tb;
reg [31:0] a, b;
reg clk = 1'b0, reset = 1'b1;
reg add_sub_signal;
wire [31:0] res;
wire exception;
Addition_Subtraction dut (
a,
b,
add_sub_signal,
exception,
res
);
always #5 clk = ~clk;
initial begin
add_sub_signal = 1'b0;
... | 7.743167 |
module Addition_tb;
reg clk = 0;
reg [31:0] a_operand;
reg [31:0] b_operand;
reg AddBar_Sub = 1'b1;
wire [31:0] result;
reg [31:0] Expected_result;
reg [95:0] testVector[`N_TESTS-1:0];
reg test_stop_enable;
integer mcd;
integer test_n = 0;
integer pass = 0;
integer error = 0;
Addition_S... | 8.472785 |
module addi_control_ID_EX_stage (
input signal_addi,
input clock,
output reg out_addi_control_reg
);
always @(posedge clock) out_addi_control_reg = signal_addi;
endmodule
| 6.882231 |
module AddLeftShift32 (
AddIn,
ALSHIn,
Out
);
input [31:0] AddIn, ALSHIn;
output reg [31:0] Out;
always @(AddIn, ALSHIn) begin
Out <= (ALSHIn << 2) + AddIn;
end
endmodule
| 7.730163 |
module addma (
input wire clk,
input wire [24:0] outdat,
output wire rden,
input wire empty,
output reg [22:0] memaddr,
input wire [31:0] memrdata,
output wire [31:0] memwdata,
output wire [1:0] memlen,
output reg memreq,
output wire memwr,
input wire memready,
input wi... | 6.865839 |
module addNbits #(
parameter N = 32
) (
input wire [N:0] x,
input wire [N:0] y,
input cin,
output wire [N:0] z,
output wire cout
);
wire [N+1:0] temp;
assign temp = {1'b0, x} + {1'b0, y} + cin;
assign z = temp[N:0];
assign cout = temp[N+1];
endmodule
| 7.928611 |
module addNbits_tb ();
localparam N = 32;
reg [N:0] x;
reg [N:0] y;
reg cin;
wire [N:0] z;
wire cout;
addNbits circuit1 (
.x(x),
.y(y),
.cin(cin),
.z(z),
.cout(cout)
);
initial begin
$dumpfile("test.vcd");
$dumpvars(0, addNbits_tb);
x = 'd2;
y = 'd... | 6.881315 |
module AddNot (
input [7:0] a,
input [7:0] b,
output [8:0] o
);
wire [7:0] _GEN_0 = ~b;
assign o = a + _GEN_0;
endmodule
| 7.3741 |
module AddNot (
input [7:0] a,
input [7:0] b,
output [8:0] o
);
wire [7:0] _GEN_0 = ~b;
assign o = a + _GEN_0;
endmodule
| 7.3741 |
module AddOperation (
input [11:0] lhs,
input [11:0] rhs,
output [11:0] result,
output overflow
);
assign {overflow, result} = lhs + rhs;
endmodule
| 7.010186 |
module addPC (
input wire [`digitsBus] f_pc,
input wire need_regids,
input wire need_valc,
output reg [`digitsBus] valPC
);
always @(*) begin
if (need_regids == 1 && need_valc == 1) begin
valPC = f_pc + 10;
end else if (need_valc == 1) begin
valPC = f_pc + 9;
end else if (need... | 6.538683 |
module AddPC1 (
input [31:0] PC,
output [31:0] PC4
);
assign PC4 = PC + 4;
endmodule
| 7.643128 |
module AddPC2 (
input [31:0] PC4,
input [31:0] Extend_Out,
output [31:0] NewPC
);
assign NewPC = PC4 + (Extend_Out << 2);
endmodule
| 8.243585 |
module AddPP_ForL (
input Clk,
input Rst,
input [1:0] MulHoldFlagFromEx,
input [`DataWidth_CSA30 - 1 : 0] SumPP_CSA30,
input [`DataWidth_CSA31 - 1 : 0] SumPP_CSA31,
input [`DataWidth_CSA30 - 1 : 0] CarryPP_CSA30,
input [`DataWidth_CSA31 - 1 : 0] CarryPP_CSA31,
input Mulitiplier_63,
o... | 6.576087 |
module AddProcess (
input [31:0] z_postAllign,
input [3:0] Opcode_Allign,
input idle_Allign,
input [35:0] cout_Allign,
input [35:0] zout_Allign,
input [31:0] sout_Allign,
input [7:0] InsTagAllign,
input clock,
output reg idle_AddState,
output reg [31:0] sout_AddState,
output ... | 6.818314 |
module ADDR1MUX (
input ADDR1MUX,
input [15:0] ADDR1FromPC,
input [15:0] ADDR1FromRF,
output reg [15:0] ADDR1
);
initial ADDR1 = 0;
always @(*) begin
if (ADDR1MUX) ADDR1 = ADDR1FromRF;
else ADDR1 = ADDR1FromPC;
end
endmodule
| 7.595127 |
module addr2 (
clk,
rst,
d0_i,
d1_i,
d_o
);
parameter IN_WIDTH = 32;
input clk;
input rst;
input wire [IN_WIDTH-1:0] d0_i;
input wire [IN_WIDTH-1:0] d1_i;
output reg [IN_WIDTH:0] d_o;
always @(posedge clk) begin
if (rst) d_o <= 0;
else d_o <= {{1{d0_i[IN_WIDTH-1]}}, d0_i} + {... | 7.539759 |
module ADDR2MUX (
input [1:0] ADDR2MUX,
input [15:0] offset6,
input [15:0] offset9,
input [15:0] offset11,
output reg [15:0] ADDR2
);
always @(*) begin
case (ADDR2MUX)
2'b00: ADDR2 = 0;
2'b01: ADDR2 = offset6;
2'b10: ADDR2 = offset9;
2'b11: ADDR2 = offset11;
... | 7.664226 |
module addr3 (
clk,
rst,
d0_i,
d1_i,
d2_i,
d_o
);
parameter IN_WIDTH = 32;
input clk;
input rst;
input wire [IN_WIDTH-1:0] d0_i;
input wire [IN_WIDTH-1:0] d1_i;
input wire [IN_WIDTH-1:0] d2_i;
output reg [IN_WIDTH:0] d_o;
always @(posedge clk) begin
if (rst) d_o <= 0;
e... | 7.407225 |
module AddrAdder (
input [15:0] A,
input [15:0] B,
output [15:0] out
);
assign out = A + B;
endmodule
| 8.212727 |
module AddrAnalyzer (
din,
NowDevice
);
input [31:0] din;
output NowDevice;
assign NowDevice = (din >= 'h0000_0000 && din <= 'h0000_2FFF) ? `NOWDEVICE_MEMO :
(din >= 'h0000_7F00 && din <= 'h0000_7FE0) ? `NOWDEVICE_IO :
'b0;
endmodule
| 6.680031 |
module exports the common arithmetic path to compute the memory address
//
// Implementation notes:
//
// The address to be computated goes as follows:
// addr = offset + row_idx * col_dim + col_idx
// =============================================================================
`include "pe.vh"
module AddrComp (
... | 8.820374 |
module addrConv (
input [8:0] addrIN,
input sign,
output [8:0] addrOUT
);
reg [8:0] addrOUT;
always @(*) begin
if (sign == 0) addrOUT = addrIN;
else addrOUT = ~addrIN + 1;
end
endmodule
| 7.346157 |
module AddrDec (
input [12:0] ADDRESS,
output reg ROM_EN,
output reg RAM_EN
);
always @(ADDRESS)
casex (ADDRESS)
13'b0_xxxx_xxxx_xxxx: {RAM_EN, ROM_EN} <= 2'b01;
13'b1_xxxx_xxxx_xxxx: {RAM_EN, ROM_EN} <= 2'b10;
default: {RAM_EN, ROM_EN} <= 2'b00;
endcase
endmodule
| 7.17026 |
module ADDRDecoding (
input [31:0] addr,
output cs // 0 = memoria interna, 1 = memoria externa
);
// Memoria interna de 1kB (400h B), começando em 2 * 500h = A00h
// => 0A00h:0A00h+03FF
// => 0A00h:0DFF
// =>
// | 11:8 | CS | intern_addr 9:8
// ...
// 9 | 1001 | 1 | xxx
... | 7.002875 |
module addRecF32_add (
input [(`floatControlWidth - 1):0] control,
input [32:0] a,
input [32:0] b,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags
);
addRecFN #(8, 24) addRecFN (
control,
1'b0,
a,
b,
roundingMode,
out,
excepti... | 6.799924 |
module addRecF64_add (
input [(`floatControlWidth - 1):0] control,
input [64:0] a,
input [64:0] b,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags
);
addRecFN #(11, 53) addRecFN (
control,
1'b0,
a,
b,
roundingMode,
out,
except... | 6.609708 |
module addRecF32_sub (
input [(`floatControlWidth - 1):0] control,
input [32:0] a,
input [32:0] b,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags
);
addRecFN #(8, 24) addRecFN (
control,
1'b1,
a,
b,
roundingMode,
out,
excepti... | 6.804548 |
module addRecF64_sub (
input [(`floatControlWidth - 1):0] control,
input [64:0] a,
input [64:0] b,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags
);
addRecFN #(11, 53) addRecFN (
control,
1'b1,
a,
b,
roundingMode,
out,
except... | 6.71431 |
module AddRemoveArea (
Selector,
Increment,
RoomDigit1,
RoomDigit0
);
//inputs
input [7:0] Selector;
input wire Increment;
//outputs
output reg [3:0] RoomDigit1, RoomDigit0;
always @(posedge Increment) begin
if (Selector == 21) begin
if (RoomDigit0 == 4'b0000) begin //if 9 sec... | 7.353477 |
module AddRemovePerson (
Selector,
Increment,
RoomDigit1,
RoomDigit0
);
//inputs
input [7:0] Selector;
input wire Increment;
//outputs
output reg [3:0] RoomDigit1, RoomDigit0;
always @(posedge Increment) begin
if (Selector == 20) begin
if (RoomDigit0 == 4'b0000) begin //if 9 s... | 7.150211 |
module calculates the correct VRAM adress for the current pixel,
as long as the image-source module has outputted source = 1.
*/
module address_generator(clk, reset, frame, hpixel, vpixel, address, select);
input clk, reset;
input [5:0] frame;
input [6:0] hpixel, vpixel;
output [13:0] address;
output select... | 7.448165 |
module top (
input CLK,
input BTN_N,
output [15:0] LED_PANEL
);
led_main #(
.DELAY(1)
) main (
.CLK(CLK),
.resetn_btn(BTN_N),
.LED_PANEL(LED_PANEL)
);
endmodule
| 7.233807 |
module painter24 (
input clk,
input reset,
input [ 9:0] frame,
input [ 7:0] subframe,
input [ 5:0] x,
input [ 5:0] y,
output [23:0] rgb24
);
wire border, x_single_bit, y_single_bit;
reg [23:0] rgb;
assign border = x == 0 || y == 0 || x == 63 || y == 63;
assign x... | 6.846537 |
module top (
input CLK,
input BTN_N,
output [15:0] LED_PANEL
);
led_main #(
.DELAY(2)
) main (
.CLK(CLK),
.resetn_btn(BTN_N),
.LED_PANEL(LED_PANEL)
);
endmodule
| 7.233807 |
module painter24 (
input clk,
input reset,
input [ 9:0] frame,
input [ 7:0] subframe,
input [ 5:0] x,
input [ 5:0] y,
output [23:0] rgb24
);
wire border, x_single_bit, y_single_bit;
reg [23:0] rgb;
assign border = x == 0 || y == 0 || x == 63 || y == 63;
assign x... | 6.846537 |
module top (
input CLK,
input BTN_N,
output [15:0] LED_PANEL
);
led_main main (
.CLK(CLK),
.resetn_btn(BTN_N),
.LED_PANEL(LED_PANEL)
);
endmodule
| 7.233807 |
module add_decoder (
addrBank,
addrBlock,
addrRow,
addrIn,
enable
);
output reg [3:0] addrBank, addrBlock;
output reg [7:0] addrRow;
input wire [15:0] addrIn;
input wire enable;
always @(enable or addrIn) begin
if (!enable) begin
addrBank = addrIn[15:12];
addrBlock = add... | 7.130094 |
module AddressEncoder (
AddrIn,
AddrOut
);
input [14:0] AddrIn;
output reg [3:0] AddrOut;
always @(*) begin
case (AddrIn) // case ̿Ͽ AddrOut
15'b100_0000_0000_0000: AddrOut = 4'd0;
15'b000_0000_0000_0001: AddrOut = 4'd1;
15'b000_0000_0000_0010: AddrOut = 4'd2;
15'b000_0000_... | 7.539822 |
module AddressExtend (
input [15:0] pc_inc,
input [11:0] address,
output reg [15:0] extended
);
always @(pc_inc or address) begin
extended[0] = 0;
extended[15:13] = pc_inc[15:13];
extended[12:1] = address;
end
endmodule
| 7.771491 |
module addressGen (
clk,
rst,
gen_en,
sobel_en,
addr,
done
);
/// when enabled, will generate address values from 0 to 1023, essentially a counter
/// then will raise done to high
/// for a more robust implemenation, the size of address counter could be parameterized to be suitable ... | 6.615115 |
module AddressingUnit (
Rside,
Iside,
Address,
clk,
ResetPC,
PCplusI,
PCplus1,
RplusI,
Rplus0,
PCenable
);
input [15:0] Rside;
input [7:0] Iside;
input ResetPC, PCplusI, PCplus1, RplusI, Rplus0, PCenable;
input clk;
output [15:0] Address;
wire [15:0] PCout;
Program... | 7.270411 |
module addressing_disp_size_detect (
input [15:0] addressing_aligned,
output [15:0] addressing,
output [1:0] addressing_bytes,
output [3:0] displacement_bytes,
input have_modrm
);
wire disp1, disp0;
assign addressing = addressing_aligned;
wire disp0mask;
wire disp1mask;
and2$(
di... | 6.500531 |
module addressing_mode_decoder (
input wire [2:0] mode_i,
output reg pre_op_o,
output reg [1:0] other_val_o,
output reg modulo_o,
output reg br_o,
output reg ar_out_o,
output reg imm_o,
output reg ar_wren_o
);
`include "std_messages.vh"
always @* begin
other_val_o = 0;
modu... | 6.57379 |
module AddressMapper (
input [31:0] ALU_Result,
output [ 7:0] addr
);
assign addr = (ALU_Result - 11'd1024) >> 2;
endmodule
| 6.758881 |
module AddressMapper_8_to_18 (
input [ 7:0] addr1,
output [17:0] addr2
);
assign addr2 = (addr1) << 1;
endmodule
| 6.758881 |
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