code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module half_adder (
x, //INPUT1
y, //INPUT2
s, //SUM
c //CARRY
);
input x, y;
output s, c;
assign s = x ^ y;
assign c = x & y;
endmodule
| 6.966406 |
module adder_test1_tb;
reg clock;
reg RSTB;
reg CSB;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
wire [7:0] mprj_io_0;
wire [15:0] checkbits;
// TODO assign check bits
assign checkbits = mprj_io[31:16];
assign mprj_io[3] = 1'b1;
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
// would be the fast clock.
always #12.5 clock <= (clock === 1'b0);
initial begin
clock = 0;
end
initial begin
$dumpfile("adder_test1.vcd");
$dumpvars(0, adder_test1_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (70) begin
repeat (1000) @(posedge clock);
// $display("+1000 cycles");
end
$display("%c[1;31m", 27);
`ifdef GL
$display("Monitor: Timeout, Adder Test 1 (GL) Failed");
`else
$display("Monitor: Timeout, Adder Test 1 (RTL) Failed");
`endif
$display("%c[0m", 27);
$finish;
end
initial begin
wait (checkbits == 16'hAB60);
$display("Monitor: Adder Test 1 Started");
wait (checkbits == 16'hAB61);
`ifdef GL
$display("Monitor: Adder Test 1 (GL) Passed");
`else
$display("Monitor: Adder Test 1 (RTL) Passed");
`endif
$finish;
end
initial begin
RSTB <= 1'b0;
CSB <= 1'b1; // Force CSB high
#2000;
RSTB <= 1'b1; // Release reset
#100000;
CSB = 1'b0; // CSB can be released
end
initial begin // Power-up sequence
power1 <= 1'b0;
power2 <= 1'b0;
#200;
power1 <= 1'b1;
#200;
power2 <= 1'b1;
end
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire VDD3V3 = power1;
wire VDD1V8 = power2;
wire USER_VDD3V3 = power3;
wire USER_VDD1V8 = power4;
wire VSS = 1'b0;
caravel uut (
.vddio (VDD3V3),
.vddio_2 (VDD3V3),
.vssio (VSS),
.vssio_2 (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
.vdda1 (VDD3V3),
.vdda1_2 (VDD3V3),
.vdda2 (VDD3V3),
.vssa1 (VSS),
.vssa1_2 (VSS),
.vssa2 (VSS),
.vccd1 (VDD1V8),
.vccd2 (VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
.clock (clock),
.gpio (gpio),
.mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.resetb (RSTB)
);
spiflash #(
.FILENAME("adder_test1.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(), // not used
.io3() // not used
);
endmodule
| 6.667905 |
module adder_tester (
output [7:0] adder_operand1,
output [7:0] adder_operand2,
input [8:0] structural_sum,
input [8:0] behavioral_sum,
input clk,
output test_fail
);
// This 'reg assignment' sets the value of the 'error' register to 0 when 'make impact' is run
// This kind of initial value setting IS NOT synthesizable on ASICs. It only works on certain FPGAs.
reg error = 0;
assign test_fail = error;
reg [15:0] operands;
assign adder_operand1 = operands[7:0];
assign adder_operand2 = operands[15:8];
// Iterate the operands continuously until all combinations are tried
always @(posedge clk) begin
operands <= operands + 1'd1;
end
// If we encounter a case where the adders don't match, or we have already encountered one such case,
// flip the error register high and hold it there.
always @(posedge clk) begin
if (structural_sum != behavioral_sum) begin
error <= 1'b1;
end else begin
error <= error;
end
end
endmodule
| 9.465263 |
module adder_test_tb;
reg clock;
reg RSTB;
reg reset;
reg CSB;
integer cycle_count;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
wire [3:0] checkbits;
reg a;
assign mprj_io[13:10] = a;
reg b;
assign mprj_io[17:14] = b;
assign checkbits = mprj_io[31:28];
always #12.5 clock <= (clock === 1'b0);
initial begin
clock = 0;
end
initial begin
$dumpfile("adder_test.vcd");
$dumpvars(0, adder_test_tb);
#1;
//Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (25) begin
repeat (1000) @(posedge clock);
// $display("+1000 cycles");
end
$display("%c[1;31m", 27);
`ifdef GL
$display("Monitor: Timeout, Test Mega-Project Loopback (GL) Failed");
`else
$display("Monitor: Timeout, Test Mega-Project Loopback (RTL) Failed");
`endif
$display("%c[0m", 27);
$finish;
end
// initial begin
// wait(checkbits == 16'hAB60);
// $display("Monitor: Test 2 MPRJ-Logic Analyzer Started");
// wait(checkbits == 16'hAB61);
// $display("Monitor: Test 2 MPRJ-Logic Analyzer Passed");
// $finish;
// end
initial begin
// assert(0 <= `VTB_INPUT_DELAY)
// else $fatal("\n=====\n\nVTB_INPUT_DELAY should >= 0\n\n=====\n");
// assert(`VTB_INPUT_DELAY < `VTB_OUTPUT_ASSERT_DELAY)
// else $fatal("\n=====\n\nVTB_OUTPUT_ASSERT_DELAY should be larger than VTB_INPUT_DELAY\n\n=====\n");
// assert(`VTB_OUTPUT_ASSERT_DELAY <= `CYCLE_TIME)
// else $fatal("\n=====\n\nVTB_OUTPUT_ASSERT_DELAY should be smaller than or equal to CYCLE_TIME\n\n=====\n");
wait (checkbits == 4'hA);
// Wait for lower edge
wait (clock == 1);
wait (clock == 0);
#6;
// Basic Test
a = 4'b0001;
b = 4'b0001;
#12.5;
if (mprj_io[21:18] != 4'b0010) begin
$display("failed :(");
$finish;
end
$display("");
$display(" [ passed ]");
$display("");
// Tick one extra cycle for better waveform
#12.5;
cycle_count += 1;
$finish;
end
initial begin
RSTB <= 1'b0;
CSB <= 1'b1; // Force CSB high
#2000;
RSTB <= 1'b1; // Release reset
#300000;
CSB = 1'b0; // CSB can be released
end
initial begin // Power-up sequence
power1 <= 1'b0;
power2 <= 1'b0;
power3 <= 1'b0;
power4 <= 1'b0;
#100;
power1 <= 1'b1;
#100;
power2 <= 1'b1;
#100;
power3 <= 1'b1;
#100;
power4 <= 1'b1;
end
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire VDD1V8;
wire VDD3V3;
wire VSS;
assign VDD3V3 = power1;
assign VDD1V8 = power2;
assign VSS = 1'b0;
assign mprj_io[3] = 1; // Force CSB high.
assign mprj_io[0] = 0; // Disable debug mode
caravel uut (
.vddio (VDD3V3),
.vddio_2 (VDD3V3),
.vssio (VSS),
.vssio_2 (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
.vdda1 (VDD3V3),
.vdda1_2 (VDD3V3),
.vdda2 (VDD3V3),
.vssa1 (VSS),
.vssa1_2 (VSS),
.vssa2 (VSS),
.vccd1 (VDD1V8),
.vccd2 (VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
.clock (clock),
.gpio (gpio),
.mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.resetb (RSTB)
);
spiflash #(
.FILENAME("adder_test.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(),
.io3()
);
endmodule
| 7.006654 |
module for adder
module adder_top
(
input clk, // 100MHz clock signal
input btnC, // reset signal
input RsRx, // RS232 Rx signal
output RsTx // RS232 Tx signal
);
wire rst;
assign rst = btnC;
wire [15:0] adder_opr1, adder_opr2, adder_ans;
wire adder_carry;
hci adder_hci(
.clk(clk),
.rst(rst),
.rx(RsRx),
.tx(RsTx),
.adder_opr1(adder_opr1),
.adder_opr2(adder_opr2),
.adder_ans(adder_ans),
.adder_carry(adder_carry)
);
adder adder(
adder_opr1, // first operand
adder_opr2, // second operand
adder_ans, // result
adder_carry // carry bit
);
endmodule
| 7.149058 |
module adder_tree #(
parameter LAYER_NUM = 4,
parameter MIN_ADDER_WIDTH = 8
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input [(2 ** LAYER_NUM) * MIN_ADDER_WIDTH - 1:0] adder_din,
output [LAYER_NUM + MIN_ADDER_WIDTH - 1:0] adder_dout
);
genvar i;
generate
for (i = LAYER_NUM; i > 0; i = i - 1) begin : adder_layer_def
wire [(2 ** i) * (MIN_ADDER_WIDTH + LAYER_NUM - i) - 1:0] layer_din;
wire [2 ** (i - 1) * (MIN_ADDER_WIDTH + LAYER_NUM - i + 1) - 1:0] layer_dout;
if (i == LAYER_NUM) begin
assign layer_din = adder_din;
end else begin
assign layer_din = adder_layer_def[i+1].layer_dout;
end
adder_layer #(
.ADDER_NUM (2 ** (i - 1)),
.ADDER_WIDTH(MIN_ADDER_WIDTH + LAYER_NUM - i)
) u_adder_layer (
.clk(clk), // Clock
.rst_n(rst_n), // Asynchronous reset active low
.adder_din(layer_din),
.adder_dout(layer_dout)
);
end
endgenerate
assign adder_dout = adder_layer_def[1].layer_dout;
endmodule
| 6.824939 |
module adder (
s,
co,
a,
b,
ci
);
output s, co; //Outputs of Sum and Carry Out
input a, b, ci; //Inputs of A, b and Carry In
wire o0, o1, o2; //Internal wiring
xor (s, a, b, ci); //Calculation of Sum
or (o0, a, b); //Calculation of Carry Out
or (o1, b, ci);
or (o2, ci, a);
and (co, o0, o1, o2);
endmodule
| 7.276647 |
module adder7 (
s,
co,
a,
b,
ci
);
output [6:0] s; //7-bit Sum output
output co; //Output bit of Carry out
input [6:0] a, b; //7-bit Input A and B
input ci; //Input bit of Carry in
wire c1, c2, c3, c4, c5, c6;
adder a0 (
s[0],
c1,
a[0],
b[0],
ci
);
adder a1 (
s[1],
c2,
a[1],
b[1],
c1
);
adder a2 (
s[2],
c3,
a[2],
b[2],
c2
);
adder a3 (
s[3],
c4,
a[3],
b[3],
c3
);
adder a4 (
s[4],
c5,
a[4],
b[4],
c4
);
adder a5 (
s[5],
c6,
a[5],
b[5],
c5
);
adder a6 (
s[6],
co,
a[6],
b[6],
c6
);
endmodule
| 7.475421 |
module adder4_2 (
s,
co,
a,
b,
c,
d
); //used as second level in tree structure
output [6:0] s,co; //7-bit Sum output and 7-bit carry in where co[0] = 0 (Carry In will be added in later)
input [6:0] a, b, c, d; //7-bit Input A, B, C, D
wire [6:0] ts;
wire [6:0] tc;
wire c1, c2; //crap 1 and 2
assign co[0] = 0;
assign tc[0] = 0;
adder s00 (
ts[0],
tc[1],
a[0],
b[0],
c[0]
);
adder s01 (
ts[1],
tc[2],
a[1],
b[1],
c[1]
);
adder s02 (
ts[2],
tc[3],
a[2],
b[2],
c[2]
);
adder s03 (
ts[3],
tc[4],
a[3],
b[3],
c[3]
);
adder s04 (
ts[4],
tc[5],
a[4],
b[4],
c[4]
);
adder s05 (
ts[5],
tc[6],
a[5],
b[5],
c[5]
);
adder s06 (
ts[6],
c1,
a[6],
b[6],
c[6]
);
adder s10 (
s[0],
co[1],
ts[0],
d[0],
tc[0]
);
adder s11 (
s[1],
co[2],
ts[1],
d[1],
tc[1]
);
adder s12 (
s[2],
co[3],
ts[2],
d[2],
tc[2]
);
adder s13 (
s[3],
co[4],
ts[3],
d[3],
tc[3]
);
adder s14 (
s[4],
co[5],
ts[4],
d[4],
tc[4]
);
adder s15 (
s[5],
co[6],
ts[5],
d[5],
tc[5]
);
adder s16 (
s[6],
c2,
ts[6],
d[6],
tc[6]
);
endmodule
| 6.856983 |
module adder5_2 (
s,
co,
a,
b,
c,
d,
e
);
output [6:0] s,co; //7-bit Sum output and 7-bit carry in where co[0] = 0 (Carry In will be added in later)
input [6:0] a, b, c, d, e; //7-bit Input A, B, C, D, E
wire [6:0] ts0, ts1;
wire [6:0] tc0, tc1;
wire c1, c2, c3, c4; //crap 1 and 2
wire t1, t2;
assign tc0[0] = 0;
assign tc1[0] = 0;
assign co[0] = 0;
adder s00 (
ts0[0],
tc0[1],
a[0],
b[0],
c[0]
);
adder s01 (
ts0[1],
tc0[2],
a[1],
b[1],
c[1]
);
adder s02 (
ts0[2],
tc0[3],
a[2],
b[2],
c[2]
);
adder s03 (
ts0[3],
tc0[4],
a[3],
b[3],
c[3]
);
adder s04 (
ts0[4],
tc0[5],
a[4],
b[4],
c[4]
);
adder s05 (
ts0[5],
tc0[6],
a[5],
b[5],
c[5]
);
adder s06 (
ts0[6],
c1,
a[6],
b[6],
c[6]
);
adder s10 (
ts1[0],
tc1[1],
ts0[0],
d[0],
e[0]
);
adder s11 (
ts1[1],
tc1[2],
ts0[1],
d[1],
e[1]
);
adder s12 (
ts1[2],
tc1[3],
ts0[2],
d[2],
e[2]
);
adder s13 (
ts1[3],
tc1[4],
ts0[3],
d[3],
e[3]
);
adder s14 (
ts1[4],
tc1[5],
ts0[4],
d[4],
e[4]
);
adder s15 (
ts1[5],
tc1[6],
ts0[5],
d[5],
e[5]
);
adder s16 (
ts1[6],
c2,
ts0[6],
d[6],
e[6]
);
adder s20 (
s[0],
co[1],
ts1[0],
tc0[0],
tc1[0]
);
adder s21 (
s[1],
co[2],
ts1[1],
tc0[1],
tc1[1]
);
adder s22 (
s[2],
co[3],
ts1[2],
tc0[2],
tc1[2]
);
adder s23 (
s[3],
co[4],
ts1[3],
tc0[3],
tc1[3]
);
adder s24 (
s[4],
co[5],
ts1[4],
tc0[4],
tc1[4]
);
adder s25 (
s[5],
co[6],
ts1[5],
tc0[5],
tc1[5]
);
adder s26 (
s[6],
c3,
ts1[6],
tc0[6],
tc1[6]
);
endmodule
| 7.126116 |
module adder_tree5 (
s,
co,
a,
b,
c,
d,
e,
f,
g,
h,
i,
j,
ci
);
output [6:0] s;
output co;
input [6:0] a, b, c, d, e, f, g, h, i, j;
input ci;
wire [6:0] ts1, ts2, ts3;
wire [6:0] tc1, tc2, tc3;
//3:2 adders in linear fashion
adder5_2 a1 (
ts1,
tc1,
a,
b,
c,
d,
e
);
adder5_2 a2 (
ts2,
tc2,
f,
g,
h,
i,
j
);
adder4_2 a3 (
ts3,
tc3,
ts1,
tc1,
ts2,
tc2
);
adder7 a4 (
s,
co,
ts3,
tc3,
ci
); //normal FA implementation, adds in ci
endmodule
| 7.113805 |
module adder_tree (
input wire [7:0] a,
b,
c,
d,
e,
f,
g,
h,
input wire clk,
rst,
output wire [10:0] y
);
reg [8:0] i11, i12, i13, i14;
reg [9:0] i21, i22;
reg [10:0] i31;
always @(posedge clk, posedge rst) begin
if (rst) begin
i11 <= 0;
i12 <= 0;
i13 <= 0;
i14 <= 0;
i21 <= 0;
i22 <= 0;
end else begin
i11 <= a + b;
i12 <= c + d;
i13 <= e + f;
i14 <= g + h;
i21 <= i11 + i12;
i22 <= i13 + i14;
i31 <= i21 + i22;
end
end
assign y = i31;
endmodule
| 6.756517 |
module adder_tree_2stage_16bit (
clk,
reset,
inp00,
inp01,
inp10,
inp11,
sum_out
);
input clk;
input reset;
input [15:0] inp00;
input [15:0] inp01;
input [15:0] inp10;
input [15:0] inp11;
output reg [31:0] sum_out;
reg [16:0] S_0_0;
reg [16:0] S_0_1;
always @(posedge clk) begin
S_0_0 <= inp00 + inp01;
S_0_1 <= inp10 + inp11;
end
always @(posedge clk) begin
if (reset == 1'b1) begin
sum_out <= 32'd0;
end else begin
sum_out <= S_0_0 + S_0_1;
end
end
endmodule
| 6.548304 |
module adder_tree_2stage_4bit (
clk,
reset,
inp00,
inp01,
inp10,
inp11,
sum_out
);
input clk;
input reset;
input [3:0] inp00;
input [3:0] inp01;
input [3:0] inp10;
input [3:0] inp11;
output reg [7:0] sum_out;
reg [4:0] S_0_0;
reg [4:0] S_0_1;
always @(posedge clk) begin
S_0_0 <= inp00 + inp01;
S_0_1 <= inp10 + inp11;
end
always @(posedge clk) begin
if (reset == 1'b1) begin
sum_out <= 8'd0;
end else begin
sum_out <= S_0_0 + S_0_1;
end
end
endmodule
| 6.548304 |
module adder_tree_2stage_8bit (
clk,
reset,
inp00,
inp01,
inp10,
inp11,
sum_out
);
input clk;
input reset;
input [7:0] inp00;
input [7:0] inp01;
input [7:0] inp10;
input [7:0] inp11;
output reg [15:0] sum_out;
reg [8:0] S_0_0;
reg [8:0] S_0_1;
always @(posedge clk) begin
S_0_0 <= inp00 + inp01;
S_0_1 <= inp10 + inp11;
end
always @(posedge clk) begin
if (reset == 1'b1) begin
sum_out <= 16'd0;
end else begin
sum_out <= S_0_0 + S_0_1;
end
end
endmodule
| 6.548304 |
module adder_tree_3stage_16bit (
clk,
reset,
inp00,
inp01,
inp10,
inp11,
inp20,
inp21,
inp30,
inp31,
sum_out
);
input clk;
input reset;
input [15:0] inp00;
input [15:0] inp01;
input [15:0] inp10;
input [15:0] inp11;
input [15:0] inp20;
input [15:0] inp21;
input [15:0] inp30;
input [15:0] inp31;
output reg [31:0] sum_out;
reg [16:0] S_0_0;
reg [16:0] S_0_1;
reg [16:0] S_0_2;
reg [16:0] S_0_3;
always @(posedge clk) begin
S_0_0 <= inp00 + inp01;
S_0_1 <= inp10 + inp11;
S_0_2 <= inp20 + inp21;
S_0_3 <= inp30 + inp31;
end
reg [17:0] S_1_0;
reg [17:0] S_1_1;
always @(posedge clk) begin
S_1_0 <= S_0_0 + S_0_1;
S_1_1 <= S_0_2 + S_0_3;
end
always @(posedge clk) begin
if (reset == 1'b1) begin
sum_out <= 32'd0;
end else begin
sum_out <= S_1_0 + S_1_1;
end
end
endmodule
| 6.622442 |
module adder_tree_3stage_4bit (
clk,
reset,
inp00,
inp01,
inp10,
inp11,
inp20,
inp21,
inp30,
inp31,
sum_out
);
input clk;
input reset;
input [3:0] inp00;
input [3:0] inp01;
input [3:0] inp10;
input [3:0] inp11;
input [3:0] inp20;
input [3:0] inp21;
input [3:0] inp30;
input [3:0] inp31;
output reg [7:0] sum_out;
reg [4:0] S_0_0;
reg [4:0] S_0_1;
reg [4:0] S_0_2;
reg [4:0] S_0_3;
always @(posedge clk) begin
S_0_0 <= inp00 + inp01;
S_0_1 <= inp10 + inp11;
S_0_2 <= inp20 + inp21;
S_0_3 <= inp30 + inp31;
end
reg [5:0] S_1_0;
reg [5:0] S_1_1;
always @(posedge clk) begin
S_1_0 <= S_0_0 + S_0_1;
S_1_1 <= S_0_2 + S_0_3;
end
always @(posedge clk) begin
if (reset == 1'b1) begin
sum_out <= 8'd0;
end else begin
sum_out <= S_1_0 + S_1_1;
end
end
endmodule
| 6.622442 |
module adder_tree_3stage_8bit (
clk,
reset,
inp00,
inp01,
inp10,
inp11,
inp20,
inp21,
inp30,
inp31,
sum_out
);
input clk;
input reset;
input [7:0] inp00;
input [7:0] inp01;
input [7:0] inp10;
input [7:0] inp11;
input [7:0] inp20;
input [7:0] inp21;
input [7:0] inp30;
input [7:0] inp31;
output reg [15:0] sum_out;
reg [8:0] S_0_0;
reg [8:0] S_0_1;
reg [8:0] S_0_2;
reg [8:0] S_0_3;
always @(posedge clk) begin
S_0_0 <= inp00 + inp01;
S_0_1 <= inp10 + inp11;
S_0_2 <= inp20 + inp21;
S_0_3 <= inp30 + inp31;
end
reg [9:0] S_1_0;
reg [9:0] S_1_1;
always @(posedge clk) begin
S_1_0 <= S_0_0 + S_0_1;
S_1_1 <= S_0_2 + S_0_3;
end
always @(posedge clk) begin
if (reset == 1'b1) begin
sum_out <= 16'd0;
end else begin
sum_out <= S_1_0 + S_1_1;
end
end
endmodule
| 6.622442 |
module FPAddSub (
clk,
rst,
a,
b,
operation, // 0 add, 1 sub
result,
flags
);
// Clock and reset
input clk; // Clock signal
input rst; // Reset (active high, resets pipeline registers)
// Input ports
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
input operation; // Operation select signal
// Output ports
output [`DWIDTH-1:0] result; // Result of the operation
output [4:0] flags; // Flags indicating exceptions according to IEEE754
assign flags = 5'b0;
//`ifdef complex_dsp
//adder_fp_clk u_add(.clk(clk), .a(a), .b(b),.out(result));
//`else
FPAddSub_16 u_FPAddSub (
.clk(clk),
.rst(rst),
.a(a),
.b(b),
.operation(1'b0),
.result(result),
.flags()
);
//`endif
endmodule
| 6.989325 |
module is responsible for taking the inputs
// apart and checking the parts for exceptions.
// The exponent difference is also calculated in this module.
//
module FPAddSub_PrealignModule(
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWIDTH-1:0] A ; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] B ; // Input B, a 32-bit floating point number
input operation ;
// Output ports
output Sa ; // A's sign
output Sb ; // B's sign
output [2*`EXPONENT-1:0] ShiftDet ;
output [4:0] InputExc ; // Input numbers are exceptions
output [`DWIDTH-2:0] Aout ;
output [`DWIDTH-2:0] Bout ;
output Opout ;
// Internal signals // If signal is high...
wire ANaN ; // A is a NaN (Not-a-Number)
wire BNaN ; // B is a NaN
wire AInf ; // A is infinity
wire BInf ; // B is infinity
wire [`EXPONENT-1:0] DAB ; // ExpA - ExpB
wire [`EXPONENT-1:0] DBA ; // ExpB - ExpA
assign ANaN = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(A[`MANTISSA-1:0]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(B[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(A[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(B[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
// Put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ;
//assign DAB = (A[30:23] - B[30:23]) ;
//assign DBA = (B[30:23] - A[30:23]) ;
assign DAB = (A[`DWIDTH-2:`MANTISSA] + ~(B[`DWIDTH-2:`MANTISSA]) + 1) ;
assign DBA = (B[`DWIDTH-2:`MANTISSA] + ~(A[`DWIDTH-2:`MANTISSA]) + 1) ;
assign Sa = A[`DWIDTH-1] ; // A's sign bit
assign Sb = B[`DWIDTH-1] ; // B's sign bit
assign ShiftDet = {DBA[`EXPONENT-1:0], DAB[`EXPONENT-1:0]} ; // Shift data
assign Opout = operation ;
assign Aout = A[`DWIDTH-2:0] ;
assign Bout = B[`DWIDTH-2:0] ;
endmodule
| 7.391888 |
module determines the larger input operand and
// sets the mantissas, shift and common exponent accordingly.
//
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number
input [`DWIDTH-2:0] B ; // Input B, a 32-bit floating point number
input [2*`EXPONENT-1:0] ShiftDet ;
// Output ports
output [`EXPONENT-1:0] CExp ; // Common Exponent
output MaxAB ; // Incidates larger of A and B (0/A, 1/B)
output [`EXPONENT-1:0] Shift ; // Number of steps to smaller mantissa shift right
output [`MANTISSA-1:0] Mmin ; // Smaller mantissa
output [`MANTISSA-1:0] Mmax ; // Larger mantissa
// Internal signals
//wire BOF ; // Check for shifting overflow if B is larger
//wire AOF ; // Check for shifting overflow if A is larger
assign MaxAB = (A[`DWIDTH-2:0] < B[`DWIDTH-2:0]) ;
//assign BOF = ShiftDet[9:5] < 25 ; // Cannot shift more than 25 bits
//assign AOF = ShiftDet[4:0] < 25 ; // Cannot shift more than 25 bits
// Determine final shift value
//assign Shift = MaxAB ? (BOF ? ShiftDet[9:5] : 5'b11001) : (AOF ? ShiftDet[4:0] : 5'b11001) ;
assign Shift = MaxAB ? ShiftDet[2*`EXPONENT-1:`EXPONENT] : ShiftDet[`EXPONENT-1:0] ;
// Take out smaller mantissa and append shift space
assign Mmin = MaxAB ? A[`MANTISSA-1:0] : B[`MANTISSA-1:0] ;
// Take out larger mantissa
assign Mmax = MaxAB ? B[`MANTISSA-1:0]: A[`MANTISSA-1:0] ;
// Common exponent
assign CExp = (MaxAB ? B[`MANTISSA+`EXPONENT-1:`MANTISSA] : A[`MANTISSA+`EXPONENT-1:`MANTISSA]) ;
endmodule
| 6.986217 |
module FPAddSub_AlignShift1 (
//bf16,
MminP,
Shift,
Mmin
);
// Input ports
//input bf16;
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [`EXPONENT-3:0] Shift ; // Shift amount. Last 2 bits of shifting are done in next stage. Hence, we have [`EXPONENT - 2] bits
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
wire bf16;
assign bf16 = 1'b1; //hardcoding to 1, to avoid ODIN issue. a `ifdef here wasn't working. apparently, nested `ifdefs don't work
// Internal signals
reg [ `MANTISSA:0] Lvl1;
reg [ `MANTISSA:0] Lvl2;
wire [2*`MANTISSA+1:0] Stage1;
integer i; // Loop variable
wire [ `MANTISSA:0] temp_0;
assign temp_0 = 0;
always @(*) begin
if (bf16 == 1'b1) begin
//hardcoding for bfloat16
//For bfloat16, we can shift the mantissa by a max of 7 bits since mantissa has a width of 7.
//Hence if either, bit[3]/bit[4]/bit[5]/bit[6]/bit[7] is 1, we can make it 0. This corresponds to bits [5:1] in our updated shift which doesn't contain last 2 bits.
//Lvl1 <= (Shift[1]|Shift[2]|Shift[3]|Shift[4]|Shift[5]) ? {temp_0} : {1'b1, MminP}; // MANTISSA + 1 width
Lvl1 <= (|Shift[`EXPONENT-3:1]) ? {temp_0} : {1'b1, MminP}; // MANTISSA + 1 width
end else begin
//for half precision fp16, 10 bits can be shifted. Hence, only shifts till 10 (01010)can be made.
Lvl1 <= Shift[2] ? {temp_0} : {1'b1, MminP};
end
end
assign Stage1 = {Lvl1, Lvl1}; //2*MANTISSA + 2 width
always @(*) begin // Rotate {0 | 4 } bits
if (bf16 == 1'b1) begin
case (Shift[0])
// Rotate by 0
1'b0: Lvl2 <= Stage1[`MANTISSA:0];
// Rotate by 4
1'b1: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+4];
end
end
endcase
end else begin
case (Shift[1:0]) // Rotate {0 | 4 | 8} bits
// Rotate by 0
2'b00: Lvl2 <= Stage1[`MANTISSA:0];
// Rotate by 4
2'b01: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+4];
end
end
// Rotate by 8
2'b10: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+8];
end
end
// Rotate by 12
2'b11: Lvl2[`MANTISSA:0] <= 0;
//2'b11: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end end
endcase
end
end
// Assign output to next shift stage
assign Mmin = Lvl2;
endmodule
| 6.969233 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount. Last 2 bits
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANTISSA:0] Lvl3;
wire [2*`MANTISSA+1:0] Stage2;
integer j; // Loop variable
assign Stage2 = {MminP, MminP};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift[1:0])
// Rotate by 0
2'b00: Lvl3 <= Stage2[`MANTISSA:0];
// Rotate by 1
2'b01: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+1];
end
end
// Rotate by 2
2'b10: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+2];
end
end
// Rotate by 3
2'b11: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+3];
end
end
endcase
end
// Assign output
assign Mmin = Lvl3; // Take out smaller mantissa
endmodule
| 6.969233 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of smaller number
input MaxAB; // Indicates the larger number (0/A, 1/B)
input OpMode; // Operation to be performed (0/Add, 1/Sub)
// Output ports
output [`DWIDTH:0] Sum; // The result of the operation
output PSgn; // The sign for the result
output Opr; // The effective (performed) operation
wire [`EXPONENT-1:0] temp_1;
assign Opr = (OpMode ^ Sa ^ Sb); // Resolve sign to determine operation
assign temp_1 = 0;
// Perform effective operation
//SAMIDH_UNSURE 5--> 8
assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, temp_1} - {Mmin, temp_1}) : ({1'b1, Mmax, temp_1} + {Mmin, temp_1}) ;
// Assign result sign
assign PSgn = (MaxAB ? Sb : Sa);
endmodule
| 6.632792 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
//Changes in this doesn't matter since even Bfloat16 can't go beyond 7 shift to the mantissa (only 3 bits valid here)
// Determine normalization shift amount by finding leading nought
assign Shift = (
Sum[16] ? 5'b00000 :
Sum[15] ? 5'b00001 :
Sum[14] ? 5'b00010 :
Sum[13] ? 5'b00011 :
Sum[12] ? 5'b00100 :
Sum[11] ? 5'b00101 :
Sum[10] ? 5'b00110 :
Sum[9] ? 5'b00111 :
Sum[8] ? 5'b01000 :
Sum[7] ? 5'b01001 :
Sum[6] ? 5'b01010 :
Sum[5] ? 5'b01011 :
Sum[4] ? 5'b01100 : 5'b01101
// Sum[19] ? 5'b01101 :
// Sum[18] ? 5'b01110 :
// Sum[17] ? 5'b01111 :
// Sum[16] ? 5'b10000 :
// Sum[15] ? 5'b10001 :
// Sum[14] ? 5'b10010 :
// Sum[13] ? 5'b10011 :
// Sum[12] ? 5'b10100 :
// Sum[11] ? 5'b10101 :
// Sum[10] ? 5'b10110 :
// Sum[9] ? 5'b10111 :
// Sum[8] ? 5'b11000 :
// Sum[7] ? 5'b11001 : 5'b11010
);
reg [`DWIDTH:0] Lvl1;
always @(*) begin
// Rotate by 16?
Lvl1 <= Shift[4] ? {Sum[8:0], 8'b00000000} : Sum;
end
// Assign outputs
assign Mmin = Lvl1; // Take out smaller mantissa
endmodule
| 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1:0] Stage1;
reg [ `DWIDTH:0] Lvl3;
wire [2*`DWIDTH+1:0] Stage2;
integer i; // Loop variable
assign Stage1 = {MminP, MminP};
always @(*) begin // Rotate {0 | 4 | 8 | 12} bits
case (Shift[3:2])
// Rotate by 0
2'b00: Lvl2 <= Stage1[`DWIDTH:0];
// Rotate by 4
2'b01: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl2[i-`DWIDTH-1] <= Stage1[i-4];
end
Lvl2[3:0] <= 0;
end
// Rotate by 8
2'b10: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl2[i-`DWIDTH-1] <= Stage1[i-8];
end
Lvl2[7:0] <= 0;
end
// Rotate by 12
2'b11: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl2[i-`DWIDTH-1] <= Stage1[i-12];
end
Lvl2[11:0] <= 0;
end
endcase
end
assign Stage2 = {Lvl2, Lvl2};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift[1:0])
// Rotate by 0
2'b00: Lvl3 <= Stage2[`DWIDTH:0];
// Rotate by 1
2'b01: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl3[i-`DWIDTH-1] <= Stage2[i-1];
end
Lvl3[0] <= 0;
end
// Rotate by 2
2'b10: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl3[i-`DWIDTH-1] <= Stage2[i-2];
end
Lvl3[1:0] <= 0;
end
// Rotate by 3
2'b11: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl3[i-`DWIDTH-1] <= Stage2[i-3];
end
Lvl3[2:0] <= 0;
end
endcase
end
// Assign outputs
assign Mmin = Lvl3; // Take out smaller mantissa
endmodule
| 6.905513 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0] NormM; // Normalized mantissa
output [`EXPONENT:0] NormE; // Adjusted exponent
output ZeroSum; // Zero flag
output NegE; // Flag indicating negative exponent
output R; // Round bit
output S; // Final sticky bit
output FG;
// Internal signals
wire MSBShift; // Flag indicating that a second shift is needed
wire [`EXPONENT:0] ExpOF; // MSB set in sum indicates overflow
wire [`EXPONENT:0] ExpOK; // MSB not set, no adjustment
// Calculate normalized exponent and mantissa, check for all-zero sum
assign MSBShift = PSSum[`DWIDTH]; // Check MSB in unnormalized sum
assign ZeroSum = ~|PSSum; // Check for all zero sum
assign ExpOK = CExp - Shift; // Adjust exponent for new normalized mantissa
assign NegE = ExpOK[`EXPONENT]; // Check for exponent overflow
assign ExpOF = CExp - Shift + 1'b1; // If MSB set, add one to exponent(x2)
assign NormE = MSBShift ? ExpOF : ExpOK; // Check for exponent overflow
assign NormM = PSSum[`DWIDTH-1:`EXPONENT+1]; // The new, normalized mantissa
// Also need to compute sticky and round bits for the rounding stage
assign FG = PSSum[`EXPONENT];
assign R = PSSum[`EXPONENT-1];
assign S = |PSSum[`EXPONENT-2:0];
endmodule
| 6.905513 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round bit
input S; // Sticky bit
input G;
input Sa; // A's sign bit
input Sb; // B's sign bit
input Ctrl; // Control bit (operation)
input MaxAB;
// Output ports
output [`DWIDTH-1:0] Z; // Final result
output EOF;
// Internal signals
wire [ `MANTISSA:0] RoundUpM; // Rounded up sum with room for overflow
wire [`MANTISSA-1:0] RoundM; // The final rounded sum
wire [ `EXPONENT:0] RoundE; // Rounded exponent (note extra bit due to poential overflow )
wire RoundUp; // Flag indicating that the sum should be rounded up
wire FSgn;
wire ExpAdd; // May have to add 1 to compensate for overflow
wire RoundOF; // Rounding overflow
wire [ `EXPONENT:0] temp_2;
assign temp_2 = 0;
// The cases where we need to round upwards (= adding one) in Round to nearest, tie to even
assign RoundUp = (G & ((R | S) | NormM[0]));
// Note that in the other cases (rounding down), the sum is already 'rounded'
assign RoundUpM = (NormM + 1); // The sum, rounded up by 1
assign RoundM = (RoundUp ? RoundUpM[`MANTISSA-1:0] : NormM); // Compute final mantissa
assign RoundOF = RoundUp & RoundUpM[`MANTISSA]; // Check for overflow when rounding up
// Calculate post-rounding exponent
assign ExpAdd = (RoundOF ? 1'b1 : 1'b0); // Add 1 to exponent to compensate for overflow
assign RoundE = ZeroSum ? temp_2 : (NormE + ExpAdd); // Final exponent
// If zero, need to determine sign according to rounding
assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ;
// Assign final result
assign Z = {FSgn, RoundE[`EXPONENT-1:0], RoundM[`MANTISSA-1:0]};
// Indicate exponent overflow
assign EOF = RoundE[`EXPONENT];
endmodule
| 7.753919 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
input EOF;
// Output ports
output [`DWIDTH-1:0] P; // Final result
output [4:0] Flags; // Exception flags
// Internal signals
wire Overflow; // Overflow flag
wire Underflow; // Underflow flag
wire DivideByZero; // Divide-by-Zero flag (always 0 in Add/Sub)
wire Invalid; // Invalid inputs or result
wire Inexact; // Result is inexact because of rounding
// Exception flags
// Result is too big to be represented
assign Overflow = EOF | InputExc[1] | InputExc[0];
// Result is too small to be represented
assign Underflow = NegE & (R | S);
// Infinite result computed exactly from finite operands
assign DivideByZero = &(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~|(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~InputExc[1] & ~InputExc[0];
// Invalid inputs or operation
assign Invalid = |(InputExc[4:2]);
// Inexact answer due to rounding, overflow or underflow
assign Inexact = (R | S) | Overflow | Underflow;
// Put pieces together to form final result
assign P = Z;
// Collect exception flags
assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact};
endmodule
| 7.326377 |
module adder_tree_node (
clk,
a,
b,
out
);
parameter IN_BITS = 16;
parameter OUT_BITS = 17;
parameter SIGN_EXT = 1;
parameter REGISTER_MIDDLE = 0; // register within adder chains
parameter REGISTER_OUTPUT = 1; // register adder outputs
parameter B_SHIFT = 1;
// for the placement of the midway pipeline registers
localparam LS_WIDTH = OUT_BITS / 2;
localparam MS_WIDTH = OUT_BITS - LS_WIDTH;
input clk;
input [IN_BITS-1:0] a, b;
output [OUT_BITS-1:0] out;
// sign extension
wire [OUT_BITS-1:0] a_ext, b_ext;
generate
if (SIGN_EXT) begin
assign a_ext = {{(OUT_BITS - IN_BITS) {a[IN_BITS-1]}}, a};
assign b_ext = {{(OUT_BITS - IN_BITS) {b[IN_BITS-1]}}, b};
end else begin
assign a_ext = {{(OUT_BITS - IN_BITS) {1'b0}}, a};
assign b_ext = {{(OUT_BITS - IN_BITS) {1'b0}}, b};
end
endgenerate
// offset B
wire [OUT_BITS-1:0] b_ext_shft;
assign b_ext_shft = b_ext << B_SHIFT;
// addition
wire [OUT_BITS-1:0] sum;
generate
if (REGISTER_MIDDLE) begin
// pipeline in the middle of the adder chain
reg [LS_WIDTH-1+1:0] ls_adder;
wire cross_carry = ls_adder[LS_WIDTH];
always @(posedge clk) begin
ls_adder <= {1'b0, a_ext[LS_WIDTH-1:0]} + {1'b0, b_ext_shft[LS_WIDTH-1:0]};
end
reg [MS_WIDTH-1:0] ms_data_a, ms_data_b;
always @(posedge clk) begin
ms_data_a <= a_ext[OUT_BITS-1:OUT_BITS-MS_WIDTH];
ms_data_b <= b_ext_shft[OUT_BITS-1:OUT_BITS-MS_WIDTH];
end
wire [MS_WIDTH-1+1:0] ms_adder;
assign ms_adder = {ms_data_a, cross_carry} + {ms_data_b, cross_carry};
assign sum = {ms_adder[MS_WIDTH:1], ls_adder[LS_WIDTH-1:0]};
end else begin
// simple addition
assign sum = a_ext + b_ext_shft;
end
endgenerate
// optional output register
reg [OUT_BITS-1:0] out;
generate
if (REGISTER_OUTPUT) begin
always @(posedge clk) begin
out <= sum;
end
end else begin
always @(*) begin
out = sum;
end
end
endgenerate
endmodule
| 6.847166 |
module adder_tree_tb ();
parameter MIN_ADDER_WIDTH = 8;
parameter LAYER_NUM = 4;
reg clk;
reg rst_n;
reg [(2 ** (LAYER_NUM - 1)) * MIN_ADDER_WIDTH - 1:0] adder_din;
wire [LAYER_NUM + MIN_ADDER_WIDTH - 1:0] adder_dout;
adder_tree #(
.LAYER_NUM(4),
.MIN_ADDER_WIDTH(8)
) dut (
.clk (clk), // Clock
.rst_n(rst_n), // Asynchronous reset active low
.adder_din (adder_din),
.adder_dout(adder_dout)
);
initial begin : clk_gen
clk = 1'b0;
forever begin
#50 clk = ~clk;
end
end
initial begin : rst_gen
rst_n = 1'b1;
#5 rst_n = 1'b0;
#10 rst_n = 1'b1;
end
initial begin
adder_din = 'b0;
forever begin
@(negedge clk);
adder_din = ((2 ** (LAYER_NUM - 1)) * MIN_ADDER_WIDTH)'($urandom_range(0, 65535));
end
end
endmodule
| 6.588422 |
module adder_udp (
input x,
input y,
input cin,
output res,
output cout
);
addresult(
res, cin, x, y
); addcarry(
cout, cin, x, y
);
endmodule
| 7.301565 |
module adder_udp_tb;
reg x;
reg y;
reg cin;
wire res;
wire cout;
adder_udp uut (
.x(x),
.y(y),
.cin(cin),
.res(res),
.cout(cout)
);
initial begin
$dumpfile("adder_udp.vcd");
$dumpvars(0, adder_udp_tb);
x = 0;
y = 0;
cin = 0;
#20 x = 1;
#20;
y = 1;
#20;
x = 0;
#20;
cin = 1;
#20;
y = 0;
#20;
x = 1;
#20;
y = 1;
#40;
end
initial begin
$monitor("time = %2d, CIN =%1b, X=%1b, Y=%1b, COUT=%1b, RES=%1b", $time, cin, y, x, cout, res);
end
endmodule
| 7.15946 |
module adder_unit #(
parameter WIDTH = 9
) ( //input declarations
input signed [WIDTH-1:0] A_in,
input signed [WIDTH-1:0] B_in,
//output declarations
output reg signed [WIDTH-1:0] C_out
);
always @(*) begin
if (A_in[WIDTH-1] ^ B_in[WIDTH-1] == 0) begin
C_out[WIDTH-2:0] <= B_in[WIDTH-2:0] + A_in[WIDTH-2:0];
C_out[WIDTH-1] <= A_in[WIDTH-1];
end
if(A_in[WIDTH-1]^B_in[WIDTH-1]==1)
//if({A_in[WIDTH-1]B_in[WIDTH-1]}==01)
begin
C_out[WIDTH-2:0] <= (B_in[WIDTH-2:0]>A_in[WIDTH-2:0])?(B_in[WIDTH-2:0]-A_in[WIDTH-2:0]):(A_in[WIDTH-2:0]-B_in[WIDTH-2:0]);
C_out[WIDTH-1] <= (B_in[WIDTH-2:0] > A_in[WIDTH-2:0]) ? (B_in[WIDTH-1]) : (A_in[WIDTH-1]);
end
end
endmodule
| 7.212241 |
module adder_using_always ();
reg a, b;
reg sum, carry;
always @(a or b) begin
{carry, sum} = a + b;
end
initial begin
$monitor(" A = %b B = %b CARRY = %b SUM = %b", a, b, carry, sum);
#10 a = 0;
b = 0;
#10 a = 1;
#10 b = 1;
#10 a = 0;
#10 b = 0;
#10 $finish;
end
endmodule
| 6.707567 |
module adder_using_assign ();
reg a, b;
wire sum, carry;
assign #5{carry, sum} = a + b;
initial begin
$monitor(" A = %b B = %b CARRY = %b SUM = %b", a, b, carry, sum);
#10 a = 0;
b = 0;
#10 a = 1;
#10 b = 1;
#10 a = 0;
#10 b = 0;
#10 $finish;
end
endmodule
| 6.707567 |
module adder (
a,
b,
out
);
input [31:0] a, b;
output [31:0] out;
assign out = a + b;
endmodule
| 7.4694 |
module adder_with_bram (
input wire clk,
input wire resetn,
input wire start_add,
input wire clear_done,
output reg bram_en,
output reg [3:0] bram_we,
output reg [14:0] bram_addr,
input wire [31:0] bram_rdata,
output reg [31:0] bram_wdata
);
reg [31:0] adder_ina;
reg [31:0] adder_inb;
reg [31:0] adder_out;
reg [3:0] state;
reg done_add;
always @(posedge clk) begin
if (resetn == 1'b0) begin
state <= 4'b0000;
end else begin
case (state)
4'b0000: begin
bram_en <= 1'b0;
adder_ina <= 32'b0;
adder_inb <= 32'b0;
adder_out <= 32'b0;
done_add <= 1'b0;
bram_wdata <= 32'b0;
bram_addr <= 15'b0;
if (start_add == 1'b1) begin
state <= 4'b0001;
end else begin
state <= 4'b0000;
end
end
4'b0001: begin
bram_en <= 1'b1;
bram_we <= 4'b0000;
bram_addr <= 15'h0;
state <= 4'b1010;
end
4'b1010: begin
//just wait
bram_en <= 1'b1;
state <= 4'b0010;
end
4'b0010: begin
bram_en <= 1'b1;
adder_ina <= bram_rdata;
bram_we <= 4'b0000;
bram_addr <= 15'h4;
state <= 4'b1011;
end
4'b1011: begin
//just wait
bram_en <= 1'b1;
state <= 4'b0011;
end
4'b0011: begin
bram_en <= 1'b1;
adder_inb <= bram_rdata;
state <= 4'b0100;
end
4'b0100: begin
bram_en <= 1'b1;
adder_out <= adder_ina + adder_inb;
state <= 4'b0101;
end
4'b0101: begin
bram_en <= 1'b1;
bram_addr <= 15'h8;
bram_wdata <= adder_out;
bram_we <= 4'b1111;
state <= 4'b1110;
end
4'b1110: begin
//just wait
bram_en <= 1'b1;
state <= 4'b0110;
end
4'b0110: begin
bram_en <= 1'b1;
bram_we <= 4'b0000;
done_add <= 1'b1;
state <= 4'b0111;
end
4'b0111: begin
bram_en <= 1'b0;
if (clear_done == 1'b1) begin
done_add <= 1'b0;
state <= 4'b0000;
end else begin
state <= 4'b0111;
end
end
endcase
end
end
endmodule
| 7.100125 |
module ram (
addr0,
d0,
we0,
q0,
clk
);
input [14:0] addr0;
input [31:0] d0;
input [3:0] we0;
output [31:0] q0;
input clk;
reg [31:0] q0;
reg [ 7:0] ram[(1<<15-1):0];
always @(posedge clk) begin
if (we0[0]) ram[addr0+0] <= d0[7:0];
if (we0[1]) ram[addr0+1] <= d0[15:8];
if (we0[2]) ram[addr0+2] <= d0[23:16];
if (we0[3]) ram[addr0+3] <= d0[31:24];
q0 <= {ram[addr0+3], ram[addr0+2], ram[addr0+1], ram[addr0]};
end
//single_port_ram u_single_port_ram(
// .data(d0),
// .we(we0),
// .addr(addr0),
// .clk(clk),
// .out(q0)
//);
endmodule
| 6.838627 |
module top;
wire [31:0] bram_rdata;
wire [31:0] bram_wdata;
wire [14:0] bram_addr;
wire [3:0] bram_we;
reg start_add;
reg clear_done;
reg clk;
reg resetn;
initial begin
clk = 0;
forever begin
#10 clk = ~clk;
end
end
initial begin
resetn = 0;
#55 resetn = 1;
end
adder_with_bram u_adder_with_bram (
.clk(clk),
.resetn(resetn),
.start_add(start_add),
.clear_done(clear_done),
.bram_en(),
.bram_we(bram_we),
.bram_addr(bram_addr),
.bram_rdata(bram_rdata),
.bram_wdata(bram_wdata)
);
ram u_ram (
.addr0(bram_addr),
.d0(bram_wdata),
.we0(bram_we),
.q0(bram_rdata),
.clk(clk)
);
initial begin
$vcdpluson;
$vcdplusmemon;
end
initial begin
force u_ram.ram[0] = 8'd4;
force u_ram.ram[1] = 8'd4;
force u_ram.ram[2] = 8'd4;
force u_ram.ram[3] = 8'd4;
force u_ram.ram[4] = 8'd3;
force u_ram.ram[5] = 8'd3;
force u_ram.ram[6] = 8'd3;
force u_ram.ram[7] = 8'd3;
start_add = 1'b0;
#105 start_add = 1'b1;
#1000 $finish;
end
endmodule
| 6.919222 |
module adder_8_bit_with_overflow (
input [7:0] a,
input [7:0] b,
output [7:0] sum,
output c_out,
output overflow
);
wire [7:0] temp_sum;
wire [7:0] overflow_extend;
adder_8_bit x1 (
.a(a),
.b(b),
.sum(temp_sum),
.c_out(c_out)
);
overflow_detection x2 (
.a_last_bit(a[7]),
.b_last_bit(b[7]),
.sum_last_bit(temp_sum[7]),
.overflow(overflow)
);
assign overflow_extend = {{7{overflow}}, overflow};
assign sum = ((~overflow_extend) & temp_sum);
endmodule
| 6.773302 |
module performs add, subtract and compare instructions. *
* *
*****************************************************************************/
// synthesis translate_off
`timescale 1ns / 100ps
// synthesis translate_on
/*
Adder_w_Comparator the_Adder_w_Comparator (
// Inputs
.operandA (),
.operandB (),
.sub (),
// Bidirectionals
// Outputs
.result (),
.negative_flag (),
.overflow_flag (),
.zero_flag ()
);
*/
module Adder_w_Comparator (
// Inputs
operandA,
operandB,
sub,
// Bidirectionals
// Outputs
result,
negative_flag,
overflow_flag,
zero_flag
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [32:0] operandA;
input [32:0] operandB;
input sub;
// Bidirectionals
// Outputs
output [31:0] result;
output negative_flag;
output overflow_flag;
output zero_flag;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
wire [32:0] add_sub_result;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign result = add_sub_result[31:0];
assign zero_flag = ((result == 0) ? 1'b1 : 1'b0);
assign negative_flag = add_sub_result[32];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
lpm_add_sub Adder_Subtractor (
.add_sub (~sub),
.dataa (operandA),
.datab (operandB),
.overflow (overflow_flag),
.result (add_sub_result)
// synopsys translate_off
,
.cin (),
.cout (),
.clock (),
.clken (),
.aclr ()
// synopsys translate_on
);
defparam
Adder_Subtractor.lpm_direction = "UNUSED",
Adder_Subtractor.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
Adder_Subtractor.lpm_type = "LPM_ADD_sub",
Adder_Subtractor.lpm_width = 33;
endmodule
| 6.821257 |
module Adder_z (
input [31:0] a_adder,
input [31:0] b_adder,
input reset,
input clock,
output [31:0] FinalSum
);
wire idle_Special, idle_Allign, idle_AddState, idle_NormaliseSum;
wire [31:0] sout_Special, sout_Allign, sout_AddState, sout_NormaliseSum;
wire [35:0] cout_Special, cout_Allign;
wire [35:0] zout_Special, zout_Allign;
wire [7:0] difference_Special;
wire [27:0] sum_AddState, sum_NormaliseSum;
wire [31:0] FinalSum_Idle1, FinalSum_Idle2, FinalSum_Idle3;
SpecialAdd Add1 (
.cin_Special(a_adder),
.zin_Special(b_adder),
.reset(reset),
.clock(clock),
.idle_Special(idle_Special),
.difference_Special(difference_Special),
.cout_Special(cout_Special),
.zout_Special(zout_Special),
.sout_Special(sout_Special)
);
AllignAdder Add2 (
.idle_Special(idle_Special),
.cout_Special(cout_Special),
.zout_Special(zout_Special),
.sout_Special(sout_Special),
.difference_Special(difference_Special),
.clock(clock),
.idle_Allign(idle_Allign),
.cout_Allign(cout_Allign),
.zout_Allign(zout_Allign),
.sout_Allign(sout_Allign)
);
Add Add3 (
.idle_Allign(idle_Allign),
.cout_Allign(cout_Allign),
.zout_Allign(zout_Allign),
.sout_Allign(sout_Allign),
.clock(clock),
.idle_AddState(idle_AddState),
.sout_AddState(sout_AddState),
.sum_AddState(sum_AddState)
);
NormaliseAdder Add4 (
.idle_AddState(idle_AddState),
.sout_AddState(sout_AddState),
.sum_AddState(sum_AddState),
.clock(clock),
.idle_NormaliseSum(idle_NormaliseSum),
.sout_NormaliseSum(sout_NormaliseSum),
.sum_NormaliseSum(sum_NormaliseSum)
);
PackAdder Add5 (
.idle_NormaliseSum(idle_NormaliseSum),
.sout_NormaliseSum(sout_NormaliseSum),
.sum_NormaliseSum(sum_NormaliseSum),
.clock(clock),
.sout_PackSum(FinalSum_Idle1)
);
IdleMult Add6 (
.FinalProduct(FinalSum_Idle1),
.clock(clock),
.FinalProductout(FinalSum_Idle2)
);
IdleMult Add7 (
.FinalProduct(FinalSum_Idle2),
.clock(clock),
.FinalProductout(FinalSum_Idle3)
);
IdleMult Add8 (
.FinalProduct(FinalSum_Idle3),
.clock(clock),
.FinalProductout(FinalSum)
);
endmodule
| 6.553626 |
module addf (
input [31:0] a,
input [31:0] b,
output reg [31:0] data_out
);
always @(*) begin
data_out = a + b;
end
endmodule
| 7.251162 |
module addfxp_18_1 (
input [17:0] a,
input [17:0] b,
input clk,
output [17:0] q
);
reg [17:0] res_0;
assign q = res_0;
always @(posedge clk) begin
res_0 <= a + b;
end
endmodule
| 6.553508 |
module addhsv (
A,
B,
CIN,
COUT,
OVF,
SUM
);
parameter N = 32;
parameter DPFLAG = 1;
parameter GROUP = "dpath1";
parameter BUFFER_SIZE = "DEFAULT";
parameter d_COUT_r = 1, d_COUT_f = 1, d_OVF_r = 1, d_OVF_f = 1, d_SUM = 1;
input [(N - 1):0] A;
input [(N - 1):0] B;
input CIN;
output COUT;
output OVF;
output [(N - 1):0] SUM;
wire COUT_temp;
wire OVF_temp;
wire [(N - 1):0] SUM_temp;
assign #(d_COUT_r, d_COUT_f) COUT = COUT_temp;
assign #(d_OVF_r, d_OVF_f) OVF = OVF_temp;
assign #(d_SUM) SUM = SUM_temp;
adder_generic #(N) inst1 (
A,
B,
CIN,
COUT_temp,
OVF_temp,
SUM_temp
);
endmodule
| 7.255995 |
module adding_five_four_bits (
pb1,
pb2,
pb3,
pb4,
rc,
in,
sum,
carry
);
input pb1;
input pb2;
input pb3;
input pb4;
input rc;
input [3:0] in;
output [5:0] sum;
wire [5:0] sum;
output carry;
wire carry;
reg [3:0] a;
reg [3:0] b;
reg [3:0] c;
reg [3:0] d;
reg [5:0] e;
wire [4:0] x;
wire [4:0] y;
wire [5:0] z;
always @(posedge pb1) begin
a[3:0] <= in;
end
always @(posedge pb2) begin
b[3:0] <= in;
end
always @(posedge pb3) begin
c[3:0] <= in;
end
always @(posedge pb4) begin
d[3:0] <= in;
end
always @(posedge rc) begin
e[3:0] <= in;
e[5:4] <= 2'b00;
end
four_bit_adder FoA1 (
a,
b,
x[3:0],
x[4]
);
four_bit_adder FoA2 (
c,
d,
y[3:0],
y[4]
);
five_bit_adder FiA1 (
x,
y,
z[4:0],
z[5]
);
six_bit_adder SA1 (
z,
e,
sum,
carry
);
endmodule
| 7.154553 |
module: adding_five_four_bits
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module adding_five_four_bits_top;
// Inputs
reg pb1;
reg pb2;
reg pb3;
reg pb4;
reg rc;
reg [3:0] in;
// Outputs
wire [5:0] sum;
wire carry;
// Instantiate the Unit Under Test (UUT)
adding_five_four_bits uut (
.pb1(pb1),
.pb2(pb2),
.pb3(pb3),
.pb4(pb4),
.rc(rc),
.in(in),
.sum(sum),
.carry(carry)
);
initial begin
pb1=1; pb2=0; pb3=0; pb4=0; rc=0; in=4'b1011;
#5
pb1=0; pb2=1; pb3=0; pb4=0; rc=0; in=4'b1100;
#5
pb1=0; pb2=0; pb3=1; pb4=0; rc=0; in=4'b1101;
#5
pb1=0; pb2=0; pb3=0; pb4=1; rc=0; in=4'b1110;
#5
pb1=0; pb2=0; pb3=0; pb4=0; rc=1; in=4'b1111;
#5
$finish;
end
endmodule
| 7.376805 |
module Addition_Subtraction (
input [31:0] a_operand,
b_operand, //Inputs in the format of IEEE-754 Representation.
input AddBar_Sub, //If Add_Sub is low then Addition else Subtraction.
output Exception,
output [31:0] result //Outputs in the format of IEEE-754 Representation.
);
wire operation_sub_addBar;
wire Comp_enable;
wire output_sign;
wire [31:0] operand_a, operand_b;
wire [23:0] significand_a, significand_b;
wire [ 7:0] exponent_diff;
wire [23:0] significand_b_add_sub;
wire [ 7:0] exponent_b_add_sub;
wire [24:0] significand_add;
wire [30:0] add_sum;
wire [23:0] significand_sub_complement;
wire [24:0] significand_sub;
wire [30:0] sub_diff;
wire [24:0] subtraction_diff;
wire [ 7:0] exponent_sub;
//for operations always operand_a must not be less than b_operand
assign {Comp_enable,operand_a,operand_b} = (a_operand[30:0] < b_operand[30:0]) ? {1'b1,b_operand,a_operand} : {1'b0,a_operand,b_operand};
assign exp_a = operand_a[30:23];
assign exp_b = operand_b[30:23];
//Exception flag sets 1 if either one of the exponent is 255.
assign Exception = (&operand_a[30:23]) | (&operand_b[30:23]);
assign output_sign = AddBar_Sub ? Comp_enable ? !operand_a[31] : operand_a[31] : operand_a[31];
assign operation_sub_addBar = AddBar_Sub ? operand_a[31] ^ operand_b[31] : ~(operand_a[31] ^ operand_b[31]);
//Assigining significand values according to Hidden Bit.
//If exponent is equal to zero then hidden bit will be 0 for that respective significand else it will be 1
assign significand_a = (|operand_a[30:23]) ? {1'b1, operand_a[22:0]} : {1'b0, operand_a[22:0]};
assign significand_b = (|operand_b[30:23]) ? {1'b1, operand_b[22:0]} : {1'b0, operand_b[22:0]};
//Evaluating Exponent Difference
assign exponent_diff = operand_a[30:23] - operand_b[30:23];
//Shifting significand_b according to exponent_diff
assign significand_b_add_sub = significand_b >> exponent_diff;
assign exponent_b_add_sub = operand_b[30:23] + exponent_diff;
//Checking exponents are same or not
assign perform = (operand_a[30:23] == exponent_b_add_sub);
///////////////////////////////////////////////////////////////////////////////////////////////////////
//------------------------------------------------ADD BLOCK------------------------------------------//
assign significand_add = (perform & operation_sub_addBar) ? (significand_a + significand_b_add_sub) : 25'd0;
//Result will be equal to Most 23 bits if carry generates else it will be Least 22 bits.
assign add_sum[22:0] = significand_add[24] ? significand_add[23:1] : significand_add[22:0];
//If carry generates in sum value then exponent must be added with 1 else feed as it is.
assign add_sum[30:23] = significand_add[24] ? (1'b1 + operand_a[30:23]) : operand_a[30:23];
///////////////////////////////////////////////////////////////////////////////////////////////////////
//------------------------------------------------SUB BLOCK------------------------------------------//
assign significand_sub_complement = (perform & !operation_sub_addBar) ? ~(significand_b_add_sub) + 24'd1 : 24'd0 ;
assign significand_sub = perform ? (significand_a + significand_sub_complement) : 25'd0;
priority_encoder pe (
significand_sub,
operand_a[30:23],
subtraction_diff,
exponent_sub
);
assign sub_diff[30:23] = exponent_sub;
assign sub_diff[22:0] = subtraction_diff[22:0];
///////////////////////////////////////////////////////////////////////////////////////////////////////
//-------------------------------------------------OUTPUT--------------------------------------------//
//If there is no exception and operation will evaluate
assign result = Exception ? 32'b0 : ((!operation_sub_addBar) ? {output_sign,sub_diff} : {output_sign,add_sum});
endmodule
| 7.743167 |
module addition (
a,
b,
c
);
// bit depth
localparam BIT_DEPTH = 16;
input wire [BIT_DEPTH-1:0] a, b;
output wire [BIT_DEPTH:0] c;
pos_add #(BIT_DEPTH, BIT_DEPTH) ADD (
a,
b,
c
);
endmodule
| 7.93101 |
module Addition_tb;
reg clk = 0;
reg [31:0] a_operand;
reg [31:0] b_operand;
wire [31:0] result;
reg AddBar_Sub;
reg [31:0] Expected_result;
reg [95:0] testVector [`N_TESTS-1:0];
reg test_stop_enable;
integer mcd;
integer test_n = 0;
integer pass = 0;
integer error = 0;
Addition_Subtraction DUT(a_operand,b_operand,AddBar_Sub,Exception,result);
always #5 clk = ~clk;
initial
AddBar_Sub = 1'b0;
begin
$readmemh("TestVectorAddition", testVector);
mcd = $fopen("ResultsAdd.txt");
end
always @(posedge clk)
begin
{a_operand,b_operand,Expected_result} = testVector[test_n];
test_n = test_n + 1'b1;
#2;
if (result[31:11] == Expected_result[31:11])
begin
//$display ("TestPassed Test Number -> %d",test_n);
pass = pass + 1'b1;
end
if (result[31:11] != Expected_result[31:11])
begin
$fdisplay (mcd,"Test Failed Expected Result = %h, Obtained result = %h, Test Number -> %d",Expected_result,result,test_n);
error = error + 1'b1;
end
if (test_n >= `N_TESTS)
begin
$fdisplay(mcd,"Completed %d tests, %d passed and %d fails.", test_n, pass, error);
test_stop_enable = 1'b1;
end
end
always @(posedge test_stop_enable)
begin
$fclose(mcd);
$finish;
end
endmodule
| 8.472785 |
module addition_fp (
Sum,
InA,
InB,
valid_in,
valid_out
);
input [31:0] InA, InB;
input valid_in;
output [31:0] Sum;
output reg valid_out;
reg [7:0] Exponent, Exponent_A, Exponent_B, Exponent_A_Out, Exponent_B_Out;
reg Sign_A, Sign_B, Sign, S, Temp;
reg [23:0] Fraction_A, Fraction_B, Fraction, Fraction_A_Out, Fraction_B_Out;
reg [24:0] Result_Fraction, Fraction_Temp;
reg [7:0] Ex_Difference;
always @(InA or InB or valid_in) begin
if (valid_in) begin
//initial
Sign_A = InA[31];
Sign_B = InB[31];
Exponent_A = InA[30:23];
Exponent_B = InB[30:23];
Fraction_A = {1'b1, InA[22:0]};
Fraction_B = {1'b1, InB[22:0]};
//compare Exponent
if (Exponent_A == Exponent_B) begin
Exponent_A_Out = Exponent_A + 8'd1;
Exponent_B_Out = Exponent_B + 8'd1;
Fraction_A_Out = Fraction_A;
Fraction_B_Out = Fraction_B;
S = 1'b1;
end else if (Exponent_A > Exponent_B) begin
Ex_Difference = Exponent_A - Exponent_B;
Exponent_A_Out = Exponent_A + 8'd1;
Exponent_B_Out = Exponent_A + 8'd1;
Fraction_A_Out = Fraction_A;
Fraction_B_Out = Fraction_B >> Ex_Difference;
S = 1'b1;
end else begin
Ex_Difference = Exponent_B - Exponent_A;
Exponent_A_Out = Exponent_B + 8'd1;
Exponent_B_Out = Exponent_B + 8'd1;
Fraction_A_Out = Fraction_B;
Fraction_B_Out = Fraction_A >> Ex_Difference;
S = 1'b0;
end
//Sub Add
if (Sign_A ^ Sign_B) Result_Fraction = Fraction_A_Out - Fraction_B_Out;
else Result_Fraction = Fraction_A_Out + Fraction_B_Out;
//normalize
Temp = Sign_A ^ Sign_B;
Sign = S ? (Sign_A ^ (Result_Fraction[24] & Temp)) : (Sign_B ^ (Result_Fraction[24] & Temp));
Fraction_Temp = (Result_Fraction[24] & Temp) ? (~Result_Fraction + 25'd1) : Result_Fraction;
Fraction = Fraction_Temp[24:1];
Exponent = Exponent_A_Out;
repeat (24) begin
if (Fraction[23] == 1'b0) begin
Fraction = Fraction << 1'b1;
Exponent = Exponent - 8'd1;
end
end
valid_out <= 1'b1;
end else valid_out <= 1'b0;
end
assign Sum = (valid_out) ? ((InA == 32'd0 && InB == 32'd0 || InA == 32'h80000000 && InB == 32'd0 ||InB == 32'h80000000 && InA == 32'd80000000 ||InB == 32'h80000000 && InA == 32'd0 ) ? 32'd0 :{Sign, Exponent, Fraction[22:0]}) : 32'dZ;
endmodule
| 7.277446 |
module addition_s (
signa,
signb,
mantissa_11,
mantissa_21,
mantissa_sum
);
input signa, signb;
input [9:0] mantissa_11, mantissa_21;
output [10:0] mantissa_sum;
wire [9:0] Mantissa_11, Mantissa_21;
assign Mantissa_11 = (signa ? (-mantissa_11) : mantissa_11);
assign Mantissa_21 = (signb ? (-mantissa_21) : mantissa_21);
assign mantissa_sum = Mantissa_11+Mantissa_21; // can instantiate full adder here instead of + operation
endmodule
| 7.246511 |
module Addition_Subtraction (
input [31:0] a,
b,
input add_sub_signal, // If 1 then addition otherwise subtraction
output exception,
output [31:0] res
);
wire operation_add_sub_signal;
wire enable;
wire output_sign;
wire [31:0] op_a, op_b;
wire [23:0] significand_a, significand_b;
wire [ 7:0] exp_diff;
wire [23:0] significand_b_add_sub;
wire [ 7:0] exp_b_add_sub;
wire [24:0] significand_add;
wire [30:0] add_sum;
wire [23:0] significand_sub_complement;
wire [24:0] significand_sub;
wire [30:0] sub_diff;
wire [24:0] subtraction_diff;
wire [ 7:0] exp_sub;
assign {enable,op_a,op_b} = (a[30:0] < b[30:0]) ? {1'b1,b,a} : {1'b0,a,b}; // For operations always op_a must not be less than b
assign exp_a = op_a[30:23];
assign exp_b = op_b[30:23];
assign exception = (&op_a[30:23]) | (&op_b[30:23]); // Exception flag sets 1 if either one of the exponent is 255.
assign output_sign = add_sub_signal ? enable ? !op_a[31] : op_a[31] : op_a[31];
assign operation_add_sub_signal = add_sub_signal ? op_a[31] ^ op_b[31] : ~(op_a[31] ^ op_b[31]);
// Assign significand values according to Hidden Bit.
assign significand_a = (|op_a[30:23]) ? {1'b1,op_a[22:0]} : {1'b0,op_a[22:0]}; // If exponent is zero,hidden bit = 0,else 1
assign significand_b = (|op_b[30:23]) ? {1'b1, op_b[22:0]} : {1'b0, op_b[22:0]};
assign exp_diff = op_a[30:23] - op_b[30:23]; // Exponent difference calculation
assign significand_b_add_sub = significand_b >> exp_diff;
assign exp_b_add_sub = op_b[30:23] + exp_diff;
assign perform = (op_a[30:23] == exp_b_add_sub); // Checking if exponents are same
// Add Block //
assign significand_add = (perform & operation_add_sub_signal) ? (significand_a + significand_b_add_sub) : 25'd0;
assign add_sum[22:0] = significand_add[24] ? significand_add[23:1] : significand_add[22:0]; // res will be most 23 bits if carry generated, else least 22 bits.
assign add_sum[30:23] = significand_add[24] ? (1'b1 + op_a[30:23]) : op_a[30:23]; // If carry generates in sum value then exponent is added with 1 else feed as it is.
// Sub Block //
assign significand_sub_complement = (perform & !operation_add_sub_signal) ? ~(significand_b_add_sub) + 24'd1 : 24'd0 ;
assign significand_sub = perform ? (significand_a + significand_sub_complement) : 25'd0;
priority_encoder pe (
significand_sub,
op_a[30:23],
subtraction_diff,
exp_sub
);
assign sub_diff[30:23] = exp_sub;
assign sub_diff[22:0] = subtraction_diff[22:0];
// Output //
assign res = exception ? 32'b0 : ((!operation_add_sub_signal) ? {output_sign,sub_diff} : {output_sign,add_sum});
endmodule
| 7.743167 |
module Addition_Subtraction_tb;
reg [31:0] a, b;
reg clk = 1'b0, reset = 1'b1;
reg add_sub_signal;
wire [31:0] res;
wire exception;
Addition_Subtraction dut (
a,
b,
add_sub_signal,
exception,
res
);
always #5 clk = ~clk;
initial begin
add_sub_signal = 1'b0;
iteration(32'h4201_51EC, 32'h4242_147B, 32'h42A1_B333, `__LINE__); //32.33 + 48.52 = 80.85
iteration(32'h4068_51EC, 32'h4090_A3D7, 32'h4102_6666, `__LINE__); //3.63 + 4.52 = 8.15.
iteration(32'h4195_0A3D, 32'h419B_47AE, 32'h4218_28F6, `__LINE__); //18.63 + 19.41 = 38.04.
iteration(32'h4217_999A, 32'h3F8C_CCCD, 32'h421C_0000, `__LINE__); //37.9 + 1.1 = 39.
iteration(32'h4383_C7AE, 32'h4164_F5C3, 32'h438A_EF5C, `__LINE__); //263.56 + 14.31 = 277.87
iteration(32'h4542_77D7, 32'h453B_8FD7, 32'h45BF_03D7,
`__LINE__); //3111.49 + 3000.99 = 6112.48
iteration(32'h3F3A_E148, 32'h3EB33333, 32'h3F8A_3D71, `__LINE__); //0.73 + 0.35 = 1.08.
iteration(32'h3F7D_70A4, 32'h3F7D_70A4, 32'h3FFD_70A4, `__LINE__); //0.99 + 0.99 = 1.98
iteration(32'h3F40_0000, 32'h3E94_7AE1, 32'h3F85_1EB8, `__LINE__); //0.75 + 0.29 = 1.04
iteration(32'h4B7F_FFFF, 32'h3F80_0000, 32'h4B80_0000, `__LINE__); //16777215 + 1 = 16777216
// Corner Case
iteration(32'h4B7F_FFFF, 32'h4000_0000, 32'h4B80_0001, `__LINE__); //16777215 + 2 = 16777217.
// Corner Case
iteration(32'h4B7F_FFFF, 32'h4B7F_FFFF, 32'h4BFF_FFFF,
`__LINE__); //16777215 + 16777215 = 33554430
// Working
iteration(32'h4B7F_FFFE, 32'h3F80_0000, 32'h4B7F_FFFF, `__LINE__); //16777214 + 1 = 16777215
iteration(32'hBF3A_E148, 32'h3EC7_AE14, 32'hBEAE_147B, `__LINE__); //-0.73 + 0.39 = -0.34
iteration(32'hC207_C28F, 32'h4243_B852, 32'h416F_D70A, `__LINE__); //-33.94 + 48.93 = 14.99
iteration(32'hBDB2_2D0E, 32'h4305_970A, 32'h4305_80C5, `__LINE__); //-0.087 + 133.59 = 133.503
iteration(32'h4E6B_79A3, 32'hCCEB_79A3, 32'h4E4E_0A6F,
`__LINE__); //987654321 - 123456789 = 864197532
iteration(32'h4B80_0000, 32'hCB80_0000, 32'h0000_0000, `__LINE__); //16777216 - 16777216 = 0
iteration(32'h4B7F_FFFF, 32'hCB7F_FFFF, 32'h0000_0000, `__LINE__); //16777215 - 16777215 = 0
// Subtraction //
add_sub_signal = 1'b1;
iteration(32'h40A00000, 32'h40C00000, 32'hBF800000, `__LINE__); //5 - 6 = -1
iteration(32'h40C00000, 32'h40A00000, 32'h3F800000, `__LINE__); //6 - 5 = 1
iteration(32'hC0C00000, 32'hC0A00000, 32'hBF800000, `__LINE__); //-6 - (-5) = -1
iteration(32'hC0A00000, 32'hC0C00000, 32'h3F800000, `__LINE__); // -5 - (-6) = 1
iteration(32'h40C00000, 32'hC0A00000, 32'h41300000, `__LINE__); // 6 - (-5) = 11
iteration(32'h40A00000, 32'hC0C00000, 32'h41300000, `__LINE__); // 5 - (-6) = 11
iteration(32'hC0A00000, 32'h40C00000, 32'hC1300000, `__LINE__); // -5 - (6) = -11
iteration(32'hC0C00000, 32'h40A00000, 32'hC1300000, `__LINE__); // -6 - (+5) = -11
// Exception Cases //
iteration(32'h0000_0000, 32'h3EC7_AE14, 32'h3EC7_AE14, `__LINE__);
iteration(32'h3EC7_AE14, 32'h0000_0000, 32'h3EC7_AE14, `__LINE__);
iteration(32'h0000_0000, 32'h0000_0000, 32'h0000_0000, `__LINE__);
iteration(32'h7F80_0000, 32'h7F90_0100, 32'h0000_0000, `__LINE__);
iteration(32'h7F80_0000, 32'h3EC7_AE14, 32'h0000_0000, `__LINE__);
iteration(32'h3EC7_AE14, 32'h7F80_0000, 32'h0000_0000, `__LINE__);
iteration(32'h7F80_0000, 32'h0000_0000, 32'h0000_0000, `__LINE__);
iteration(32'h7F90_0100, 32'h7F80_0000, 32'h0000_0000, `__LINE__);
@(negedge clk) $stop;
end
task iteration(input [31:0] op_a, op_b, expected_value, input integer line_num);
begin
@(negedge clk) begin
a = op_a;
b = op_b;
end
@(posedge clk) begin
#1;
if (expected_value == res) $display("Success: Line Number -> %d", line_num);
else
$display(
"Failed: \t\n A => %h, \t\n B => %h, \t\n Result Obtained => %h, \t\n Expected Value => %h - Line Number",
op_a,
op_b,
res,
expected_value,
line_num
);
end
end
endtask
endmodule
| 7.743167 |
module Addition_tb;
reg clk = 0;
reg [31:0] a_operand;
reg [31:0] b_operand;
reg AddBar_Sub = 1'b1;
wire [31:0] result;
reg [31:0] Expected_result;
reg [95:0] testVector[`N_TESTS-1:0];
reg test_stop_enable;
integer mcd;
integer test_n = 0;
integer pass = 0;
integer error = 0;
Addition_Subtraction DUT (
a_operand,
b_operand,
AddBar_Sub
,,
result
);
always #5 clk = ~clk;
initial begin
$readmemh("TestVectorSubtraction", testVector);
mcd = $fopen("ResultsSub.txt");
end
always @(posedge clk) begin
{a_operand, b_operand, Expected_result} = testVector[test_n];
test_n = test_n + 1'b1;
#2;
if (result[31:11] == Expected_result[31:11]) begin
//$display ("TestPassed Test Number -> %d",test_n);
pass = pass + 1'b1;
end
if (result[31:11] != Expected_result[31:11]) begin
$fdisplay(mcd, "Test Failed Expected Result = %h, Obtained result = %h, Test Number -> %d",
Expected_result, result, test_n);
error = error + 1'b1;
end
if (test_n >= `N_TESTS) begin
$fdisplay(mcd, "Completed %d tests, %d passes and %d fails.", test_n, pass, error);
test_stop_enable = 1'b1;
end
end
always @(posedge test_stop_enable) begin
$fclose(mcd);
$finish;
end
endmodule
| 8.472785 |
module addi_control_ID_EX_stage (
input signal_addi,
input clock,
output reg out_addi_control_reg
);
always @(posedge clock) out_addi_control_reg = signal_addi;
endmodule
| 6.882231 |
module AddLeftShift32 (
AddIn,
ALSHIn,
Out
);
input [31:0] AddIn, ALSHIn;
output reg [31:0] Out;
always @(AddIn, ALSHIn) begin
Out <= (ALSHIn << 2) + AddIn;
end
endmodule
| 7.730163 |
module addma (
input wire clk,
input wire [24:0] outdat,
output wire rden,
input wire empty,
output reg [22:0] memaddr,
input wire [31:0] memrdata,
output wire [31:0] memwdata,
output wire [1:0] memlen,
output reg memreq,
output wire memwr,
input wire memready,
input wire memack
);
reg [31:0] dat[0:3];
reg [1:0] ctr;
reg [2:0] state;
localparam FILL = 0;
localparam REQ = 1;
localparam DAT = 2;
assign memwdata = dat[ctr];
assign rden = state == FILL && !empty && (ctr == 0 || !outdat[24]);
assign memwr = 1;
assign memlen = 3;
always @(posedge clk)
case (state)
FILL:
if (!empty) begin
dat[ctr] <= {8'h0, outdat[23:0]};
if (outdat[24]) memaddr <= 0;
ctr <= ctr + 1;
if (ctr == 3) begin
memreq <= 1;
state <= REQ;
end
end
REQ:
if (memready) begin
memreq <= 0;
memaddr <= memaddr + 4;
state <= DAT;
end
DAT:
if (memack) begin
ctr <= ctr + 1;
if (ctr == 3) state <= FILL;
end
endcase
endmodule
| 6.865839 |
module addNbits #(
parameter N = 32
) (
input wire [N:0] x,
input wire [N:0] y,
input cin,
output wire [N:0] z,
output wire cout
);
wire [N+1:0] temp;
assign temp = {1'b0, x} + {1'b0, y} + cin;
assign z = temp[N:0];
assign cout = temp[N+1];
endmodule
| 7.928611 |
module addNbits_tb ();
localparam N = 32;
reg [N:0] x;
reg [N:0] y;
reg cin;
wire [N:0] z;
wire cout;
addNbits circuit1 (
.x(x),
.y(y),
.cin(cin),
.z(z),
.cout(cout)
);
initial begin
$dumpfile("test.vcd");
$dumpvars(0, addNbits_tb);
x = 'd2;
y = 'd2;
cin = 1'd0;
#20;
x = 'd255;
y = 'd255;
cin = 1'd0;
#20;
$stop;
end
initial begin
$monitor("x = %b y = %b cin = %b cout = %b z = %b", x, y, cin, cout, z);
end
endmodule
| 6.881315 |
module AddNot (
input [7:0] a,
input [7:0] b,
output [8:0] o
);
wire [7:0] _GEN_0 = ~b;
assign o = a + _GEN_0;
endmodule
| 7.3741 |
module AddNot (
input [7:0] a,
input [7:0] b,
output [8:0] o
);
wire [7:0] _GEN_0 = ~b;
assign o = a + _GEN_0;
endmodule
| 7.3741 |
module AddOperation (
input [11:0] lhs,
input [11:0] rhs,
output [11:0] result,
output overflow
);
assign {overflow, result} = lhs + rhs;
endmodule
| 7.010186 |
module addPC (
input wire [`digitsBus] f_pc,
input wire need_regids,
input wire need_valc,
output reg [`digitsBus] valPC
);
always @(*) begin
if (need_regids == 1 && need_valc == 1) begin
valPC = f_pc + 10;
end else if (need_valc == 1) begin
valPC = f_pc + 9;
end else if (need_regids == 1) begin
valPC = f_pc + 2;
end else begin
valPC = f_pc + 1;
end
end
endmodule
| 6.538683 |
module AddPC1 (
input [31:0] PC,
output [31:0] PC4
);
assign PC4 = PC + 4;
endmodule
| 7.643128 |
module AddPC2 (
input [31:0] PC4,
input [31:0] Extend_Out,
output [31:0] NewPC
);
assign NewPC = PC4 + (Extend_Out << 2);
endmodule
| 8.243585 |
module AddPP_ForL (
input Clk,
input Rst,
input [1:0] MulHoldFlagFromEx,
input [`DataWidth_CSA30 - 1 : 0] SumPP_CSA30,
input [`DataWidth_CSA31 - 1 : 0] SumPP_CSA31,
input [`DataWidth_CSA30 - 1 : 0] CarryPP_CSA30,
input [`DataWidth_CSA31 - 1 : 0] CarryPP_CSA31,
input Mulitiplier_63,
output [(`DataWidth * 2) - 1 : 0] Sum,
output reg MulHoldEndToEx
);
reg [`DataWidth_CSA40 - 1 : 0] SumPP_CSA40Inside;
reg [`DataWidth_CSA40 - 1 : 0] CarryPP_CSA40Inside;
reg Mulitiplier_63Inside;
reg [1:0] MulHoldFlagFromExInside;
// Forth Level
// CSA40 width = data_width
wire [`DataWidth_CSA40 - 1 : 0] SumPP_CSA40;
wire [`DataWidth_CSA40 - 1 : 0] CarryPP_CSA40;
CasAdder4_2 #(
.DataWidth(`DataWidth_CSA40)
) CSA_40 (
{32'h0000_0000, SumPP_CSA30},
{SumPP_CSA31, 30'h0000_0000},
{32'h0000_0000, CarryPP_CSA30},
{CarryPP_CSA31, 30'h0000_0000},
SumPP_CSA40,
CarryPP_CSA40
);
AddPP_FivL u_AddPP_FivL (
Clk,
Rst,
MulHoldFlagFromExInside,
SumPP_CSA40Inside,
CarryPP_CSA40Inside,
Mulitiplier_63Inside,
Sum,
MulHoldEndToEx
);
Reg #(2, 2'b0) Reg_MulHoldFlagFromExInside (
Clk,
Rst,
MulHoldFlagFromEx,
MulHoldFlagFromExInside,
1'b1
);
always @(posedge Clk) begin
if (!Rst) begin
SumPP_CSA40Inside <= `DataWidth_CSA40'h0;
CarryPP_CSA40Inside <= `DataWidth_CSA40'h0;
end else begin
SumPP_CSA40Inside <= SumPP_CSA40;
CarryPP_CSA40Inside <= CarryPP_CSA40;
end
end
Reg #(1, 1'b0) Reg_Mulitiplier_63Inside (
Clk,
Rst,
Mulitiplier_63,
Mulitiplier_63Inside,
1'b1
);
endmodule
| 6.576087 |
module AddProcess (
input [31:0] z_postAllign,
input [3:0] Opcode_Allign,
input idle_Allign,
input [35:0] cout_Allign,
input [35:0] zout_Allign,
input [31:0] sout_Allign,
input [7:0] InsTagAllign,
input clock,
output reg idle_AddState,
output reg [31:0] sout_AddState,
output reg [27:0] sum_AddState,
output reg [3:0] Opcode_AddState,
output reg [31:0] z_postAddState,
output reg [7:0] InsTagAdder
);
parameter no_idle = 1'b0, put_idle = 1'b1;
wire z_sign;
wire [7:0] z_exponent;
wire [26:0] z_mantissa;
wire c_sign;
wire [7:0] c_exponent;
wire [26:0] c_mantissa;
assign z_sign = zout_Allign[35];
assign z_exponent = zout_Allign[34:27] - 127;
assign z_mantissa = {zout_Allign[26:0]};
assign c_sign = cout_Allign[35];
assign c_exponent = cout_Allign[34:27] - 127;
assign c_mantissa = {cout_Allign[26:0]};
parameter sin_cos = 4'd0,
sinh_cosh = 4'd1,
arctan = 4'd2,
arctanh = 4'd3,
exp = 4'd4,
sqr_root = 4'd5, // Pre processed input is given 4'd11
// This requires pre processing. x = (a+1)/2 and y = (a-1)/2
division = 4'd6, tan = 4'd7, // This is iterative. sin_cos followed by division.
tanh = 4'd8, // This is iterative. sinh_cosh followed by division.
nat_log = 4'd9, // This requires pre processing. x = (a+1) and y = (a-1)
hypotenuse = 4'd10, PreProcess = 4'd11;
always @(posedge clock) begin
InsTagAdder <= InsTagAllign;
z_postAddState <= z_postAllign;
Opcode_AddState <= Opcode_Allign;
//if(Opcode_Allign == PreProcess) begin
idle_AddState <= idle_Allign;
if (idle_Allign != put_idle) begin
sout_AddState[30:23] <= c_exponent;
sout_AddState[22:0] <= 0;
if (c_sign == z_sign) begin
sum_AddState <= c_mantissa + z_mantissa;
sout_AddState[31] <= c_sign;
end else begin
if (c_mantissa >= z_mantissa) begin
sum_AddState <= c_mantissa - z_mantissa;
sout_AddState[31] <= c_sign;
end else begin
sum_AddState <= z_mantissa - c_mantissa;
sout_AddState[31] <= z_sign;
end
end
end else begin
sout_AddState <= sout_Allign;
sum_AddState <= 0;
end
//end
end
endmodule
| 6.818314 |
module ADDR1MUX (
input ADDR1MUX,
input [15:0] ADDR1FromPC,
input [15:0] ADDR1FromRF,
output reg [15:0] ADDR1
);
initial ADDR1 = 0;
always @(*) begin
if (ADDR1MUX) ADDR1 = ADDR1FromRF;
else ADDR1 = ADDR1FromPC;
end
endmodule
| 7.595127 |
module addr2 (
clk,
rst,
d0_i,
d1_i,
d_o
);
parameter IN_WIDTH = 32;
input clk;
input rst;
input wire [IN_WIDTH-1:0] d0_i;
input wire [IN_WIDTH-1:0] d1_i;
output reg [IN_WIDTH:0] d_o;
always @(posedge clk) begin
if (rst) d_o <= 0;
else d_o <= {{1{d0_i[IN_WIDTH-1]}}, d0_i} + {{1{d1_i[IN_WIDTH-1]}}, d1_i};
end
endmodule
| 7.539759 |
module ADDR2MUX (
input [1:0] ADDR2MUX,
input [15:0] offset6,
input [15:0] offset9,
input [15:0] offset11,
output reg [15:0] ADDR2
);
always @(*) begin
case (ADDR2MUX)
2'b00: ADDR2 = 0;
2'b01: ADDR2 = offset6;
2'b10: ADDR2 = offset9;
2'b11: ADDR2 = offset11;
default: ADDR2 = 0;
endcase
end
endmodule
| 7.664226 |
module addr3 (
clk,
rst,
d0_i,
d1_i,
d2_i,
d_o
);
parameter IN_WIDTH = 32;
input clk;
input rst;
input wire [IN_WIDTH-1:0] d0_i;
input wire [IN_WIDTH-1:0] d1_i;
input wire [IN_WIDTH-1:0] d2_i;
output reg [IN_WIDTH:0] d_o;
always @(posedge clk) begin
if (rst) d_o <= 0;
else
d_o <= {{1{d0_i[IN_WIDTH-1]}}, d0_i} + {{1{d1_i[IN_WIDTH-1]}}, d1_i} + {{1{d2_i[IN_WIDTH-1]}}, d2_i};
end
endmodule
| 7.407225 |
module AddrAdder (
input [15:0] A,
input [15:0] B,
output [15:0] out
);
assign out = A + B;
endmodule
| 8.212727 |
module AddrAnalyzer (
din,
NowDevice
);
input [31:0] din;
output NowDevice;
assign NowDevice = (din >= 'h0000_0000 && din <= 'h0000_2FFF) ? `NOWDEVICE_MEMO :
(din >= 'h0000_7F00 && din <= 'h0000_7FE0) ? `NOWDEVICE_IO :
'b0;
endmodule
| 6.680031 |
module exports the common arithmetic path to compute the memory address
//
// Implementation notes:
//
// The address to be computated goes as follows:
// addr = offset + row_idx * col_dim + col_idx
// =============================================================================
`include "pe.vh"
module AddrComp (
input wire [`WMemAddrBus] offset, // memory offset
input wire [`PeActNoBus] row_idx, // row index
input wire [`PeAddrBus] col_dim, // column dimension
input wire [`PeAddrBus] col_idx, // column index
output wire [`WMemAddrBus] addr // calculated address
);
assign addr = offset + row_idx * col_dim + col_idx;
endmodule
| 8.820374 |
module addrConv (
input [8:0] addrIN,
input sign,
output [8:0] addrOUT
);
reg [8:0] addrOUT;
always @(*) begin
if (sign == 0) addrOUT = addrIN;
else addrOUT = ~addrIN + 1;
end
endmodule
| 7.346157 |
module AddrDec (
input [12:0] ADDRESS,
output reg ROM_EN,
output reg RAM_EN
);
always @(ADDRESS)
casex (ADDRESS)
13'b0_xxxx_xxxx_xxxx: {RAM_EN, ROM_EN} <= 2'b01;
13'b1_xxxx_xxxx_xxxx: {RAM_EN, ROM_EN} <= 2'b10;
default: {RAM_EN, ROM_EN} <= 2'b00;
endcase
endmodule
| 7.17026 |
module ADDRDecoding (
input [31:0] addr,
output cs // 0 = memoria interna, 1 = memoria externa
);
// Memoria interna de 1kB (400h B), começando em 2 * 500h = A00h
// => 0A00h:0A00h+03FF
// => 0A00h:0DFF
// =>
// | 11:8 | CS | intern_addr 9:8
// ...
// 9 | 1001 | 1 | xxx
// A | 1010 | 0 | 00
// B | 1011 | 0 | 01
// C | 1100 | 0 | 10
// D | 1101 | 0 | 11
// E | 1110 | 1 | xxx
// ...
// =>
// \9,8
// 11,10 \ 00 01 11 10
// 00 | 1 1 1 1
// 01 | 1 1 1 1
// 11 | 0 0 1 1
// 10 | 1 1 0 0
// =>
// CS = ~((b[31:12]==0).(b11.b10.~b9 | b11.~b10.b9))
// => CS = ~((b[31:12]==0).b11.(b10.~b9 | ~b10.b9))
// => CS = ~((b[31:12]==0).b11.(b10 xor b9))
//
// intern_addr = { ~b9, b[8:0] } <- coloquei direto na porta do DataMemory
assign cs = ~((addr[31:12] == 0) && addr[11] && (addr[10] ^ addr[9]));
endmodule
| 7.002875 |
module addRecF32_add (
input [(`floatControlWidth - 1):0] control,
input [32:0] a,
input [32:0] b,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags
);
addRecFN #(8, 24) addRecFN (
control,
1'b0,
a,
b,
roundingMode,
out,
exceptionFlags
);
endmodule
| 6.799924 |
module addRecF64_add (
input [(`floatControlWidth - 1):0] control,
input [64:0] a,
input [64:0] b,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags
);
addRecFN #(11, 53) addRecFN (
control,
1'b0,
a,
b,
roundingMode,
out,
exceptionFlags
);
endmodule
| 6.609708 |
module addRecF32_sub (
input [(`floatControlWidth - 1):0] control,
input [32:0] a,
input [32:0] b,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags
);
addRecFN #(8, 24) addRecFN (
control,
1'b1,
a,
b,
roundingMode,
out,
exceptionFlags
);
endmodule
| 6.804548 |
module addRecF64_sub (
input [(`floatControlWidth - 1):0] control,
input [64:0] a,
input [64:0] b,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags
);
addRecFN #(11, 53) addRecFN (
control,
1'b1,
a,
b,
roundingMode,
out,
exceptionFlags
);
endmodule
| 6.71431 |
module AddRemoveArea (
Selector,
Increment,
RoomDigit1,
RoomDigit0
);
//inputs
input [7:0] Selector;
input wire Increment;
//outputs
output reg [3:0] RoomDigit1, RoomDigit0;
always @(posedge Increment) begin
if (Selector == 21) begin
if (RoomDigit0 == 4'b0000) begin //if 9 seconds na, i zero niya then i increment si tens
RoomDigit0 <= 9;
if(RoomDigit1 == 4'b0000) //if 99 seconds na, i zero niya si tens then i increment si minutes
RoomDigit1 <= 9;
else RoomDigit1 <= RoomDigit1 - 1;
end else RoomDigit0 <= RoomDigit0 - 1;
end
if (Selector == 5) begin
if (RoomDigit0 == 4'b1001) begin //if 9 seconds na, i zero niya then i increment si tens
RoomDigit0 <= 0;
if(RoomDigit1 == 4'b1001) //if 99 seconds na, i zero niya si tens then i increment si minutes
RoomDigit1 <= 0;
else RoomDigit1 <= RoomDigit1 + 1;
end else RoomDigit0 <= RoomDigit0 + 1;
end
end
endmodule
| 7.353477 |
module AddRemovePerson (
Selector,
Increment,
RoomDigit1,
RoomDigit0
);
//inputs
input [7:0] Selector;
input wire Increment;
//outputs
output reg [3:0] RoomDigit1, RoomDigit0;
always @(posedge Increment) begin
if (Selector == 20) begin
if (RoomDigit0 == 4'b0000) begin //if 9 seconds na, i zero niya then i increment si tens
RoomDigit0 <= 9;
if(RoomDigit1 == 4'b0000) //if 99 seconds na, i zero niya si tens then i increment si minutes
RoomDigit1 <= 9;
else RoomDigit1 <= RoomDigit1 - 1;
end else RoomDigit0 <= RoomDigit0 - 1;
end
if (Selector == 4) begin
if (RoomDigit0 == 4'b1001) begin //if 9 seconds na, i zero niya then i increment si tens
RoomDigit0 <= 0;
if(RoomDigit1 == 4'b1001) //if 99 seconds na, i zero niya si tens then i increment si minutes
RoomDigit1 <= 0;
else RoomDigit1 <= RoomDigit1 + 1;
end else RoomDigit0 <= RoomDigit0 + 1;
end
end
endmodule
| 7.150211 |
module calculates the correct VRAM adress for the current pixel,
as long as the image-source module has outputted source = 1.
*/
module address_generator(clk, reset, frame, hpixel, vpixel, address, select);
input clk, reset;
input [5:0] frame;
input [6:0] hpixel, vpixel;
output [13:0] address;
output select;
reg select;
reg [5:0] old_frame;
//My animation consists of 8 sprites, therefore I need a 3 bit reg to cycle through them
reg [2:0] current_sprite;
/*
My animation's speed will be 10FPS.
My VGA driver works at 60FPS, so, in order to achive 10FPS,
the same frame must be displayed 6 times.
*/
reg [2:0] frame_counter;
reg [6:0] H; //horizontal offset
reg [6:0] V; //vertical offset
//7 most/least significant bits of address
wire [6:0] address_high, address_low;
parameter [2:0] MAX_FRAME = 3'd6; //resulting FPS will be 60/MAX_FRAME
always @(posedge clk or posedge reset) begin
if (reset == 1'b1) begin
frame_counter = 3'b000;
current_sprite = 3'b000;
end
else begin
old_frame <= frame;
if (old_frame != frame) begin
//frame changed
frame_counter = frame_counter + 3'b1;
end
if (frame_counter == MAX_FRAME) begin
//time to change the displayed sprite
frame_counter = 3'd0;
current_sprite = current_sprite + 3'b1;
end
/*
First set of block RAMs has the first 6 sprites, while the second
set has the last 2.
The sprites are stored left-to-right, top-to-bottom.
All offsets are in regard of the first pixel (leftmost of first row)
of the first sprite.
So each for each sprite that was displayed in the same row, the horizontal
offset must be incremented by 42, while the bottom sprites have a
vertical offset of 48.
*/
case (current_sprite)
3'd0:
begin
H = 7'd0; //no offsets
V = 6'd0;
//first 6 sprites are stored in the first set of block RAMs
select = 1'b0;
end
3'd1:
begin
H = 7'd42; //
V = 6'd0;
end
3'd2:
begin
H = 7'd84;
V = 6'd0;
end
3'd3:
begin
H = 7'd0;
V = 6'd48;
end
3'd4:
begin
H = 7'd42;
V = 6'd48;
end
3'd5:
begin
H = 7'd84;
V = 6'd48;
end
//same as case 0, since this is the same position at the second atlas
3'd6:
begin
H = 7'd0;
V = 6'd0;
//last 2 sprites are stored in the second set of block RAMs
select = 1'b1;
end
//same as case 1, since this is the same position at the second atlas
3'd7:
begin
H = 7'd42;
V = 6'd0;
end
endcase
end
end
/*
I subtract 23 from vpixel and 42 from hpixel to align the displayed sprite with
point A, which is the start of the box in which the sprites are displayed
<---------128-------->
43 42 43
<---><----------><--->
^ +--------------------+ ^
|24 | | |
v | A(42,23) | |
^ | +----------+ | |
|48 | | | | | 96
| | | | | |
v | +----------+ | |
^ | | |
|24 | | |
v +--------------------+ v
*/
assign address_low = hpixel - 6'd42 + H;
assign address_high = vpixel - 6'd23 + V;
assign address = {address_high,address_low};
endmodule
| 7.448165 |
module top (
input CLK,
input BTN_N,
output [15:0] LED_PANEL
);
led_main #(
.DELAY(1)
) main (
.CLK(CLK),
.resetn_btn(BTN_N),
.LED_PANEL(LED_PANEL)
);
endmodule
| 7.233807 |
module painter24 (
input clk,
input reset,
input [ 9:0] frame,
input [ 7:0] subframe,
input [ 5:0] x,
input [ 5:0] y,
output [23:0] rgb24
);
wire border, x_single_bit, y_single_bit;
reg [23:0] rgb;
assign border = x == 0 || y == 0 || x == 63 || y == 63;
assign x_single_bit = (|x) & (~|(x & (x - 1)));
assign y_single_bit = (|y) & (~|(y & (y - 1)));
always @(posedge clk)
if (reset) rgb <= 0;
else if (frame < x + y) rgb <= 0;
else
// BLUE GREEN RED
rgb <= {
{8{x_single_bit}}, {8{y_single_bit}}, {8{border}}
};
assign rgb24 = rgb;
endmodule
| 6.846537 |
module top (
input CLK,
input BTN_N,
output [15:0] LED_PANEL
);
led_main #(
.DELAY(2)
) main (
.CLK(CLK),
.resetn_btn(BTN_N),
.LED_PANEL(LED_PANEL)
);
endmodule
| 7.233807 |
module painter24 (
input clk,
input reset,
input [ 9:0] frame,
input [ 7:0] subframe,
input [ 5:0] x,
input [ 5:0] y,
output [23:0] rgb24
);
wire border, x_single_bit, y_single_bit;
reg [23:0] rgb;
assign border = x == 0 || y == 0 || x == 63 || y == 63;
assign x_single_bit = (|x) & (~|(x & (x - 1)));
assign y_single_bit = (|y) & (~|(y & (y - 1)));
always @(posedge clk)
if (reset) rgb <= 0;
else
// BLUE GREEN RED
rgb <= {
{8{x_single_bit}}, {8{y_single_bit}}, {8{border}}
};
assign rgb24 = rgb;
endmodule
| 6.846537 |
module top (
input CLK,
input BTN_N,
output [15:0] LED_PANEL
);
led_main main (
.CLK(CLK),
.resetn_btn(BTN_N),
.LED_PANEL(LED_PANEL)
);
endmodule
| 7.233807 |
module add_decoder (
addrBank,
addrBlock,
addrRow,
addrIn,
enable
);
output reg [3:0] addrBank, addrBlock;
output reg [7:0] addrRow;
input wire [15:0] addrIn;
input wire enable;
always @(enable or addrIn) begin
if (!enable) begin
addrBank = addrIn[15:12];
addrBlock = addrIn[11:8];
addrRow = addrIn[7:0];
end
end
endmodule
| 7.130094 |
module AddressEncoder (
AddrIn,
AddrOut
);
input [14:0] AddrIn;
output reg [3:0] AddrOut;
always @(*) begin
case (AddrIn) // case ̿Ͽ AddrOut
15'b100_0000_0000_0000: AddrOut = 4'd0;
15'b000_0000_0000_0001: AddrOut = 4'd1;
15'b000_0000_0000_0010: AddrOut = 4'd2;
15'b000_0000_0000_0100: AddrOut = 4'd3;
15'b000_0000_0000_1000: AddrOut = 4'd4;
15'b000_0000_0001_0000: AddrOut = 4'd5;
15'b000_0000_0010_0000: AddrOut = 4'd6;
15'b000_0000_0100_0000: AddrOut = 4'd7;
15'b000_0000_1000_0000: AddrOut = 4'd8;
15'b000_0001_0000_0000: AddrOut = 4'd9;
15'b000_0010_0000_0000: AddrOut = 4'd10;
15'b000_0100_0000_0000: AddrOut = 4'd11;
15'b000_1000_0000_0000: AddrOut = 4'd12;
15'b001_0000_0000_0000: AddrOut = 4'd13;
15'b010_0000_0000_0000: AddrOut = 4'd14;
default: AddrOut = 4'd0; // AddrIn 찡 ۼ ʾ default
endcase
end
endmodule
| 7.539822 |
module AddressExtend (
input [15:0] pc_inc,
input [11:0] address,
output reg [15:0] extended
);
always @(pc_inc or address) begin
extended[0] = 0;
extended[15:13] = pc_inc[15:13];
extended[12:1] = address;
end
endmodule
| 7.771491 |
module addressGen (
clk,
rst,
gen_en,
sobel_en,
addr,
done
);
/// when enabled, will generate address values from 0 to 1023, essentially a counter
/// then will raise done to high
/// for a more robust implemenation, the size of address counter could be parameterized to be suitable for the desired image size
input clk, rst, gen_en, sobel_en;
output reg [9:0] addr;
output reg done;
reg [9:0] c_addr;
//reg [3:0] state, state_c;
reg lock;
initial addr = 10'b00000_00000;
always @(posedge clk) begin
addr <= c_addr; //default
end
//The only issue with this module is that the period for which it asynchronously asserts high is very small and caused some issues with the FSM.
always @(*) begin
done = 0;
if ((gen_en == 1'b1 | sobel_en == 1'b1) & lock == 1'b0) begin
if (addr < 10'b11111_11111) begin
done = 1'b0;
lock = 1'b0;
c_addr = addr + 10'b00000_00001;
end else begin
lock = 1'b1;
done = 1'b1;
c_addr = 10'b00000_00000;
end
end else begin
done = 1'b0;
lock = 1'b0;
c_addr = 10'b00000_00000;
end
if (rst == 1'b1) begin
c_addr = 10'b00000_00000;
done = 1'b0;
lock = 1'b0;
end
end
endmodule
| 6.615115 |
module AddressingUnit (
Rside,
Iside,
Address,
clk,
ResetPC,
PCplusI,
PCplus1,
RplusI,
Rplus0,
PCenable
);
input [15:0] Rside;
input [7:0] Iside;
input ResetPC, PCplusI, PCplus1, RplusI, Rplus0, PCenable;
input clk;
output [15:0] Address;
wire [15:0] PCout;
ProgramCounter PC (
Address,
PCenable,
clk,
PCout
);
AddressLogic AL (
PCout,
Rside,
Iside,
Address,
ResetPC,
PCplusI,
PCplus1,
RplusI,
Rplus0
);
endmodule
| 7.270411 |
module addressing_disp_size_detect (
input [15:0] addressing_aligned,
output [15:0] addressing,
output [1:0] addressing_bytes,
output [3:0] displacement_bytes,
input have_modrm
);
wire disp1, disp0;
assign addressing = addressing_aligned;
wire disp0mask;
wire disp1mask;
and2$(
disp0mask, disp0, have_modrm
); and2$(
disp1mask, disp1, have_modrm
);
mux #(
.WIDTH (4),
.INPUTS(4)
) disp_size_mux (
{4'd4, 4'd4, 4'd1, 4'd0},
displacement_bytes,
{disp1mask, disp0mask}
);
wire sib_mask;
and2$(
sib_mask, sib_byte, have_modrm
);
mux #(
.WIDTH (2),
.INPUTS(4)
) addr_size_mux (
{2'd2, 2'd2, 2'd1, 2'd0},
addressing_bytes,
{sib_mask, have_modrm}
);
modrm_size_map msm (
addressing_aligned[15],
addressing_aligned[14],
addressing_aligned[10],
addressing_aligned[9],
addressing_aligned[8],
sib_byte,
disp1,
disp0
);
endmodule
| 6.500531 |
module addressing_mode_decoder (
input wire [2:0] mode_i,
output reg pre_op_o,
output reg [1:0] other_val_o,
output reg modulo_o,
output reg br_o,
output reg ar_out_o,
output reg imm_o,
output reg ar_wren_o
);
`include "std_messages.vh"
always @* begin
other_val_o = 0;
modulo_o = 0;
br_o = 0;
ar_out_o = 1;
imm_o = 0;
ar_wren_o = 0;
pre_op_o = 0;
case (mode_i) //Decoding addressing mode
`A_INDR: begin
ar_out_o = 0;
end
`A_INDX: begin
pre_op_o = 1;
end
`A_INC: begin
ar_wren_o = 1;
other_val_o = 2'b01;
end // case: `A_INC
`A_DEC: begin
pre_op_o = 1;
ar_wren_o = 1;
other_val_o = 2'b11;
end // case: `A_DEC
`A_OFS: begin
imm_o = 1;
pre_op_o = 1;
end // case: `A_OFS
`A_MINC: begin
ar_wren_o = 1;
other_val_o = 2'b01;
modulo_o = 1;
end // case: `A_MINC
`A_ABS: begin
imm_o = 1;
ar_out_o = 0;
end // case: `A_ABS
`A_BRV: begin
ar_wren_o = 1;
other_val_o = 2'b01;
br_o = 1;
end // case: `A_BRV
default: begin
if (defined_but_illegal(mode_i, 3, "mode_i")) begin
$stop;
end
end
endcase
end
endmodule
| 6.57379 |
module AddressMapper (
input [31:0] ALU_Result,
output [ 7:0] addr
);
assign addr = (ALU_Result - 11'd1024) >> 2;
endmodule
| 6.758881 |
module AddressMapper_8_to_18 (
input [ 7:0] addr1,
output [17:0] addr2
);
assign addr2 = (addr1) << 1;
endmodule
| 6.758881 |
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