code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module adder_max (
cout,
sum,
a,
b,
cin
);
parameter size = 190; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size parameter
input cin;
input [size-1:0] a, b; // 'a' and 'b' use the size parameter
assign {cout, sum} = a + b + cin;
e... | 6.648594 |
module adder_modified (
A,
B,
sub,
sum,
ovf_out
);
input [26:0] A, B;
input sub;
output reg [26:0] sum;
output reg ovf_out;
reg carry_out;
always @(*) begin
{carry_out, sum} = A + B + sub;
ovf_out = carry_out & ~sub;
end
endmodule
| 6.883456 |
module adder_modified_new (
A,
B,
sub,
sum,
ovf_out
);
input [26:0] A, B;
input sub;
output wire [26:0] sum;
output wire ovf_out;
//internal signals
wire carry_out;
//instances
adder adder_inst (
A,
B,
sub,
sum,
carry_out
);
ovf_block ovf_block_inst ... | 6.883456 |
module Adder_module (
data_one,
data_two,
out
);
input [63:0] data_one, data_two;
output [63:0] out;
assign out = data_one + data_two;
endmodule
| 7.328436 |
module adder_mux (
a,
b,
ci,
s,
co
);
input [3:0] a;
input [3:0] b;
input ci;
output [3:0] s;
output co;
wire c0, c1;
wire [3:0] s1, s0;
adder_4bits a1 (
.a (a),
.b (b),
.ci(1'b1),
.s (s1),
.co(c1)
);
adder_4bits a0 (
.a (a),
.b (b),
... | 6.548586 |
module adder_N #(
parameter DATA_W = 32,
parameter N_INPUTS = 2,
parameter N_LEVELS = $clog2(N_INPUTS)
) (
input clk,
input rst,
// data
input [N_INPUTS*DATA_W-1:0] data_in,
output reg [ DATA_W-1:0] data_out
);
// au... | 7.024611 |
module adder_line #(
parameter DATA_W = 32,
parameter N_ADDERS = 2
) (
//data
input [2*N_ADDERS*DATA_W-1:0] data_in,
output [ N_ADDERS*DATA_W-1:0] data_out
);
// generate an adder line
genvar i;
generate
for (i = 0; i < N_ADDERS; i = i + 1) begin : adder_l
adder2_1 #(
... | 8.009343 |
module adder2_1 #(
parameter DATA_W = 32
) (
//data
input [2*DATA_W-1:0] data_in,
output [ DATA_W-1:0] data_out
);
assign data_out = data_in[0*DATA_W+:DATA_W] + data_in[1*DATA_W+:DATA_W];
endmodule
| 7.918827 |
module adder_nbit
// Parameters section
#(
parameter N = 3
)
// Ports section
(
input [N-1:0] a,
input [N-1:0] b,
output reg [N:0] sum
);
// Wildcard operator is best for the procedure's
// sensitivity list (control list)
always @(*) begin
sum[N:0] = a[N-1:0] + b[N-1:0];
//sum = a + b;
... | 7.523262 |
module tb_adder_nbit ();
parameter ADDER_WIDTH = 10;
reg [ADDER_WIDTH-1:0] a;
reg [ADDER_WIDTH-1:0] b;
wire [ ADDER_WIDTH:0] sum;
// Instantiate the parameterized DUT
adder_nbit #(
.N(ADDER_WIDTH)
) ADDER1 (
.a (a),
.b (b),
.sum(sum)
);
// Create stimulus
initial begi... | 6.662005 |
module adder_N_bits #(
parameter N = 8
) (
input [N-1:0] A,
B,
input cin,
output [N-1:0] S,
output cout
);
assign {cout, S} = A + B + cin;
endmodule
| 7.790948 |
module adder_one (
a,
b,
c1,
sum,
c2
);
input wire a, b, c1;
output wire c2, sum;
assign sum = a ^~ b ^~ c1;
assign c2 = (a & b) | (b & c1) | (a & c1);
endmodule
| 7.303335 |
module can act as an `incarry` bit for another adder
// The value of sum, represents the sum of both the numbers.
module adder_parallel_4_bit(sum, outcarry, num1, num2, incarry);
input[3:0] num1, num2;
input incarry;
wire[3:0] carry_bits;
output[3:0] sum;
output outcarry;
adder_full wire_driv... | 8.362232 |
module adder_param (
in1,
in2,
cin,
sum,
cout
);
parameter WIDTH = 32;
input cin;
input [WIDTH-1:0] in1, in2;
output [WIDTH-1:0] sum;
output cout;
wire [WIDTH-1:0] cout_adders;
adder1bit adders[WIDTH-1:0] (
.sum (sum),
.cout(cout_adders),
.in1 (in1),
.in2 (i... | 7.512604 |
module Adder_PCPlus4 (
PC_o,
PCPlus4
);
input [31:0] PC_o;
output reg [31:0] PCPlus4;
always @(*) begin
PCPlus4 = PC_o + 32'd4;
end
endmodule
| 8.177714 |
module Adder (
input iSA,
input [7:0] iData_a,
input [7:0] iData_b,
output reg [8:0] oData,
output reg oData_C
);
reg [7:0] iData_A;
reg [7:0] iData_B;
always @(*) begin
case (iSA)
1'b1: begin
//oData={iData_a[7],iData_a}+{iData_b[7],iData_b};
if (iData_a[7] == 1) beg... | 7.642138 |
module finaladderr (
output Si,
input ai,
bi,
Ci
);
wire w;
xor (w, ai, bi);
xor (Si, w, Ci);
endmodule
| 7.712775 |
module calcblock (
output G,
P,
input Gi,
Pi,
Gip,
Pip
);
wire w;
and (w, Pi, Gip);
or (G, w, Gi);
and (P, Pi, Pip);
endmodule
| 8.025708 |
module dff (
d,
clk,
clear,
q
);
input d, clk, clear;
output reg q;
always @(posedge clk) begin
if (clear == 1) q <= 0;
else q <= d;
//$display("%d\n",$time);
end
endmodule
| 7.361383 |
module adder_8bits(
a,
b,
ci,
y,
co
);
input a;
input b;
input ci;
output y;
output co;
wire [7:0] a;
wire [7:0] b;
wire [7:0] y
always @(a or b or ci) begin
{co, y} = {1'b0, a} + {ci, b};
end
endmodule
| 6.831238 |
module adder_16bits(
a,
b,
ci,
y,
co
);
input a;
input b;
input ci;
output y;
output co;
wire [15:0] a;
wire [15:0] b;
wire [15:0] y
wire co_lo;
wire [7:0] y_lo;
wire [7:0] y_hi;
adder_8bibts
adder_lo (
.a(a[7:0]),
.b(b[7:0]),
.ci(ci),
.y(y_lo),
.co(co_lo)
);
adder_8bits
adder_hi (
.a(a... | 7.576228 |
module adder_16bits_pipeline(
clk,
resetn,
a,
b,
ci,
y,
co
);
input clk;
input resetn;
input a;
input b;
input ci;
output y;
output co;
wire [15:0] a;
wire [15:0] b;
wire [15:0] y
//interal variable
reg[7:0] a_hi;
reg[7:0] b_hi;
reg[7:0] y_hi;
reg[7:0] y_lo;
reg co_lo;
reg[1:0] counter;
always @(posedge clk or... | 6.637331 |
module ripple_adder (
X,
Y,
S,
Co
);
input [7:0] X, Y; // Two 8-bit inputs
output [7:0] S;
output Co;
wire w0, w1, w2, w3, w4, w5, w6;
// instantiating 8 1-bit full adders in Verilog
fulladder u1 (
X[0],
Y[0],
1'b0,
S[0],
w0
);
fulladder u2 (
X[1],
... | 9.165067 |
module Adder_Round #(
parameter SW = 26
) (
input wire clk,
input wire rst,
input wire load_i, //Reg load input
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
/////////////////////////////////////////////////////////////
output wire [SW-1:0] Data_Result_o,
output wi... | 6.89936 |
module BLOCKG_0 (
pik,
gik,
gk_1j,
gij
);
input pik;
input gik;
input gk_1j;
output gij;
// Internal wires
wire n2;
INV_X1 U1 (
.A (n2),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(pik),
.B2(gk_1j),
.ZN(n2)
);
endmodule
| 6.594924 |
module BLOCKPG_0 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n2;
AND2_X1 U1 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
INV_X1 U2 (
.A (n2),
.ZN(gij)
);
AOI2... | 6.506862 |
module BLOCKG_1 (
pik,
gik,
gk_1j,
gij
);
input pik;
input gik;
input gk_1j;
output gij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(pik),
.B2(gk_1j),
.ZN(n1)
);
endmodule
| 6.52544 |
module BLOCKG_2 (
pik,
gik,
gk_1j,
gij
);
input pik;
input gik;
input gk_1j;
output gij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(pik),
.B2(gk_1j),
.ZN(n1)
);
endmodule
| 7.107481 |
module BLOCKG_3 (
pik,
gik,
gk_1j,
gij
);
input pik;
input gik;
input gk_1j;
output gij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(pik),
.B2(gk_1j),
.ZN(n1)
);
endmodule
| 7.131068 |
module BLOCKG_4 (
pik,
gik,
gk_1j,
gij
);
input pik;
input gik;
input gk_1j;
output gij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(pik),
.B2(gk_1j),
.ZN(n1)
);
endmodule
| 6.716439 |
module BLOCKG_5 (
pik,
gik,
gk_1j,
gij
);
input pik;
input gik;
input gk_1j;
output gij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(pik),
.B2(gk_1j),
.ZN(n1)
);
endmodule
| 6.541632 |
module BLOCKG_6 (
pik,
gik,
gk_1j,
gij
);
input pik;
input gik;
input gk_1j;
output gij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(pik),
.B2(gk_1j),
.ZN(n1)
);
endmodule
| 6.993577 |
module BLOCKG_7 (
pik,
gik,
gk_1j,
gij
);
input pik;
input gik;
input gk_1j;
output gij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(pik),
.B2(gk_1j),
.ZN(n1)
);
endmodule
| 7.109247 |
module BLOCKG_8 (
pik,
gik,
gk_1j,
gij
);
input pik;
input gik;
input gk_1j;
output gij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(pik),
.B2(gk_1j),
.ZN(n1)
);
endmodule
| 6.857043 |
module BLOCKPG_1 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
AND2_X1 U1 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
INV_X1 U2 (
.A (n1),
.ZN(gij)
);
AOI2... | 6.579407 |
module BLOCKPG_2 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
AND2_X1 U1 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
INV_X1 U2 (
.A (n1),
.ZN(gij)
);
AOI2... | 7.349652 |
module BLOCKPG_3 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN... | 6.914638 |
module BLOCKPG_4 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN... | 6.766767 |
module BLOCKPG_5 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
AND2_X1 U1 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
INV_X1 U2 (
.A (n1),
.ZN(gij)
);
AOI2... | 6.706367 |
module BLOCKPG_6 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
AOI21_X1 U1 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
INV_X1 U2 (
.A (n1),
.ZN(... | 6.804914 |
module BLOCKPG_7 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN... | 7.056747 |
module BLOCKPG_8 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN... | 7.035015 |
module BLOCKPG_9 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN... | 6.909036 |
module BLOCKPG_10 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.Z... | 6.9038 |
module BLOCKPG_11 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.Z... | 6.772201 |
module BLOCKPG_12 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
AOI21_X1 U1 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U2 (
.A1(pk_1j),
... | 6.898401 |
module BLOCKPG_13 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.Z... | 7.09307 |
module BLOCKPG_14 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.Z... | 7.098283 |
module BLOCKPG_15 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.Z... | 6.896809 |
module BLOCKPG_16 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.Z... | 7.027928 |
module BLOCKPG_17 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.Z... | 6.828824 |
module BLOCKPG_18 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.Z... | 6.864316 |
module BLOCKPG_19 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.Z... | 6.701137 |
module BLOCKPG_20 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.Z... | 7.277324 |
module BLOCKPG_21 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.Z... | 6.872382 |
module BLOCKPG_22 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.Z... | 6.693136 |
module BLOCKPG_23 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.Z... | 6.592909 |
module BLOCKPG_24 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.Z... | 6.862365 |
module BLOCKPG_25 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.Z... | 6.826138 |
module BLOCKPG_26 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.Z... | 6.672245 |
module RCA_NBIT4_0 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_0 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_63 FAI_2 (
.A (A[1]),
... | 7.740963 |
module RCA_NBIT4_15 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_60 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_59 FAI_2 (
.A (A[1]),
... | 7.949759 |
module FA_4 (
A,
B,
Ci,
S,
Co
);
input A;
input B;
input Ci;
output S;
output Co;
// Internal wires
wire n1;
wire n3;
XOR2_X1 U3 (
.A(Ci),
.B(n3),
.Z(S)
);
XOR2_X1 U4 (
.A(A),
.B(B),
.Z(n3)
);
INV_X1 U1 (
.A (n1),
.ZN(Co)
... | 6.626139 |
module RCA_NBIT4_1 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_4 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_3 FAI_2 (
.A (A[1]),
... | 7.874833 |
module FA_7 (
A,
B,
Ci,
S,
Co
);
input A;
input B;
input Ci;
output S;
output Co;
// Internal wires
wire n1;
wire n3;
XOR2_X1 U3 (
.A(Ci),
.B(n3),
.Z(S)
);
XOR2_X1 U4 (
.A(A),
.B(B),
.Z(n3)
);
INV_X1 U1 (
.A (n1),
.ZN(Co)
... | 6.624434 |
module FA_8 (
A,
B,
Ci,
S,
Co
);
input A;
input B;
input Ci;
output S;
output Co;
// Internal wires
wire n1;
wire n3;
XOR2_X1 U3 (
.A(Ci),
.B(n3),
.Z(S)
);
XOR2_X1 U4 (
.A(A),
.B(B),
.Z(n3)
);
INV_X1 U1 (
.A (n1),
.ZN(Co)
... | 6.565071 |
module RCA_NBIT4_2 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_8 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_7 FAI_2 (
.A (A[1]),
... | 7.968296 |
module RCA_NBIT4_3 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_12 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_11 FAI_2 (
.A (A[1]),
... | 7.787572 |
module RCA_NBIT4_4 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_16 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_15 FAI_2 (
.A (A[1]),
... | 7.974063 |
module RCA_NBIT4_5 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_20 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_19 FAI_2 (
.A (A[1]),
... | 8.124965 |
module RCA_NBIT4_6 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_24 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_23 FAI_2 (
.A (A[1]),
... | 7.931223 |
module CSB_RADIX4_3 (
A,
B,
Ci,
S
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
// Internal wires
wire [3:0] S0;
wire [3:0] S1;
RCA_NBIT4_6 RCA0 (
.A (A),
.B (B),
.Ci(1'b0),
.S (S0)
);
RCA_NBIT4_5 RCA1 (
.A (A),
.B (B),
.Ci(1'b... | 6.528569 |
module FA_25 (
A,
B,
Ci,
S,
Co
);
input A;
input B;
input Ci;
output S;
output Co;
// Internal wires
wire n1;
wire n3;
XOR2_X1 U3 (
.A(Ci),
.B(n3),
.Z(S)
);
XOR2_X1 U4 (
.A(A),
.B(B),
.Z(n3)
);
INV_X1 U1 (
.A (n1),
.ZN(Co)
... | 6.590419 |
module RCA_NBIT4_7 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_28 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_27 FAI_2 (
.A (A[1]),
... | 7.936123 |
module RCA_NBIT4_8 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_32 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_31 FAI_2 (
.A (A[1]),
... | 7.986719 |
module RCA_NBIT4_9 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_36 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_35 FAI_2 (
.A (A[1]),
... | 7.787699 |
module RCA_NBIT4_10 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_40 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_39 FAI_2 (
.A (A[1]),
... | 7.738482 |
module FA_43 (
A,
B,
Ci,
S,
Co
);
input A;
input B;
input Ci;
output S;
output Co;
// Internal wires
wire n1;
wire n3;
XOR2_X1 U3 (
.A(Ci),
.B(n3),
.Z(S)
);
XOR2_X1 U4 (
.A(A),
.B(B),
.Z(n3)
);
INV_X1 U1 (
.A (n1),
.ZN(Co)
... | 6.914429 |
module FA_44 (
A,
B,
Ci,
S,
Co
);
input A;
input B;
input Ci;
output S;
output Co;
// Internal wires
wire n1;
wire n3;
XOR2_X1 U3 (
.A(Ci),
.B(n3),
.Z(S)
);
XOR2_X1 U4 (
.A(A),
.B(B),
.Z(n3)
);
INV_X1 U1 (
.A (n1),
.ZN(Co)
... | 6.871119 |
module RCA_NBIT4_11 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_44 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_43 FAI_2 (
.A (A[1]),
... | 7.846434 |
module RCA_NBIT4_12 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_48 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_47 FAI_2 (
.A (A[1]),
... | 7.992663 |
module CSB_RADIX4_6 (
A,
B,
Ci,
S
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
// Internal wires
wire [3:0] S0;
wire [3:0] S1;
RCA_NBIT4_12 RCA0 (
.A (A),
.B (B),
.Ci(1'b0),
.S (S0)
);
RCA_NBIT4_11 RCA1 (
.A (A),
.B (B),
.Ci(1... | 6.510462 |
module RCA_NBIT4_13 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_52 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_51 FAI_2 (
.A (A[1]),
... | 7.780681 |
module RCA_NBIT4_14 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_56 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_55 FAI_2 (
.A (A[1]),
... | 7.934078 |
module SUMGEN_NBIT32_RADIX4 (
A,
B,
Ci,
S
);
input [31:0] A;
input [31:0] B;
input [7:0] Ci;
output [31:0] S;
CSB_RADIX4_0 GENi_7 (
.A ({A[31], A[30], A[29], A[28]}),
.B ({B[31], B[30], B[29], B[28]}),
.Ci(Ci[7]),
.S ({S[31], S[30], S[29], S[28]})
);
CSB_RADIX4_7 G... | 7.221513 |
module P4ADDER_NBIT32 (
A,
B,
Ci,
S,
Co
);
input [31:0] A;
input [31:0] B;
input Ci;
output [31:0] S;
output Co;
// Internal wires
wire [6:0] carry_ST;
SPARSETREE_NBIT32_RADIX4 SPARSETREE0 (
.A (A),
.B (B),
.Ci(Ci),
.Co({Co, carry_ST})
);
SUMGEN_NBIT32_R... | 7.085748 |
module adder_signed #(
parameter WIDTH = 16
) (
input [WIDTH-1:0] a,
b,
output [WIDTH-1:0] c
);
assign c = a + b;
//always @(*)
// c = b[WIDTH-1] ? ~c1:c1;
endmodule
| 8.183344 |
module adder_stage (
input clock,
input reset,
input [2:0] a,
input [2:0] b,
output reg [3:0] out
);
wire [3:0] adder_next = $signed({1'b0, a}) + $signed({1'b0, b});
always @(posedge clock) begin
if (reset) begin
out <= 'h0;
end else begin
ou... | 6.931138 |
module adder (A, B, Cin, S, P, G, OVF);
module adder (A, B, Cin, S, OVF);
////////
// IO //
////////
input [31:0] A, B;
input Cin;
// output [31:0] S, P, G;
output [31:0] S;
output OVF;
// P, G
// assign G = A & B; // carry generate
// assign P = A ^ B; // carry propagate
// let the syn... | 6.674372 |
module
// Carry Look-Ahead Unit
module CLA (P, G, C, Cout, Pin, Gin, Cin);
// I/O
output [3:0] C;
output Cout, P, G;
input [3:0] Pin, Gin;
input Cin;
assign C[0] = Cin;
assign C[1] = Gin[0] | (Pin[0] & Cin);
assign C[2] = Gin[1] | (Pin[1] & Gin[0]) | (Pin[1] & Pin[0] & Cin);
assign C[3] = Gin[2] | ... | 7.63573 |
module adder_subs (
input [3:0] a,
b,
input sel,
output [3:0] s,
output co
);
wire b_in;
mux_4_1_4b mux (
.a (b),
.b (~b),
.sel(sel),
.z (b_in)
);
full_adder_4b fa (
.a (a),
.b (b_in),
.ci(sel),
.s (s)
);
endmodule
| 7.290006 |
module adder_subs_4b (
input [4:0] dato0,
input [4:0] dato1,
input [4:0] dato2,
input [4:0] dato3,
input clk,
output [3:0] segm,
output [3:0] transistor
);
endmodule
| 6.823239 |
module mux_in_time_4x4 (
input [4:0] dato0,
input [4:0] dato1,
input [4:0] dato2,
input [4:0] dato3,
input clk,
output [3:0] segm,
output [3:0] transistor
);
endmodule
| 6.98045 |
module is a 3 bit adder/subtractor.
It will output B - A if desired.
*/
module adder_subtractor_3bit(a, b, want_subtract, c_out, s);
/*
* I/Os
*/
input [2:0] a, b;
input want_subtract; // If want_subtract == 1, we subtract. Otherwise we add.
output [2:0] s;
output c_out;
wire [1:0]c;
wire [... | 7.257624 |
module is a 4 bit adder/subtractor.
It will output B - A if desired.
*/
module adder_subtractor_4bit(a, b, want_subtract, c_out, s);
/*
* I/Os
*/
input [3:0] a, b;
input want_subtract; // If want_subtract == 1, we subtract. Otherwise we add.
output [3:0] s;
output c_out;
wire [2:0]c;
wire [... | 7.220341 |
module is a 6 bit adder/subtractor.
It will output B - A if desired.
*/
module adder_subtractor_6bit(a, b, want_subtract, c_out, s);
/*
I/Os
*/
input [5:0] a, b;
input want_subtract; // If want_subtract == 1, we subtract. Otherwise we add.
output [5:0] s;
output c_out;
wire [4:0]c;
wire [5:0]a_adder;
... | 6.691948 |
module adder_sub_24bit (
in1,
in2,
carry_previous,
sum_bits,
carry_out,
add_sub
);
input wire [23:0] in1, in2;
input wire carry_previous, add_sub;
output wire [23:0] sum_bits;
output wire carry_out;
wire [2:0] temp_carry;
//instantiating three 8 bit adders , previous carry is add_... | 6.992766 |
module adder_sub_8bit (
in1,
in2,
carry_out,
sum,
add_sub,
carry_in
);
input wire [7:0] in1, in2;
input wire add_sub, carry_in;
output wire carry_out;
output wire [7:0] sum;
wire [7:0] temp_in2, temp_carry_next;
// Manipulate input 2 for subtraction
xor x7 (temp_in2[7], in2, add... | 7.635772 |
module adder_switch #(
parameter DATA_TYPE = 32,
parameter NUM_IN = 4,
parameter SEL_IN = 2
) (
clk,
rst,
i_valid, // valid data signal
i_data_bus, // input data bus coming into adder switch
// reconfigurable control signal
i_add_en, // add enable
i_cmd, // command forward
... | 8.233951 |
module Adder_Target_Addr (
output reg [31:0] Output,
input [23:0] inputA,
input [31:0] inputB
);
always @(inputA, inputB) begin
// Calculate two's comp;
Output = 32'b00000000000000000000000000000000;
if (inputA[23] == 1) begin
Output[23:0] = ~inputA;
Output = inputB - Output - 1'b1... | 6.56098 |
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