code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module adder_max (
cout,
sum,
a,
b,
cin
);
parameter size = 190; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size parameter
input cin;
input [size-1:0] a, b; // 'a' and 'b' use the size parameter
assign {cout, sum} = a + b + cin;
endmodule
| 6.648594 |
module adder_modified (
A,
B,
sub,
sum,
ovf_out
);
input [26:0] A, B;
input sub;
output reg [26:0] sum;
output reg ovf_out;
reg carry_out;
always @(*) begin
{carry_out, sum} = A + B + sub;
ovf_out = carry_out & ~sub;
end
endmodule
| 6.883456 |
module adder_modified_new (
A,
B,
sub,
sum,
ovf_out
);
input [26:0] A, B;
input sub;
output wire [26:0] sum;
output wire ovf_out;
//internal signals
wire carry_out;
//instances
adder adder_inst (
A,
B,
sub,
sum,
carry_out
);
ovf_block ovf_block_inst (
carry_out,
sub,
ovf_out
);
endmodule
| 6.883456 |
module Adder_module (
data_one,
data_two,
out
);
input [63:0] data_one, data_two;
output [63:0] out;
assign out = data_one + data_two;
endmodule
| 7.328436 |
module adder_mux (
a,
b,
ci,
s,
co
);
input [3:0] a;
input [3:0] b;
input ci;
output [3:0] s;
output co;
wire c0, c1;
wire [3:0] s1, s0;
adder_4bits a1 (
.a (a),
.b (b),
.ci(1'b1),
.s (s1),
.co(c1)
);
adder_4bits a0 (
.a (a),
.b (b),
.ci(1'b0),
.s (s0),
.co(c0)
);
assign co = ci & c1 | c0;
mux2 #(
.n(4)
) m (
.ina (s0),
.inb (s1),
.sel (ci),
.outy(s)
);
endmodule
| 6.548586 |
module adder_N #(
parameter DATA_W = 32,
parameter N_INPUTS = 2,
parameter N_LEVELS = $clog2(N_INPUTS)
) (
input clk,
input rst,
// data
input [N_INPUTS*DATA_W-1:0] data_in,
output reg [ DATA_W-1:0] data_out
);
// aux wire
wire signed [(2*N_INPUTS-1)*DATA_W-1:0] part_sum;
//assign input
assign part_sum[0+:N_INPUTS*DATA_W] = data_in;
// generate all tree levels
genvar i;
generate
if (N_LEVELS == 0) begin : no_tree
assign part_sum[(2*N_INPUTS-1)*DATA_W-1-:DATA_W] = data_in;
end else begin
for (i = 0; i < N_LEVELS; i = i + 1) begin : adder_tree
localparam LINE_ADDERS = N_INPUTS / (2 ** (i + 1)); // Number of adders in i-th line
localparam ACC_SUMS = 2*N_INPUTS-4*LINE_ADDERS; // Number of partial sums done before i-th line
adder_line #(
.DATA_W (DATA_W),
.N_ADDERS(LINE_ADDERS)
) adder_tree_line (
.data_in (part_sum[ACC_SUMS*DATA_W+:LINE_ADDERS*2*DATA_W]),
.data_out(part_sum[(ACC_SUMS+2*LINE_ADDERS)*DATA_W+:LINE_ADDERS*DATA_W])
);
end
end
endgenerate
// register output
always @(posedge clk, posedge rst)
if (rst) data_out <= {DATA_W{1'b0}};
else data_out <= part_sum[(2*N_INPUTS-1)*DATA_W-1-:DATA_W];
endmodule
| 7.024611 |
module adder_line #(
parameter DATA_W = 32,
parameter N_ADDERS = 2
) (
//data
input [2*N_ADDERS*DATA_W-1:0] data_in,
output [ N_ADDERS*DATA_W-1:0] data_out
);
// generate an adder line
genvar i;
generate
for (i = 0; i < N_ADDERS; i = i + 1) begin : adder_l
adder2_1 #(
.DATA_W(DATA_W)
) adder2_1_inst (
.data_in (data_in[i*2*DATA_W+:2*DATA_W]),
.data_out(data_out[i*DATA_W+:DATA_W])
);
end
endgenerate
endmodule
| 8.009343 |
module adder2_1 #(
parameter DATA_W = 32
) (
//data
input [2*DATA_W-1:0] data_in,
output [ DATA_W-1:0] data_out
);
assign data_out = data_in[0*DATA_W+:DATA_W] + data_in[1*DATA_W+:DATA_W];
endmodule
| 7.918827 |
module adder_nbit
// Parameters section
#(
parameter N = 3
)
// Ports section
(
input [N-1:0] a,
input [N-1:0] b,
output reg [N:0] sum
);
// Wildcard operator is best for the procedure's
// sensitivity list (control list)
always @(*) begin
sum[N:0] = a[N-1:0] + b[N-1:0];
//sum = a + b;
end
endmodule
| 7.523262 |
module tb_adder_nbit ();
parameter ADDER_WIDTH = 10;
reg [ADDER_WIDTH-1:0] a;
reg [ADDER_WIDTH-1:0] b;
wire [ ADDER_WIDTH:0] sum;
// Instantiate the parameterized DUT
adder_nbit #(
.N(ADDER_WIDTH)
) ADDER1 (
.a (a),
.b (b),
.sum(sum)
);
// Create stimulus
initial begin
$monitor($time, " a = %d, b = %d, sum = %d", a, b, sum);
#1;
a = 0;
b = 0;
#2;
a = 1;
b = 99;
#1;
a = 33;
b = 66;
#1;
a = 100;
b = 47;
#1;
$stop;
end
endmodule
| 6.662005 |
module adder_N_bits #(
parameter N = 8
) (
input [N-1:0] A,
B,
input cin,
output [N-1:0] S,
output cout
);
assign {cout, S} = A + B + cin;
endmodule
| 7.790948 |
module adder_one (
a,
b,
c1,
sum,
c2
);
input wire a, b, c1;
output wire c2, sum;
assign sum = a ^~ b ^~ c1;
assign c2 = (a & b) | (b & c1) | (a & c1);
endmodule
| 7.303335 |
module can act as an `incarry` bit for another adder
// The value of sum, represents the sum of both the numbers.
module adder_parallel_4_bit(sum, outcarry, num1, num2, incarry);
input[3:0] num1, num2;
input incarry;
wire[3:0] carry_bits;
output[3:0] sum;
output outcarry;
adder_full wire_driver_0(sum[0], carry_bits[0], num1[0], num2[0], incarry);
adder_full wire_driver_1(sum[1], carry_bits[1], num1[1], num2[1], carry_bits[0]);
adder_full wire_driver_2(sum[2], carry_bits[2], num1[2], num2[2], carry_bits[1]);
adder_full wire_driver_3(sum[3], carry_bits[3], num1[3], num2[3], carry_bits[2]);
assign outcarry = carry_bits[3];
endmodule
| 8.362232 |
module adder_param (
in1,
in2,
cin,
sum,
cout
);
parameter WIDTH = 32;
input cin;
input [WIDTH-1:0] in1, in2;
output [WIDTH-1:0] sum;
output cout;
wire [WIDTH-1:0] cout_adders;
adder1bit adders[WIDTH-1:0] (
.sum (sum),
.cout(cout_adders),
.in1 (in1),
.in2 (in2),
.cin ({cout_adders[WIDTH-2:0], cin})
);
assign cout = cout_adders[WIDTH-1];
endmodule
| 7.512604 |
module Adder_PCPlus4 (
PC_o,
PCPlus4
);
input [31:0] PC_o;
output reg [31:0] PCPlus4;
always @(*) begin
PCPlus4 = PC_o + 32'd4;
end
endmodule
| 8.177714 |
module Adder (
input iSA,
input [7:0] iData_a,
input [7:0] iData_b,
output reg [8:0] oData,
output reg oData_C
);
reg [7:0] iData_A;
reg [7:0] iData_B;
always @(*) begin
case (iSA)
1'b1: begin
//oData={iData_a[7],iData_a}+{iData_b[7],iData_b};
if (iData_a[7] == 1) begin
iData_A = iData_a;
iData_A[6] = ~iData_a[6];
iData_A[5] = ~iData_a[5];
iData_A[4] = ~iData_a[4];
iData_A[3] = ~iData_a[3];
iData_A[2] = ~iData_a[2];
iData_A[1] = ~iData_a[1];
iData_A[0] = ~iData_a[0];
iData_A = iData_A + 1;
end
if (iData_b[7] == 1) begin
iData_B = iData_b;
iData_B[6] = ~iData_b[6];
iData_B[5] = ~iData_b[5];
iData_B[4] = ~iData_b[4];
iData_B[3] = ~iData_b[3];
iData_B[2] = ~iData_b[2];
iData_B[1] = ~iData_b[1];
iData_B[0] = ~iData_b[0];
iData_B = iData_B + 1;
end
if ((iData_a[7] == 1 && iData_b[7] == 0)) begin
oData = iData_A + iData_B;
oData_C = 0;
end else if ((iData_a[7] == 0 && iData_b[7] == 1)) begin
oData = iData_A + iData_B;
oData_C = 0;
end else if ((iData_a[7] == 0 && iData_b[7] == 0)) begin
oData = iData_a + iData_b;
oData_C = oData[7];
end else if (((iData_a[7] == 1 && iData_b[7] == 1))) begin
oData = iData_A + iData_B;
oData_C = oData[8];
end
end
1'b0: begin
oData = iData_a + iData_b;
oData_C = oData[8];
end
default: begin
oData_C = 1'bx;
oData = 8'bxxxxxxxx;
end
endcase
end
endmodule
| 7.642138 |
module finaladderr (
output Si,
input ai,
bi,
Ci
);
wire w;
xor (w, ai, bi);
xor (Si, w, Ci);
endmodule
| 7.712775 |
module calcblock (
output G,
P,
input Gi,
Pi,
Gip,
Pip
);
wire w;
and (w, Pi, Gip);
or (G, w, Gi);
and (P, Pi, Pip);
endmodule
| 8.025708 |
module dff (
d,
clk,
clear,
q
);
input d, clk, clear;
output reg q;
always @(posedge clk) begin
if (clear == 1) q <= 0;
else q <= d;
//$display("%d\n",$time);
end
endmodule
| 7.361383 |
module adder_8bits(
a,
b,
ci,
y,
co
);
input a;
input b;
input ci;
output y;
output co;
wire [7:0] a;
wire [7:0] b;
wire [7:0] y
always @(a or b or ci) begin
{co, y} = {1'b0, a} + {ci, b};
end
endmodule
| 6.831238 |
module adder_16bits(
a,
b,
ci,
y,
co
);
input a;
input b;
input ci;
output y;
output co;
wire [15:0] a;
wire [15:0] b;
wire [15:0] y
wire co_lo;
wire [7:0] y_lo;
wire [7:0] y_hi;
adder_8bibts
adder_lo (
.a(a[7:0]),
.b(b[7:0]),
.ci(ci),
.y(y_lo),
.co(co_lo)
);
adder_8bits
adder_hi (
.a(a[8:15]),
.b(b[8:15]),
.ci(co_lo),
.y(y_hi),
.co(co)
);
assign y = {y_hi, y_lo};
endmodule
| 7.576228 |
module adder_16bits_pipeline(
clk,
resetn,
a,
b,
ci,
y,
co
);
input clk;
input resetn;
input a;
input b;
input ci;
output y;
output co;
wire [15:0] a;
wire [15:0] b;
wire [15:0] y
//interal variable
reg[7:0] a_hi;
reg[7:0] b_hi;
reg[7:0] y_hi;
reg[7:0] y_lo;
reg co_lo;
reg[1:0] counter;
always @(posedge clk or negedge resetn)
if (~resetn) begin
a_hi <= 8'h0;
b_hi <= 8'h0;
y_hi <= 8'h0;
y_lo <= 8'h0;
co_lo <= 1'b0;
counter <= 0;
end else begin
if (counter ==0) begin
a_hi <= a[15:8];
b_hi <= b[15:8];
{co_lo, y_lo} <= {1'b0, a[7:0] } + {ci, b[7:0]};
counter <= 1;
end else if (counter ==1) begin
{co, y_hi} <= {1'b0, a_hi} + {co_lo, b_hi};
counter <=2;
end else if (counter == 2) begin
y <= {y_hi, y_lo};
counter <= 0;
end
end
endmodule
| 6.637331 |
module ripple_adder (
X,
Y,
S,
Co
);
input [7:0] X, Y; // Two 8-bit inputs
output [7:0] S;
output Co;
wire w0, w1, w2, w3, w4, w5, w6;
// instantiating 8 1-bit full adders in Verilog
fulladder u1 (
X[0],
Y[0],
1'b0,
S[0],
w0
);
fulladder u2 (
X[1],
Y[1],
w0,
S[1],
w1
);
fulladder u3 (
X[2],
Y[2],
w1,
S[2],
w2
);
fulladder u4 (
X[3],
Y[3],
w2,
S[3],
w3
);
fulladder u5 (
X[4],
Y[4],
w3,
S[4],
w4
);
fulladder u6 (
X[5],
Y[5],
w4,
S[5],
w5
);
fulladder u7 (
X[6],
Y[6],
w5,
S[6],
w6
);
fulladder u8 (
X[7],
Y[7],
w6,
S[7],
Co
);
endmodule
| 9.165067 |
module Adder_Round #(
parameter SW = 26
) (
input wire clk,
input wire rst,
input wire load_i, //Reg load input
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
/////////////////////////////////////////////////////////////
output wire [SW-1:0] Data_Result_o,
output wire FSM_C_o
);
wire [SW:0] result_A_adder;
adder #(
.W(SW)
) A_operation (
.Data_A_i(Data_A_i),
.Data_B_i(Data_B_i),
.Data_S_o(result_A_adder)
);
RegisterAdd #(
.W(SW)
) Add_Subt_Result (
.clk(clk),
.rst(rst),
.load(load_i),
.D(result_A_adder[SW-1:0]),
.Q(Data_Result_o)
);
RegisterAdd #(
.W(1)
) Add_overflow_Result (
.clk(clk),
.rst(rst),
.load(load_i),
.D(result_A_adder[SW]),
.Q(FSM_C_o)
);
endmodule
| 6.89936 |
module BLOCKG_0 (
pik,
gik,
gk_1j,
gij
);
input pik;
input gik;
input gk_1j;
output gij;
// Internal wires
wire n2;
INV_X1 U1 (
.A (n2),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(pik),
.B2(gk_1j),
.ZN(n2)
);
endmodule
| 6.594924 |
module BLOCKPG_0 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n2;
AND2_X1 U1 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
INV_X1 U2 (
.A (n2),
.ZN(gij)
);
AOI21_X1 U3 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n2)
);
endmodule
| 6.506862 |
module BLOCKG_1 (
pik,
gik,
gk_1j,
gij
);
input pik;
input gik;
input gk_1j;
output gij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(pik),
.B2(gk_1j),
.ZN(n1)
);
endmodule
| 6.52544 |
module BLOCKG_2 (
pik,
gik,
gk_1j,
gij
);
input pik;
input gik;
input gk_1j;
output gij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(pik),
.B2(gk_1j),
.ZN(n1)
);
endmodule
| 7.107481 |
module BLOCKG_3 (
pik,
gik,
gk_1j,
gij
);
input pik;
input gik;
input gk_1j;
output gij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(pik),
.B2(gk_1j),
.ZN(n1)
);
endmodule
| 7.131068 |
module BLOCKG_4 (
pik,
gik,
gk_1j,
gij
);
input pik;
input gik;
input gk_1j;
output gij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(pik),
.B2(gk_1j),
.ZN(n1)
);
endmodule
| 6.716439 |
module BLOCKG_5 (
pik,
gik,
gk_1j,
gij
);
input pik;
input gik;
input gk_1j;
output gij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(pik),
.B2(gk_1j),
.ZN(n1)
);
endmodule
| 6.541632 |
module BLOCKG_6 (
pik,
gik,
gk_1j,
gij
);
input pik;
input gik;
input gk_1j;
output gij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(pik),
.B2(gk_1j),
.ZN(n1)
);
endmodule
| 6.993577 |
module BLOCKG_7 (
pik,
gik,
gk_1j,
gij
);
input pik;
input gik;
input gk_1j;
output gij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(pik),
.B2(gk_1j),
.ZN(n1)
);
endmodule
| 7.109247 |
module BLOCKG_8 (
pik,
gik,
gk_1j,
gij
);
input pik;
input gik;
input gk_1j;
output gij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(pik),
.B2(gk_1j),
.ZN(n1)
);
endmodule
| 6.857043 |
module BLOCKPG_1 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
AND2_X1 U1 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
INV_X1 U2 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U3 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
endmodule
| 6.579407 |
module BLOCKPG_2 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
AND2_X1 U1 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
INV_X1 U2 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U3 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
endmodule
| 7.349652 |
module BLOCKPG_3 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 6.914638 |
module BLOCKPG_4 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 6.766767 |
module BLOCKPG_5 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
AND2_X1 U1 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
INV_X1 U2 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U3 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
endmodule
| 6.706367 |
module BLOCKPG_6 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
AOI21_X1 U1 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
INV_X1 U2 (
.A (n1),
.ZN(gij)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 6.804914 |
module BLOCKPG_7 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 7.056747 |
module BLOCKPG_8 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 7.035015 |
module BLOCKPG_9 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 6.909036 |
module BLOCKPG_10 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 6.9038 |
module BLOCKPG_11 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 6.772201 |
module BLOCKPG_12 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
AOI21_X1 U1 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U2 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
INV_X1 U3 (
.A (n1),
.ZN(gij)
);
endmodule
| 6.898401 |
module BLOCKPG_13 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 7.09307 |
module BLOCKPG_14 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 7.098283 |
module BLOCKPG_15 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 6.896809 |
module BLOCKPG_16 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 7.027928 |
module BLOCKPG_17 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 6.828824 |
module BLOCKPG_18 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 6.864316 |
module BLOCKPG_19 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 6.701137 |
module BLOCKPG_20 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 7.277324 |
module BLOCKPG_21 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 6.872382 |
module BLOCKPG_22 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 6.693136 |
module BLOCKPG_23 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 6.592909 |
module BLOCKPG_24 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 6.862365 |
module BLOCKPG_25 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 6.826138 |
module BLOCKPG_26 (
pik,
gik,
gk_1j,
pk_1j,
gij,
pij
);
input pik;
input gik;
input gk_1j;
input pk_1j;
output gij;
output pij;
// Internal wires
wire n1;
INV_X1 U1 (
.A (n1),
.ZN(gij)
);
AOI21_X1 U2 (
.A (gik),
.B1(gk_1j),
.B2(pik),
.ZN(n1)
);
AND2_X1 U3 (
.A1(pk_1j),
.A2(pik),
.ZN(pij)
);
endmodule
| 6.672245 |
module RCA_NBIT4_0 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_0 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_63 FAI_2 (
.A (A[1]),
.B (B[1]),
.Ci(CTMP[1]),
.S (S[1]),
.Co(CTMP[2])
);
FA_62 FAI_3 (
.A (A[2]),
.B (B[2]),
.Ci(CTMP[2]),
.S (S[2]),
.Co(CTMP[3])
);
FA_61 FAI_4 (
.A (A[3]),
.B (B[3]),
.Ci(CTMP[3]),
.S (S[3]),
.Co(Co)
);
endmodule
| 7.740963 |
module RCA_NBIT4_15 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_60 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_59 FAI_2 (
.A (A[1]),
.B (B[1]),
.Ci(CTMP[1]),
.S (S[1]),
.Co(CTMP[2])
);
FA_58 FAI_3 (
.A (A[2]),
.B (B[2]),
.Ci(CTMP[2]),
.S (S[2]),
.Co(CTMP[3])
);
FA_57 FAI_4 (
.A (A[3]),
.B (B[3]),
.Ci(CTMP[3]),
.S (S[3]),
.Co(Co)
);
endmodule
| 7.949759 |
module FA_4 (
A,
B,
Ci,
S,
Co
);
input A;
input B;
input Ci;
output S;
output Co;
// Internal wires
wire n1;
wire n3;
XOR2_X1 U3 (
.A(Ci),
.B(n3),
.Z(S)
);
XOR2_X1 U4 (
.A(A),
.B(B),
.Z(n3)
);
INV_X1 U1 (
.A (n1),
.ZN(Co)
);
AOI22_X1 U2 (
.A1(B),
.A2(A),
.B1(n3),
.B2(Ci),
.ZN(n1)
);
endmodule
| 6.626139 |
module RCA_NBIT4_1 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_4 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_3 FAI_2 (
.A (A[1]),
.B (B[1]),
.Ci(CTMP[1]),
.S (S[1]),
.Co(CTMP[2])
);
FA_2 FAI_3 (
.A (A[2]),
.B (B[2]),
.Ci(CTMP[2]),
.S (S[2]),
.Co(CTMP[3])
);
FA_1 FAI_4 (
.A (A[3]),
.B (B[3]),
.Ci(CTMP[3]),
.S (S[3]),
.Co(Co)
);
endmodule
| 7.874833 |
module FA_7 (
A,
B,
Ci,
S,
Co
);
input A;
input B;
input Ci;
output S;
output Co;
// Internal wires
wire n1;
wire n3;
XOR2_X1 U3 (
.A(Ci),
.B(n3),
.Z(S)
);
XOR2_X1 U4 (
.A(A),
.B(B),
.Z(n3)
);
INV_X1 U1 (
.A (n1),
.ZN(Co)
);
AOI22_X1 U2 (
.A1(B),
.A2(A),
.B1(n3),
.B2(Ci),
.ZN(n1)
);
endmodule
| 6.624434 |
module FA_8 (
A,
B,
Ci,
S,
Co
);
input A;
input B;
input Ci;
output S;
output Co;
// Internal wires
wire n1;
wire n3;
XOR2_X1 U3 (
.A(Ci),
.B(n3),
.Z(S)
);
XOR2_X1 U4 (
.A(A),
.B(B),
.Z(n3)
);
INV_X1 U1 (
.A (n1),
.ZN(Co)
);
AOI22_X1 U2 (
.A1(B),
.A2(A),
.B1(n3),
.B2(Ci),
.ZN(n1)
);
endmodule
| 6.565071 |
module RCA_NBIT4_2 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_8 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_7 FAI_2 (
.A (A[1]),
.B (B[1]),
.Ci(CTMP[1]),
.S (S[1]),
.Co(CTMP[2])
);
FA_6 FAI_3 (
.A (A[2]),
.B (B[2]),
.Ci(CTMP[2]),
.S (S[2]),
.Co(CTMP[3])
);
FA_5 FAI_4 (
.A (A[3]),
.B (B[3]),
.Ci(CTMP[3]),
.S (S[3]),
.Co(Co)
);
endmodule
| 7.968296 |
module RCA_NBIT4_3 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_12 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_11 FAI_2 (
.A (A[1]),
.B (B[1]),
.Ci(CTMP[1]),
.S (S[1]),
.Co(CTMP[2])
);
FA_10 FAI_3 (
.A (A[2]),
.B (B[2]),
.Ci(CTMP[2]),
.S (S[2]),
.Co(CTMP[3])
);
FA_9 FAI_4 (
.A (A[3]),
.B (B[3]),
.Ci(CTMP[3]),
.S (S[3]),
.Co(Co)
);
endmodule
| 7.787572 |
module RCA_NBIT4_4 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_16 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_15 FAI_2 (
.A (A[1]),
.B (B[1]),
.Ci(CTMP[1]),
.S (S[1]),
.Co(CTMP[2])
);
FA_14 FAI_3 (
.A (A[2]),
.B (B[2]),
.Ci(CTMP[2]),
.S (S[2]),
.Co(CTMP[3])
);
FA_13 FAI_4 (
.A (A[3]),
.B (B[3]),
.Ci(CTMP[3]),
.S (S[3]),
.Co(Co)
);
endmodule
| 7.974063 |
module RCA_NBIT4_5 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_20 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_19 FAI_2 (
.A (A[1]),
.B (B[1]),
.Ci(CTMP[1]),
.S (S[1]),
.Co(CTMP[2])
);
FA_18 FAI_3 (
.A (A[2]),
.B (B[2]),
.Ci(CTMP[2]),
.S (S[2]),
.Co(CTMP[3])
);
FA_17 FAI_4 (
.A (A[3]),
.B (B[3]),
.Ci(CTMP[3]),
.S (S[3]),
.Co(Co)
);
endmodule
| 8.124965 |
module RCA_NBIT4_6 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_24 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_23 FAI_2 (
.A (A[1]),
.B (B[1]),
.Ci(CTMP[1]),
.S (S[1]),
.Co(CTMP[2])
);
FA_22 FAI_3 (
.A (A[2]),
.B (B[2]),
.Ci(CTMP[2]),
.S (S[2]),
.Co(CTMP[3])
);
FA_21 FAI_4 (
.A (A[3]),
.B (B[3]),
.Ci(CTMP[3]),
.S (S[3]),
.Co(Co)
);
endmodule
| 7.931223 |
module CSB_RADIX4_3 (
A,
B,
Ci,
S
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
// Internal wires
wire [3:0] S0;
wire [3:0] S1;
RCA_NBIT4_6 RCA0 (
.A (A),
.B (B),
.Ci(1'b0),
.S (S0)
);
RCA_NBIT4_5 RCA1 (
.A (A),
.B (B),
.Ci(1'b1),
.S (S1)
);
MUX21_GENERIC_NBIT4_3 MUX21_SUM (
.S1 (S1),
.S0 (S0),
.SEL(Ci),
.Y (S)
);
endmodule
| 6.528569 |
module FA_25 (
A,
B,
Ci,
S,
Co
);
input A;
input B;
input Ci;
output S;
output Co;
// Internal wires
wire n1;
wire n3;
XOR2_X1 U3 (
.A(Ci),
.B(n3),
.Z(S)
);
XOR2_X1 U4 (
.A(A),
.B(B),
.Z(n3)
);
INV_X1 U1 (
.A (n1),
.ZN(Co)
);
AOI22_X1 U2 (
.A1(B),
.A2(A),
.B1(n3),
.B2(Ci),
.ZN(n1)
);
endmodule
| 6.590419 |
module RCA_NBIT4_7 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_28 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_27 FAI_2 (
.A (A[1]),
.B (B[1]),
.Ci(CTMP[1]),
.S (S[1]),
.Co(CTMP[2])
);
FA_26 FAI_3 (
.A (A[2]),
.B (B[2]),
.Ci(CTMP[2]),
.S (S[2]),
.Co(CTMP[3])
);
FA_25 FAI_4 (
.A (A[3]),
.B (B[3]),
.Ci(CTMP[3]),
.S (S[3]),
.Co(Co)
);
endmodule
| 7.936123 |
module RCA_NBIT4_8 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_32 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_31 FAI_2 (
.A (A[1]),
.B (B[1]),
.Ci(CTMP[1]),
.S (S[1]),
.Co(CTMP[2])
);
FA_30 FAI_3 (
.A (A[2]),
.B (B[2]),
.Ci(CTMP[2]),
.S (S[2]),
.Co(CTMP[3])
);
FA_29 FAI_4 (
.A (A[3]),
.B (B[3]),
.Ci(CTMP[3]),
.S (S[3]),
.Co(Co)
);
endmodule
| 7.986719 |
module RCA_NBIT4_9 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_36 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_35 FAI_2 (
.A (A[1]),
.B (B[1]),
.Ci(CTMP[1]),
.S (S[1]),
.Co(CTMP[2])
);
FA_34 FAI_3 (
.A (A[2]),
.B (B[2]),
.Ci(CTMP[2]),
.S (S[2]),
.Co(CTMP[3])
);
FA_33 FAI_4 (
.A (A[3]),
.B (B[3]),
.Ci(CTMP[3]),
.S (S[3]),
.Co(Co)
);
endmodule
| 7.787699 |
module RCA_NBIT4_10 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_40 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_39 FAI_2 (
.A (A[1]),
.B (B[1]),
.Ci(CTMP[1]),
.S (S[1]),
.Co(CTMP[2])
);
FA_38 FAI_3 (
.A (A[2]),
.B (B[2]),
.Ci(CTMP[2]),
.S (S[2]),
.Co(CTMP[3])
);
FA_37 FAI_4 (
.A (A[3]),
.B (B[3]),
.Ci(CTMP[3]),
.S (S[3]),
.Co(Co)
);
endmodule
| 7.738482 |
module FA_43 (
A,
B,
Ci,
S,
Co
);
input A;
input B;
input Ci;
output S;
output Co;
// Internal wires
wire n1;
wire n3;
XOR2_X1 U3 (
.A(Ci),
.B(n3),
.Z(S)
);
XOR2_X1 U4 (
.A(A),
.B(B),
.Z(n3)
);
INV_X1 U1 (
.A (n1),
.ZN(Co)
);
AOI22_X1 U2 (
.A1(B),
.A2(A),
.B1(n3),
.B2(Ci),
.ZN(n1)
);
endmodule
| 6.914429 |
module FA_44 (
A,
B,
Ci,
S,
Co
);
input A;
input B;
input Ci;
output S;
output Co;
// Internal wires
wire n1;
wire n3;
XOR2_X1 U3 (
.A(Ci),
.B(n3),
.Z(S)
);
XOR2_X1 U4 (
.A(A),
.B(B),
.Z(n3)
);
INV_X1 U1 (
.A (n1),
.ZN(Co)
);
AOI22_X1 U2 (
.A1(B),
.A2(A),
.B1(n3),
.B2(Ci),
.ZN(n1)
);
endmodule
| 6.871119 |
module RCA_NBIT4_11 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_44 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_43 FAI_2 (
.A (A[1]),
.B (B[1]),
.Ci(CTMP[1]),
.S (S[1]),
.Co(CTMP[2])
);
FA_42 FAI_3 (
.A (A[2]),
.B (B[2]),
.Ci(CTMP[2]),
.S (S[2]),
.Co(CTMP[3])
);
FA_41 FAI_4 (
.A (A[3]),
.B (B[3]),
.Ci(CTMP[3]),
.S (S[3]),
.Co(Co)
);
endmodule
| 7.846434 |
module RCA_NBIT4_12 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_48 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_47 FAI_2 (
.A (A[1]),
.B (B[1]),
.Ci(CTMP[1]),
.S (S[1]),
.Co(CTMP[2])
);
FA_46 FAI_3 (
.A (A[2]),
.B (B[2]),
.Ci(CTMP[2]),
.S (S[2]),
.Co(CTMP[3])
);
FA_45 FAI_4 (
.A (A[3]),
.B (B[3]),
.Ci(CTMP[3]),
.S (S[3]),
.Co(Co)
);
endmodule
| 7.992663 |
module CSB_RADIX4_6 (
A,
B,
Ci,
S
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
// Internal wires
wire [3:0] S0;
wire [3:0] S1;
RCA_NBIT4_12 RCA0 (
.A (A),
.B (B),
.Ci(1'b0),
.S (S0)
);
RCA_NBIT4_11 RCA1 (
.A (A),
.B (B),
.Ci(1'b1),
.S (S1)
);
MUX21_GENERIC_NBIT4_6 MUX21_SUM (
.S1 (S1),
.S0 (S0),
.SEL(Ci),
.Y (S)
);
endmodule
| 6.510462 |
module RCA_NBIT4_13 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_52 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_51 FAI_2 (
.A (A[1]),
.B (B[1]),
.Ci(CTMP[1]),
.S (S[1]),
.Co(CTMP[2])
);
FA_50 FAI_3 (
.A (A[2]),
.B (B[2]),
.Ci(CTMP[2]),
.S (S[2]),
.Co(CTMP[3])
);
FA_49 FAI_4 (
.A (A[3]),
.B (B[3]),
.Ci(CTMP[3]),
.S (S[3]),
.Co(Co)
);
endmodule
| 7.780681 |
module RCA_NBIT4_14 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
// Internal wires
wire [3:1] CTMP;
FA_56 FAI_1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(CTMP[1])
);
FA_55 FAI_2 (
.A (A[1]),
.B (B[1]),
.Ci(CTMP[1]),
.S (S[1]),
.Co(CTMP[2])
);
FA_54 FAI_3 (
.A (A[2]),
.B (B[2]),
.Ci(CTMP[2]),
.S (S[2]),
.Co(CTMP[3])
);
FA_53 FAI_4 (
.A (A[3]),
.B (B[3]),
.Ci(CTMP[3]),
.S (S[3]),
.Co(Co)
);
endmodule
| 7.934078 |
module SUMGEN_NBIT32_RADIX4 (
A,
B,
Ci,
S
);
input [31:0] A;
input [31:0] B;
input [7:0] Ci;
output [31:0] S;
CSB_RADIX4_0 GENi_7 (
.A ({A[31], A[30], A[29], A[28]}),
.B ({B[31], B[30], B[29], B[28]}),
.Ci(Ci[7]),
.S ({S[31], S[30], S[29], S[28]})
);
CSB_RADIX4_7 GENi_6 (
.A ({A[27], A[26], A[25], A[24]}),
.B ({B[27], B[26], B[25], B[24]}),
.Ci(Ci[6]),
.S ({S[27], S[26], S[25], S[24]})
);
CSB_RADIX4_6 GENi_5 (
.A ({A[23], A[22], A[21], A[20]}),
.B ({B[23], B[22], B[21], B[20]}),
.Ci(Ci[5]),
.S ({S[23], S[22], S[21], S[20]})
);
CSB_RADIX4_5 GENi_4 (
.A ({A[19], A[18], A[17], A[16]}),
.B ({B[19], B[18], B[17], B[16]}),
.Ci(Ci[4]),
.S ({S[19], S[18], S[17], S[16]})
);
CSB_RADIX4_4 GENi_3 (
.A ({A[15], A[14], A[13], A[12]}),
.B ({B[15], B[14], B[13], B[12]}),
.Ci(Ci[3]),
.S ({S[15], S[14], S[13], S[12]})
);
CSB_RADIX4_3 GENi_2 (
.A ({A[11], A[10], A[9], A[8]}),
.B ({B[11], B[10], B[9], B[8]}),
.Ci(Ci[2]),
.S ({S[11], S[10], S[9], S[8]})
);
CSB_RADIX4_2 GENi_1 (
.A ({A[7], A[6], A[5], A[4]}),
.B ({B[7], B[6], B[5], B[4]}),
.Ci(Ci[1]),
.S ({S[7], S[6], S[5], S[4]})
);
CSB_RADIX4_1 GENi_0 (
.A ({A[3], A[2], A[1], A[0]}),
.B ({B[3], B[2], B[1], B[0]}),
.Ci(Ci[0]),
.S ({S[3], S[2], S[1], S[0]})
);
endmodule
| 7.221513 |
module P4ADDER_NBIT32 (
A,
B,
Ci,
S,
Co
);
input [31:0] A;
input [31:0] B;
input Ci;
output [31:0] S;
output Co;
// Internal wires
wire [6:0] carry_ST;
SPARSETREE_NBIT32_RADIX4 SPARSETREE0 (
.A (A),
.B (B),
.Ci(Ci),
.Co({Co, carry_ST})
);
SUMGEN_NBIT32_RADIX4 SUMGEN0 (
.A (A),
.B (B),
.Ci({carry_ST, Ci}),
.S (S)
);
endmodule
| 7.085748 |
module adder_signed #(
parameter WIDTH = 16
) (
input [WIDTH-1:0] a,
b,
output [WIDTH-1:0] c
);
assign c = a + b;
//always @(*)
// c = b[WIDTH-1] ? ~c1:c1;
endmodule
| 8.183344 |
module adder_stage (
input clock,
input reset,
input [2:0] a,
input [2:0] b,
output reg [3:0] out
);
wire [3:0] adder_next = $signed({1'b0, a}) + $signed({1'b0, b});
always @(posedge clock) begin
if (reset) begin
out <= 'h0;
end else begin
out <= adder_next;
end
end
endmodule
| 6.931138 |
module adder (A, B, Cin, S, P, G, OVF);
module adder (A, B, Cin, S, OVF);
////////
// IO //
////////
input [31:0] A, B;
input Cin;
// output [31:0] S, P, G;
output [31:0] S;
output OVF;
// P, G
// assign G = A & B; // carry generate
// assign P = A ^ B; // carry propagate
// let the synthesis tools do all the work for the adder
assign S = A + B + Cin;
assign OVF = (A[31] & B[31] & ~S[31]) | (~A[31] & ~B[31] & S[31]);
/*
/////////////////////////////
// Ripple Carry Type Adder //
/////////////////////////////
reg [31:0] carrychain;
wire [32:0] shiftedcarry;
// Carry Chain
always @(*) begin : carry_generation
integer i;
carrychain[0] = G[0] + (P[0] & Cin);
for(i = 1; i <= 31; i = i + 1) begin
carrychain[i] = G[i] + (P[i] & carrychain[i-1]);
end
end
// Sum
assign shiftedcarry = {carrychain,Cin};
assign S = P ^ shiftedcarry[31:0]; // summation
// Overflow
assign OVF = shiftedcarry[32] ^ shiftedcarry[31];
*/
endmodule
| 6.674372 |
module
// Carry Look-Ahead Unit
module CLA (P, G, C, Cout, Pin, Gin, Cin);
// I/O
output [3:0] C;
output Cout, P, G;
input [3:0] Pin, Gin;
input Cin;
assign C[0] = Cin;
assign C[1] = Gin[0] | (Pin[0] & Cin);
assign C[2] = Gin[1] | (Pin[1] & Gin[0]) | (Pin[1] & Pin[0] & Cin);
assign C[3] = Gin[2] | (Pin[2] & Gin[1]) | (Pin[2] & Pin[1] & Gin[0]) | (Pin[2] & Pin[1] & Pin[0] & Cin);
assign Cout = Gin[3] | (Pin[3] & Gin[2]) | (Pin[3] & Pin[2] & Gin[1]) | (Pin[3] & Pin[2] & Pin[1] & Gin[0]) | (Pin[3] & Pin[2] & Pin[1] & Pin[0] & Cin);
assign P = &Pin;
assign G = Gin[3] | (Pin[3]&Gin[2]) | (Pin[3]&Pin[2]& Gin[1]) | (Pin[3]&Pin[2]&Pin[1]&Gin[0]);
endmodule
| 7.63573 |
module adder_subs (
input [3:0] a,
b,
input sel,
output [3:0] s,
output co
);
wire b_in;
mux_4_1_4b mux (
.a (b),
.b (~b),
.sel(sel),
.z (b_in)
);
full_adder_4b fa (
.a (a),
.b (b_in),
.ci(sel),
.s (s)
);
endmodule
| 7.290006 |
module adder_subs_4b (
input [4:0] dato0,
input [4:0] dato1,
input [4:0] dato2,
input [4:0] dato3,
input clk,
output [3:0] segm,
output [3:0] transistor
);
endmodule
| 6.823239 |
module mux_in_time_4x4 (
input [4:0] dato0,
input [4:0] dato1,
input [4:0] dato2,
input [4:0] dato3,
input clk,
output [3:0] segm,
output [3:0] transistor
);
endmodule
| 6.98045 |
module is a 3 bit adder/subtractor.
It will output B - A if desired.
*/
module adder_subtractor_3bit(a, b, want_subtract, c_out, s);
/*
* I/Os
*/
input [2:0] a, b;
input want_subtract; // If want_subtract == 1, we subtract. Otherwise we add.
output [2:0] s;
output c_out;
wire [1:0]c;
wire [2:0]a_adder;
mux_2_1bit m_0( .data0(a[0]), .data1(~a[0]), .sel(want_subtract), .result(a_adder[0]) );
mux_2_1bit m_1( .data0(a[1]), .data1(~a[1]), .sel(want_subtract), .result(a_adder[1]) );
mux_2_1bit m_2( .data0(a[2]), .data1(~a[2]), .sel(want_subtract), .result(a_adder[2]) );
full_adder_1bit a_0( .a(a_adder[0]), .b(b[0]), .c_in(want_subtract), .c_out(c[0]), .s(s[0]) );
full_adder_1bit a_1( .a(a_adder[1]), .b(b[1]), .c_in(c[0]), .c_out(c[1]), .s(s[1]) );
full_adder_1bit a_2( .a(a_adder[2]), .b(b[2]), .c_in(c[1]), .c_out(c_out), .s(s[2]) );
endmodule
| 7.257624 |
module is a 4 bit adder/subtractor.
It will output B - A if desired.
*/
module adder_subtractor_4bit(a, b, want_subtract, c_out, s);
/*
* I/Os
*/
input [3:0] a, b;
input want_subtract; // If want_subtract == 1, we subtract. Otherwise we add.
output [3:0] s;
output c_out;
wire [2:0]c;
wire [3:0]a_adder;
mux_2_1bit m_0( .data0(a[0]), .data1(~a[0]), .sel(want_subtract), .result(a_adder[0]) );
mux_2_1bit m_1( .data0(a[1]), .data1(~a[1]), .sel(want_subtract), .result(a_adder[1]) );
mux_2_1bit m_2( .data0(a[2]), .data1(~a[2]), .sel(want_subtract), .result(a_adder[2]) );
mux_2_1bit m_3( .data0(a[3]), .data1(~a[3]), .sel(want_subtract), .result(a_adder[3]) );
full_adder_1bit a_0( .a(a_adder[0]), .b(b[0]), .c_in(want_subtract), .c_out(c[0]), .s(s[0]) );
full_adder_1bit a_1( .a(a_adder[1]), .b(b[1]), .c_in(c[0]), .c_out(c[1]), .s(s[1]) );
full_adder_1bit a_2( .a(a_adder[2]), .b(b[2]), .c_in(c[1]), .c_out(c[2]), .s(s[2]) );
full_adder_1bit a_3( .a(a_adder[3]), .b(b[3]), .c_in(c[2]), .c_out(c_out), .s(s[3]) );
endmodule
| 7.220341 |
module is a 6 bit adder/subtractor.
It will output B - A if desired.
*/
module adder_subtractor_6bit(a, b, want_subtract, c_out, s);
/*
I/Os
*/
input [5:0] a, b;
input want_subtract; // If want_subtract == 1, we subtract. Otherwise we add.
output [5:0] s;
output c_out;
wire [4:0]c;
wire [5:0]a_adder;
mux_2_1bit m_0( .data0(a[0]), .data1(~a[0]), .sel(want_subtract), .result(a_adder[0]) );
mux_2_1bit m_1( .data0(a[1]), .data1(~a[1]), .sel(want_subtract), .result(a_adder[1]) );
mux_2_1bit m_2( .data0(a[2]), .data1(~a[2]), .sel(want_subtract), .result(a_adder[2]) );
mux_2_1bit m_3( .data0(a[3]), .data1(~a[3]), .sel(want_subtract), .result(a_adder[3]) );
mux_2_1bit m_4( .data0(a[4]), .data1(~a[4]), .sel(want_subtract), .result(a_adder[4]) );
mux_2_1bit m_5( .data0(a[5]), .data1(~a[5]), .sel(want_subtract), .result(a_adder[5]) );
full_adder_1bit a_0( .a(a_adder[0]), .b(b[0]), .c_in(want_subtract), .c_out(c[0]), .s(s[0]) );
full_adder_1bit a_1( .a(a_adder[1]), .b(b[1]), .c_in(c[0]), .c_out(c[1]), .s(s[1]) );
full_adder_1bit a_2( .a(a_adder[2]), .b(b[2]), .c_in(c[1]), .c_out(c[2]), .s(s[2]) );
full_adder_1bit a_3( .a(a_adder[3]), .b(b[3]), .c_in(c[2]), .c_out(c[3]), .s(s[3]) );
full_adder_1bit a_4( .a(a_adder[4]), .b(b[4]), .c_in(c[3]), .c_out(c[4]), .s(s[4]) );
full_adder_1bit a_5( .a(a_adder[5]), .b(b[5]), .c_in(c[4]), .c_out(c_out), .s(s[5]) );
endmodule
| 6.691948 |
module adder_sub_24bit (
in1,
in2,
carry_previous,
sum_bits,
carry_out,
add_sub
);
input wire [23:0] in1, in2;
input wire carry_previous, add_sub;
output wire [23:0] sum_bits;
output wire carry_out;
wire [2:0] temp_carry;
//instantiating three 8 bit adders , previous carry is add_sub signal supplied to first block
adder_sub_8bit a0 (
.in1(in1[7:0]),
.in2(in2[7:0]),
.carry_out(temp_carry[0]),
.sum(sum_bits[7:0]),
.add_sub(add_sub),
.carry_in(carry_previous)
);
adder_sub_8bit a1 (
.in1(in1[14:8]),
.in2(in2[14:8]),
.carry_out(temp_carry[1]),
.sum(sum_bits[7:0]),
.add_sub(add_sub),
.carry_in(temp_carry[0])
);
adder_sub_8bit a2 (
.in1(in1[23:15]),
.in2(in2[23:15]),
.carry_out(temp_carry[1]),
.sum(sum_bits[7:0]),
.add_sub(add_sub),
.carry_in(temp_carry[1])
);
assign carry_out = temp_carry[2];
endmodule
| 6.992766 |
module adder_sub_8bit (
in1,
in2,
carry_out,
sum,
add_sub,
carry_in
);
input wire [7:0] in1, in2;
input wire add_sub, carry_in;
output wire carry_out;
output wire [7:0] sum;
wire [7:0] temp_in2, temp_carry_next;
// Manipulate input 2 for subtraction
xor x7 (temp_in2[7], in2, add_sub);
xor x6 (temp_in2[6], in2, add_sub);
xor x5 (temp_in2[5], in2, add_sub);
xor x4 (temp_in2[4], in2, add_sub);
xor x3 (temp_in2[3], in2, add_sub);
xor x2 (temp_in2[2], in2, add_sub);
xor x1 (temp_in2[1], in2, add_sub);
xor x0 (temp_in2[0], in2, add_sub);
// eight series combination of full adder
adder_1_bit a0 (
.x_current(in1),
.y_current(temp_in2[0]),
.carry_previous(carry_in),
.sum_current(sum[0]),
.next_carry(temp_carry_next[0])
);
adder_1_bit a1 (
.x_current(in1),
.y_current(temp_in2[1]),
.carry_previous(temp_carry_next[0]),
.sum_current(sum[1]),
.next_carry(temp_carry_next[1])
);
adder_1_bit a2 (
.x_current(in1),
.y_current(temp_in2[2]),
.carry_previous(temp_carry_next[1]),
.sum_current(sum[2]),
.next_carry(temp_carry_next[2])
);
adder_1_bit a3 (
.x_current(in1),
.y_current(temp_in2[3]),
.carry_previous(temp_carry_next[2]),
.sum_current(sum[3]),
.next_carry(temp_carry_next[3])
);
adder_1_bit a4 (
.x_current(in1),
.y_current(temp_in2[4]),
.carry_previous(temp_carry_next[3]),
.sum_current(sum[4]),
.next_carry(temp_carry_next[4])
);
adder_1_bit a5 (
.x_current(in1),
.y_current(temp_in2[5]),
.carry_previous(temp_carry_next[4]),
.sum_current(sum[5]),
.next_carry(temp_carry_next[5])
);
adder_1_bit a6 (
.x_current(in1),
.y_current(temp_in2[6]),
.carry_previous(temp_carry_next[5]),
.sum_current(sum[6]),
.next_carry(temp_carry_next[6])
);
adder_1_bit a7 (
.x_current(in1),
.y_current(temp_in2[7]),
.carry_previous(temp_carry_next[6]),
.sum_current(sum[7]),
.next_carry(temp_carry_next[7])
);
assign carry_out = temp_carry_next[7];
endmodule
| 7.635772 |
module adder_switch #(
parameter DATA_TYPE = 32,
parameter NUM_IN = 4,
parameter SEL_IN = 2
) (
clk,
rst,
i_valid, // valid data signal
i_data_bus, // input data bus coming into adder switch
// reconfigurable control signal
i_add_en, // add enable
i_cmd, // command forward
i_sel, // reduction mux select bits
o_vn, // vn output
o_vn_valid, // vn output valid
o_adder // output of the adders (can be sum or forwarding)
);
parameter NUM_OUT = 2;
input clk;
input rst;
input i_valid; // input data valid
input [(DATA_TYPE*NUM_IN)-1:0] i_data_bus; // input data bus to select from
input i_add_en;
input [2:0] i_cmd; // Adder functionality bits
// 000 --> NA
// 001 --> forward both original data (left to left, right to right) - REMOVED bypass regardless
// 010 --> add data and forward to both paths
// 011 --> send left input as VN output and forward right input
// 100 --> send right input as VN output and forward left input
// 101 --> send both inputs as VN outputs
input [SEL_IN-1:0] i_sel; // select bits for the reduction mux
output reg [(2*DATA_TYPE)-1:0] o_vn; // vn output
output reg [1:0] o_vn_valid; // vn output valid
output reg [(DATA_TYPE*NUM_OUT)-1:0] o_adder; // output of the adders (can be sum or forwarding), upper half --> left, lower half --> right
wire [(2 * DATA_TYPE)-1:0] w_sel_data; // selected data from reduction mux
wire [DATA_TYPE-1:0] w_O; // output of adder
reg [(DATA_TYPE*NUM_OUT)-1:0] r_adder;
reg r_add_en;
reg [(2*DATA_TYPE)-1:0] r_vn;
reg [1:0] r_vn_valid;
// generate mux logic to select input data bus values to the two inputs of the adder
reduction_mux #(
.W(DATA_TYPE),
.NUM_IN(NUM_IN),
.SEL_IN(SEL_IN),
.NUM_OUT(NUM_OUT)
) my_reduction_mux (
.i_data(i_data_bus),
.i_sel (i_sel),
.o_data(w_sel_data)
);
// Reconfigurable control logic select
always @(posedge clk) begin
if (rst == 1'b1) begin
r_adder <= 'b0;
r_vn <= 'b0;
r_vn_valid <= 'b0;
end else begin
if (i_valid == 1'b1) begin
case (i_cmd)
3'b000: begin
// NA
r_vn_valid <= 2'b00;
end
3'b001: begin
//forward both original data (left to left, right to right)
r_adder <= w_sel_data;
r_vn_valid <= 2'b00;
end
3'b010: begin
// NA
r_vn_valid <= 2'b00;
end
3'b011: begin
// send left input as VN output and forward right input
r_adder[2*DATA_TYPE-1:DATA_TYPE] <= w_sel_data[2*DATA_TYPE-1:DATA_TYPE];
r_vn[DATA_TYPE-1:0] <= i_data_bus[DATA_TYPE-1:0];
r_vn_valid <= 2'b01;
end
3'b100: begin
// send right input as VN output and forward left input
r_adder[DATA_TYPE-1:0] <= w_sel_data[DATA_TYPE-1:0];
r_vn[2*DATA_TYPE-1:DATA_TYPE] <= i_data_bus[(DATA_TYPE*NUM_IN)-1:DATA_TYPE*(NUM_IN-1)];
r_vn_valid <= 2'b10;
end
3'b101: begin
// send both inputs as VN outputs
r_vn <= w_sel_data;
r_vn_valid <= 2'b11;
end
default: begin
// nothing happens, adder inactive
r_vn_valid <= 2'b00;
end
endcase
end
end
end
// flop i_cmd for timing logic
always @(posedge clk) begin
if (rst == 1'b1) begin
r_add_en <= 'b0;
end else begin
r_add_en <= i_add_en;
end
end
// Flop forwarding values for timing consistency with o_adder timing logic
always @(*) begin
if (rst == 1'b1) begin
o_adder <= 'd0;
o_vn <= 'd0;
o_vn_valid <= 'd0;
end else begin
if (r_add_en == 1'b0) begin
o_adder <= r_adder;
end else begin
o_adder <= {w_O, w_O};
end
o_vn <= r_vn;
o_vn_valid <= r_vn_valid;
end
end
// instantiate FP32 adder
adder32 my_adder (
.clk(clk),
.rst(rst),
.A (w_sel_data[DATA_TYPE+:DATA_TYPE]),
.B (w_sel_data[0+:DATA_TYPE]),
.O (w_O)
);
endmodule
| 8.233951 |
module Adder_Target_Addr (
output reg [31:0] Output,
input [23:0] inputA,
input [31:0] inputB
);
always @(inputA, inputB) begin
// Calculate two's comp;
Output = 32'b00000000000000000000000000000000;
if (inputA[23] == 1) begin
Output[23:0] = ~inputA;
Output = inputB - Output - 1'b1; // ?? +
end else begin
Output = inputA + inputB;
end
end
endmodule
| 6.56098 |
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