code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module adder_128b_tb ();
wire [127:0] out0;
wire out1;
reg [127:0] in0;
reg [127:0] in1;
integer i, file, mem, temp;
adder_128b U0 (
in0,
in1,
out0,
out1
);
initial begin
$display("-- Begining Simulation --");
$dumpfile("./adder_128b.vcd");
$dumpvars(0, adder_128b_tb);
file = $fopen("output.txt", "w");
mem = $fopen("dataset", "r");
in0 = 0;
in1 = 0;
#10
for (i = 0; i < 1000000; i = i + 1) begin
temp = $fscanf(mem, "%h %h \n", in0, in1);
#10 $fwrite(file, "%d\n", {out1, out0});
$display("-- Progress: %d/1000000 --", i + 1);
end
$fclose(file);
$fclose(mem);
$finish;
end
endmodule
| 6.673318 |
module add_12_bit (
input1,
input2,
answer
);
parameter N = 12;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1[0],
input2[0],
answer[0],
carry[0]
);
else
full_adder f (
input1[i],
input2[i],
carry[i-1],
answer[i],
carry[i]
);
end
assign carry_out = carry[N-1];
endgenerate
endmodule
| 7.022223 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_15 (
input x,
input y,
input cin,
output reg s,
output reg cout
);
reg i;
reg j;
reg k;
always @* begin
s = x ^ y ^ cin;
i = x & y;
j = y & cin;
k = x & cin;
cout = i | j | k;
end
endmodule
| 6.826636 |
module adder_16 (
A,
B,
Cin,
O
);
input [15:0] A;
input [15:0] B;
input Cin;
output [16:0] O;
wire [15:0] P;
wire [15:0] G;
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin
prop_gen a (
.a(A[i]),
.b(B[i]),
.P(P[i]),
.G(G[i])
);
end
endgenerate
// Zeroth Layer
wire V;
grey L0 (
.G_i(G[0]),
.P_i(P[0]),
.G_k(Cin),
.G_j(V)
);
// First Layer
wire [7:0] G1;
wire [7:0] P1;
grey L1 (
.G_i(G[1]),
.P_i(P[1]),
.G_k(V),
.G_j(G1[0])
);
black B0 (
.G_i(G[3]),
.P_i(P[3]),
.G_k(G[2]),
.P_k(P[2]),
.G_j(G1[1]),
.P_j(P1[1])
);
black B1 (
.G_i(G[5]),
.P_i(P[5]),
.G_k(G[4]),
.P_k(P[4]),
.G_j(G1[2]),
.P_j(P1[2])
);
black B2 (
.G_i(G[7]),
.P_i(P[7]),
.G_k(G[6]),
.P_k(P[6]),
.G_j(G1[3]),
.P_j(P1[3])
);
black B3 (
.G_i(G[9]),
.P_i(P[9]),
.G_k(G[8]),
.P_k(P[8]),
.G_j(G1[4]),
.P_j(P1[4])
);
black B4 (
.G_i(G[11]),
.P_i(P[11]),
.G_k(G[10]),
.P_k(P[10]),
.G_j(G1[5]),
.P_j(P1[5])
);
black B5 (
.G_i(G[13]),
.P_i(P[13]),
.G_k(G[12]),
.P_k(P[12]),
.G_j(G1[6]),
.P_j(P1[6])
);
black B6 (
.G_i(G[15]),
.P_i(P[15]),
.G_k(G[14]),
.P_k(P[14]),
.G_j(G1[7]),
.P_j(P1[7])
);
//Second Layer
wire [3:0] G2;
wire [3:0] P2;
grey L2 (
.G_i(G1[1]),
.P_i(P1[1]),
.G_k(G1[0]),
.G_j(G2[0])
);
black B7 (
.G_i(G1[3]),
.P_i(P1[3]),
.G_k(G1[2]),
.P_k(P1[2]),
.G_j(G2[1]),
.P_j(P2[1])
);
black B8 (
.G_i(G1[5]),
.P_i(P1[5]),
.G_k(G1[4]),
.P_k(P1[4]),
.G_j(G2[2]),
.P_j(P2[2])
);
black B9 (
.G_i(G1[7]),
.P_i(P1[7]),
.G_k(G1[6]),
.P_k(P1[6]),
.G_j(G2[3]),
.P_j(P2[3])
);
//Third Layer
wire [1:0] G3;
wire [1:0] P3;
grey L3 (
.G_i(G2[1]),
.P_i(P2[1]),
.G_k(G2[0]),
.G_j(G3[0])
);
black B10 (
.G_i(G2[3]),
.P_i(P2[3]),
.G_k(G2[2]),
.P_k(P2[2]),
.G_j(G3[1]),
.P_j(P3[1])
);
//Fourth Layer
wire G4;
grey L4 (
.G_i(G3[1]),
.P_i(P3[1]),
.G_k(G3[0]),
.G_j(G4)
);
//Fifth Layer
wire G5;
grey L5 (
.G_i(G2[2]),
.P_i(P2[2]),
.G_k(G3[0]),
.G_j(G5)
);
//Sixth Layer
wire [2:0] G6;
grey L6 (
.G_i(G1[2]),
.P_i(P1[2]),
.G_k(G2[0]),
.G_j(G6[0])
);
grey L7 (
.G_i(G1[4]),
.P_i(P1[4]),
.G_k(G3[0]),
.G_j(G6[1])
);
grey L8 (
.G_i(G1[6]),
.P_i(P1[6]),
.G_k(G5),
.G_j(G6[2])
);
//Seventh Layer
wire [15:0] X;
assign X[0] = V;
assign X[1] = G1[0];
grey L9 (
.G_i(G[2]),
.P_i(P[2]),
.G_k(G1[0]),
.G_j(X[2])
);
assign X[3] = G2[0];
grey L10 (
.G_i(G[4]),
.P_i(P[4]),
.G_k(G2[0]),
.G_j(X[4])
);
assign X[5] = G6[0];
grey L11 (
.G_i(G[6]),
.P_i(P[6]),
.G_k(G6[0]),
.G_j(X[6])
);
assign X[7] = G3[0];
grey L12 (
.G_i(G[8]),
.P_i(P[8]),
.G_k(G3[0]),
.G_j(X[8])
);
assign X[9] = G6[1];
grey L13 (
.G_i(G[10]),
.P_i(P[10]),
.G_k(G6[1]),
.G_j(X[10])
);
assign X[11] = G5;
grey L14 (
.G_i(G[12]),
.P_i(P[12]),
.G_k(G5),
.G_j(X[12])
);
assign X[13] = G6[2];
grey L15 (
.G_i(G[14]),
.P_i(P[14]),
.G_k(G6[2]),
.G_j(X[14])
);
assign X[15] = G4;
//Sum Layer
xor T0 (O[0], P[0], Cin);
xor T1 (O[1], P[1], X[0]);
xor T2 (O[2], P[2], X[1]);
xor T3 (O[3], P[3], X[2]);
xor T4 (O[4], P[4], X[3]);
xor T5 (O[5], P[5], X[4]);
xor T6 (O[6], P[6], X[5]);
xor T7 (O[7], P[7], X[6]);
xor T8 (O[8], P[8], X[7]);
xor T9 (O[9], P[9], X[8]);
xor T10 (O[10], P[10], X[9]);
xor T11 (O[11], P[11], X[10]);
xor T12 (O[12], P[12], X[11]);
xor T13 (O[13], P[13], X[12]);
xor T14 (O[14], P[14], X[13]);
xor T15 (O[15], P[15], X[14]);
assign O[16] = X[15];
endmodule
| 7.110663 |
module Adder_16bit (
input [15:0] A,
input [15:0] B,
output CarryOut,
output [15:0] Result
);
wire [14:0] COUT;
Adder_1bit adder16bit_0 (
A[0],
B[0],
0,
Result[0],
COUT[0]
);
Adder_1bit adder16bit_1 (
A[1],
B[1],
COUT[0],
Result[1],
COUT[1]
);
Adder_1bit adder16bit_2 (
A[2],
B[2],
COUT[1],
Result[2],
COUT[2]
);
Adder_1bit adder16bit_3 (
A[3],
B[3],
COUT[2],
Result[3],
COUT[3]
);
Adder_1bit adder16bit_4 (
A[4],
B[4],
COUT[3],
Result[4],
COUT[4]
);
Adder_1bit adder16bit_5 (
A[5],
B[5],
COUT[4],
Result[5],
COUT[5]
);
Adder_1bit adder16bit_6 (
A[6],
B[6],
COUT[5],
Result[6],
COUT[6]
);
Adder_1bit adder16bit_7 (
A[7],
B[7],
COUT[6],
Result[7],
COUT[7]
);
Adder_1bit adder16bit_8 (
A[8],
B[8],
COUT[7],
Result[8],
COUT[8]
);
Adder_1bit adder16bit_9 (
A[9],
B[9],
COUT[8],
Result[9],
COUT[9]
);
Adder_1bit adder16bit_10 (
A[10],
B[10],
COUT[9],
Result[10],
COUT[10]
);
Adder_1bit adder16bit_11 (
A[11],
B[11],
COUT[10],
Result[11],
COUT[11]
);
Adder_1bit adder16bit_12 (
A[12],
B[12],
COUT[11],
Result[12],
COUT[12]
);
Adder_1bit adder16bit_13 (
A[13],
B[13],
COUT[12],
Result[13],
COUT[13]
);
Adder_1bit adder16bit_14 (
A[14],
B[14],
COUT[13],
Result[14],
COUT[14]
);
Adder_1bit adder16bit_15 (
A[15],
B[15],
COUT[14],
Result[15],
CarryOut
);
endmodule
| 7.160367 |
module adder_16bits (
a,
b,
ci,
s,
co
);
input [15 : 0] a;
input [15 : 0] b;
input ci;
output [15 : 0] s;
output co;
wire [2 : 0] c;
adder_4bits adder_4bits_inst (
.a (a[3 : 0]),
.b (b[3 : 0]),
.ci(ci),
.s (s[3 : 0]),
.co(c[0])
);
mux_adder_4bits mux_adder_4bits_inst1 (
.a (a[7 : 4]),
.b (b[7 : 4]),
.ci(c[0]),
.s (s[7 : 4]),
.co(c[1])
);
mux_adder_4bits mux_adder_4bits_inst2 (
.a (a[11 : 8]),
.b (b[11 : 8]),
.ci(c[1]),
.s (s[11 : 8]),
.co(c[2])
);
mux_adder_4bits mux_adder_4bits_inst3 (
.a (a[15 : 12]),
.b (b[15 : 12]),
.ci(c[2]),
.s (s[15 : 12]),
.co(co)
);
endmodule
| 7.525748 |
module adder_nbit_BIT_WIDTH16 (
a,
b,
carry_in,
sum,
overflow
);
input [15:0] a;
input [15:0] b;
output [15:0] sum;
input carry_in;
output overflow;
wire [15:1] carrys;
adder_1bit_15 \genblk1[0].IX (
.a(a[0]),
.b(b[0]),
.carry_in(carry_in),
.sum(sum[0]),
.carry_out(carrys[1])
);
adder_1bit_14 \genblk1[1].IX (
.a(a[1]),
.b(b[1]),
.carry_in(carrys[1]),
.sum(sum[1]),
.carry_out(carrys[2])
);
adder_1bit_13 \genblk1[2].IX (
.a(a[2]),
.b(b[2]),
.carry_in(carrys[2]),
.sum(sum[2]),
.carry_out(carrys[3])
);
adder_1bit_12 \genblk1[3].IX (
.a(a[3]),
.b(b[3]),
.carry_in(carrys[3]),
.sum(sum[3]),
.carry_out(carrys[4])
);
adder_1bit_11 \genblk1[4].IX (
.a(a[4]),
.b(b[4]),
.carry_in(carrys[4]),
.sum(sum[4]),
.carry_out(carrys[5])
);
adder_1bit_10 \genblk1[5].IX (
.a(a[5]),
.b(b[5]),
.carry_in(carrys[5]),
.sum(sum[5]),
.carry_out(carrys[6])
);
adder_1bit_9 \genblk1[6].IX (
.a(a[6]),
.b(b[6]),
.carry_in(carrys[6]),
.sum(sum[6]),
.carry_out(carrys[7])
);
adder_1bit_8 \genblk1[7].IX (
.a(a[7]),
.b(b[7]),
.carry_in(carrys[7]),
.sum(sum[7]),
.carry_out(carrys[8])
);
adder_1bit_7 \genblk1[8].IX (
.a(a[8]),
.b(b[8]),
.carry_in(carrys[8]),
.sum(sum[8]),
.carry_out(carrys[9])
);
adder_1bit_6 \genblk1[9].IX (
.a(a[9]),
.b(b[9]),
.carry_in(carrys[9]),
.sum(sum[9]),
.carry_out(carrys[10])
);
adder_1bit_5 \genblk1[10].IX (
.a(a[10]),
.b(b[10]),
.carry_in(carrys[10]),
.sum(sum[10]),
.carry_out(carrys[11])
);
adder_1bit_4 \genblk1[11].IX (
.a(a[11]),
.b(b[11]),
.carry_in(carrys[11]),
.sum(sum[11]),
.carry_out(carrys[12])
);
adder_1bit_3 \genblk1[12].IX (
.a(a[12]),
.b(b[12]),
.carry_in(carrys[12]),
.sum(sum[12]),
.carry_out(carrys[13])
);
adder_1bit_2 \genblk1[13].IX (
.a(a[13]),
.b(b[13]),
.carry_in(carrys[13]),
.sum(sum[13]),
.carry_out(carrys[14])
);
adder_1bit_1 \genblk1[14].IX (
.a(a[14]),
.b(b[14]),
.carry_in(carrys[14]),
.sum(sum[14]),
.carry_out(carrys[15])
);
adder_1bit_0 \genblk1[15].IX (
.a(a[15]),
.b(b[15]),
.carry_in(carrys[15]),
.sum(sum[15]),
.carry_out(overflow)
);
endmodule
| 6.79806 |
module adder_16bit (
a,
b,
carry_in,
sum,
overflow
);
input [15:0] a;
input [15:0] b;
output [15:0] sum;
input carry_in;
output overflow;
adder_nbit_BIT_WIDTH16 AX (
.a(a),
.b(b),
.carry_in(carry_in),
.sum(sum),
.overflow(overflow)
);
endmodule
| 7.133988 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_16 (
a,
b,
carry_in,
sum,
overflow
);
input [15:0] a;
input [15:0] b;
output [15:0] sum;
input carry_in;
output overflow;
adder_16_DW01_add_0 r304 (
.A ({1'b0, a}),
.B ({1'b0, b}),
.CI (carry_in),
.SUM({overflow, sum})
);
endmodule
| 7.110663 |
module adder_16_bit (
input [15:0] A,
input [15:0] B,
output reg [15:0] R
);
always @* R = A + B;
endmodule
| 7.596403 |
module adder_16_bit_tb;
// Inputs
reg [15:0] A;
reg [15:0] B;
// Outputs
wire [15:0] R;
// Instantiate the Unit Under Test (UUT)
adder_16_bit uut (
.A(A),
.B(B),
.R(R)
);
initial begin
// Initialize Inputs
A = 0;
B = 0;
// Wait 100 ns for global reset to finish
#100;
A = -20;
B = -20;
repeat (40) begin
repeat (40) begin
A = A + 1;
#1;
if (A + B == R) begin
$display("PASS");
end else begin
$display("FAIL: %d + %d = %d", A, B, R);
end
#5;
end
A = -20;
B = B + 1;
#5;
end
end
endmodule
| 7.045454 |
module adder_16_test ();
/* Make a reset that pulses once. */
wire [15:0] sum;
wire cout;
reg [15:0] a;
reg [15:0] b;
reg c_in;
adder_16 l_m_RC_CLA_0 (
.sum (sum),
.c_out(cout),
.a (a),
.b (b),
.c_in (c_in)
);
initial begin
$dumpfile("adder_16_test.vcd");
$dumpvars(0, adder_16_test);
a = 4;
b = 3;
c_in = 0;
#100;
c_in = 1;
#100;
a = 8;
b = 7;
#100;
a = 1025;
b = 255;
#100;
$finish();
end
initial $monitor("At time %t, sum = %h (%0d), cout = %h (%0d)", $time, sum, sum, cout, cout);
endmodule
| 6.582509 |
module adder_17 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn_signal,
output reg [15:0] out,
output reg [0:0] z,
output reg [0:0] v,
output reg [0:0] n
);
reg [15:0] s;
always @* begin
s = 16'h0000;
case (alufn_signal[0+0-:1])
1'h0: begin
s = a + b;
end
1'h1: begin
s = a - b;
end
default: begin
s = 16'h0000;
end
endcase
n = s[15+0-:1];
v = (a[15+0-:1] & (b[15+0-:1] ^ alufn_signal[0+0-:1]) & !s[15+0-:1]) | (!a[15+0-:1] & !(b[15+0-:1] ^ alufn_signal[0+0-:1]) & s[15+0-:1]);
z = ~(|s);
out = s;
end
endmodule
| 7.216158 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_1b (
a,
b,
cin,
cout,
sum
);
input a, b, cin;
output cout, sum;
/** Cálculo do CarryOut **/
//CarryOut = (b.CarryIn) + (a.CarryIn) + (b.a)
wire and_cout1_out, and_cout2_out, and_cout3_out;
and and_cout1 (and_cout1_out, b, cin);
and and_cout2 (and_cout2_out, a, cin);
and and_cout3 (and_cout3_out, a, b);
or cout_or (cout, and_cout1_out, and_cout2_out, and_cout3_out);
/** Cálculo da soma **/
//Sum = (a.-b.-CarryIn) + (-a.b.-CarryIn) + (-a.-b.CarryIn) + (a.b.CarryIn)
wire and_sum1_out, and_sum2_out, and_sum3_out, and_sum4_out;
wire not_a_out, not_b_out, not_cin_out;
not not_a (not_a_out, a);
not not_b (not_b_out, b);
not not_cin (not_cin_out, cin);
and and_sum1 (and_sum1_out, a, not_b_out, not_cin_out);
and and_sum2 (and_sum2_out, not_a_out, b, not_cin_out);
and and_sum3 (and_sum3_out, not_a_out, not_b_out, cin);
and and_sum4 (and_sum4_out, a, b, cin);
or big_or (sum, and_sum1_out, and_sum2_out, and_sum3_out, and_sum4_out);
//
endmodule
| 7.284049 |
module adder_1_bit (
input A,
input B,
input Cin,
output S,
output Cout
);
assign S = A ^ B ^ Cin;
assign Cout = (A & B) | (B & Cin) | (Cin & A);
endmodule
| 6.744845 |
module adder_1_bit_board (
input [2:0] SW,
output [1:0] LEDR
);
adder_1_bit ex1 (
SW[0],
SW[1],
SW[2],
LEDR[0],
LEDR[1]
);
endmodule
| 8.378088 |
module adder_1_bit_primitive (
input a,
b,
cin,
output s,
cout
);
wire x, y, z;
xor (x, a, b);
xor (s, x, cin);
and (y, x, cin);
and (z, a, b);
or (cout, y, z);
endmodule
| 7.054475 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_21 (
input x,
input y,
input cin,
output reg s,
output reg cout
);
reg i;
reg j;
reg k;
always @* begin
s = x ^ y ^ cin;
i = x & y;
j = y & cin;
k = x & cin;
cout = i | j | k;
end
endmodule
| 7.009905 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_27 (
input x,
input y,
input cin,
output reg s,
output reg cout
);
reg i;
reg j;
reg k;
always @* begin
s = x ^ y ^ cin;
i = x & y;
j = y & cin;
k = x & cin;
cout = i | j | k;
end
endmodule
| 6.528538 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_2bit (
A,
B,
S,
cout
);
input [1:0] A;
input [1:0] B;
output [1:0] S;
output cout;
wire cin;
fullAdder FA0 (
A[0],
B[0],
1'b0,
S[0],
cin
);
fullAdder FA1 (
A[1],
B[1],
cin,
S[1],
cout
);
endmodule
| 6.761888 |
module adder_2bits (
input Cin,
input A,
input B,
input select,
output Sum,
output Cout
);
// First we choose the selected B
wire b_result;
xor #(10) import_select (b_result, B, select);
// Then we give all the selections into full adder
full_adder add_2_bit (
Cin,
A,
b_result,
Sum,
Cout
);
endmodule
| 7.566682 |
module adder_2bits_non_delay (
input Cin,
input A,
input B,
input select,
output Sum,
output Cout
);
// First we choose the selected B
wire b_result;
xor import_select (b_result, B, select);
// Then we give all the selections into full adder
full_adder_non_delay add_2_bit (
Cin,
A,
b_result,
Sum,
Cout
);
endmodule
| 7.756499 |
module adder_2in (
in1,
in2,
out
);
input wire [7:0] in1, in2;
output wire [8:0] out;
assign out = in1 + in2;
endmodule
| 8.07843 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder32 (
A,
B,
S,
C31
);
input [31:0] A;
input [31:0] B;
output [31:0] S;
output C31;
wire px1, gx1, px2, gx2;
wire c15;
CLA_16 CLA1 (
.A (A[15:0]),
.B (B[15:0]),
.cin(0),
.S (S[15:0]),
.px (px1),
.gx (gx1)
);
CLA_16 CLA2 (
.A (A[31:16]),
.B (B[31:16]),
.cin(c15),
.S (S[31:16]),
.px (px2),
.gx (gx2)
);
assign c15 = gx1 | (px1 && 0), //c0 = 0
C31 = gx2 | (px2 && c15);
endmodule
| 8.194085 |
module adder_32b (
input [31:0] A,
input [31:0] B,
output [31:0] R
);
wire [32:0] R_tmp;
assign R_tmp = A + B;
assign R = R_tmp[31:0];
endmodule
| 6.868313 |
module adder_32bit (
cfinal,
sum,
num1,
num2,
cin
);
input [31:0] num1, num2;
input cin;
output [31:0] sum;
output cfinal;
wire cout[3:0];
ADDER_8bit add1 (
cout[0],
sum[7:0],
num1[7:0],
num2[7:0],
cin
);
ADDER_8bit add2 (
cout[1],
sum[15:8],
num1[15:8],
num2[15:8],
cout[0]
);
ADDER_8bit add3 (
cout[2],
sum[23:16],
num1[23:16],
num2[23:16],
cout[1]
);
ADDER_8bit add4 (
cout[3],
sum[31:24],
num1[31:24],
num2[31:24],
cout[2]
);
assign cfinal = cout[2];
endmodule
| 6.670207 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module thirtytwo_bit_Recursive_Carry_Adder (
output [31:0] sum,
output cout,
input [31:0] a,
b,
input clk
);
wire cin = 1'b0;
wire [31:0] c, g, p;
kgpchoose kgp[31:0] (
g,
p,
a,
b
);
wire [31:1] g2, p2;
buff buff_0 (
c[0],
g[0]
);
calcblock calc_1[31:1] (
g2[31:1],
p2[31:1],
g[31:1],
p[31:1],
g[30:0],
p[30:0]
);
wire [31:0] c_1, g_1, p_1, a_1, b_1;
wire [31:1] g2_1, p2_1;
dff df10[31:0] (
g,
clk,
1'b0,
g_1
);
dff df11[31:0] (
p,
clk,
1'b0,
p_1
);
//dff df12[31:0](a,clk,1'b0,a_1);
//dff df13[31:0](b,clk,1'b0,b_1);
dff df14[31:0] (
c,
clk,
1'b0,
c_1
);
dff df15[31:1] (
g2,
clk,
1'b0,
g2_1
);
dff df16[31:1] (
p2,
clk,
1'b0,
p2_1
);
wire cin_1;
dff df1 (
cin,
clk,
1'b0,
cin_1
);
wire [31:2] g3, p3;
buff buff_1 (
c_1[1],
g2_1[1]
);
calcblock calc_2[31:2] (
g3[31:2],
p3[31:2],
g2_1[31:2],
p2_1[31:2],
{g2_1[29:1], g_1[0]},
{p2_1[29:1], p_1[0]}
);
wire [31:0] c_2, g_2, p_2, a_2, b_2;
wire [31:1] g2_2, p2_2;
wire [31:2] g3_2, p3_2;
dff df20[31:0] (
g_1,
clk,
1'b0,
g_2
);
dff df21[31:0] (
p_1,
clk,
1'b0,
p_2
);
//dff df22[31:0](a_1,clk,1'b0,a_2);
//dff df23[31:0](b_1,clk,1'b0,b_2);
dff df24[31:0] (
c_1,
clk,
1'b0,
c_2
);
dff df25[31:1] (
g2_1,
clk,
1'b0,
g2_2
);
dff df26[31:1] (
p2_1,
clk,
1'b0,
p2_2
);
dff df27[31:2] (
g3,
clk,
1'b0,
g3_2
);
dff df28[31:2] (
p3,
clk,
1'b0,
p3_2
);
wire cin_2;
dff df2 (
cin_1,
clk,
1'b0,
cin_2
);
wire [31:4] g4, p4;
buff buff_2[3:2] (
c_2[3:2],
g3_2[3:2]
);
calcblock calc_3[31:4] (
g4[31:4],
p4[31:4],
g3_2[31:4],
p3_2[31:4],
{g3_2[27:2], g2_2[1], g_2[0]},
{p3_2[27:2], p2_2[1], p_2[0]}
);
wire [31:0] c_3, g_3, p_3, a_3, b_3;
wire [31:1] g2_3, p2_3;
wire [31:2] g3_3, p3_3;
wire [31:4] g4_3, p4_3;
dff df30[31:0] (
g_2,
clk,
1'b0,
g_3
);
dff df31[31:0] (
p_2,
clk,
1'b0,
p_3
);
//dff df32[31:0](a_2,clk,1'b0,a_3);
//dff df33[31:0](b_2,clk,1'b0,b_3);
dff df34[31:0] (
c_2,
clk,
1'b0,
c_3
);
dff df35[31:1] (
g2_2,
clk,
1'b0,
g2_3
);
dff df36[31:1] (
p2_2,
clk,
1'b0,
p2_3
);
dff df37[31:2] (
g3_2,
clk,
1'b0,
g3_3
);
dff df38[31:2] (
p3_2,
clk,
1'b0,
p3_3
);
dff df39[31:4] (
g4,
clk,
1'b0,
g4_3
);
dff df310[31:4] (
p4,
clk,
1'b0,
p4_3
);
wire cin_3;
dff df3 (
cin_2,
clk,
1'b0,
cin_3
);
wire [31:8] g5, p5;
buff buff_3[7:4] (
c_3[7:4],
g4_3[7:4]
);
calcblock calc_4[31:8] (
g5[31:8],
p5[31:8],
g4_3[31:8],
p4_3[31:8],
{g4_3[23:4], g3_3[3:2], g2_3[1], g_3[0]},
{p4_3[23:4], p3_3[3:2], p2_3[1], p_3[0]}
);
wire [31:0] c_4, g_4, p_4, a_4, b_4;
wire [31:1] g2_4, p2_4;
wire [31:2] g3_4, p3_4;
wire [31:4] g4_4, p4_4;
wire [31:8] g5_4, p5_4;
dff df40[31:0] (
g_3,
clk,
1'b0,
g_4
);
dff df41[31:0] (
p_3,
clk,
1'b0,
p_4
);
//dff df42[31:0](a_3,clk,1'b0,a_4);
//dff df43[31:0](b_3,clk,1'b0,b_4);
dff df44[31:0] (
c_3,
clk,
1'b0,
c_4
);
dff df45[31:1] (
g2_3,
clk,
1'b0,
g2_4
);
dff df46[31:1] (
p2_3,
clk,
1'b0,
p2_4
);
dff df47[31:2] (
g3_3,
clk,
1'b0,
g3_4
);
dff df48[31:2] (
p3_3,
clk,
1'b0,
p3_4
);
dff df49[31:4] (
g4_3,
clk,
1'b0,
g4_4
);
dff df410[31:4] (
p4_3,
clk,
1'b0,
p4_4
);
dff df411[31:8] (
g5,
clk,
1'b0,
g5_4
);
dff df412[31:8] (
p5,
clk,
1'b0,
p5_4
);
wire cin_4;
dff df4 (
cin_3,
clk,
1'b0,
cin_4
);
wire [31:16] g6, p6;
buff buff_4[15:8] (
c_4[15:8],
g5_4[15:8]
);
calcblock calc_5[31:16] (
g6[31:16],
p6[31:16],
g5_4[31:16],
p5_4[31:16],
{g5_4[15:8], g4_4[7:4], g3_4[3:2], g2_4[1], g_4[0]},
{p5_4[15:8], p4_4[7:4], p3_4[3:2], p2_4[1], p_4[0]}
);
wire [31:0] c_5, g_5, p_5, a_5, b_5;
wire [31:1] g2_5, p2_5;
wire [31:2] g3_5, p3_5;
wire [31:4] g4_5, p4_5;
wire [31:8] g5_5, p5_5;
wire [31:16] g6_5, p6_5;
dff df50[31:0] (
g_4,
clk,
1'b0,
g_5
);
dff df51[31:0] (
p_4,
clk,
1'b0,
p_5
);
//dff df52[31:0](a_4,clk,1'b0,a_5);
//dff df53[31:0](b_4,clk,1'b0,b_5);
dff df54[31:0] (
c_4,
clk,
1'b0,
c_5
);
dff df55[31:1] (
g2_4,
clk,
1'b0,
g2_5
);
dff df56[31:1] (
p2_4,
clk,
1'b0,
p2_5
);
dff df57[31:2] (
g3_4,
clk,
1'b0,
g3_5
);
dff df58[31:2] (
p3_4,
clk,
1'b0,
p3_5
);
dff df59[31:4] (
g4_4,
clk,
1'b0,
g4_5
);
dff df510[31:4] (
p4_4,
clk,
1'b0,
p4_5
);
dff df511[31:8] (
g5_4,
clk,
1'b0,
g5_5
);
dff df512[31:8] (
p5_4,
clk,
1'b0,
p5_5
);
dff df513[31:16] (
g6,
clk,
1'b0,
g6_5
);
dff df514[31:16] (
p6,
clk,
1'b0,
p6_5
);
wire cin_5;
dff df5 (
cin_4,
clk,
1'b0,
cin_5
);
buff buff_5[31:16] (
c_5[31:16],
g6_5[31:16]
);
finaladder adder_0 (
sum[0],
p_5[0],
cin_5
);
finaladder addr_1[31:1] (
sum[31:1],
p_5[31:1],
c_5[30:0]
);
buf (cout, c_5[31]);
endmodule
| 6.696784 |
module finaladderr (
output Si,
input ai,
bi,
Ci
);
wire w;
xor (w, ai, bi);
xor (Si, w, Ci);
endmodule
| 7.712775 |
module calcblock (
output G,
P,
input Gi,
Pi,
Gip,
Pip
);
wire w;
and (w, Pi, Gip);
or (G, w, Gi);
and (P, Pi, Pip);
endmodule
| 8.025708 |
module dff (
d,
clk,
clear,
q
);
input d, clk, clear;
output reg q;
always @(posedge clk) begin
if (clear == 1) q <= 0;
else q <= d;
//$display("%d\n",$time);
end
endmodule
| 7.361383 |
module Adder_32_Bits #(
parameter NBits = 32
) (
input [NBits-1:0] Data0,
input [NBits-1:0] Data1,
output [NBits-1:0] Result
);
assign Result = Data1 + Data0;
endmodule
| 9.431841 |
module adder_34 (
input [7:0] a,
input [7:0] b,
input alufn,
output reg [7:0] out,
output reg z,
output reg v,
output reg n
);
reg [7:0] outp;
always @* begin
case (alufn)
1'h0: begin
outp = a + b;
end
1'h1: begin
outp = a - b;
end
default: begin
outp = 1'h0;
end
endcase
case (outp[7+0-:1])
1'h1: begin
n = 1'h1;
end
1'h0: begin
n = 1'h0;
end
default: begin
n = 1'h0;
end
endcase
if (outp == 8'h00) begin
z = 1'h1;
end else begin
z = 1'h0;
end
v = a[7+0-:1] & (b[7+0-:1] ^ alufn) & (~outp[7+0-:1]) | (~a[7+0-:1]) & (~b[7+0-:1] ^ alufn) & outp[7+0-:1];
out = outp;
end
endmodule
| 6.796745 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_3bit (
A,
B,
S,
cout
);
input [2:0] A;
input [2:0] B;
output [2:0] S;
output cout;
wire [2:1] cin;
fullAdder FA0 (
A[0],
B[0],
1'b0,
S[0],
cin[1]
);
fullAdder FA1 (
A[1],
B[1],
cin[1],
S[1],
cin[2]
);
fullAdder FA2 (
A[2],
B[2],
cin[2],
S[2],
cout
);
endmodule
| 6.908683 |
module adder_3in (
i_a,
i_b,
i_c,
o
);
// parameters
parameter DWIDTH = 32;
parameter FRAC = 24;
// input ports
input signed [DWIDTH-1:0] i_a, i_b, i_c;
// output ports
output signed [DWIDTH-1:0] o;
// adding i_a, i_b, and i_c
assign o = i_a + i_b + i_c;
endmodule
| 8.457397 |
module adder_4 (
x,
y,
cin,
c3,
F,
Gm,
Pm
);
input [3:0] x;
input [3:0] y;
input cin;
output c3, Gm, Pm;
output [3:0] F;
wire p0, p1, p2, p3, g0, g1, g2, g3;
wire c0, c1, c2;
adder adder1 (
.X(x[0]),
.Y(y[0]),
.Cin(cin),
.F(F[0]),
.Cout()
);
adder adder2 (
.X(x[1]),
.Y(y[1]),
.Cin(c0),
.F(F[1]),
.Cout()
);
adder adder3 (
.X(x[2]),
.Y(y[2]),
.Cin(c1),
.F(F[2]),
.Cout()
);
adder adder4 (
.X(x[3]),
.Y(y[3]),
.Cin(c2),
.F(F[3]),
.Cout()
);
CLA CLA (
.cin(cin),
.c0 (c0),
.c1 (c1),
.c2 (c2),
.c3 (c3),
.p0 (p0),
.p1 (p1),
.p2 (p2),
.p3 (p3),
.g0 (g0),
.g1 (g1),
.g2 (g2),
.g3 (g3)
);
assign p0 = x[0] | y[0], p1 = x[1] | y[1], p2 = x[2] | y[2], p3 = x[3] | y[3];
assign g0 = x[0] & y[0], g1 = x[1] & y[1], g2 = x[2] & y[2], g3 = x[3] & y[3];
assign Pm = p0 & p1 & p2 & p3, Gm = g3 | (p3 & g2) | (p3 & p2 & g1) | (p3 & p2 & p1 & g0);
endmodule
| 7.763613 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_4b (
sum,
c_out,
a,
b,
c_in
);
input [3:0] a, b;
input c_in;
output [3:0] sum;
output c_out;
wire acarreo0, acarreo1, acarreo2;
full_adder_v1 fa0 (
a[0],
b[0],
c_in,
sum[0],
acarreo0
);
full_adder_v1 fa1 (
a[1],
b[1],
acarreo0,
sum[1],
acarreo1
);
full_adder_v1 fa2 (
a[2],
b[2],
acarreo1,
sum[2],
acarreo2
);
full_adder_v1 fa3 (
a[3],
b[3],
acarreo2,
sum[3],
c_out
);
endmodule
| 6.885487 |
module adder_4bit (
S,
Cout,
A,
B,
Cin
);
output reg [3:0] S;
output reg Cout;
input [3:0] A, B;
input Cin;
always {Cout, S} = A + B + Cin;
endmodule
| 9.041993 |
module adder_4bits (
input [3:0] a,
input [3:0] b,
input ci,
output [3:0] s,
output co
);
wire [2:0] ct;
adder_1bit
a1 (
.a (a[0]),
.b (b[0]),
.ci(ci),
.s (s[0]),
.co(ct[0])
),
a2 (
.a (a[1]),
.b (b[1]),
.ci(ct[0]),
.s (s[1]),
.co(ct[1])
),
a3 (
.a (a[2]),
.b (b[2]),
.ci(ct[1]),
.s (s[2]),
.co(ct[2])
),
a4 (
.a (a[3]),
.b (b[3]),
.ci(ct[2]),
.s (s[3]),
.co(co)
);
endmodule
| 8.00499 |
module adder_4bits (
input [3 : 0] a,
input [3 : 0] b,
input ci,
output [3 : 0] s,
output co
);
wire [2 : 0] ct;
adder_1bit
a1 (
.a (a[0]),
.b (b[0]),
.ci(ci),
.s (s[0]),
.co(ct[0])
),
a2 (
.a (a[1]),
.b (b[1]),
.ci(ct[0]),
.s (s[1]),
.co(ct[1])
),
a3 (
.a (a[2]),
.b (b[2]),
.ci(ct[1]),
.s (s[2]),
.co(ct[2])
),
a4 (
.a (a[3]),
.b (b[3]),
.ci(ct[2]),
.s (s[3]),
.co(co)
);
endmodule
| 8.00499 |
module top_adder_4bits_generatecase
//Clock frequency in unit of MHz
(
input [3:0] a,
b,
input CLK1,
CLK2,
input RST,
output [3:0] sum_HH,
sum_HL,
sum_LH,
sum_LL,
output c_HH,
c_HL,
c_LH,
c_LL
);
//Load other module(s)
adder_4bits_generatecase #(
.CLOCK_FREQNENCY(`FREQUENCY1),
.HIGH_CHIP(1)
) A_HH (
.a (a),
.b (b),
.CLK(CLK1),
.RST(RST),
.sum(sum_HH),
.c (c_HH)
);
adder_4bits_generatecase #(
.CLOCK_FREQNENCY(`FREQUENCY1),
.HIGH_CHIP(0)
) A_HL (
.a (a),
.b (b),
.CLK(CLK1),
.RST(RST),
.sum(sum_HL),
.c (c_HL)
);
adder_4bits_generatecase #(
.CLOCK_FREQNENCY(`FREQUENCY2),
.HIGH_CHIP(1)
) A_LH (
.a (a),
.b (b),
.CLK(CLK2),
.RST(RST),
.sum(sum_LH),
.c (c_LH)
);
adder_4bits_generatecase #(
.CLOCK_FREQNENCY(`FREQUENCY2),
.HIGH_CHIP(0)
) A_LL (
.a (a),
.b (b),
.CLK(CLK2),
.RST(RST),
.sum(sum_LL),
.c (c_LL)
);
//Definition for Variables in the module
//Logical
endmodule
| 7.921185 |
module adder_4bits_generatecase
//Clock frequency in unit of MHz
(
input [3:0] a,
b,
input CLK,
input RST,
output [3:0] sum,
output c
);
parameter [8:0] CLOCK_FREQNENCY = 100;
parameter [0:0] HIGH_CHIP = 0;
localparam [0:0] HIGH_CLOCK = (CLOCK_FREQNENCY > `HIGH_SPEED);
//Load other module(s)
generate
begin
case ({
HIGH_CLOCK, HIGH_CHIP
})
2'b11: //High clock frequency or low quality chip
//Pipeline select
begin
adder_4bits_pipeline pipeline (
.a (a),
.b (b),
.CLK(CLK),
.RST(RST),
.sum(sum),
.c (c)
);
end
2'b10: //Low quality chips,pipeline selected
begin
adder_4bits_pipeline pipeline (
.a (a),
.b (b),
.CLK(CLK),
.RST(RST),
.sum(sum),
.c (c)
);
end
2'b00: //Low quality chips, pipeline selected
begin
adder_4bits_pipeline pipeline (
.a (a),
.b (b),
.CLK(CLK),
.RST(RST),
.sum(sum),
.c (c)
);
end
2'b01: //others. combined logic
begin
adder_4bits combine (
.a (a),
.b (b),
.sum(sum),
.c (c)
);
end
endcase
end
endgenerate
//Definition for Variables in the module
//Logical
endmodule
| 7.721974 |
module top_adder_4bits_generateif
//Clock frequency in unit of MHz
(
input [3:0] a,
b,
input CLK1,
CLK2,
input RST,
output [3:0] sum1,
sum2,
output c1,
c2
);
//Load other module(s)
adder_4bits_generateif #(
.CLOCK_FREQNENCY(`FREQUENCY1)
) A1 (
.a (a),
.b (b),
.CLK(CLK1),
.RST(RST),
.sum(sum1),
.c (c1)
);
adder_4bits_generateif #(
.CLOCK_FREQNENCY(`FREQUENCY2)
) A2 (
.a (a),
.b (b),
.CLK(CLK2),
.RST(RST),
.sum(sum2),
.c (c2)
);
//Definition for Variables in the module
//Logical
endmodule
| 7.921185 |
module adder_4bits_generateif #(
parameter CLOCK_FREQNENCY = 100
)
//Clock frequency in unit of MHz
(
input [3:0] a,
b,
input CLK,
input RST,
output [3:0] sum,
output c
);
//Load other module(s)
generate
begin
if (CLOCK_FREQNENCY > `HIGH_SPEED) begin
adder_4bits_pipeline pipeline (
.a (a),
.b (b),
.CLK(CLK),
.RST(RST),
.sum(sum),
.c (c)
);
end else begin
adder_4bits combine (
.a (a),
.b (b),
.sum(sum),
.c (c)
);
end
end
endgenerate
//Definition for Variables in the module
//Logical
endmodule
| 7.721974 |
module top_adder_4bits_generateifinif
//Clock frequency in unit of MHz
(
input [3:0] a,
b,
input CLK1,
CLK2,
input RST,
output [3:0] sum_HH,
sum_HL,
sum_LH,
sum_LL,
output c_HH,
c_HL,
c_LH,
c_LL
);
//Load other module(s)
adder_4bits_generateifinif #(
.CLOCK_FREQNENCY(`FREQUENCY1),
.HIGH_CHIP(1)
) A_HH (
.a (a),
.b (b),
.CLK(CLK1),
.RST(RST),
.sum(sum_HH),
.c (c_HH)
);
adder_4bits_generateifinif #(
.CLOCK_FREQNENCY(`FREQUENCY1),
.HIGH_CHIP(0)
) A_HL (
.a (a),
.b (b),
.CLK(CLK1),
.RST(RST),
.sum(sum_HL),
.c (c_HL)
);
adder_4bits_generateifinif #(
.CLOCK_FREQNENCY(`FREQUENCY2),
.HIGH_CHIP(1)
) A_LH (
.a (a),
.b (b),
.CLK(CLK2),
.RST(RST),
.sum(sum_LH),
.c (c_LH)
);
adder_4bits_generateifinif #(
.CLOCK_FREQNENCY(`FREQUENCY2),
.HIGH_CHIP(0)
) A_LL (
.a (a),
.b (b),
.CLK(CLK2),
.RST(RST),
.sum(sum_LL),
.c (c_LL)
);
//Definition for Variables in the module
//Logical
endmodule
| 7.921185 |
module adder_4bits_generateifinif
//Clock frequency in unit of MHz
(
input [3:0] a,
b,
input CLK,
input RST,
output [3:0] sum,
output c
);
parameter [8:0] CLOCK_FREQNENCY = 100;
parameter [0:0] HIGH_CHIP = 0;
localparam [0:0] HIGH_CLOCK = (CLOCK_FREQNENCY > `HIGH_SPEED);
//Load other module(s)
generate
begin
if (~HIGH_CHIP) begin
adder_4bits_pipeline pipeline (
.a (a),
.b (b),
.CLK(CLK),
.RST(RST),
.sum(sum),
.c (c)
);
end else begin
if (HIGH_CLOCK) begin
adder_4bits_pipeline pipeline (
.a (a),
.b (b),
.CLK(CLK),
.RST(RST),
.sum(sum),
.c (c)
);
end else begin
adder_4bits combine (
.a (a),
.b (b),
.sum(sum),
.c (c)
);
end
end
end
endgenerate
//Definition for Variables in the module
//Logical
endmodule
| 7.721974 |
module adder_4bits_non_delay (
input [3:0] A,
input [3:0] B,
input select,
output [3:0] sum,
output carry_out
);
// Creating 4 , 2 bit adders and connecting them to each
wire co0, co1, co2;
adder_2bits_non_delay
bits_0 (
select,
A[0],
B[0],
select,
sum[0],
co0
),
bits_1 (
co0,
A[1],
B[1],
select,
sum[1],
co1
),
bits_2 (
co1,
A[2],
B[2],
select,
sum[2],
co2
),
bits_3 (
co2,
A[3],
B[3],
select,
sum[3],
carry_out
);
endmodule
| 7.824048 |
module counter input
CLR: module counter input
out_num: output port for the counter module
OV: overflow flag
------------------------------------------------------
History:
01-07-2016: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simulation time assignment
//Insert the modules
module adder_4bits_pipeline_test;
//defination for Variables
reg clk;
reg reset;
reg[7:0] cntr;
wire EN;
wire CLR;
wire[7:0] out_num;
wire OV;
wire[3:0] sum;
wire c;
//Connection to the modules
counter C1(.clk(clk), .Reset(reset), .EN(EN),
.CLR(CLR), .counter(out_num), .OV(OV));
adder_4bits_pipeline A1(.a(out_num[3:0]), .b(out_num[7:4]),
.CLK(clk), .RST(reset),
.sum(sum), .c(c));
begin
assign EN = 1'b1;
assign CLR = 1'b0;
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#10 clk = !clk;
//Reverse the clock in each 10ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
//Couner as input
always @(posedge clk or reset)
begin
if ( !reset)
//reset statement: counter keeps at 0
begin
cntr <= 8'h00;
end
else
//Wroking, counter increasing
begin
cntr <= cntr + 8'h01;
end
end
end
endmodule
| 7.206611 |
module counter input
CLR: module counter input
out_num: output port for the counter module
OV: overflow flag
------------------------------------------------------
History:
12-03-2015: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simulation time assignment
//Insert the modules
module adder_4bits_test;
//defination for Variables
reg clk;
reg reset;
reg[7:0] cntr;
wire EN;
wire CLR;
wire[7:0] out_num;
wire OV;
wire[3:0] sum;
wire c;
//Connection to the modules
counter C1(.clk(clk), .Reset(reset), .EN(EN),
.CLR(CLR), .counter(out_num), .OV(OV));
adder_4bits A1(.a0(out_num[3:0]), .a1(out_num[7:4]), .sum(sum), .c(c));
begin
assign EN = 1'b1;
assign CLR = 1'b0;
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#10 clk = !clk;
//Reverse the clock in each 10ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
//Couner as input
always @(posedge clk or reset)
begin
if ( !reset)
//reset statement: counter keeps at 0
begin
cntr <= 8'h00;
end
else
//Wroking, counter increasing
begin
cntr <= cntr + 8'h01;
end
end
end
endmodule
| 7.206611 |
module adder_4bit_red (
Sum,
A,
B,
C_in,
C_out
);
input [3:0] A, B; //input values
input C_in; //carry input
output [3:0] Sum; //sum
output C_out; //carry output
wire [2:0] carry; //carry throught the FAdders
full_adder_1bit bit1 (
.A(A[0]),
.B(B[0]),
.Cin(C_in),
.S(Sum[0]),
.Cout(carry[0])
);
full_adder_1bit bit2 (
.A(A[1]),
.B(B[1]),
.Cin(carry[0]),
.S(Sum[1]),
.Cout(carry[1])
);
full_adder_1bit bit3 (
.A(A[2]),
.B(B[2]),
.Cin(carry[1]),
.S(Sum[2]),
.Cout(carry[2])
);
full_adder_1bit bit4 (
.A(A[3]),
.B(B[3]),
.Cin(carry[2]),
.S(Sum[3]),
.Cout(C_out)
);
endmodule
| 7.453881 |
module adder_4b_ins (
input [3:0] a,
b,
input cin,
output [3:0] sum,
output cout
);
wire [2:0] c; // Intermediate Carry
full_adder FA1 (
.a(a[0]),
.b(b[0]),
.cin(cin),
.sum(sum[0]),
.cout(c[0])
);
full_adder FA2 (
.a(a[1]),
.b(b[1]),
.cin(c[0]),
.sum(sum[1]),
.cout(c[1])
);
full_adder FA3 (
.a(a[2]),
.b(b[2]),
.cin(c[1]),
.sum(sum[2]),
.cout(c[2])
);
full_adder FA4 (
.a(a[3]),
.b(b[3]),
.cin(c[2]),
.sum(sum[3]),
.cout(cout)
);
endmodule
| 6.928906 |
module adder_4in (
A,
B,
C,
out
);
parameter DWIDTH = 32;
parameter frac = 24;
input signed [DWIDTH-1:0] A, B, C;
output signed [DWIDTH-1:0] out;
assign out = A + B + C;
endmodule
| 9.091391 |
module adder_4X16 (
input clk,
input reset,
input wire signed [15:0] in_0,
input wire signed [15:0] in_1,
input wire signed [15:0] in_2,
input wire signed [15:0] in_3,
output reg signed [15:0] out
);
always @(posedge clk)
if (reset) out <= 0;
else out <= in_0 + in_1 + in_2 + in_3;
endmodule
| 7.342812 |
module adder_4_bit (
input [3:0] A,
input [3:0] B,
input Cin,
output [3:0] S,
output Cout
);
wire carry[0:2];
adder_1_bit a0 (
A[0],
B[0],
Cin,
S[0],
carry[0]
);
adder_1_bit a1 (
A[1],
B[1],
carry[0],
S[1],
carry[1]
);
adder_1_bit a2 (
A[2],
B[2],
carry[1],
S[2],
carry[2]
);
adder_1_bit a3 (
A[3],
B[3],
carry[2],
S[3],
Cout
);
endmodule
| 7.002036 |
module adder_4_bit_board (
input [9:0] SW,
output [9:0] LEDR
);
wire [2:0] c;
/* adder_1_bit ex0(SW[0],SW[4],SW[9],LEDR[0],c[0]);
adder_1_bit ex1(SW[1],SW[5],c[0],LEDR[1],c[1]);
adder_1_bit ex2(SW[2],SW[6],c[1],LEDR[2],c[2]);
adder_1_bit ex3(SW[3],SW[7],c[2],LEDR[3],LEDR[9]); */
adder_4_bit ex0 (
SW[3:0],
SW[7:4],
SW[9],
LEDR[3:0],
LEDR[9]
);
endmodule
| 7.727639 |
module adder_4_bit (
cout,
Sum,
A,
B,
cin
);
output [3:0] Sum;
output cout;
input [3:0] A;
input [3:0] B;
input cin;
assign {cout, Sum} = A + B + cin;
endmodule
| 7.002036 |
module adder_5 (
input [4:0] x,
input [4:0] y,
input cin,
output [4:0] z,
output cout
);
wire [5:0] carry5;
full_adder N1 (
.A(x[0]),
.B(y[0]),
.cin(cin),
.S(z[0]),
.cout(carry5[1])
);
full_adder N2 (
.A(x[1]),
.B(y[1]),
.cin(carry5[1]),
.S(z[1]),
.cout(carry5[2])
);
full_adder N3 (
.A(x[2]),
.B(y[2]),
.cin(carry5[2]),
.S(z[2]),
.cout(carry5[3])
);
full_adder N4 (
.A(x[3]),
.B(y[3]),
.cin(carry5[3]),
.S(z[3]),
.cout(carry5[4])
);
full_adder N5 (
.A(x[4]),
.B(y[4]),
.cin(carry5[4]),
.S(z[4]),
.cout(cout)
);
endmodule
| 7.499105 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
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