code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module adder_128b_tb ();
wire [127:0] out0;
wire out1;
reg [127:0] in0;
reg [127:0] in1;
integer i, file, mem, temp;
adder_128b U0 (
in0,
in1,
out0,
out1
);
initial begin
$display("-- Begining Simulation --");
$dumpfile("./adder_128b.vcd");
$dumpvars(0, adder_128... | 6.673318 |
module add_12_bit (
input1,
input2,
answer
);
parameter N = 12;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1... | 7.022223 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_15 (
input x,
input y,
input cin,
output reg s,
output reg cout
);
reg i;
reg j;
reg k;
always @* begin
s = x ^ y ^ cin;
i = x & y;
j = y & cin;
k = x & cin;
cout = i | j | k;
end
endmodule
| 6.826636 |
module adder_16 (
A,
B,
Cin,
O
);
input [15:0] A;
input [15:0] B;
input Cin;
output [16:0] O;
wire [15:0] P;
wire [15:0] G;
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin
prop_gen a (
.a(A[i]),
.b(B[i]),
.P(P[i]),
.G(G[i])
... | 7.110663 |
module Adder_16bit (
input [15:0] A,
input [15:0] B,
output CarryOut,
output [15:0] Result
);
wire [14:0] COUT;
Adder_1bit adder16bit_0 (
A[0],
B[0],
0,
Result[0],
COUT[0]
);
Adder_1bit adder16bit_1 (
A[1],
B[1],
COUT[0],
Result[1],
COU... | 7.160367 |
module adder_16bits (
a,
b,
ci,
s,
co
);
input [15 : 0] a;
input [15 : 0] b;
input ci;
output [15 : 0] s;
output co;
wire [2 : 0] c;
adder_4bits adder_4bits_inst (
.a (a[3 : 0]),
.b (b[3 : 0]),
.ci(ci),
.s (s[3 : 0]),
.co(c[0])
);
mux_adder_4bits ... | 7.525748 |
module adder_nbit_BIT_WIDTH16 (
a,
b,
carry_in,
sum,
overflow
);
input [15:0] a;
input [15:0] b;
output [15:0] sum;
input carry_in;
output overflow;
wire [15:1] carrys;
adder_1bit_15 \genblk1[0].IX (
.a(a[0]),
.b(b[0]),
.carry_in(carry_in),
.sum(sum[0]),
... | 6.79806 |
module adder_16bit (
a,
b,
carry_in,
sum,
overflow
);
input [15:0] a;
input [15:0] b;
output [15:0] sum;
input carry_in;
output overflow;
adder_nbit_BIT_WIDTH16 AX (
.a(a),
.b(b),
.carry_in(carry_in),
.sum(sum),
.overflow(overflow)
);
endmodule
| 7.133988 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_16 (
a,
b,
carry_in,
sum,
overflow
);
input [15:0] a;
input [15:0] b;
output [15:0] sum;
input carry_in;
output overflow;
adder_16_DW01_add_0 r304 (
.A ({1'b0, a}),
.B ({1'b0, b}),
.CI (carry_in),
.SUM({overflow, sum})
);
endmodule
| 7.110663 |
module adder_16_bit (
input [15:0] A,
input [15:0] B,
output reg [15:0] R
);
always @* R = A + B;
endmodule
| 7.596403 |
module adder_16_bit_tb;
// Inputs
reg [15:0] A;
reg [15:0] B;
// Outputs
wire [15:0] R;
// Instantiate the Unit Under Test (UUT)
adder_16_bit uut (
.A(A),
.B(B),
.R(R)
);
initial begin
// Initialize Inputs
A = 0;
B = 0;
// Wait 100 ns for global reset to finish... | 7.045454 |
module adder_16_test ();
/* Make a reset that pulses once. */
wire [15:0] sum;
wire cout;
reg [15:0] a;
reg [15:0] b;
reg c_in;
adder_16 l_m_RC_CLA_0 (
.sum (sum),
.c_out(cout),
.a (a),
.b (b),
.c_in (c_in)
);
initial begin
$dumpfile("adder_... | 6.582509 |
module adder_17 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn_signal,
output reg [15:0] out,
output reg [0:0] z,
output reg [0:0] v,
output reg [0:0] n
);
reg [15:0] s;
always @* begin
s = 16'h0000;
case (alufn_signal[0+0-:1])
1'h0: begin
s = a + b;
... | 7.216158 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_1b (
a,
b,
cin,
cout,
sum
);
input a, b, cin;
output cout, sum;
/** Cálculo do CarryOut **/
//CarryOut = (b.CarryIn) + (a.CarryIn) + (b.a)
wire and_cout1_out, and_cout2_out, and_cout3_out;
and and_cout1 (and_cout1_out, b, cin);
and and_cout2 (and_cout2_out, a, cin);
and... | 7.284049 |
module adder_1_bit (
input A,
input B,
input Cin,
output S,
output Cout
);
assign S = A ^ B ^ Cin;
assign Cout = (A & B) | (B & Cin) | (Cin & A);
endmodule
| 6.744845 |
module adder_1_bit_board (
input [2:0] SW,
output [1:0] LEDR
);
adder_1_bit ex1 (
SW[0],
SW[1],
SW[2],
LEDR[0],
LEDR[1]
);
endmodule
| 8.378088 |
module adder_1_bit_primitive (
input a,
b,
cin,
output s,
cout
);
wire x, y, z;
xor (x, a, b);
xor (s, x, cin);
and (y, x, cin);
and (z, a, b);
or (cout, y, z);
endmodule
| 7.054475 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_21 (
input x,
input y,
input cin,
output reg s,
output reg cout
);
reg i;
reg j;
reg k;
always @* begin
s = x ^ y ^ cin;
i = x & y;
j = y & cin;
k = x & cin;
cout = i | j | k;
end
endmodule
| 7.009905 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_27 (
input x,
input y,
input cin,
output reg s,
output reg cout
);
reg i;
reg j;
reg k;
always @* begin
s = x ^ y ^ cin;
i = x & y;
j = y & cin;
k = x & cin;
cout = i | j | k;
end
endmodule
| 6.528538 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_2bit (
A,
B,
S,
cout
);
input [1:0] A;
input [1:0] B;
output [1:0] S;
output cout;
wire cin;
fullAdder FA0 (
A[0],
B[0],
1'b0,
S[0],
cin
);
fullAdder FA1 (
A[1],
B[1],
cin,
S[1],
cout
);
endmodule
| 6.761888 |
module adder_2bits (
input Cin,
input A,
input B,
input select,
output Sum,
output Cout
);
// First we choose the selected B
wire b_result;
xor #(10) import_select (b_result, B, select);
// Then we give all the selections into full adder
full_adder add_2_bit (
Cin,
A... | 7.566682 |
module adder_2bits_non_delay (
input Cin,
input A,
input B,
input select,
output Sum,
output Cout
);
// First we choose the selected B
wire b_result;
xor import_select (b_result, B, select);
// Then we give all the selections into full adder
full_adder_non_delay add_2_bit (
... | 7.756499 |
module adder_2in (
in1,
in2,
out
);
input wire [7:0] in1, in2;
output wire [8:0] out;
assign out = in1 + in2;
endmodule
| 8.07843 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder32 (
A,
B,
S,
C31
);
input [31:0] A;
input [31:0] B;
output [31:0] S;
output C31;
wire px1, gx1, px2, gx2;
wire c15;
CLA_16 CLA1 (
.A (A[15:0]),
.B (B[15:0]),
.cin(0),
.S (S[15:0]),
.px (px1),
.gx (gx1)
);
CLA_16 CLA2 (
.A (A... | 8.194085 |
module adder_32b (
input [31:0] A,
input [31:0] B,
output [31:0] R
);
wire [32:0] R_tmp;
assign R_tmp = A + B;
assign R = R_tmp[31:0];
endmodule
| 6.868313 |
module adder_32bit (
cfinal,
sum,
num1,
num2,
cin
);
input [31:0] num1, num2;
input cin;
output [31:0] sum;
output cfinal;
wire cout[3:0];
ADDER_8bit add1 (
cout[0],
sum[7:0],
num1[7:0],
num2[7:0],
cin
);
ADDER_8bit add2 (
cout[1],
sum[15:8]... | 6.670207 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module thirtytwo_bit_Recursive_Carry_Adder (
output [31:0] sum,
output cout,
input [31:0] a,
b,
input clk
);
wire cin = 1'b0;
wire [31:0] c, g, p;
kgpchoose kgp[31:0] (
g,
p,
a,
b
);
wire [31:1] g2, p2;
buff buff_0 (
c[0],
g[0]
);
calcblock calc_... | 6.696784 |
module finaladderr (
output Si,
input ai,
bi,
Ci
);
wire w;
xor (w, ai, bi);
xor (Si, w, Ci);
endmodule
| 7.712775 |
module calcblock (
output G,
P,
input Gi,
Pi,
Gip,
Pip
);
wire w;
and (w, Pi, Gip);
or (G, w, Gi);
and (P, Pi, Pip);
endmodule
| 8.025708 |
module dff (
d,
clk,
clear,
q
);
input d, clk, clear;
output reg q;
always @(posedge clk) begin
if (clear == 1) q <= 0;
else q <= d;
//$display("%d\n",$time);
end
endmodule
| 7.361383 |
module Adder_32_Bits #(
parameter NBits = 32
) (
input [NBits-1:0] Data0,
input [NBits-1:0] Data1,
output [NBits-1:0] Result
);
assign Result = Data1 + Data0;
endmodule
| 9.431841 |
module adder_34 (
input [7:0] a,
input [7:0] b,
input alufn,
output reg [7:0] out,
output reg z,
output reg v,
output reg n
);
reg [7:0] outp;
always @* begin
case (alufn)
1'h0: begin
outp = a + b;
end
1'h1: begin
outp = a - b;
end
d... | 6.796745 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_3bit (
A,
B,
S,
cout
);
input [2:0] A;
input [2:0] B;
output [2:0] S;
output cout;
wire [2:1] cin;
fullAdder FA0 (
A[0],
B[0],
1'b0,
S[0],
cin[1]
);
fullAdder FA1 (
A[1],
B[1],
cin[1],
S[1],
cin[2]
);
fullAdde... | 6.908683 |
module adder_3in (
i_a,
i_b,
i_c,
o
);
// parameters
parameter DWIDTH = 32;
parameter FRAC = 24;
// input ports
input signed [DWIDTH-1:0] i_a, i_b, i_c;
// output ports
output signed [DWIDTH-1:0] o;
// adding i_a, i_b, and i_c
assign o = i_a + i_b + i_c;
endmodule
| 8.457397 |
module adder_4 (
x,
y,
cin,
c3,
F,
Gm,
Pm
);
input [3:0] x;
input [3:0] y;
input cin;
output c3, Gm, Pm;
output [3:0] F;
wire p0, p1, p2, p3, g0, g1, g2, g3;
wire c0, c1, c2;
adder adder1 (
.X(x[0]),
.Y(y[0]),
.Cin(cin),
.F(F[0]),
.Cout()
);
... | 7.763613 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_4b (
sum,
c_out,
a,
b,
c_in
);
input [3:0] a, b;
input c_in;
output [3:0] sum;
output c_out;
wire acarreo0, acarreo1, acarreo2;
full_adder_v1 fa0 (
a[0],
b[0],
c_in,
sum[0],
acarreo0
);
full_adder_v1 fa1 (
a[1],
b[1],
ac... | 6.885487 |
module adder_4bit (
S,
Cout,
A,
B,
Cin
);
output reg [3:0] S;
output reg Cout;
input [3:0] A, B;
input Cin;
always {Cout, S} = A + B + Cin;
endmodule
| 9.041993 |
module adder_4bits (
input [3:0] a,
input [3:0] b,
input ci,
output [3:0] s,
output co
);
wire [2:0] ct;
adder_1bit
a1 (
.a (a[0]),
.b (b[0]),
.ci(ci),
.s (s[0]),
.co(ct[0])
),
a2 (
.a (a[1]),
.b (b[1]),
... | 8.00499 |
module adder_4bits (
input [3 : 0] a,
input [3 : 0] b,
input ci,
output [3 : 0] s,
output co
);
wire [2 : 0] ct;
adder_1bit
a1 (
.a (a[0]),
.b (b[0]),
.ci(ci),
.s (s[0]),
.co(ct[0])
),
a2 (
.a (a[1]),
.b (b... | 8.00499 |
module top_adder_4bits_generatecase
//Clock frequency in unit of MHz
(
input [3:0] a,
b,
input CLK1,
CLK2,
input RST,
output [3:0] sum_HH,
sum_HL,
sum_LH,
sum_LL,
output c_HH,
c_HL,
c_LH,
c_LL
);
//Load other module(s)
adder_4bits_generatecase #(
.CLOCK_FREQ... | 7.921185 |
module adder_4bits_generatecase
//Clock frequency in unit of MHz
(
input [3:0] a,
b,
input CLK,
input RST,
output [3:0] sum,
output c
);
parameter [8:0] CLOCK_FREQNENCY = 100;
parameter [0:0] HIGH_CHIP = 0;
localparam [0:0] HIGH_CLOCK = (CLOCK_FREQNENCY > `HIGH_SPEED);
//Load other modul... | 7.721974 |
module top_adder_4bits_generateif
//Clock frequency in unit of MHz
(
input [3:0] a,
b,
input CLK1,
CLK2,
input RST,
output [3:0] sum1,
sum2,
output c1,
c2
);
//Load other module(s)
adder_4bits_generateif #(
.CLOCK_FREQNENCY(`FREQUENCY1)
) A1 (
.a (a),
.b (b)... | 7.921185 |
module adder_4bits_generateif #(
parameter CLOCK_FREQNENCY = 100
)
//Clock frequency in unit of MHz
(
input [3:0] a,
b,
input CLK,
input RST,
output [3:0] sum,
output c
);
//Load other module(s)
generate
begin
if (CLOCK_FREQNENCY > `HIGH_SPEED) begin
adder_4bits_pipelin... | 7.721974 |
module top_adder_4bits_generateifinif
//Clock frequency in unit of MHz
(
input [3:0] a,
b,
input CLK1,
CLK2,
input RST,
output [3:0] sum_HH,
sum_HL,
sum_LH,
sum_LL,
output c_HH,
c_HL,
c_LH,
c_LL
);
//Load other module(s)
adder_4bits_generateifinif #(
.CLOCK_... | 7.921185 |
module adder_4bits_generateifinif
//Clock frequency in unit of MHz
(
input [3:0] a,
b,
input CLK,
input RST,
output [3:0] sum,
output c
);
parameter [8:0] CLOCK_FREQNENCY = 100;
parameter [0:0] HIGH_CHIP = 0;
localparam [0:0] HIGH_CLOCK = (CLOCK_FREQNENCY > `HIGH_SPEED);
//Load other mod... | 7.721974 |
module adder_4bits_non_delay (
input [3:0] A,
input [3:0] B,
input select,
output [3:0] sum,
output carry_out
);
// Creating 4 , 2 bit adders and connecting them to each
wire co0, co1, co2;
adder_2bits_non_delay
bits_0 (
select,
A[0],
B[0],
select... | 7.824048 |
module counter input
CLR: module counter input
out_num: output port for the counter module
OV: overflow flag
------------------------------------------------------
History:
01-07-2016: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simula... | 7.206611 |
module counter input
CLR: module counter input
out_num: output port for the counter module
OV: overflow flag
------------------------------------------------------
History:
12-03-2015: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simula... | 7.206611 |
module adder_4bit_red (
Sum,
A,
B,
C_in,
C_out
);
input [3:0] A, B; //input values
input C_in; //carry input
output [3:0] Sum; //sum
output C_out; //carry output
wire [2:0] carry; //carry throught the FAdders
full_adder_1bit bit1 (
.A(A[0]),
.B(B[0]),
.Cin(C_in... | 7.453881 |
module adder_4b_ins (
input [3:0] a,
b,
input cin,
output [3:0] sum,
output cout
);
wire [2:0] c; // Intermediate Carry
full_adder FA1 (
.a(a[0]),
.b(b[0]),
.cin(cin),
.sum(sum[0]),
.cout(c[0])
);
full_adder FA2 (
.a(a[1]),
.b(b[1]),
.cin(c[... | 6.928906 |
module adder_4in (
A,
B,
C,
out
);
parameter DWIDTH = 32;
parameter frac = 24;
input signed [DWIDTH-1:0] A, B, C;
output signed [DWIDTH-1:0] out;
assign out = A + B + C;
endmodule
| 9.091391 |
module adder_4X16 (
input clk,
input reset,
input wire signed [15:0] in_0,
input wire signed [15:0] in_1,
input wire signed [15:0] in_2,
input wire signed [15:0] in_3,
output reg signed [15:0] out
);
always @(posedge clk)
if (reset) out <= 0;
else out <= in_0 + in_1 + in_2 + in_3;... | 7.342812 |
module adder_4_bit (
input [3:0] A,
input [3:0] B,
input Cin,
output [3:0] S,
output Cout
);
wire carry[0:2];
adder_1_bit a0 (
A[0],
B[0],
Cin,
S[0],
carry[0]
);
adder_1_bit a1 (
A[1],
B[1],
carry[0],
S[1],
carry[1]
);
adder_1... | 7.002036 |
module adder_4_bit_board (
input [9:0] SW,
output [9:0] LEDR
);
wire [2:0] c;
/* adder_1_bit ex0(SW[0],SW[4],SW[9],LEDR[0],c[0]);
adder_1_bit ex1(SW[1],SW[5],c[0],LEDR[1],c[1]);
adder_1_bit ex2(SW[2],SW[6],c[1],LEDR[2],c[2]);
adder_1_bit ex3(SW[3],SW[7],c[2],LEDR[3],LEDR[9]); */
adder_4_bit ex0 (
... | 7.727639 |
module adder_4_bit (
cout,
Sum,
A,
B,
cin
);
output [3:0] Sum;
output cout;
input [3:0] A;
input [3:0] B;
input cin;
assign {cout, Sum} = A + B + cin;
endmodule
| 7.002036 |
module adder_5 (
input [4:0] x,
input [4:0] y,
input cin,
output [4:0] z,
output cout
);
wire [5:0] carry5;
full_adder N1 (
.A(x[0]),
.B(y[0]),
.cin(cin),
.S(z[0]),
.cout(carry5[1])
);
full_adder N2 (
.A(x[1]),
.B(y[1]),
.cin(carry5[1]),
... | 7.499105 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.