code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENBUFX2 (
input A,
output Y
);
assign Y = A;
endmodule
| 6.850249 |
module PDKGENXNOR2X1 (
input A,
input B,
output Y
);
assign Y = ~(A ^ B);
endmodule
| 8.39041 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENINVX1 (
input A,
output Y
);
assign Y = ~A;
endmodule
| 7.577469 |
module PDKGENNOR2X1 (
input A,
input B,
output Y
);
assign Y = ~(A | B);
endmodule
| 7.795351 |
module PDKGENNAND3X1 (
input A,
input B,
input C,
output Y
);
assign Y = ~((A & B) & C);
endmodule
| 8.198688 |
module PDKGENBUFX2 (
input A,
output Y
);
assign Y = A;
endmodule
| 6.850249 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENINVX1 (
input A,
output Y
);
assign Y = ~A;
endmodule
| 7.577469 |
module PDKGENNOR2X1 (
input A,
input B,
output Y
);
assign Y = ~(A | B);
endmodule
| 7.795351 |
module PDKGENNOR3X1 (
input A,
input B,
input C,
output Y
);
assign Y = ~((A | B) | C);
endmodule
| 6.941576 |
module PDKGENBUFX2 (
input A,
output Y
);
assign Y = A;
endmodule
| 6.850249 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module PDKGENMUX2X1 (
input A,
input B,
input S,
output Y
);
assign Y = (A & ~S) | (B & S);
endmodule
| 8.673181 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENINVX1 (
input A,
output Y
);
assign Y = ~A;
endmodule
| 7.577469 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module add9 (
dataa,
datab,
cout,
overflow,
result
);
input [8:0] dataa;
input [8:0] datab;
output cout;
output overflow;
output [8:0] result;
wire sub_wire0;
wire sub_wire1;
wire [8:0] sub_wire2;
wire overflow = sub_wire0;
wire cout = sub_wire1;
wire [8:0] result = sub_wire2[8:0];
lpm_add_sub LPM_ADD_SUB_component (
.datab(datab),
.dataa(dataa),
.overflow(sub_wire0),
.cout(sub_wire1),
.result(sub_wire2)
// synopsys translate_off
, .aclr(),
.add_sub(),
.cin(),
.clken(),
.clock()
// synopsys translate_on
);
defparam LPM_ADD_SUB_component.lpm_direction = "ADD", LPM_ADD_SUB_component.lpm_hint =
"ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO", LPM_ADD_SUB_component.lpm_representation = "SIGNED",
LPM_ADD_SUB_component.lpm_type = "LPM_ADD_SUB", LPM_ADD_SUB_component.lpm_width = 9;
endmodule
| 6.721821 |
module add9 (
dataa,
datab,
cout,
overflow,
result
);
input [8:0] dataa;
input [8:0] datab;
output cout;
output overflow;
output [8:0] result;
endmodule
| 6.721821 |
module addalu (
valorEstendidoDeslocado,
pcincrementado,
Addresult
);
input [31:0] valorEstendidoDeslocado, pcincrementado;
output [31:0] Addresult;
assign Addresult = valorEstendidoDeslocado + pcincrementado;
endmodule
| 7.11169 |
module AddAnd (
input [11:0] A,
input [11:0] B,
input CI,
input OE_ADD,
input OE_AND,
output [11:0] S,
output CO
);
wire [12:0] sum;
assign sum = A + B + {12'b0, CI};
assign S = OE_ADD ? sum[11:0] : OE_AND ? A & B : 12'b0;
assign CO = OE_ADD ? sum[12] : 1'b0;
endmodule
| 6.643152 |
module addat (
input wire adclk,
input wire adsfl,
input wire advs,
input wire adhs,
input wire adfield,
input wire [19:0] addat,
output reg inde,
output reg [24:0] indat
);
reg [39:0] sr;
reg [1:0] ctr;
reg act;
reg start;
initial begin
start = 0;
end
always @(posedge adclk) begin
sr <= {sr[29:0], addat[19:10]};
if ({sr[39:32], sr[29:22], sr[19:12]} == 24'hFF0000) begin
act <= sr[7:6] == 0;
ctr <= 0;
end else ctr <= ctr + 1;
end
reg aact, aact_;
reg async;
reg [9:0] ay, ay_, acb, acr;
always @(posedge adclk) begin
aact <= 0;
aact_ <= 0;
if ({sr[39:32], sr[29:22], sr[19:12]} == 24'hFF0000 && sr[7:6] == 2'b11) start <= 1;
if (act && ctr == 3 && {sr[39:32], sr[29:22], sr[19:12]} != 24'hFF0000) begin
aact <= 1;
aact_ <= 1;
ay <= sr[29:20];
ay_ <= sr[9:0];
acb <= sr[39:30];
acr <= sr[19:10];
async <= start;
start <= 0;
end
if (aact_) begin
aact <= 1;
ay <= ay_;
async <= 0;
end
end
reg [35:0] bsy, bscr0, bscb0, bscr1, bscb1;
reg [37:0] cr, cg, cb;
reg bact, cact;
reg bsync, csync;
always @(posedge adclk) begin
bsy <= 32897 * ay;
bscr0 <= 46122 * acr;
bscr1 <= 23492 * acr;
bscb0 <= 58294 * acb;
bscb1 <= 11321 * acb;
bact <= aact;
bsync <= async;
cr <= bsy + bscr0 - 23745800 + (1 << 16);
cb <= bsy + bscb0 - 29977900 + (1 << 16);
cg <= bsy - bscr1 - bscb1 + 17693200 + (1 << 16);
cact <= bact;
csync <= bsync;
indat[7:0] <= cb[26] ? 0 : cb[25] ? 255 : cb[24:17];
indat[15:8] <= cg[26] ? 0 : cg[25] ? 255 : cg[24:17];
indat[23:16] <= cr[26] ? 0 : cr[25] ? 255 : cr[24:17];
indat[24] <= csync;
inde <= cact;
end
endmodule
| 6.670727 |
module addattest;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [23:0] indat; // From addat0 of addat.v
wire inde; // From addat0 of addat.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg adclk; // To addat0 of addat.v
reg adfield; // To addat0 of addat.v
reg adhs; // To addat0 of addat.v
reg adsfl; // To addat0 of addat.v
reg advs; // To addat0 of addat.v
// End of automatics
initial adclk = 0;
localparam N = 100;
always #0.5 adclk = !adclk;
reg [9:0] mem[0:4+N*2];
reg [9:0] y, cb, cr;
real ry, rcb, rcr, rr, rg, rb;
reg [7:0] r, g, b;
reg [23:0] out[0:N-1];
integer i;
integer idx, oidx;
initial begin
mem[0] = {8'hff, 2'b0};
mem[1] = 0;
mem[2] = 0;
mem[3] = 10'b1000000000;
for (i = 4; i < 4 + N * 2; i = i + 1) begin
mem[i] = $random;
while (mem[i] == 0 || mem[i] == 1023) mem[i] = $random;
end
for (i = 0; i < N; i = i + 1) begin
cb = mem[4+(i/2)*4];
cr = mem[4+(i/2)*4+2];
y = mem[4+2*i+1];
ry = (y - 4.0) / 1016;
rcb = (cb - 4.0) / 1016 - 0.5;
rcr = (cr - 4.0) / 1016 - 0.5;
rr = 1.402 * rcr + ry;
rg = 1.70358 * (0.587 * ry - 0.419198 * rcr - 0.202008 * rcb);
rb = 1.772 * rcb + ry;
r = rr < 0 ? 0 : rr >= 1 ? 255 : 255 * rr;
g = rg < 0 ? 0 : rg >= 1 ? 255 : 255 * rg;
b = rb < 0 ? 0 : rb >= 1 ? 255 : 255 * rb;
out[i] = {r, g, b};
end
idx = 0;
oidx = 0;
end
wire [19:0] addat = {mem[idx], 10'bx};
always @(posedge adclk) begin
idx <= idx + 1;
if (inde) begin
if (indat != out[oidx]) $display("%d: %x != %x", oidx, indat, out[oidx]);
oidx <= oidx + 1;
end
end
initial #1000 $finish;
initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
addat addat0 ( /*AUTOINST*/
// Outputs
.inde(inde),
.indat(indat[23:0]),
// Inputs
.adclk(adclk),
.adsfl(adsfl),
.advs(advs),
.adhs(adhs),
.adfield(adfield),
.addat(addat[19:0])
);
endmodule
| 6.624231 |
module adda_out (
input clk,
output wire [7:0] dacdata,
input rst_n //KEY IN PORT
);
wire [7:0] rom_address;
/* ------------------------------------------------------------------
* WAVE RELATED
* ------------------------------------------------------------------- */
wire [7:0] rom_data;
reg [7:0] save_data; //choose the generated wave
assign dacdata = {1'b0, save_data[7:1]}; //get rom data
always @(posedge clk) begin
begin
save_data <= rom_data;
end
end
/* ------------------------------------------------------------------
* FREQUENCE CTRL MODULE:USING USATR PART
* COMPUTING FORMULA: fre=2^32*F(the fre you hope to get)*TCLK(T of clk source :20ns)
* ------------------------------------------------------------------- */
wire [59:0] truefre;
assign truefre = 60'd858993; //10k
/* ------------------------------------------------------------------
* INSTANTIATION PROCESS
* ------------------------------------------------------------------- */
addr_ctrl addr_ctrl_inst (
.clk_50M(clk),
.rst_n(rst_n),
.addr(rom_address),
.freqctrl(truefre[31:0])
);
sin sin_inst (
.clock(clk),
.address(rom_address),
.q(rom_data)
);
endmodule
| 7.639413 |
module adda_pll_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [2:1] CLK_OUT,
// High bits of counters driven by clocks
output [2:1] COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
localparam NUM_C = 2;
genvar count_gen;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
reg [NUM_C:1] rst_sync;
reg [NUM_C:1] rst_sync_int;
reg [NUM_C:1] rst_sync_int1;
reg [NUM_C:1] rst_sync_int2;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk_n;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Insert BUFGs on all input clocks that don't already have them
//--------------------------------------------------------------
BUFG clkin1_buf (
.O(clk_in1_buf),
.I(CLK_IN1)
);
// Instantiation of the clocking network
//--------------------------------------
adda_pll clknetwork ( // Clock in ports
.clk_in (clk_in1_buf),
// Clock out ports
.clk_out1(clk_int[1]),
.clk_out2(clk_int[2]),
// Status and control signals
.reset (RESET),
.locked (LOCKED)
);
genvar clk_out_pins;
generate
for (
clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1
) begin : gen_outclk_oddr
assign clk_n[clk_out_pins] = ~clk[clk_out_pins];
ODDR2 clkout_oddr (
.Q (CLK_OUT[clk_out_pins]),
.C0(clk[clk_out_pins]),
.C1(clk_n[clk_out_pins]),
.CE(1'b1),
.D0(1'b1),
.D1(1'b0),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
// Connect the output clocks to the design
//-----------------------------------------
assign clk[1] = clk_int[1];
assign clk[2] = clk_int[2];
// Reset synchronizer
//-----------------------------------
generate
for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin : counters_1
always @(posedge reset_int or posedge clk[count_gen]) begin
if (reset_int) begin
rst_sync[count_gen] <= 1'b1;
rst_sync_int[count_gen] <= 1'b1;
rst_sync_int1[count_gen] <= 1'b1;
rst_sync_int2[count_gen] <= 1'b1;
end else begin
rst_sync[count_gen] <= 1'b0;
rst_sync_int[count_gen] <= rst_sync[count_gen];
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
end
end
end
endgenerate
// Output clock sampling
//-----------------------------------
generate
for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin : counters
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
if (rst_sync_int2[count_gen]) begin
counter[count_gen] <= #TCQ{C_W{1'b0}};
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule
| 7.411442 |
module adda_pll_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.0 * ONE_NS;
localparam time PER1_1 = PER1 / 2;
localparam time PER1_2 = PER1 - PER1 / 2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [ 2:1] COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
wire [ 2:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1 * 6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1 * 6);
COUNTER_RESET = 1;
#(PER1 * 19.5) COUNTER_RESET = 0;
#(PER1 * 1) $display("Timing checks are valid");
test_phase = "counting";
#(PER1 * COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n", $time / PER1);
$finish;
end
always @(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n", $time / PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
adda_pll_exdes dut ( // Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET(COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED)
);
// Freq Check
endmodule
| 7.318295 |
module addbit (
a, // first input
b, // Second input
ci, // Carry input
sum, // sum output
co // carry output
);
//Input declaration
input a;
input b;
input ci;
//Ouput declaration
output sum;
output co;
//Port Data types
wire a;
wire b;
wire ci;
wire sum;
wire co;
//Code starts here
assign {co, sum} = a + b + ci;
endmodule
| 7.120785 |
module addecrc (
i_clk,
i_ce,
i_en,
i_cancel,
i_v,
i_d,
o_v,
o_d
);
localparam INVERT = 1; // Proper operation requires INVERT=1
input wire i_clk, i_ce, i_en, i_cancel;
input wire i_v;
input wire [3:0] i_d;
output reg o_v;
output reg [3:0] o_d;
reg [ 7:0] r_p;
reg [31:0] r_crc;
wire [ 3:0] lownibble;
wire [31:0] shifted_crc;
assign lownibble = r_crc[3:0] ^ i_d;
assign shifted_crc = {4'h0, r_crc[31:4]};
initial o_v = 1'b0;
always @(posedge i_clk)
if (i_ce) begin
if (((!i_v) && (!o_v)) || (i_cancel)) begin
r_crc <= (INVERT == 0) ? 32'h00 : 32'hffffffff;
r_p <= 8'hff;
end else if (i_v) begin
o_v <= i_v;
r_p <= 8'hff;
o_d <= i_d;
`define CRCBIT8 32'hedb88320
`define CRCBIT4 32'h76dc4190
`define CRCBIT2 32'h3b6e20c8
`define CRCBIT1 32'h1db71064
// 0xedb88320 . 76dc4190 . 3b6e20c8 . 1db71064 . 0edb8832
case (lownibble)
4'h0: r_crc <= shifted_crc;
4'h1: r_crc <= shifted_crc ^ `CRCBIT1;
4'h2: r_crc <= shifted_crc ^ `CRCBIT2;
4'h3: r_crc <= shifted_crc ^ `CRCBIT2 ^ `CRCBIT1;
4'h4: r_crc <= shifted_crc ^ `CRCBIT4;
4'h5: r_crc <= shifted_crc ^ `CRCBIT4 ^ `CRCBIT1;
4'h6: r_crc <= shifted_crc ^ `CRCBIT4 ^ `CRCBIT2;
4'h7: r_crc <= shifted_crc ^ `CRCBIT4 ^ `CRCBIT2 ^ `CRCBIT1;
4'h8: r_crc <= shifted_crc ^ `CRCBIT8;
4'h9: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT1;
4'ha: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT2;
4'hb: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT2 ^ `CRCBIT1;
4'hc: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT4;
4'hd: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT4 ^ `CRCBIT1;
4'he: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT4 ^ `CRCBIT2;
4'hf: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT4 ^ `CRCBIT2 ^ `CRCBIT1;
default: r_crc <= {4'h0, r_crc[31:4]};
endcase
end else begin
r_p <= {r_p[6:0], 1'b0};
o_v <= (i_en) ? r_p[7] : 1'b0;
o_d <= r_crc[3:0] ^ ((INVERT == 0) ? 4'h0 : 4'hf);
r_crc <= {4'h0, r_crc[31:4]};
end
end
endmodule
| 6.845018 |
module addepad (
i_clk,
i_ce,
i_cancel,
i_v,
i_d,
o_v,
o_d
);
parameter MINNIBBLES = 120;
localparam LGNCOUNT=(MINNIBBLES<63)? 6
:((MINNIBBLES<127)? 7:((MINNIBBLES<255)? 8:9));
input wire i_clk, i_ce, i_cancel;
input wire i_v; // Valid
input wire [3:0] i_d; // Data nibble
output reg o_v;
output reg [3:0] o_d;
reg [(LGNCOUNT-1):0] r_ncnt;
initial o_v = 1'b0;
always @(posedge i_clk)
if (i_ce) begin
if (((!i_v) && (!o_v)) || (i_cancel)) begin
r_ncnt <= 0;
o_v <= 1'b0;
end else if (i_v) begin
o_v <= i_v;
r_ncnt <= (r_ncnt < MINNIBBLES) ? r_ncnt + 1'b1 : r_ncnt;
end else begin
o_v <= (r_ncnt < MINNIBBLES);
r_ncnt <= (r_ncnt < MINNIBBLES) ? r_ncnt + 1'b1 : r_ncnt;
end
if (i_v) o_d <= i_d;
else o_d <= 4'h0;
end
endmodule
| 7.961737 |
module addepreamble (
i_clk,
i_ce,
i_en,
i_cancel,
i_v,
i_d,
o_v,
o_d
);
input wire i_clk, i_ce, i_en, i_cancel;
input wire i_v; // Valid
input wire [3:0] i_d; // Data nibble
output wire o_v;
output wire [3:0] o_d;
reg [84:0] shiftreg;
reg r_v;
reg [3:0] r_d;
initial r_v = 1'b0;
always @(posedge i_clk)
if (i_ce) begin
shiftreg <= {shiftreg[79:0], {i_v, i_d}};
r_v <= shiftreg[84];
r_d <= shiftreg[83:80];
if (((!i_v) && (!o_v)) || (i_cancel)) begin
shiftreg <= {
5'h00,
5'h15,
5'h15,
5'h15,
5'h15,
5'h15,
5'h15,
5'h15,
5'h15,
5'h15,
5'h15,
5'h15,
5'h15,
5'h15,
5'h15,
5'h15,
5'h1d
};
if (!i_en) begin
shiftreg[4] <= 1'b0;
shiftreg[9] <= 1'b0;
shiftreg[14] <= 1'b0;
shiftreg[19] <= 1'b0;
shiftreg[24] <= 1'b0;
shiftreg[29] <= 1'b0;
shiftreg[34] <= 1'b0;
shiftreg[39] <= 1'b0;
shiftreg[44] <= 1'b0;
shiftreg[49] <= 1'b0;
shiftreg[54] <= 1'b0;
shiftreg[59] <= 1'b0;
shiftreg[64] <= 1'b0;
shiftreg[69] <= 1'b0;
shiftreg[74] <= 1'b0;
shiftreg[79] <= 1'b0;
end
end
end
assign o_v = r_v;
assign o_d = r_d;
endmodule
| 7.167665 |
module FA16bit (
input [15:0] term,
result,
input flag,
output [15:0] FA_Out
);
assign FA_Out = (~flag) ? (result + term) : (result - term);
endmodule
| 7.262555 |
module adder #(
parameter fcw = 16'd10000
) ( //参数为16位大小 默认参数（10000）
sum,
clk,
rst
);
output [15:0] sum; //输出地址
input clk;
input rst;
reg [15:0] sum; //初值
always @(posedge clk)//正沿触发
begin
if (!rst) //复位0有效
sum <= 16'd0;
else sum <= sum + fcw; //求和
end
endmodule
| 9.043323 |
module Adder (
INPUT1,
INPUT2,
OUTPUT
);
input wire [31:0] INPUT1;
input wire [31:0] INPUT2;
output wire [31:0] OUTPUT;
assign OUTPUT = INPUT1 + INPUT2;
endmodule
| 7.280733 |
module Adder (
input clock,
input reset,
input [31:0] io_inputx,
input [31:0] io_inputy,
output [31:0] io_result
);
assign io_result = io_inputx + io_inputy;
endmodule
| 7.642138 |
module Adder #(
parameter OPERAND_WIDTH = 32
) (
y,
op1,
op2
);
input [OPERAND_WIDTH - 1 : 0] op1;
input [OPERAND_WIDTH - 1 : 0] op2;
output [OPERAND_WIDTH - 1 : 0] y;
assign y = op1 + op2;
endmodule
| 9.509237 |
module add_1p (
x,
y,
sum,
clk
);
parameter WIDTH = 16, // Total bit width
LSB_WIDTH = 8, // Bit width of LSBs
MSB_WIDTH = 8; // Bit width of MSBs
input [WIDTH-1:0] x, y; // Inputs
output [WIDTH-1:0] sum; // Result
input clk; // Clock
reg [LSB_WIDTH-1:0] l1, l2; // LSBs of inputs
wire [LSB_WIDTH-1:0] q1, r1; /// LSBs of inputs
reg [MSB_WIDTH-1:0] l3, l4; // MSBs of input
wire [MSB_WIDTH-1:0] r2, q2, u2; // MSBs of input
wire cr1, cq1; // LSBs carry signal
wire [MSB_WIDTH-1:0] h2; // Auxiliary MSBs of input
// Split in MSBs and LSBS and store in registers
always @(posedge clk) begin
// Split LSBs from input x,y
//l1[LSB_WIDTH-1:0] <= x[LSB_WIDTH-1:0];
//l2[LSB_WIDTH-1:0] <= y[LSB_WIDTH-1:0];
// Split MSBs from input x,y
l3[MSB_WIDTH-1:0] <= x[MSB_WIDTH-1+LSB_WIDTH:LSB_WIDTH];
l4[MSB_WIDTH-1:0] <= y[MSB_WIDTH-1+LSB_WIDTH:LSB_WIDTH];
end
/************* First stage of the adder *****************/
lpm_add_sub #(LSB_WIDTH, "ADD") add_1 // Add LSBs of x and y
(
.result(r1),
.dataa(x[LSB_WIDTH-1:0]),
.datab(y[LSB_WIDTH-1:0]),
.cin(1'b0),
.cout(cr1)
); // Used ports
lpm_ff #(LSB_WIDTH) reg_1 // Save LSBs of x+y
(
.data(r1),
.q(q1),
.clock(clk)
);
lpm_ff #(1) reg_2 // Save LSBs carry
(
.data(cr1),
.q(cq1),
.clock(clk)
);
lpm_add_sub #(MSB_WIDTH, "ADD") add_2 //Add MSBs of x and y
(
.dataa(l3),
.datab(l4),
.result(r2),
.cin(cq1),
.cout()
); //Used ports
//lpm_ff #(MSB_WIDTH) reg_3 // Save MSBs of x+y
//(.data(r2), .q(q2), .clock(clk)); // Used ports
assign sum = {r2, q1};
endmodule
| 6.645901 |
module lpm_ff #(
parameter WIDTH = 1
) (
input [WIDTH-1:0] data,
output reg [WIDTH-1:0] q,
input clock
);
always @(posedge clock) begin
q <= data;
end
endmodule
| 7.074985 |
module lpm_add_sub #(
parameter WIDTH = 1,
parameter ALU = "ADD"
) (
input [WIDTH-1:0] dataa,
input [WIDTH-1:0] datab,
input cin,
output cout,
output [WIDTH-1:0] result
);
reg [WIDTH:0] temp;
always @* begin
case (ALU)
"ADD": temp = dataa + datab + cin;
"SUB": temp = dataa - datab;
default: temp = {WIDTH{1'b1}};
endcase
end
assign cout = temp[WIDTH];
assign result = temp[WIDTH-1:0];
//assign {cout,result} = dataa + datab + cin;
endmodule
| 7.42875 |
module top_module (
input [99:0] a,
b,
input cin,
output cout,
output [99:0] sum
);
// method 1
reg [100:0] result;
assign result = a[99:0] + b[99:0] + cin;
assign sum = result[99:0];
assign cout = result[100];
// method 2
wire [98:0] carry;
full_adder u_full_adder_0 (
a[0],
b[0],
cin,
carry[0],
sum[0]
);
full_adder u_full_adder_99 (
a[99],
b[99],
carry[98],
cout,
sum[99]
);
generate
genvar i;
for (i = 1; i < 99; i++) begin : add_100
full_adder u_full_adder (
a[i],
b[i],
carry[i-1],
carry[i],
sum[i]
);
end
endgenerate
endmodule
| 7.203305 |
module top_module (
input [99:0] a,
b,
input cin,
output cout,
output [99:0] sum
);
assign {cout, sum} = a + b + cin;
endmodule
| 7.203305 |
module top_module (
input [99:0] a,
b,
input cin,
output [99:0] cout,
output [99:0] sum
);
always @(*) begin
sum[0] = a[0] ^ b[0] ^ cin;
cout[0] = (a[0] & b[0]) | ((a[0] ^ b[0]) & cin);
for (integer i = 1; i < 100; i++) begin
sum[i] = a[i] ^ b[i] ^ cout[i-1];
cout[i] = (a[i] & b[i]) | ((a[i] ^ b[i]) & cout[i-1]);
end
end
endmodule
| 7.203305 |
module adder16 #(
parameter DATA_BITWIDTH = 16
) (
input [DATA_BITWIDTH-1:0] in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
in8,
in9,
in10,
in11,
in12,
in13,
in14,
in15,
output [DATA_BITWIDTH-1:0] out
);
assign out = in0+ in1+ in2+ in3+ in4+ in5+ in6+ in7+ in8+ in9+ in10+ in11+ in12+ in13+ in14+ in15;
endmodule
| 8.066423 |
module adder16b (
input [15:0] in_a,
input [15:0] in_b,
input op,
output reg [15:0] o
);
always @(in_a, in_b, op) begin
if (op == 0) begin
o = in_a + in_b;
end else begin
o = in_a - in_b;
end
end
endmodule
| 7.364985 |
module ADDER16BIT (
data_out,
data0,
data1
);
parameter n = 16; // multiplicand width size
output [n:0] data_out;
input [n-1:0] data0, data1;
assign data_out = {1'b0, data0} + {1'b0, data1};
endmodule
| 7.328254 |
module Adder16Test (
input iClock,
input signed [15:0] A,
input signed [15:0] B,
output signed [15:0] C
);
reg signed [15:0] a, b, c;
assign C = c;
always @(posedge iClock) begin
a <= A;
b <= B;
c <= a + b;
end
endmodule
| 7.134141 |
module adder16_17 (
input [0:15] A,
input [0:15] B,
output [0:16] Out
);
assign Out = A + B;
endmodule
| 6.953224 |
module cla_testbench;
reg [15:0] a, b;
reg cin;
wire [15:0] sum;
wire cout;
sixteenbit_sklansky_adder ssa (
sum[15:0],
cout,
a[15:0],
b[15:0]
);
initial begin
$display(" a + b = sum , carryout");
end
initial begin
a = 'b1111111111111111;
b = 'b1111111111111111;
#30 a = 'b0000000000000000;
b = 'b1111111111111111;
#30 a = 'b1010101010101010;
b = 'b0101010101010101;
#30 a = 'b1100110011001100;
b = 'b1100000000000110;
#30 a = 'b1100110011001100;
b = 'b0000000000000000;
#30 a = 'b1000000000000000;
b = 'b1000000000000000;
#30 a = 'b0000;
b = 'b00111;
end
initial begin
$monitor(" %b + %b = %b cout= %b ", a[15:0], b[15:0], sum[15:0], cout);
end
endmodule
| 6.678521 |
module adder17 (
input signed [16:0] a,
input signed [16:0] b,
output signed [17:0] s
);
assign s = a + b;
endmodule
| 7.230211 |
module adder17_18 (
input [0:16] A,
input [0:16] B,
output [0:17] Out
);
assign Out = A + B;
endmodule
| 6.739915 |
module adder18_19 (
input [0:17] A,
input [0:17] B,
output [0:18] Out
);
assign Out = A + B;
endmodule
| 6.872859 |
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