code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENBUFX2 (
input A,
output Y
);
assign Y = A;
endmodule
| 6.850249 |
module PDKGENXNOR2X1 (
input A,
input B,
output Y
);
assign Y = ~(A ^ B);
endmodule
| 8.39041 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENINVX1 (
input A,
output Y
);
assign Y = ~A;
endmodule
| 7.577469 |
module PDKGENNOR2X1 (
input A,
input B,
output Y
);
assign Y = ~(A | B);
endmodule
| 7.795351 |
module PDKGENNAND3X1 (
input A,
input B,
input C,
output Y
);
assign Y = ~((A & B) & C);
endmodule
| 8.198688 |
module PDKGENBUFX2 (
input A,
output Y
);
assign Y = A;
endmodule
| 6.850249 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENINVX1 (
input A,
output Y
);
assign Y = ~A;
endmodule
| 7.577469 |
module PDKGENNOR2X1 (
input A,
input B,
output Y
);
assign Y = ~(A | B);
endmodule
| 7.795351 |
module PDKGENNOR3X1 (
input A,
input B,
input C,
output Y
);
assign Y = ~((A | B) | C);
endmodule
| 6.941576 |
module PDKGENBUFX2 (
input A,
output Y
);
assign Y = A;
endmodule
| 6.850249 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module PDKGENMUX2X1 (
input A,
input B,
input S,
output Y
);
assign Y = (A & ~S) | (B & S);
endmodule
| 8.673181 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENINVX1 (
input A,
output Y
);
assign Y = ~A;
endmodule
| 7.577469 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
module PDKGENOR2X1 (
input A,
input B,
output Y
);
assign Y = A | B;
endmodule
| 8.143174 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENXOR2X1 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.46634 |
module add9 (
dataa,
datab,
cout,
overflow,
result
);
input [8:0] dataa;
input [8:0] datab;
output cout;
output overflow;
output [8:0] result;
wire sub_wire0;
wire sub_wire1;
wire [8:0] sub_wire2;
wire overflow = sub_wire0;
wire cout = sub_wire1;
wire [8:0] result = sub_wire2... | 6.721821 |
module add9 (
dataa,
datab,
cout,
overflow,
result
);
input [8:0] dataa;
input [8:0] datab;
output cout;
output overflow;
output [8:0] result;
endmodule
| 6.721821 |
module addalu (
valorEstendidoDeslocado,
pcincrementado,
Addresult
);
input [31:0] valorEstendidoDeslocado, pcincrementado;
output [31:0] Addresult;
assign Addresult = valorEstendidoDeslocado + pcincrementado;
endmodule
| 7.11169 |
module AddAnd (
input [11:0] A,
input [11:0] B,
input CI,
input OE_ADD,
input OE_AND,
output [11:0] S,
output CO
);
wire [12:0] sum;
assign sum = A + B + {12'b0, CI};
assign S = OE_ADD ? sum[11:0] : OE_AND ? A & B : 12'b0;
assign CO = OE_ADD ? sum[12] : 1'b0;
endmodule
| 6.643152 |
module addat (
input wire adclk,
input wire adsfl,
input wire advs,
input wire adhs,
input wire adfield,
input wire [19:0] addat,
output reg inde,
output reg [24:0] indat
);
reg [39:0] sr;
reg [1:0] ctr;
reg act;
reg start;
initial begin
start = 0;
end
always @(posed... | 6.670727 |
module addattest;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [23:0] indat; // From addat0 of addat.v
wire inde; // From addat0 of addat.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module i... | 6.624231 |
module adda_out (
input clk,
output wire [7:0] dacdata,
input rst_n //KEY IN PORT
);
wire [7:0] rom_address;
/* ------------------------------------------------------------------
* WAVE RELATED
* ------------------------------------------------------------------- */
wire [7:0] rom_data;
re... | 7.639413 |
module adda_pll_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [2:1] CLK_OUT,
// High bits of counters driven by clocks
output [2:1] COUNT,
// Status and control signals
in... | 7.411442 |
module adda_pll_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.... | 7.318295 |
module addbit (
a, // first input
b, // Second input
ci, // Carry input
sum, // sum output
co // carry output
);
//Input declaration
input a;
input b;
input ci;
//Ouput declaration
output sum;
output co;
//Port Data types
wire a;
wire b;
wire ci;
wire sum;
wire co;
/... | 7.120785 |
module addecrc (
i_clk,
i_ce,
i_en,
i_cancel,
i_v,
i_d,
o_v,
o_d
);
localparam INVERT = 1; // Proper operation requires INVERT=1
input wire i_clk, i_ce, i_en, i_cancel;
input wire i_v;
input wire [3:0] i_d;
output reg o_v;
output reg [3:0] o_d;
reg [ 7:0] r_p;
reg [31... | 6.845018 |
module addepad (
i_clk,
i_ce,
i_cancel,
i_v,
i_d,
o_v,
o_d
);
parameter MINNIBBLES = 120;
localparam LGNCOUNT=(MINNIBBLES<63)? 6
:((MINNIBBLES<127)? 7:((MINNIBBLES<255)? 8:9));
input wire i_clk, i_ce, i_cancel;
input wire i_v; // Valid
input wire [3:0] i_d; // Data nibble
o... | 7.961737 |
module addepreamble (
i_clk,
i_ce,
i_en,
i_cancel,
i_v,
i_d,
o_v,
o_d
);
input wire i_clk, i_ce, i_en, i_cancel;
input wire i_v; // Valid
input wire [3:0] i_d; // Data nibble
output wire o_v;
output wire [3:0] o_d;
reg [84:0] shiftreg;
reg r_v;
reg [3:0] r_d;
initia... | 7.167665 |
module FA16bit (
input [15:0] term,
result,
input flag,
output [15:0] FA_Out
);
assign FA_Out = (~flag) ? (result + term) : (result - term);
endmodule
| 7.262555 |
module adder #(
parameter fcw = 16'd10000
) ( //参数为16位大小 默认参数（10000）
sum,
clk,
rst
);
output [15:0] sum; //输出地址
input clk;
input rst;
reg [15:0] sum; //初值
always @(posedge clk)//正沿触发
begin
if (!rst) //复位0有效
sum <= 16'd0;
else sum <= sum + fcw; //求和
end
endmodu... | 9.043323 |
module Adder (
INPUT1,
INPUT2,
OUTPUT
);
input wire [31:0] INPUT1;
input wire [31:0] INPUT2;
output wire [31:0] OUTPUT;
assign OUTPUT = INPUT1 + INPUT2;
endmodule
| 7.280733 |
module Adder (
input clock,
input reset,
input [31:0] io_inputx,
input [31:0] io_inputy,
output [31:0] io_result
);
assign io_result = io_inputx + io_inputy;
endmodule
| 7.642138 |
module Adder #(
parameter OPERAND_WIDTH = 32
) (
y,
op1,
op2
);
input [OPERAND_WIDTH - 1 : 0] op1;
input [OPERAND_WIDTH - 1 : 0] op2;
output [OPERAND_WIDTH - 1 : 0] y;
assign y = op1 + op2;
endmodule
| 9.509237 |
module add_1p (
x,
y,
sum,
clk
);
parameter WIDTH = 16, // Total bit width
LSB_WIDTH = 8, // Bit width of LSBs
MSB_WIDTH = 8; // Bit width of MSBs
input [WIDTH-1:0] x, y; // Inputs
output [WIDTH-1:0] sum; // Result
input clk; // Clock
reg [LSB_WIDTH-1:0] l1, l2; // LSBs of input... | 6.645901 |
module lpm_ff #(
parameter WIDTH = 1
) (
input [WIDTH-1:0] data,
output reg [WIDTH-1:0] q,
input clock
);
always @(posedge clock) begin
q <= data;
end
endmodule
| 7.074985 |
module lpm_add_sub #(
parameter WIDTH = 1,
parameter ALU = "ADD"
) (
input [WIDTH-1:0] dataa,
input [WIDTH-1:0] datab,
input cin,
output cout,
output [WIDTH-1:0] result
);
reg [WIDTH:0] temp;
always @* begin
case (ALU)
"ADD": temp = dataa + datab + cin;
"SUB": tem... | 7.42875 |
module top_module (
input [99:0] a,
b,
input cin,
output cout,
output [99:0] sum
);
// method 1
reg [100:0] result;
assign result = a[99:0] + b[99:0] + cin;
assign sum = result[99:0];
assign cout = result[100];
// method 2
wire [98:0] carry;
full_adder u_full_adder_0 (
a[0],... | 7.203305 |
module top_module (
input [99:0] a,
b,
input cin,
output cout,
output [99:0] sum
);
assign {cout, sum} = a + b + cin;
endmodule
| 7.203305 |
module top_module (
input [99:0] a,
b,
input cin,
output [99:0] cout,
output [99:0] sum
);
always @(*) begin
sum[0] = a[0] ^ b[0] ^ cin;
cout[0] = (a[0] & b[0]) | ((a[0] ^ b[0]) & cin);
for (integer i = 1; i < 100; i++) begin
sum[i] = a[i] ^ b[i] ^ cout[i-1];
cout[i] = (... | 7.203305 |
module adder16 #(
parameter DATA_BITWIDTH = 16
) (
input [DATA_BITWIDTH-1:0] in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
in8,
in9,
in10,
in11,
in12,
in13,
in14,
in15,
output [DATA_BITWIDTH-1:0] out
);
assign out = in0+ in1+ in2+ in3+ in4+ in5+ in6+... | 8.066423 |
module adder16b (
input [15:0] in_a,
input [15:0] in_b,
input op,
output reg [15:0] o
);
always @(in_a, in_b, op) begin
if (op == 0) begin
o = in_a + in_b;
end else begin
o = in_a - in_b;
end
end
endmodule
| 7.364985 |
module ADDER16BIT (
data_out,
data0,
data1
);
parameter n = 16; // multiplicand width size
output [n:0] data_out;
input [n-1:0] data0, data1;
assign data_out = {1'b0, data0} + {1'b0, data1};
endmodule
| 7.328254 |
module Adder16Test (
input iClock,
input signed [15:0] A,
input signed [15:0] B,
output signed [15:0] C
);
reg signed [15:0] a, b, c;
assign C = c;
always @(posedge iClock) begin
a <= A;
b <= B;
c <= a + b;
end
endmodule
| 7.134141 |
module adder16_17 (
input [0:15] A,
input [0:15] B,
output [0:16] Out
);
assign Out = A + B;
endmodule
| 6.953224 |
module cla_testbench;
reg [15:0] a, b;
reg cin;
wire [15:0] sum;
wire cout;
sixteenbit_sklansky_adder ssa (
sum[15:0],
cout,
a[15:0],
b[15:0]
);
initial begin
$display(" a + b = sum , carryout");
end
initial begin
a = 'b1111111111111111;
b = 'b1111111111111111;
... | 6.678521 |
module adder17 (
input signed [16:0] a,
input signed [16:0] b,
output signed [17:0] s
);
assign s = a + b;
endmodule
| 7.230211 |
module adder17_18 (
input [0:16] A,
input [0:16] B,
output [0:17] Out
);
assign Out = A + B;
endmodule
| 6.739915 |
module adder18_19 (
input [0:17] A,
input [0:17] B,
output [0:18] Out
);
assign Out = A + B;
endmodule
| 6.872859 |
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