code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module adder19 (
input signed [18:0] a,
input signed [18:0] b,
output signed [19:0] s
);
assign s = a + b;
endmodule
| 6.846397 |
module adder19_20 (
input [0:18] A,
input [0:18] B,
output [0:19] Out
);
assign Out = A + B;
endmodule
| 7.854083 |
module Adder1b (
input wire A,
B,
Ci,
output wire S,
Co
);
wire gen, p_and_ci, prop;
assign prop = A ^ B;
assign S = prop ^ Ci;
assign gen = A & B;
assign p_and_ci = prop & Ci;
assign Co = gen | p_and_ci;
endmodule
| 7.060511 |
module adder1 (
dataa,
datab,
result
);
input [15:0] dataa;
input [15:0] datab;
output [15:0] result;
endmodule
| 7.322982 |
module adder2 #(
parameter DATA_BITWIDTH = 16
) (
input [DATA_BITWIDTH-1:0] left,
right,
output [DATA_BITWIDTH-1:0] out
);
assign out = left + right;
endmodule
| 8.897197 |
module Adder20 (
input [20:0] a,
input [20:0] b,
input c_in,
output c_out,
output [20:0] out
);
assign {c_out, out} = a + b + c_in;
endmodule
| 7.598417 |
module adder22 (
input signed [19:0] a,
input signed [21:0] b,
output signed [22:0] s
);
assign s = a + b;
endmodule
| 7.262047 |
module adder24 (
a,
b,
sum
);
input [23:0] a, b;
output [23:0] sum;
wire [23:0] sum;
assign sum = a + b;
endmodule
| 6.585162 |
module is same with IP c_addsub_v12 in function and utilization
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module adder28_un(A, B, CLK, CE, SCLR, S);
input [27:0]A;
input [27:0]B... | 6.593332 |
module adder2bit #(
parameter DW = 2
) (
input [DW-1:0] a_in,
input [DW-1:0] b_in,
output [ DW:0] o_sum
);
reg r_c0;
reg r_s1;
assign o_sum[0] = a_in[0] ^ b_in[0];
assign r_c0 = a_in[0] & b_in[0];
assign r_s1 = a_in[1] ^ b_in[1];
assign o_sum[1] = r_s1 ^ r_c0;
assign o_sum[2] = a_in[... | 6.557265 |
module notgate (
s,
a
);
input a;
output s;
nand AND1 (s, a, a);
endmodule
| 7.575943 |
module masterAdder (
s0,
s1,
s2,
s3,
a0,
b0,
a1,
b1,
a2,
b2
);
input a0, b0, a1, b1, a2, b2;
output s0, s1, s2, s3;
halfadder HA1 (
s0,
sa,
a0,
b0
);
fullAdder FA1 (
s1,
sb,
a1,
b1,
sa
);
fullAdder FA2 (
... | 6.500378 |
module adder3 #(
parameter DATA_BITWIDTH = 16
) (
input [DATA_BITWIDTH-1:0] in0,
in1,
in2,
output [DATA_BITWIDTH-1:0] out
);
assign out = in0 + in1 + in2;
endmodule
| 7.561541 |
module Adder32 (
c_out,
sum,
a,
b,
c_in
);
input [31:0] a;
input [31:0] b;
input c_in;
output c_out;
output [31:0] sum;
wire carry_out1;
Adder16 A1 (
carry_out1,
sum[15:0],
a[15:0],
b[15:0],
c_in
);
Adder16 A2 (
c_out,
sum[31:16],
a... | 7.953506 |
module adder (
si,
xout,
a,
b,
xin
);
input [31:0] a, b;
input [7:0] xin;
output [32:0][7:0] x;
integer i = 0;
output reg [7:0] ym;
output [7:0] xout;
output [31:0][7:0] y;
output reg [31:0] si;
kpgg kpg_0 (
x[8:1],
a[7:0],
b[7:0]
);
kpgg kpg_1 (
x[1... | 7.276647 |
module Adder32b (
input [31:0] A,
input [31:0] B,
input Ci,
input Ctrl,
output [31:0] S,
output CF,
OF,
ZF,
SF,
PF, // 符号SF、进位CF、溢出OF、零标志ZF、奇偶PF
output SLTu,
SLT
);
AddSub32bFlag addsub (
A,
B,
Ci,
Ctrl,
S,
CF,
OF,
ZF,
... | 6.696557 |
module Adder32bits #(
parameter NBits = 32
) (
input [NBits-1:0] Data0,
input [NBits-1:0] Data1,
output [NBits-1:0] Result
);
assign Result = Data1 + Data0;
endmodule
| 9.181608 |
module Adder32b (
input [31:0] A,
B,
input SUB,
output COUT,
output [31:0] S
);
wire [31:0] C;
wire C1, C2, C3;
/* XOR entre cada bit de B e o SUB, responsável por complementar B caso SUB = 1*/
assign C = B ^ {32{SUB}};
/* Sequencia de Carry Look-Ahead Adders de 8 bits, interligados de m... | 6.696557 |
module Adder32b_TB ();
reg [31:0] A, B, correctS;
reg [32:0] Sum; // Variável responsável por armazenar a soma A + B ou A + (-B)
reg SUB, correctCOUT;
wire [31:0] S;
wire COUT;
integer i, j, errors;
// task que verifica se a saída do módulo é igual ao valor esperado*/
task Check;
input [31:0] xpec... | 7.407299 |
module adder32_4 (
a,
b,
sum
);
input [31:0] a, b;
output [32:0] sum;
wire c1, c2, c3, c4, c5, c6, c7, c8;
blockSize4 b0 (
a[3:0],
b[3:0],
1'b0,
sum[3:0],
c1
);
blockSize4 b1 (
a[7:4],
b[7:4],
c1,
sum[7:4],
c2
);
blockSize4 b2 (
... | 6.522919 |
module adder32 (
a,
b,
r
);
input [31:0] a, b;
output [32:0] r;
assign r[32:16] = a[31:16] + b[31:16];
assign r[15:0] = a[15:0] | b[15:0];
endmodule
| 8.194085 |
module adder32_artix7 (
input clk, // clock
input [31: 0] a, // operand input
input [31: 0] b, // operand input
output [31: 0] s, // sum output
input c_in, // carry input
output c_out // carry output
);
//
// Lower and higher parts of operand
//
wire [17:0] bl = b[17:0];
w... | 6.502268 |
module adder32_generic (
input clk, // clock
input [31: 0] a, // operand input
input [31: 0] b, // operand input
output [31: 0] s, // sum output
input c_in, // carry input
output c_out // carry output
);
//
// Sum
//
reg [32:0] s_int;
always @(posedge clk) s_int <= {1'b0,... | 6.62168 |
module cla_testbench;
reg [31:0] a, b;
reg cin;
reg clk;
wire [31:0] sum;
wire cout;
thirtytwo_bit_Recursive_Carry_Adder adder (
sum[31:0],
cout,
a[31:0],
b[31:0],
clk
);
initial begin
$display("\t\t\t\t a + b = sum , carryout");
end
initial begin
clk = 1;
... | 6.678521 |
module adder32_wrapper (
input clk, // clock
input [31: 0] a, // operand input
input [31: 0] b, // operand input
output [31: 0] s, // sum output
input c_in, // carry input
output c_out // carry output
);
//
// Include Primitive Selector
//
`include "ecdsa_lowlevel_settings.v... | 6.523789 |
module adder36 (
input [35:0] a,
input [35:0] b,
output [35:0] s
);
assign s = a + b;
endmodule
| 6.894171 |
module Adder3bit (
A,
B,
sum,
cy
);
input [2:0] A, B;
output [2:0] sum;
output cy;
wire w1, w2;
FullAdder M1 (
A[0],
B[0],
1'b0,
sum[0],
w1
);
FullAdder M2 (
A[1],
B[1],
w1,
sum[1],
w2
);
FullAdder M3 (
A[2],
B[2... | 7.769292 |
module adder3 #(
parameter N = 16
) (
input clk,
input rst,
input [N-1:0] A,
input [N-1:0] B,
input [N-1:0] C,
output reg [N-1:0] D
);
always @(posedge clk or posedge rst) begin
if (rst) begin
D = 0;
end else begin
D = A + B + C... | 7.561541 |
module FullAdder (
input io_a,
input io_b,
input io_cin,
output io_sum,
output io_cout
);
wire a_xor_b = io_a ^ io_b; // @[FullAdder.scala 16:22]
wire a_and_b = io_a & io_b; // @[FullAdder.scala 19:22]
wire b_and_cin = io_b & io_cin; // @[FullAdder.scala 20:24]
wire a_and_cin = io_a & ... | 7.610141 |
module Adder4 (
input clock,
input reset,
input [3:0] io_A,
input [3:0] io_B,
input io_Cin,
output [3:0] io_Sum,
output io_Cout
);
wire Adder0_io_a; // @[Adder4.scala 17:22]
wire Adder0_io_b; // @[Adder4.scala 17:22]
wire Adder0_io_cin; // @[Adder4.scala... | 7.84746 |
module adder47_artix7 (
input clk, // clock
input [46: 0] a, // operand input
input [46: 0] b, // operand input
output [46: 0] s // sum output
);
//
// Lower and higher parts of operand
//
wire [17:0] bl = b[17:0];
wire [28:0] bh = b[46:18];
//
// DSP48E1 Slice
//
/* Operation ... | 6.830874 |
module adder4a (
A,
B,
C
);
input [3:0] A;
input [3:0] B;
output [3:0] C;
wire [3:0] c;
ha f (
A[0],
B[0],
C[0],
c[0]
);
fa f1 (
A[1],
B[1],
c[0],
C[1],
c[1]
);
fa f2 (
A[2],
B[2],
c[1],
C[2],
c[2]
);... | 6.768537 |
module adder4a_top (
input wire clk,
input wire btn,
input wire [7:0] sw,
output wire [6:0] a_to_g,
output wire [3:0] an,
output wire dp
);
wire [15:0] x;
wire cf;
wire [3:0] s;
assign x[15:12] = sw[7:4];
assign x[11:8] = sw[3:0];
assign x[7:4] = {3'b000, cf};
assign x[3:0] = ... | 6.80645 |
module Adder4b (
input wire [3:0] A,
input wire [3:0] B,
input wire Ci,
output wire [3:0] S,
output wire Co
);
wire c1, c2, c3;
Adder1b a1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(c1)
);
Adder1b a2 (
.A (A[1]),
.B (B[1]),
.Ci(c1),
... | 6.623844 |
module adder_4bit (
AA,
BB,
SS,
CC
);
input [3:0] AA, BB;
output [3:0] SS;
output CC;
wire [4:1] C;
assign CC = C[4];
adder_1bit A1 (
AA[0],
BB[0],
1'b0,
SS[0],
C[1]
);
adder_1bit A2 (
AA[1],
BB[1],
C[1],
SS[1],
C[2]
);
... | 9.041993 |
module adder_tb;
reg [7:0] stim;
wire [3:0] Sum;
wire Carry_Out;
adder_4bit DUT (
stim[3:0],
stim[7:4],
Sum,
Carry_Out
);
initial begin
stim = 8'b0;
repeat (100) begin
#20 stim = $random;
end
#10;
end
initial $monitor("Stim:%b Sum:%b CO:%b", stim, Sum, C... | 6.543655 |
module adder4bit (
A,
B,
cin,
S,
cout
);
input [3:0] A;
input [3:0] B;
input cin;
output [3:0] S;
output cout;
wire c0, c1, c2;
adder a0 (
.a(A[0]),
.b(B[0]),
.cin(cin),
.s(S[0]),
.cout(c0)
);
adder a1 (
.a(A[1]),
.b(B[1]),
.cin(c0... | 6.983906 |
module adder (
a,
b,
cin,
s,
cout
);
input a, b, cin;
output s, cout;
assign s = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));
endmodule
| 7.4694 |
module adder4bitFPGA (
SW,
LEDR
);
input [9:0] SW;
output [9:0] LEDR;
adder4bit a (
.A(SW[7:4]),
.B(SW[3:0]),
.cin(SW[8]),
.S(LEDR[3:0]),
.cout(LEDR[4])
);
endmodule
| 7.659715 |
module adder4bit (
A,
B,
cin,
S,
cout
);
input [3:0] A;
input [3:0] B;
input cin;
output [3:0] S;
output cout;
wire c0, c1, c2;
adder a0 (
.a(A[0]),
.b(B[0]),
.cin(cin),
.s(S[0]),
.cout(c0)
);
adder a1 (
.a(A[1]),
.b(B[1]),
.cin(c0... | 6.983906 |
module adder (
a,
b,
cin,
s,
cout
);
input a, b, cin;
output s, cout;
assign s = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));
endmodule
| 7.4694 |
module adder4b_test ();
reg [3:0] in1, in2;
reg carryIn;
wire [3:0] out;
wire carryOut;
ADDER4B dut (
carryIn,
in1,
in2,
out,
carryOut
);
initial begin
// carryIn: 0, in1: 0000, in2: 0000 => out: 0000, carryOut: 0
carryIn = 0;
in1 = 4'b0000;
in2 = 4'b0000;
... | 6.573767 |
module adder4_2comp (
input [127:0] A1,
input [127:0] A2,
input [127:0] A3,
input [127:0] A4,
output [127:0] S1,
output [127:0] S2
);
wire [127:0] w1, w2;
carrySaveAdder fa1 (
A1,
A2,
A3,
w1,
w2
);
carrySaveAdder fa2 (
A4,
w1,
w2,
... | 7.695701 |
module adder4_32 (
data0x,
data1x,
data2x,
data3x,
result
);
input [31:0] data0x;
input [31:0] data1x;
input [31:0] data2x;
input [31:0] data3x;
output [33:0] result;
wire [ 33:0] sub_wire5;
wire [ 31:0] sub_wire4 = data3x[31:0];
wire [ 31:0] sub_wire3 = data2x[31:0];
wire [ 31:0... | 6.96667 |
module adder5_2comp (
input [31:0] A1,
input [31:0] A2,
input [31:0] A3,
input [31:0] A4,
input [31:0] A5,
output [31:0] S1,
output [31:0] S2
);
wire [31:0] w1, w2, w3, w4;
carrySaveAdder csa1 (
A1,
A2,
A3,
w1,
w2
);
carrySaveAdder csa2 (
A4... | 7.058341 |
module adder6 (
a,
b,
sum
);
input [5:0] a, b;
output [5:0] sum;
wire [5:0] sum;
assign sum = a + b;
endmodule
| 7.069424 |
module Adder64 (
c_out,
sum,
a,
b,
c_in
);
input [63:0] a;
input [63:0] b;
input c_in;
output [63:0] sum;
output c_out;
wire carry_out1, carry_out2, carry_out3;
Adder16 A1 (
carry_out1,
sum[15:0],
a[15:0],
b[15:0],
c_in
);
Adder16 A2 (
carry_ou... | 6.919409 |
module adder (
si,
xout,
a,
b,
xin
);
input [63:0] a, b;
input [7:0] xin;
output [64:0][7:0] x;
integer i = 0;
output reg [7:0] ym;
output [7:0] xout;
output [63:0][7:0] y;
output reg [63:0] si;
kpgg kpg_0 (
x[8:1],
a[7:0],
b[7:0]
);
kpgg kpg_1 (
x[1... | 7.276647 |
module adder6bit (
sum,
cout,
in1,
in2
);
output [5:0] sum;
output cout;
input [5:0] in1, in2;
wire cout0, cout1, cout2, cout3, cout4;
adder1bit add0 (
sum[0],
cout0,
in1[0],
in2[0],
1'b0
);
adder1bit add1 (
sum[1],
cout1,
in1[1],
i... | 7.483619 |
module adder7bit (
sum,
cout,
in1,
in2
);
output [6:0] sum;
output cout;
input [6:0] in1, in2;
wire cout0, cout1, cout2, cout3, cout4, cout5;
adder1bit add0 (
sum[0],
cout0,
in1[0],
in2[0],
1'b0
);
adder1bit add1 (
sum[1],
cout1,
in1[1],
... | 7.640212 |
module adder (
s,
co,
a,
b,
ci
);
output s, co; //Outputs of Sum and Carry Out
input a, b, ci; //Inputs of A, b and Carry In
wire o0, o1, o2; //Internal wiring
xor (s, a, b, ci); //Calculation of Sum
or (o0, a, b); //Calculation of Carry Out
or (o1, b, ci);
or (o2, ci, a);
a... | 7.276647 |
module adder7 (
s,
co,
a,
b,
ci
);
output [6:0] s; //7-bit Sum output
output co; //Output bit of Carry out
input [6:0] a, b; //7-bit Input A and B
input ci; //Input bit of Carry in
wire c1, c2, c3, c4, c5, c6;
adder a0 (
s[0],
c1,
a[0],
b[0],
ci
);
... | 7.475421 |
module adder7_8 (
s,
co,
a,
b,
c,
d,
e,
f,
g,
h,
ci
);
output [6:0] s;
output co;
input [6:0] a, b, c, d, e, f, g, h;
input ci;
wire [6:0] s1, s2, s3, s4, s5, s6;
wire co1, co2, co3, co4, co5, co6;
adder7 a0 (
s1,
co1,
a,
b,
ci
... | 7.416022 |
module adder8 (
a,
b,
sum
);
input [7:0] a, b;
output [7:0] sum;
wire [7:0] sum;
assign sum = a + b;
endmodule
| 6.980581 |
module tb_Adder8bit ();
reg [7:0] A, B;
reg Ci;
wire [7:0] Sum, Co;
Adder8bit b (
Sum,
Co,
A,
B,
Ci
);
initial begin
end
endmodule
| 6.609884 |
module Adder8bit (
S,
Cout,
A,
B,
Cin
);
input [7:0] A, B;
input Cin;
output [7:0] S, Cout;
full_adder UO (
S[0],
Cout[0],
A[0],
B[0],
Cin
);
full_adder U1 (
S[1],
Cout[1],
A[1],
B[1],
Cout[0]
);
full_adder U2 (
S[2],
... | 6.844801 |
module adder8_4 (
x,
y,
add
);
input [7:0] x, y;
output [8:0] add;
wire c1;
blockSize4 b1 (
x[3:0],
y[3:0],
1'b0,
add[3:0],
c1
);
blockSize4 b2 (
x[7:4],
y[7:4],
c1,
add[7:4],
cout
);
assign add[8] = cout;
endmodule
| 7.202405 |
module adder8_8 (
a,
b,
sum
);
input [7:0] a, b;
output [8:0] sum;
wire c0;
blockSize8 b0 (
a[7:0],
b[7:0],
1'b0,
sum[7:0],
c0
);
assign sum[8] = c0;
endmodule
| 6.879971 |
module: full_adder_8bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module adder8_bitTest;
// Inputs
reg [7:0] a;
reg [7:0] b;
// Outputs
wire cout;
wire [7:0] s;
// Instantia... | 7.25697 |
module adder9 (
input [8:0] a,
input [8:0] b,
output [8:0] s
);
assign s = a + b;
endmodule
| 6.834286 |
module adderB (
input [31:0] in1,
input [31:0] in2,
output [31:0] out
);
assign out = in1 + in2;
endmodule
| 7.260942 |
module AdderBasic #(
parameter WIDTH = 32 // ӷλ
) (
input CI, // 1λλ
input [WIDTH - 1 : 0] A, // (WIDTH)λA
input [WIDTH - 1 : 0] B, // (WIDTH)λB
output [WIDTH - 1 : 0] S, // (WIDTH)λS
output [WIDTH - 1 : 0] C // (WIDTH)λλC
);
// ȼAdderUnitҪ
localparam integer U... | 7.402408 |
module adderCircuit (
LEDR,
SW
);
input [9:0] SW;
output [9:0] LEDR;
wire c1;
wire c2;
wire c3;
wire c4;
fullAdder u0 (
.A(SW[4]),
.B(SW[0]),
.cin(SW[8]),
.S(LEDR[0]),
.cout(c1)
);
fullAdder u1 (
.A(SW[5]),
.B(SW[1]),
.cin(c1),
.S(LEDR[1])... | 6.586857 |
module AdderExtModule (
input [15:0] foo,
output [15:0] bar
);
assign bar = foo + 1;
endmodule
| 7.452252 |
module adderFour (
next,
outAddr
);
input [31:0] next;
output reg [31:0] outAddr;
always @(next) begin
outAddr = next + 32'd4;
end
endmodule
| 6.595846 |
module addergen_st #(
parameter NBITS = 16
) (
output [NBITS-1:0] r,
output cout,
input [NBITS-1:0] a,
input [NBITS-1:0] b,
input cin
);
wire [NBITS:0] carry;
assign carry[0] = cin;
genvar k;
generate
for (k = 0; k < NBITS; k = k + 1) begin : blk
fulladder_st FA (
... | 7.475074 |
module AdderL (
add_statusL,
addip1L,
addip2L,
addopL,
addorsubL
);
input add_statusL, addorsubL;
input [39:0] addip1L, addip2L;
output reg [39:0] addopL;
always @(addip1L or addip2L or addorsubL) begin
if (addorsubL == 1'b1) addopL = addip1L - addip2L;
else addopL = addip1L + add... | 6.904073 |
module AdderMacro (
a,
b,
q
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O and parameter declarations
parameter WIDTH = 8;
input wire [WIDTH-1:0] a;
input wire [WIDTH-1:0] b;
output wire [WIDTH-1:0] q;
///////... | 8.306087 |
module AdderMacro4bit (
cin,
a,
b,
q,
cout
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O and parameter declarations
input wire cin;
input wire [3:0] a;
input wire [3:0] b;
output wire [3:0] q;
output wi... | 7.177771 |
module AdderMacroWithInputXors (
a,
b,
ax,
bx,
q
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O and parameter declarations
parameter WIDTH = 8;
input wire [WIDTH-1:0] a;
input wire [WIDTH-1:0] b;
input wi... | 7.352311 |
module AdderMacroWithInputXor4bit (
cin,
a,
b,
ax,
bx,
q,
cout
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O and parameter declarations
input wire cin;
input wire [3:0] a;
input wire [3:0] b;
input... | 7.352311 |
module AdderModule (
PCIn,
PCOut
);
//inputs - Current Program Counter
input [31:0] PCIn;
//Outputs - Next Program Counter (CurrentPC + 4)
output reg [31:0] PCOut;
//Add 4 to get next PC
always @(*) begin
PCOut = PCIn + 4;
end
endmodule
| 7.060307 |
module fixed_adder (
num1,
num2,
result,
overflow
);
input [15:0] num1, num2;
output [15:0] result;
output overflow;
//single assign statement handles fixed additon
assign {overflow, result} = (num1 + num2);
endmodule
| 6.746191 |
module addermux (
c_out,
adder_out,
sub_out,
select
);
input adder_out, sub_out;
input select;
output reg c_out;
always @(*) begin
case (select)
1'b0: c_out = adder_out;
1'b1: c_out = sub_out;
default: c_out = 0;
endcase
end
endmodule
| 6.558569 |
module addern (
carryin,
X,
Y,
S,
carryout
);
parameter n = 32;
input carryin;
input [n-1:0] X, Y;
output [n-1:0] S;
output carryout;
wire [n:0] C;
genvar k;
assign C[0] = carryin;
assign carryout = C[n];
generate
for (k = 0; k < n; k = k + 1) begin : fulladd_stage
wir... | 7.682323 |
module AdderNBit #(
parameter N = 4 //Number of bits in adder (default 4)
) (
// Declare input and output ports
input cin,
input [N-1:0] a,
input [N-1:0] b,
output [N-1:0] sum,
output cout
);
wire [N-0:0] carry; //Internal carry signal, N+1 wide to include carry in/ou... | 8.393819 |
module addern_tb;
parameter n = 32;
reg carryin;
reg [n-1:0] X, Y;
wire [n-1:0] S;
wire carryout;
addern a1 (
carryin,
X,
Y,
carryout
);
initial begin
carryin = 0;
X = 32;
Y = 23;
#10 X = 67;
Y = 78;
end
endmodule
| 6.694659 |
module AdderPc (
input [31:0] pcIn,
output reg [31:0] dataOut
);
integer b4;
always @(*) begin
b4 = 3'b100;
case (b4)
3'b100: begin
dataOut = pcIn + b4;
end
endcase
end
initial begin
dataOut = 32'd0;
end
endmodule
| 7.038903 |
module adderPlus #(
parameter N = 8
) (
inputA,
inputB,
Sum,
Carry
);
input [N-1:0] inputA, inputB;
output [N-1:0] Sum;
output Carry;
assign {Carry, Sum} = inputA + inputB;
endmodule
| 7.611791 |
module AdderR (
add_statusR,
addip1R,
addip2R,
addopR,
addorsubR
);
input add_statusR, addorsubR;
input [39:0] addip1R, addip2R;
output reg [39:0] addopR;
always @(addip1R or addip2R or addorsubR) begin
if (addorsubR == 1'b1) addopR = addip1R - addip2R;
else addopR = addip1R + add... | 6.661425 |
module AdderReg (
i_Add1,
i_Add2,
result,
write_enable,
clk,
rst
);
input [63:0] i_Add1;
input [63:0] i_Add2;
output [64:0] result;
input write_enable;
input clk;
input rst;
reg [64:0] Temp;
ripple_adder #(64) adder (
i_Add1,
i_Add2,
Temp
);
Register RReg (
... | 6.796054 |
module adderStage5_2 (
input [20:0] input1,
input [20:0] input2,
output reg [21:0] output1,
input enable,
input clk,
output reg done
);
always @(posedge clk) begin
if (enable) begin
output1 <= {input1[20], input1} + {input2[20], input2};
done <= 1'b1;
end else begin
... | 6.614071 |
module AdderStage7 (
m447,
m448,
m449,
m450,
m451,
m452,
m453,
m454,
m455,
m456,
m457,
m458,
m459,
m460,
m461,
m462,
m463,
m464,
m465,
m466,
m467,
m468,
m469,
m470,
m471,
m472,
m473,
m474,
m475,
m476,... | 6.891576 |
module addersub (
opB,
opA,
op,
result_slt,
result
);
//parameter WIDTH=32;
//`DEFINE WIDTH 32
input [31:0] opA;
input [31:0] opB;
//input carry_in;
input [2:0] op;
output result_slt;
output [31:0] result;
wire [32:0] sum;
wire addsub;
wire useless;
assign useless = o... | 7.127372 |
module mux2to1 (
V,
W,
Sel,
F
);
parameter k = 8;
input [k-1:0] V, W;
input Sel;
output [k-1:0] F;
reg [k-1:0] F;
always @(V or W or Sel)
if (Sel == 0) F = V;
else F = W;
endmodule
| 7.107199 |
module adderk (
carryin,
X,
Y,
S,
carryout
);
parameter k = 8;
input carryin;
input [k-1:0] X, Y;
output [k-1:0] S;
output carryout;
reg [k-1:0] S;
reg carryout;
always @(X or Y or carryin) {carryout, S} = X + Y + carryin;
endmodule
| 7.424977 |
module mux2to1 (
V,
W,
Selm,
F
);
parameter k = 8;
input [k-1:0] V, W;
input Selm;
output [k-1:0] F;
reg [k-1:0] F;
always @(V or W or Selm)
if (Selm == 0) F = V;
else F = W;
endmodule
| 7.107199 |
module AdderSubtractor32x32 (
input [31:0] A, // input [2's complement 32 bits]
input [31:0] B, // input [2's complement 32 bits]
input sel, // input [add:sel=0 || sub:sel=1]
output [31:0] S // output [2's complement 32 bits]
);
// if sel = 0 then add else subtract
/* write ... | 7.160384 |
module AdderSubtractor4BitWithoutDelay (
input [3:0] A,
input [3:0] B,
input sel,
output [3:0] S,
output cout
);
wire cout1, cout2, cout3;
fullAdder ASD0 (
.a(A[0]),
.b(B[0]),
.cin(sel),
.sel(sel),
.sum(S[0]),
.cout(cout1)
);
fullAdder ASD1 (
.a(A[1... | 7.160384 |
module addersub (
opA,
opB,
op,
result,
result_slt
);
parameter WIDTH = 32;
input [WIDTH-1:0] opA;
input [WIDTH-1:0] opB;
//input carry_in;
input [3-1:0] op;
output [WIDTH-1:0] result;
output result_slt;
wire carry_out;
wire [WIDTH:0] sum;
// Mux between sum, and slt
wire... | 7.127372 |
module Adders_t;
reg a = 1'b0;
reg b = 1'b0;
reg cin = 1'b0;
wire ha_sum, ha_cout;
wire fa_sum, fa_cout;
Half_Adder ha (
.a(a),
.b(b),
.cout(ha_cout),
.sum(ha_sum)
);
Full_Adder fa (
.a(a),
.b(b),
.cin(cin),
.cout(fa_cout),
.sum(fa_sum)
);
// ... | 6.63568 |
module addertb;
reg [7:0] a_test, b_test;
wire [7:0] sum_test;
reg cin_test;
wire cout_test;
reg [17:0] test;
integer error_count;
add8 u1 (
a_test,
b_test,
cin_test,
sum_test,
cout_test
);
initial begin
`ifdef vcdplusdump
$vcdpluson;
$vcdplusdeltacycleon;
... | 6.797809 |
module Adder (
input [9:0] io_in0,
input [9:0] io_in1,
output [9:0] io_out
);
assign io_out = io_in0 + io_in1; // @[Adder.scala 17:20]
endmodule
| 7.642138 |
module AdderUnit (
input CI, // 1λλ
input [3 : 0] A, // 4λA
input [3 : 0] B, // 4λB
output [3 : 0] S, // 4λS
output [3 : 0] C // 4λλC
);
CARRY4 CARRY4_inst (
.CO (C), // 4λλ
.O (S[3 : 0]), // 4λ
.CI (CI), ... | 6.761389 |
module adderz #(
parameter n = 32
) (
input [n-1:0] a,
input [n-1:0] b,
output [n-1:0] num
);
assign num = a + b;
endmodule
| 9.214982 |
module Adder_1 (
input clock,
input reset,
input [31:0] io_inputx,
input [31:0] io_inputy,
output [31:0] io_result
);
assign io_result = io_inputx + io_inputy;
endmodule
| 6.969904 |
module adder_1 (
input [3:0] A,
input [3:0] B,
input cin,
output [3:0] S,
output cout
);
wire [3:0] carry;
full_adder A1 (
.A(A[0]),
.B(B[0]),
.cin(cin),
.S(S[0]),
.cout(carry[1])
);
full_adder A2 (
.A(A[1]),
.B(B[1]),
.cin(carry[1]),
.... | 6.607745 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_128 (
cout,
sum,
a,
b,
cin
);
parameter size = 128; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size parameter
input cin;
input [size-1:0] a, b; // 'a' and 'b' use the size parameter
assign {cout, sum} = a + b + cin;
e... | 6.995163 |
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