code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module adder19 (
input signed [18:0] a,
input signed [18:0] b,
output signed [19:0] s
);
assign s = a + b;
endmodule
| 6.846397 |
module adder19_20 (
input [0:18] A,
input [0:18] B,
output [0:19] Out
);
assign Out = A + B;
endmodule
| 7.854083 |
module Adder1b (
input wire A,
B,
Ci,
output wire S,
Co
);
wire gen, p_and_ci, prop;
assign prop = A ^ B;
assign S = prop ^ Ci;
assign gen = A & B;
assign p_and_ci = prop & Ci;
assign Co = gen | p_and_ci;
endmodule
| 7.060511 |
module adder1 (
dataa,
datab,
result
);
input [15:0] dataa;
input [15:0] datab;
output [15:0] result;
endmodule
| 7.322982 |
module adder2 #(
parameter DATA_BITWIDTH = 16
) (
input [DATA_BITWIDTH-1:0] left,
right,
output [DATA_BITWIDTH-1:0] out
);
assign out = left + right;
endmodule
| 8.897197 |
module Adder20 (
input [20:0] a,
input [20:0] b,
input c_in,
output c_out,
output [20:0] out
);
assign {c_out, out} = a + b + c_in;
endmodule
| 7.598417 |
module adder22 (
input signed [19:0] a,
input signed [21:0] b,
output signed [22:0] s
);
assign s = a + b;
endmodule
| 7.262047 |
module adder24 (
a,
b,
sum
);
input [23:0] a, b;
output [23:0] sum;
wire [23:0] sum;
assign sum = a + b;
endmodule
| 6.585162 |
module is same with IP c_addsub_v12 in function and utilization
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module adder28_un(A, B, CLK, CE, SCLR, S);
input [27:0]A;
input [27:0]B;
input CLK;
input CE;
input SCLR;
output reg [27:0]S;
always @(posedge CLK)
if(SCLR)
S <= 0;
else if(CE)
S <= A + B;
endmodule
| 6.593332 |
module adder2bit #(
parameter DW = 2
) (
input [DW-1:0] a_in,
input [DW-1:0] b_in,
output [ DW:0] o_sum
);
reg r_c0;
reg r_s1;
assign o_sum[0] = a_in[0] ^ b_in[0];
assign r_c0 = a_in[0] & b_in[0];
assign r_s1 = a_in[1] ^ b_in[1];
assign o_sum[1] = r_s1 ^ r_c0;
assign o_sum[2] = a_in[1] & b_in[1];
endmodule
| 6.557265 |
module notgate (
s,
a
);
input a;
output s;
nand AND1 (s, a, a);
endmodule
| 7.575943 |
module masterAdder (
s0,
s1,
s2,
s3,
a0,
b0,
a1,
b1,
a2,
b2
);
input a0, b0, a1, b1, a2, b2;
output s0, s1, s2, s3;
halfadder HA1 (
s0,
sa,
a0,
b0
);
fullAdder FA1 (
s1,
sb,
a1,
b1,
sa
);
fullAdder FA2 (
s2,
s3,
a2,
b2,
sb
);
endmodule
| 6.500378 |
module adder3 #(
parameter DATA_BITWIDTH = 16
) (
input [DATA_BITWIDTH-1:0] in0,
in1,
in2,
output [DATA_BITWIDTH-1:0] out
);
assign out = in0 + in1 + in2;
endmodule
| 7.561541 |
module Adder32 (
c_out,
sum,
a,
b,
c_in
);
input [31:0] a;
input [31:0] b;
input c_in;
output c_out;
output [31:0] sum;
wire carry_out1;
Adder16 A1 (
carry_out1,
sum[15:0],
a[15:0],
b[15:0],
c_in
);
Adder16 A2 (
c_out,
sum[31:16],
a[31:16],
b[31:16],
carry_out1
);
endmodule
| 7.953506 |
module adder (
si,
xout,
a,
b,
xin
);
input [31:0] a, b;
input [7:0] xin;
output [32:0][7:0] x;
integer i = 0;
output reg [7:0] ym;
output [7:0] xout;
output [31:0][7:0] y;
output reg [31:0] si;
kpgg kpg_0 (
x[8:1],
a[7:0],
b[7:0]
);
kpgg kpg_1 (
x[16:9],
a[15:8],
b[15:8]
);
kpgg kpg_2 (
x[24:17],
a[23:16],
b[23:16]
);
kpgg kpg_3 (
x[32:25],
a[31:24],
b[31:24]
);
assign x[0] = xin;
ppc ppc_0 (
y[31:0],
x[31:0]
);
always @(*) begin
if (x[32] == "p") begin
if (y[31] == "g") ym = "g";
else ym = "k";
end else ym = x[32];
for (i = 0; i < 32; i = i + 1) begin
if (y[i] == "k") si[i] = (a[i] ^ b[i]) ^ 0;
else si[i] = (a[i] ^ b[i]) ^ 1;
end
end
assign xout = ym;
endmodule
| 7.276647 |
module Adder32b (
input [31:0] A,
input [31:0] B,
input Ci,
input Ctrl,
output [31:0] S,
output CF,
OF,
ZF,
SF,
PF, // 符号SF、进位CF、溢出OF、零标志ZF、奇偶PF
output SLTu,
SLT
);
AddSub32bFlag addsub (
A,
B,
Ci,
Ctrl,
S,
CF,
OF,
ZF,
SF,
PF
);
Comparator32b cmp (
.A(A),
.B(B),
.ZF(),
.SLTu(SLTu),
.SLT(SLT)
);
endmodule
| 6.696557 |
module Adder32bits #(
parameter NBits = 32
) (
input [NBits-1:0] Data0,
input [NBits-1:0] Data1,
output [NBits-1:0] Result
);
assign Result = Data1 + Data0;
endmodule
| 9.181608 |
module Adder32b (
input [31:0] A,
B,
input SUB,
output COUT,
output [31:0] S
);
wire [31:0] C;
wire C1, C2, C3;
/* XOR entre cada bit de B e o SUB, responsável por complementar B caso SUB = 1*/
assign C = B ^ {32{SUB}};
/* Sequencia de Carry Look-Ahead Adders de 8 bits, interligados de modo Ripple Carry */
CLAAdder8b U7_0 (
.A(A[7:0]),
.B(C[7:0]),
.CIN(SUB),
.S(S[7:0]),
.COUT(C1)
); // Sinal SUB ligado diretamente no CIN, para somar 1 do 2's complement caso SUB = 1
CLAAdder8b U15_8 (
.A(A[15:8]),
.B(C[15:8]),
.CIN(C1),
.S(S[15:8]),
.COUT(C2)
);
CLAAdder8b U23_16 (
.A(A[23:16]),
.B(C[23:16]),
.CIN(C2),
.S(S[23:16]),
.COUT(C3)
);
CLAAdder8b U31_24 (
.A(A[31:24]),
.B(C[31:24]),
.CIN(C3),
.S(S[31:24]),
.COUT(COUT)
);
endmodule
| 6.696557 |
module Adder32b_TB ();
reg [31:0] A, B, correctS;
reg [32:0] Sum; // Variável responsável por armazenar a soma A + B ou A + (-B)
reg SUB, correctCOUT;
wire [31:0] S;
wire COUT;
integer i, j, errors;
// task que verifica se a saída do módulo é igual ao valor esperado*/
task Check;
input [31:0] xpectS;
input xpectCOUT;
begin
if (S != xpectS) begin
$display("Error A: %32b, B: %32b, expected %32b, got S: %32b", A, B, xpectS, S);
errors = errors + 1;
end
if (COUT != xpectCOUT) begin
$display("Error A: %32b, B: %32b, expected %b, got COUT: %b", A, B, xpectCOUT, COUT);
errors = errors + 1;
end
end
endtask
// módulo testado
Adder32b UUT (
.A(A),
.B(B),
.SUB(SUB),
.S(S),
.COUT(COUT)
);
initial begin
errors = 0;
SUB = 1; //Parâmetro para teste: 0 para fazer A + B, 1 para A + (-B)
// Laços for que passam por todas as somas possíveis entre os números de 0 a 255
for (i = 0; i < 256; i = i + 1)
for (j = 0; j < 256; j = j + 1) begin
A = i;
B = j;
if (SUB == 0) Sum = A + B;
else Sum = A + (B ^ {(32) {1'b1}}) + 1; // Caso SUB = 1, faz o 2's complement em B
correctS = Sum[31:0];
correctCOUT = Sum[32]; // posição do carry out
#10 Check(correctS, correctCOUT);
end
$display("Finished, got %2d errors", errors);
end
endmodule
| 7.407299 |
module adder32_4 (
a,
b,
sum
);
input [31:0] a, b;
output [32:0] sum;
wire c1, c2, c3, c4, c5, c6, c7, c8;
blockSize4 b0 (
a[3:0],
b[3:0],
1'b0,
sum[3:0],
c1
);
blockSize4 b1 (
a[7:4],
b[7:4],
c1,
sum[7:4],
c2
);
blockSize4 b2 (
a[11:8],
b[11:8],
c2,
sum[11:8],
c3
);
blockSize4 b3 (
a[15:12],
b[15:12],
c3,
sum[15:12],
c4
);
blockSize4 b4 (
a[19:16],
b[19:16],
c4,
sum[19:16],
c5
);
blockSize4 b5 (
a[23:20],
b[23:20],
c5,
sum[23:20],
c6
);
blockSize4 b6 (
a[27:24],
b[27:24],
c6,
sum[27:24],
c7
);
blockSize4 b7 (
a[31:28],
b[31:28],
c7,
sum[31:28],
c8
);
assign sum[32] = c8;
endmodule
| 6.522919 |
module adder32 (
a,
b,
r
);
input [31:0] a, b;
output [32:0] r;
assign r[32:16] = a[31:16] + b[31:16];
assign r[15:0] = a[15:0] | b[15:0];
endmodule
| 8.194085 |
module adder32_artix7 (
input clk, // clock
input [31: 0] a, // operand input
input [31: 0] b, // operand input
output [31: 0] s, // sum output
input c_in, // carry input
output c_out // carry output
);
//
// Lower and higher parts of operand
//
wire [17:0] bl = b[17:0];
wire [13:0] bh = b[31:18];
//
// DSP48E1 Slice
//
/* Operation Mode */
wire [ 3:0] dsp48e1_alumode = 4'b0000;
wire [ 6:0] dsp48e1_opmode = 7'b0110011;
/* Internal Product */
wire [47:0] p_int;
dsp48e1_wrapper dsp_adder (
.clk(clk),
.ce(1'b1),
.carry(c_in),
.alumode(dsp48e1_alumode),
.opmode (dsp48e1_opmode),
.a({{16{1'b0}}, bh}),
.b(bl),
.c({{16{1'b0}}, a}),
.p(p_int)
);
//
// Output Mapping
//
assign s = p_int[31:0];
assign c_out = p_int[32];
endmodule
| 6.502268 |
module adder32_generic (
input clk, // clock
input [31: 0] a, // operand input
input [31: 0] b, // operand input
output [31: 0] s, // sum output
input c_in, // carry input
output c_out // carry output
);
//
// Sum
//
reg [32:0] s_int;
always @(posedge clk) s_int <= {1'b0, a} + {1'b0, b} + {{32{1'b0}}, c_in};
//
// Output
//
assign s = s_int[31:0];
assign c_out = s_int[32];
endmodule
| 6.62168 |
module cla_testbench;
reg [31:0] a, b;
reg cin;
reg clk;
wire [31:0] sum;
wire cout;
thirtytwo_bit_Recursive_Carry_Adder adder (
sum[31:0],
cout,
a[31:0],
b[31:0],
clk
);
initial begin
$display("\t\t\t\t a + b = sum , carryout");
end
initial begin
clk = 1;
forever begin
#1 clk = ~clk;
end
end
initial begin
a = 'b10101010101010101010101010101010;
b = 'b01010101010101010101010101010101;
#2 a = 'b11111111111111111111111111111111;
b = 'b11111111111111111111111111111111;
#2 a = 'b00000000000000000000000000000000;
b = 'b11111111111111111111111111111111;
#2 a = 'b11001100110011001100110011001100;
b = 'b11000000000001100000000000111101;
#50 $finish;
end
initial begin
$monitor("%d - %b + %b = %b cout= %b ", $time, a[31:0], b[31:0], sum[31:0], cout);
end
endmodule
| 6.678521 |
module adder32_wrapper (
input clk, // clock
input [31: 0] a, // operand input
input [31: 0] b, // operand input
output [31: 0] s, // sum output
input c_in, // carry input
output c_out // carry output
);
//
// Include Primitive Selector
//
`include "ecdsa_lowlevel_settings.v"
//
// Instantiate Vendor/Generic Primitive
//
`ADDER32_PRIMITIVE adder32_inst (
.clk(clk),
.a(a),
.b(b),
.s(s),
.c_in(c_in),
.c_out(c_out)
);
endmodule
| 6.523789 |
module adder36 (
input [35:0] a,
input [35:0] b,
output [35:0] s
);
assign s = a + b;
endmodule
| 6.894171 |
module Adder3bit (
A,
B,
sum,
cy
);
input [2:0] A, B;
output [2:0] sum;
output cy;
wire w1, w2;
FullAdder M1 (
A[0],
B[0],
1'b0,
sum[0],
w1
);
FullAdder M2 (
A[1],
B[1],
w1,
sum[1],
w2
);
FullAdder M3 (
A[2],
B[2],
w2,
sum[2],
cy
);
endmodule
| 7.769292 |
module adder3 #(
parameter N = 16
) (
input clk,
input rst,
input [N-1:0] A,
input [N-1:0] B,
input [N-1:0] C,
output reg [N-1:0] D
);
always @(posedge clk or posedge rst) begin
if (rst) begin
D = 0;
end else begin
D = A + B + C;
end
end
endmodule
| 7.561541 |
module FullAdder (
input io_a,
input io_b,
input io_cin,
output io_sum,
output io_cout
);
wire a_xor_b = io_a ^ io_b; // @[FullAdder.scala 16:22]
wire a_and_b = io_a & io_b; // @[FullAdder.scala 19:22]
wire b_and_cin = io_b & io_cin; // @[FullAdder.scala 20:24]
wire a_and_cin = io_a & io_cin; // @[FullAdder.scala 21:24]
assign io_sum = a_xor_b ^ io_cin; // @[FullAdder.scala 17:21]
assign io_cout = a_and_b | b_and_cin | a_and_cin; // @[FullAdder.scala 22:34]
endmodule
| 7.610141 |
module Adder4 (
input clock,
input reset,
input [3:0] io_A,
input [3:0] io_B,
input io_Cin,
output [3:0] io_Sum,
output io_Cout
);
wire Adder0_io_a; // @[Adder4.scala 17:22]
wire Adder0_io_b; // @[Adder4.scala 17:22]
wire Adder0_io_cin; // @[Adder4.scala 17:22]
wire Adder0_io_sum; // @[Adder4.scala 17:22]
wire Adder0_io_cout; // @[Adder4.scala 17:22]
wire Adder1_io_a; // @[Adder4.scala 23:22]
wire Adder1_io_b; // @[Adder4.scala 23:22]
wire Adder1_io_cin; // @[Adder4.scala 23:22]
wire Adder1_io_sum; // @[Adder4.scala 23:22]
wire Adder1_io_cout; // @[Adder4.scala 23:22]
wire Adder2_io_a; // @[Adder4.scala 29:22]
wire Adder2_io_b; // @[Adder4.scala 29:22]
wire Adder2_io_cin; // @[Adder4.scala 29:22]
wire Adder2_io_sum; // @[Adder4.scala 29:22]
wire Adder2_io_cout; // @[Adder4.scala 29:22]
wire Adder3_io_a; // @[Adder4.scala 35:22]
wire Adder3_io_b; // @[Adder4.scala 35:22]
wire Adder3_io_cin; // @[Adder4.scala 35:22]
wire Adder3_io_sum; // @[Adder4.scala 35:22]
wire Adder3_io_cout; // @[Adder4.scala 35:22]
wire [2:0] s2 = {Adder2_io_sum, Adder1_io_sum, Adder0_io_sum}; // @[Cat.scala 29:58]
FullAdder Adder0 ( // @[Adder4.scala 17:22]
.io_a(Adder0_io_a),
.io_b(Adder0_io_b),
.io_cin(Adder0_io_cin),
.io_sum(Adder0_io_sum),
.io_cout(Adder0_io_cout)
);
FullAdder Adder1 ( // @[Adder4.scala 23:22]
.io_a(Adder1_io_a),
.io_b(Adder1_io_b),
.io_cin(Adder1_io_cin),
.io_sum(Adder1_io_sum),
.io_cout(Adder1_io_cout)
);
FullAdder Adder2 ( // @[Adder4.scala 29:22]
.io_a(Adder2_io_a),
.io_b(Adder2_io_b),
.io_cin(Adder2_io_cin),
.io_sum(Adder2_io_sum),
.io_cout(Adder2_io_cout)
);
FullAdder Adder3 ( // @[Adder4.scala 35:22]
.io_a(Adder3_io_a),
.io_b(Adder3_io_b),
.io_cin(Adder3_io_cin),
.io_sum(Adder3_io_sum),
.io_cout(Adder3_io_cout)
);
assign io_Sum = {Adder3_io_sum, s2}; // @[Cat.scala 29:58]
assign io_Cout = Adder3_io_cout; // @[Adder4.scala 40:11]
assign Adder0_io_a = io_A[0]; // @[Adder4.scala 18:22]
assign Adder0_io_b = io_B[0]; // @[Adder4.scala 19:22]
assign Adder0_io_cin = io_Cin; // @[Adder4.scala 20:17]
assign Adder1_io_a = io_A[1]; // @[Adder4.scala 24:22]
assign Adder1_io_b = io_B[1]; // @[Adder4.scala 25:22]
assign Adder1_io_cin = Adder0_io_cout; // @[Adder4.scala 26:17]
assign Adder2_io_a = io_A[2]; // @[Adder4.scala 30:22]
assign Adder2_io_b = io_B[2]; // @[Adder4.scala 31:22]
assign Adder2_io_cin = Adder1_io_cout; // @[Adder4.scala 32:17]
assign Adder3_io_a = io_A[3]; // @[Adder4.scala 36:22]
assign Adder3_io_b = io_B[3]; // @[Adder4.scala 37:22]
assign Adder3_io_cin = Adder2_io_cout; // @[Adder4.scala 38:17]
endmodule
| 7.84746 |
module adder47_artix7 (
input clk, // clock
input [46: 0] a, // operand input
input [46: 0] b, // operand input
output [46: 0] s // sum output
);
//
// Lower and higher parts of operand
//
wire [17:0] bl = b[17:0];
wire [28:0] bh = b[46:18];
//
// DSP48E1 Slice
//
/* Operation Mode */
wire [ 3:0] dsp48e1_alumode = 4'b0000;
wire [ 6:0] dsp48e1_opmode = 7'b0110011;
/* Internal Product */
wire [47:0] p_int;
dsp48e1_wrapper dsp_adder (
.clk(clk),
.ce(1'b1),
.carry(1'b0),
.alumode(dsp48e1_alumode),
.opmode (dsp48e1_opmode),
.a({1'b0, bh}),
.b(bl),
.c({1'b0, a}),
.p(p_int)
);
//
// Output Mapping
//
assign s = p_int[46:0];
endmodule
| 6.830874 |
module adder4a (
A,
B,
C
);
input [3:0] A;
input [3:0] B;
output [3:0] C;
wire [3:0] c;
ha f (
A[0],
B[0],
C[0],
c[0]
);
fa f1 (
A[1],
B[1],
c[0],
C[1],
c[1]
);
fa f2 (
A[2],
B[2],
c[1],
C[2],
c[2]
);
fa f3 (
A[3],
B[3],
c[2],
C[3],
c[3]
);
endmodule
| 6.768537 |
module adder4a_top (
input wire clk,
input wire btn,
input wire [7:0] sw,
output wire [6:0] a_to_g,
output wire [3:0] an,
output wire dp
);
wire [15:0] x;
wire cf;
wire [3:0] s;
assign x[15:12] = sw[7:4];
assign x[11:8] = sw[3:0];
assign x[7:4] = {3'b000, cf};
assign x[3:0] = s;
adder4a A1 (
.a (sw[7:4]),
.b (sw[3:0]),
.s (s),
.cf(cf)
);
x7seg X1 (
.x(x),
.clk(clk),
.clr(btn),
.a_to_g(a_to_g),
.an(an),
.dp(dp)
);
endmodule
| 6.80645 |
module Adder4b (
input wire [3:0] A,
input wire [3:0] B,
input wire Ci,
output wire [3:0] S,
output wire Co
);
wire c1, c2, c3;
Adder1b a1 (
.A (A[0]),
.B (B[0]),
.Ci(Ci),
.S (S[0]),
.Co(c1)
);
Adder1b a2 (
.A (A[1]),
.B (B[1]),
.Ci(c1),
.S (S[1]),
.Co(c2)
);
Adder1b a3 (
.A (A[2]),
.B (B[2]),
.Ci(c2),
.S (S[2]),
.Co(c3)
);
Adder1b a4 (
.A (A[3]),
.B (B[3]),
.Ci(c3),
.S (S[3]),
.Co(Co)
);
endmodule
| 6.623844 |
module adder_4bit (
AA,
BB,
SS,
CC
);
input [3:0] AA, BB;
output [3:0] SS;
output CC;
wire [4:1] C;
assign CC = C[4];
adder_1bit A1 (
AA[0],
BB[0],
1'b0,
SS[0],
C[1]
);
adder_1bit A2 (
AA[1],
BB[1],
C[1],
SS[1],
C[2]
);
adder_1bit A3 (
AA[2],
BB[2],
C[2],
SS[2],
C[3]
);
adder_1bit A4 (
AA[3],
BB[3],
C[3],
SS[3],
C[4]
);
endmodule
| 9.041993 |
module adder_tb;
reg [7:0] stim;
wire [3:0] Sum;
wire Carry_Out;
adder_4bit DUT (
stim[3:0],
stim[7:4],
Sum,
Carry_Out
);
initial begin
stim = 8'b0;
repeat (100) begin
#20 stim = $random;
end
#10;
end
initial $monitor("Stim:%b Sum:%b CO:%b", stim, Sum, Carry_Out);
endmodule
| 6.543655 |
module adder4bit (
A,
B,
cin,
S,
cout
);
input [3:0] A;
input [3:0] B;
input cin;
output [3:0] S;
output cout;
wire c0, c1, c2;
adder a0 (
.a(A[0]),
.b(B[0]),
.cin(cin),
.s(S[0]),
.cout(c0)
);
adder a1 (
.a(A[1]),
.b(B[1]),
.cin(c0),
.s(S[1]),
.cout(c1)
);
adder a2 (
.a(A[2]),
.b(B[2]),
.cin(c1),
.s(S[2]),
.cout(c2)
);
adder a3 (
.a(A[3]),
.b(B[3]),
.cin(c2),
.s(S[3]),
.cout(cout)
);
endmodule
| 6.983906 |
module adder (
a,
b,
cin,
s,
cout
);
input a, b, cin;
output s, cout;
assign s = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));
endmodule
| 7.4694 |
module adder4bitFPGA (
SW,
LEDR
);
input [9:0] SW;
output [9:0] LEDR;
adder4bit a (
.A(SW[7:4]),
.B(SW[3:0]),
.cin(SW[8]),
.S(LEDR[3:0]),
.cout(LEDR[4])
);
endmodule
| 7.659715 |
module adder4bit (
A,
B,
cin,
S,
cout
);
input [3:0] A;
input [3:0] B;
input cin;
output [3:0] S;
output cout;
wire c0, c1, c2;
adder a0 (
.a(A[0]),
.b(B[0]),
.cin(cin),
.s(S[0]),
.cout(c0)
);
adder a1 (
.a(A[1]),
.b(B[1]),
.cin(c0),
.s(S[1]),
.cout(c1)
);
adder a2 (
.a(A[2]),
.b(B[2]),
.cin(c1),
.s(S[2]),
.cout(c2)
);
adder a3 (
.a(A[3]),
.b(B[3]),
.cin(c2),
.s(S[3]),
.cout(cout)
);
endmodule
| 6.983906 |
module adder (
a,
b,
cin,
s,
cout
);
input a, b, cin;
output s, cout;
assign s = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));
endmodule
| 7.4694 |
module adder4b_test ();
reg [3:0] in1, in2;
reg carryIn;
wire [3:0] out;
wire carryOut;
ADDER4B dut (
carryIn,
in1,
in2,
out,
carryOut
);
initial begin
// carryIn: 0, in1: 0000, in2: 0000 => out: 0000, carryOut: 0
carryIn = 0;
in1 = 4'b0000;
in2 = 4'b0000;
#10;
assert (out == 4'b0000 && carryOut == 1'b0) $display("PASSED");
else $display("FAILED (%b, %b)", out, carryOut);
// carryIn: 0, in1: 0101, in2: 0101 => out: 1010, carryOut: 0
carryIn = 0;
in1 = 4'b0101;
in2 = 4'b0101;
#10;
assert (out == 4'b1010 && carryOut == 1'b0) $display("PASSED");
else $display("FAILED (%b, %b)", out, carryOut);
// carryIn: 0, in1: 1010, in2: 1010 => out: 0100, carryOut: 1
carryIn = 0;
in1 = 4'b1010;
in2 = 4'b1010;
#10;
assert (out == 4'b0100 && carryOut == 1'b1) $display("PASSED");
else $display("FAILED (%b, %b)", out, carryOut);
// carryIn: 0, in1: 1111, in2: 1111 => out: 1110, carryOut: 1
carryIn = 0;
in1 = 4'b1111;
in2 = 4'b1111;
#10;
assert (out == 4'b1110 && carryOut == 1'b1) $display("PASSED");
else $display("FAILED (%b, %b)", out, carryOut);
// carryIn: 1, in1: 0000, in2: 0000 => out: 0001, carryOut: 0
carryIn = 1;
in1 = 4'b0000;
in2 = 4'b0000;
#10;
assert (out == 4'b0001 && carryOut == 1'b0) $display("PASSED");
else $display("FAILED (%b, %b)", out, carryOut);
// carryIn: 1, in1: 0101, in2: 0101 => out: 1011, carryOut: 0
carryIn = 1;
in1 = 4'b0101;
in2 = 4'b0101;
#10;
assert (out == 4'b1011 && carryOut == 1'b0) $display("PASSED");
else $display("FAILED (%b, %b)", out, carryOut);
// carryIn: 1, in1: 1010, in2: 1010 => out: 0101, carryOut: 1
carryIn = 1;
in1 = 4'b1010;
in2 = 4'b1010;
#10;
assert (out == 4'b0101 && carryOut == 1'b1) $display("PASSED");
else $display("FAILED (%b, %b)", out, carryOut);
// carryIn: 1, in1: 1111, in2: 1111 => out: 1111, carryOut: 1
carryIn = 1;
in1 = 4'b1111;
in2 = 4'b1111;
#10;
assert (out == 4'b1111 && carryOut == 1'b1) $display("PASSED");
else $display("FAILED (%b, %b)", out, carryOut);
end
endmodule
| 6.573767 |
module adder4_2comp (
input [127:0] A1,
input [127:0] A2,
input [127:0] A3,
input [127:0] A4,
output [127:0] S1,
output [127:0] S2
);
wire [127:0] w1, w2;
carrySaveAdder fa1 (
A1,
A2,
A3,
w1,
w2
);
carrySaveAdder fa2 (
A4,
w1,
w2,
S1,
S2
);
endmodule
| 7.695701 |
module adder4_32 (
data0x,
data1x,
data2x,
data3x,
result
);
input [31:0] data0x;
input [31:0] data1x;
input [31:0] data2x;
input [31:0] data3x;
output [33:0] result;
wire [ 33:0] sub_wire5;
wire [ 31:0] sub_wire4 = data3x[31:0];
wire [ 31:0] sub_wire3 = data2x[31:0];
wire [ 31:0] sub_wire2 = data1x[31:0];
wire [ 31:0] sub_wire0 = data0x[31:0];
wire [127:0] sub_wire1 = {sub_wire4, sub_wire3, sub_wire2, sub_wire0};
wire [ 33:0] result = sub_wire5[33:0];
parallel_add parallel_add_component (
.data (sub_wire1),
.result(sub_wire5)
// synopsys translate_off
, .aclr (),
.clken (),
.clock ()
// synopsys translate_on
);
defparam parallel_add_component.msw_subtract = "NO", parallel_add_component.pipeline = 0,
parallel_add_component.representation = "SIGNED", parallel_add_component.result_alignment =
"LSB", parallel_add_component.shift = 0, parallel_add_component.size = 4,
parallel_add_component.width = 32, parallel_add_component.widthr = 34;
endmodule
| 6.96667 |
module adder5_2comp (
input [31:0] A1,
input [31:0] A2,
input [31:0] A3,
input [31:0] A4,
input [31:0] A5,
output [31:0] S1,
output [31:0] S2
);
wire [31:0] w1, w2, w3, w4;
carrySaveAdder csa1 (
A1,
A2,
A3,
w1,
w2
);
carrySaveAdder csa2 (
A4,
A5,
w1,
w3,
w4
);
carrySaveAdder csa3 (
w2,
w3,
w4,
S1,
S2
);
endmodule
| 7.058341 |
module adder6 (
a,
b,
sum
);
input [5:0] a, b;
output [5:0] sum;
wire [5:0] sum;
assign sum = a + b;
endmodule
| 7.069424 |
module Adder64 (
c_out,
sum,
a,
b,
c_in
);
input [63:0] a;
input [63:0] b;
input c_in;
output [63:0] sum;
output c_out;
wire carry_out1, carry_out2, carry_out3;
Adder16 A1 (
carry_out1,
sum[15:0],
a[15:0],
b[15:0],
c_in
);
Adder16 A2 (
carry_out2,
sum[31:16],
a[31:16],
b[31:16],
carry_out1
);
Adder16 A3 (
carry_out3,
sum[47:32],
a[47:32],
b[47:32],
carry_out2
);
Adder16 A4 (
c_out,
sum[63:48],
a[63:48],
b[63:48],
carry_out3
);
endmodule
| 6.919409 |
module adder (
si,
xout,
a,
b,
xin
);
input [63:0] a, b;
input [7:0] xin;
output [64:0][7:0] x;
integer i = 0;
output reg [7:0] ym;
output [7:0] xout;
output [63:0][7:0] y;
output reg [63:0] si;
kpgg kpg_0 (
x[8:1],
a[7:0],
b[7:0]
);
kpgg kpg_1 (
x[16:9],
a[15:8],
b[15:8]
);
kpgg kpg_2 (
x[24:17],
a[23:16],
b[23:16]
);
kpgg kpg_3 (
x[32:25],
a[31:24],
b[31:24]
);
kpgg kpg_4 (
x[40:33],
a[39:32],
b[39:32]
);
kpgg kpg_5 (
x[48:41],
a[47:40],
b[47:40]
);
kpgg kpg_6 (
x[56:49],
a[55:48],
b[55:48]
);
kpgg kpg_7 (
x[64:57],
a[63:56],
b[63:56]
);
assign x[0] = xin;
ppc ppc_0 (
y[63:0],
x[63:0]
);
always @(*) begin
if (x[64] == "p") begin
if (y[63] == "g") ym = "g";
else ym = "k";
end else ym = x[64];
for (i = 0; i < 64; i = i + 1) begin
if (y[i] == "k") si[i] = (a[i] ^ b[i]) ^ 0;
else si[i] = (a[i] ^ b[i]) ^ 1;
end
end
assign xout = ym;
endmodule
| 7.276647 |
module adder6bit (
sum,
cout,
in1,
in2
);
output [5:0] sum;
output cout;
input [5:0] in1, in2;
wire cout0, cout1, cout2, cout3, cout4;
adder1bit add0 (
sum[0],
cout0,
in1[0],
in2[0],
1'b0
);
adder1bit add1 (
sum[1],
cout1,
in1[1],
in2[1],
cout0
);
adder1bit add2 (
sum[2],
cout2,
in1[2],
in2[2],
cout1
);
adder1bit add3 (
sum[3],
cout3,
in1[3],
in2[3],
cout2
);
adder1bit add4 (
sum[4],
cout4,
in1[4],
in2[4],
cout3
);
adder1bit add5 (
sum[5],
cout,
in1[5],
in2[5],
cout4
);
endmodule
| 7.483619 |
module adder7bit (
sum,
cout,
in1,
in2
);
output [6:0] sum;
output cout;
input [6:0] in1, in2;
wire cout0, cout1, cout2, cout3, cout4, cout5;
adder1bit add0 (
sum[0],
cout0,
in1[0],
in2[0],
1'b0
);
adder1bit add1 (
sum[1],
cout1,
in1[1],
in2[1],
cout0
);
adder1bit add2 (
sum[2],
cout2,
in1[2],
in2[2],
cout1
);
adder1bit add3 (
sum[3],
cout3,
in1[3],
in2[3],
cout2
);
adder1bit add4 (
sum[4],
cout4,
in1[4],
in2[4],
cout3
);
adder1bit add5 (
sum[5],
cout5,
in1[5],
in2[5],
cout4
);
adder1bit add6 (
sum[6],
cout,
in1[6],
in2[6],
cout5
);
endmodule
| 7.640212 |
module adder (
s,
co,
a,
b,
ci
);
output s, co; //Outputs of Sum and Carry Out
input a, b, ci; //Inputs of A, b and Carry In
wire o0, o1, o2; //Internal wiring
xor (s, a, b, ci); //Calculation of Sum
or (o0, a, b); //Calculation of Carry Out
or (o1, b, ci);
or (o2, ci, a);
and (co, o0, o1, o2);
endmodule
| 7.276647 |
module adder7 (
s,
co,
a,
b,
ci
);
output [6:0] s; //7-bit Sum output
output co; //Output bit of Carry out
input [6:0] a, b; //7-bit Input A and B
input ci; //Input bit of Carry in
wire c1, c2, c3, c4, c5, c6;
adder a0 (
s[0],
c1,
a[0],
b[0],
ci
);
adder a1 (
s[1],
c2,
a[1],
b[1],
c1
);
adder a2 (
s[2],
c3,
a[2],
b[2],
c2
);
adder a3 (
s[3],
c4,
a[3],
b[3],
c3
);
adder a4 (
s[4],
c5,
a[4],
b[4],
c4
);
adder a5 (
s[5],
c6,
a[5],
b[5],
c5
);
adder a6 (
s[6],
co,
a[6],
b[6],
c6
);
endmodule
| 7.475421 |
module adder7_8 (
s,
co,
a,
b,
c,
d,
e,
f,
g,
h,
ci
);
output [6:0] s;
output co;
input [6:0] a, b, c, d, e, f, g, h;
input ci;
wire [6:0] s1, s2, s3, s4, s5, s6;
wire co1, co2, co3, co4, co5, co6;
adder7 a0 (
s1,
co1,
a,
b,
ci
);
adder7 a1 (
s2,
co2,
c,
s1,
co1
);
adder7 a2 (
s3,
co3,
d,
s2,
co2
);
adder7 a3 (
s4,
co4,
e,
s3,
co3
);
adder7 a4 (
s5,
co5,
f,
s4,
co4
);
adder7 a5 (
s6,
co6,
g,
s5,
co5
);
adder7 a6 (
s,
co,
h,
s6,
co6
);
endmodule
| 7.416022 |
module adder8 (
a,
b,
sum
);
input [7:0] a, b;
output [7:0] sum;
wire [7:0] sum;
assign sum = a + b;
endmodule
| 6.980581 |
module tb_Adder8bit ();
reg [7:0] A, B;
reg Ci;
wire [7:0] Sum, Co;
Adder8bit b (
Sum,
Co,
A,
B,
Ci
);
initial begin
end
endmodule
| 6.609884 |
module Adder8bit (
S,
Cout,
A,
B,
Cin
);
input [7:0] A, B;
input Cin;
output [7:0] S, Cout;
full_adder UO (
S[0],
Cout[0],
A[0],
B[0],
Cin
);
full_adder U1 (
S[1],
Cout[1],
A[1],
B[1],
Cout[0]
);
full_adder U2 (
S[2],
Cout[2],
A[2],
B[2],
Cout[1]
);
full_adder U3 (
S[3],
Cout[3],
A[3],
B[3],
Cout[2]
);
full_adder U4 (
S[4],
Cout[4],
A[4],
B[4],
Cout[3]
);
full_adder U5 (
S[5],
Cout[5],
A[5],
B[5],
Cout[4]
);
full_adder U6 (
S[6],
Cout[6],
A[6],
B[6],
Cout[5]
);
full_adder U7 (
S[7],
Cout[7],
A[7],
B[7],
Cout[6]
);
endmodule
| 6.844801 |
module adder8_4 (
x,
y,
add
);
input [7:0] x, y;
output [8:0] add;
wire c1;
blockSize4 b1 (
x[3:0],
y[3:0],
1'b0,
add[3:0],
c1
);
blockSize4 b2 (
x[7:4],
y[7:4],
c1,
add[7:4],
cout
);
assign add[8] = cout;
endmodule
| 7.202405 |
module adder8_8 (
a,
b,
sum
);
input [7:0] a, b;
output [8:0] sum;
wire c0;
blockSize8 b0 (
a[7:0],
b[7:0],
1'b0,
sum[7:0],
c0
);
assign sum[8] = c0;
endmodule
| 6.879971 |
module: full_adder_8bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module adder8_bitTest;
// Inputs
reg [7:0] a;
reg [7:0] b;
// Outputs
wire cout;
wire [7:0] s;
// Instantiate the Unit Under Test (UUT)
full_adder_8bit uut (
.a(a),
.b(b),
.cout(cout),
.s(s)
);
initial begin
// Initialize Inputs
a = 8'b00011110;
b = 8'b00000001;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
a = 8'b00100011;
b = 8'b00000100;
// Wait 100 ns for global reset to finish
#100;
end
endmodule
| 7.25697 |
module adder9 (
input [8:0] a,
input [8:0] b,
output [8:0] s
);
assign s = a + b;
endmodule
| 6.834286 |
module adderB (
input [31:0] in1,
input [31:0] in2,
output [31:0] out
);
assign out = in1 + in2;
endmodule
| 7.260942 |
module AdderBasic #(
parameter WIDTH = 32 // ӷλ
) (
input CI, // 1λλ
input [WIDTH - 1 : 0] A, // (WIDTH)λA
input [WIDTH - 1 : 0] B, // (WIDTH)λB
output [WIDTH - 1 : 0] S, // (WIDTH)λS
output [WIDTH - 1 : 0] C // (WIDTH)λλC
);
// ȼAdderUnitҪ
localparam integer UNITS = $ceil(WIDTH / 4.0);
// AdderUnit
wire [ UNITS - 1 : 0] CIi; // UNITSλ
wire [4 * UNITS - 1 : 0] Ai; // 4 * UNITSλ(UNITS)A
wire [4 * UNITS - 1 : 0] Bi; // 4 * UNITSλ(UNITS)B
wire [4 * UNITS - 1 : 0] So; // 4 * UNITSλ(UNITS)S
wire [4 * UNITS - 1 : 0] Co; // 4 * UNITSλ(UNITS)λC
// i
genvar i;
// UNITSAdderUnitԪ
generate
for (i = 0; i < UNITS; i = i + 1) begin
AdderUnit Unit (
.CI(CIi[i]),
.A (Ai[i*4+3 : i*4]),
.B (Bi[i*4+3 : i*4]),
.S (So[i*4+3 : i*4]),
.C (Co[i*4+3 : i*4])
);
end
endgenerate
// AdderUnitԪһλλһλ룬һCI
generate
for (i = 0; i < UNITS; i = i + 1) begin
if (i != 0) begin
assign CIi[i] = Co[4*i-1];
end else begin
assign CIi[i] = CI;
end
end
endgenerate
// ӼAͼBλʹ0λ֤ӷȷ
generate
for (i = 0; i < 4 * UNITS; i = i + 1) begin
assign Ai[i] = (i < WIDTH) ? A[i] : 1'b0;
assign Bi[i] = (i < WIDTH) ? B[i] : 1'b0;
end
endgenerate
// ӽSͽλC
assign S = So[WIDTH-1 : 0];
assign C = Co[WIDTH-1 : 0];
endmodule
| 7.402408 |
module adderCircuit (
LEDR,
SW
);
input [9:0] SW;
output [9:0] LEDR;
wire c1;
wire c2;
wire c3;
wire c4;
fullAdder u0 (
.A(SW[4]),
.B(SW[0]),
.cin(SW[8]),
.S(LEDR[0]),
.cout(c1)
);
fullAdder u1 (
.A(SW[5]),
.B(SW[1]),
.cin(c1),
.S(LEDR[1]),
.cout(c2)
);
fullAdder u2 (
.A(SW[6]),
.B(SW[2]),
.cin(c2),
.S(LEDR[2]),
.cout(c3)
);
fullAdder u3 (
.A(SW[7]),
.B(SW[3]),
.cin(c3),
.S(LEDR[3]),
.cout(c4)
);
assign LEDR[4] = c4;
endmodule
| 6.586857 |
module AdderExtModule (
input [15:0] foo,
output [15:0] bar
);
assign bar = foo + 1;
endmodule
| 7.452252 |
module adderFour (
next,
outAddr
);
input [31:0] next;
output reg [31:0] outAddr;
always @(next) begin
outAddr = next + 32'd4;
end
endmodule
| 6.595846 |
module addergen_st #(
parameter NBITS = 16
) (
output [NBITS-1:0] r,
output cout,
input [NBITS-1:0] a,
input [NBITS-1:0] b,
input cin
);
wire [NBITS:0] carry;
assign carry[0] = cin;
genvar k;
generate
for (k = 0; k < NBITS; k = k + 1) begin : blk
fulladder_st FA (
.r(r[k]),
.cout(carry[k+1]),
.a(a[k]),
.b(b[k]),
.cin(carry[k])
);
end
endgenerate
assign cout = carry[NBITS];
endmodule
| 7.475074 |
module AdderL (
add_statusL,
addip1L,
addip2L,
addopL,
addorsubL
);
input add_statusL, addorsubL;
input [39:0] addip1L, addip2L;
output reg [39:0] addopL;
always @(addip1L or addip2L or addorsubL) begin
if (addorsubL == 1'b1) addopL = addip1L - addip2L;
else addopL = addip1L + addip2L;
end
endmodule
| 6.904073 |
module AdderMacro (
a,
b,
q
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O and parameter declarations
parameter WIDTH = 8;
input wire [WIDTH-1:0] a;
input wire [WIDTH-1:0] b;
output wire [WIDTH-1:0] q;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Sanity checks
initial begin
if (WIDTH[1:0]) begin
$display("AdderMacro width must be multiple of 4 bits");
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The actual adder logic
wire [(WIDTH >> 2)- 1 : 0] carry;
`include "stringfuncs.vh"
genvar g;
generate
for (g = 0; g < WIDTH; g = g + 4) begin : adder
//No carry in for first state
if (g == 0) begin
(* RLOC = {"X", `VAR_TO_STRING(0), "Y", `VAR_TO_STRING(g[31:2])} *)
AdderMacro4bit nibble (
.cin(1'b0),
.a(a[g+:4]),
.b(b[g+:4]),
.q(q[g+:4]),
.cout(carry[g>>2])
);
end //We *do* need carry in here
else begin
(* RLOC = {"X", `VAR_TO_STRING(0), "Y", `VAR_TO_STRING(g[31:2])} *)
AdderMacro4bit nibble (
.cin(carry[(g>>2)-1]),
.a(a[g+:4]),
.b(b[g+:4]),
.q(q[g+:4]),
.cout(carry[g>>2])
);
end
end
endgenerate
endmodule
| 8.306087 |
module AdderMacro4bit (
cin,
a,
b,
q,
cout
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O and parameter declarations
input wire cin;
input wire [3:0] a;
input wire [3:0] b;
output wire [3:0] q;
output wire cout;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The actual adder logic
//Carry state
wire [3:0] lcout;
wire [3:0] muxout;
assign cout = muxout[3];
//Carry generate/propagate LUTs
//BEL constraints are inferred for now
(* RLOC="X0Y0" *)
AdderMacroCell lut0 (
.a(a[0]),
.b(b[0]),
.lcout(lcout[0])
);
(* RLOC="X0Y0" *) AdderMacroCell lut1 (
.a(a[1]),
.b(b[1]),
.lcout(lcout[1])
);
(* RLOC="X0Y0" *) AdderMacroCell lut2 (
.a(a[2]),
.b(b[2]),
.lcout(lcout[2])
);
(* RLOC="X0Y0" *) AdderMacroCell lut3 (
.a(a[3]),
.b(b[3]),
.lcout(lcout[3])
);
//Carry chain muxes
(* RLOC="X0Y0" *)
MUXCY mux0 (
.DI(a[0]),
.CI(cin),
.S (lcout[0]),
.O (muxout[0])
);
(* RLOC="X0Y0" *) MUXCY mux1 (
.DI(a[1]),
.CI(muxout[0]),
.S (lcout[1]),
.O (muxout[1])
);
(* RLOC="X0Y0" *) MUXCY mux2 (
.DI(a[2]),
.CI(muxout[1]),
.S (lcout[2]),
.O (muxout[2])
);
(* RLOC="X0Y0" *) MUXCY mux3 (
.DI(a[3]),
.CI(muxout[2]),
.S (lcout[3]),
.O (muxout[3])
);
//Output XORs
(* RLOC="X0Y0" *)
XORCY xor0 (
.LI(lcout[0]),
.CI(cin),
.O (q[0])
);
(* RLOC="X0Y0" *) XORCY xor1 (
.LI(lcout[1]),
.CI(muxout[0]),
.O (q[1])
);
(* RLOC="X0Y0" *) XORCY xor2 (
.LI(lcout[2]),
.CI(muxout[1]),
.O (q[2])
);
(* RLOC="X0Y0" *) XORCY xor3 (
.LI(lcout[3]),
.CI(muxout[2]),
.O (q[3])
);
endmodule
| 7.177771 |
module AdderMacroWithInputXors (
a,
b,
ax,
bx,
q
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O and parameter declarations
parameter WIDTH = 8;
input wire [WIDTH-1:0] a;
input wire [WIDTH-1:0] b;
input wire [WIDTH-1:0] ax;
input wire [WIDTH-1:0] bx;
output wire [WIDTH-1:0] q;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Sanity checks
initial begin
if (WIDTH[1:0]) begin
$display("AdderMacroWithInputXors width must be multiple of 4 bits");
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The actual adder logic
wire [(WIDTH >> 2)- 1 : 0] carry;
`include "stringfuncs.vh"
genvar g;
generate
for (g = 0; g < WIDTH; g = g + 4) begin : adder
//No carry in for first state
if (g == 0) begin
(* RLOC = {"X", `VAR_TO_STRING(0), "Y", `VAR_TO_STRING(g[31:2])} *)
AdderMacroWithInputXor4bit nibble (
.cin(1'b0),
.a(a[g+:4]),
.b(b[g+:4]),
.ax(ax[g+:4]),
.bx(bx[g+:4]),
.q(q[g+:4]),
.cout(carry[g>>2])
);
end //We *do* need carry in here
else begin
(* RLOC = {"X", `VAR_TO_STRING(0), "Y", `VAR_TO_STRING(g[31:2])} *)
AdderMacroWithInputXor4bit nibble (
.cin(carry[(g>>2)-1]),
.a(a[g+:4]),
.b(b[g+:4]),
.ax(ax[g+:4]),
.bx(bx[g+:4]),
.q(q[g+:4]),
.cout(carry[g>>2])
);
end
end
endgenerate
endmodule
| 7.352311 |
module AdderMacroWithInputXor4bit (
cin,
a,
b,
ax,
bx,
q,
cout
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O and parameter declarations
input wire cin;
input wire [3:0] a;
input wire [3:0] b;
input wire [3:0] ax;
input wire [3:0] bx;
output wire [3:0] q;
output wire cout;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The actual adder logic
//Carry state
wire [3:0] lcout;
wire [3:0] muxout;
wire [3:0] axout;
assign cout = muxout[3];
//Carry generate/propagate LUTs
//BEL constraints are inferred for now
(* RLOC="X0Y0" *)
AdderMacroCellWithInputXor lut0 (
.a(a[0]),
.b(b[0]),
.ax(ax[0]),
.bx(bx[0]),
.lcout(lcout[0]),
.axout(axout[0])
);
(* RLOC="X0Y0" *) AdderMacroCellWithInputXor lut1 (
.a(a[1]),
.b(b[1]),
.ax(ax[1]),
.bx(bx[1]),
.lcout(lcout[1]),
.axout(axout[1])
);
(* RLOC="X0Y0" *) AdderMacroCellWithInputXor lut2 (
.a(a[2]),
.b(b[2]),
.ax(ax[2]),
.bx(bx[2]),
.lcout(lcout[2]),
.axout(axout[2])
);
(* RLOC="X0Y0" *) AdderMacroCellWithInputXor lut3 (
.a(a[3]),
.b(b[3]),
.ax(ax[3]),
.bx(bx[3]),
.lcout(lcout[3]),
.axout(axout[3])
);
//Carry chain muxes
(* RLOC="X0Y0" *)
MUXCY mux0 (
.DI(axout[0]),
.CI(cin),
.S (lcout[0]),
.O (muxout[0])
);
(* RLOC="X0Y0" *) MUXCY mux1 (
.DI(axout[1]),
.CI(muxout[0]),
.S (lcout[1]),
.O (muxout[1])
);
(* RLOC="X0Y0" *) MUXCY mux2 (
.DI(axout[2]),
.CI(muxout[1]),
.S (lcout[2]),
.O (muxout[2])
);
(* RLOC="X0Y0" *) MUXCY mux3 (
.DI(axout[3]),
.CI(muxout[2]),
.S (lcout[3]),
.O (muxout[3])
);
//Output XORs
(* RLOC="X0Y0" *)
XORCY xor0 (
.LI(lcout[0]),
.CI(cin),
.O (q[0])
);
(* RLOC="X0Y0" *) XORCY xor1 (
.LI(lcout[1]),
.CI(muxout[0]),
.O (q[1])
);
(* RLOC="X0Y0" *) XORCY xor2 (
.LI(lcout[2]),
.CI(muxout[1]),
.O (q[2])
);
(* RLOC="X0Y0" *) XORCY xor3 (
.LI(lcout[3]),
.CI(muxout[2]),
.O (q[3])
);
endmodule
| 7.352311 |
module AdderModule (
PCIn,
PCOut
);
//inputs - Current Program Counter
input [31:0] PCIn;
//Outputs - Next Program Counter (CurrentPC + 4)
output reg [31:0] PCOut;
//Add 4 to get next PC
always @(*) begin
PCOut = PCIn + 4;
end
endmodule
| 7.060307 |
module fixed_adder (
num1,
num2,
result,
overflow
);
input [15:0] num1, num2;
output [15:0] result;
output overflow;
//single assign statement handles fixed additon
assign {overflow, result} = (num1 + num2);
endmodule
| 6.746191 |
module addermux (
c_out,
adder_out,
sub_out,
select
);
input adder_out, sub_out;
input select;
output reg c_out;
always @(*) begin
case (select)
1'b0: c_out = adder_out;
1'b1: c_out = sub_out;
default: c_out = 0;
endcase
end
endmodule
| 6.558569 |
module addern (
carryin,
X,
Y,
S,
carryout
);
parameter n = 32;
input carryin;
input [n-1:0] X, Y;
output [n-1:0] S;
output carryout;
wire [n:0] C;
genvar k;
assign C[0] = carryin;
assign carryout = C[n];
generate
for (k = 0; k < n; k = k + 1) begin : fulladd_stage
wire z1, z2, z3; //wires within full-adder
xor (S[k], X[k], Y[k], C[k]);
and (z1, X[k], Y[k]);
and (z2, X[k], C[k]);
and (z3, Y[k], C[k]);
or (C[k+1], z1, z2, z3);
end
endgenerate
endmodule
| 7.682323 |
module AdderNBit #(
parameter N = 4 //Number of bits in adder (default 4)
) (
// Declare input and output ports
input cin,
input [N-1:0] a,
input [N-1:0] b,
output [N-1:0] sum,
output cout
);
wire [N-0:0] carry; //Internal carry signal, N+1 wide to include carry in/out
assign carry[0] = cin; //First bit is Carry In
assign cout = carry[N]; //Last bit is Carry Out
genvar i; //Generate variable to be used in the for loop
generate
for (i = 0; i < N; i = i + 1) begin : adder_loop //Loop "N" Times.
//We can do maths with the genvar valus using localparam statements, e.g.
localparam j = i + 1;
//You can also do things like: if (i[0]) ... which would happen on even loops
//or even if(i == 1) ... which would be the first loop.
//We can instantiate modules...
//Instantiate "N" 1-bit FullAdder modules (From Lab 1, QuartusTest.v)
Adder1Bit adder (
.cin (carry[i]),
.a (a[i]),
.b (b[i]),
.sum (sum[i]),
.cout(carry[j])
);
//We can do procedural blocks
// always @ ( whatever ) do something...
//Or make local variables
// wire localVar; <- only visible inside the loop. Can do this in if-else too
end
endgenerate
endmodule
| 8.393819 |
module addern_tb;
parameter n = 32;
reg carryin;
reg [n-1:0] X, Y;
wire [n-1:0] S;
wire carryout;
addern a1 (
carryin,
X,
Y,
carryout
);
initial begin
carryin = 0;
X = 32;
Y = 23;
#10 X = 67;
Y = 78;
end
endmodule
| 6.694659 |
module AdderPc (
input [31:0] pcIn,
output reg [31:0] dataOut
);
integer b4;
always @(*) begin
b4 = 3'b100;
case (b4)
3'b100: begin
dataOut = pcIn + b4;
end
endcase
end
initial begin
dataOut = 32'd0;
end
endmodule
| 7.038903 |
module adderPlus #(
parameter N = 8
) (
inputA,
inputB,
Sum,
Carry
);
input [N-1:0] inputA, inputB;
output [N-1:0] Sum;
output Carry;
assign {Carry, Sum} = inputA + inputB;
endmodule
| 7.611791 |
module AdderR (
add_statusR,
addip1R,
addip2R,
addopR,
addorsubR
);
input add_statusR, addorsubR;
input [39:0] addip1R, addip2R;
output reg [39:0] addopR;
always @(addip1R or addip2R or addorsubR) begin
if (addorsubR == 1'b1) addopR = addip1R - addip2R;
else addopR = addip1R + addip2R;
end
endmodule
| 6.661425 |
module AdderReg (
i_Add1,
i_Add2,
result,
write_enable,
clk,
rst
);
input [63:0] i_Add1;
input [63:0] i_Add2;
output [64:0] result;
input write_enable;
input clk;
input rst;
reg [64:0] Temp;
ripple_adder #(64) adder (
i_Add1,
i_Add2,
Temp
);
Register RReg (
Temp,
write_enable,
clk,
rst,
result
);
endmodule
| 6.796054 |
module adderStage5_2 (
input [20:0] input1,
input [20:0] input2,
output reg [21:0] output1,
input enable,
input clk,
output reg done
);
always @(posedge clk) begin
if (enable) begin
output1 <= {input1[20], input1} + {input2[20], input2};
done <= 1'b1;
end else begin
output1 <= 0;
done <= 1'b0;
end
end
endmodule
| 6.614071 |
module AdderStage7 (
m447,
m448,
m449,
m450,
m451,
m452,
m453,
m454,
m455,
m456,
m457,
m458,
m459,
m460,
m461,
m462,
m463,
m464,
m465,
m466,
m467,
m468,
m469,
m470,
m471,
m472,
m473,
m474,
m475,
m476,
m477,
m478,
m479,
m480,
m481,
m482,
m483,
m484,
m485,
m486,
m487,
m488,
m489,
m490,
m491,
m492,
m493,
s337,
s338,
s339,
s340,
s341,
s342,
s343,
s344,
s345,
s346,
s347,
s348,
s349,
s350,
s351,
s352,
s353,
s354,
s355,
s356,
s357,
s358,
s359,
s360,
s361,
s362,
s363,
s364,
s365,
s366,
s367,
s368,
s369,
s370,
s371,
s372,
s373,
s374,
s375,
s376,
s377,
s378,
s379,
s380,
s381,
s382,
s383,
s384,
s385,
s386,
s387,
s388,
s389,
s390,
s391,
s392,
s393,
s394,
s395,
s396,
s397,
s398,
s399,
s400,
s401,
s402,
s403,
s404,
s405,
s406,
s407,
s408,
s409,
s410,
s411,
s412,
s413,
s414,
s415,
s416,
s417,
s418,
s419,
s420,
s421,
s422,
s423,
s424,
s425,
s426,
s427,
s428,
s429,
s430,
s431,
s432,
p9,
p57
);
input m447,m448,m449,m450,m451,m452,m453,m454,m455,m456,m457,m458,m459,m460,m461,m462,m463,m464,m465,m466,m467,m468,m469,m470,m471,m472,m473,m474,m475,m476,m477,m478,m479,m480,m481,m482,m483,m484,m485,m486,m487,m488,m489,m490,m491,m492,m493,s337,s338,s339,s340,s341,s342,s343,s344,s345,s346,s347,s348,s349,s350,s351,s352,s353,s354,s355,s356,s357,s358,s359,s360,s361,s362,s363,s364,s365,s366,s367,s368,s369,s370,s371,s372,s373,s374,s375,s376,s377,s378,s379,s380,s381,s382,s383,s384,s385;
output s386,s387,s388,s389,s390,s391,s392,s393,s394,s395,s396,s397,s398,s399,s400,s401,s402,s403,s404,s405,s406,s407,s408,s409,s410,s411,s412,s413,s414,s415,s416,s417,s418,s419,s420,s421,s422,s423,s424,s425,s426,s427,s428,s429,s430,s431,s432,p9,p57;
wire d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15,d16,d17,d18,d19,d20,d21,d22,d23,d24,d25,d26,d27,d28,d29,d30,d31,d32,d33,d34,d35,d36,d37,d38,d39,d40,d41,d42,d43,d44,d45,d46,d47,d48;
FullAdder fulladder0 (
s337,
m447,
1'b0,
p9,
d1
);
FullAdder fulladder1 (
s338,
m448,
d1,
s386,
d2
);
FullAdder fulladder2 (
s339,
m449,
d2,
s387,
d3
);
FullAdder fulladder3 (
s340,
m450,
d3,
s388,
d4
);
FullAdder fulladder4 (
s341,
m451,
d4,
s389,
d5
);
FullAdder fulladder5 (
s342,
m452,
d5,
s390,
d6
);
FullAdder fulladder6 (
s343,
m453,
d6,
s391,
d7
);
FullAdder fulladder7 (
s344,
m454,
d7,
s392,
d8
);
FullAdder fulladder8 (
s345,
m455,
d8,
s393,
d9
);
FullAdder fulladder9 (
s346,
m456,
d9,
s394,
d10
);
FullAdder fulladder10 (
s347,
m457,
d10,
s395,
d11
);
FullAdder fulladder11 (
s348,
m458,
d11,
s396,
d12
);
FullAdder fulladder12 (
s349,
m459,
d12,
s397,
d13
);
FullAdder fulladder13 (
s350,
m460,
d13,
s398,
d14
);
FullAdder fulladder14 (
s351,
m461,
d14,
s399,
d15
);
FullAdder fulladder15 (
s352,
m462,
d15,
s400,
d16
);
FullAdder fulladder16 (
s353,
m463,
d16,
s401,
d17
);
FullAdder fulladder17 (
s354,
m464,
d17,
s402,
d18
);
FullAdder fulladder18 (
s355,
m465,
d18,
s403,
d19
);
FullAdder fulladder19 (
s356,
m466,
d19,
s404,
d20
);
FullAdder fulladder20 (
s357,
m467,
d20,
s405,
d21
);
FullAdder fulladder21 (
s358,
m468,
d21,
s406,
d22
);
FullAdder fulladder22 (
s359,
m469,
d22,
s407,
d23
);
FullAdder fulladder23 (
s360,
m470,
d23,
s408,
d24
);
FullAdder fulladder24 (
s361,
m471,
d24,
s409,
d25
);
FullAdder fulladder25 (
s362,
m472,
d25,
s410,
d26
);
FullAdder fulladder26 (
s363,
m473,
d26,
s411,
d27
);
FullAdder fulladder27 (
s364,
m474,
d27,
s412,
d28
);
FullAdder fulladder28 (
s365,
m475,
d28,
s413,
d29
);
FullAdder fulladder29 (
s366,
m476,
d29,
s414,
d30
);
FullAdder fulladder30 (
s367,
m477,
d30,
s415,
d31
);
FullAdder fulladder31 (
s368,
m478,
d31,
s416,
d32
);
FullAdder fulladder32 (
s369,
m479,
d32,
s417,
d33
);
FullAdder fulladder33 (
s370,
m480,
d33,
s418,
d34
);
FullAdder fulladder34 (
s371,
m481,
d34,
s419,
d35
);
FullAdder fulladder35 (
s372,
m482,
d35,
s420,
d36
);
FullAdder fulladder36 (
s373,
m483,
d36,
s421,
d37
);
FullAdder fulladder37 (
s374,
m484,
d37,
s422,
d38
);
FullAdder fulladder38 (
s375,
m485,
d38,
s423,
d39
);
FullAdder fulladder39 (
s376,
m486,
d39,
s424,
d40
);
FullAdder fulladder40 (
s377,
m487,
d40,
s425,
d41
);
FullAdder fulladder41 (
s378,
m488,
d41,
s426,
d42
);
FullAdder fulladder42 (
s379,
m489,
d42,
s427,
d43
);
FullAdder fulladder43 (
s380,
m490,
d43,
s428,
d44
);
FullAdder fulladder44 (
s381,
m491,
d44,
s429,
d45
);
FullAdder fulladder45 (
s382,
m492,
d45,
s430,
d46
);
FullAdder fulladder46 (
s383,
m493,
d46,
s431,
d47
);
FullAdder fulladder47 (
s384,
1'b0,
d47,
s432,
d48
);
FullAdder fulladder48 (
s385,
1'b0,
d48,
p57,
);
endmodule
| 6.891576 |
module addersub (
opB,
opA,
op,
result_slt,
result
);
//parameter WIDTH=32;
//`DEFINE WIDTH 32
input [31:0] opA;
input [31:0] opB;
//input carry_in;
input [2:0] op;
output result_slt;
output [31:0] result;
wire [32:0] sum;
wire addsub;
wire useless;
assign useless = op[1] & op[2];
assign addsub = op[0];
wire not_addsub;
assign not_addsub = ~addsub;
assign result = sum[31:0];
assign result_slt = sum[32];
dummy_add_sub adder32bit (
opA,
opB,
not_addsub,
sum
);
// This is an LPM from Altera, replacing with a dummy one for now
/*
lpm_add_sub adder_inst(
.dataa({signext&opA[WIDTH-1],opA}),
.datab({signext&opB[WIDTH-1],opB}),
.cin(~addsub),
.add_sub(addsub),
.result(sum)
// synopsys translate_off
,
.cout (),
.clken (),
.clock (),
.overflow (),
.aclr ()
// synopsys translate_on
);
//defparam
// adder_inst.lpm_width=WIDTH+1,
// adder_inst.lpm_representation="SIGNED";
*/
endmodule
| 7.127372 |
module mux2to1 (
V,
W,
Sel,
F
);
parameter k = 8;
input [k-1:0] V, W;
input Sel;
output [k-1:0] F;
reg [k-1:0] F;
always @(V or W or Sel)
if (Sel == 0) F = V;
else F = W;
endmodule
| 7.107199 |
module adderk (
carryin,
X,
Y,
S,
carryout
);
parameter k = 8;
input carryin;
input [k-1:0] X, Y;
output [k-1:0] S;
output carryout;
reg [k-1:0] S;
reg carryout;
always @(X or Y or carryin) {carryout, S} = X + Y + carryin;
endmodule
| 7.424977 |
module mux2to1 (
V,
W,
Selm,
F
);
parameter k = 8;
input [k-1:0] V, W;
input Selm;
output [k-1:0] F;
reg [k-1:0] F;
always @(V or W or Selm)
if (Selm == 0) F = V;
else F = W;
endmodule
| 7.107199 |
module AdderSubtractor32x32 (
input [31:0] A, // input [2's complement 32 bits]
input [31:0] B, // input [2's complement 32 bits]
input sel, // input [add:sel=0 || sub:sel=1]
output [31:0] S // output [2's complement 32 bits]
);
// if sel = 0 then add else subtract
/* write your code here */
assign S = (sel == 0) ? (A + B) : (A - B);
endmodule
| 7.160384 |
module AdderSubtractor4BitWithoutDelay (
input [3:0] A,
input [3:0] B,
input sel,
output [3:0] S,
output cout
);
wire cout1, cout2, cout3;
fullAdder ASD0 (
.a(A[0]),
.b(B[0]),
.cin(sel),
.sel(sel),
.sum(S[0]),
.cout(cout1)
);
fullAdder ASD1 (
.a(A[1]),
.b(B[1]),
.cin(cout1),
.sel(sel),
.sum(S[1]),
.cout(cout2)
);
fullAdder ASD2 (
.a(A[2]),
.b(B[2]),
.cin(cout2),
.sel(sel),
.sum(S[2]),
.cout(cout3)
);
fullAdder ASD3 (
.a(A[3]),
.b(B[3]),
.cin(cout3),
.sel(sel),
.sum(S[3]),
.cout(cout)
);
endmodule
| 7.160384 |
module addersub (
opA,
opB,
op,
result,
result_slt
);
parameter WIDTH = 32;
input [WIDTH-1:0] opA;
input [WIDTH-1:0] opB;
//input carry_in;
input [3-1:0] op;
output [WIDTH-1:0] result;
output result_slt;
wire carry_out;
wire [WIDTH:0] sum;
// Mux between sum, and slt
wire is_slt;
wire signext;
wire addsub;
assign is_slt = op[2];
assign signext = op[1];
assign addsub = op[0];
assign result = sum[WIDTH-1:0];
//assign result_slt[WIDTH-1:1]={31{1'b0}};
//assign result_slt[0]=sum[WIDTH];
assign result_slt = sum[WIDTH];
lpm_add_sub adder_inst (
.dataa({signext & opA[WIDTH-1], opA}),
.datab({signext & opB[WIDTH-1], opB}),
.cin(~addsub),
.add_sub(addsub),
.result(sum)
// synopsys translate_off
, .cout(),
.clken(),
.clock(),
.overflow(),
.aclr()
// synopsys translate_on
);
defparam adder_inst.lpm_width = WIDTH + 1, adder_inst.lpm_representation = "SIGNED";
assign carry_out = sum[WIDTH];
endmodule
| 7.127372 |
module Adders_t;
reg a = 1'b0;
reg b = 1'b0;
reg cin = 1'b0;
wire ha_sum, ha_cout;
wire fa_sum, fa_cout;
Half_Adder ha (
.a(a),
.b(b),
.cout(ha_cout),
.sum(ha_sum)
);
Full_Adder fa (
.a(a),
.b(b),
.cin(cin),
.cout(fa_cout),
.sum(fa_sum)
);
// uncommment and add "+access+r" to your nverilog command to dump fsdb waveform on NTHUCAD
// initial begin
// $fsdbDumpfile("Adders.fsdb");
// $fsdbDumpvars;
// end
initial begin
repeat (2 ** 3) begin
#1{a, b, cin} = {a, b, cin} + 1'b1;
end
#1 $finish;
end
endmodule
| 6.63568 |
module addertb;
reg [7:0] a_test, b_test;
wire [7:0] sum_test;
reg cin_test;
wire cout_test;
reg [17:0] test;
integer error_count;
add8 u1 (
a_test,
b_test,
cin_test,
sum_test,
cout_test
);
initial begin
`ifdef vcdplusdump
$vcdpluson;
$vcdplusdeltacycleon;
$vcdplusglitchon;
$vcdplustraceon;
`endif
error_count = 0;
end
initial begin
for (test = 0; test <= 18'h1ffff; test = test + 1) begin
cin_test = test[16];
a_test = test[15:8];
b_test = test[7:0];
if ({cout_test, sum_test} !== (a_test + b_test + cin_test)) begin
error_count = error_count + 1;
if (error_count <= 10) begin
$display("***ERROR at time = %0d***", $time);
$display("a = %h, b = %h, sum = %h; cin = %h, cout = %h", a_test, b_test, sum_test,
cin_test, cout_test);
end
if (error_count == 10) begin
$display("\n\nError count reached 10, subsequent error message are suppressed");
`ifdef vcdplusdump
$vcdplusoff;
$vcdplusdeltacycleoff;
$vcdplusglitchoff;
$vcdplustraceoff;
`endif
end
end
#50;
end
if (error_count == 0) $display("****Testbench Successfully Completed!***");
else begin
$display("\n****************************************");
$display("***Testbench completed with %0d errors ***", error_count);
$display("****************************************\n\n");
end
$finish;
end
endmodule
| 6.797809 |
module Adder (
input [9:0] io_in0,
input [9:0] io_in1,
output [9:0] io_out
);
assign io_out = io_in0 + io_in1; // @[Adder.scala 17:20]
endmodule
| 7.642138 |
module AdderUnit (
input CI, // 1λλ
input [3 : 0] A, // 4λA
input [3 : 0] B, // 4λB
output [3 : 0] S, // 4λS
output [3 : 0] C // 4λλC
);
CARRY4 CARRY4_inst (
.CO (C), // 4λλ
.O (S[3 : 0]), // 4λ
.CI (CI), // 1λλ
.CYINIT(1'b0), // 1λλʼôCI
.DI (A[3 : 0]), // 4λλ-ѡ룬A
.S (A[3 : 0] ^ B[3 : 0]) // 4λλ-ѡѡ룬AB
);
endmodule
| 6.761389 |
module adderz #(
parameter n = 32
) (
input [n-1:0] a,
input [n-1:0] b,
output [n-1:0] num
);
assign num = a + b;
endmodule
| 9.214982 |
module Adder_1 (
input clock,
input reset,
input [31:0] io_inputx,
input [31:0] io_inputy,
output [31:0] io_result
);
assign io_result = io_inputx + io_inputy;
endmodule
| 6.969904 |
module adder_1 (
input [3:0] A,
input [3:0] B,
input cin,
output [3:0] S,
output cout
);
wire [3:0] carry;
full_adder A1 (
.A(A[0]),
.B(B[0]),
.cin(cin),
.S(S[0]),
.cout(carry[1])
);
full_adder A2 (
.A(A[1]),
.B(B[1]),
.cin(carry[1]),
.S(S[1]),
.cout(carry[2])
);
full_adder A3 (
.A(A[2]),
.B(B[2]),
.cin(carry[2]),
.S(S[2]),
.cout(carry[3])
);
full_adder A4 (
.A(A[3]),
.B(B[3]),
.cin(carry[3]),
.S(S[3]),
.cout(cout)
);
endmodule
| 6.607745 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_128 (
cout,
sum,
a,
b,
cin
);
parameter size = 128; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size parameter
input cin;
input [size-1:0] a, b; // 'a' and 'b' use the size parameter
assign {cout, sum} = a + b + cin;
endmodule
| 6.995163 |
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