code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_5bits (
a,
b,
ci,
s,
co
);
input [4 : 0] a;
input [4 : 0] b;
input ci;
output [4 : 0] s;
output co;
wire [4 : 0] g;
wire [4 : 0] p;
wire [3 : 0] c;
assign g = a & b;
assign p = a | b;
assign c[0] = g[0] | (p[0] & ci);
assign c[1] = g[1] | (p[1] & g[0]) | (p[1... | 7.029925 |
module adder_6 (
cout,
sum,
a,
b,
cin
);
parameter size = 6; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size parameter
input cin;
input [size-1:0] a, b; // 'a' and 'b' use the size parameter
assign {cout, sum} = a + b + cin;
endmo... | 7.100413 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module counter input
CLR: module counter input
out_num: output port for the counter module
OV: overflow flag
------------------------------------------------------
History:
01-07-2016: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simula... | 7.206611 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module add_6_bit (
input1,
input2,
answer
);
parameter N = 6;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1[0... | 7.079085 |
module adder_6bits (
a,
b,
ci,
s,
co
);
input [5 : 0] a;
input [5 : 0] b;
input ci;
output [5 : 0] s;
output co;
wire [5 : 0] g;
wire [5 : 0] p;
wire [4 : 0] c;
assign g = a & b;
assign p = a | b;
assign c[0] = g[0] | (p[0] & ci);
assign c[1] = g[1] | (p[1] & g[0]) | (p[1... | 6.767423 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_8 (
cout,
sum,
a,
b,
cin
);
parameter size = 8; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size parameter
input cin;
input [size-1:0] a, b; // 'a' and 'b' use the size parameter
assign {cout, sum} = a + b + cin;
endmo... | 7.047398 |
module ADDER_8bit (
cfinal,
sum,
num1,
num2,
cin
);
input [7:0] num1, num2;
output [7:0] sum;
wire [7:0] cout;
input cin;
output cfinal;
FADDER add0 (
sum[0],
cout[0],
num1[0],
num2[0],
cin
);
FADDER add1 (
sum[1],
cout[1],
num1[1],
... | 6.91515 |
module adder_8bits (
a,
b,
ci,
s,
co
);
input [7 : 0] a;
input [7 : 0] b;
input ci;
output [7 : 0] s;
output co;
wire c;
adder_4bits adder_4bits_inst (
.a (a[3 : 0]),
.b (b[3 : 0]),
.ci(ci),
.s (s[3 : 0]),
.co(c)
);
mux_adder_4bits mux_adder_4bits... | 7.981077 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module csa_adder_8in #(
parameter p_input_width = 14
) (
input [p_input_width-1:0] i_a,
input [p_input_width-1:0] i_b,
input [p_input_width-1:0] i_c,
input [p_input_width-1:0] i_d,
input [p_input_width-1:0] i_e,
input [p_input_width-1:0] i_f,
input [p_input_width-1:0] i_g,
input [p_... | 6.912097 |
module adder_8_bit (
input [7:0] a,
input [7:0] b,
output [7:0] sum,
output c_out
);
wire c_in;
assign c_in = 1'b0;
fulladder_1_bit f0 (
.a(a[0]),
.b(b[0]),
.c_in(c_in),
.s(sum[0]),
.c_out(ripple0)
);
fulladder_1_bit f1 (
.a(a[1]),
.b(b[1]),
.c_i... | 7.295209 |
module adder_8_bit_with_overflow_test;
// Inputs
reg [7:0] a;
reg [7:0] b;
// Outputs
wire [7:0] sum;
wire c_out;
wire overflow;
integer i;
// Instantiate the Unit Under Test (UUT)
adder_8_bit_with_overflow uut (
.a(a),
.b(b),
.sum(sum),
.c_out(c_out),
.overflow(over... | 6.773302 |
module adder_3bits (
a,
b,
ci,
s,
co
);
input [2 : 0] a;
input [2 : 0] b;
input ci;
output [2 : 0] s;
output co;
wire [2 : 0] g;
wire [2 : 0] p;
wire [1 : 0] c;
assign g = a & b;
assign p = a | b;
assign c[0] = g[0] | (p[0] & ci);
assign c[1] = g[1] | (p[1] & g[0]) | (p[1... | 7.015374 |
module mux_adder_3bits (
a,
b,
ci,
s,
co
);
input [2 : 0] a;
input [2 : 0] b;
input ci;
output [2 : 0] s;
output co;
wire c0, c1;
wire [2 : 0] s0, s1;
adder_3bits adder_inst1 (
.a (a),
.b (b),
.ci(1'b1),
.s (s1),
.co(c1)
);
adder_3bits adder_inst... | 6.93875 |
module adder_9bits (
a,
b,
ci,
s,
co
);
input [8 : 0] a;
input [8 : 0] b;
input ci;
output [8 : 0] s;
output co;
wire [1 : 0] c;
adder_3bits adder_3bits_inst (
.a (a[2 : 0]),
.b (b[2 : 0]),
.ci(ci),
.s (s[2 : 0]),
.co(c[0])
);
mux_adder_3bits mux_... | 7.505426 |
module MUX1 (
input [7:0] In1,
In2,
input Sel,
output [7:0] Out
);
assign Out = (Sel == 1) ? In1 : In2;
endmodule
| 7.237621 |
module adder_array (
cmd,
ain0,
ain1,
ain2,
ain3,
bin0,
bin1,
bin2,
bin3,
dout0,
dout1,
dout2,
dout3,
overflow
);
parameter BIT_WIDTH = 32;
input [2:0] cmd;
input [BIT_WIDTH-1:0] ain0, ain1, ain2, ain3;
input [BIT_WIDTH-1:0] bin0, bin1, bin2, bin3;
outp... | 8.320408 |
module adder_aTB ();
reg clk;
reg signed [15:0] n1, n2;
wire signed [16:0] sum;
adder_a(
.clk(clk), .n1(n1), .n2(n2), .sum(sum)
);
initial begin
clk = 0;
forever #1 clk = ~clk;
end
initial begin
$monitor("n1 = %d, n2 = %d, sum = %d", n1, n2, sum);
end
initial begin : apply_st... | 6.909664 |
module regN (
reset,
CLK,
D,
Q
);
input reset;
input CLK;
parameter N = 8;
input [N-1:0] D;
output [N-1:0] Q;
reg [N-1:0] Q;
always @(posedge CLK or posedge reset)
if (reset) Q = 0;
else Q = D;
endmodule
| 7.765402 |
module adder_A_B_8_bits (
input [7:0] SW,
input [1:0] KEY,
output [0:6] HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
output [0:0] LEDR
);
wire [7:0] myNumber;
regN #(8) newRegister (
~KEY[0],
~KEY[1],
SW[7:0],
myNumber
);
integer sum, cout, mod16, multiple... | 7.592316 |
module adder_A_B_8_bits_board (
input [7:0] SW,
input [1:0] KEY,
output [6:0] HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
output LEDR0
);
wire [7:0] sum, A, B;
adder_A_B_8_bits adder (
SW,
KEY[1],
KEY[0],
sum,
LEDR0,
A,
B
);
decoder_hex_16 ... | 7.592316 |
module decoder_hex_10 (
input [3:0] bcd,
output reg [0:6] H,
output reg E
);
always @(bcd)
if (bcd > 4'b1001) begin
E = 1;
end else begin
E = 0;
case (bcd)
0: H = 7'b0000001;
1: H = 7'b1001111;
2: H = 7'b0010010;
3: H = 7'b0000110;
4: H = 7... | 7.325232 |
module adder_BCD_2_digits (
input [8:0] SW,
output reg [0:6] HEX0,
HEX1,
output [0:6] HEX3,
HEX5,
output [9:0] LEDR
);
wire [4:0] sum;
wire err1, err2;
assign LEDR[7:0] = SW[7:0];
decoder_hex_10 display1 (
SW[7:4],
HEX5,
err2
);
decoder_hex_10 display2 (
SW... | 8.00698 |
module displayNumber (
input [3:0] decimalNumber,
output reg [0:6] displayer
);
always @(*)
case (decimalNumber)
4'b0000: displayer = 7'b0000001;
4'b0001: displayer = 7'b1001111;
4'b0010: displayer = 7'b0010010;
4'b0011: displayer = 7'b0000110;
4'b0100: displayer = 7'b1001100... | 8.666146 |
module displayNumberV2 (
input [3:0] decimalNumber,
output reg [0:6] displayer
);
always @(*)
case (decimalNumber)
0: displayer = 7'b0000001;
1: displayer = 7'b1001111;
2: displayer = 7'b0010010;
3: displayer = 7'b0000110;
4: displayer = 7'b1001100;
5: displayer = 7'b01... | 8.666146 |
module adder_BCD_2_digits_b (
input [8:0] SW,
output [0:6] HEX0,
HEX1,
HEX3,
HEX5,
output [9:0] LEDR
);
assign LEDR[7:0] = SW[7:0];
integer x, y, cin, enteredNumber;
integer zet0, c1, s0, s1;
always @(*) begin
x = SW[3:0];
y = SW[7:4];
cin = SW[8];
enteredNumber = x + y ... | 8.00698 |
module adder_BCD_2_digits_board (
input [8:0] SW,
output [6:0] HEX0,
HEX1,
HEX3,
HEX5,
output [7:0] LEDR,
output LEDR9
);
assign LEDR[7:0] = SW[7:0];
adder_BCD_2_digits(
SW[7:4], SW[3:0], SW[8], HEX5[6:0], HEX3[6:0], HEX0[6:0], HEX1[6:0], LEDR9
);
endmodule
| 8.00698 |
module adder_BCD_2_digits_b_board (
input [8:0] SW,
output [6:0] HEX0,
HEX1,
HEX3,
HEX5,
output [7:0] LEDR,
output LEDR9
);
assign LEDR[7:0] = SW[7:0];
adder_BCD_2_digits_b(
SW[7:4], SW[3:0], SW[8], HEX5[6:0], HEX3[6:0], HEX0[6:0], HEX1[6:0], LEDR9
);
endmodule
| 8.00698 |
module adder_bTB ();
reg clk;
reg signed [15:0] n1, n2;
wire signed [16:0] sum;
adder_b(
.clk(clk), .n1(n1), .n2(n2), .sum(sum)
);
initial begin
clk = 0;
forever #1 clk = ~clk;
end
initial begin : apply_stimulus
integer i;
n1 = 0;
n2 = 0;
for (i = 1; i <= 10; i = i + 1... | 6.542579 |
module approx_adder (
input [7:0] prod1,
input [7:0] prod2,
input [7:0] prod3,
input [7:0] prod4,
output [15:0] PROD
);
LUT6_2 #(
.INIT(64'hFEFEFEFEFEFEFEFE) // Specify LUT Contents
) LUT6_2_inst1 (
.O6(P4), // 1-bit LUT6 output
.I0(prod1[4]), // 1-bit LUT input
.I1(... | 7.183956 |
module adder_cascaded32 (
A,
B,
S,
Ov
);
// Definitions
input wire [31:0] A, B;
output wire [31:0] S;
output wire Ov;
// N bits added need N+1 Cout to Cin connections.
wire [32:0] CotoCin;
// No carry in for the first adder.
assign CotoCin[0] = 0;
// Connects each adder via the Co... | 7.521619 |
module adder_chains #(
parameter MIN_WIDTH = 8,
parameter ADDER_NUM = 4
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input [MIN_WIDTH * ADDER_NUM - 1:0] adder_din,
output [MIN_WIDTH + ADDER_NUM - 1:0] adder_dout
);
genvar i;
generate
for (i = 0; i < ADDER_NUM... | 7.190648 |
module cla_4 (
input wire [3:0] a,
input wire [3:0] b,
input wire c0,
output wire [3:0] s, //sum
output wire G0,
output wire P0
);
wire [3:0] g;
wire [3:0] p;
wire [3:0] c; //carry
assign g = a & b;
assign p = a | b;
assign G0 = g[3] | (p[3] & g[2]) | (p[3] & p[2] & g[1]) | (p[3] ... | 7.145415 |
module adder_clk_gating (
input clk,
input reset_b,
input [15:0] a_in,
input [15:0] b_in,
input carry_in,
output carry_out,
output [15:0] sum_out,
input CG
);
wire temp_carry;
wire clkb;
assign clkb = clk & CG;
adder_8_bit adder_lsb (
.clk(clk),
.reset_b(reset_b),
... | 6.846744 |
module adder_8_bit (
input clk,
input reset_b,
input [7:0] a_in,
input [7:0] b_in,
input carry_in,
output carry_out,
output reg [7:0] sum_out
);
wire [7:0] sum_w;
wire carry_w;
rca rca_0 (
.num1 (a_in),
.num2 (b_in),
.c_in (carry_in),
.carry(carry_w),
... | 7.295209 |
module rca (
input [7:0] num1,
input [7:0] num2,
input c_in,
output carry,
output [7:0] sum
);
wire [7:0] int_sum;
wire [7:0] int_co;
fa u_fa_0 (
.a (num1[0]),
.b (num2[0]),
.c (c_in),
.co (int_co[0]),
.sum(int_sum[0])
);
fa u_fa_1 (
.a (num1[1]),
... | 7.490376 |
module fa (
input a,
input b,
input c,
output co,
output sum
);
assign {co, sum} = a + b + c;
endmodule
| 7.001699 |
module adder_columns (
cout,
sum,
a,
b,
cin
);
input [379:0] a, b;
output [379:0] sum;
input [1:0] cin;
output [1:0] cout;
adder_max ad1 (
.a(a[189:0]),
.b(b[189:0]),
.cin(cin[0]),
.sum(sum[189:0]),
.cout(cout[0])
);
adder_max ad2 (
.a(a[379:190]),... | 6.688807 |
module adder_max (
cout,
sum,
a,
b,
cin
);
parameter size = 190; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size parameter
input cin;
input [size-1:0] a, b; // 'a' and 'b' use the size parameter
assign {cout, sum} = a + b + cin;
e... | 6.648594 |
module adder_controller (
inp,
cin,
set,
unlock,
select,
out,
cout,
setled,
unlockled,
select0led,
select1led,
clk
);
// Assigining ports as in/out
input [7:0] inp;
input cin, set, unlock, clk;
input [1:0] select;
output [7:0] out;
output cout, setled, unlock... | 6.592194 |
module adder_en_tb ();
reg [3:0] add_in;
reg t_en, t_en_n;
wire [1:0] add_out;
adder_en DUT (
.A(add_in[0]),
.B(add_in[1]),
.Cin(add_in[2]),
.Cout(add_out[1]),
.Z(add_out[0]),
.add_en(t_en),
.add_en_n(t_en_n)
);
initial begin
t_en = 1;
t_en_n = 0;
... | 7.236926 |
module, the order is not important.
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module adder_explicit (
result , // Output of the adder
carry , // Carry output of adder
r1 , // first input
r2 , // second input
ci // carry i... | 7.870522 |
module adder_f (
sum,
cout,
a,
b,
cin
);
input a, b, cin;
output sum, cout;
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
| 6.926974 |
module adder_FFs (
a,
b,
clk,
clr,
d_out,
cout
);
input [127:0] a, b;
output [127:0] d_out;
input clr, clk;
output [1:0] cout;
shift_reg sf1 (
.shift_in(a[0]),
.clk(clk),
.clr(clr),
.shift_out(s_out_w)
);
adder ad1 (
.a(a),
.b(b),
.cin(s_... | 6.852735 |
module shift_reg #(
parameter size = 128
) (
shift_in,
clk,
clr,
shift_out
);
// Port Declaration
input shift_in;
input clk;
input clr;
output shift_out;
reg [size:0] shift; // shift register
always @(posedge clk or posedge clr) begin
if (clr) shift = 0;
else shift = {shi... | 9.26065 |
module adder_flex (
input rst,
input clk,
input in1,
output out1
);
reg [7:0] cnt;
assign out1 = 1'b1 & cnt[1];
always @(posedge clk, negedge rst) begin
if (!rst) begin
cnt <= 0;
end else if (cnt < 8'hff) cnt <= cnt + 1;
else if (cnt >= 8'hff) cnt <= 0;
else cnt <= cnt;
... | 6.505438 |
module adder_flexible_biterwidth (
clk,
RST,
a,
b,
result
);
parameter WIDTH_A = 8, WIDTH_B = 8;
//Bit width for input
localparam WIDTH_OUT = 1 + ((WIDTH_A > WIDTH_B) ? (WIDTH_A) : (WIDTH_B));
//Bit width for output: maximum between the width + 1 bit for carried bit
input clk, RST;
inp... | 9.079318 |
modules
`define WIDTH_1 8
`define WIDTH_2 8
`define WIDTH_12 9
`define WIDTH_3 16
//Bit width definition
module adder_flexible_bitWidth_test;
//defination for Variables
reg clk;
reg reset;
wire[`WIDTH_1 -1:0] a1;
wire[`WIDTH_2 -1:0] a2;
wire[`WIDTH_12 -1:0] b1;
wire[`WIDTH_3 -1:0] b2;
wire[`WIDTH_3 + 1 -1:0] c, c1;
/... | 7.377087 |
module Adder_four (
input a0,
input a1,
input b0,
input b1,
output s0,
output s1,
output Carry
);
wire c, cout1, cout2, cout3;
assign {cout1, s0} = a0 + b0;
assign {cout2, c} = cout1 + a1;
assign {cout3, s1} = c + b1;
assign Carry = cout2 + cout3;
endmodule
| 8.295355 |
module Adder_Four_Bit (
A,
B,
Sum,
Reset
);
input [3:0] A, B;
input Reset;
output [4:0] Sum;
wire w1, w2, w3;
Half_Adder f1 (
Sum[0],
w1,
A[0],
B[0],
Reset
);
Full_Adder f2 (
Sum[1],
w2,
A[1],
B[1],
w1,
Reset
);
Full_Add... | 7.913367 |
module Adder_Four_Bit_Out (
A,
B,
Sum,
Reset
);
input [3:0] A, B;
input Reset;
output [3:0] Sum;
wire w1, w2, w3;
Half_Adder f1 (
Sum[0],
w1,
A[0],
B[0],
Reset
);
Full_Adder f2 (
Sum[1],
w2,
A[1],
B[1],
w1,
Reset
);
Full... | 7.913367 |
module: Adder_four
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Adder_four_tb;
// Inputs
reg a0;
reg a1;
reg b0;
reg b1;
// Outputs
wire s0;
wire s1;
wire Carry;
// I... | 6.709555 |
module: adder_fp32
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module adder_fp32_tb;
// Inputs
reg [31:0] x;
reg [31:0] y;
reg op;
reg clk;
reg rd;
reg rese... | 7.125541 |
module adder_full_1bit (
proC,
sum,
add,
aug,
preC
);
input add, aug, preC;
output proC, sum;
assign proC = aug & preC | add & preC | add & aug;
assign sum = ~add & ~aug & preC | ~add & aug & ~preC | add & ~aug & ~preC | add & aug & preC;
endmodule
| 7.179069 |
module adder_full_1bit_tb;
reg add, aug, preC;
wire proC, sum;
//D.U.T. instantiation
adder_full_1bit adder (
proC,
sum,
add,
aug,
preC
);
/*時脈初始化
always
begin
#`CLOCK_FREQ Clk = !Clk;
end
*/
initial begin
//初始化
$dumpfile("Simulation/adder_full_1bit_... | 7.179069 |
module adder_full_4bit (
proC,
sum,
add,
aug,
preC
);
input [3:0] add, aug;
input preC;
output proC;
output [3:0] sum;
wire c3, c2, c1;
adder_full_1bit
fa0 (
c1,
sum[0],
add[0],
aug[0],
preC
),
fa1 (
c2,
... | 7.570751 |
module adder_full_4bit_tb;
reg [3:0] add, aug;
reg preC;
wire proC;
wire [3:0] sum;
//D.U.T. instantiation
adder_full_4bit adder (
proC,
sum,
add,
aug,
preC
);
initial begin
//初始化
$dumpfile("Simulation/adder_full_4bit_tb.vcd");
$dumpvars;
$monitor($time, "... | 7.570751 |
module adder_full_8bit (
proC,
sum,
add,
aug,
preC
);
input [7:0] add;
input [7:0] aug;
input preC;
output proC;
output [7:0] sum;
wire [7:1] c;
adder_full_1bit
fa0 (
c[1],
sum[0],
add[0],
aug[0],
preC
),
fa1 (
... | 7.530642 |
module adder_full_8bit_tb;
reg [7:0] add, aug;
reg preC;
wire proC;
wire [7:0] sum;
//D.U.T. instantiation
adder_full_8bit adder (
proC,
sum,
add,
aug,
preC
);
initial begin
//初始化
$dumpfile("Simulation/adder_full_8bit_tb.vcd");
$dumpvars;
$monitor($time, "... | 7.530642 |
module ks_adder_gate_8 (
x,
y,
carry,
out
);
input [7:0] x, y;
output carry;
output [7:0] out;
wire [7:0] p, g, c, s0;
half_adder_pg ha0 (
x[0],
y[0],
out[0],
g[0]
);
half_adder_pg ha1 (
x[1],
y[1],
p[1],
g[1]
);
half_adder_pg ha2 (
... | 6.742585 |
module adder_gate (
x,
y,
carry,
out
);
input [7:0] x, y;
output carry;
output [7:0] out;
full_adder fa0 (
x[0],
y[0],
1'b0,
out[0],
c0
);
full_adder fa1 (
x[1],
y[1],
c0,
out[1],
c1
);
full_adder fa2 (
x[2],
y[2],
... | 7.321758 |
module half_adder_pg (
x,
y,
p,
g
);
input x, y;
output p, g;
xor #`ADDER_GATE_DELAY xor0 (p, x, y);
and #`ADDER_GATE_DELAY and0 (g, x, y);
endmodule
| 6.552584 |
module adder_gate_tb;
reg input1;
reg input2;
reg carryin;
wire out;
wire carryout;
adder_gate uut (
.x(input1),
.y(input2),
.cin(carryin),
.res(res),
.cout(carryout)
);
initial begin
$dumpfile("adder.vcd");
$dumpvars(0, adder_gate_tb);
input1 = 0;
i... | 7.510645 |
module adder_gate_test;
parameter pattern_num = 13;
wire [7:0] out;
wire carry;
reg [7:0] x, y;
reg clk;
reg stop;
integer i, num, error;
reg [8:0] ans_out;
reg [8:0] adder_out;
reg [7:0] data_base1[0:100];
reg [8:0] data_base2[0:100];
ks_adder_gate_8 A (
x,
y,
carry,
... | 7.355073 |
module adder_h (
sum,
cout,
a,
b
);
input a, b;
output sum, cout;
assign sum = a ^ b;
assign cout = a & b;
endmodule
| 7.873975 |
module adder_half (
x,
y,
sum,
carry
);
input x, y;
output sum, carry;
//* Data-flow modelling
assign carry = x & y;
assign sum = x ^ y; // `^` is xor operation
endmodule
| 7.444731 |
module testbenchforhalfadder;
reg x, y;
wire sum, carry;
adder_half h1 (
x,
y,
sum,
carry
); // we are creating an object h1 using `adder_half` module.
/*
As we change `x` and `y` during run-time of the program, the values of `sum` and `carry` will also change according to the log... | 7.057029 |
module adder_half_1bit (
carry,
sum,
input_a,
input_b
);
//port 類型宣告
output carry, sum;
input input_a, input_b;
xor gate_sum (sum, input_a, input_b);
and gate_carry (carry, input_a, input_b);
endmodule
| 7.43267 |
module adder_half_1bit_testbench ();
//宣告port類型
reg input_a, input_b;
wire output_carry, output_sum;
//D.U.T. instantiation
adder_half_1bit dut (
output_carry,
output_sum,
input_a,
input_b
);
/* 時脈產生器
always begin
#`CLOCK_PERIOD_HALF Clk = !Clk;
end
*/
initial begin
... | 7.43267 |
module adder_hier (
result, // Output of the adder
carry, // Carry output of adder
r1, // first input
r2, // second input
ci // carry input
);
// Input Port Declarations
input [3:0] r1;
input [3:0] r2;
input ci;
// Output Port Declarations
output [3:0] result;
output carr... | 8.160914 |
module tb ();
reg [3:0] r1, r2;
reg ci;
wire [3:0] result;
wire carry;
// Drive the inputs
initial begin
r1 = 0;
r2 = 0;
ci = 0;
#10 r1 = 10;
#10 r2 = 2;
#10 ci = 1;
#10 $display("+--------------------------------------------------------+");
$finish;
end
// Connect the... | 7.195167 |
module adder_hold_register (
clk,
enable_adl,
enable_sb06,
enable_sb7,
data_in,
adl,
sb,
adder_hold_reg
);
input clk; //clk_2
input enable_adl; //net: 1015; aka add_adl
input enable_sb06; //net: 129; aka add_sb06
input enable_sb7; //net: 214; aka add_sb17
input [7:0] data_i... | 7.384802 |
module adder_implicit (
result, // Output of the adder
carry, // Carry output of adder
r1, // first input
r2, // second input
ci // carry input
);
// Input Port Declarations
input [3:0] r1;
input [3:0] r2;
input ci;
// Output Port Declarations
output [3:0] result;
output ... | 7.732806 |
module adder_internal (
input [7:0] a,
input [2:0] b,
output [7:0] y
);
assign y = a + ({{5{2'b0}}, b});
endmodule
| 7.843775 |
module adder_layer #(
parameter ADDER_NUM = 4,
parameter ADDER_WIDTH = 8
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input [ADDER_NUM * ADDER_WIDTH * 2 - 1:0] adder_din,
output [ADDER_NUM * (ADDER_WIDTH + 1) - 1:0] adder_dout
);
genvar i;
generate
for (i =... | 7.382159 |
module fulladder (
s,
cout,
a,
b,
cin
);
output s, cout;
input a, b, cin;
wire partial_s, partial_c1, partial_c2;
halfadder ha0 (
partial_s,
partial_c1,
a,
b
);
halfadder ha1 (
s,
partial_c2,
partial_s,
cin
);
or o1 (cout, partial_c1, ... | 7.454465 |
module adder (
s,
co,
a,
b,
ci
);
output s, co; //Outputs of Sum and Carry Out
input a, b, ci; //Inputs of A, b and Carry In
wire o0, o1, o2; //Internal wiring
xor (s, a, b, ci); //Calculation of Sum
or (o0, a, b); //Calculation of Carry Out
or (o1, b, ci);
or (o2, ci, a);
a... | 7.276647 |
module adder7 (
s,
co,
a,
b,
ci
);
output [6:0] s; //7-bit Sum output
output co; //Output bit of Carry out
input [6:0] a, b; //7-bit Input A and B
input ci; //Input bit of Carry in
wire c1, c2, c3, c4, c5, c6;
adder a0 (
s[0],
c1,
a[0],
b[0],
ci
);... | 7.475421 |
module adder3_2 (
s,
co,
a,
b,
c
);
output [6:0] s,co; //7-bit Sum output and 7-bit carry in where co[0] = 0 (Carry In will be added in later)
input [6:0] a, b, c; //7-bit Input A and B
wire c1; //the last carry bit is not used so assign to bogus entiry
assign co[0] = 0; //assingment of... | 7.235552 |
module adder_lin (
s,
co,
a,
b,
c,
d,
e,
f,
g,
h,
ci
);
output [6:0] s;
output co;
input [6:0] a, b, c, d, e, f, g, h;
input ci;
wire [6:0] s1, s2, s3, s4, s5, s6;
wire [6:0] co1, co2, co3, co4, co5, co6;
//3:2 adders in linear fashion
adder3_2 a0 (
s... | 7.782114 |
modules
module adder_line_generate_test;
//defination for Variables
reg clk;
reg reset;
wire[7:0] d1;
wire[11:0] d2;
wire[4:0] sum1, s1;
wire[6:0] sum2, s2;
//Connection to the modules
counter_parameter #(.WIDTH(8),.MAX_VALUE(2**8 - 1))
C1 ( .clk(clk), .RST(reset), .counter(d1) );
counter_parameter #(.WIDTH(12),... | 6.885623 |
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