code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_5bits (
a,
b,
ci,
s,
co
);
input [4 : 0] a;
input [4 : 0] b;
input ci;
output [4 : 0] s;
output co;
wire [4 : 0] g;
wire [4 : 0] p;
wire [3 : 0] c;
assign g = a & b;
assign p = a | b;
assign c[0] = g[0] | (p[0] & ci);
assign c[1] = g[1] | (p[1] & g[0]) | (p[1] & p[0] & ci);
assign c[2] = g[2] | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & ci);
assign c[3] = g[3] | (p[3] & g[2]) | (p[3] & p[2] & g[1]) | (p[3] & p[2] & p[1] & g[0]) | (p[3] & p[2] & p[1] & p[0] & ci);
assign co = g[4] | (p[4] & g[3]) | (p[4] & p[3] & g[2]) | (p[4] & p[3] & p[2] & g[1]) | (p[4] & p[3] & p[2] & p[1] & p[0] & ci);
assign s = (p & ~g) ^ {c[3 : 0], ci};
endmodule
| 7.029925 |
module adder_6 (
cout,
sum,
a,
b,
cin
);
parameter size = 6; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size parameter
input cin;
input [size-1:0] a, b; // 'a' and 'b' use the size parameter
assign {cout, sum} = a + b + cin;
endmodule
| 7.100413 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module counter input
CLR: module counter input
out_num: output port for the counter module
OV: overflow flag
------------------------------------------------------
History:
01-07-2016: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simulation time assignment
//Insert the modules
module adder_64bits_seperated_32bits_test;
//defination for Variables
reg clk;
reg reset;
reg[7:0] cntr;
wire EN;
wire CLR;
wire[127:0] out_num;
wire OV;
wire[63:0] sum;
wire c;
wire[63:0] sum_test;
wire c_test;
//Connection to the modules
counter128 C1(.clk(clk), .Reset(reset), .EN(EN),
.CLR(CLR), .counter(out_num), .OV(OV));
adder_64bits_seperated_32bits A1
(.a(~out_num[63:0]), .b(~out_num[127:64]),
.CLK(clk), .RST(reset),
.sum(sum), .c(c));
begin
assign {c_test, sum_test} = {1'b0, ~out_num[63:0]} + {1'b0, ~out_num[127:64]};
assign EN = 1'b1;
assign CLR = 1'b0;
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#10 clk = !clk;
//Reverse the clock in each 10ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
//Couner as input
always @(posedge clk or reset)
begin
if ( !reset)
//reset statement: counter keeps at 0
begin
cntr <= 8'h00;
end
else
//Wroking, counter increasing
begin
cntr <= cntr + 8'h01;
end
end
end
endmodule
| 7.206611 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module add_6_bit (
input1,
input2,
answer
);
parameter N = 6;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1[0],
input2[0],
answer[0],
carry[0]
);
else
full_adder f (
input1[i],
input2[i],
carry[i-1],
answer[i],
carry[i]
);
end
assign carry_out = carry[N-1];
endgenerate
endmodule
| 7.079085 |
module adder_6bits (
a,
b,
ci,
s,
co
);
input [5 : 0] a;
input [5 : 0] b;
input ci;
output [5 : 0] s;
output co;
wire [5 : 0] g;
wire [5 : 0] p;
wire [4 : 0] c;
assign g = a & b;
assign p = a | b;
assign c[0] = g[0] | (p[0] & ci);
assign c[1] = g[1] | (p[1] & g[0]) | (p[1] & p[0] & ci);
assign c[2] = g[2] | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & ci);
assign c[3] = g[3] | (p[3] & g[2]) | (p[3] & p[2] & g[1]) | (p[3] & p[2] & p[1] & g[0]) | (p[3] & p[2] & p[1] & p[0] & ci);
assign c[4] = g[4] | (p[4] & g[3]) | (p[4] & p[3] & g[2]) | (p[4] & p[3] & p[2] & g[1]) | (p[4] & p[3] & p[2] & p[1] & g[0]) | (p[4] & p[3] & p[2] & p[1] & p[0] & ci);
assign co = g[5] | (p[5] & g[4]) | (p[5] & p[4] & g[3]) | (p[5] & p[4] & p[3] & g[2]) | (p[5] & p[4] & p[3] & p[2] & g[1]) | (p[5] & p[4] & p[3] & p[2] & p[1] & g[0]) | (p[5] & p[4] & p[3] & p[2] & p[1] & p[0] & ci);
assign s = (p & ~g) ^ {c[4 : 0], ci};
endmodule
| 6.767423 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module adder_8 (
cout,
sum,
a,
b,
cin
);
parameter size = 8; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size parameter
input cin;
input [size-1:0] a, b; // 'a' and 'b' use the size parameter
assign {cout, sum} = a + b + cin;
endmodule
| 7.047398 |
module ADDER_8bit (
cfinal,
sum,
num1,
num2,
cin
);
input [7:0] num1, num2;
output [7:0] sum;
wire [7:0] cout;
input cin;
output cfinal;
FADDER add0 (
sum[0],
cout[0],
num1[0],
num2[0],
cin
);
FADDER add1 (
sum[1],
cout[1],
num1[1],
num2[1],
cout[0]
);
FADDER add2 (
sum[2],
cout[2],
num1[2],
num2[2],
cout[1]
);
FADDER add3 (
sum[3],
cout[3],
num1[3],
num2[3],
cout[2]
);
FADDER add4 (
sum[4],
cout[4],
num1[4],
num2[4],
cout[3]
);
FADDER add5 (
sum[5],
cout[5],
num1[5],
num2[5],
cout[4]
);
FADDER add6 (
sum[6],
cout[6],
num1[6],
num2[6],
cout[5]
);
FADDER add7 (
sum[7],
cout[7],
num1[7],
num2[7],
cout[6]
);
assign cfinal = cout[7];
endmodule
| 6.91515 |
module adder_8bits (
a,
b,
ci,
s,
co
);
input [7 : 0] a;
input [7 : 0] b;
input ci;
output [7 : 0] s;
output co;
wire c;
adder_4bits adder_4bits_inst (
.a (a[3 : 0]),
.b (b[3 : 0]),
.ci(ci),
.s (s[3 : 0]),
.co(c)
);
mux_adder_4bits mux_adder_4bits_inst1 (
.a (a[7 : 4]),
.b (b[7 : 4]),
.ci(c),
.s (s[7 : 4]),
.co(co)
);
endmodule
| 7.981077 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
wire x, y;
wire s, c;
HA1D0BWP g23__2398 (
.A (y),
.B (x),
.CO(c),
.S (s)
);
endmodule
| 6.966406 |
module full_adder_1 (
x,
y,
c_in,
s,
c_out
);
input x, y, c_in;
output s, c_out;
wire x, y, c_in;
wire s, c_out;
FA1D0BWP g61__6260 (
.A (y),
.B (x),
.CI(c_in),
.CO(c_out),
.S (s)
);
endmodule
| 6.657465 |
module csa_adder_8in #(
parameter p_input_width = 14
) (
input [p_input_width-1:0] i_a,
input [p_input_width-1:0] i_b,
input [p_input_width-1:0] i_c,
input [p_input_width-1:0] i_d,
input [p_input_width-1:0] i_e,
input [p_input_width-1:0] i_f,
input [p_input_width-1:0] i_g,
input [p_input_width-1:0] i_h,
output [p_input_width+2:0] o_s
);
wire [p_input_width-1:0] w_p10;
wire [p_input_width-1:0] w_p11;
wire [p_input_width-1:0] w_g10;
wire [p_input_width-1:0] w_g11;
wire [p_input_width-1:0] w_s11;
wire [p_input_width-1:0] w_p20;
wire [p_input_width-1:0] w_p21;
wire [p_input_width-1:0] w_g20;
wire [p_input_width-1:0] w_g21;
wire [p_input_width-1:0] w_s12;
wire [p_input_width : 0] w_co11;
wire [p_input_width+1:0] w_co12;
wire [p_input_width+1:0] w_s21;
wire [p_input_width+1:0] w_s22;
wire [p_input_width : 0] w_co21;
wire [p_input_width+1:0] w_co22;
assign w_p10 = i_a ^ i_b;
assign w_p11 = i_c ^ i_d;
assign w_g10 = i_a & i_b;
assign w_g11 = i_c & i_d;
assign w_s11 = w_p10 ^ w_p11;
assign w_co11 = {((w_g10 & ~w_g11) | (~w_g10 & w_g11) | (w_p10 & w_p11)), 1'b0};
assign w_co12 = {(w_g10 & w_g11), 2'b0};
assign w_p20 = i_e ^ i_f;
assign w_p21 = i_g ^ i_h;
assign w_g20 = i_e & i_f;
assign w_g21 = i_g & i_h;
assign w_s12 = w_p20 ^ w_p21;
assign w_co21 = {((w_g20 & ~w_g21) | (~w_g20 & w_g21) | (w_p20 & w_p21)), 1'b0};
assign w_co22 = {(w_g20 & w_g21), 2'b0};
assign w_s21 = w_s11 + w_co11 + w_co12;
assign w_s22 = w_s12 + w_co21 + w_co22;
assign o_s = {1'b0, w_s21} + {1'b0, w_s22};
endmodule
| 6.912097 |
module adder_8_bit (
input [7:0] a,
input [7:0] b,
output [7:0] sum,
output c_out
);
wire c_in;
assign c_in = 1'b0;
fulladder_1_bit f0 (
.a(a[0]),
.b(b[0]),
.c_in(c_in),
.s(sum[0]),
.c_out(ripple0)
);
fulladder_1_bit f1 (
.a(a[1]),
.b(b[1]),
.c_in(ripple0),
.s(sum[1]),
.c_out(ripple1)
);
fulladder_1_bit f2 (
.a(a[2]),
.b(b[2]),
.c_in(ripple1),
.s(sum[2]),
.c_out(ripple2)
);
fulladder_1_bit f3 (
.a(a[3]),
.b(b[3]),
.c_in(ripple2),
.s(sum[3]),
.c_out(ripple3)
);
fulladder_1_bit f4 (
.a(a[4]),
.b(b[4]),
.c_in(ripple3),
.s(sum[4]),
.c_out(ripple4)
);
fulladder_1_bit f5 (
.a(a[5]),
.b(b[5]),
.c_in(ripple4),
.s(sum[5]),
.c_out(ripple5)
);
fulladder_1_bit f6 (
.a(a[6]),
.b(b[6]),
.c_in(ripple5),
.s(sum[6]),
.c_out(ripple6)
);
fulladder_1_bit f7 (
.a(a[7]),
.b(b[7]),
.c_in(ripple6),
.s(sum[7]),
.c_out(c_out)
);
endmodule
| 7.295209 |
module adder_8_bit_with_overflow_test;
// Inputs
reg [7:0] a;
reg [7:0] b;
// Outputs
wire [7:0] sum;
wire c_out;
wire overflow;
integer i;
// Instantiate the Unit Under Test (UUT)
adder_8_bit_with_overflow uut (
.a(a),
.b(b),
.sum(sum),
.c_out(c_out),
.overflow(overflow)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
end
initial $monitor("a(%b) + b(%b) = carry sum overflow(%b %b %b)", a, b, c_out, sum, overflow);
always @(a or b) begin
for (i = 0; i < 16 * 16 * 16 * 16; i = i + 1) #1{a, b} = i;
end
endmodule
| 6.773302 |
module adder_3bits (
a,
b,
ci,
s,
co
);
input [2 : 0] a;
input [2 : 0] b;
input ci;
output [2 : 0] s;
output co;
wire [2 : 0] g;
wire [2 : 0] p;
wire [1 : 0] c;
assign g = a & b;
assign p = a | b;
assign c[0] = g[0] | (p[0] & ci);
assign c[1] = g[1] | (p[1] & g[0]) | (p[1] & p[0] & ci);
assign co = g[2] | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & ci);
assign s = (p & ~g) ^ {c[1 : 0], ci};
endmodule
| 7.015374 |
module mux_adder_3bits (
a,
b,
ci,
s,
co
);
input [2 : 0] a;
input [2 : 0] b;
input ci;
output [2 : 0] s;
output co;
wire c0, c1;
wire [2 : 0] s0, s1;
adder_3bits adder_inst1 (
.a (a),
.b (b),
.ci(1'b1),
.s (s1),
.co(c1)
);
adder_3bits adder_inst0 (
.a (a),
.b (b),
.ci(1'b0),
.s (s0),
.co(c0)
);
assign co = (ci & c1) | c0;
assign s = ci ? s1 : s0;
endmodule
| 6.93875 |
module adder_9bits (
a,
b,
ci,
s,
co
);
input [8 : 0] a;
input [8 : 0] b;
input ci;
output [8 : 0] s;
output co;
wire [1 : 0] c;
adder_3bits adder_3bits_inst (
.a (a[2 : 0]),
.b (b[2 : 0]),
.ci(ci),
.s (s[2 : 0]),
.co(c[0])
);
mux_adder_3bits mux_adder_3bits_inst1 (
.a (a[5 : 3]),
.b (b[5 : 3]),
.ci(c[0]),
.s (s[5 : 3]),
.co(c[1])
);
mux_adder_3bits mux_adder_3bits_inst2 (
.a (a[8 : 6]),
.b (b[8 : 6]),
.ci(c[1]),
.s (s[8 : 6]),
.co(co)
);
endmodule
| 7.505426 |
module MUX1 (
input [7:0] In1,
In2,
input Sel,
output [7:0] Out
);
assign Out = (Sel == 1) ? In1 : In2;
endmodule
| 7.237621 |
module adder_array (
cmd,
ain0,
ain1,
ain2,
ain3,
bin0,
bin1,
bin2,
bin3,
dout0,
dout1,
dout2,
dout3,
overflow
);
parameter BIT_WIDTH = 32;
input [2:0] cmd;
input [BIT_WIDTH-1:0] ain0, ain1, ain2, ain3;
input [BIT_WIDTH-1:0] bin0, bin1, bin2, bin3;
output reg [BIT_WIDTH-1:0] dout0, dout1, dout2, dout3;
output reg [3:0] overflow;
wire [BIT_WIDTH*4-1:0] ain = {ain3, ain2, ain1, ain0};
wire [BIT_WIDTH*4-1:0] bin = {bin3, bin2, bin1, bin0};
wire [BIT_WIDTH*4-1:0] dout;
wire [3:0] temp_overflow;
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin : add
my_add my_add_impl (
ain[BIT_WIDTH*(i+1)-1 : BIT_WIDTH*i],
bin[BIT_WIDTH*(i+1)-1 : BIT_WIDTH*i],
dout[BIT_WIDTH*(i+1)-1 : BIT_WIDTH*i],
temp_overflow[i]
);
end
endgenerate
always @(*) begin
if (cmd == 3'b000) begin
{dout3, dout2, dout1, dout0} = {
{(BIT_WIDTH * 3) {1'b0}}, dout[(BIT_WIDTH*1)-1 : (BIT_WIDTH*0)], {(BIT_WIDTH * 0) {1'b0}}
};
overflow = {{3{1'b0}}, temp_overflow[0], {0{1'b0}}};
end else if (cmd == 3'b001) begin
{dout3, dout2, dout1, dout0} = {
{(BIT_WIDTH * 2) {1'b0}}, dout[(BIT_WIDTH*2)-1 : (BIT_WIDTH*1)], {(BIT_WIDTH * 1) {1'b0}}
};
overflow = {{2{1'b0}}, temp_overflow[1], {1{1'b0}}};
end else if (cmd == 3'b010) begin
{dout3, dout2, dout1, dout0} = {
{(BIT_WIDTH * 1) {1'b0}}, dout[(BIT_WIDTH*3)-1 : (BIT_WIDTH*2)], {(BIT_WIDTH * 2) {1'b0}}
};
overflow = {{1{1'b0}}, temp_overflow[2], {2{1'b0}}};
end else if (cmd == 3'b011) begin
{dout3, dout2, dout1, dout0} = {
{(BIT_WIDTH * 0) {1'b0}}, dout[(BIT_WIDTH*4)-1 : (BIT_WIDTH*3)], {(BIT_WIDTH * 3) {1'b0}}
};
overflow = {{0{1'b0}}, temp_overflow[3], {3{1'b0}}};
end else if (cmd == 3'b100) begin
{dout3, dout2, dout1, dout0} = dout;
overflow = temp_overflow;
end else begin
$display("invalid cmd: %d", cmd);
end
end
endmodule
| 8.320408 |
module adder_aTB ();
reg clk;
reg signed [15:0] n1, n2;
wire signed [16:0] sum;
adder_a(
.clk(clk), .n1(n1), .n2(n2), .sum(sum)
);
initial begin
clk = 0;
forever #1 clk = ~clk;
end
initial begin
$monitor("n1 = %d, n2 = %d, sum = %d", n1, n2, sum);
end
initial begin : apply_stimulus
integer i;
n1 = -6;
n2 = -6;
for (i = -5; i <= 5; i = i + 1) begin
#2;
n1 = i;
n2 = i;
end
#2;
end
endmodule
| 6.909664 |
module regN (
reset,
CLK,
D,
Q
);
input reset;
input CLK;
parameter N = 8;
input [N-1:0] D;
output [N-1:0] Q;
reg [N-1:0] Q;
always @(posedge CLK or posedge reset)
if (reset) Q = 0;
else Q = D;
endmodule
| 7.765402 |
module adder_A_B_8_bits (
input [7:0] SW,
input [1:0] KEY,
output [0:6] HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
output [0:0] LEDR
);
wire [7:0] myNumber;
regN #(8) newRegister (
~KEY[0],
~KEY[1],
SW[7:0],
myNumber
);
integer sum, cout, mod16, multiple16, _sum;
integer firstMod, firstMulti;
integer secondMod, secondMulti;
always @(SW[7:0] or myNumber[7:0]) begin
/* sumator */
sum = SW[7:0] + myNumber[7:0];
_sum = sum % 256;
cout = sum / 256 > 0 ? 1 : 0;
mod16 = _sum % 16;
multiple16 = _sum / 16;
/* odejmowanie
if(SW[7:0] > myNumber[7:0]) begin
cout = 1;
sum = SW[7:0] - myNumber[7:0];
end
else begin
cout = 0;
sum = myNumber[7:0] - SW[7:0];
end
mod16 = sum % 16;
multiple16 = sum / 16;
/* koniec odejmowania */
firstMod = SW[7:0] % 16;
firstMulti = SW[7:0] / 16;
secondMod = myNumber[7:0] % 16;
secondMulti = myNumber[7:0] / 16;
end
assign LEDR[0] = cout;
displayer displayHex5 (
multiple16,
HEX5
);
displayer displayHex4 (
mod16,
HEX4
);
displayer displayHex3 (
firstMulti,
HEX3
);
displayer displayHex2 (
firstMod,
HEX2
);
displayer displayHex1 (
secondMulti,
HEX1
);
displayer displayHex0 (
secondMod,
HEX0
);
endmodule
| 7.592316 |
module adder_A_B_8_bits_board (
input [7:0] SW,
input [1:0] KEY,
output [6:0] HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
output LEDR0
);
wire [7:0] sum, A, B;
adder_A_B_8_bits adder (
SW,
KEY[1],
KEY[0],
sum,
LEDR0,
A,
B
);
decoder_hex_16 hA1 (
(A / 16),
HEX3
);
decoder_hex_16 hA2 (
(A % 16),
HEX2
);
decoder_hex_16 hB1 (
(B / 16),
HEX1
);
decoder_hex_16 hB2 (
(B % 16),
HEX0
);
decoder_hex_16 hS1 (
(sum / 16),
HEX5
);
decoder_hex_16 hS2 (
(sum % 16),
HEX4
);
endmodule
| 7.592316 |
module decoder_hex_10 (
input [3:0] bcd,
output reg [0:6] H,
output reg E
);
always @(bcd)
if (bcd > 4'b1001) begin
E = 1;
end else begin
E = 0;
case (bcd)
0: H = 7'b0000001;
1: H = 7'b1001111;
2: H = 7'b0010010;
3: H = 7'b0000110;
4: H = 7'b1001100;
5: H = 7'b0100100;
6: H = 7'b0100000;
7: H = 7'b0001111;
8: H = 7'b0000000;
9: H = 7'b0000100;
default: H = 7'b1111111;
endcase
end
endmodule
| 7.325232 |
module adder_BCD_2_digits (
input [8:0] SW,
output reg [0:6] HEX0,
HEX1,
output [0:6] HEX3,
HEX5,
output [9:0] LEDR
);
wire [4:0] sum;
wire err1, err2;
assign LEDR[7:0] = SW[7:0];
decoder_hex_10 display1 (
SW[7:4],
HEX5,
err2
);
decoder_hex_10 display2 (
SW[3:0],
HEX3,
err1
);
assign LEDR[9] = err1 | err2;
assign sum[4:0] = SW[3:0] + SW[7:4] + SW[8];
always @(sum) begin
case (sum)
0: begin
HEX0 = 7'b0000001;
HEX1 = 7'b0000001;
end
1: begin
HEX0 = 7'b1001111;
HEX1 = 7'b0000001;
end
2: begin
HEX0 = 7'b0010010;
HEX1 = 7'b0000001;
end
3: begin
HEX0 = 7'b0000110;
HEX1 = 7'b0000001;
end
4: begin
HEX0 = 7'b1001100;
HEX1 = 7'b0000001;
end
5: begin
HEX0 = 7'b0100100;
HEX1 = 7'b0000001;
end
6: begin
HEX0 = 7'b0100000;
HEX1 = 7'b0000001;
end
7: begin
HEX0 = 7'b0001111;
HEX1 = 7'b0000001;
end
8: begin
HEX0 = 7'b0000000;
HEX1 = 7'b0000001;
end
9: begin
HEX0 = 7'b0000100;
HEX1 = 7'b0000001;
end
10: begin
HEX0 = 7'b0000001;
HEX1 = 7'b1001111;
end
11: begin
HEX0 = 7'b1001111;
HEX1 = 7'b1001111;
end
12: begin
HEX0 = 7'b0010010;
HEX1 = 7'b1001111;
end
13: begin
HEX0 = 7'b0000110;
HEX1 = 7'b1001111;
end
14: begin
HEX0 = 7'b1001100;
HEX1 = 7'b1001111;
end
15: begin
HEX0 = 7'b0100100;
HEX1 = 7'b1001111;
end
16: begin
HEX0 = 7'b0100000;
HEX1 = 7'b1001111;
end
17: begin
HEX0 = 7'b0001111;
HEX1 = 7'b1001111;
end
18: begin
HEX0 = 7'b0000000;
HEX1 = 7'b1001111;
end
19: begin
HEX0 = 7'b0000100;
HEX1 = 7'b1001111;
end
default: begin
HEX0 = 7'b1111111;
HEX1 = 7'b1111111;
end
endcase
if (err1 | err2) begin
HEX0 = 7'b1111111;
HEX1 = 7'b1111111;
end
end
endmodule
| 8.00698 |
module displayNumber (
input [3:0] decimalNumber,
output reg [0:6] displayer
);
always @(*)
case (decimalNumber)
4'b0000: displayer = 7'b0000001;
4'b0001: displayer = 7'b1001111;
4'b0010: displayer = 7'b0010010;
4'b0011: displayer = 7'b0000110;
4'b0100: displayer = 7'b1001100;
4'b0101: displayer = 7'b0100100;
4'b0110: displayer = 7'b0100000;
4'b0111: displayer = 7'b0001111;
4'b1000: displayer = 7'b0000000;
4'b1001: displayer = 7'b0000100;
default: displayer = 7'b1111111;
endcase
endmodule
| 8.666146 |
module displayNumberV2 (
input [3:0] decimalNumber,
output reg [0:6] displayer
);
always @(*)
case (decimalNumber)
0: displayer = 7'b0000001;
1: displayer = 7'b1001111;
2: displayer = 7'b0010010;
3: displayer = 7'b0000110;
4: displayer = 7'b1001100;
5: displayer = 7'b0100100;
6: displayer = 7'b0100000;
7: displayer = 7'b0001111;
8: displayer = 7'b0000000;
9: displayer = 7'b0000100;
default: displayer = 7'b1111111;
endcase
endmodule
| 8.666146 |
module adder_BCD_2_digits_b (
input [8:0] SW,
output [0:6] HEX0,
HEX1,
HEX3,
HEX5,
output [9:0] LEDR
);
assign LEDR[7:0] = SW[7:0];
integer x, y, cin, enteredNumber;
integer zet0, c1, s0, s1;
always @(*) begin
x = SW[3:0];
y = SW[7:4];
cin = SW[8];
enteredNumber = x + y + cin;
if (enteredNumber > 19) begin
s0 = 10;
s1 = 10;
end else if (enteredNumber > 9) begin
zet0 = 10;
c1 = 1;
s0 = enteredNumber - zet0;
s1 = c1;
end else begin
zet0 = 0;
c1 = 0;
s0 = enteredNumber;
s1 = c1;
end
end
displayNumber(
SW[3:0], HEX3
); displayNumber(
SW[7:4], HEX5
); displayNumberV2(
s0, HEX0
); displayNumberV2(
s1, HEX1
);
endmodule
| 8.00698 |
module adder_BCD_2_digits_board (
input [8:0] SW,
output [6:0] HEX0,
HEX1,
HEX3,
HEX5,
output [7:0] LEDR,
output LEDR9
);
assign LEDR[7:0] = SW[7:0];
adder_BCD_2_digits(
SW[7:4], SW[3:0], SW[8], HEX5[6:0], HEX3[6:0], HEX0[6:0], HEX1[6:0], LEDR9
);
endmodule
| 8.00698 |
module adder_BCD_2_digits_b_board (
input [8:0] SW,
output [6:0] HEX0,
HEX1,
HEX3,
HEX5,
output [7:0] LEDR,
output LEDR9
);
assign LEDR[7:0] = SW[7:0];
adder_BCD_2_digits_b(
SW[7:4], SW[3:0], SW[8], HEX5[6:0], HEX3[6:0], HEX0[6:0], HEX1[6:0], LEDR9
);
endmodule
| 8.00698 |
module adder_bTB ();
reg clk;
reg signed [15:0] n1, n2;
wire signed [16:0] sum;
adder_b(
.clk(clk), .n1(n1), .n2(n2), .sum(sum)
);
initial begin
clk = 0;
forever #1 clk = ~clk;
end
initial begin : apply_stimulus
integer i;
n1 = 0;
n2 = 0;
for (i = 1; i <= 10; i = i + 1) begin
#2;
n1 = i;
n2 = i;
end
#2;
end
endmodule
| 6.542579 |
module approx_adder (
input [7:0] prod1,
input [7:0] prod2,
input [7:0] prod3,
input [7:0] prod4,
output [15:0] PROD
);
LUT6_2 #(
.INIT(64'hFEFEFEFEFEFEFEFE) // Specify LUT Contents
) LUT6_2_inst1 (
.O6(P4), // 1-bit LUT6 output
.I0(prod1[4]), // 1-bit LUT input
.I1(prod2[0]), // 1-bit LUT input
.I2(prod3[0]), // 1-bit LUT input
.I3(1'b0), // 1-bit LUT input
.I4(1'b0), // 1-bit LUT input
.I5(1'b0) // 1-bit LUT input (fast MUX select only available to O6 output)
);
LUT6_2 #(
.INIT(64'hFEFEFEFEFEFEFEFE) // Specify LUT Contents
) LUT6_2_inst2 (
.O6(P5), // 1-bit LUT6 output
.I0(prod1[5]), // 1-bit LUT input
.I1(prod2[1]), // 1-bit LUT input
.I2(prod3[1]), // 1-bit LUT input
.I3(1'b0), // 1-bit LUT input
.I4(1'b0), // 1-bit LUT input
.I5(1'b0) // 1-bit LUT input
);
LUT6_2 #(
.INIT(64'hFEFEFEFEFEFEFEFE) // Specify LUT Contents
) LUT6_2_inst3 (
.O6(P6), // 1-bit LUT6 output
.I0(prod1[6]), // 1-bit LUT input
.I1(prod2[2]), // 1-bit LUT input
.I2(prod3[2]), // 1-bit LUT input
.I3(1'b0), // 1-bit LUT input
.I4(1'b0), // 1-bit LUT input
.I5(1'b0) // 1-bit LUT input
);
LUT6_2 #(
.INIT(64'hFFFFFFFEFFFEFEFE) // Specify LUT Contents
) LUT6_2_inst4 (
.O6(P7), // 1-bit LUT6 output
.I0(prod1[7]), // 1-bit LUT input
.I1(prod2[3]), // 1-bit LUT input
.I2(prod3[3]), // 1-bit LUT input
.I3(prod1[6]), // 1-bit LUT input
.I4(prod2[2]), // 1-bit LUT input
.I5(prod3[2]) // 1-bit LUT input
);
LUT6_2 #(
.INIT(64'hFFFFFFFEFFFEFEFE) // Specify LUT Contents
) LUT6_2_inst5 (
.O6(P8), // 1-bit LUT6 output
.I0(prod2[4]), // 1-bit LUT input
.I1(prod3[4]), // 1-bit LUT input
.I2(prod4[0]), // 1-bit LUT input
.I3(prod1[7]), // 1-bit LUT input
.I4(prod2[3]), // 1-bit LUT input
.I5(prod3[3]) // 1-bit LUT input
);
LUT6_2 #(
.INIT(64'hFFFFFFFEFFFEFEFE) // Specify LUT Contents
) LUT6_2_inst6 (
.O6(P9), // 1-bit LUT6 output
.I0(prod2[5]), // 1-bit LUT input
.I1(prod3[5]), // 1-bit LUT input
.I2(prod4[1]), // 1-bit LUT input
.I3(prod2[4]), // 1-bit LUT input
.I4(prod3[4]), // 1-bit LUT input
.I5(prod4[0]) // 1-bit LUT input
);
LUT6_2 #(
.INIT(64'hFFFFFFFEFFFEFEFE) // Specify LUT Contents
) LUT6_2_inst7 (
.O6(P10), // 1-bit LUT6 output
.I0(prod2[6]), // 1-bit LUT input
.I1(prod3[6]), // 1-bit LUT input
.I2(prod4[2]), // 1-bit LUT input
.I3(prod2[5]), // 1-bit LUT input
.I4(prod3[5]), // 1-bit LUT input
.I5(prod4[1]) // 1-bit LUT input (fast MUX select only available to O6 output)
);
LUT6_2 #(
.INIT(64'hFFFFFFFEFFFEFEFE) // Specify LUT Contents
) LUT6_2_inst8 (
.O6(P11), // 1-bit LUT6 output
.I0(prod2[7]), // 1-bit LUT input
.I1(prod3[7]), // 1-bit LUT input
.I2(prod4[3]), // 1-bit LUT input
.I3(prod2[6]), // 1-bit LUT input
.I4(prod3[6]), // 1-bit LUT input
.I5(prod4[2]) // 1-bit LUT input (fast MUX select only available to O6 output)
);
assign PROD = {
prod4[7],
prod4[6],
prod4[5],
prod4[4],
P11,
P10,
P9,
P8,
P7,
P6,
P5,
P4,
prod1[3],
prod1[2],
prod1[1],
prod1[0]
};
endmodule
| 7.183956 |
module adder_cascaded32 (
A,
B,
S,
Ov
);
// Definitions
input wire [31:0] A, B;
output wire [31:0] S;
output wire Ov;
// N bits added need N+1 Cout to Cin connections.
wire [32:0] CotoCin;
// No carry in for the first adder.
assign CotoCin[0] = 0;
// Connects each adder via the CotoCin wire.
generate
genvar i;
for (i = 1; i < 33; i = i + 1) begin
adder_1bit adder_gen (
.A (A[i-1]),
.B (B[i-1]),
.Ci(CotoCin[i-1]),
.Co(CotoCin[i]),
.S (S[i-1])
);
end
endgenerate
// XORing the last two Co's yield an overflow truth.
assign Ov = CotoCin[32] ^ CotoCin[31];
endmodule
| 7.521619 |
module adder_chains #(
parameter MIN_WIDTH = 8,
parameter ADDER_NUM = 4
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input [MIN_WIDTH * ADDER_NUM - 1:0] adder_din,
output [MIN_WIDTH + ADDER_NUM - 1:0] adder_dout
);
genvar i;
generate
for (i = 0; i < ADDER_NUM; i = i + 1) begin : layer
reg [MIN_WIDTH + i:0] layer_result;
wire [MIN_WIDTH + i - 1:0] layer_din0, layer_din1;
if (i == 0) begin
assign layer_din0 = adder_din[MIN_WIDTH-1:0];
assign layer_din1 = adder_din[2*MIN_WIDTH-1:MIN_WIDTH];
end else begin
assign layer_din0 = layer[i-1].layer_result;
assign layer_din1 = {adder_din[i*MIN_WIDTH+:MIN_WIDTH]};
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
layer_result <= 'b0;
end else begin
layer_result <= layer_din0 + layer_din1;
end
end
end
endgenerate
assign adder_dout = layer[ADDER_NUM-1].layer_result;
endmodule
| 7.190648 |
module cla_4 (
input wire [3:0] a,
input wire [3:0] b,
input wire c0,
output wire [3:0] s, //sum
output wire G0,
output wire P0
);
wire [3:0] g;
wire [3:0] p;
wire [3:0] c; //carry
assign g = a & b;
assign p = a | b;
assign G0 = g[3] | (p[3] & g[2]) | (p[3] & p[2] & g[1]) | (p[3] & p[2] & p[1] & g[0]);
assign P0 = &p;
//c4 = G0 + P0*c0
//carry look ahead
assign c = {
g[2] | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & c0), //c3
g[1] | (p[1] & g[0]) | (p[1] & p[0] & c0), //c2
g[0] | (p[0] & c0), //c1
c0
}; //c0
assign s = a ^ b ^ c;
endmodule
| 7.145415 |
module adder_clk_gating (
input clk,
input reset_b,
input [15:0] a_in,
input [15:0] b_in,
input carry_in,
output carry_out,
output [15:0] sum_out,
input CG
);
wire temp_carry;
wire clkb;
assign clkb = clk & CG;
adder_8_bit adder_lsb (
.clk(clk),
.reset_b(reset_b),
.a_in(a_in[7:0]),
.b_in(b_in[7:0]),
.carry_in(carry_in),
.carry_out(temp_carry),
.sum_out(sum_out[7:0])
);
adder_8_bit adder_msb (
.clk(clkb),
.reset_b(reset_b),
.a_in(a_in[15:8]),
.b_in(b_in[15:8]),
.carry_in(temp_carry),
.carry_out(carry_out),
.sum_out(sum_out[15:8])
);
endmodule
| 6.846744 |
module adder_8_bit (
input clk,
input reset_b,
input [7:0] a_in,
input [7:0] b_in,
input carry_in,
output carry_out,
output reg [7:0] sum_out
);
wire [7:0] sum_w;
wire carry_w;
rca rca_0 (
.num1 (a_in),
.num2 (b_in),
.c_in (carry_in),
.carry(carry_w),
.sum (sum_w)
);
always @(posedge clk or negedge reset_b) begin
if (!reset_b) begin
sum_out <= 0;
//carry_out <= 0 ;
end else begin
sum_out <= sum_w;
//carry_out <= carry_w ;
end
end
assign carry_out = carry_w;
endmodule
| 7.295209 |
module rca (
input [7:0] num1,
input [7:0] num2,
input c_in,
output carry,
output [7:0] sum
);
wire [7:0] int_sum;
wire [7:0] int_co;
fa u_fa_0 (
.a (num1[0]),
.b (num2[0]),
.c (c_in),
.co (int_co[0]),
.sum(int_sum[0])
);
fa u_fa_1 (
.a (num1[1]),
.b (num2[1]),
.c (int_co[0]),
.co (int_co[1]),
.sum(int_sum[1])
);
fa u_fa_2 (
.a (num1[2]),
.b (num2[2]),
.c (int_co[1]),
.co (int_co[2]),
.sum(int_sum[2])
);
fa u_fa_3 (
.a (num1[3]),
.b (num2[3]),
.c (int_co[2]),
.co (int_co[3]),
.sum(int_sum[3])
);
fa u_fa_4 (
.a (num1[4]),
.b (num2[4]),
.c (int_co[3]),
.co (int_co[4]),
.sum(int_sum[4])
);
fa u_fa_5 (
.a (num1[5]),
.b (num2[5]),
.c (int_co[4]),
.co (int_co[5]),
.sum(int_sum[5])
);
fa u_fa_6 (
.a (num1[6]),
.b (num2[6]),
.c (int_co[5]),
.co (int_co[6]),
.sum(int_sum[6])
);
fa u_fa_7 (
.a (num1[7]),
.b (num2[7]),
.c (int_co[6]),
.co (int_co[7]),
.sum(int_sum[7])
);
assign sum[7:0] = int_sum;
assign carry = int_co[7];
endmodule
| 7.490376 |
module fa (
input a,
input b,
input c,
output co,
output sum
);
assign {co, sum} = a + b + c;
endmodule
| 7.001699 |
module adder_columns (
cout,
sum,
a,
b,
cin
);
input [379:0] a, b;
output [379:0] sum;
input [1:0] cin;
output [1:0] cout;
adder_max ad1 (
.a(a[189:0]),
.b(b[189:0]),
.cin(cin[0]),
.sum(sum[189:0]),
.cout(cout[0])
);
adder_max ad2 (
.a(a[379:190]),
.b(b[379:190]),
.cin(cin[1]),
.sum(sum[379:190]),
.cout(cout[1])
);
endmodule
| 6.688807 |
module adder_max (
cout,
sum,
a,
b,
cin
);
parameter size = 190; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size parameter
input cin;
input [size-1:0] a, b; // 'a' and 'b' use the size parameter
assign {cout, sum} = a + b + cin;
endmodule
| 6.648594 |
module adder_controller (
inp,
cin,
set,
unlock,
select,
out,
cout,
setled,
unlockled,
select0led,
select1led,
clk
);
// Assigining ports as in/out
input [7:0] inp;
input cin, set, unlock, clk;
input [1:0] select;
output [7:0] out;
output cout, setled, unlockled, select0led, select1led;
// Logic connections
// For the locking mechanism, to handle bounce of the buttons
reg lock;
initial lock = 1'b0;
assign setled = set;
assign unlockled = unlock;
assign select0led = select[0];
assign select1led = select[1];
// Registers required
reg [31:0] numA, numB;
wire [31:0] sum;
reg [ 2:0] counter;
initial begin
numA = 0;
numB = 0;
counter = 3'b000;
end
// Connecting the adder
sklansky_adder Sklansky_adder (
numA,
numB,
cin,
sum,
cout
);
// Getting output
assign out = (select == 2'b00) ? sum[7:0] :
((select == 2'b01) ? sum[15:8] :
((select == 2'b10) ? sum[23:16] : sum[31:24]));
// To fill in the registers on pressing setA and setB
always @(posedge clk) begin
if (set == 1 && lock == 0) begin
case (counter)
3'b000: numA[7:0] = inp;
3'b001: numA[15:8] = inp;
3'b010: numA[23:16] = inp;
3'b011: numA[31:24] = inp;
3'b100: numB[7:0] = inp;
3'b101: numB[15:8] = inp;
3'b110: numB[23:16] = inp;
3'b111: numB[31:24] = inp;
endcase
counter = counter + 3'b001;
lock = 1'b1;
end else if (unlock == 1) begin
lock = 1'b0;
end
end
endmodule
| 6.592194 |
module adder_en_tb ();
reg [3:0] add_in;
reg t_en, t_en_n;
wire [1:0] add_out;
adder_en DUT (
.A(add_in[0]),
.B(add_in[1]),
.Cin(add_in[2]),
.Cout(add_out[1]),
.Z(add_out[0]),
.add_en(t_en),
.add_en_n(t_en_n)
);
initial begin
t_en = 1;
t_en_n = 0;
for (add_in = 0; add_in < 8; add_in = add_in + 1) begin
#1
if (add_out != add_in[0] + add_in[1] + add_in[2]) begin
$display("ERROR, %x != %b + %b + %b", add_out, add_in[0], add_in[1], add_in[2]);
$stop;
end
end
t_en = 0;
t_en_n = 1;
for (add_in = 0; add_in < 8; add_in = add_in + 1) begin
#1
if (add_out != add_in[0] + add_in[1] + add_in[2]) begin
$display("ERROR, %x != %b + %b + %b", add_out, add_in[0], add_in[1], add_in[2]);
$stop;
end
end
end
endmodule
| 7.236926 |
module, the order is not important.
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module adder_explicit (
result , // Output of the adder
carry , // Carry output of adder
r1 , // first input
r2 , // second input
ci // carry input
);
// Input Port Declarations
input [3:0] r1 ;
input [3:0] r2 ;
input ci ;
// Output Port Declarations
output [3:0] result ;
output carry ;
// Port Wires
wire [3:0] r1 ;
wire [3:0] r2 ;
wire ci ;
wire [3:0] result ;
wire carry ;
// Internal variables
wire c1 ;
wire c2 ;
wire c3 ;
// Code Starts Here
addbit u0 (
.a (r1[0]) ,
.b (r2[0]) ,
.ci (ci) ,
.sum (result[0]) ,
.co (c1)
);
addbit u1 (
.a (r1[1]) ,
.b (r2[1]) ,
.ci (c1) ,
.sum (result[1]) ,
.co (c2)
);
addbit u2 (
.a (r1[2]) ,
.b (r2[2]) ,
.ci (c2) ,
.sum (result[2]) ,
.co (c3)
);
addbit u3 (
.a (r1[3]) ,
.b (r2[3]) ,
.ci (c3) ,
.sum (result[3]) ,
.co (carry)
);
endmodule
| 7.870522 |
module adder_f (
sum,
cout,
a,
b,
cin
);
input a, b, cin;
output sum, cout;
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
| 6.926974 |
module adder_FFs (
a,
b,
clk,
clr,
d_out,
cout
);
input [127:0] a, b;
output [127:0] d_out;
input clr, clk;
output [1:0] cout;
shift_reg sf1 (
.shift_in(a[0]),
.clk(clk),
.clr(clr),
.shift_out(s_out_w)
);
adder ad1 (
.a(a),
.b(b),
.cin(s_out_w),
.sum(d_out),
.cout(cout[0])
);
shift_reg sf2 (
.shift_in(cout[0]),
.clk(clk),
.clr(clr),
.shift_out(cout[1])
);
endmodule
| 6.852735 |
module shift_reg #(
parameter size = 128
) (
shift_in,
clk,
clr,
shift_out
);
// Port Declaration
input shift_in;
input clk;
input clr;
output shift_out;
reg [size:0] shift; // shift register
always @(posedge clk or posedge clr) begin
if (clr) shift = 0;
else shift = {shift[size-1:0], shift_in};
end
assign shift_out = shift[size];
endmodule
| 9.26065 |
module adder_flex (
input rst,
input clk,
input in1,
output out1
);
reg [7:0] cnt;
assign out1 = 1'b1 & cnt[1];
always @(posedge clk, negedge rst) begin
if (!rst) begin
cnt <= 0;
end else if (cnt < 8'hff) cnt <= cnt + 1;
else if (cnt >= 8'hff) cnt <= 0;
else cnt <= cnt;
end
endmodule
| 6.505438 |
module adder_flexible_biterwidth (
clk,
RST,
a,
b,
result
);
parameter WIDTH_A = 8, WIDTH_B = 8;
//Bit width for input
localparam WIDTH_OUT = 1 + ((WIDTH_A > WIDTH_B) ? (WIDTH_A) : (WIDTH_B));
//Bit width for output: maximum between the width + 1 bit for carried bit
input clk, RST;
input [WIDTH_A - 1:0] a;
input [WIDTH_B - 1:0] b;
output [WIDTH_OUT - 1:0] result;
//Load other module(s)
//Definition for Variables in the module
//Logic
assign result = {{(WIDTH_OUT - WIDTH_A) {1'b0}}, a} + {{(WIDTH_OUT - WIDTH_A) {1'b0}}, b};
endmodule
| 9.079318 |
modules
`define WIDTH_1 8
`define WIDTH_2 8
`define WIDTH_12 9
`define WIDTH_3 16
//Bit width definition
module adder_flexible_bitWidth_test;
//defination for Variables
reg clk;
reg reset;
wire[`WIDTH_1 -1:0] a1;
wire[`WIDTH_2 -1:0] a2;
wire[`WIDTH_12 -1:0] b1;
wire[`WIDTH_3 -1:0] b2;
wire[`WIDTH_3 + 1 -1:0] c, c1;
//Connection to the modules
counter_parameter #(.WIDTH(`WIDTH_1),.MAX_VALUE(200))
C1( .clk(clk), .RST(reset),
.counter(a1));
counter_parameter #(.WIDTH(`WIDTH_2),.MAX_VALUE(234))
C2( .clk(clk), .RST(reset),
.counter(a2));
counter_parameter #(.WIDTH(`WIDTH_3),.MAX_VALUE(425))
C3( .clk(clk), .RST(reset),
.counter(b2));
//Generate Operents
adder_flexible_biterwidth
#(.WIDTH_A(`WIDTH_1), .WIDTH_B(`WIDTH_2))
A1( .a(a1),.b(a2),.result(b1) );
adder_flexible_biterwidth
#(.WIDTH_A(`WIDTH_12), .WIDTH_B(`WIDTH_3))
A2( .a(b1),.b(b2),.result(c) );
//Operations
begin
assign c1 = a1 + a2 + b2;
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#10 clk = !clk;
//Reverse the clock in each 10ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
end
endmodule
| 7.377087 |
module Adder_four (
input a0,
input a1,
input b0,
input b1,
output s0,
output s1,
output Carry
);
wire c, cout1, cout2, cout3;
assign {cout1, s0} = a0 + b0;
assign {cout2, c} = cout1 + a1;
assign {cout3, s1} = c + b1;
assign Carry = cout2 + cout3;
endmodule
| 8.295355 |
module Adder_Four_Bit (
A,
B,
Sum,
Reset
);
input [3:0] A, B;
input Reset;
output [4:0] Sum;
wire w1, w2, w3;
Half_Adder f1 (
Sum[0],
w1,
A[0],
B[0],
Reset
);
Full_Adder f2 (
Sum[1],
w2,
A[1],
B[1],
w1,
Reset
);
Full_Adder f3 (
Sum[2],
w3,
A[2],
B[2],
w2,
Reset
);
Full_Adder f4 (
Sum[3],
Sum[4],
A[3],
B[3],
w3,
Reset
);
endmodule
| 7.913367 |
module Adder_Four_Bit_Out (
A,
B,
Sum,
Reset
);
input [3:0] A, B;
input Reset;
output [3:0] Sum;
wire w1, w2, w3;
Half_Adder f1 (
Sum[0],
w1,
A[0],
B[0],
Reset
);
Full_Adder f2 (
Sum[1],
w2,
A[1],
B[1],
w1,
Reset
);
Full_Adder f3 (
Sum[2],
w3,
A[2],
B[2],
w2,
Reset
);
Full_Adder f4 (
Sum[3]
,,
A[3],
B[3],
w3,
Reset
);
endmodule
| 7.913367 |
module: Adder_four
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Adder_four_tb;
// Inputs
reg a0;
reg a1;
reg b0;
reg b1;
// Outputs
wire s0;
wire s1;
wire Carry;
// Instantiate the Unit Under Test (UUT)
Adder_four uut (
.a0(a0),
.a1(a1),
.b0(b0),
.b1(b1),
.s0(s0),
.s1(s1),
.Carry(Carry)
);
initial begin
// Initialize Inputs
a0 = 0;
a1 = 1;
b0 = 1;
b1 = 1;
// Wait 100 ns for global reset to finish
#100;
#100 a0 = 1; a1 = 1; b0 = 1; b1 = 1;
// Add stimulus here
end
endmodule
| 6.709555 |
module: adder_fp32
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module adder_fp32_tb;
// Inputs
reg [31:0] x;
reg [31:0] y;
reg op;
reg clk;
reg rd;
reg reset;
// Outputs
wire [31:0] z;
wire wr;
// Instantiate the Unit Under Test (UUT)
adder_fp32 uut (
.clk(clk),
.reset(reset),
.op(op),
.rd(rd),
.wr(wr),
.z(z),
.x(x),
.y(y)
);
always #10 clk = ~clk;
initial begin
// Initialize Inputs
x = 0;
y = 0;
op = 0;
clk = 0;
rd = 0;
reset = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// 1 + 10 = 11
reset = 0;
rd = 1;
x = 32'b00111111100000000000000000000000;
y = 32'b01000001001000000000000000000000;
#200 rd = 0;
$display("%b + %b = %b", x, y, z, $time);
// 1 - 1E10 = -1E10; no diff
#200 rd = 1;
op = 1;
x = 32'b00111111100000000000000000000000;
y = 32'b01010000000101010000001011111001;
#200 rd = 0;
$display("%b - %b = %b", x, y, z, $time);
// 1 + (-1E10) = (-1E10); no diff
#200 rd = 1;
op = 0;
x = 32'b00111111100000000000000000000000;
y = 32'b11010000000101010000001011111001;
#200 rd = 0;
$display("%b + %b = %b", x, y, z, $time);
// 1 + NaN = NaN
#200 rd = 1;
op = 0;
x = 32'b00111111100000000000000000000000;
y = 32'b01111111111111111011111111000000;
#200 rd = 0;
$display("%b + %b = %b", x, y, z, $time);
// NaN + 1 = NaN
#200 rd = 1;
op = 0;
x = 32'b01111111111111111011111111000000;
y = 32'b00111111100000000000000000000000;
#200 rd = 0;
$display("%b + %b = %b", x, y, z, $time);
// Inf + (-Inf) = NaN
#200 rd = 1;
op = 0;
x = 32'b01111111100000000000000000000000;
y = 32'b11111111100000000000000000000000;
#200 rd = 0;
$display("%b + %b = %b", x, y, z, $time);
// -Inf - (-Inf) == NaN
#200 rd = 1;
op = 1;
x = 32'b11111111100000000000000000000000;
y = 32'b11111111100000000000000000000000;
#200 rd = 0;
$display("%b - %b = %b", x, y, z, $time);
// -Inf + 10 == -Inf
#200 rd = 1;
op = 0;
x = 32'b11111111100000000000000000000000;
y = 32'b01000001001000000000000000000000;
#200 rd = 0;
$display("%b + %b = %b", x, y, z, $time);
// -Inf - (+Inf) == Inf
#200 rd = 1;
op = 1;
x = 32'b01111111100000000000000000000000;
y = 32'b11111111100000000000000000000000;
#200 rd = 0;
$display("%b - %b = %b", x, y, z, $time);
// 10 + (-Inf) == -Inf
#200 rd = 1;
op = 0;
x = 32'b01000001001000000000000000000000;
y = 32'b11111111100000000000000000000000;
#200 rd = 0;
$display("%b + %b = %b", x, y, z, $time);
// Addition of denormals
#200 rd = 1;
op = 0;
x = 32'b00000000001010000100000100000000;
y = 32'b00000000000100000100000100000001;
#200 rd = 0;
$display("%b + %b = %b", x, y, z, $time);
// Subtraction of denormals
#200 rd = 1;
op = 1;
x = 32'b00000000001110000100000100000001;
y = 32'b00000000000100000100000100000001;
#200 rd = 0;
$display("%b - %b = %b", x, y, z, $time);
end
endmodule
| 7.125541 |
module adder_full_1bit (
proC,
sum,
add,
aug,
preC
);
input add, aug, preC;
output proC, sum;
assign proC = aug & preC | add & preC | add & aug;
assign sum = ~add & ~aug & preC | ~add & aug & ~preC | add & ~aug & ~preC | add & aug & preC;
endmodule
| 7.179069 |
module adder_full_1bit_tb;
reg add, aug, preC;
wire proC, sum;
//D.U.T. instantiation
adder_full_1bit adder (
proC,
sum,
add,
aug,
preC
);
/*時脈初始化
always
begin
#`CLOCK_FREQ Clk = !Clk;
end
*/
initial begin
//初始化
$dumpfile("Simulation/adder_full_1bit_tb.vcd");
$dumpvars;
$monitor($time, " add=%b + aug=%b + preC=%b = proC=%b + sum=%b", add, aug, preC, proC, sum);
//模擬
add = 0;
aug = 0;
preC = 0;
#10 preC = 1;
#10 aug = 1;
preC = 0;
#10 preC = 1;
#10 add = 1;
aug = 0;
preC = 0;
#10 preC = 1;
#10 aug = 1;
preC = 0;
#10 preC = 1;
#10 $finish;
end
endmodule
| 7.179069 |
module adder_full_4bit (
proC,
sum,
add,
aug,
preC
);
input [3:0] add, aug;
input preC;
output proC;
output [3:0] sum;
wire c3, c2, c1;
adder_full_1bit
fa0 (
c1,
sum[0],
add[0],
aug[0],
preC
),
fa1 (
c2,
sum[1],
add[1],
aug[1],
c1
),
fa2 (
c3,
sum[2],
add[2],
aug[2],
c2
),
fa3 (
proC,
sum[3],
add[3],
aug[3],
c3
);
endmodule
| 7.570751 |
module adder_full_4bit_tb;
reg [3:0] add, aug;
reg preC;
wire proC;
wire [3:0] sum;
//D.U.T. instantiation
adder_full_4bit adder (
proC,
sum,
add,
aug,
preC
);
initial begin
//初始化
$dumpfile("Simulation/adder_full_4bit_tb.vcd");
$dumpvars;
$monitor($time, " add=%4b + aug=%4b + preC=%b = proC=%b + sum=%4b", add, aug, preC, proC, sum);
//模擬
add = 4'b0000;
aug = 4'b0000;
preC = 0;
#10 preC = 1;
#10 add = 4'b0101;
aug = 4'b1010;
preC = 1;
#10 $finish;
end
endmodule
| 7.570751 |
module adder_full_8bit (
proC,
sum,
add,
aug,
preC
);
input [7:0] add;
input [7:0] aug;
input preC;
output proC;
output [7:0] sum;
wire [7:1] c;
adder_full_1bit
fa0 (
c[1],
sum[0],
add[0],
aug[0],
preC
),
fa1 (
c[2],
sum[1],
add[1],
aug[1],
c[1]
),
fa2 (
c[3],
sum[2],
add[2],
aug[2],
c[2]
),
fa3 (
c[4],
sum[3],
add[3],
aug[3],
c[3]
),
fa4 (
c[5],
sum[4],
add[4],
aug[4],
c[4]
),
fa5 (
c[6],
sum[5],
add[5],
aug[5],
c[5]
),
fa6 (
c[7],
sum[6],
add[6],
aug[6],
c[6]
),
fa7 (
proC,
sum[7],
add[7],
aug[7],
c[7]
);
endmodule
| 7.530642 |
module adder_full_8bit_tb;
reg [7:0] add, aug;
reg preC;
wire proC;
wire [7:0] sum;
//D.U.T. instantiation
adder_full_8bit adder (
proC,
sum,
add,
aug,
preC
);
initial begin
//初始化
$dumpfile("Simulation/adder_full_8bit_tb.vcd");
$dumpvars;
$monitor($time, " add=%8b + aug=%8b + preC=%b = proC=%b + sum=%8b", add, aug, preC, proC, sum);
//模擬
add = 8'b00000000;
aug = 8'b00000000;
preC = 0;
#10 preC = 1;
#10 add = 8'b01010101;
aug = 8'b10101010;
preC = 1;
#10 $finish;
end
endmodule
| 7.530642 |
module ks_adder_gate_8 (
x,
y,
carry,
out
);
input [7:0] x, y;
output carry;
output [7:0] out;
wire [7:0] p, g, c, s0;
half_adder_pg ha0 (
x[0],
y[0],
out[0],
g[0]
);
half_adder_pg ha1 (
x[1],
y[1],
p[1],
g[1]
);
half_adder_pg ha2 (
x[2],
y[2],
p[2],
g[2]
);
half_adder_pg ha3 (
x[3],
y[3],
p[3],
g[3]
);
half_adder_pg ha4 (
x[4],
y[4],
p[4],
g[4]
);
half_adder_pg ha5 (
x[5],
y[5],
p[5],
g[5]
);
half_adder_pg ha6 (
x[6],
y[6],
p[6],
g[6]
);
half_adder_pg ha7 (
x[7],
y[7],
p[7],
g[7]
);
ks_parallel_prefix_logic_8 ksppl0 (
g,
p,
{carry, c}
);
xor #`ADDER_GATE_DELAY xor1 (out[1], p[1], c[1]);
xor #`ADDER_GATE_DELAY xor2 (out[2], p[2], c[2]);
xor #`ADDER_GATE_DELAY xor3 (out[3], p[3], c[3]);
xor #`ADDER_GATE_DELAY xor4 (out[4], p[4], c[4]);
xor #`ADDER_GATE_DELAY xor5 (out[5], p[5], c[5]);
xor #`ADDER_GATE_DELAY xor6 (out[6], p[6], c[6]);
xor #`ADDER_GATE_DELAY xor7 (out[7], p[7], c[7]);
endmodule
| 6.742585 |
module adder_gate (
x,
y,
carry,
out
);
input [7:0] x, y;
output carry;
output [7:0] out;
full_adder fa0 (
x[0],
y[0],
1'b0,
out[0],
c0
);
full_adder fa1 (
x[1],
y[1],
c0,
out[1],
c1
);
full_adder fa2 (
x[2],
y[2],
c1,
out[2],
c2
);
full_adder fa3 (
x[3],
y[3],
c2,
out[3],
c3
);
full_adder fa4 (
x[4],
y[4],
c3,
out[4],
c4
);
full_adder fa5 (
x[5],
y[5],
c4,
out[5],
c5
);
full_adder fa6 (
x[6],
y[6],
c5,
out[6],
c6
);
full_adder fa7 (
x[7],
y[7],
c6,
out[7],
carry
);
endmodule
| 7.321758 |
module half_adder_pg (
x,
y,
p,
g
);
input x, y;
output p, g;
xor #`ADDER_GATE_DELAY xor0 (p, x, y);
and #`ADDER_GATE_DELAY and0 (g, x, y);
endmodule
| 6.552584 |
module adder_gate_tb;
reg input1;
reg input2;
reg carryin;
wire out;
wire carryout;
adder_gate uut (
.x(input1),
.y(input2),
.cin(carryin),
.res(res),
.cout(carryout)
);
initial begin
$dumpfile("adder.vcd");
$dumpvars(0, adder_gate_tb);
input1 = 0;
input2 = 0;
carryin = 0;
#20 input1 = 1;
#20;
input2 = 1;
#20;
input1 = 0;
#20;
carryin = 1;
#20;
input2 = 0;
#20;
input1 = 1;
#20;
input2 = 1;
#40;
end
initial begin
$monitor("time = %2d, CIN =%1b, IN1=%1b, IN2=%1b, COUT=%1b, OUT_A=%1b", $time, carryin, input2,
input1, carryout, res);
end
endmodule
| 7.510645 |
module adder_gate_test;
parameter pattern_num = 13;
wire [7:0] out;
wire carry;
reg [7:0] x, y;
reg clk;
reg stop;
integer i, num, error;
reg [8:0] ans_out;
reg [8:0] adder_out;
reg [7:0] data_base1[0:100];
reg [8:0] data_base2[0:100];
ks_adder_gate_8 A (
x,
y,
carry,
out
);
// carry_lookahead_adder_gate_8 A (x, y, carry, out);
// adder_gate A (x, y, carry, out);
initial begin
$readmemh(`INFILE, data_base1);
$readmemh(`OUTFILE, data_base2);
clk = 1'b1;
error = 0;
stop = 0;
i = 0;
end
always begin
#(`CYCLE * 0.5) clk = ~clk;
end
initial begin
x[7:0] = data_base1[0];
y[7:0] = data_base1[1];
for (num = 2; num < (pattern_num * 2); num = num + 2) begin
@(posedge clk) begin
x[7:0] = data_base1[num];
y[7:0] = data_base1[num+1];
end
end
end
always @(posedge clk) begin
i <= i + 1;
if (i >= pattern_num) stop <= 1;
end
always @(posedge clk) begin
adder_out <= {carry, out};
ans_out <= data_base2[i];
if (adder_out !== ans_out) begin
error <= error + 1;
$display("An ERROR occurs at no.%d pattern: {carry out, output} %h != answer %h.\n", i,
adder_out, ans_out);
end
end
initial begin
@(posedge stop) begin
if (error == 0) begin
$display("==========================================\n");
$display("====== Congratulation! You Pass! =======\n");
$display("==========================================\n");
end else begin
$display("===============================\n");
$display("There are %d errors.", error);
$display("===============================\n");
end
$finish;
end
end
/*================Dumping Waveform files====================*/
initial begin
$dumpfile("adder.vcd");
$dumpvars;
/* $fsdbDumpfile("adder.fsdb");
$fsdbDumpvars; */
end
endmodule
| 7.355073 |
module adder_h (
sum,
cout,
a,
b
);
input a, b;
output sum, cout;
assign sum = a ^ b;
assign cout = a & b;
endmodule
| 7.873975 |
module adder_half (
x,
y,
sum,
carry
);
input x, y;
output sum, carry;
//* Data-flow modelling
assign carry = x & y;
assign sum = x ^ y; // `^` is xor operation
endmodule
| 7.444731 |
module testbenchforhalfadder;
reg x, y;
wire sum, carry;
adder_half h1 (
x,
y,
sum,
carry
); // we are creating an object h1 using `adder_half` module.
/*
As we change `x` and `y` during run-time of the program, the values of `sum` and `carry` will also change according to the logic implemented in the `adder_half` module, since those positional parameters are declared as `output`s in the `adder_half` module.
This can be viewed by adding `sum` and `carry` in the visualizer panel in any software.
*/
//* Behavioral Modelling
initial begin
// change default runtime from Simulate --> Runtime options
// #100 means perform the operation after 100 ps.
// 1'b0 is register 0 , 1'b1 is register 1
#20 x = 1'b0;
y = 1'b0;
#20 x = 1'b0;
y = 1'b1;
#20 x = 1'b1;
y = 1'b0;
#20 x = 1'b1;
y = 1'b1;
#20 $finish;
end
endmodule
| 7.057029 |
module adder_half_1bit (
carry,
sum,
input_a,
input_b
);
//port 類型宣告
output carry, sum;
input input_a, input_b;
xor gate_sum (sum, input_a, input_b);
and gate_carry (carry, input_a, input_b);
endmodule
| 7.43267 |
module adder_half_1bit_testbench ();
//宣告port類型
reg input_a, input_b;
wire output_carry, output_sum;
//D.U.T. instantiation
adder_half_1bit dut (
output_carry,
output_sum,
input_a,
input_b
);
/* 時脈產生器
always begin
#`CLOCK_PERIOD_HALF Clk = !Clk;
end
*/
initial begin
//初始化
$dumpfile("Simulation/adder_half_1bit_testbench.vcd");
$dumpvars;
$display("\t\t時間\tcarry\tsum\tb\ta");
$monitor("%d\t%b\t%b\t%b\t%b", $time, output_carry, output_sum, input_a, input_b);
//模擬
// 0, 0
input_a = 0;
input_b = 0;
#10 //0, 1
input_a = 1;
#10 //1, 0
input_a = 0;
input_b = 1;
#10 //1, 1
input_a = 1;
#10 $finish;
end
endmodule
| 7.43267 |
module adder_hier (
result, // Output of the adder
carry, // Carry output of adder
r1, // first input
r2, // second input
ci // carry input
);
// Input Port Declarations
input [3:0] r1;
input [3:0] r2;
input ci;
// Output Port Declarations
output [3:0] result;
output carry;
// Port Wires
wire [3:0] r1;
wire [3:0] r2;
wire ci;
wire [3:0] result;
wire carry;
// Internal variables
wire c1;
wire c2;
wire c3;
// Code Starts Here
addbit u0 (
r1[0],
r2[0],
ci,
result[0],
c1
);
addbit u1 (
r1[1],
r2[1],
c1,
result[1],
c2
);
addbit u2 (
r1[2],
r2[2],
c2,
result[2],
c3
);
addbit u3 (
r1[3],
r2[3],
c3,
result[3],
carry
);
endmodule
| 8.160914 |
module tb ();
reg [3:0] r1, r2;
reg ci;
wire [3:0] result;
wire carry;
// Drive the inputs
initial begin
r1 = 0;
r2 = 0;
ci = 0;
#10 r1 = 10;
#10 r2 = 2;
#10 ci = 1;
#10 $display("+--------------------------------------------------------+");
$finish;
end
// Connect the lower module
adder_hier U (
result,
carry,
r1,
r2,
ci
);
// Hier demo here
initial begin
$display("+--------------------------------------------------------+");
$display("| r1 | r2 | ci | u0.sum | u1.sum | u2.sum | u3.sum |");
$display("+--------------------------------------------------------+");
$monitor("| %h | %h | %h | %h | %h | %h | %h |", r1, r2, ci,
tb.U.u0.sum, tb.U.u1.sum, tb.U.u2.sum, tb.U.u3.sum);
end
endmodule
| 7.195167 |
module adder_hold_register (
clk,
enable_adl,
enable_sb06,
enable_sb7,
data_in,
adl,
sb,
adder_hold_reg
);
input clk; //clk_2
input enable_adl; //net: 1015; aka add_adl
input enable_sb06; //net: 129; aka add_sb06
input enable_sb7; //net: 214; aka add_sb17
input [7:0] data_in; //data from alu
output [7:0] adl; //address data low bus
output [7:0] sb; //special bus
output reg [7:0] adder_hold_reg; //output to decimal adjust adders
assign adl = (enable_adl) ? adder_hold_reg : 8'bz;
assign sb[7] = (enable_sb7) ? adder_hold_reg[7] : 1'bz;
assign sb[6:0] = (enable_sb06) ? adder_hold_reg[6:0] : 7'bz;
always @(clk or data_in) begin
if (clk)
adder_hold_reg <= ~data_in; //alu outputs are opposite value of true result so we invert here
end
endmodule
| 7.384802 |
module adder_implicit (
result, // Output of the adder
carry, // Carry output of adder
r1, // first input
r2, // second input
ci // carry input
);
// Input Port Declarations
input [3:0] r1;
input [3:0] r2;
input ci;
// Output Port Declarations
output [3:0] result;
output carry;
// Port Wires
wire [3:0] r1;
wire [3:0] r2;
wire ci;
wire [3:0] result;
wire carry;
// Internal variables
wire c1;
wire c2;
wire c3;
// Code Starts Here
addbit u0 (
r1[0],
r2[0],
ci,
result[0],
c1
);
addbit u1 (
r1[1],
r2[1],
c1,
result[1],
c2
);
addbit u2 (
r1[2],
r2[2],
c2,
result[2],
c3
);
addbit u3 (
r1[3],
r2[3],
c3,
result[3],
carry
);
endmodule
| 7.732806 |
module adder_internal (
input [7:0] a,
input [2:0] b,
output [7:0] y
);
assign y = a + ({{5{2'b0}}, b});
endmodule
| 7.843775 |
module adder_layer #(
parameter ADDER_NUM = 4,
parameter ADDER_WIDTH = 8
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input [ADDER_NUM * ADDER_WIDTH * 2 - 1:0] adder_din,
output [ADDER_NUM * (ADDER_WIDTH + 1) - 1:0] adder_dout
);
genvar i;
generate
for (i = 0; i < ADDER_NUM; i = i + 1) begin : adder_layer_gen
wire [ADDER_WIDTH - 1:0] add1 = adder_din[2*i*ADDER_WIDTH+:ADDER_WIDTH];
wire [ADDER_WIDTH - 1:0] add2 = adder_din[(2*i+1)*ADDER_WIDTH+:ADDER_WIDTH];
wire [ADDER_WIDTH:0] sum = add1 + add2;
reg [ADDER_WIDTH:0] sum_reg;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
sum_reg <= 'b0;
end else begin
sum_reg <= sum;
end
end
assign adder_dout[i*(ADDER_WIDTH+1)+:ADDER_WIDTH+1] = sum_reg;
end
endgenerate
endmodule
| 7.382159 |
module fulladder (
s,
cout,
a,
b,
cin
);
output s, cout;
input a, b, cin;
wire partial_s, partial_c1, partial_c2;
halfadder ha0 (
partial_s,
partial_c1,
a,
b
);
halfadder ha1 (
s,
partial_c2,
partial_s,
cin
);
or o1 (cout, partial_c1, partial_c2);
endmodule
| 7.454465 |
module adder (
s,
co,
a,
b,
ci
);
output s, co; //Outputs of Sum and Carry Out
input a, b, ci; //Inputs of A, b and Carry In
wire o0, o1, o2; //Internal wiring
xor (s, a, b, ci); //Calculation of Sum
or (o0, a, b); //Calculation of Carry Out
or (o1, b, ci);
or (o2, ci, a);
and (co, o0, o1, o2);
endmodule
| 7.276647 |
module adder7 (
s,
co,
a,
b,
ci
);
output [6:0] s; //7-bit Sum output
output co; //Output bit of Carry out
input [6:0] a, b; //7-bit Input A and B
input ci; //Input bit of Carry in
wire c1, c2, c3, c4, c5, c6;
adder a0 (
s[0],
c1,
a[0],
b[0],
ci
);
adder a1 (
s[1],
c2,
a[1],
b[1],
c1
);
adder a2 (
s[2],
c3,
a[2],
b[2],
c2
);
adder a3 (
s[3],
c4,
a[3],
b[3],
c3
);
adder a4 (
s[4],
c5,
a[4],
b[4],
c4
);
adder a5 (
s[5],
c6,
a[5],
b[5],
c5
);
adder a6 (
s[6],
co,
a[6],
b[6],
c6
);
endmodule
| 7.475421 |
module adder3_2 (
s,
co,
a,
b,
c
);
output [6:0] s,co; //7-bit Sum output and 7-bit carry in where co[0] = 0 (Carry In will be added in later)
input [6:0] a, b, c; //7-bit Input A and B
wire c1; //the last carry bit is not used so assign to bogus entiry
assign co[0] = 0; //assingment of co[0] to 0, this causes the Carry vector to be shifted over to left by 1
adder a0 (
s[0],
co[1],
a[0],
b[0],
c[0]
);
adder a1 (
s[1],
co[2],
a[1],
b[1],
c[1]
);
adder a2 (
s[2],
co[3],
a[2],
b[2],
c[2]
);
adder a3 (
s[3],
co[4],
a[3],
b[3],
c[3]
);
adder a4 (
s[4],
co[5],
a[4],
b[4],
c[4]
);
adder a5 (
s[5],
co[6],
a[5],
b[5],
c[5]
);
adder a6 (
s[6],
c1,
a[6],
b[6],
c[6]
);
endmodule
| 7.235552 |
module adder_lin (
s,
co,
a,
b,
c,
d,
e,
f,
g,
h,
ci
);
output [6:0] s;
output co;
input [6:0] a, b, c, d, e, f, g, h;
input ci;
wire [6:0] s1, s2, s3, s4, s5, s6;
wire [6:0] co1, co2, co3, co4, co5, co6;
//3:2 adders in linear fashion
adder3_2 a0 (
s1,
co1,
a,
b,
c
);
adder3_2 a1 (
s2,
co2,
s1,
co1,
d
);
adder3_2 a2 (
s3,
co3,
s2,
co2,
e
);
adder3_2 a3 (
s4,
co4,
s3,
co3,
f
);
adder3_2 a4 (
s5,
co5,
s4,
co4,
g
);
adder3_2 a5 (
s6,
co6,
s5,
co5,
h
);
adder7 a6 (
s,
co,
s6,
co6,
ci
); //normal FA implementation, adds in ci
endmodule
| 7.782114 |
modules
module adder_line_generate_test;
//defination for Variables
reg clk;
reg reset;
wire[7:0] d1;
wire[11:0] d2;
wire[4:0] sum1, s1;
wire[6:0] sum2, s2;
//Connection to the modules
counter_parameter #(.WIDTH(8),.MAX_VALUE(2**8 - 1))
C1 ( .clk(clk), .RST(reset), .counter(d1) );
counter_parameter #(.WIDTH(12),.MAX_VALUE(2**12 - 1))
C2 ( .clk(clk), .RST(reset), .counter(d2) );
//Input generate
top_adder_line_generate T1(.a10(d1[3:0]), .a11(d1[7:4]), .sum1(sum1),
.a20(d2[5:0]), .a21(d2[11:6]), .sum2(sum2) );
begin
assign s1 = d1[3:0] + d1[7:4];
assign s2 = d2[5:0] + d2[11:6];
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#10 clk = !clk;
//Reverse the clock in each 10ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
end
endmodule
| 6.885623 |
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