code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module AddressMapping (
input [31:0] ALU_result,
output [ 5:0] address
);
wire [31:0] address_base;
assign address_base = (ALU_result - 1024);
// sram check for [7:1]
assign address = address_base[7:2];
endmodule
| 7.394252 |
module addressRAM (
input [4:0] step,
output reg re_RAM,
output reg [12:0] firstaddr,
lastaddr
);
parameter picture_size = 0;
parameter convolution_size = 0;
parameter picture_storage_limit = picture_size * picture_size;
parameter convweight = picture_storage_limit + (1*4 + 4*4 + 4*8 + 8*8) * c... | 7.695746 |
module addressRegister (
addrOut,
addrIn,
enable
);
output reg [15:0] addrOut;
input wire [15:0] addrIn;
input wire enable;
always @(enable) begin
if (!enable) begin
addrOut = addrIn;
end
end
endmodule
| 6.628698 |
module AddressRegisterFile #(
parameter reg_width = 32
) (
input CLK,
input [2:0] REG_SEL,
input SUPERVISOR_MODE,
input S,
input [reg_width-1:0] D,
output [reg_width-1:0] Q
);
wire [7:0] en;
wire [7:0] en_gnd;
Decoder #(3) reg_sel (
REG_SEL,
en
);
assign en_gnd = 8'b0... | 7.466366 |
module addrRegMux (
initAddr,
incrAddr,
selStartAddr,
addrCountOut,
shiftRegOut,
adderAddr
);
output reg [15:0] initAddr;
input wire [15:0] addrCountOut, adderAddr, shiftRegOut;
input wire selStartAddr, incrAddr;
initial begin
incrAddr = 0;
selStartAddr = 0;
end
always @(i... | 6.79522 |
module AddressStack #(
parameter N2 = 8,
parameter S = 32,
parameter S2 = 5
) (
input clk,
input reset,
input call_ah_as,
input retn_ah_as,
input cnt_inc_ah_as,
input [N2-1:0] funcNum_ah_as,
output reg call_as_cb,
output reg retn_as_cb,
output reg cnt_inc_as_cb,
ou... | 6.74131 |
module AddressWindow (
Address,
Base,
Head,
Valid,
Offset
);
input [15:0] Address, Base, Head;
output Valid;
output [15:0] Offset;
wor baseValid;
wire headValid;
AlteraCompareUnsigned compareBase (
.dataa(Address),
.datab(Base),
.aeb (baseValid),
.agb (baseV... | 7.305518 |
module address_adder_test;
reg [1:0] ADDR1_SEL;
reg [2:0] ADDR2_SEL;
reg LSHFT;
reg signed [15:0] IR;
reg [15:0] PC;
reg [15:0] SR1;
wire [15:0] OUT;
ADDRESS_ADDER test_address_adder (
ADDR1_SEL,
ADDR2_SEL,
LSHFT,
IR,
PC,
SR1,
OUT
);
initial begin
// C... | 6.742658 |
module address_counter (
input clk,
input reset,
input set_valid,
input [7:0] set_value,
output rd,
output [7:0] address
);
reg [1:0] tact;
reg tact_flag;
reg [7:0] current_address;
always @(posedge clk) begin
if (reset) tact <= 3'b000;
else ta... | 6.631086 |
module address_decode (
input [15:0] cpu_a,
input [ 3:0] romsel,
output ddr_enable,
// Memory enables
output ram_enable,
// 0x0000
output rom_enable,
// 0x8000 (BASIC/sideways ROMs)
output mos_enable,
// 0xC000
// IO region enables
output io_fred,
// 0xFC00 (... | 7.247981 |
module Address_Decoder_tb;
reg clk;
reg [31:0] Address;
reg write_enable;
wire out_WE1, out_WE2, out_WEM;
wire [1:0] Read_Data_Sel;
Address_Decoder DUT (
.A(Address),
.WE(write_enable),
.WE1(out_WE1),
.WE2(out_WE2),
.WEM(out_WEM),
.RdSel(Read_Data_Sel)
);
reg [31:... | 6.64906 |
module address_decode_mpu (
input wire clk,
input wire vma,
input wire e_rom,
input wire screen_control,
input wire [15:0] addr,
input wire r_w_n,
output wire [13:0] ram_addr,
output wire [ 1:0] ram_lane_sel,
output wire racnt,
outp... | 7.247981 |
module name - address_dispatch
// Version: V3.4.0.20220301
// Created:
// by - fenglin
////////////////////////////////////////////////////////////////////////////
// Description:
// - encapsulate ARP request frame、PTP frame、NMAC report frame to tsmp frame;
//////////////////////////////////////////////... | 7.871214 |
module address_display (
input wire [8:0] address_line,
input wire clk,
input wire reset,
output reg [7:0] sseg_indicator,
output reg [3:0] digits
);
reg [31:0] counter;
reg [11:0] tubes_bcd_values;
reg [ 2:0] digit_counter;
always @(posedge clk) begin
if (~reset) begin
counter <... | 6.599651 |
module: address_display
//
// Dependencies:
//
// Revision:
// Revision 1.0
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module address_display_testbench;
// Inputs
reg [8:0] address_line;
reg clk;
reg reset;
// Outputs
wire [7:... | 7.2938 |
module address_gen (
iRST_N,
iCLK,
oADDRESS,
iEND_ADDRESS
);
parameter WIDE = 23;
input iRST_N, iCLK;
output [WIDE-1:0] oADDRESS;
//parameter END_ADDRESS = 20'hFFFFF;
input [WIDE -1 : 0] iEND_ADDRESS;
reg [WIDE-1:0] addr_cnt;
assign oADDRESS = addr_cnt;
////////// ADDRESS Generator... | 6.808832 |
module is_op1_reg (
out,
op1,
mod_rm
);
output out;
input [2:0] op1;
input [7:0] mod_rm;
// reg if op1 == 1 or (op1 == 4 and mod == 11)
wire [1:0] mod = mod_rm[7:6];
wire op1_is_1;
compare #(
.WIDTH(3)
) op1_cmp (
op1,
3'd1,
op1_is_1
);
wire mod_rm_reg;
co... | 7.089995 |
module address_uart_generator (
s_tick,
address_uart,
recieving,
recieve_over,
recieve_start,
transmit_begin,
transmit_active,
transmit_over,
finish,
write_en_uart,
start_calculation,
uart_en
);
input s_tick;
output reg [19:0] address_uart = 20'd0;
input recieving, ... | 6.997047 |
module CLOCK_DIVIDER (
clk_IN,
clk
); // clock divider for top design
input clk_IN;
reg [7:0] counter = 8'd0;
output reg clk = 1'd0;
always @(posedge clk_IN) begin
if (counter==8'd9) // generate 1mhz frequency from 50mhz internal oscillator
begin
counter = 8'd0;
clk = ~clk;
en... | 7.080154 |
module address_gererate_tb;
reg [6:0] rd_data_add;
reg [6:0] r_lay_cnt;
reg [5:0] bf_cnt;
reg [2:0] lay_cnt;
reg [5:0] rom_wn;
reg clk;
initial clk = 0;
always #20 clk = ~clk;
initial begin
r_lay_cnt = 1;
forever begin
#2560;
r_lay_cnt = 6'd1 << lay_cnt + 1;
end
end
in... | 6.993316 |
module address_jump (
PC,
INST,
O
);
input [31:0] PC, INST;
output [31:0] O;
buf buf_1 (
O[31], PC[31]
), buf_2 (
O[30], PC[30]
), buf_3 (
O[29], PC[29]
), buf_4 (
O[28], PC[28]
), buf_4_2 (
O[27], PC[27]
), buf_4_3 (
O[26], PC[26]
), buf_5 (
O[2... | 6.949518 |
module address_jump_testbench ();
reg [31:0] pc, inst;
wire [31:0] o;
address_jump test (
pc,
inst,
o
);
initial begin
pc = 32'b1110_0000_0000_0000_0000_0000_0000_0000;
inst = 32'b0000_0011_1111_1111_1111_1111_1111_1111;
#`DELAY;
pc = 32'b1010_0000_0000_0000_0000_000... | 7.473832 |
module address_map (
input wire [ 1:0] sel_in,
input wire [18:0] col_index_in,
input wire [18:0] row_index_in,
output wire [18:0] address_out
);
localparam array_wid = 19'd320;
localparam array_hgt = 19'd240;
localparam LEFT_IMAGE = 19'd10, RIGHT_IMAGE = 19'd174763, DISP_IMAGE = 19'd349525;
... | 7.119441 |
module Address_Mapping (
input [31:0] in,
output [31:0] out
);
assign out = in - 32'b00000000000000000000010000000000;
endmodule
| 9.084946 |
module address_map_tb;
reg [ 3:0] NODEADDRESS;
reg [31:0] MEMADDRESS;
wire [31:0] ADDRESS;
address_map my_address_map (
NODEADDRESS,
MEMADDRESS,
ADDRESS
);
initial begin
// ------- ADDRESS MAP Test 01 : Address generation for node (0, 0) ----------
NODEADDRESS = 4'b0000;
M... | 6.765859 |
module address_multiplexer (
input fetch,
input [12:0] ir_addr,
input [12:0] pc_addr,
output [12:0] addr
);
assign addr = fetch ? pc_addr : ir_addr;
endmodule
| 7.710017 |
module Addr_MUX (
CLK,
RST,
HADDR,
HADDR_1,
HADDR_2,
SEL
);
input [1:0] SEL;
input RST, CLK;
input [15:0] HADDR_1, HADDR_2;
output reg [15:0] HADDR;
always @(posedge CLK or posedge RST) begin
if(SEL == 2'b01 && RST != 1) // Master 1 selected
begin
HADDR = HADDR_1;
en... | 7.830388 |
module address_request_decoder (
input wire [9:0] address,
input wire ale,
input wire aen,
input wire ior, // = g_rd
input wire iow, // = p_wr
input wire interrupt_req, // = v_rp
input wire zk4,
output wire sel,
output wire sel1,
output wire [1:0] internal_address,
ou... | 6.614643 |
module address_request_decoder_testbench ();
reg [ 9:0] address;
reg ale;
reg aen;
reg ior; // = g_rd
reg iow; // = p_wr
reg interrupt_req; // = v_rp
reg zk4;
wire sel;
wire sel1;
wire [ 1:0] internal_address;
wire interrupt... | 6.614643 |
module address_resolver (
input [1:0] mapping,
input [5:0] addri,
output reg [5:0] addro
);
localparam DECODE_TRUE = 2'd0, ENCODE_TRUE = 2'd1, STANDARD = 2'd2;
always @(*) begin
case (mapping)
DECODE_TRUE: begin
addro = {addri[3], addri[2], addri[1], addri[0], addri[5], add... | 7.238851 |
module Address_Selector (
ADD,
Q,
RAM_S
);
input [15:0] ADD;
output reg [16:0] Q;
output reg RAM_S;
always @(ADD) begin
if (ADD[15:0] < 17) begin
RAM_S <= 1'b0;
end else begin
RAM_S <= 1'b1;
end
case (ADD[15:0])
16'h0000: Q <= 17'b00000000000000001;
16'h0001... | 7.525099 |
module Address_setter #(
parameter ADDR_WIDTH = 5,
parameter SHIFT_CONTROL = 2
) (
input single_clk,
input [(SHIFT_CONTROL-1):0] change_shift,
output write_shift_enabler,
read_shift_enabler
);
reg read_shift, write_shift;
always @(posedge single_clk) begin
// changes write_shift
if... | 7.205516 |
modules together in the form, allowing to use them in the single-cycle MIPS processor.
// Author: github.com/vsilchuk
module address_space(i_clk, i_we, i_arst, i_address, i_write_data, o_read_data, io_IO, bam_output);
input i_clk; // Input clock signal, 50MHz system clock on Altera DE2 FPGA board, for example
... | 8.112044 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module address_x (
clk,
rst_n,
enable,
wren,
rden,
address_w,
address_r,
address
);
input clk, rst_n, enable;
input [6:0] address;
output wren, rden;
output [6:0] address_w;
output [6:0] address_r;
reg wren, rden;
reg preenable;
reg [6:0] address_w;
reg [6:0] address_wr... | 6.783092 |
module outputs the "zig-zag" index. For instance, the
* pixel at location (row = 2, col = 3) is index 19 in row-major indexing and is index 17 in the
* zig-zag order
*/
module row_major_to_zig_zag(input [5:0] row_major_index,
output reg [5:0] zig_zag_index);
// I'm sure there's a smar... | 7.147491 |
module Address_controller (
input rx_done,
tx_done,
Pro_over,
input [7:0] RxD,
input Pro_wea,
input [7:0] Pro_Dout,
input [17:0] ProAddress,
output reg [17:0] MemAddress,
output reg [7:0] MemData,
output reg Pro_rst,
output reg wea,
output reg Tx_start,
output reg Rx_... | 6.915489 |
module ADDRgen #(
parameter R = 5,
parameter N = 32
) (
input i_clk,
input i_rst,
input i_en,
output reg o_sel_wing,
output reg [R-2:0] o_a0, //m0 bank address
output reg [R-2:0] o_a1 //m1 bank address
);
// parameter, reg, wire
localparam s_0 = 2'b00; // IDLE
localparam s_1 = ... | 8.268888 |
module barrel_shifter (
input s,
output w1,
w0
);
assign w1 = s ? 1'b1 : 1'b0;
assign w0 = s ? 1'b0 : 1'b1;
endmodule
| 8.606549 |
module bwMUX (
input in1,
input in2,
input sel,
output out
);
assign out = sel ? in1 : in2;
endmodule
| 8.991236 |
module Addr_MEM (
input wire clk,
bubbleM,
flushM,
input wire [4:0] reg_dest_EX,
output reg [4:0] reg_dest_MEM
);
initial reg_dest_MEM = 0;
always @(posedge clk)
if (!bubbleM) begin
if (flushM) reg_dest_MEM <= 0;
else reg_dest_MEM <= reg_dest_EX;
end
endmodule
| 7.246075 |
module addrmodule (
din,
muxin,
clk,
ena,
ageb,
muxout,
ab
);
//function: sorts the addresses accoring to the values of the counts
parameter DATA_WIDTH = 16; // size of each input data
parameter TOTAL_SYMBOLS = 10; // total number of symbols to be initialized
parameter ADDR_WIDTH ... | 7.120711 |
module AddrMux (
input CLK_FETCH,
input [12:0] ADDR_PC,
input [12:0] ADDR_IR,
output [12:0] ADDR
);
assign ADDR = (CLK_FETCH) ? ADDR_PC : ADDR_IR;
endmodule
| 6.717531 |
module addrndkey (
input wire [127:0] state_in,
input wire [127:0] key,
output wire [127:0] state_out
);
assign state_out = state_in ^ key;
endmodule
| 8.270668 |
module addroundkeytestbench (
input begintest,
output reg endtest,
output reg dutpassed,
output reg [7:0] shiftrowsout[3:0][3:0],
output reg [7:0] roundkey[3:0][3:0],
input [7:0] addroundkeyout[3:0][3:0]
);
always @(begintest) begin
endtest = 0;
dutpassed = 1;
shiftrowsout[3][3]... | 7.114493 |
module AddRoundKey (
input Rst,
input Clk,
input En_ARK,
output reg Ry_ARK,
input [127:0] In_ARK,
output reg [127:0] Out_ARK,
input [127:0] Key_ARK
);
integer i;
always @(posedge Clk) begin
if (Rst) begin
Ry_ARK = 0;
Out_ARK = 0;
end else if (En_ARK) begin
for... | 7.103156 |
module AddRoundKey_tb ();
reg [127:0] state_in;
reg [127:0] key_in;
wire [127:0] state_out;
AddRoundKey dut (
state_in,
key_in,
state_out
);
initial begin
$dumpfile("AddRoundKey.vcd");
$dumpvars(0, AddRoundKey_tb);
state_in = 128'h3243f6a8885a308d313198a2e0370734;
key... | 6.821768 |
module addrselect (
input [2:0] addr, // The set address
input [2:0] aBus, // Adress from buss
output enable // Enabled?
);
assign enable = (aBus == ~addr) ? 1 : 0;
endmodule
| 8.170566 |
module addrunit (
input wire clk_in,
input wire rst_in,
input wire rdy_in,
//from reservation station
input wire [`IDWidth - 1 : 0] rs_addrunit_a_in,
input wire [`IDWidth - 1 : 0] rs_addrunit_vj_in,
input wire [`ROBWidth - 1 : 0] rs_addrunit_dest_in,
input wire [`InstTypeWidth - 1 : 0] ... | 7.228716 |
module Addr_WB (
input wire clk,
bubbleW,
flushW,
input wire [4:0] reg_dest_MEM,
output reg [4:0] reg_dest_WB
);
initial reg_dest_WB = 4'h0;
always @(posedge clk)
if (!bubbleW) begin
if (flushW) reg_dest_WB <= 4'h0;
else reg_dest_WB <= reg_dest_MEM;
end
endmodule
| 6.677724 |
module addr_16bit (
S,
C3,
A,
B,
C_1
);
input [15:0] A, B; //16位被加数A和B
input C_1; //最低位的进位信号
output [15:0] S; //16位和
output C3; //向最高位和=的进位信号
wire C0, C1, C2;
addr_4bit
FA4bit0 (
S[3:0],
C0,
A[3:0],
B[3:0],
C_1
), //调用4位... | 6.994005 |
module addr_32bit (
S,
C1,
A,
B,
C_1
);
input [31:0] A, B; //32位被加数A和B
input C_1; //最低位的进位信号
output [31:0] S; //32位和
output C1; //向最高位和=的进位信号
wire C0;
addr_16bit
FA16bit0 (
S[15:0],
C0,
A[15:0],
B[15:0],
C_1
), //调用16位全加... | 7.469937 |
module addr_4bit (
S,
C3,
A,
B,
C_1
);
input [3:0] A, B; //四位被加数A和B
input C_1; //最低位的进位信号
output [3:0] S; //四位和
output C3; //向最高位和=的进位信号
wire C0, C1, C2;
fulladder
FA0 (
S[0],
C0,
A[0],
B[0],
C_1
), //调用1位全加器
FA1 (... | 7.052758 |
module adder_4bit (
ina,
inb,
sum,
cout,
cin
);
input [3:0] ina, inb;
input cin;
output [3:0] sum;
output cout;
assign {cout, sum} = ina + inb + cin;
endmodule
| 9.041993 |
module adder_4bit (
ina,
inb,
sum,
cout,
cin
);
input [3:0] ina, inb;
input cin;
output reg [3:0] sum;
output reg cout;
always @(*) {cout, sum} = ina + inb + cin;
endmodule
| 9.041993 |
module addr_BCD_converter (
output reg [16:0] addr,
input [3:0] BCD,
input [9:0] h_cnt,
input [9:0] v_cnt
);
always @* begin
case (BCD)
4'd0: addr = (h_cnt >> 1) % 35 + (v_cnt >> 1) % 35 * 320;
4'd1: addr = (h_cnt >> 1) % 35 + (v_cnt >> 1) % 35 * 320 + 35 * 320;
4'd2: addr = ... | 6.888468 |
module AddrBusBitLow (
PHI1,
PHI2,
ADX,
Z_ADX,
ADX_ABX,
ABus_out
);
input PHI1;
input PHI2;
input ADX; // Address bus bit
input Z_ADX; // Bit zeroing command
input ADX_ABX;
output ABus_out; // Output value of the address bus terminal
wire n_adx = ~(ADX & ~Z_ADX);
wire abff_o... | 7.743473 |
module AddrBusBit (
PHI1,
PHI2,
ADX,
ADX_ABX,
ABus_out
);
input PHI1;
input PHI2;
input ADX;
input ADX_ABX;
output ABus_out;
wire n_adx = ~(ADX);
wire abff_out;
AddrBusFF abff (
.phi_load(PHI1),
.phi_keep(PHI2),
.en(ADX_ABX),
.val(n_adx),
.q(abff_out)... | 6.884705 |
module AddrBusFF (
phi_load,
phi_keep,
en,
val,
q,
nq
);
input phi_load; // PHI phase during which the FF value can be modified
input phi_keep; // PHI phase during which the current value is "holding".
input en; // 1: Writing a value is enabled
input val; // New value
output q; /... | 7.108188 |
module controls the addressing of the ring
// buffer storage readout. It receives the last
// address that the rb wrote to, and when there is
// a readout request it starts from that location and
// iterates backwards, outputting which address the rb
// should read out next. It also receives how many words
// are to b... | 7.843499 |
module Addr_Color #(
parameter ADDR_WIDTH = 17
) (
input clk,
input rstn,
input en,
output color_finish,
output clear_finish,
output [ADDR_WIDTH-1:0] addr
);
reg [ADDR_WIDTH-1 : 0] cnt;
wire [ADDR_... | 8.144665 |
module addr_ctrl (
input wire clk_50M,
input wire rst_n,
output wire [7:0] addr,
input wire [31:0] freqctrl //frequency control word
);
reg [31:0] cnt;
assign addr = cnt[31:24];
always @(posedge clk_50M, negedge rst_n) begin
if (rst_n == 0) cnt <= 0;
else cnt <= cnt + freqctrl;
en... | 7.302113 |
module addr_decode (
input [12:0] addr,
output reg rom_en,
output reg ram_en
);
always @(addr)
casex (addr)
13'b1_0xxx_xxxx_xxxx: {rom_en, ram_en} <= 2'b10;
13'b0_0xxx_xxxx_xxxx: {rom_en, ram_en} <= 2'b10;
13'b1_1xxx_xxxx_xxxx: {rom_en, ram_en} <= 2'b01;
default: {rom_en, ram_... | 7.911742 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module ADDR_FOR_SVM (
input iClk,
input iReady,
output reg [11:0] oADDR,
output reg oDONE
);
reg [3:0] count;
always @(posedge iClk) begin
if (iReady) begin
count <= 4'd0;
oADDR <= 12'd0;
end else begin
count <= count + 1'b1;
if (count == 4'd9) begin
oADDR <=... | 6.834998 |
module AddrGenerator #(
// ADDR_WIDTH must not be greater than 67
parameter ADDR_WIDTH = 27
) (
input wire clk,
input wire i_rst,
input wire i_wen,
input wire i_ren,
output wire [ADDR_WIDTH-1 : 0] o_waddr,
ou... | 8.779836 |
module addr_gen_integer (
input wire rst_n,
input wire clk,
input wire clr,
input wire en_sw,
input wire en_tb,
input wire [11:0] init_mvec, // {w, h}
output reg [11:0] addr_sw,
output reg [ 7:0] addr_tb
);
reg en_sw_pre;
reg [4:0] c... | 6.578557 |
module Addr_Ini #(
parameter ADDR_WIDTH = 17
) (
input clk,
input rstn,
input cnt_en,
output reg Initial_finish,
output [ADDR_WIDTH-1 : 0] addr
);
reg [ADDR_WIDTH-1 : 0] cnt;
wire [ADDR_WIDTH-1 :... | 7.405961 |
module test;
localparam sc_100_k = 13'h1148; // 00
localparam sc_10_k = 13'h1149; // 03
localparam sc_1_k = 13'h114a; // 00
localparam sc_100 = 13'h114b; // 02
localparam sc_10 = 13'h114c; // 09
localparam sc_1 = 13'h114d; // 00
reg reset = 1;
/* Make a reset that pulses once. */
initial begin... | 6.675276 |
module addr_load (
input [31:0] BusA,
input [31:0] imm,
output reg [31:0] Address
);
always @(*) begin
Address = BusA + imm;
Address = (Address[31:28] == 4'ha || Address[31:28] == 4'hb) ? Address - 32'ha0000000 : Address;
end
endmodule
| 7.915335 |
module addr_manager #(
parameter ADDR_WIDTH = 16,
parameter ADDR_PAGE_NUM_LOG = 12,
parameter DATA_WIDTH = 8,
parameter MODE_INIT = 0
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
//from controller
input table_read_req,
input table_write_req,
input [ADD... | 7.510022 |
module addr_mux (
addr,
d_in_0,
d_in_1,
d_out
);
input addr;
input [`WIDTH-1:0] d_in_0, d_in_1;
output reg [`WIDTH-1:0] d_out;
always @* begin
if (addr) d_out = d_in_1;
else d_out = d_in_0;
end
endmodule
| 7.601012 |
module: addr_mux4
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module addr_mux4_tb;
// Inputs
reg [9:0] data0;
reg [9:0] data1;
reg [9:0] data2;
reg [9:0] data3;
reg [1:0] select;... | 6.87286 |
module Addr_Parameter (
input clk,
input rstn,
input en,
output reg [15:0] col_start,
output reg [15:0] row_start
);
wire [15:0] col_start_nxt = (col_start == 16'd220) ? 16'd0 : col_start + 16'd20;
wire [15:0] row_start_nxt = ( col_start == 16'd220 ) ? ( row_... | 7.728704 |
module addr_parse #(
parameter BYTES_PER_LINE = 16,
parameter NUM_LINE = 256,
parameter OFFSET_WIDTH = $clog2(BYTES_PER_LINE),
parameter INDEX_WIDTH = $clog2(NUM_LINE),
parameter TAG_WIDTH = 32 - OFFSET_WIDTH - INDEX_WIDTH
) (
input [31:0] addr,
output [INDEX_WIDTH-1:0] index,
output [T... | 7.699279 |
module addr_reg (
clk,
reset,
data_on_ar,
ar_on_bus,
load_ar
);
input clk;
input reset;
input load_ar;
input [7:0] data_on_ar;
output [7:0] ar_on_bus;
reg [7:0] ar_on_bus;
always @(posedge clk) begin
if (reset) ar_on_bus <= 8'd0;
else begin
if (load_ar) ar_on_bus <= data... | 6.602304 |
module addr_shift (
addr_in,
addr_out
);
input [31:0] addr_in;
output [31:0] addr_out;
assign addr_out = addr_in << 2;
endmodule
| 8.446049 |
module \$add (
A,
B,
Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_BITS_CONNMAP_ = 0;
parameter _TECHMAP_CONNMAP_A_ = 0;
... | 7.120414 |
module addsl2 (
input [31:0] OP,
input [31:0] OP1,
output reg [31:0] OPS
);
always @* begin
OPS <= OP + OP1;
end
endmodule
| 7.084656 |
module AddState (
input [1:0] idle_Allign2,
input [35:0] cout_Allign2,
input [35:0] zout_Allign2,
input [31:0] sout_Allign2,
input [1:0] modeout_Allign2,
input operationout_Allign2,
input NatLogFlagout_Allign2,
input [7:0] InsTag_Allign2,
input clock,
output reg [1:0] idle_AddSta... | 7.327793 |
module addsub #(
parameter DATAWIDTH = 6
) (
input AddSub,
input [DATAWIDTH-1:0] A,
input [DATAWIDTH-1:0] BusWires,
output reg [DATAWIDTH-1:0] Sum
);
always @(*) begin
if (!AddSub) Sum = A + BusWires;
else Sum = A - BusWires;
end
endmodule
| 6.882069 |
module AddSub1b (
input wire A,
B,
Ctrl,
Ci,
output wire S,
Co
);
wire tmp;
assign tmp = B ^ Ctrl;
Adder1b add (
.A (A),
.B (tmp),
.Ci(Ci),
.S (S),
.Co(Co)
);
endmodule
| 7.315286 |
module addsub32 (
a,
b,
sub,
s,
co,
ofl,
sign
);
input [31:0] a, b;
input sub;
output [31:0] s;
output co, ofl, sign;
reg ofl = 1'b0;
assign sign = s[31];
always @(a or b or sub) begin
if (a[31] == b[31]) begin
if (s[31] != a[31]) begin
ofl = 1'b1;
end
... | 6.768353 |
module AddSub32bFlag (
input [31:0] A,
input [31:0] B,
input Ci,
input Ctrl,
output [31:0] S,
output CF,
OF,
ZF,
SF,
PF // 符号SF、进位CF、溢出OF、零标志ZF、奇偶PF
);
wire add_cf, sub_cf, sub_sf, co;
wire [31:0] c;
AddSub1b aS0 (
.A(A[0]),
.B(B[0]),
.Ci(Ctrl ^ Ci),
... | 7.882733 |
module addsub4 (
input wire [3:0] a,
input wire [3:0] b,
input wire e,
output wire [3:0] s,
output wire cf
);
wire [4:0] c;
wire [3:0] bx;
assign bx = b ^ {4{e}};
assign c[0] = e;
assign s = a ^ bx ^ c[3:0];
assign c[4:1] = a & bx | c[3:0] & (a ^ bx);
assign cf = c[4];
endmodule
| 7.146674 |
module AddSub4b (
input wire [3:0] A,
input wire [3:0] B,
input wire Ci, // if subtraction, it is borrow
input wire Ctrl, // [mode] 0: addup; 1: subtraction
output wire [3:0] S,
output wire Co
);
wire c1, c2, c3;
AddSub1b aS1 (
.A(A[0]),
.B(B[0]),
.Ci(Ctrl ^ Ci),
.... | 6.637786 |
module AddSub4bFlag (
input [3:0] A,
input [3:0] B,
input Ci,
input Ctrl,
output [3:0] S,
output CF,
OF,
ZF,
SF,
PF // 符号SF、进位CF、溢出OF、零标志ZF、奇偶PF
);
wire add_cf, sub_cf, sub_sf, co;
wire c0, c1, c2, c3;
AddSub1b aS0 (
.A(A[0]),
.B(B[0]),
.Ci(Ctrl ^ Ci),... | 7.852344 |
module AddSub4bFlag_tb ();
reg [3:0] A;
reg [3:0] B;
reg Ci;
reg Ctrl;
wire [3:0] S;
wire CF, OF, ZF, SF, PF; // 符号SF、进位CF、溢出OF、零标志ZF、奇偶PF
AddSub4bFlag uut (
A,
B,
Ci,
Ctrl,
S,
CF,
OF,
ZF,
SF,
PF
);
initial begin
$dumpfile("AddSub4bFla... | 6.844324 |
module addsub4b_tb;
// Inputs
reg [3:0] A;
reg [3:0] B;
reg add_sub;
// Outputs
wire [3:0] R;
wire Co;
// Instantiate the Unit Under Test (UUT)
addsub4b uut (
.add_sub(add_sub),
.A3(A[3]),
.A2(A[2]),
.A1(A[1]),
.A0(A[0]),
.B3(B[3]),
.B2(B[2]),
.B1(B[1... | 6.810319 |
module addsub4_structural (
result,
carry_out,
subtract,
a,
b,
carry_in
);
input [3:0] a, b;
input carry_in; // input carry or borrow
input subtract; // subtract: 1, subtract; 0, add
output [3:0] result;
output carry_out;
wire [2:0] carry_borrow;
wire [3:0] b_subtract;
wire ... | 6.51423 |
module addsub4_structural_test;
reg [3:0] a, b;
reg carry_in;
reg subtract;
wire [3:0] result;
wire carry_out;
addsub4_structural ass1 (
result,
carry_out,
subtract,
a,
b,
carry_in
);
initial begin
a = 4'b0000;
b = 4'b0000;
carry_in = 1;
subtract = ... | 6.51423 |
module AddSubC #(
////////////////////////////////////////////////////
// Parameters
parameter width = 4 //input bit width
) (
////////////////////////////////////////////////////
// Ports
input SubEn, //Subustractor Enable
input [width-1:0] A,
B,
output reg [width-1:0] S,
out... | 7.725658 |
module FA
////////////////////////////////////////////////////
// Ports
(
input A,
B,
Ci,
output S,
Co
);
wire exAB = A ^ B;
assign S = exAB ^ Ci;
assign Co = (A & B) | (exAB & Ci);
endmodule
| 7.055788 |
module addSubNbits #(
parameter N = 4
) (
input wire [N:0] x,
input wire [N:0] y,
input sel,
output wire [N+1:0] z
);
assign z = (sel == 0) ? {1'b0, x} + {1'b0, y} : {1'b0, x} - {1'b0, y};
endmodule
| 7.2424 |
module addSubNbits2 #(
parameter N = 4
) (
input wire [N:0] x,
input wire [N:0] y,
input sel,
output reg [N+1:0] z
);
always @(*) begin
if (sel == 0) z = {1'b0, x} + {1'b0, y};
else z = {1'b0, x} - {1'b0, y};
end
always @(*) begin
case (sel)
1'b0: z = {1'b0, x} + {1'b0, y};... | 6.868045 |
module AddSub #(
////////////////////////////////////////////////////
// Parameters
parameter width = 4 //input bit width
) (
////////////////////////////////////////////////////
// Ports
input SubEn, //Subustractor Enable
input [width-1:0] A,
B,
output [width:0] S
);
/////////... | 7.718964 |
module FA
////////////////////////////////////////////////////
// Ports
(
input A,
B,
Ci,
output S,
Co
);
wire exAB = A ^ B;
assign S = exAB ^ Ci;
assign Co = (A & B) | (exAB & Ci);
endmodule
| 7.055788 |
module RoundRawFNToRecFN (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [26:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [32:0] io_out
);
wire roundAn... | 6.992477 |
module AddSubPE_tb;
reg clock, reset;
reg [31:0] in_0;
reg [31:0] in_1;
reg op_type;
reg use_int;
reg tininess;
reg [ 2:0] rounding;
wire [31:0] out;
// PERIOD
localparam period = 5;
AddSubPE UUT (
.clock(clock),
.reset(reset),
.io_use_int(use_int),
... | 7.323087 |
module AddSubtract (
input wire [num_bits_1-1:0] in1,
input wire [num_bits_2-1:0] in2,
input wire [num_bits_2-1:0] in3,
input wire clock,
input wire reset_n,
output reg [num_bits_1-1:0] out
);
initial begin
out = 0;
end
parameter num_bits_1 = 16;
parameter num_bits_2 = 12;
alway... | 7.858811 |
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