code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module AddressMapping (
input [31:0] ALU_result,
output [ 5:0] address
);
wire [31:0] address_base;
assign address_base = (ALU_result - 1024);
// sram check for [7:1]
assign address = address_base[7:2];
endmodule
| 7.394252 |
module addressRAM (
input [4:0] step,
output reg re_RAM,
output reg [12:0] firstaddr,
lastaddr
);
parameter picture_size = 0;
parameter convolution_size = 0;
parameter picture_storage_limit = picture_size * picture_size;
parameter convweight = picture_storage_limit + (1*4 + 4*4 + 4*8 + 8*8) * convolution_size; // all convolution weights [784:1828]
parameter conv1 = picture_storage_limit + 1 * 4 * convolution_size;
parameter conv2 = picture_storage_limit + (1 * 4 + 4 * 4) * convolution_size;
parameter conv3 = picture_storage_limit + (1 * 4 + 4 * 4 + 4 * 8) * convolution_size;
parameter conv4 = picture_storage_limit + (1 * 4 + 4 * 4 + 4 * 8 + 8 * 8) * convolution_size;
parameter conv5 = picture_storage_limit + (1*4 + 4*4 + 4*8 + 8*8 + 8*16) * convolution_size;
parameter conv6 = picture_storage_limit + (1*4 + 4*4 + 4*8 + 8*8 + 8*16 + 16*16) * convolution_size;
parameter dense = conv6 + 176;
always @(step)
case (step)
1'd1: begin //picture
firstaddr = 0;
lastaddr = picture_storage_limit;
re_RAM = 1;
end
2'd2: begin //weights conv1
firstaddr = picture_storage_limit;
lastaddr = conv1;
re_RAM = 1;
end
3'd4: begin //weights conv2
firstaddr = conv1;
lastaddr = conv2;
re_RAM = 1;
end
3'd6: begin //weights conv3
firstaddr = conv2;
lastaddr = conv3;
re_RAM = 1;
end
4'd8: begin //weights conv4
firstaddr = conv3;
lastaddr = conv4;
re_RAM = 1;
end
4'd10: begin //weights conv5
firstaddr = conv4;
lastaddr = conv5;
re_RAM = 1;
end
4'd12: begin //weights conv6
firstaddr = conv5;
lastaddr = conv6;
re_RAM = 1;
end
4'd14: begin //weights conv7
firstaddr = conv6;
lastaddr = dense;
re_RAM = 1;
end
default: begin
re_RAM = 0;
end
endcase
endmodule
| 7.695746 |
module addressRegister (
addrOut,
addrIn,
enable
);
output reg [15:0] addrOut;
input wire [15:0] addrIn;
input wire enable;
always @(enable) begin
if (!enable) begin
addrOut = addrIn;
end
end
endmodule
| 6.628698 |
module AddressRegisterFile #(
parameter reg_width = 32
) (
input CLK,
input [2:0] REG_SEL,
input SUPERVISOR_MODE,
input S,
input [reg_width-1:0] D,
output [reg_width-1:0] Q
);
wire [7:0] en;
wire [7:0] en_gnd;
Decoder #(3) reg_sel (
REG_SEL,
en
);
assign en_gnd = 8'b0;
wire [reg_width-1:0] q_gnd;
// TODO: this doesn't actually work lol
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : generate_registers
Register #(reg_width) a (
CLK,
en[i],
en_gnd[i],
S,
D,
Q,
q_gnd[i]
);
end
endgenerate
endmodule
| 7.466366 |
module addrRegMux (
initAddr,
incrAddr,
selStartAddr,
addrCountOut,
shiftRegOut,
adderAddr
);
output reg [15:0] initAddr;
input wire [15:0] addrCountOut, adderAddr, shiftRegOut;
input wire selStartAddr, incrAddr;
initial begin
incrAddr = 0;
selStartAddr = 0;
end
always @(incrAddr or selStartAddr) begin
if (incrAddr) begin
initAddr <= adderAddr;
end else if (selStartAddr) begin
initAddr <= shiftRegOut;
end
end
endmodule
| 6.79522 |
module AddressStack #(
parameter N2 = 8,
parameter S = 32,
parameter S2 = 5
) (
input clk,
input reset,
input call_ah_as,
input retn_ah_as,
input cnt_inc_ah_as,
input [N2-1:0] funcNum_ah_as,
output reg call_as_cb,
output reg retn_as_cb,
output reg cnt_inc_as_cb,
output [N2-1:0] funcNum_as_cb,
output reg exe_start_as,
output reg exe_end_as
);
//+++++++++++++++++++++++++++++
// PIPELINING
//+++++++++++++++++++++++++++++
reg call_r;
reg retn_r;
reg cnt_inc_r;
reg exe_end_r; // delay(pipeline) one cycle so that exe_end_as is aligned with the last write in CounterStorage
always @(posedge clk) begin
if (reset) begin
call_r <= 1'b0;
retn_r <= 1'b0;
cnt_inc_r <= 1'b0;
call_as_cb <= 1'b0;
retn_as_cb <= 1'b0;
cnt_inc_as_cb <= 1'b0;
end else begin
call_r <= call_ah_as;
retn_r <= retn_ah_as;
cnt_inc_r <= cnt_inc_ah_as;
call_as_cb <= call_r & ~(exe_end_r | exe_end_as);
retn_as_cb <= retn_r & ~(exe_end_r | exe_end_as);
cnt_inc_as_cb <= cnt_inc_r;
end
end
//+++++++++++++++++++++++++++++
// STACK
//+++++++++++++++++++++++++++++
wire [N2-1:0] stack_rd_data;
reg [N2-1:0] stack_wr_data;
reg [S2-1:0] stack_addr;
reg stack_wren;
assign funcNum_as_cb = stack_rd_data;
always @(posedge clk) begin
if (reset) begin
stack_wren <= 0;
stack_wr_data <= {N2{1'b0}};
stack_addr <= {S2{1'b1}}; // The first funcNum (first call) will be written to addr 0
end else begin
stack_wren <= call_ah_as; // push on call - write stack only on call
stack_wr_data <= funcNum_ah_as;
if (call_ah_as) stack_addr <= stack_addr + 1'b1; // push on call
else if (retn_ah_as) stack_addr <= stack_addr - 1'b1; // pop on retn
else stack_addr <= stack_addr;
end
end
// Just a ram blk used as stack; Nothing Fancy Here ~~~
altsyncram stack (
.clock0 (clk),
.clocken0 (1'b1),
.address_a (stack_addr),
.wren_a (stack_wren),
.data_a (stack_wr_data),
.q_a (stack_rd_data),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b0),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b0),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b0),
.wren_b (1'b0)
);
defparam stack.clock_enable_input_a = "BYPASS", stack.clock_enable_output_a = "BYPASS",
stack.intended_device_family = "Cyclone II", stack.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
stack.lpm_type = "altsyncram", stack.numwords_a = S, stack.operation_mode = "SINGLE_PORT",
stack.outdata_aclr_a = "NONE", stack.outdata_reg_a = "UNREGISTERED",
stack.power_up_uninitialized = "FALSE", stack.ram_block_type = "M4K", stack.widthad_a = S2,
stack.width_a = N2, stack.width_byteena_a = 1;
//+++++++++++++++++++++++++++++
// EXECUTION STATUS
//+++++++++++++++++++++++++++++
always @(posedge clk) begin
if (reset) begin
exe_start_as <= 1'b0;
exe_end_r <= 1'b0;
exe_end_as <= 1'b0;
end else begin
// aligned with *_as_cb signals
exe_start_as <= exe_start_as | call_r; // aligned with call_as_cb
exe_end_r <= exe_start_as & (&stack_addr) & retn_r; // aligned with retn_as_cb
exe_end_as <= exe_end_r | exe_end_as; // aligned with last write in CounterStorage
end
end
endmodule
| 6.74131 |
module AddressWindow (
Address,
Base,
Head,
Valid,
Offset
);
input [15:0] Address, Base, Head;
output Valid;
output [15:0] Offset;
wor baseValid;
wire headValid;
AlteraCompareUnsigned compareBase (
.dataa(Address),
.datab(Base),
.aeb (baseValid),
.agb (baseValid)
);
AlteraCompareUnsigned compareHead (
.dataa(Address),
.datab(Head),
.alb (headValid)
);
assign Valid = baseValid & headValid;
assign Offset = Address - Base;
endmodule
| 7.305518 |
module address_adder_test;
reg [1:0] ADDR1_SEL;
reg [2:0] ADDR2_SEL;
reg LSHFT;
reg signed [15:0] IR;
reg [15:0] PC;
reg [15:0] SR1;
wire [15:0] OUT;
ADDRESS_ADDER test_address_adder (
ADDR1_SEL,
ADDR2_SEL,
LSHFT,
IR,
PC,
SR1,
OUT
);
initial begin
// Check PC + 0
PC = 5;
ADDR1_SEL = test_address_adder.ADDR1_PC;
ADDR2_SEL = test_address_adder.ADDR2_ZERO;
LSHFT = 0;
if (OUT != 5) begin
$display("OUT = 0x%h, expected 0x5", OUT);
end
// Check PC + IR[5:0]
PC = 5;
IR = 16'h1111;
ADDR1_SEL = test_address_adder.ADDR1_PC;
ADDR2_SEL = test_address_adder.ADDR2_OFFSET6;
LSHFT = 0;
#2
if (OUT != 16'h16) begin
$display("OUT = 0x%h, expected 0x16", OUT);
end
// Check PC + IR[5:0], with sign extension
PC = 5;
IR = -1;
ADDR1_SEL = test_address_adder.ADDR1_PC;
ADDR2_SEL = test_address_adder.ADDR2_OFFSET6;
LSHFT = 0;
#2
if (OUT != 16'h4) begin
$display("OUT = 0x%h, expected 0x4", OUT);
end
// Check PC + IR[8:0]
PC = 5;
IR = 16'h1011;
ADDR1_SEL = test_address_adder.ADDR1_PC;
ADDR2_SEL = test_address_adder.ADDR2_PCOFFSET9;
LSHFT = 0;
#2
if (OUT != 16'h16) begin
$display("OUT = 0x%h, expected 0x16", OUT);
end
// Check PC + IR[8:0], with sign extension
PC = 256;
IR = -255;
ADDR1_SEL = test_address_adder.ADDR1_PC;
ADDR2_SEL = test_address_adder.ADDR2_PCOFFSET9;
LSHFT = 0;
#2
if (OUT != 16'h1) begin
$display("OUT = 0x%h, expected 0x1", OUT);
end
// Check PC + IR[10:0]
PC = 5;
IR = 16'h1111;
ADDR1_SEL = test_address_adder.ADDR1_PC;
ADDR2_SEL = test_address_adder.ADDR2_PCOFFSET11;
LSHFT = 0;
#2
if (OUT != 16'h116) begin
$display("OUT = 0x%h, expected 0x116", OUT);
end
// Check PC + IR[10:0], with sign extension
PC = 200;
IR = -100;
ADDR1_SEL = test_address_adder.ADDR1_PC;
ADDR2_SEL = test_address_adder.ADDR2_PCOFFSET11;
LSHFT = 0;
#2
if (OUT != 16'd100) begin
$display("OUT = %d, expected 100", OUT);
end
// Check BASER + IR[10:0], with left shift
SR1 = 16'h40;
IR = 16'h10;
ADDR1_SEL = test_address_adder.ADDR1_BASER;
ADDR2_SEL = test_address_adder.ADDR2_PCOFFSET11;
LSHFT = 1;
#2
if (OUT != 16'h60) begin
$display("OUT = 0x%h, expected 0x60", OUT);
end
// Check BASER + IR[10:0], with left shift and sign extend
SR1 = 16'h40;
IR = -1;
ADDR1_SEL = test_address_adder.ADDR1_BASER;
ADDR2_SEL = test_address_adder.ADDR2_PCOFFSET11;
LSHFT = 1;
#2
if (OUT != 16'h3e) begin
$display("OUT = 0x%h, expected 0x3e", OUT);
end
$display("Address adder test done");
end
endmodule
| 6.742658 |
module address_counter (
input clk,
input reset,
input set_valid,
input [7:0] set_value,
output rd,
output [7:0] address
);
reg [1:0] tact;
reg tact_flag;
reg [7:0] current_address;
always @(posedge clk) begin
if (reset) tact <= 3'b000;
else tact <= tact + 1'b1;
if (tact == 2'b10) tact_flag <= 1'b1;
else tact_flag <= 1'b0;
end
always @(posedge clk) begin
if (reset) current_address <= 8'h00;
else if (set_valid) current_address <= set_value;
else if (tact_flag) current_address <= current_address + 1'b1;
end
assign rd = tact_flag;
assign address = current_address;
endmodule
| 6.631086 |
module address_decode (
input [15:0] cpu_a,
input [ 3:0] romsel,
output ddr_enable,
// Memory enables
output ram_enable,
// 0x0000
output rom_enable,
// 0x8000 (BASIC/sideways ROMs)
output mos_enable,
// 0xC000
// IO region enables
output io_fred,
// 0xFC00 (1 MHz bus)
output io_jim,
// 0xFD00 (1 MHz bus)
output io_sheila,
// 0xFE00 (System peripherals)
// SHIELA
output crtc_enable,
// 0xFE00-FE07
output acia_enable,
// 0xFE08-FE0F
output serproc_enable,
// 0xFE10-FE1F
output vidproc_enable,
// 0xFE20-FE2F
output romsel_enable,
// 0xFE30-FE3F
output sys_via_enable,
// 0xFE40-FE5F
output user_via_enable,
// 0xFE60-FE7F
output fddc_enable,
// 0xFE80-FE9F
output adlc_enable,
// 0xFEA0-FEBF (Econet)
output adc_enable,
// 0xFEC0-FEDF
output tube_enable,
// 0xFEE0-FEFF
output mhz1_enable
);
// Set for access to any 1 MHz peripheral
// Address decoding
// 0x0000 = 32 KB SRAM
// 0x8000 = 16 KB BASIC/Sideways ROMs
// 0xC000 = 16 KB MOS ROM
//
// IO regions are mapped into a hole in the MOS. There are three regions:
// 0xFC00 = FRED
// 0xFD00 = JIM
// 0xFE00 = SHEILA
assign ddr_enable = (!romsel[3] & (cpu_a[15:14] === 2'b10));
assign ram_enable = ~cpu_a[15];
assign rom_enable = cpu_a[15] & ~cpu_a[14];
assign mos_enable = cpu_a[15] & cpu_a[14] & ~(io_fred | io_jim | io_sheila);
assign io_fred = cpu_a[15:8] === 8'b11111100 ? 1'b1 : 1'b0;
assign io_jim = cpu_a[15:8] === 8'b11111101 ? 1'b1 : 1'b0;
assign io_sheila = cpu_a[15:8] === 8'b11111110 ? 1'b1 : 1'b0;
// The following IO regions are accessed at 1 MHz and hence will stall the
// CPU accordingly
assign mhz1_enable = io_fred | io_jim | adc_enable | sys_via_enable |
user_via_enable | serproc_enable | acia_enable | crtc_enable;
// SHEILA address demux
// All the system peripherals are mapped into this page as follows:
// 0xFE00 - 0xFE07 = MC6845 CRTC
// 0xFE08 - 0xFE0F = MC6850 ACIA (Serial/Tape)
// 0xFE10 - 0xFE1F = Serial ULA
// 0xFE20 - 0xFE2F = Video ULA
// 0xFE30 - 0xFE3F = Paged ROM select latch
// 0xFE40 - 0xFE5F = System VIA (6522)
// 0xFE60 - 0xFE7F = User VIA (6522)
// 0xFE80 - 0xFE9F = 8271 Floppy disc controller
// 0xFEA0 - 0xFEBF = 68B54 ADLC for Econet
// 0xFEC0 - 0xFEDF = uPD7002 ADC
// 0xFEE0 - 0xFEFF = Tube ULA
assign crtc_enable = io_sheila & (cpu_a[7:3] === 'd0);
assign acia_enable = io_sheila & (cpu_a[7:3] === 'd1);
assign serproc_enable = io_sheila & (cpu_a[7:4] === 'b0001);
assign vidproc_enable = io_sheila & (cpu_a[7:4] === 'b0010);
assign romsel_enable = io_sheila & (cpu_a[7:4] === 'b0011);
assign sys_via_enable = io_sheila & (cpu_a[7:5] === 'b010);
assign user_via_enable = io_sheila & (cpu_a[7:5] === 'b011);
assign fddc_enable = io_sheila & (cpu_a[7:5] === 'b100);
assign adlc_enable = io_sheila & (cpu_a[7:5] === 'b101);
assign adc_enable = io_sheila & (cpu_a[7:5] === 'b110);
assign tube_enable = io_sheila & (cpu_a[7:5] === 'b111);
endmodule
| 7.247981 |
module Address_Decoder_tb;
reg clk;
reg [31:0] Address;
reg write_enable;
wire out_WE1, out_WE2, out_WEM;
wire [1:0] Read_Data_Sel;
Address_Decoder DUT (
.A(Address),
.WE(write_enable),
.WE1(out_WE1),
.WE2(out_WE2),
.WEM(out_WEM),
.RdSel(Read_Data_Sel)
);
reg [31:0] i;
initial begin
// Memory Module
for (i = 0; i < 'hFD; i = i + 1) begin
Address <= i;
write_enable <= 0;
tick;
end
for (i = 0; i < 'hFD; i = i + 1) begin
Address <= i;
write_enable <= 1;
tick;
end
// Factorial Module
for (i = 0; i < 'h0C; i = i + 1) begin
Address <= i + 'h800;
write_enable <= 0;
tick;
end
for (i = 0; i < 'h0C; i = i + 1) begin
Address <= i + 'h800;
write_enable <= 1;
tick;
end
// GPIO Module
for (i = 0; i < 'h0C; i = i + 1) begin
Address <= i + 'h900;
write_enable <= 0;
tick;
end
for (i = 0; i < 'h0C; i = i + 1) begin
Address <= i + 'h900;
write_enable <= 1;
tick;
end
// unmapped Addresses
for (i = 0; i < 'hFF; i = i + 1) begin
Address <= i + 'h100;
write_enable <= 1;
tick;
end
for (i = 0; i < 'hFF; i = i + 1) begin
Address <= i + 'h200;
write_enable <= 0;
tick;
end
for (i = 0; i < 'hFF; i = i + 1) begin
Address <= i + 'h1000;
write_enable <= 1;
tick;
end
end
task tick;
begin
clk <= 0;
#5;
clk <= 1;
#5;
end
endtask
endmodule
| 6.64906 |
module address_decode_mpu (
input wire clk,
input wire vma,
input wire e_rom,
input wire screen_control,
input wire [15:0] addr,
input wire r_w_n,
output wire [13:0] ram_addr,
output wire [ 1:0] ram_lane_sel,
output wire racnt,
output wire rom_cs,
output wire palette_ram_cs,
output wire pia_widget_cs,
output wire pia_rom_cs,
output wire reg_misc_cs,
output wire evie,
output wire video_count_cs,
output wire cmos_ram_cs
);
wire [5:0] pseudo_addr;
rom_decoder_4 decoder_4 (
.clock_i(clk),
.clock_enable_i(1'b1),
.address_i({screen_control, addr[15:8]}),
.data_o({ram_lane_sel, pseudo_addr})
);
assign ram_addr = {addr[7:0], pseudo_addr};
wire mux_8e_g1 = (addr[15] && addr[14]) || (r_w_n && e_rom);
wire mux_8e_g2 = vma;
wire [15:0] mux_8e_y_n;
mux_74154 mux_8e (
.a (addr[15:12]),
.g_n({!mux_8e_g2, !mux_8e_g1}),
.y_n(mux_8e_y_n)
);
assign racnt = (!mux_8e_y_n[9] || !mux_8e_y_n[10] || !mux_8e_y_n[11] || !mux_8e_g1) && vma;
wire i_o = !mux_8e_y_n[12];
assign rom_cs =
!mux_8e_y_n[0]
|| !mux_8e_y_n[1]
|| !mux_8e_y_n[2]
|| !mux_8e_y_n[3]
|| !mux_8e_y_n[4]
|| !mux_8e_y_n[5]
|| !mux_8e_y_n[6]
|| !mux_8e_y_n[7]
|| !mux_8e_y_n[8]
|| !mux_8e_y_n[13]
|| !mux_8e_y_n[14]
|| !mux_8e_y_n[15]
;
wire addr_c0xx_c3xx = i_o && (addr[11:10] == 2'b00);
wire addr_c4xx_c7xx = i_o && (addr[11:10] == 2'b01);
wire addr_c8xx_cbxx = i_o && (addr[11:10] == 2'b10);
wire addr_ccxx_cfxx = i_o && (addr[11:10] == 2'b11);
wire addr_c8xx = i_o && (addr[11:8] == 4'b1000);
wire addr_c9xx = i_o && (addr[11:8] == 4'b1001);
wire addr_caxx = i_o && (addr[11:8] == 4'b1010);
wire addr_cbxx = i_o && (addr[11:8] == 4'b1011);
assign palette_ram_cs = addr_c0xx_c3xx;
assign pia_widget_cs = addr_c8xx && (addr[3:2] == 2'b01);
assign pia_rom_cs = addr_c8xx && (addr[3:2] == 2'b11);
assign reg_misc_cs = addr_c9xx;
assign evie = addr_caxx;
assign video_count_cs = addr_cbxx && (addr[0] == 1'b0);
assign cmos_ram_cs = addr_ccxx_cfxx;
/*
localparam
ADDR_RAM,
ADDR_ROM,
ADDR_PIA_ROM,
ADDR_PIA_WIDGET,
ADDR_PALETTE,
ADDR_MISC,
ADDR_EVIE,
ADDR_VIDEO_COUNT,
ADDR_CMOS
;
always @* begin
casez(addr[15:12])
16'b0000_????_????_????: blah;
endcase
end
*/
endmodule
| 7.247981 |
module name - address_dispatch
// Version: V3.4.0.20220301
// Created:
// by - fenglin
////////////////////////////////////////////////////////////////////////////
// Description:
// - encapsulate ARP request frame、PTP frame、NMAC report frame to tsmp frame;
///////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module address_dispatch
(
i_clk,
i_rst_n,
iv_data,
i_data_wr,
ov_hcp_mid,
ov_tsnlight_mid
);
// I/O
// clk & rst
input i_clk;
input i_rst_n;
// pkt input
input [8:0] iv_data;
input i_data_wr;
// pkt output
output reg [11:0] ov_hcp_mid;
output reg [11:0] ov_tsnlight_mid;
reg [1:0] rv_adi_state;
reg [6:0] rv_byte_cnt;
localparam IDLE_S = 2'd0,
EXTRACT_MAC_S = 2'd1,
DISCARD_DATA_S = 2'd2;
always @(posedge i_clk or negedge i_rst_n) begin
if(!i_rst_n) begin
rv_byte_cnt <= 7'b0;
ov_hcp_mid <= 12'h0;
ov_tsnlight_mid <= 12'h0;
rv_adi_state <= IDLE_S;
end
else begin
case(rv_adi_state)
IDLE_S:begin
if(i_data_wr && iv_data[8])begin
rv_byte_cnt <= 7'd1;
rv_adi_state <= EXTRACT_MAC_S;
end
else begin
rv_byte_cnt <= 7'b0;
rv_adi_state <= IDLE_S;
end
end
EXTRACT_MAC_S:begin
rv_byte_cnt <= rv_byte_cnt + 1'b1;
if(rv_byte_cnt == 7'd17)begin
ov_tsnlight_mid[11:4] <= iv_data[7:0];
end
else if(rv_byte_cnt == 7'd18)begin
ov_tsnlight_mid[3:0] <= iv_data[7:4];
ov_hcp_mid[11:8] <= iv_data[3:0];
end
else if(rv_byte_cnt == 7'd19)begin
ov_hcp_mid[7:0] <= iv_data[7:0];
rv_adi_state <= DISCARD_DATA_S;
end
else begin
rv_adi_state <= EXTRACT_MAC_S;
end
end
DISCARD_DATA_S:begin
if(i_data_wr && iv_data[8])begin//last cycle
rv_adi_state <= IDLE_S;
end
else begin
rv_adi_state <= DISCARD_DATA_S;
end
end
default:begin
rv_adi_state <= IDLE_S;
end
endcase
end
end
endmodule
| 7.871214 |
module address_display (
input wire [8:0] address_line,
input wire clk,
input wire reset,
output reg [7:0] sseg_indicator,
output reg [3:0] digits
);
reg [31:0] counter;
reg [11:0] tubes_bcd_values;
reg [ 2:0] digit_counter;
always @(posedge clk) begin
if (~reset) begin
counter <= 0;
digits <= 4'b1111;
tubes_bcd_values <= 0;
sseg_indicator <= 8'b11000000;
digit_counter <= 0;
end else counter <= counter + 1;
if (counter == 4) begin
tubes_bcd_values <= //12'b001101011001; // 359
encode_to_bcd(
address_line
);
case (digit_counter)
3'b000: begin
sseg_indicator <= encode_to_sseg(tubes_bcd_values[11:8]);
digits <= 4'b1011;
end
3'b001: begin
sseg_indicator <= encode_to_sseg(tubes_bcd_values[7:4]);
digits <= 4'b1101;
end
3'b010: begin
sseg_indicator <= encode_to_sseg(tubes_bcd_values[3:0]);
digits <= 4'b1110;
end
default: begin
end
endcase
end
if (counter == 100000) begin
counter <= 0;
digit_counter <= digit_counter + 1;
if (digit_counter == 3'b010) digit_counter <= 0;
end
begin
end
end
function [11:0] encode_to_bcd;
input reg [8:0] binary_code;
reg [3:0] hundreds;
reg [3:0] tens;
reg [3:0] ones;
integer i;
begin
hundreds = 0;
tens = 0;
ones = 0;
for (i = 8; i >= 0; i = i - 1) begin
if (hundreds >= 5) hundreds = hundreds + 3;
if (tens >= 5) tens = tens + 3;
if (ones >= 5) ones = ones + 3;
hundreds = hundreds << 1;
hundreds[0] = tens[3];
tens = tens << 1;
tens[0] = ones[3];
ones = ones << 1;
ones[0] = binary_code[i];
end
$display("Encode to bcd, hundreds : %d", hundreds);
$display("Encode to bcd, tens : %d", tens);
$display("Encode to bcd, ones : %d", ones);
encode_to_bcd[3:0] = ones[3:0];
encode_to_bcd[7:4] = tens[3:0];
encode_to_bcd[11:8] = hundreds[3:0];
end
endfunction
function [7:0] encode_to_sseg;
input [3:0] bcd;
case (bcd)
4'b0000: encode_to_sseg = 8'b11000000; // 0
4'b0001: encode_to_sseg = 8'b11111001; // 1
4'b0010: encode_to_sseg = 8'b10100100; // 2
4'b0011: encode_to_sseg = 8'b10110000; // 3
4'b0100: encode_to_sseg = 8'b10011001; // 4
4'b0101: encode_to_sseg = 8'b10010010; // 5
4'b0110: encode_to_sseg = 8'b10000010; // 6
4'b0111: encode_to_sseg = 8'b11111000; // 7
4'b1000: encode_to_sseg = 8'b10000000; // 8
4'b1001: encode_to_sseg = 8'b10010000; // 9
default: encode_to_sseg = 8'b11000000; // 0
endcase
endfunction
endmodule
| 6.599651 |
module: address_display
//
// Dependencies:
//
// Revision:
// Revision 1.0
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module address_display_testbench;
// Inputs
reg [8:0] address_line;
reg clk;
reg reset;
// Outputs
wire [7:0] sseg_indicator;
wire [3:0] digits;
reg [9:0] counter;
// Instantiate the Unit Under Test (UUT)
address_display uut (
.address_line(address_line),
.clk(clk),
.reset(reset),
.sseg_indicator(sseg_indicator),
.digits(digits)
);
initial begin
clk = 0;
reset = 1;
counter = 0;
address_line = 0;
// Wait 200 ns for pulse reset
#200 reset = 0;
// Add stimulus here
#200 reset = 1;
end
always
begin
#10 clk <= ~clk;
counter <= counter + 1;
if(counter == 70)
address_line <= 1;
if(counter == 90)
address_line <= 124;
if(counter == 110)
address_line <= 279;
end
endmodule
| 7.2938 |
module address_gen (
iRST_N,
iCLK,
oADDRESS,
iEND_ADDRESS
);
parameter WIDE = 23;
input iRST_N, iCLK;
output [WIDE-1:0] oADDRESS;
//parameter END_ADDRESS = 20'hFFFFF;
input [WIDE -1 : 0] iEND_ADDRESS;
reg [WIDE-1:0] addr_cnt;
assign oADDRESS = addr_cnt;
////////// ADDRESS Generator //////////////
always @(negedge iCLK or negedge iRST_N) begin
parameter ONE = 23'b1;
parameter ZERO = 23'b0;
if (!iRST_N) addr_cnt <= ZERO;
else begin
if (addr_cnt < iEND_ADDRESS) addr_cnt <= addr_cnt + ONE;
// else
//addr_cnt <= ZERO;
end
end
endmodule
| 6.808832 |
module is_op1_reg (
out,
op1,
mod_rm
);
output out;
input [2:0] op1;
input [7:0] mod_rm;
// reg if op1 == 1 or (op1 == 4 and mod == 11)
wire [1:0] mod = mod_rm[7:6];
wire op1_is_1;
compare #(
.WIDTH(3)
) op1_cmp (
op1,
3'd1,
op1_is_1
);
wire mod_rm_reg;
compare #(
.WIDTH(5)
) mod_rm_cmp (
{op1, mod},
5'b10011,
mod_rm_reg
);
or2$ or_out (
out,
op1_is_1,
mod_rm_reg
);
endmodule
| 7.089995 |
module address_uart_generator (
s_tick,
address_uart,
recieving,
recieve_over,
recieve_start,
transmit_begin,
transmit_active,
transmit_over,
finish,
write_en_uart,
start_calculation,
uart_en
);
input s_tick;
output reg [19:0] address_uart = 20'd0;
input recieving, recieve_over, recieve_start;
output reg transmit_begin = 1'b0;
input transmit_active, transmit_over;
input finish;
output reg [1:0] write_en_uart;
output reg start_calculation = 1'b0;
output reg uart_en = 1'b0;
reg [3:0] state;
parameter idle_rx=4'd0,data_bits=4'd1, write_state=4'd2 , write_idle=4'd3, cal_address_uart=4'd4, over_rx=4'd5;
parameter idle1_tx=4'd6,idle2_tx=4'd7, read_state=4'd8 ,transmit_start=4'd9,transmitting=4'd10,calc_tx_address_uart=4'd11,over_tx =4'd12;
parameter write = 2'b11, read = 2'b00, h_imp = 2'd10;
parameter end_of_original_image=20'd65024 , begining_of_sampled_image= 20'd65025, end_of_sampled_image = 20'd81153;
always @(posedge s_tick) begin
case (state)
idle_rx: begin
if (recieve_start) state = data_bits;
end
data_bits: begin
if (recieving == 1'b0) state = write_state;
else state = data_bits;
end
write_state: begin
write_en_uart = write;
uart_en = 1'b1;
state = write_idle;
end
write_idle: state = cal_address_uart;
cal_address_uart: begin
if (recieve_over) begin
write_en_uart = h_imp;
uart_en = 1'b0;
if(address_uart==end_of_original_image)// end of the image address
begin
//rx_check=8'd100;
state = over_rx;
end else begin
address_uart = address_uart + 1'b1;
state = idle_rx;
end
end else state = cal_address_uart;
end
over_rx: begin
start_calculation = 1'b1;
uart_en = 1'b0; //0
state = idle1_tx;
end
idle1_tx: begin
if (finish) begin // finish ctr signal is from state machine
address_uart=begining_of_sampled_image; // begining of the new down sampled image memory location
state = idle2_tx;
//rx_check=8'd255;
end
end
idle2_tx: begin
state = read_state;
write_en_uart = read;
uart_en = 1'b1;
//rx_check=8'd25;
end
read_state: begin
state = transmit_start;
//rx_check=8'd28;
end
transmit_start: begin
transmit_begin = 1'b1;
if (transmit_active) begin
transmit_begin = 1'b0;
state = transmitting;
end
end
transmitting: begin
if (transmit_active == 1'b0) state = calc_tx_address_uart;
else state = transmitting;
end
calc_tx_address_uart: begin
write_en_uart = h_imp;
uart_en = 1'b0;
if (transmit_over) begin
if(address_uart==end_of_sampled_image)// end of the new down sampled image memory location
begin
state = over_tx;
end else begin
state = idle2_tx;
address_uart = address_uart + 1'b1;
end
end else state = calc_tx_address_uart;
end
over_tx: begin
uart_en = 1'b0;
end
default: state = idle_rx;
endcase
end
endmodule
| 6.997047 |
module CLOCK_DIVIDER (
clk_IN,
clk
); // clock divider for top design
input clk_IN;
reg [7:0] counter = 8'd0;
output reg clk = 1'd0;
always @(posedge clk_IN) begin
if (counter==8'd9) // generate 1mhz frequency from 50mhz internal oscillator
begin
counter = 8'd0;
clk = ~clk;
end else begin
counter = counter + 8'd1;
end
end
endmodule
| 7.080154 |
module address_gererate_tb;
reg [6:0] rd_data_add;
reg [6:0] r_lay_cnt;
reg [5:0] bf_cnt;
reg [2:0] lay_cnt;
reg [5:0] rom_wn;
reg clk;
initial clk = 0;
always #20 clk = ~clk;
initial begin
r_lay_cnt = 1;
forever begin
#2560;
r_lay_cnt = 6'd1 << lay_cnt + 1;
end
end
initial begin
lay_cnt = 0;
forever begin
#2560;
lay_cnt = lay_cnt + 1;
end
end
initial bf_cnt = 0;
always #40 bf_cnt = bf_cnt + 1;
initial begin
#40000;
$stop;
end
initial
forever begin
/*每次蝶形变换的RAM 数据读取的地址*/
rd_data_add[0] <= (r_lay_cnt[6]|r_lay_cnt[5]|r_lay_cnt[4]|r_lay_cnt[3]|r_lay_cnt[2]|r_lay_cnt[1])&(bf_cnt[0]) ;
rd_data_add[1] <= (r_lay_cnt[6]|r_lay_cnt[5]|r_lay_cnt[4]|r_lay_cnt[3]|r_lay_cnt[2])&(bf_cnt[1])|(r_lay_cnt[0])&bf_cnt[0];
rd_data_add[2] <= (r_lay_cnt[6]|r_lay_cnt[5]|r_lay_cnt[4]|r_lay_cnt[3])&(bf_cnt[2])|(r_lay_cnt[1]|r_lay_cnt[0])&bf_cnt[1];
rd_data_add[3] <= (r_lay_cnt[6]|r_lay_cnt[5]|r_lay_cnt[4])&(bf_cnt[3])|(r_lay_cnt[2]|r_lay_cnt[1]|r_lay_cnt[0])&bf_cnt[2];
rd_data_add[4] <= (r_lay_cnt[6]|r_lay_cnt[5])&(bf_cnt[4])|(r_lay_cnt[3]|r_lay_cnt[2]|r_lay_cnt[1]|r_lay_cnt[0])&bf_cnt[3];
rd_data_add[5] <= (r_lay_cnt[6])&(bf_cnt[5])|(r_lay_cnt[4]|r_lay_cnt[3]|r_lay_cnt[2]|r_lay_cnt[1]|r_lay_cnt[0])&bf_cnt[4];
rd_data_add[6] <= (r_lay_cnt[5]|r_lay_cnt[4]|r_lay_cnt[3]|r_lay_cnt[2]|r_lay_cnt[1]|r_lay_cnt[0])&bf_cnt[5];
/*每次蝶形变换的 旋转因子的地址*/
rom_wn <={r_lay_cnt[6],r_lay_cnt[6],r_lay_cnt[6],r_lay_cnt[6],r_lay_cnt[6],r_lay_cnt[6]}&{bf_cnt[5],bf_cnt[4],bf_cnt[3],bf_cnt[2],bf_cnt[1],bf_cnt[0]}|
{r_lay_cnt[5],r_lay_cnt[5],r_lay_cnt[5],r_lay_cnt[5],r_lay_cnt[5],r_lay_cnt[5]}&{bf_cnt[4],bf_cnt[3],bf_cnt[2],bf_cnt[1],bf_cnt[0],1'b0}|
{r_lay_cnt[4],r_lay_cnt[4],r_lay_cnt[4],r_lay_cnt[4],r_lay_cnt[4],r_lay_cnt[4]}&{bf_cnt[3],bf_cnt[2],bf_cnt[1],bf_cnt[0],1'b0,1'b0}|
{r_lay_cnt[3],r_lay_cnt[3],r_lay_cnt[3],r_lay_cnt[3],r_lay_cnt[3],r_lay_cnt[3]}&{bf_cnt[2],bf_cnt[1],bf_cnt[0],1'b0,1'b0,1'b0}|
{r_lay_cnt[2],r_lay_cnt[2],r_lay_cnt[2],r_lay_cnt[2],r_lay_cnt[2],r_lay_cnt[2]}&{bf_cnt[1],bf_cnt[0],1'b0,1'b0,1'b0,1'b0}|
{r_lay_cnt[1],r_lay_cnt[1],r_lay_cnt[1],r_lay_cnt[1],r_lay_cnt[1],r_lay_cnt[1]}&{bf_cnt[0],1'b0,1'b0,1'b0,1'b0,1'b0}|
{r_lay_cnt[0],r_lay_cnt[0],r_lay_cnt[0],r_lay_cnt[0],r_lay_cnt[0],r_lay_cnt[0]}&{1'b0,1'b0,1'b0,1'b0,1'b0,1'b0};
#40;
end
endmodule
| 6.993316 |
module address_jump (
PC,
INST,
O
);
input [31:0] PC, INST;
output [31:0] O;
buf buf_1 (
O[31], PC[31]
), buf_2 (
O[30], PC[30]
), buf_3 (
O[29], PC[29]
), buf_4 (
O[28], PC[28]
), buf_4_2 (
O[27], PC[27]
), buf_4_3 (
O[26], PC[26]
), buf_5 (
O[25], INST[25]
), buf_6 (
O[24], INST[24]
), buf_7 (
O[23], INST[23]
), buf_8 (
O[22], INST[22]
), buf_9 (
O[21], INST[21]
), buf_10 (
O[20], INST[20]
), buf_11 (
O[19], INST[19]
), buf_12 (
O[18], INST[18]
), buf_13 (
O[17], INST[17]
), buf_14 (
O[16], INST[16]
), buf_15 (
O[15], INST[15]
), buf_16 (
O[14], INST[14]
), buf_17 (
O[13], INST[13]
), buf_18 (
O[12], INST[12]
), buf_19 (
O[11], INST[11]
), buf_20 (
O[10], INST[10]
), buf_21 (
O[9], INST[9]
), buf_22 (
O[8], INST[8]
), buf_23 (
O[7], INST[7]
), buf_24 (
O[6], INST[6]
), buf_25 (
O[5], INST[5]
), buf_26 (
O[4], INST[4]
), buf_27 (
O[3], INST[3]
), buf_28 (
O[2], INST[2]
), buf_29 (
O[1], INST[1]
), buf_30 (
O[0], INST[0]
);
endmodule
| 6.949518 |
module address_jump_testbench ();
reg [31:0] pc, inst;
wire [31:0] o;
address_jump test (
pc,
inst,
o
);
initial begin
pc = 32'b1110_0000_0000_0000_0000_0000_0000_0000;
inst = 32'b0000_0011_1111_1111_1111_1111_1111_1111;
#`DELAY;
pc = 32'b1010_0000_0000_0000_0000_0000_0000_0000;
inst = 32'b0000_0011_0000_1111_0000_1111_1111_1111;
end
initial begin
$monitor("time = %2d, pc =%1b, ins=%1b, OUT=%1b", $time, pc, inst, o);
end
endmodule
| 7.473832 |
module address_map (
input wire [ 1:0] sel_in,
input wire [18:0] col_index_in,
input wire [18:0] row_index_in,
output wire [18:0] address_out
);
localparam array_wid = 19'd320;
localparam array_hgt = 19'd240;
localparam LEFT_IMAGE = 19'd10, RIGHT_IMAGE = 19'd174763, DISP_IMAGE = 19'd349525;
reg [31:0] address;
always @* begin
case (sel_in)
2'b00: begin
address = LEFT_IMAGE + (row_index_in * (array_wid)) + col_index_in;
end
2'b01: begin
address = RIGHT_IMAGE + (row_index_in * (array_wid)) + col_index_in;
end
2'b10: begin
address = DISP_IMAGE + (row_index_in * (array_wid)) + col_index_in;
end
2'b11: begin
address = LEFT_IMAGE + (row_index_in * (array_wid)) + col_index_in;
end
default: begin
end
endcase
end
assign address_out = address[18:0];
endmodule
| 7.119441 |
module Address_Mapping (
input [31:0] in,
output [31:0] out
);
assign out = in - 32'b00000000000000000000010000000000;
endmodule
| 9.084946 |
module address_map_tb;
reg [ 3:0] NODEADDRESS;
reg [31:0] MEMADDRESS;
wire [31:0] ADDRESS;
address_map my_address_map (
NODEADDRESS,
MEMADDRESS,
ADDRESS
);
initial begin
// ------- ADDRESS MAP Test 01 : Address generation for node (0, 0) ----------
NODEADDRESS = 4'b0000;
MEMADDRESS = 32'd10;
#0;
`assert(ADDRESS, 32'd10);
$display("ADDRESS MAP Test 01: Address generation for node (0, 1) passed!");
// ------- ADDRESS MAP Test 02 : Address generation for node (0, 1) ----------
NODEADDRESS = 4'b0001;
MEMADDRESS = 32'd10;
#0;
`assert(ADDRESS, 32'd1034);
$display("ADDRESS MAP Test 02: Address generation for node (0, 1) passed!");
// ------- ADDRESS MAP Test 03 : Address generation for node (1, 1) ----------
NODEADDRESS = 4'b0101;
MEMADDRESS = 32'd10;
#0;
`assert(ADDRESS, 32'd5130);
$display("ADDRESS MAP Test 03: Address generation for node (1, 1) passed!");
$display("All Tests Passed !!!");
end
endmodule
| 6.765859 |
module address_multiplexer (
input fetch,
input [12:0] ir_addr,
input [12:0] pc_addr,
output [12:0] addr
);
assign addr = fetch ? pc_addr : ir_addr;
endmodule
| 7.710017 |
module Addr_MUX (
CLK,
RST,
HADDR,
HADDR_1,
HADDR_2,
SEL
);
input [1:0] SEL;
input RST, CLK;
input [15:0] HADDR_1, HADDR_2;
output reg [15:0] HADDR;
always @(posedge CLK or posedge RST) begin
if(SEL == 2'b01 && RST != 1) // Master 1 selected
begin
HADDR = HADDR_1;
end
else if(SEL == 2'b10 && RST != 1) // Master 2 selected
begin
HADDR = HADDR_2;
end
else if(RST == 1) // Async reset
begin
HADDR = 16'bx;
end else begin
HADDR = 16'bx;
end
end
endmodule
| 7.830388 |
module address_request_decoder (
input wire [9:0] address,
input wire ale,
input wire aen,
input wire ior, // = g_rd
input wire iow, // = p_wr
input wire interrupt_req, // = v_rp
input wire zk4,
output wire sel,
output wire sel1,
output wire [1:0] internal_address,
output wire interrupt_en // interrupt enabled
);
wire [7:0] d10_addr;
wire [1:0] d10_cs;
wire [3:0] d10_out;
wire [3:0] d10_out_pulled;
wire d5_y3;
wire d9_y1;
wire d9_y2;
wire d9_y3;
// DD10
assign d10_addr[0] = address[6];
assign d10_addr[1] = address[5];
assign d10_addr[2] = address[4];
assign d10_addr[3] = address[3];
assign d10_addr[4] = address[2];
assign d10_addr[5] = address[1];
assign d10_addr[6] = address[0];
assign d10_addr[7] = ale;
assign d10_cs[0] = d9_y1;
assign d10_cs[1] = aen;
assign d10_out_pulled[0] = d10_out[0] == 1'b0 ? 1'b0 : 1'b1;
assign d10_out_pulled[1] = d10_out[1] == 1'b0 ? 1'b0 : 1'b1;
assign d10_out_pulled[2] = d10_out[2] == 1'b0 ? 1'b0 : 1'b1;
assign d10_out_pulled[3] = d10_out[3] == 1'b0 ? 1'b0 : 1'b1;
assign interrupt_en = d9_y3;
assign internal_address[0] = d10_out_pulled[1];
assign internal_address[1] = d10_out_pulled[0];
assign sel1 = d10_out_pulled[2];
// DD5
SN74LS00 d5 (
.a3(ior),
.b3(iow),
.y3(d5_y3),
.a4(d9_y2),
.b4(address[8]),
.y4(sel)
);
// DD9
SN74LS27 d9 (
.a1(d5_y3),
.b1(d5_y3),
.c1(d5_y3),
.y1(d9_y1),
.a2(address[7]),
.b2(d10_out_pulled[3]),
.c2(address[9]),
.y2(d9_y2),
.a3(interrupt_req),
.b3(zk4),
.c3(interrupt_req),
.y3(d9_y3)
);
// DD10
dig_machine_ip3601 d10 (
.address(d10_addr),
.cs(d10_cs),
.data(d10_out)
);
endmodule
| 6.614643 |
module address_request_decoder_testbench ();
reg [ 9:0] address;
reg ale;
reg aen;
reg ior; // = g_rd
reg iow; // = p_wr
reg interrupt_req; // = v_rp
reg zk4;
wire sel;
wire sel1;
wire [ 1:0] internal_address;
wire interrupt_en; // interrupt enabled
reg [31:0] counter;
reg [ 1:0] operation; // 0 -read, 1 - write
address_request_decoder uut (
.address(address),
.ale(ale),
.aen(aen),
.ior(ior),
.iow(iow),
.interrupt_req(interrupt_req),
.zk4(zk4),
.sel(sel),
.sel1(sel1),
.internal_address(internal_address),
.interrupt_en(interrupt_en)
);
initial begin
address <= 40;
ale <= 0;
aen <= 0;
ior <= 1;
iow <= 1;
interrupt_req <= 0; // ???
zk4 <= 1;
counter <= 0;
operation <= 0;
end
always @* begin
#120 counter <= counter + 1;
// ALE generation
if (counter == 10) begin
ale <= 1;
aen <= 1;
end else if (counter == 20) begin
if (operation == 0) ior <= 0;
else iow <= 0;
end else if (counter == 44) begin
ale <= 0;
aen <= 0;
end else if (counter == 136) begin
if (operation == 0) ior <= 1;
else iow <= 1;
end else if (counter == 146) begin
counter <= 10;
operation <= operation + 1;
if (operation == 1) begin
address <= address + 1;
operation <= 0;
end
// isa addresses range from 100-13E
if (address == 318) begin
address <= 256;
end
end
end
endmodule
| 6.614643 |
module address_resolver (
input [1:0] mapping,
input [5:0] addri,
output reg [5:0] addro
);
localparam DECODE_TRUE = 2'd0, ENCODE_TRUE = 2'd1, STANDARD = 2'd2;
always @(*) begin
case (mapping)
DECODE_TRUE: begin
addro = {addri[3], addri[2], addri[1], addri[0], addri[5], addri[4]};
end
ENCODE_TRUE: begin
addro = {addri[1], addri[0], addri[5], addri[4], addri[3], addri[2]};
end
STANDARD: begin
addro = addri;
end
default: begin
addro = addri;
end
endcase
end
endmodule
| 7.238851 |
module Address_Selector (
ADD,
Q,
RAM_S
);
input [15:0] ADD;
output reg [16:0] Q;
output reg RAM_S;
always @(ADD) begin
if (ADD[15:0] < 17) begin
RAM_S <= 1'b0;
end else begin
RAM_S <= 1'b1;
end
case (ADD[15:0])
16'h0000: Q <= 17'b00000000000000001;
16'h0001: Q <= 17'b00000000000000010;
16'h0002: Q <= 17'b00000000000000100;
16'h0003: Q <= 17'b00000000000001000;
16'h0004: Q <= 17'b00000000000010000;
16'h0005: Q <= 17'b00000000000100000;
16'h0006: Q <= 17'b00000000001000000;
16'h0007: Q <= 17'b00000000010000000;
16'h0008: Q <= 17'b00000000100000000;
16'h0009: Q <= 17'b00000001000000000;
16'h000a: Q <= 17'b00000010000000000;
16'h000b: Q <= 17'b00000100000000000;
16'h000c: Q <= 17'b00001000000000000;
16'h000d: Q <= 17'b00010000000000000;
16'h000e: Q <= 17'b00100000000000000;
16'h000f: Q <= 17'b01000000000000000;
16'h0010: Q <= 17'b10000000000000000;
default: Q <= 17'b00000000000000000;
endcase
end
endmodule
| 7.525099 |
module Address_setter #(
parameter ADDR_WIDTH = 5,
parameter SHIFT_CONTROL = 2
) (
input single_clk,
input [(SHIFT_CONTROL-1):0] change_shift,
output write_shift_enabler,
read_shift_enabler
);
reg read_shift, write_shift;
always @(posedge single_clk) begin
// changes write_shift
if ((change_shift == 2'b01) && (write_shift == 1'b0)) begin
write_shift <= 1'b1;
end else if ((change_shift == 2'b01) && (write_shift == 1'b1)) begin
write_shift <= 1'b0;
end // changes read_shift
else if ((change_shift == 2'b11) && (read_shift == 1'b0)) begin
read_shift <= 1'b1;
end else if ((change_shift == 2'b11) && (read_shift == 1'b1)) begin
read_shift <= 1'b0;
end
end
assign write_shift_enabler = write_shift;
assign read_shift_enabler = read_shift;
endmodule
| 7.205516 |
modules together in the form, allowing to use them in the single-cycle MIPS processor.
// Author: github.com/vsilchuk
module address_space(i_clk, i_we, i_arst, i_address, i_write_data, o_read_data, io_IO, bam_output);
input i_clk; // Input clock signal, 50MHz system clock on Altera DE2 FPGA board, for example
input i_we; // We want to write data in the RAM, or, maybe in some other configuration registers, like GPIO or BAM registers
input i_arst; // Reset signal
input [31:0] i_address; // Generated by ALU
input [31:0] i_write_data; // Input data, which will be written
output [31:0] o_read_data; // RAM HAS AN ASYNCHONOUS READING - ONLY i_address --> assign
inout [31:0] io_IO; // GPIO inout 32-bit port
output bam_output; // Output pin, which is the source of BAM signal
wire RAM_WE;
wire GPIO_DDIR_WE;
wire GPIO_DOUT_WE;
wire GPIO_DIN_RE;
wire BAM_DC_WE;
wire BAM_CFG_WE;
wire [31:0] DIN; // Read data from GPIO
wire [31:0] o_ram_data; // Read data from RAM
assign o_read_data = (GPIO_DIN_RE) ? DIN : o_ram_data; // To choose between output data from RAM and output data from GPIO DIN register
wire bam_enable; // Signals the GPIO module (i_ALT) that the BAM module generates a signal
wire bam_signal; // Source of the BAM signal in the GPIO module (i_ALT_IN)
reg [3:0] CONFIG; // BAM configuration register, precsaler mode and start module bit
reg [15:0] DCYCLE; // BAM configuration register, duty cycle
always @(posedge i_clk, posedge i_arst, posedge BAM_CFG_WE, posedge BAM_DC_WE) begin
if(i_arst) begin
CONFIG <= {4{1'b0}};
DCYCLE <= {16{1'b0}};
end else if (BAM_CFG_WE) begin
CONFIG <= i_write_data[3:0];
end else if(BAM_DC_WE) begin
DCYCLE <= i_write_data[15:0];
end else begin
CONFIG <= CONFIG;
DCYCLE <= DCYCLE;
end
end
address_decoder adec_inst(.i_clk(i_clk),
.i_we(i_we),
.i_address(i_address),
.o_ram_we(RAM_WE),
.o_ddir_we(GPIO_DDIR_WE),
.o_dout_we(GPIO_DOUT_WE),
.o_din_re(GPIO_DIN_RE),
.o_dcycle_we(BAM_DC_WE),
.o_config_we(BAM_CFG_WE));
data_memory RAM_inst(.i_clk(i_clk), // same as module in the MIPS folder
.i_we(RAM_WE),
.i_arst(i_arst),
.i_address(i_address),
.i_write_data(i_write_data),
.o_read_data(o_ram_data));
GPIO GPIO_inst(.i_clk(i_clk),
.i_arst(i_arst),
.i_DATA(i_write_data),
.i_ALT(bam_enable),
.i_ALT_IN(bam_signal),
.i_DDIR_WE(GPIO_DDIR_WE),
.i_DIN_RE(GPIO_DIN_RE),
.i_DOUT_WE(GPIO_DOUT_WE),
.o_DIN(DIN),
.io_IO(io_IO),
.BAM_output(bam_output));
BAM BAM_inst(.i_clk(i_clk),
.i_arst(i_arst),
.i_on(CONFIG[0]),
.i_presc_mode(CONFIG[3:1]),
.i_duty_cycle(DCYCLE[15:0]),
.o_bam_enable(bam_enable),
.o_signal(bam_signal));
endmodule
| 8.112044 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module fifo_address_sync #(
parameter ADDRESS_WIDTH = 4
) (
input clk,
input resetn,
input m_axis_ready,
output reg m_axis_valid,
output reg [ADDRESS_WIDTH-1:0] m_axis_raddr,
output [ADDRESS_WIDTH:0] m_axis_level,
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output reg [ADDRESS_WIDTH-1:0] s_axis_waddr,
output [ADDRESS_WIDTH:0] s_axis_room
);
localparam MAX_ROOM = {1'b1,{ADDRESS_WIDTH{1'b0}}};
reg [ADDRESS_WIDTH:0] room = MAX_ROOM;
reg [ADDRESS_WIDTH:0] level = 'h00;
reg [ADDRESS_WIDTH:0] level_next;
assign s_axis_room = room;
assign m_axis_level = level;
wire read = m_axis_ready & m_axis_valid;
wire write = s_axis_ready & s_axis_valid;
always @(posedge clk)
begin
if (resetn == 1'b0) begin
s_axis_waddr <= 'h00;
m_axis_raddr <= 'h00;
end else begin
if (write)
s_axis_waddr <= s_axis_waddr + 1'b1;
if (read)
m_axis_raddr <= m_axis_raddr + 1'b1;
end
end
always @(*)
begin
if (read & ~write)
level_next <= level - 1'b1;
else if (~read & write)
level_next <= level + 1'b1;
else
level_next <= level;
end
always @(posedge clk)
begin
if (resetn == 1'b0) begin
m_axis_valid <= 1'b0;
s_axis_ready <= 1'b0;
level <= 'h00;
room <= MAX_ROOM;
s_axis_empty <= 'h00;
end else begin
level <= level_next;
room <= MAX_ROOM - level_next;
m_axis_valid <= level_next != 0;
s_axis_ready <= level_next != MAX_ROOM;
s_axis_empty <= level_next == 0;
end
end
endmodule
| 8.180735 |
module address_x (
clk,
rst_n,
enable,
wren,
rden,
address_w,
address_r,
address
);
input clk, rst_n, enable;
input [6:0] address;
output wren, rden;
output [6:0] address_w;
output [6:0] address_r;
reg wren, rden;
reg preenable;
reg [6:0] address_w;
reg [6:0] address_wr;
reg [6:0] address_r;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
wren <= 0;
rden <= 0;
address_wr <= 0;
address_w <= 0;
address_r <= 0;
preenable <= 0;
end else begin
preenable <= enable;
if ((enable == 1'b1) & (preenable == 0)) begin
address_w <= address_wr;
if (address_wr == 65) address_wr <= 0;
else address_wr <= address_wr + 1;
wren = 1;
end else if (enable == 1'b1) begin
if (address_w >= address) address_r = address_w - address;
else address_r = 66 + address_w - address;
rden = 1;
wren = 0;
end else begin
rden = 0;
wren = 0;
end
end
end
endmodule
| 6.783092 |
module outputs the "zig-zag" index. For instance, the
* pixel at location (row = 2, col = 3) is index 19 in row-major indexing and is index 17 in the
* zig-zag order
*/
module row_major_to_zig_zag(input [5:0] row_major_index,
output reg [5:0] zig_zag_index);
// I'm sure there's a smarter way to synthesize this with for loops, but I don't have time for that.
// It took me like 10 minutes to make this table because the octal numbers make everything easy when
// talking about row-major indexes in an 8x8 block.
always @* begin
case(row_major_index)
6'o 0_0: zig_zag_index = 6'd0;
6'o 0_1: zig_zag_index = 6'd1;
6'o 1_0: zig_zag_index = 6'd2;
6'o 2_0: zig_zag_index = 6'd3;
6'o 1_1: zig_zag_index = 6'd4;
6'o 0_2: zig_zag_index = 6'd5;
6'o 0_3: zig_zag_index = 6'd6;
6'o 1_2: zig_zag_index = 6'd7;
6'o 2_1: zig_zag_index = 6'd8;
6'o 3_0: zig_zag_index = 6'd9;
6'o 4_0: zig_zag_index = 6'd10;
6'o 3_1: zig_zag_index = 6'd11;
6'o 2_2: zig_zag_index = 6'd12;
6'o 1_3: zig_zag_index = 6'd13;
6'o 0_4: zig_zag_index = 6'd14;
6'o 0_5: zig_zag_index = 6'd15;
6'o 1_4: zig_zag_index = 6'd16;
6'o 2_3: zig_zag_index = 6'd17;
6'o 3_2: zig_zag_index = 6'd18;
6'o 4_1: zig_zag_index = 6'd19;
6'o 5_0: zig_zag_index = 6'd20;
6'o 6_0: zig_zag_index = 6'd21;
6'o 5_1: zig_zag_index = 6'd22;
6'o 4_2: zig_zag_index = 6'd23;
6'o 3_3: zig_zag_index = 6'd24;
6'o 2_4: zig_zag_index = 6'd25;
6'o 1_5: zig_zag_index = 6'd26;
6'o 0_6: zig_zag_index = 6'd27;
6'o 0_7: zig_zag_index = 6'd28;
6'o 1_6: zig_zag_index = 6'd29;
6'o 2_5: zig_zag_index = 6'd30;
6'o 3_4: zig_zag_index = 6'd31;
6'o 4_3: zig_zag_index = 6'd32;
6'o 5_2: zig_zag_index = 6'd33;
6'o 6_1: zig_zag_index = 6'd34;
6'o 7_0: zig_zag_index = 6'd35;
6'o 7_1: zig_zag_index = 6'd36;
6'o 6_2: zig_zag_index = 6'd37;
6'o 5_3: zig_zag_index = 6'd38;
6'o 4_4: zig_zag_index = 6'd39;
6'o 3_5: zig_zag_index = 6'd40;
6'o 2_6: zig_zag_index = 6'd41;
6'o 1_7: zig_zag_index = 6'd42;
6'o 2_7: zig_zag_index = 6'd43;
6'o 3_6: zig_zag_index = 6'd44;
6'o 4_5: zig_zag_index = 6'd45;
6'o 5_4: zig_zag_index = 6'd46;
6'o 6_3: zig_zag_index = 6'd47;
6'o 7_2: zig_zag_index = 6'd48;
6'o 7_3: zig_zag_index = 6'd49;
6'o 6_4: zig_zag_index = 6'd50;
6'o 5_5: zig_zag_index = 6'd51;
6'o 4_6: zig_zag_index = 6'd52;
6'o 3_7: zig_zag_index = 6'd53;
6'o 4_7: zig_zag_index = 6'd54;
6'o 5_6: zig_zag_index = 6'd55;
6'o 6_5: zig_zag_index = 6'd56;
6'o 7_4: zig_zag_index = 6'd57;
6'o 7_5: zig_zag_index = 6'd58;
6'o 6_6: zig_zag_index = 6'd59;
6'o 5_7: zig_zag_index = 6'd60;
6'o 6_7: zig_zag_index = 6'd61;
6'o 7_6: zig_zag_index = 6'd62;
6'o 7_7: zig_zag_index = 6'd63;
endcase
end
endmodule
| 7.147491 |
module Address_controller (
input rx_done,
tx_done,
Pro_over,
input [7:0] RxD,
input Pro_wea,
input [7:0] Pro_Dout,
input [17:0] ProAddress,
output reg [17:0] MemAddress,
output reg [7:0] MemData,
output reg Pro_rst,
output reg wea,
output reg Tx_start,
output reg Rx_finish = 1'b0,
output reg Tx_finish = 1'b0
);
localparam iba = 18'd7; //in begin address
localparam oba = 18'd7; //out begin address
localparam size = 18'd65536;
localparam out_size = 18'd16257;
reg u_wea = 1'b1;
reg [17:0] Rcounter = 18'd1;
reg [17:0] Tcounter = 18'd1;
reg [17:0] Rxaddress = 18'd7;
reg [17:0] Txaddress = 18'd65543;
//Receiver addressing
always @(posedge rx_done) begin
if (~Rx_finish) begin
if (size > Rcounter) begin
u_wea = 1'b1;
Rxaddress = Rxaddress + 1;
Rcounter = Rcounter + 1;
end else if (size == Rcounter) begin
Rx_finish = 1'b1;
u_wea = 1'b0;
end
end
end
//Transmitter addressing
always @(posedge tx_done) begin
if (~Tx_finish) begin
if (out_size > Tcounter) begin
Txaddress = Txaddress + 1;
Tcounter = Tcounter + 1;
end else if (out_size == Tcounter) Tx_finish = 1'b1;
end
end
//Final assignments
always@(Rx_finish or Tx_finish or Pro_over or Rxaddress or RxD or u_wea or ProAddress or Pro_Dout or Pro_wea or Txaddress)
begin
if(~Rx_finish) //Recieving img
begin
MemAddress = Rxaddress;
MemData = RxD;
wea = u_wea;
Tx_start = 0;
Pro_rst = 1;
end
else if(~Pro_over) //Processing
begin
MemAddress = ProAddress;
MemData = Pro_Dout;
wea = Pro_wea;
Tx_start = 0;
Pro_rst = 0;
end
else if(~Tx_finish) //Transmitting
begin
MemAddress = Txaddress;
MemData = RxD;
wea = u_wea;
Tx_start = 1;
Pro_rst = 0;
end else //Over
begin
MemAddress = Txaddress;
MemData = RxD;
wea = u_wea;
Tx_start = 0;
Pro_rst = 0;
end
end
endmodule
| 6.915489 |
module ADDRgen #(
parameter R = 5,
parameter N = 32
) (
input i_clk,
input i_rst,
input i_en,
output reg o_sel_wing,
output reg [R-2:0] o_a0, //m0 bank address
output reg [R-2:0] o_a1 //m1 bank address
);
// parameter, reg, wire
localparam s_0 = 2'b00; // IDLE
localparam s_1 = 2'b01; // RUN
localparam s_2 = 2'b10;
reg [ 1:0] r_ps; // present state
reg [R-2:0] r_bcnt;
reg [ 3:0] r_ccnt;
wire [R-2:0] w_a0;
wire [R-2:0] w_a1;
// Internal Connection
ADDRgen_element #(
.i(0),
.R(5)
) ADDRgen_element_a0 (
.i_b1(r_bcnt[0]),
.i_b0(1'b0),
.i_c (r_ccnt),
.i_s (^r_bcnt),
.o_a0(w_a0[0]),
.o_a1(w_a1[0])
);
ADDRgen_element #(
.i(1),
.R(5)
) ADDRgen_element_a1 (
.i_b1(r_bcnt[1]),
.i_b0(r_bcnt[0]),
.i_c (r_ccnt),
.i_s (^r_bcnt),
.o_a0(w_a0[1]),
.o_a1(w_a1[1])
);
ADDRgen_element #(
.i(2),
.R(5)
) ADDRgen_element_a2 (
.i_b1(r_bcnt[2]),
.i_b0(r_bcnt[1]),
.i_c (r_ccnt),
.i_s (^r_bcnt),
.o_a0(w_a0[2]),
.o_a1(w_a1[2])
);
ADDRgen_element #(
.i(3),
.R(5)
) ADDRgen_element_a3 (
.i_b1(r_bcnt[3]),
.i_b0(r_bcnt[2]),
.i_c (r_ccnt),
.i_s (^r_bcnt),
.o_a0(w_a0[3]),
.o_a1(w_a1[3])
);
// Sequntial Logic
always @(posedge i_clk) begin
if (i_rst) begin
o_a0 <= 0;
o_a1 <= 0;
r_ps <= s_0;
r_bcnt <= 0;
r_ccnt <= 0;
o_sel_wing <= 0;
end else begin
case (r_ps)
s_0: begin
if (i_en) r_ps <= s_1;
else r_ps <= s_0;
end
s_1: begin
r_ps <= s_2;
o_a0 <= w_a1;
o_a1 <= w_a0;
o_sel_wing <= ^r_bcnt;
if (r_bcnt == N / 2 - 1) begin
if (r_ccnt == R - 1) begin
r_bcnt <= 0;
r_ccnt <= 0;
end else begin
r_bcnt <= 0;
r_ccnt <= r_ccnt + 1;
end
end else r_bcnt <= r_bcnt + 1;
end
s_2: begin
r_ps <= s_0;
end
endcase
end
end
endmodule
| 8.268888 |
module barrel_shifter (
input s,
output w1,
w0
);
assign w1 = s ? 1'b1 : 1'b0;
assign w0 = s ? 1'b0 : 1'b1;
endmodule
| 8.606549 |
module bwMUX (
input in1,
input in2,
input sel,
output out
);
assign out = sel ? in1 : in2;
endmodule
| 8.991236 |
module Addr_MEM (
input wire clk,
bubbleM,
flushM,
input wire [4:0] reg_dest_EX,
output reg [4:0] reg_dest_MEM
);
initial reg_dest_MEM = 0;
always @(posedge clk)
if (!bubbleM) begin
if (flushM) reg_dest_MEM <= 0;
else reg_dest_MEM <= reg_dest_EX;
end
endmodule
| 7.246075 |
module addrmodule (
din,
muxin,
clk,
ena,
ageb,
muxout,
ab
);
//function: sorts the addresses accoring to the values of the counts
parameter DATA_WIDTH = 16; // size of each input data
parameter TOTAL_SYMBOLS = 10; // total number of symbols to be initialized
parameter ADDR_WIDTH = 4; // size of address to account for total symbols
input wire [ADDR_WIDTH-1:0] din; //input to the DFF
input wire [ADDR_WIDTH-1:0] muxin; // input to the mux (on schematic DATA)
input wire clk; //clk input for the DFF
input wire ena; // enable signal for DFF
input wire ageb; // True when A is greater than or equal to B (or reverse for ascending order)
output wire [ADDR_WIDTH-1:0] muxout; //output from the mux to next unit
output wire [ADDR_WIDTH-1:0] ab; // output from DFF which holds the stored value
assign muxout = ageb ? ab : muxin; // if (AGEB) then muxout = ab; else muxout = muxin
dffa #(ADDR_WIDTH) dat (
din,
clk,
ena,
ab
);
endmodule
| 7.120711 |
module AddrMux (
input CLK_FETCH,
input [12:0] ADDR_PC,
input [12:0] ADDR_IR,
output [12:0] ADDR
);
assign ADDR = (CLK_FETCH) ? ADDR_PC : ADDR_IR;
endmodule
| 6.717531 |
module addrndkey (
input wire [127:0] state_in,
input wire [127:0] key,
output wire [127:0] state_out
);
assign state_out = state_in ^ key;
endmodule
| 8.270668 |
module addroundkeytestbench (
input begintest,
output reg endtest,
output reg dutpassed,
output reg [7:0] shiftrowsout[3:0][3:0],
output reg [7:0] roundkey[3:0][3:0],
input [7:0] addroundkeyout[3:0][3:0]
);
always @(begintest) begin
endtest = 0;
dutpassed = 1;
shiftrowsout[3][3] = 8'd28;
roundkey[3][3] = 8'd74;
#10;
if (addroundkeyout[3][3] != 8'b1010110) begin
dutpassed = 0;
$display("Add Round Key [3][3] Broken");
end
shiftrowsout[2][2] = 8'd6;
roundkey[2][2] = 8'd127;
#10;
if (addroundkeyout[2][2] != 8'b1111001) begin
dutpassed = 0;
$display("Add Round Key Broken");
end
shiftrowsout[1][1] = 8'd195;
roundkey[1][1] = 8'd13;
#10;
if (addroundkeyout[1][1] != 8'b11001110) begin
dutpassed = 0;
$display("Add Round Key Broken");
end
endtest = 1;
end
endmodule
| 7.114493 |
module AddRoundKey (
input Rst,
input Clk,
input En_ARK,
output reg Ry_ARK,
input [127:0] In_ARK,
output reg [127:0] Out_ARK,
input [127:0] Key_ARK
);
integer i;
always @(posedge Clk) begin
if (Rst) begin
Ry_ARK = 0;
Out_ARK = 0;
end else if (En_ARK) begin
for (i = 0; i < 128; i = i + 1) begin
Out_ARK[i] = In_ARK[i] ^ Key_ARK[i];
end
Ry_ARK = 1;
end else Ry_ARK = 0;
end
endmodule
| 7.103156 |
module AddRoundKey_tb ();
reg [127:0] state_in;
reg [127:0] key_in;
wire [127:0] state_out;
AddRoundKey dut (
state_in,
key_in,
state_out
);
initial begin
$dumpfile("AddRoundKey.vcd");
$dumpvars(0, AddRoundKey_tb);
state_in = 128'h3243f6a8885a308d313198a2e0370734;
key_in = 128'h2b7e151628aed2a6abf7158809cf4f3c;
#20
if (state_out == 128'h193de3bea0f4e22b9ac68d2ae9f84808) begin
$display("Test Passed");
end else begin
$display("Test Failed");
end
end
endmodule
| 6.821768 |
module addrselect (
input [2:0] addr, // The set address
input [2:0] aBus, // Adress from buss
output enable // Enabled?
);
assign enable = (aBus == ~addr) ? 1 : 0;
endmodule
| 8.170566 |
module addrunit (
input wire clk_in,
input wire rst_in,
input wire rdy_in,
//from reservation station
input wire [`IDWidth - 1 : 0] rs_addrunit_a_in,
input wire [`IDWidth - 1 : 0] rs_addrunit_vj_in,
input wire [`ROBWidth - 1 : 0] rs_addrunit_dest_in,
input wire [`InstTypeWidth - 1 : 0] rs_addrunit_opcode_in,
//to lbuffer
output wire addrunit_lbuffer_en_out,
output wire [`AddressWidth - 1 : 0] addrunit_lbuffer_a_out,
output wire [`ROBWidth - 1 : 0] addrunit_lbuffer_dest_out,
output wire [`InstTypeWidth - 1 : 0] addrunit_lbuffer_opcode_out,
//from & to reorder buffer
input wire rob_addrunit_rst_in,
output wire [`ROBWidth - 1 : 0] addrunit_rob_h_out,
output wire [`AddressWidth - 1 : 0] addrunit_rob_address_out
);
assign addrunit_lbuffer_dest_out = rs_addrunit_dest_in;
assign addrunit_lbuffer_a_out = rs_addrunit_vj_in + rs_addrunit_a_in;
assign addrunit_lbuffer_opcode_out = rs_addrunit_opcode_in;
assign addrunit_rob_address_out = rs_addrunit_vj_in + rs_addrunit_a_in;
assign addrunit_lbuffer_en_out = `LB <= rs_addrunit_opcode_in && rs_addrunit_opcode_in <= `LHU;
assign addrunit_rob_h_out = rs_addrunit_opcode_in != `NOP ? rs_addrunit_dest_in : `ROBWidth'b0;
endmodule
| 7.228716 |
module Addr_WB (
input wire clk,
bubbleW,
flushW,
input wire [4:0] reg_dest_MEM,
output reg [4:0] reg_dest_WB
);
initial reg_dest_WB = 4'h0;
always @(posedge clk)
if (!bubbleW) begin
if (flushW) reg_dest_WB <= 4'h0;
else reg_dest_WB <= reg_dest_MEM;
end
endmodule
| 6.677724 |
module addr_16bit (
S,
C3,
A,
B,
C_1
);
input [15:0] A, B; //16位被加数A和B
input C_1; //最低位的进位信号
output [15:0] S; //16位和
output C3; //向最高位和=的进位信号
wire C0, C1, C2;
addr_4bit
FA4bit0 (
S[3:0],
C0,
A[3:0],
B[3:0],
C_1
), //调用4位全加器
FA4bit1 (
S[7:4],
C1,
A[7:4],
B[7:4],
C0
),
FA4bit2 (
S[11:8],
C2,
A[11:8],
B[11:8],
C1
),
FA4bit3 (
S[15:12],
C3,
A[15:12],
B[15:12],
C2
);
endmodule
| 6.994005 |
module addr_32bit (
S,
C1,
A,
B,
C_1
);
input [31:0] A, B; //32位被加数A和B
input C_1; //最低位的进位信号
output [31:0] S; //32位和
output C1; //向最高位和=的进位信号
wire C0;
addr_16bit
FA16bit0 (
S[15:0],
C0,
A[15:0],
B[15:0],
C_1
), //调用16位全加器
FA16bit1 (
S[31:16],
C1,
A[31:16],
B[31:16],
C0
);
endmodule
| 7.469937 |
module addr_4bit (
S,
C3,
A,
B,
C_1
);
input [3:0] A, B; //四位被加数A和B
input C_1; //最低位的进位信号
output [3:0] S; //四位和
output C3; //向最高位和=的进位信号
wire C0, C1, C2;
fulladder
FA0 (
S[0],
C0,
A[0],
B[0],
C_1
), //调用1位全加器
FA1 (
S[1],
C1,
A[1],
B[1],
C0
),
FA2 (
S[2],
C2,
A[2],
B[2],
C1
),
FA3 (
S[3],
C3,
A[3],
B[3],
C2
);
endmodule
| 7.052758 |
module adder_4bit (
ina,
inb,
sum,
cout,
cin
);
input [3:0] ina, inb;
input cin;
output [3:0] sum;
output cout;
assign {cout, sum} = ina + inb + cin;
endmodule
| 9.041993 |
module adder_4bit (
ina,
inb,
sum,
cout,
cin
);
input [3:0] ina, inb;
input cin;
output reg [3:0] sum;
output reg cout;
always @(*) {cout, sum} = ina + inb + cin;
endmodule
| 9.041993 |
module addr_BCD_converter (
output reg [16:0] addr,
input [3:0] BCD,
input [9:0] h_cnt,
input [9:0] v_cnt
);
always @* begin
case (BCD)
4'd0: addr = (h_cnt >> 1) % 35 + (v_cnt >> 1) % 35 * 320;
4'd1: addr = (h_cnt >> 1) % 35 + (v_cnt >> 1) % 35 * 320 + 35 * 320;
4'd2: addr = (h_cnt >> 1) % 35 + (v_cnt >> 1) % 35 * 320 + 35 * 320 * 2;
4'd3: addr = (h_cnt >> 1) % 35 + (v_cnt >> 1) % 35 * 320 + 35 * 320 * 3;
4'd4: addr = (h_cnt >> 1) % 35 + (v_cnt >> 1) % 35 * 320 + 35 * 320 * 4;
4'd5: addr = (h_cnt >> 1) % 35 + (v_cnt >> 1) % 35 * 320 + 35 * 320 * 5;
4'd6: addr = (h_cnt >> 1) % 35 + (v_cnt >> 1) % 35 * 320 + 35;
4'd7: addr = (h_cnt >> 1) % 35 + (v_cnt >> 1) % 35 * 320 + 35 + 35 * 320;
4'd8: addr = (h_cnt >> 1) % 35 + (v_cnt >> 1) % 35 * 320 + 35 + 35 * 320 * 2;
4'd9: addr = (h_cnt >> 1) % 35 + (v_cnt >> 1) % 35 * 320 + 35 + 35 * 320 * 3;
4'd10: addr = (h_cnt >> 1) % 35 + (v_cnt >> 1) % 35 * 320 + 35 + 35 * 320 * 4;
4'd11: addr = (h_cnt >> 1) % 35 + (v_cnt >> 1) % 35 * 320 + 35 + 35 * 320 * 5;
4'd12: addr = (h_cnt >> 1) % 35 + (v_cnt >> 1) % 35 * 320 + 35 * 2;
4'd15: addr = 76800;
endcase
end
endmodule
| 6.888468 |
module AddrBusBitLow (
PHI1,
PHI2,
ADX,
Z_ADX,
ADX_ABX,
ABus_out
);
input PHI1;
input PHI2;
input ADX; // Address bus bit
input Z_ADX; // Bit zeroing command
input ADX_ABX;
output ABus_out; // Output value of the address bus terminal
wire n_adx = ~(ADX & ~Z_ADX);
wire abff_out;
AddrBusFF abff (
.phi_load(PHI1),
.phi_keep(PHI2),
.en(ADX_ABX),
.val(n_adx),
.q(abff_out)
);
assign ABus_out = ~abff_out;
endmodule
| 7.743473 |
module AddrBusBit (
PHI1,
PHI2,
ADX,
ADX_ABX,
ABus_out
);
input PHI1;
input PHI2;
input ADX;
input ADX_ABX;
output ABus_out;
wire n_adx = ~(ADX);
wire abff_out;
AddrBusFF abff (
.phi_load(PHI1),
.phi_keep(PHI2),
.en(ADX_ABX),
.val(n_adx),
.q(abff_out)
);
assign ABus_out = ~abff_out;
endmodule
| 6.884705 |
module AddrBusFF (
phi_load,
phi_keep,
en,
val,
q,
nq
);
input phi_load; // PHI phase during which the FF value can be modified
input phi_keep; // PHI phase during which the current value is "holding".
input en; // 1: Writing a value is enabled
input val; // New value
output q; // Current value
output nq; // Current value (complement)
(* keep = "true" *) wire inp;
not (inp, val);
(* keep = "true" *) wire not1out;
not (not1out, floater);
(* keep = "true" *) wire not2out;
not (not2out, not1out);
(* keep = "true" *) wire floater;
bufif1 (floater, not2out, phi_keep);
(* keep = "true" *) wire mid;
bufif1 (mid, inp, phi_load);
bufif1 (floater, mid, en);
assign q = ~not2out;
assign nq = not2out;
endmodule
| 7.108188 |
module controls the addressing of the ring
// buffer storage readout. It receives the last
// address that the rb wrote to, and when there is
// a readout request it starts from that location and
// iterates backwards, outputting which address the rb
// should read out next. It also receives how many words
// are to be read out via howmany_i, and when all requested
// words have been read it flags completion via ro_done_n.
module addr_cntrl #(parameter SIZE=10) (
input wire [SIZE-1:0] offset_in,
input wire [SIZE-1:0] howmany_in,
input wire [SIZE-1:0] ain,
input wire rd_request,
input wire sysclk,
input wire rst,
input wire SPI_done,
output wire [SIZE-1:0] address,
output wire ro_done_n
);
reg [SIZE-1:0] reg_addr;
reg [SIZE-1:0] offset;
reg [SIZE-1:0] howmany;
// where to start readout. only updated if
// not during a ro cycle.
always @(posedge sysclk) begin
if ( rst ) begin
howmany <= {SIZE{1'b0}};
offset <= {SIZE{1'b0}};
end
else if ( ! rd_request) begin
reg_addr <= ain - offset - 1'b1;
howmany <= howmany_in; // - 1'b1; // without the -1 leads to an off-by-one error
offset <= offset_in;
end
else if ( rd_request) begin // readout block
// Wait for SPI to finish current word before moving to next
if (SPI_done) begin
reg_addr <= reg_addr - 1'b1;
howmany <= howmany - 1'b1;
end
end
end
assign address = rd_request ? reg_addr : {SIZE{1'b0}};
assign ro_done_n = |howmany; // enable readout as long as howmany is non-zero
endmodule
| 7.843499 |
module Addr_Color #(
parameter ADDR_WIDTH = 17
) (
input clk,
input rstn,
input en,
output color_finish,
output clear_finish,
output [ADDR_WIDTH-1:0] addr
);
reg [ADDR_WIDTH-1 : 0] cnt;
wire [ADDR_WIDTH-1 : 0] cnt_nxt = cnt < 17'd933 ? cnt + 1'b1 : 17'd107;
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
cnt <= 17'd107;
end else begin
if (en) cnt <= cnt_nxt;
end
end
assign addr = cnt < 17'd119 ? cnt :
cnt < 17'd519 ? 17'd119 :
cnt < 17'd533 ? cnt - 17'd400:
cnt < 17'd933 ? 17'd132 : cnt - 17'd800 ;
assign color_finish = addr == 17'd120;
assign clear_finish = addr == 17'd133;
endmodule
| 8.144665 |
module addr_ctrl (
input wire clk_50M,
input wire rst_n,
output wire [7:0] addr,
input wire [31:0] freqctrl //frequency control word
);
reg [31:0] cnt;
assign addr = cnt[31:24];
always @(posedge clk_50M, negedge rst_n) begin
if (rst_n == 0) cnt <= 0;
else cnt <= cnt + freqctrl;
end
endmodule
| 7.302113 |
module addr_decode (
input [12:0] addr,
output reg rom_en,
output reg ram_en
);
always @(addr)
casex (addr)
13'b1_0xxx_xxxx_xxxx: {rom_en, ram_en} <= 2'b10;
13'b0_0xxx_xxxx_xxxx: {rom_en, ram_en} <= 2'b10;
13'b1_1xxx_xxxx_xxxx: {rom_en, ram_en} <= 2'b01;
default: {rom_en, ram_en} <= 2'b00;
endcase
endmodule
| 7.911742 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module ADDR_FOR_SVM (
input iClk,
input iReady,
output reg [11:0] oADDR,
output reg oDONE
);
reg [3:0] count;
always @(posedge iClk) begin
if (iReady) begin
count <= 4'd0;
oADDR <= 12'd0;
end else begin
count <= count + 1'b1;
if (count == 4'd9) begin
oADDR <= oADDR + 1'b1;
count <= 4'd0;
if (oADDR == 12'd3779) oDONE <= 1'b1;
else oDONE <= 1'b0;
end
end
end
endmodule
| 6.834998 |
module AddrGenerator #(
// ADDR_WIDTH must not be greater than 67
parameter ADDR_WIDTH = 27
) (
input wire clk,
input wire i_rst,
input wire i_wen,
input wire i_ren,
output wire [ADDR_WIDTH-1 : 0] o_waddr,
output wire [ADDR_WIDTH-1 : 0] o_raddr
);
reg [ADDR_WIDTH-4 : 0] waddr;
reg [ADDR_WIDTH-4 : 0] raddr;
assign o_waddr = {waddr, 3'b000};
assign o_raddr = {raddr, 3'b000};
always @(posedge clk) begin
if (i_rst) begin
waddr <= 0;
raddr <= 0;
end else begin
if (i_wen) begin
waddr <= waddr + 1;
end
if (i_ren) begin
raddr <= raddr + 1;
end
end
end
endmodule
| 8.779836 |
module addr_gen_integer (
input wire rst_n,
input wire clk,
input wire clr,
input wire en_sw,
input wire en_tb,
input wire [11:0] init_mvec, // {w, h}
output reg [11:0] addr_sw,
output reg [ 7:0] addr_tb
);
reg en_sw_pre;
reg [4:0] cnt_h;
reg [4:0] cnt_w;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
addr_sw <= 0;
cnt_h <= 0;
cnt_w <= 0;
end else begin
if (clr) begin
addr_sw <= #1 0;
cnt_h <= #1 0;
cnt_w <= #1 0;
end else if (en_sw && ~en_sw_pre) begin
addr_sw <= #1 init_mvec;
cnt_h <= #1 0;
cnt_w <= #1 0;
end else if (en_sw) begin
if (cnt_h < 17) begin
addr_sw <= #1{addr_sw[11:6], addr_sw[5:0] + 6'd1};
cnt_h <= #1 cnt_h + 1;
end else begin
addr_sw <= #1{addr_sw[11:6] + 6'd1, addr_sw[5:0] - 6'd17};
cnt_h <= #1 0;
cnt_w <= #1 cnt_w + 1;
end
end
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) addr_tb <= 0;
else if (clr) addr_tb <= #1 0;
else if (en_tb) addr_tb <= #1 addr_tb + 1;
end
always @(posedge clk) en_sw_pre <= #1 en_sw;
endmodule
| 6.578557 |
module Addr_Ini #(
parameter ADDR_WIDTH = 17
) (
input clk,
input rstn,
input cnt_en,
output reg Initial_finish,
output [ADDR_WIDTH-1 : 0] addr
);
reg [ADDR_WIDTH-1 : 0] cnt;
wire [ADDR_WIDTH-1 : 0] cnt_nxt = cnt + 1'b1;
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
cnt <= {ADDR_WIDTH{1'b0}};
end else begin
if (cnt_en) cnt <= cnt_nxt;
else cnt <= cnt;
end
end
assign addr = (cnt <= 17'd105) ? cnt : (cnt < 17'd76906 ? 17'd106 : cnt - 17'd76800);
always @(posedge clk, negedge rstn) begin
if (!rstn) begin
Initial_finish = 1'b0;
end else begin
if (addr == 17'd107) begin
Initial_finish = 1'b1;
end
end
end
endmodule
| 7.405961 |
module test;
localparam sc_100_k = 13'h1148; // 00
localparam sc_10_k = 13'h1149; // 03
localparam sc_1_k = 13'h114a; // 00
localparam sc_100 = 13'h114b; // 02
localparam sc_10 = 13'h114c; // 09
localparam sc_1 = 13'h114d; // 00
reg reset = 1;
/* Make a reset that pulses once. */
initial begin
$dumpfile("test.vcd");
$dumpvars(0, test);
#8;
reset <= 0;
#8;
address <= sc_10_k;
re <= 0;
data_write <= 8'h04;
start <= 1;
wait (ready == 0);
start <= 0;
wait (ready == 1);
address <= sc_1_k;
re <= 0;
data_write <= 8'h08;
start <= 1;
wait (ready == 0);
start <= 0;
wait (ready == 1);
#8;
$finish;
end
reg clk = 0;
always #1 clk = !clk;
reg re = 0;
reg start = 0;
wire ready;
reg [12:0] address = 0;
reg [7:0] data_write = 0;
wire [7:0] sram_data_pins;
wire [12:0] sram_address;
wire sram_n_write, sram_n_ce1;
// addr listener
top top_inst (
.clk(clk),
.sram_data_pins(sram_data_pins),
.sram_address(sram_address),
.sram_n_write(sram_n_write),
.sram_n_ce1(sram_n_ce1)
);
// sram driver
sram_driver #(
.WAIT_TIME(3)
) sram_driver_0 (
.clk (clk),
.reset(reset),
// module interface
.ready(ready),
.re(re),
.start(start),
.address(address),
.data_write(data_write),
// sram control pins
.sram_address(sram_address),
.sram_data_write(sram_data_pins),
.n_ce1(sram_n_ce1),
.n_we(sram_n_write)
);
endmodule
| 6.675276 |
module addr_load (
input [31:0] BusA,
input [31:0] imm,
output reg [31:0] Address
);
always @(*) begin
Address = BusA + imm;
Address = (Address[31:28] == 4'ha || Address[31:28] == 4'hb) ? Address - 32'ha0000000 : Address;
end
endmodule
| 7.915335 |
module addr_manager #(
parameter ADDR_WIDTH = 16,
parameter ADDR_PAGE_NUM_LOG = 12,
parameter DATA_WIDTH = 8,
parameter MODE_INIT = 0
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
//from controller
input table_read_req,
input table_write_req,
input [ADDR_PAGE_NUM_LOG - 1:0] table_write_addr,
//to controller
output reg [ADDR_PAGE_NUM_LOG - 1:0] table_read_addr,
output reg [ADDR_PAGE_NUM_LOG - 1:0] table_read_last_addr,
output reg table_empty,
//from ram
input [DATA_WIDTH - 1:0] ram_read_data
);
reg read_req_buffer1, read_req_buffer2;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
read_req_buffer1 <= 'b0;
read_req_buffer2 <= 'b0;
end else begin
read_req_buffer1 <= table_read_req;
read_req_buffer2 <= table_read_req1;
end
end
reg [2 * DATA_WIDTH - 1:0] head_point_temp;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
head_point_temp <= 'b0;
end else begin
if (read_req_buffer1) begin
head_point_temp[DATA_WIDTH-1:0] <= ram_read_data;
end else if (read_req_buffer2) begin
head_point_temp[2*DATA_WIDTH-1:DATA_WIDTH] <= ram_read_data;
end
end
end
assign table_read_addr = head_point_temp[ADDR_PAGE_NUM_LOG-1:0];
reg [ADDR_PAGE_NUM_LOG - 1:0] table_read_last_addr;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
table_read_last_addr <= 'b0;
end else if (table_write_req) begin
table_read_last_addr <= table_write_addr;
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
table_empty <= 1'(MODE_INIT);
end else if (table_read_addr == table_read_last_addr) begin
table_empty <= 1'b1;
end else begin
table_empty <= 'b0;
end
end
endmodule
| 7.510022 |
module addr_mux (
addr,
d_in_0,
d_in_1,
d_out
);
input addr;
input [`WIDTH-1:0] d_in_0, d_in_1;
output reg [`WIDTH-1:0] d_out;
always @* begin
if (addr) d_out = d_in_1;
else d_out = d_in_0;
end
endmodule
| 7.601012 |
module: addr_mux4
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module addr_mux4_tb;
// Inputs
reg [9:0] data0;
reg [9:0] data1;
reg [9:0] data2;
reg [9:0] data3;
reg [1:0] select;
// Outputs
wire [9:0] dataOut;
// Instantiate the Unit Under Test (UUT)
addr_mux4 uut (
.data0(data0),
.data1(data1),
.data2(data2),
.data3(data3),
.select(select),
.dataOut(dataOut)
);
initial begin
// Initialize Inputs
data0 = 0;
data1 = 0;
data2 = 0;
data3 = 0;
select = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
data3 = 10'd512;
select = 3;
end
endmodule
| 6.87286 |
module Addr_Parameter (
input clk,
input rstn,
input en,
output reg [15:0] col_start,
output reg [15:0] row_start
);
wire [15:0] col_start_nxt = (col_start == 16'd220) ? 16'd0 : col_start + 16'd20;
wire [15:0] row_start_nxt = ( col_start == 16'd220 ) ? ( row_start == 16'd300 ? 16'd0 : row_start + 16'd20 ): row_start;
always @(posedge clk, negedge rstn) begin
if (!rstn) begin
col_start <= 16'b0;
row_start <= 16'b0;
end else begin
if (en) begin
col_start <= col_start_nxt;
row_start <= row_start_nxt;
end
end
end
endmodule
| 7.728704 |
module addr_parse #(
parameter BYTES_PER_LINE = 16,
parameter NUM_LINE = 256,
parameter OFFSET_WIDTH = $clog2(BYTES_PER_LINE),
parameter INDEX_WIDTH = $clog2(NUM_LINE),
parameter TAG_WIDTH = 32 - OFFSET_WIDTH - INDEX_WIDTH
) (
input [31:0] addr,
output [INDEX_WIDTH-1:0] index,
output [TAG_WIDTH-1:0] tag,
output [OFFSET_WIDTH-1:0] offset
);
assign index = addr[(31-TAG_WIDTH)-:INDEX_WIDTH];
assign tag = addr[31-:TAG_WIDTH];
assign offset = addr[0+:OFFSET_WIDTH];
endmodule
| 7.699279 |
module addr_reg (
clk,
reset,
data_on_ar,
ar_on_bus,
load_ar
);
input clk;
input reset;
input load_ar;
input [7:0] data_on_ar;
output [7:0] ar_on_bus;
reg [7:0] ar_on_bus;
always @(posedge clk) begin
if (reset) ar_on_bus <= 8'd0;
else begin
if (load_ar) ar_on_bus <= data_on_ar;
end
end
endmodule
| 6.602304 |
module addr_shift (
addr_in,
addr_out
);
input [31:0] addr_in;
output [31:0] addr_out;
assign addr_out = addr_in << 2;
endmodule
| 8.446049 |
module \$add (
A,
B,
Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_BITS_CONNMAP_ = 0;
parameter _TECHMAP_CONNMAP_A_ = 0;
parameter _TECHMAP_CONNMAP_B_ = 0;
wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH < Y_WIDTH ||
_TECHMAP_CONNMAP_A_ != _TECHMAP_CONNMAP_B_;
assign Y = A << 1;
endmodule
| 7.120414 |
module addsl2 (
input [31:0] OP,
input [31:0] OP1,
output reg [31:0] OPS
);
always @* begin
OPS <= OP + OP1;
end
endmodule
| 7.084656 |
module AddState (
input [1:0] idle_Allign2,
input [35:0] cout_Allign2,
input [35:0] zout_Allign2,
input [31:0] sout_Allign2,
input [1:0] modeout_Allign2,
input operationout_Allign2,
input NatLogFlagout_Allign2,
input [7:0] InsTag_Allign2,
input clock,
output reg [1:0] idle_AddState,
output reg [31:0] sout_AddState,
output reg [1:0] modeout_AddState,
output reg operationout_AddState,
output reg NatLogFlagout_AddState,
output reg [27:0] sum_AddState,
output reg [7:0] InsTag_AddState
);
parameter mode_circular = 2'b01, mode_linear = 2'b00, mode_hyperbolic = 2'b11;
parameter no_idle = 2'b00, allign_idle = 2'b01, put_idle = 2'b10;
wire z_sign;
wire [7:0] z_exponent;
wire [26:0] z_mantissa;
wire c_sign;
wire [7:0] c_exponent;
wire [26:0] c_mantissa;
assign z_sign = zout_Allign2[35];
assign z_exponent = zout_Allign2[34:27] - 127;
assign z_mantissa = {zout_Allign2[26:0]};
assign c_sign = cout_Allign2[35];
assign c_exponent = cout_Allign2[34:27] - 127;
assign c_mantissa = {cout_Allign2[26:0]};
always @(posedge clock) begin
InsTag_AddState <= InsTag_Allign2;
idle_AddState <= idle_Allign2;
modeout_AddState <= modeout_Allign2;
operationout_AddState <= operationout_Allign2;
NatLogFlagout_AddState <= NatLogFlagout_Allign2;
if (idle_Allign2 != put_idle) begin
sout_AddState[30:23] <= c_exponent;
sout_AddState[22:0] <= 0;
if (c_sign == z_sign) begin
sum_AddState <= c_mantissa + z_mantissa;
sout_AddState[31] <= c_sign;
end else begin
if (c_mantissa >= z_mantissa) begin
sum_AddState <= c_mantissa - z_mantissa;
sout_AddState[31] <= c_sign;
end else begin
sum_AddState <= z_mantissa - c_mantissa;
sout_AddState[31] <= z_sign;
end
end
end else begin
sout_AddState <= sout_Allign2;
sum_AddState <= 0;
end
end
endmodule
| 7.327793 |
module addsub #(
parameter DATAWIDTH = 6
) (
input AddSub,
input [DATAWIDTH-1:0] A,
input [DATAWIDTH-1:0] BusWires,
output reg [DATAWIDTH-1:0] Sum
);
always @(*) begin
if (!AddSub) Sum = A + BusWires;
else Sum = A - BusWires;
end
endmodule
| 6.882069 |
module AddSub1b (
input wire A,
B,
Ctrl,
Ci,
output wire S,
Co
);
wire tmp;
assign tmp = B ^ Ctrl;
Adder1b add (
.A (A),
.B (tmp),
.Ci(Ci),
.S (S),
.Co(Co)
);
endmodule
| 7.315286 |
module addsub32 (
a,
b,
sub,
s,
co,
ofl,
sign
);
input [31:0] a, b;
input sub;
output [31:0] s;
output co, ofl, sign;
reg ofl = 1'b0;
assign sign = s[31];
always @(a or b or sub) begin
if (a[31] == b[31]) begin
if (s[31] != a[31]) begin
ofl = 1'b1;
end
end
end
cla32 as32 (
a,
b ^ {32{sub}},
sub,
s,
co
);
endmodule
| 6.768353 |
module AddSub32bFlag (
input [31:0] A,
input [31:0] B,
input Ci,
input Ctrl,
output [31:0] S,
output CF,
OF,
ZF,
SF,
PF // 符号SF、进位CF、溢出OF、零标志ZF、奇偶PF
);
wire add_cf, sub_cf, sub_sf, co;
wire [31:0] c;
AddSub1b aS0 (
.A(A[0]),
.B(B[0]),
.Ci(Ctrl ^ Ci),
.S(S[0]),
.Co(c[0]),
.Ctrl(Ctrl)
);
AddSub1b aS1 (
.A(A[1]),
.B(B[1]),
.Ci(c[0]),
.S(S[1]),
.Co(c[1]),
.Ctrl(Ctrl)
);
AddSub1b aS2 (
.A(A[2]),
.B(B[2]),
.Ci(c[1]),
.S(S[2]),
.Co(c[2]),
.Ctrl(Ctrl)
);
AddSub1b aS3 (
.A(A[3]),
.B(B[3]),
.Ci(c[2]),
.S(S[3]),
.Co(c[3]),
.Ctrl(Ctrl)
);
AddSub1b aS4 (
.A(A[4]),
.B(B[4]),
.Ci(c[3]),
.S(S[4]),
.Co(c[4]),
.Ctrl(Ctrl)
);
AddSub1b aS5 (
.A(A[5]),
.B(B[5]),
.Ci(c[4]),
.S(S[5]),
.Co(c[5]),
.Ctrl(Ctrl)
);
AddSub1b aS6 (
.A(A[6]),
.B(B[6]),
.Ci(c[5]),
.S(S[6]),
.Co(c[6]),
.Ctrl(Ctrl)
);
AddSub1b aS7 (
.A(A[7]),
.B(B[7]),
.Ci(c[6]),
.S(S[7]),
.Co(c[7]),
.Ctrl(Ctrl)
);
AddSub1b aS8 (
.A(A[8]),
.B(B[8]),
.Ci(c[7]),
.S(S[8]),
.Co(c[8]),
.Ctrl(Ctrl)
);
AddSub1b aS9 (
.A(A[9]),
.B(B[9]),
.Ci(c[8]),
.S(S[9]),
.Co(c[9]),
.Ctrl(Ctrl)
);
AddSub1b aS10 (
.A(A[10]),
.B(B[10]),
.Ci(c[9]),
.S(S[10]),
.Co(c[10]),
.Ctrl(Ctrl)
);
AddSub1b aS11 (
.A(A[11]),
.B(B[11]),
.Ci(c[10]),
.S(S[11]),
.Co(c[11]),
.Ctrl(Ctrl)
);
AddSub1b aS12 (
.A(A[12]),
.B(B[12]),
.Ci(c[11]),
.S(S[12]),
.Co(c[12]),
.Ctrl(Ctrl)
);
AddSub1b aS13 (
.A(A[13]),
.B(B[13]),
.Ci(c[12]),
.S(S[13]),
.Co(c[13]),
.Ctrl(Ctrl)
);
AddSub1b aS14 (
.A(A[14]),
.B(B[14]),
.Ci(c[13]),
.S(S[14]),
.Co(c[14]),
.Ctrl(Ctrl)
);
AddSub1b aS15 (
.A(A[15]),
.B(B[15]),
.Ci(c[14]),
.S(S[15]),
.Co(c[15]),
.Ctrl(Ctrl)
);
AddSub1b aS16 (
.A(A[16]),
.B(B[16]),
.Ci(c[15]),
.S(S[16]),
.Co(c[16]),
.Ctrl(Ctrl)
);
AddSub1b aS17 (
.A(A[17]),
.B(B[17]),
.Ci(c[16]),
.S(S[17]),
.Co(c[17]),
.Ctrl(Ctrl)
);
AddSub1b aS18 (
.A(A[18]),
.B(B[18]),
.Ci(c[17]),
.S(S[18]),
.Co(c[18]),
.Ctrl(Ctrl)
);
AddSub1b aS19 (
.A(A[19]),
.B(B[19]),
.Ci(c[18]),
.S(S[19]),
.Co(c[19]),
.Ctrl(Ctrl)
);
AddSub1b aS20 (
.A(A[20]),
.B(B[20]),
.Ci(c[19]),
.S(S[20]),
.Co(c[20]),
.Ctrl(Ctrl)
);
AddSub1b aS21 (
.A(A[21]),
.B(B[21]),
.Ci(c[20]),
.S(S[21]),
.Co(c[21]),
.Ctrl(Ctrl)
);
AddSub1b aS22 (
.A(A[22]),
.B(B[22]),
.Ci(c[21]),
.S(S[22]),
.Co(c[22]),
.Ctrl(Ctrl)
);
AddSub1b aS23 (
.A(A[23]),
.B(B[23]),
.Ci(c[22]),
.S(S[23]),
.Co(c[23]),
.Ctrl(Ctrl)
);
AddSub1b aS24 (
.A(A[24]),
.B(B[24]),
.Ci(c[23]),
.S(S[24]),
.Co(c[24]),
.Ctrl(Ctrl)
);
AddSub1b aS25 (
.A(A[25]),
.B(B[25]),
.Ci(c[24]),
.S(S[25]),
.Co(c[25]),
.Ctrl(Ctrl)
);
AddSub1b aS26 (
.A(A[26]),
.B(B[26]),
.Ci(c[25]),
.S(S[26]),
.Co(c[26]),
.Ctrl(Ctrl)
);
AddSub1b aS27 (
.A(A[27]),
.B(B[27]),
.Ci(c[26]),
.S(S[27]),
.Co(c[27]),
.Ctrl(Ctrl)
);
AddSub1b aS28 (
.A(A[28]),
.B(B[28]),
.Ci(c[27]),
.S(S[28]),
.Co(c[28]),
.Ctrl(Ctrl)
);
AddSub1b aS29 (
.A(A[29]),
.B(B[29]),
.Ci(c[28]),
.S(S[29]),
.Co(c[29]),
.Ctrl(Ctrl)
);
AddSub1b aS30 (
.A(A[30]),
.B(B[30]),
.Ci(c[29]),
.S(S[30]),
.Co(c[30]),
.Ctrl(Ctrl)
);
AddSub1b aS31 (
.A(A[31]),
.B(B[31]),
.Ci(c[30]),
.S(S[31]),
.Co(c[31]),
.Ctrl(Ctrl)
);
assign CF = Ctrl ^ c[31];
assign SF = S[31];
assign OF = c[30] ^ c[31];
assign PF = ^S;
assign ZF = ~|S;
endmodule
| 7.882733 |
module addsub4 (
input wire [3:0] a,
input wire [3:0] b,
input wire e,
output wire [3:0] s,
output wire cf
);
wire [4:0] c;
wire [3:0] bx;
assign bx = b ^ {4{e}};
assign c[0] = e;
assign s = a ^ bx ^ c[3:0];
assign c[4:1] = a & bx | c[3:0] & (a ^ bx);
assign cf = c[4];
endmodule
| 7.146674 |
module AddSub4b (
input wire [3:0] A,
input wire [3:0] B,
input wire Ci, // if subtraction, it is borrow
input wire Ctrl, // [mode] 0: addup; 1: subtraction
output wire [3:0] S,
output wire Co
);
wire c1, c2, c3;
AddSub1b aS1 (
.A(A[0]),
.B(B[0]),
.Ci(Ctrl ^ Ci),
.S(S[0]),
.Co(c1),
.Ctrl(Ctrl)
);
AddSub1b aS2 (
.A(A[1]),
.B(B[1]),
.Ci(c1),
.S(S[1]),
.Co(c2),
.Ctrl(Ctrl)
);
AddSub1b aS3 (
.A(A[2]),
.B(B[2]),
.Ci(c2),
.S(S[2]),
.Co(c3),
.Ctrl(Ctrl)
);
AddSub1b aS4 (
.A(A[3]),
.B(B[3]),
.Ci(c3),
.S(S[3]),
.Co(Co),
.Ctrl(Ctrl)
);
endmodule
| 6.637786 |
module AddSub4bFlag (
input [3:0] A,
input [3:0] B,
input Ci,
input Ctrl,
output [3:0] S,
output CF,
OF,
ZF,
SF,
PF // 符号SF、进位CF、溢出OF、零标志ZF、奇偶PF
);
wire add_cf, sub_cf, sub_sf, co;
wire c0, c1, c2, c3;
AddSub1b aS0 (
.A(A[0]),
.B(B[0]),
.Ci(Ctrl ^ Ci),
.S(S[0]),
.Co(c0),
.Ctrl(Ctrl)
);
AddSub1b aS1 (
.A(A[1]),
.B(B[1]),
.Ci(c0),
.S(S[1]),
.Co(c1),
.Ctrl(Ctrl)
);
AddSub1b aS2 (
.A(A[2]),
.B(B[2]),
.Ci(c1),
.S(S[2]),
.Co(c2),
.Ctrl(Ctrl)
);
AddSub1b aS3 (
.A(A[3]),
.B(B[3]),
.Ci(c2),
.S(S[3]),
.Co(c3),
.Ctrl(Ctrl)
);
assign CF = Ctrl ^ c3;
assign SF = S[3];
assign OF = c2 ^ c3;
assign PF = ^S;
assign ZF = ~|S;
endmodule
| 7.852344 |
module AddSub4bFlag_tb ();
reg [3:0] A;
reg [3:0] B;
reg Ci;
reg Ctrl;
wire [3:0] S;
wire CF, OF, ZF, SF, PF; // 符号SF、进位CF、溢出OF、零标志ZF、奇偶PF
AddSub4bFlag uut (
A,
B,
Ci,
Ctrl,
S,
CF,
OF,
ZF,
SF,
PF
);
initial begin
$dumpfile("AddSub4bFlag_tb.vcd");
$dumpvars(0, AddSub4bFlag_tb);
A = 4'h1;
B = 4'h7;
Ci = 0;
Ctrl = 0;
#10;
A = 4'h3;
B = 4'hf;
Ci = 0;
Ctrl = 1;
#10;
end
endmodule
| 6.844324 |
module addsub4b_tb;
// Inputs
reg [3:0] A;
reg [3:0] B;
reg add_sub;
// Outputs
wire [3:0] R;
wire Co;
// Instantiate the Unit Under Test (UUT)
addsub4b uut (
.add_sub(add_sub),
.A3(A[3]),
.A2(A[2]),
.A1(A[1]),
.A0(A[0]),
.B3(B[3]),
.B2(B[2]),
.B1(B[1]),
.B0(B[0]),
.Co(Co),
.R3(R[3]),
.R2(R[2]),
.R1(R[1]),
.R0(R[0])
);
initial begin
// Add stimulus here
#100;
A = 4'b0000;
B = 4'b0000;
add_sub = 0;
#100;
A = 4'b0000;
B = 4'b0001;
add_sub = 0;
#100;
A = 4'b1110;
B = 4'b1100;
add_sub = 1;
#100;
A = 4'b1010;
B = 4'b0011;
add_sub = 0;
#100;
A = 4'b1111;
B = 4'b1111;
add_sub = 1;
#100;
$stop;
end
endmodule
| 6.810319 |
module addsub4_structural (
result,
carry_out,
subtract,
a,
b,
carry_in
);
input [3:0] a, b;
input carry_in; // input carry or borrow
input subtract; // subtract: 1, subtract; 0, add
output [3:0] result;
output carry_out;
wire [2:0] carry_borrow;
wire [3:0] b_subtract;
wire carry_borrow_in;
xor xor0 (b_subtract[0], b[0], subtract);
xor xor1 (b_subtract[1], b[1], subtract);
xor xor2 (b_subtract[2], b[2], subtract);
xor xor3 (b_subtract[3], b[3], subtract);
xor xor4 (carry_borrow_in, carry_in, subtract);
fulladder_structural fas1 (
result[0],
carry_borrow[0],
a[0],
b_subtract[0],
carry_borrow_in
);
fulladder_structural fas2 (
result[1],
carry_borrow[1],
a[1],
b_subtract[1],
carry_borrow[0]
);
fulladder_structural fas3 (
result[2],
carry_borrow[2],
a[2],
b_subtract[2],
carry_borrow[1]
);
fulladder_structural fas4 (
result[3],
carry_out,
a[3],
b_subtract[3],
carry_borrow[2]
);
endmodule
| 6.51423 |
module addsub4_structural_test;
reg [3:0] a, b;
reg carry_in;
reg subtract;
wire [3:0] result;
wire carry_out;
addsub4_structural ass1 (
result,
carry_out,
subtract,
a,
b,
carry_in
);
initial begin
a = 4'b0000;
b = 4'b0000;
carry_in = 1;
subtract = 0;
#1 a = 4'b0001;
b = 4'b0001;
carry_in = 1;
subtract = 0;
#1 a = 4'b0011;
b = 4'b0001;
carry_in = 1;
subtract = 0;
#1 a = 4'b0111;
b = 4'b0001;
carry_in = 1;
subtract = 0;
#1 a = 4'b1111;
b = 4'b0001;
carry_in = 1;
subtract = 0;
#1 a = 4'b0001;
b = 4'b0001;
carry_in = 1;
subtract = 1;
#1 a = 4'b0011;
b = 4'b0001;
carry_in = 1;
subtract = 1;
#1 a = 4'b0111;
b = 4'b0001;
carry_in = 1;
subtract = 1;
#1 a = 4'b1111;
b = 4'b0001;
carry_in = 1;
subtract = 1;
#1 a = 4'b0001;
b = 4'b0001;
carry_in = 0;
subtract = 1;
#1 a = 4'b0011;
b = 4'b0001;
carry_in = 0;
subtract = 1;
#1 a = 4'b0111;
b = 4'b0001;
carry_in = 0;
subtract = 1;
#1 a = 4'b1111;
b = 4'b0001;
carry_in = 0;
subtract = 1;
#1 a = 4'b0000;
b = 4'b0001;
carry_in = 0;
subtract = 1;
#1 a = 4'b0000;
b = 4'b0011;
carry_in = 0;
subtract = 1;
#1 a = 4'b0000;
b = 4'b0111;
carry_in = 0;
subtract = 1;
#1 a = 4'b0000;
b = 4'b1111;
carry_in = 0;
subtract = 1;
#1 $finish;
end
initial begin
$monitor($time, "\ta=%b", a, "\tb=%b", b, "\tcin=%b", carry_in, "\tsubtract=%b", subtract,
"\tresult=%b", result, "\tcout=%b", carry_out);
$dumpfile("addsub4_structural_test.vcd");
$dumpvars;
end
endmodule
| 6.51423 |
module AddSubC #(
////////////////////////////////////////////////////
// Parameters
parameter width = 4 //input bit width
) (
////////////////////////////////////////////////////
// Ports
input SubEn, //Subustractor Enable
input [width-1:0] A,
B,
output reg [width-1:0] S,
output reg Carry
);
////////////////////////////////////////////////////
// Net
wire [width-1:0] wFAB; //Full Adder B input wire
wire [ width:0] C; //Carry
wire [width-1:0] wS;
assign C[0] = SubEn;
generate
genvar i;
for (i = 0; i < width; i = i + 1) begin : loop
assign wFAB[i] = (SubEn) ? ~B[i] : B[i];
FA a (
.A (A[i]),
.B (wFAB[i]),
.Ci(C[i]),
.S (wS[i]),
.Co(C[i+1])
);
end
endgenerate
always @(posedge Clock or posedge Reset) begin
if (Reset) begin
Carry <= 1'b0;
S <= 0;
end else begin
Carry <= C[width];
S <= wS;
end
end
endmodule
| 7.725658 |
module FA
////////////////////////////////////////////////////
// Ports
(
input A,
B,
Ci,
output S,
Co
);
wire exAB = A ^ B;
assign S = exAB ^ Ci;
assign Co = (A & B) | (exAB & Ci);
endmodule
| 7.055788 |
module addSubNbits #(
parameter N = 4
) (
input wire [N:0] x,
input wire [N:0] y,
input sel,
output wire [N+1:0] z
);
assign z = (sel == 0) ? {1'b0, x} + {1'b0, y} : {1'b0, x} - {1'b0, y};
endmodule
| 7.2424 |
module addSubNbits2 #(
parameter N = 4
) (
input wire [N:0] x,
input wire [N:0] y,
input sel,
output reg [N+1:0] z
);
always @(*) begin
if (sel == 0) z = {1'b0, x} + {1'b0, y};
else z = {1'b0, x} - {1'b0, y};
end
always @(*) begin
case (sel)
1'b0: z = {1'b0, x} + {1'b0, y};
1'b1: z = {1'b0, x} - {1'b0, y};
default: z = 0;
endcase
end
endmodule
| 6.868045 |
module AddSub #(
////////////////////////////////////////////////////
// Parameters
parameter width = 4 //input bit width
) (
////////////////////////////////////////////////////
// Ports
input SubEn, //Subustractor Enable
input [width-1:0] A,
B,
output [width:0] S
);
////////////////////////////////////////////////////
// Net
wire [width-1:0] wFAB; //Full Adder B input wire
wire [ width:0] C; //Carry
assign C[0] = SubEn;
assign S[width] = C[width];
generate
genvar i;
for (i = 0; i < width; i = i + 1) begin : loop
assign wFAB[i] = (SubEn) ? ~B[i] : B[i];
FA a (
.A (A[i]),
.B (wFAB[i]),
.Ci(C[i]),
.S (S[i]),
.Co(C[i+1])
);
end
endgenerate
endmodule
| 7.718964 |
module FA
////////////////////////////////////////////////////
// Ports
(
input A,
B,
Ci,
output S,
Co
);
wire exAB = A ^ B;
assign S = exAB ^ Ci;
assign Co = (A & B) | (exAB & Ci);
endmodule
| 7.055788 |
module RoundRawFNToRecFN (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [26:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [32:0] io_out
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_sign; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [9:0] roundAnyRawFNToRecFN_io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [26:0] roundAnyRawFNToRecFN_io_in_sig; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [2:0] roundAnyRawFNToRecFN_io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [32:0] roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 307:15]
RoundAnyRawFNToRecFN roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala 307:15]
.io_invalidExc(roundAnyRawFNToRecFN_io_invalidExc),
.io_in_isNaN(roundAnyRawFNToRecFN_io_in_isNaN),
.io_in_isInf(roundAnyRawFNToRecFN_io_in_isInf),
.io_in_isZero(roundAnyRawFNToRecFN_io_in_isZero),
.io_in_sign(roundAnyRawFNToRecFN_io_in_sign),
.io_in_sExp(roundAnyRawFNToRecFN_io_in_sExp),
.io_in_sig(roundAnyRawFNToRecFN_io_in_sig),
.io_roundingMode(roundAnyRawFNToRecFN_io_roundingMode),
.io_out(roundAnyRawFNToRecFN_io_out)
);
assign io_out = roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 315:23]
assign roundAnyRawFNToRecFN_io_invalidExc = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 310:44]
assign roundAnyRawFNToRecFN_io_in_isNaN = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isInf = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isZero = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sign = io_in_sign; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sExp = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sig = io_in_sig; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_roundingMode = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 313:44]
endmodule
| 6.992477 |
module AddSubPE_tb;
reg clock, reset;
reg [31:0] in_0;
reg [31:0] in_1;
reg op_type;
reg use_int;
reg tininess;
reg [ 2:0] rounding;
wire [31:0] out;
// PERIOD
localparam period = 5;
AddSubPE UUT (
.clock(clock),
.reset(reset),
.io_use_int(use_int),
.io_op(op_type),
.io_rounding(rounding),
.io_tininess(tininess),
.io_in_0(in_0),
.io_in_1(in_1),
.io_out(out)
);
// DUMPFILE
initial begin
$dumpfile("AddSubPE_tb.vcd");
$dumpvars(0, AddSubPE_tb);
end
// CLOCK
always begin
clock = 1'b1;
#1;
clock = 1'b0;
#1;
end
// task for RESET
task init_RESET;
begin
reset = 1;
#1;
reset = 0;
#1;
end
endtask
// task for INT32
task check_INT;
begin
op_type = 1'b1;
use_int = 1'b1;
tininess = 1'b0;
rounding = 3'b100;
in_0 = 32'b00000000000000000000000000010111; // 23
in_1 = 32'b00000000000000000000000000001011; // 11
#(period);
end
endtask
// task for FP32
task check_FP;
begin
op_type = 1'b1;
use_int = 1'b0;
tininess = 1'b1;
rounding = 3'b100;
in_0 = 32'b01000001101110000000000000000000; // 23
in_1 = 32'b01000001001100000000000000000000; // 11
#(period);
end
endtask
// task for OUT
task check_OUT;
input [31:0] out_data;
begin
$display($time, "[debug] check output ......");
if (out == out_data) begin
$display($time, "[debug] TEST PASS !");
end else begin
$display($time, "[debug] TEST FAIL !");
end
$display("[debug] out(binary) = %b && out(decimal) = %d", out, out);
end
endtask
// MONITOR
initial //always
begin
#(period);
$monitor("[monitor] time = %g\n", $time);
$display("[debug] out(binary) = %b && out(decimal) = %d", out, out);
end
// RUN TEST
initial begin
$display($time, " << start simulation >>");
init_RESET();
@(posedge clock);
check_INT();
check_OUT(32'b00000000000000000000000000001100);
@(posedge clock);
check_FP();
check_OUT(32'b01000001010000000000000000000000);
#30;
$display($time, " << end simulation >>");
//$stop;
$finish;
end
endmodule
| 7.323087 |
module AddSubtract (
input wire [num_bits_1-1:0] in1,
input wire [num_bits_2-1:0] in2,
input wire [num_bits_2-1:0] in3,
input wire clock,
input wire reset_n,
output reg [num_bits_1-1:0] out
);
initial begin
out = 0;
end
parameter num_bits_1 = 16;
parameter num_bits_2 = 12;
always @(posedge clock or negedge reset_n) begin : add
if (~reset_n) out = 0;
else out = in1 + in2 - in3;
end
endmodule
| 7.858811 |
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