code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module rcv_counter_tail (
clk,
n_rst,
count_en2,
tail_ptr,
tail_tog
);
output [1:0] tail_ptr;
input clk, n_rst, count_en2;
output tail_tog;
wire temp_tail_tog, n3, n2;
DFFSR tail_tog_reg (
.D (temp_tail_tog),
.CLK(clk),
.R (n_rst),
.S (1'b1),
.Q (tail_tog... | 6.536109 |
module rcv_counter_idx (
clk,
n_rst,
count_en1,
sync_clr,
tail_side
);
output [1:0] tail_side;
input clk, n_rst, count_en1, sync_clr;
fifo_flex_counter_NUM_CNT_BITS2_1 FLEXCNT (
.clk(clk),
.n_rst(n_rst),
.clear(sync_clr),
.count_enable(count_en1),
.rollover_val(... | 7.471843 |
module rcv_fifo (
clk,
n_rst,
HWDATA,
rcv_deq,
rcv_enq_word,
fix_error,
rcv_fifo_out,
full,
empty,
framing_error
);
input [31:0] HWDATA;
output [127:0] rcv_fifo_out;
input clk, n_rst, rcv_deq, rcv_enq_word, fix_error;
output full, empty, framing_error;
wire count_en1, c... | 6.577353 |
module tx_counter_idx (
clk,
n_rst,
count_en1,
head_side
);
output [1:0] head_side;
input clk, n_rst, count_en1;
fifo_flex_counter_NUM_CNT_BITS2_0 FLEXCNT (
.clk(clk),
.n_rst(n_rst),
.clear(1'b0),
.count_enable(count_en1),
.rollover_val({1'b1, 1'b1}),
.count_o... | 7.587936 |
module tx_fifo (
clk,
n_rst,
data_in,
tx_enq,
tx_deq_word,
full,
empty,
tx_fifo_out
);
input [127:0] data_in;
output [31:0] tx_fifo_out;
input clk, n_rst, tx_enq, tx_deq_word;
output full, empty;
wire count_en1, count_en2, tail_tog, head_tog;
wire [1:0] head_side;
wire [2:0... | 7.105997 |
module sub_bytes (
i_data,
o_data
);
input [127:0] i_data;
output [127:0] o_data;
s_box_lookup_15 SUB1 (
.input_word(i_data[127:120]),
.substituted_word(o_data[127:120])
);
s_box_lookup_14 SUB2 (
.input_word(i_data[119:112]),
.substituted_word(o_data[119:112])
);
s_box_lo... | 6.930515 |
module inv_sub_bytes (
i_data,
o_data
);
input [127:0] i_data;
output [127:0] o_data;
inv_s_box_lookup_15 ISUB1 (
.input_word(i_data[127:120]),
.substituted_word(o_data[127:120])
);
inv_s_box_lookup_14 ISUB2 (
.input_word(i_data[119:112]),
.substituted_word(o_data[119:112])
... | 6.81424 |
module AES_toplevel (
HCLK,
HRESETn,
HSELx,
HADDR,
HWDATA,
HBURST,
HPROT,
HSIZE,
HTRANS,
HWRITE,
HRDATA,
HREADY,
HRESP
);
input [31:0] HADDR;
input [31:0] HWDATA;
input [2:0] HBURST;
input [3:0] HPROT;
input [2:0] HSIZE;
input [1:0] HTRANS;
output [31:0]... | 7.323601 |
module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module aes_top(
clk,
rst,
kld,
text_out,
done
);
input clk;
input rst;
input kld;
wire [383:0] tv = 384'h3243f6a8885a308d3... | 7.612722 |
module aes_top_example (
clk,
reset,
i_enable,
i_enc_dec,
i_key_mode,
i_data,
i_data_sel,
i_data_valid,
o_data_sel,
o_key_ready,
o_ready,
o_data,
o_data_valid
);
//---------------------------------------------------------------------------------------
// module in... | 6.730975 |
module aes_top_wb (
wb_adr_i,
wb_cyc_i,
wb_dat_i,
wb_sel_i,
wb_stb_i,
wb_we_i,
wb_ack_o,
wb_err_o,
wb_dat_o,
wb_clk_i,
wb_rst_i,
int_o
);
parameter DW = 32;
parameter AW = 32;
input wire [AW-1:0] wb_adr_i;
input wire wb_cyc_i;
input wire [DW-1:0] wb_dat_i;
i... | 7.443134 |
module getinvRoundKeys returns ten 128-bit keys with invRoundKeys[127:0] referring to key for first inverse round
// mKey refers to the (transformed) master key used in first round of encryption
module getInvRoundKeys(output [1279:0] invRoundKeys, input [127:0] mKey);
getRoundKeys g1(.outKey(invRoundKeys[1279:1152]), ... | 7.079177 |
module subBytes (
output [127:0] sub,
input [127:0] data
);
sbox q0 (
.toReplace(data[127:120]),
.sub(sub[127:120])
);
sbox q1 (
.toReplace(data[119:112]),
.sub(sub[119:112])
);
sbox q2 (
.toReplace(data[111:104]),
.sub(sub[111:104])
);
sbox q3 (
.toRepla... | 7.325733 |
module inv_round (
outRound,
data,
rKey
);
output [127:0] outRound;
input [127:0] rKey, data;
//wire [127:0] XORRound, inv_mixed, inv_shifted; //bug???
wire [127:0] XORRoundKey, inv_mixed, inv_shifted;
assign XORRoundKey = rKey ^ data;
inv_mixColumns imc1 (
.aNew(inv_mixed),
.a(XOR... | 7.103645 |
module roundLast (
encryptedData,
data,
inKey,
roundNum
);
output [127:0] encryptedData;
input [127:0] data, inKey;
input [3:0] roundNum;
wire [127:0] sub, shifted, outKey;
getRoundKeys g1 (
.outKey(outKey),
.inKey(inKey),
.roundNum(roundNum)
);
subBytes sb1 (
.su... | 6.623808 |
module aes_v1_latency (
input wire g_clk,
input wire g_resetn,
input wire valid, // Input data valid
input wire dec, // Encrypt (0) or decrypt (1)
input wire mix, // Do MixColumns (1) or SubBytes (0)
input wire [31:0] rs1, // Input source ... | 7.517149 |
module aes_v1_size (
input wire g_clk,
input wire g_resetn,
input wire valid, // Input data valid
input wire dec, // Encrypt (0) or decrypt (1)
input wire mix, // Do MixColumns (1) or SubBytes (0)
input wire [31:0] rs1, // Input source reg... | 7.809908 |
module: aes_v2
//
// Latency (clock cycles) optimised.
//
module aes_v2_latency (
input wire g_clk ,
input wire g_resetn ,
input wire valid , // Are the inputs valid?
input wire sub , // Sub if set, Mix if clear
input wire enc , // Perform encrypt (set) or decr... | 7.701265 |
module: aes_v2
//
// Size optimised
//
module aes_v2_size(
input wire g_clk ,
input wire g_resetn ,
input wire valid , // Are the inputs valid?
input wire sub , // Sub if set, Mix if clear
input wire [31:0] rs1 , // Input source register 1
input wire [31:0] rs2 ... | 7.701265 |
module aes_v3_1 (
input wire valid, // Are the inputs valid? Used for logic gating.
input wire dec, // Encrypt (clear) or decrypt (set)
input wire mix, // Perform MixColumn transformation (if set)
input wire [31:0] rs1, // Source register 1
input wire [31:0] rs2, // Source register 2
... | 7.298698 |
module AES_W (
Clock,
Reset,
DataIn,
DataInValid,
DataInReady,
Key,
DataOut,
DataOutValid
);
`include "PathORAM.vh"
parameter W = 1;
parameter AESWIn_Width = AESEntropy;
//--------------------------------------------------------------------------
// System I/O
//------... | 6.789286 |
module AFA (
input x1,
x2,
cin,
output sum,
cout
);
wire w;
assign w = x1 | x2;
assign sum = w ^ cin;
assign cout = w & cin;
endmodule
| 7.190925 |
module AFE_ADS_TOP (
//--- GLOBAL ---
input sys_rst_n, //reset input, low is valid
input sys_clk, //system clock
//--- AFE PORTS ---
//-- control ports --
output AFE_CLK, //outputs the analog voltage from each integrator channel on each rising edge
output AFE_INTG, //integrate pixel s... | 7.459986 |
module afe_command_controller (
input clk,
reset_n,
input enable,
input serial_ready,
input [3:0] command,
output [7:0] rom_address,
output start_transaction,
output done
);
// Controller commands from afe_command_rom
parameter COMMAND_TO_SEND = 4'b0001, SEQUENCE_DONE = 4'b0000;
... | 8.070643 |
module afe_command_rom (
input clk,
reset_n,
input [7:0] address,
output [3:0] controller_command,
output [19:0] afe_shift_data
);
// Memory variable
reg [23:0] rom[255:0];
reg [23:0] command_reg;
assign controller_command = command_reg[23:20];
assign afe_shift_data = command_reg[19:0];
... | 7.26605 |
module afe_configure (
input clk,
reset_n,
input miso,
output device_reset,
output pdn,
output cs_n,
output mosi,
output device_sync,
output configure_done
);
wire reset_done;
wire transaction_done;
wire start_transaction;
wire command_transactions_done;
assign configur... | 6.541046 |
module afe_reset_timer (
input clk,
reset_n,
output device_reset,
output done
);
reg [15:0] counter;
reg device_reset_reg, done_reg;
assign device_reset = device_reset_reg;
assign done = done_reg;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
counter <= 16'hF... | 6.613985 |
module afe_serial_out (
input clk,
reset_n,
input enable,
input start_transaction,
input [19:0] parallel_input,
output cs_n,
output mosi,
output transaction_done
);
// State machine parameterized states
parameter idle_state = 3'd0, load_state = 3'd1, shifting_state = 3'd2, delay_sta... | 8.216108 |
module AFIFO #(
parameter DSIZE = 8,
parameter ASIZE = 4
) (
//Input Port
rst_n,
//Input Port (read)
rclk,
rinc,
//Input Port (write)
wclk,
winc,
wdata,
//Output Port (read)
rempty,
rdata,
//Output Port (write)
wfull
);
//------------------------------... | 7.320306 |
module afifo16 (
reset_ni,
rd_clk_i,
rd_en_i,
rd_data_o,
wr_clk_i,
wr_en_i,
wr_data_i,
rempty_o,
wfull_o
);
parameter WIDTH = 16;
input reset_ni;
input rd_clk_i;
input rd_en_i;
output [WIDTH-1:0] rd_data_o;
input wr_clk_i;
input wr_en_i;
input [WIDTH-1:0] wr_da... | 6.586682 |
module afifo18 (
input wire [17:0] Data,
input wire WrClock,
input wire RdClock,
input wire WrEn,
input wire RdEn,
input wire Reset,
input wire RPReset,
output wire [17:0] Q,
output wire Empty,
output wire Full
);
asfifo #(
.DATA_WIDTH(18),
.ADDRESS_WIDTH(13)
) a... | 6.847937 |
module afifo18_7 (
input wire [17:0] Data,
input wire WrClock,
input wire RdClock,
input wire WrEn,
input wire RdEn,
input wire Reset,
input wire RPReset,
output wire [17:0] Q,
output wire Empty,
output wire Full
);
asfifo #(
.DATA_WIDTH(18),
.ADDRESS_WIDTH(7)
) ... | 6.903262 |
module afifo72_w156_r250 (
input wire rst,
input wire wr_clk,
input wire rd_clk,
input wire [71:0] din,
input wire wr_en,
input wire rd_en,
output wire [71:0] dout,
output wire full,
output wire empty
);
asfifo #(
.DATA_WIDTH(72),
.ADDRESS_WIDTH(12)
) asfifo_inst (
... | 7.091994 |
module afifo72_w250_r156 (
input wire rst,
input wire wr_clk,
input wire rd_clk,
input wire [71:0] din,
input wire wr_en,
input wire rd_en,
output wire [71:0] dout,
output wire full,
output wire empty
);
asfifo #(
.DATA_WIDTH(72),
.ADDRESS_WIDTH(12)
) asfifo_inst (
... | 7.083324 |
module afifo9 (
input wire [8:0] Data,
input wire WrClock,
input wire RdClock,
input wire WrEn,
input wire RdEn,
input wire Reset,
input wire RPReset,
output wire [8:0] Q,
output wire Empty,
output wire Full
);
asfifo #(
.DATA_WIDTH(9),
.ADDRESS_WIDTH(10)
) asfif... | 7.060125 |
module afifo_16i_64o_256 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [63:0] q;
output rdempty;
output [5:0] rdusedw;
output wrfull;
output [7:0] wrusedw... | 6.691314 |
module afifo_16_256 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw
);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [7:0] rdusedw;
output wrfull;
... | 6.557148 |
module afifo_16_512 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw
);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [8:0] rdusedw;
output wrfull;
... | 6.948456 |
module afifo_64i_16o_64 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [63:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [7:0] rdusedw;
output wrfull;
output [5:0] wrusedw;... | 6.9074 |
module afifo_8i_16o_1024 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [8:0] rdusedw;
output wrfull;
output [9:0] wrusedw;... | 7.262557 |
module afifo_8i_16o_1024 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw
);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [8:0] rdusedw;
output wrfu... | 7.262557 |
module afifo_8i_32o_1024 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output [7:0] rdusedw;
output wrfull;
output [9:0] wrusedw;... | 7.218815 |
module afifo_8i_32o_1024 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw
);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output [7:0] rdusedw;
output wrfu... | 7.218815 |
module gray_counter_assim #(
parameter COUNTER_WIDTH = 4
) (
input wire rst, //Count reset.
input wire clk,
input wire en, //Count enable.
output [COUNTER_WIDTH-1:0] data_out
);
reg [COUNTER_WIDTH-1:0] bin_counter;
r... | 7.789595 |
module afifo_assim_tb;
//Inputs
reg reset;
reg read;
bit rclk;
reg [`W_DATA_W-1:0] data_in;
reg write;
bit wclk;
//Outputs
reg [`R_DATA_W-1:0] data_out;
wire empty_out;
wire [`R_ADDR_W-1:0] level_r;
wire full_out;
wire [`W_ADDR_W-1:0] level_w;
integer i;
parameter clk_per = 10; // clk... | 7.084496 |
module aFifo_negedge #(
parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 4,
FIFO_DEPTH = (1 << ADDRESS_WIDTH)
)
//Reading port
(
output wire [DATA_WIDTH-1:0] q,
output reg rdempty,
input wire rdreq,
input wire rdclk,
//Writing port.... | 7.197214 |
module afifo_sync_dff (
clk_d,
rst_d_n,
init_d_n,
data_s,
test,
data_d
);
parameter WIDTH = 1; // RANGE 1 to 1024
parameter F_SYNC_TYPE = 2; // RANGE 0 to 4
parameter TST_MODE = 0; // RANGE 0 to 1
parameter VERIF_EN = 1; // RANGE 0 to 4
input clk_d; // clock input from destinat... | 8.320194 |
module async_fifo_tb;
//Inputs
reg reset;
reg read;
bit rclk;
reg [`DATA_W-1:0] data_in;
reg write;
bit wclk;
//Outputs
reg [`DATA_W-1:0] data_out;
wire empty_out;
wire [`ADDR_W-1:0] level_r;
wire full_out;
wire [`ADDR_W-1:0] level_w;
integer i;
parameter clk_per = 10; // clk period =... | 6.523155 |
modules just wrap around. Only deadly if
// run_filter _doesn't_ show up more often than every 1024 cycles.
module afilter_siso #(
parameter pcw = 10
) (
input clk,
input reset, // XXX unimplemented, would be nice to have the ability to force filter state to zero
input run_filter,
input signed [17:0] u_in,
outp... | 7.235163 |
module afilter_siso_tb;
reg clk;
wire lb_clk = clk;
integer cc;
`ifdef SIMULATE
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("afilter_siso.vcd");
$dumpvars(5, afilter_siso_tb);
end
for (cc = 0; cc < 400; cc = cc + 1) begin
clk = 0;
#4;
clk = 1;
#4;
... | 6.554122 |
module is Offset Binary
// [It is perhaps stupid to have that here and it should be moved into another module]
// CONCEPT: The mid point along the circle of a of 2 complex numbers that already lie
// on a circle is not a plain average. To obtain the (real/imaginary) component
// of this mid-point one... | 6.526246 |
module afterburner2 (
input clk, // timespec 6.0 ns
input signed [16:0] data,
output [15:0] data_out0,
output [15:0] data_out1
);
parameter coeff = `AFTERBURNER_COEFF;
// concept: a1 k*(a1+a2) a2 k*(a2+a3) a3 ...
// where k = 0.5*sec(theta) = 0.5*sec(2*pi*11/28) = -0.63952
// to handle ... | 7.199949 |
module afu_csr (
input wire clk,
input wire reset_n,
input wire spl_reset,
// RX, afu_io --> afu_csr
input wire io_rx_csr_valid,
input wire [13:0] io_rx_csr_addr,
input wire [31:0] io_rx_csr_data,
// afu_csr-->afu_core, afu_id
output reg csr_id_valid,
input wir... | 6.558658 |
module af_data_buffer (
input wire i_clk,
input wire i_valid,
input wire [39:0] i_inputData,
output reg [39:0] o_outputData
);
always @(posedge i_clk) begin
o_outputData <= (i_valid ? i_inputData[39:32] : o_outputData);
end
endmodule
| 6.655606 |
module and_gate (
input a,
input b,
output reg y
);
always @(*) begin
assign y = a & b;
end
endmodule
| 8.887051 |
module AGC (
input wire clk,
input wire rst,
input wire [ 7:0] a_coef,
input wire [15:0] reference,
input wire signed [15:0] x_in,
output wire signed [15:0] y_out
);
wire [31:0] x_mod;
wire [31:0] ref_rms;
wire signed [ 8:0] a_c... | 7.320386 |
module agc_sim ();
parameter CLK_PRD = 10;
parameter DATA_DEP = 16384 * 5;
reg clk;
reg reset_n;
reg [9:0] data_I_in;
reg [9:0] data_Q_in;
reg agc_en;
task clock_gen;
begin
clk = 1'b0;
forever #(CLK_PRD / 2) clk = ~clk;
end
endtask
task reset_gen;
begin
reset_n = 1'b... | 6.853351 |
module agearr #(
parameter HEIGHT = 16,
parameter WIDTH = 16
) (
input clk,
input rst,
input set_row_valid,
input [HEIGHT-1:0] set_row_sel,
input clear_col_valid,
input [WIDTH-1:0] clear_col_sel,
input [HEIGHT-1:0] row_sel,
output [HEIGHT-1:0] col_se... | 7.71801 |
module AgenLsu (
input clk,
input reset,
input ctrlMispredict_i,
input [`CHECKPOINTS_LOG-1:0] ctrlSMTid_i,
input [`CHECKPOINTS+`LDST_TYPES_LOG+`EXECUTION_FLAGS+`SIZE_PHYSICAL_LOG+`SIZE_ACTIVELIST_LOG+`SIZE_DATA+`SIZE_ISSUEQ_LOG+
`SIZE_LSQ_LOG+`CHECKPOINTS_LOG+`SIZE_CTI_LOG+`SIZE... | 7.113476 |
module age_set_ctr (
clk,
rst,
re,
we,
hit,
miss,
access_addr,
write_addr,
age_1D
);
parameter k = 3; /////////////age counter width//////////
parameter j = 2; /////////////set counter width- will be used for Age Granularity//////////
parameter A = 2; //////////////Age Gra... | 7.17768 |
module aggregator (
input [9:0] in_use,
input [159:0] samples,
input clk,
reset,
//compiles the average of all samples
output [15:0] sample_out,
output [15:0] sample_out_left,
output [15:0] sample_out_right
);
wire [ 3:0] numSamples;
wire [25:0] interMed;
wire [25:0] pre_interMed... | 7.870736 |
module aggregator_tb;
reg clk;
reg rst_n;
wire [`DATA_WIDTH - 1 : 0] fifo_dout;
wire fifo_empty_n;
wire fifo_deq;
wire [`FETCH_WIDTH * `DATA_WIDTH - 1 : 0] receiver_din;
reg [`FETCH_WIDTH * `DATA_WIDTH - 1 : 0] expected_dout;
reg receiver_full_n;
wire receiver_enq;
reg [`DATA_WIDTH - 1 : 0] fifo_di... | 6.525058 |
module agitador (
input clk_i, //@100MHz
input onOff_i,
input selbtn_i,
input upbtn_i,
input downbtn_i,
input rx_i,
inout zero_i,
output motor_o,
output heater_o,
output motor_d,
output heater_d,
output tx_o,
output [7:0] SEG_o,
output [3:0] AN_o
);
wire updat... | 6.527058 |
module agnus_audiodma (
input wire clk, // bus clock
input wire clk7_en, // 7MHz clock enable
output wire dma, // true if audio dma engine uses it's cycle
input wire [ 4-1:0] audio_dmal, // audio dma data transfer request (from Paula... | 6.567104 |
module can shift 0-15 positions to the right (normal mode) or to the left (descending mode).
//Multipliers are used to save logic.
module agnus_blitter_barrelshifter
(
input desc, // select descending mode (shift to the left)
input [3:0] shift, // shift value (0 to 15)
input [15:0] new_val, // barrel shifter d... | 7.166817 |
module has 2 modes,inclusive fill and exclusive fill.
//Both share the same xor operation but in inclusive fill mode,
//the output of the xor-filler is or-ed with the input data.
module agnus_blitter_fill
(
input ife, //inclusive fill enable
input efe, //exclusive fill enable
input fci, //fill carry i... | 7.451104 |
module agnus_diskdma (
input clk, //bus clock
input clk7_en,
output dma, //true if disk dma engine uses it's cycle
input dmal, //Paula requests dma
input dmas, //Paula special dma
input ... | 6.84107 |
module agtb_16 (
input wire clk
, input wire [15:0] inpa
, input wire [15:0] inpb
, output reg out_agtb
);
// break this troublesome compare in half
wire [7:0] inpa_hi, inpa_lo;
wire [7:0] inpb_hi, inpb_lo;
assign {inpb_hi, inpb_lo} = inpb;
assign {inpa_hi, inpa_lo} = inpa;
reg inpa_gt_in... | 6.801099 |
module agtb_8 (
input wire clk
, input wire [07:0] inpa
, input wire [07:0] inpb
, output reg out_agtb
);
// break this troublesome compare in half
wire [3:0] inpa_hi, inpa_lo;
wire [3:0] inpb_hi, inpb_lo;
assign {inpb_hi, inpb_lo} = inpb;
assign {inpa_hi, inpa_lo} = inpa;
reg inpa_gt_inp... | 6.713251 |
module agu (
input [XLEN - 1 : 0] base_i,
input [XLEN - 1 : 0] offset_i,
output [VIRTUAL_ADDR_LEN - 1 : 0] addr_o
);
assign addr_o = base_i[VIRTUAL_ADDR_LEN-1 : 0] + offset_i[VIRTUAL_ADDR_LEN-1 : 0];
endmodule
| 6.726108 |
module agucam_ram0 (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
localparam DATA_WIDTH = (3 + 3 * `mOp_width) / 2 + 1;
localparam ADDR_WIDTH = 3;
localparam ADDR_COUNT = 8;
input clk;
input rst;
input read_clkEn;
input [ADDR_WIDTH-1:0]... | 7.941291 |
module agucam_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
localparam DATA_WIDTH = 3 + 3 * `mOp_width;
localparam ADDR_WIDTH = 3;
localparam ADDR_COUNT = 8;
input clk;
input rst;
input read_clkEn;
input [ADDR_WIDTH-1:0] read_addr;
... | 7.378573 |
module agusec_range (
input [63:0] ptr,
input cin_secq,
input diff,
output cout_secq
);
wire [7:0] low = {ptr[`ptr_low], 1'b0};
wire [7:0] high = {ptr[`ptr_hi], 1'b1};
//wire diff=ptr[`ptr_hi_less];
wire hi_pass = diff && ptr[`ptr_on_low];
wire lo_lass = diff && ~ptr[`ptr_on_low];
wire [7:0... | 7.056686 |
module
// with baseclk frequency ~ 10 x phi_0
`define AG6502_EXTERNAL_CLOCK
`ifndef AG6502_EXTERNAL_CLOCK
module ag6502_clock(input phi_0, output phi_1, output phi_2);
wire phi_01;
not#3(phi_1,phi_0);
or(phi_01,~phi_0, phi_1);
not#1(phi_2, phi_01);
endmodule
| 6.600709 |
module ag6502_phase_shift (
input baseclk,
input phi_0,
output reg phi_1
);
parameter DELAY = 1; // delay in waves of baseclk
initial phi_1 = 0;
integer cnt = 0;
always @(posedge baseclk) begin
if (phi_0 != phi_1) begin
if (!cnt) begin
phi_1 <= phi_0;
cnt <= DELAY;
... | 6.54584 |
module ag6502_ext_clock(input baseclk, input phi_0, output phi_1, output phi_2);
parameter DELAY1 = 3, DELAY2 = 1; // delays in waves of baseclk
wire phi_1_neg, phi_01;
ag6502_phase_shift#DELAY1 d1(baseclk, phi_0, phi_1_neg);
assign phi_1 = ~phi_1_neg;
and(phi_01, phi_0, phi_1_neg);
ag6502_phase_shift#DELAY... | 6.804942 |
module ag6502_decimal (
ADD,
D_IN,
NEG,
CORR
);
input wire [4:0] ADD;
input wire D_IN, NEG;
output wire [4:0] CORR;
wire C9 = {ADD[4] ^ NEG, ADD[3:0]} > 5'd9;
assign CORR = D_IN ? {C9 ^ NEG, C9 ? ADD[3:0] + (NEG ? 4'd10 : 4'd6) : ADD[3:0]} : ADD;
endmodule
| 6.971945 |
module signal_filter (
input clk,
input in,
output reg out
);
always @(posedge clk) begin
out <= in;
end
endmodule
| 6.764118 |
module ps2_keyb_driver (
ps2_clk,
ps2_data,
ps2_code,
ps2_up,
ps2_ext,
ps2_event
);
input wire ps2_clk, ps2_data;
output reg [7:0] ps2_code = 0;
output reg ps2_up = 0, ps2_ext = 0, ps2_event = 0;
reg [10:0] shreg = 11'b11111111111;
wire [10:0] shnew = {ps2_data, shreg[10:1]};
wire s... | 7.489071 |
module ag_reg_decoder (
keyb_in,
shift,
ctrl,
keyb_out
);
input wire [6:0] keyb_in;
input wire shift, ctrl;
output wire [6:0] keyb_out;
wire is_alpha = keyb_in[6] && !keyb_in[5];
wire is_digit = !keyb_in[6] && keyb_in[5] && keyb_in[3:0];
assign keyb_out =
is_alpha?
(shift?{1'b1,1'b1,k... | 7.044385 |
module ag_keyb (
clk,
ps2_bus,
keyb_reg,
keyb_clear,
keyb_rus,
keyb_rst,
keyb_pause
);
input clk;
input wire [1:0] ps2_bus;
output wire [7:0] keyb_reg;
input wire keyb_clear;
output wire keyb_rus;
output wire keyb_rst;
output wire keyb_pause;
wire ps2_clk, ps2_data;
assig... | 7.390119 |
module RAM2kx8 (
input CLK,
input [10:0] AB,
input CS,
input READ,
output [7:0] DO,
input [7:0] DI
);
reg [7:0] mem[0:2047];
reg [7:0] R;
assign DO = CS ? R : 8'bZ;
initial begin
`include "monitor7.v"
// mem['h7FA] = 8'h58;
// mem['h7FB] = 8'hF9;
mem['h7FC] = 8'h00;
... | 6.924805 |
module RAM4kx8 (
input CLK,
input [11:0] AB,
input CS,
input READ,
output [7:0] DO,
input [7:0] DI
);
reg [7:0] mem[0:4095];
reg [7:0] R;
assign DO = CS ? R : 8'bZ;
always @(posedge CLK)
if (CS)
if (READ) R <= mem[AB];
else mem[AB] <= DI;
endmodule
| 7.142793 |
module RAM8kx8 (
input CLK,
input [12:0] AB,
input CS,
input READ,
output [7:0] DO,
input [7:0] DI
);
reg [7:0] mem[0:8191];
reg [7:0] R;
assign DO = CS ? R : 8'bZ;
always @(posedge CLK)
if (CS)
if (READ) R <= mem[AB];
else mem[AB] <= DI;
endmodule
| 7.295068 |
module RAM1Kx1 (
input CLK1,
input [9:0] AB1,
input CS1,
input READ,
output DO1,
input DI1,
input CLK2,
input [9:0] AB2,
input CS2,
output DO2
);
parameter FILL = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC;
reg mem[0:'h3FF];
integer i;
initial ... | 6.503124 |
module RAM32Kx8x16 (
input CLK1,
input [14:0] AB1,
input CS1,
input READ,
output [7:0] DO1,
input [7:0] DI1,
input CLK2,
input [13:0] AB2,
input CS2,
output [15:0] DO2
);
wire [ 1:0] CSM = {(~AB1[0]) & CS1, AB1[0] & CS1}; // CS for modules
wire [13:0] AB1x = AB1[14:1];
`in... | 7.702713 |
module FONT_ROM (
input [10:0] adr,
input cs,
output [7:0] DO
);
reg [7:0] mem[0:2047];
assign DO = cs ? mem[adr] : 8'bZ;
initial begin
`include "agathe7.v"
end
endmodule
| 8.099762 |
module AHA (
input x1,
x2,
output sum,
cout
);
assign sum = x1 | x2;
assign cout = x1 & x2;
endmodule
| 8.27824 |
module AhaAhbCodeRegion (
// Inputs
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire HREADY,
input wire [ 1:0] HTRANS,
input wire [ 2:0] HSIZE,
input wire HWRITE,
input wire [31:0] HADDR,
input wire [31:0] HWDATA,
// Outputs
output w... | 7.742278 |
module AhaAhbRam128K #(
parameter IMAGE_FILE = "None"
) (
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire HREADY,
input wire [ 1:0] HTRANS,
input wire [ 2:0] HSIZE,
input wire HWRITE,
input wire [31:0] HADDR,
input wire [31:0] HWDATA,
o... | 7.029429 |
module AhaAHBToParallel #(
parameter ADDR_WIDTH = 12
) (
// AHB Interface
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire HWRITE,
input wire [ 2:0] HSIZE,
input wire [ 2:0] HBURST,
input wire [... | 8.233608 |
module AhaAsyncPulseGen (
input wire CLK,
input wire RESETn,
input wire D,
output wire RISE_PULSE,
output wire FALL_PULSE
);
wire d_sync;
reg d_r;
AhaDataSync u_data_sync (
.CLK (CLK),
.RESETn(RESETn),
.D (D),
.Q (d_sync)
);
always @(posedge CLK or ... | 7.754295 |
module AhaAxiToSifRead (
input wire ACLK,
input wire ARESETn,
input wire [ 3:0] ARID,
input wire [31:0] ARADDR,
input wire [ 7:0] ARLEN,
input wire [ 2:0] ARSIZE,
input wire [ 1:0] ARBURST,
input wire ARLOCK,
input wire [ 3:0] ARCACHE,
input wire [ 2:0] ARPROT,
... | 7.36763 |
module AhaAxiToSifReadAddrGen (
input wire ACLK,
input wire ARESETn,
input wire [31:0] ARADDR,
input wire [ 1:0] ARBURST,
input wire [ 2:0] ARSIZE,
input wire [ 7:0] ARLEN,
input wire ARVALID,
output wire ARREADY,
input wire RVALID,
input wire RREADY,
inp... | 7.36763 |
module AhaAxiToSifReadData (
input wire ACLK,
input wire ARESETn,
input wire [7:0] ARLEN,
input wire ARVALID,
input wire ARREADY,
input wire RREADY,
output wire RVALID,
output wire RLAST,
output wire [63:0] RDATA,
input wire [63:0] SIF_RD_DATA... | 7.36763 |
module AhaAxiToSifWrite (
input wire ACLK,
input wire ARESETn,
input wire [ 3:0] AWID,
input wire [31:0] AWADDR,
input wire [ 7:0] AWLEN,
input wire [ 2:0] AWSIZE,
input wire [ 1:0] AWBURST,
input wire AWLOCK,
input wire [ 3:0] AWCACHE,
input wire [ 2:0] AWPROT,
... | 6.797945 |
module AhaClockDivider (
// Inputs
input wire CLK_IN,
input wire RESETn,
// Outputs
output wire CLK_by_1,
output wire CLK_by_1_EN,
output wire CLK_by_2,
output wire CLK_by_2_EN,
output wire CLK_by_4,
output wire CLK_by_4_EN,
output wire CLK_by_8,
output wire CLK_by_8_EN,... | 7.467431 |
module AhaClockEnGate (
input wire PORESETn,
input wire TE,
input wire E,
input wire CP, // clock associated with the clock enable signal
input wire CE, // clock enable signal
output wire Q
);
// Internal Wires and Regs
wire reset_n;
wire en;
reg en_r;
assign en = ... | 7.200709 |
module AhaClockGate (
input wire TE,
input wire E,
input wire CP,
output wire Q
);
// Internal Wires and Regs
wire en;
reg en_r;
assign en = TE | E;
// Logic
always @(CP or en) begin
if (CP == 1'b0) en_r <= en;
end
// Output
assign Q = CP & en_r;
endmodule
| 6.821352 |
module AhaClockSwitch (
// Clock Signals
input wire CLK,
input wire CLK_EN,
// State of Other Clock Signals
input wire ALT_CLK_EN1,
input wire ALT_CLK_EN2,
input wire ALT_CLK_EN3,
input wire ALT_CLK_EN4,
input wire ALT_CLK_EN5,
// Selector Lines
input wire [2:0] SELECT_REQ,... | 9.473661 |
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