code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module rcv_counter_tail (
clk,
n_rst,
count_en2,
tail_ptr,
tail_tog
);
output [1:0] tail_ptr;
input clk, n_rst, count_en2;
output tail_tog;
wire temp_tail_tog, n3, n2;
DFFSR tail_tog_reg (
.D (temp_tail_tog),
.CLK(clk),
.R (n_rst),
.S (1'b1),
.Q (tail_tog)
);
XNOR2X1 U5 (
.A(tail_tog),
.B(n3),
.Y(temp_tail_tog)
);
NAND3X1 U6 (
.A(count_en2),
.B(n2),
.C(tail_ptr[1]),
.Y(n3)
);
fifo_flex_counter_NUM_CNT_BITS2_3 FLEXCNT (
.clk(clk),
.n_rst(n_rst),
.clear(1'b0),
.count_enable(count_en2),
.rollover_val({1'b1, 1'b0}),
.count_out(tail_ptr)
);
INVX2 U4 (
.A(tail_ptr[0]),
.Y(n2)
);
endmodule
| 6.536109 |
module rcv_counter_idx (
clk,
n_rst,
count_en1,
sync_clr,
tail_side
);
output [1:0] tail_side;
input clk, n_rst, count_en1, sync_clr;
fifo_flex_counter_NUM_CNT_BITS2_1 FLEXCNT (
.clk(clk),
.n_rst(n_rst),
.clear(sync_clr),
.count_enable(count_en1),
.rollover_val({1'b1, 1'b1}),
.count_out(tail_side)
);
endmodule
| 7.471843 |
module rcv_fifo (
clk,
n_rst,
HWDATA,
rcv_deq,
rcv_enq_word,
fix_error,
rcv_fifo_out,
full,
empty,
framing_error
);
input [31:0] HWDATA;
output [127:0] rcv_fifo_out;
input clk, n_rst, rcv_deq, rcv_enq_word, fix_error;
output full, empty, framing_error;
wire count_en1, count_en2, sync_clr, WE, tail_tog, head_tog;
wire [1:0] tail_side;
wire [1:0] tail_ptr;
wire [1:0] head_ptr;
rcv_fifo_fsm FSM (
.clk(clk),
.n_rst(n_rst),
.rcv_enq_word(rcv_enq_word),
.full(full),
.tail_side(tail_side),
.fix_error(fix_error),
.count_en1(count_en1),
.sync_clr(sync_clr),
.count_en2(count_en2),
.WE(WE)
);
rcv_counter_tail TAIL_PTR (
.clk(clk),
.n_rst(n_rst),
.count_en2(count_en2),
.tail_ptr(tail_ptr),
.tail_tog(tail_tog)
);
rcv_counter_head HEAD_PTR (
.clk(clk),
.n_rst(n_rst),
.rcv_deq(rcv_deq),
.head_ptr(head_ptr),
.head_tog(head_tog)
);
rcv_counter_idx TAIL_IDX (
.clk(clk),
.n_rst(n_rst),
.count_en1(count_en1),
.sync_clr(sync_clr),
.tail_side(tail_side)
);
rcv_comb_output COMB_OUT (
.head_ptr(head_ptr),
.tail_side(tail_side),
.tail_ptr(tail_ptr),
.tail_tog(tail_tog),
.head_tog(head_tog),
.full(full),
.empty(empty),
.framing_error(framing_error)
);
rcv_fifo_reg FIFO_REG (
.clk(clk),
.tail_ptr(tail_ptr),
.tail_side(tail_side),
.head_ptr(head_ptr),
.HWDATA(HWDATA),
.WE(WE),
.rcv_fifo_out(rcv_fifo_out)
);
endmodule
| 6.577353 |
module tx_counter_idx (
clk,
n_rst,
count_en1,
head_side
);
output [1:0] head_side;
input clk, n_rst, count_en1;
fifo_flex_counter_NUM_CNT_BITS2_0 FLEXCNT (
.clk(clk),
.n_rst(n_rst),
.clear(1'b0),
.count_enable(count_en1),
.rollover_val({1'b1, 1'b1}),
.count_out(head_side)
);
endmodule
| 7.587936 |
module tx_fifo (
clk,
n_rst,
data_in,
tx_enq,
tx_deq_word,
full,
empty,
tx_fifo_out
);
input [127:0] data_in;
output [31:0] tx_fifo_out;
input clk, n_rst, tx_enq, tx_deq_word;
output full, empty;
wire count_en1, count_en2, tail_tog, head_tog;
wire [1:0] head_side;
wire [2:0] tail_ptr;
wire [2:0] head_ptr;
tx_fifo_fsm FSM (
.clk(clk),
.n_rst(n_rst),
.tx_deq_word(tx_deq_word),
.empty(empty),
.head_side(head_side),
.count_en1(count_en1),
.count_en2(count_en2)
);
tx_counter_tail TAIL_PTR (
.clk(clk),
.n_rst(n_rst),
.tx_enq(tx_enq),
.tail_ptr(tail_ptr),
.tail_tog(tail_tog)
);
tx_counter_head HEAD_PTR (
.clk(clk),
.n_rst(n_rst),
.count_en2(count_en2),
.head_ptr(head_ptr),
.head_tog(head_tog)
);
tx_counter_idx HEAD_IDX (
.clk(clk),
.n_rst(n_rst),
.count_en1(count_en1),
.head_side(head_side)
);
tx_comb_output COMB_OUT (
.head_ptr(head_ptr),
.head_side(head_side),
.tail_ptr(tail_ptr),
.tail_tog(tail_tog),
.head_tog(head_tog),
.full(full),
.empty(empty)
);
tx_fifo_reg FIFO_REG (
.clk(clk),
.tail_ptr(tail_ptr),
.head_side(head_side),
.head_ptr(head_ptr),
.data_in(data_in),
.WE(tx_enq),
.tx_fifo_out(tx_fifo_out)
);
endmodule
| 7.105997 |
module sub_bytes (
i_data,
o_data
);
input [127:0] i_data;
output [127:0] o_data;
s_box_lookup_15 SUB1 (
.input_word(i_data[127:120]),
.substituted_word(o_data[127:120])
);
s_box_lookup_14 SUB2 (
.input_word(i_data[119:112]),
.substituted_word(o_data[119:112])
);
s_box_lookup_13 SUB3 (
.input_word(i_data[111:104]),
.substituted_word(o_data[111:104])
);
s_box_lookup_12 SUB4 (
.input_word(i_data[103:96]),
.substituted_word(o_data[103:96])
);
s_box_lookup_11 SUB5 (
.input_word(i_data[95:88]),
.substituted_word(o_data[95:88])
);
s_box_lookup_10 SUB6 (
.input_word(i_data[87:80]),
.substituted_word(o_data[87:80])
);
s_box_lookup_9 SUB7 (
.input_word(i_data[79:72]),
.substituted_word(o_data[79:72])
);
s_box_lookup_8 SUB8 (
.input_word(i_data[71:64]),
.substituted_word(o_data[71:64])
);
s_box_lookup_7 SUB9 (
.input_word(i_data[63:56]),
.substituted_word(o_data[63:56])
);
s_box_lookup_6 SUB10 (
.input_word(i_data[55:48]),
.substituted_word(o_data[55:48])
);
s_box_lookup_5 SUB11 (
.input_word(i_data[47:40]),
.substituted_word(o_data[47:40])
);
s_box_lookup_4 SUB12 (
.input_word(i_data[39:32]),
.substituted_word(o_data[39:32])
);
s_box_lookup_3 SUB13 (
.input_word(i_data[31:24]),
.substituted_word(o_data[31:24])
);
s_box_lookup_2 SUB14 (
.input_word(i_data[23:16]),
.substituted_word(o_data[23:16])
);
s_box_lookup_1 SUB15 (
.input_word(i_data[15:8]),
.substituted_word(o_data[15:8])
);
s_box_lookup_0 SUB16 (
.input_word(i_data[7:0]),
.substituted_word(o_data[7:0])
);
endmodule
| 6.930515 |
module inv_sub_bytes (
i_data,
o_data
);
input [127:0] i_data;
output [127:0] o_data;
inv_s_box_lookup_15 ISUB1 (
.input_word(i_data[127:120]),
.substituted_word(o_data[127:120])
);
inv_s_box_lookup_14 ISUB2 (
.input_word(i_data[119:112]),
.substituted_word(o_data[119:112])
);
inv_s_box_lookup_13 ISUB3 (
.input_word(i_data[111:104]),
.substituted_word(o_data[111:104])
);
inv_s_box_lookup_12 ISUB4 (
.input_word(i_data[103:96]),
.substituted_word(o_data[103:96])
);
inv_s_box_lookup_11 ISUB5 (
.input_word(i_data[95:88]),
.substituted_word(o_data[95:88])
);
inv_s_box_lookup_10 ISUB6 (
.input_word(i_data[87:80]),
.substituted_word(o_data[87:80])
);
inv_s_box_lookup_9 ISUB7 (
.input_word(i_data[79:72]),
.substituted_word(o_data[79:72])
);
inv_s_box_lookup_8 ISUB8 (
.input_word(i_data[71:64]),
.substituted_word(o_data[71:64])
);
inv_s_box_lookup_7 ISUB9 (
.input_word(i_data[63:56]),
.substituted_word(o_data[63:56])
);
inv_s_box_lookup_6 ISUB10 (
.input_word(i_data[55:48]),
.substituted_word(o_data[55:48])
);
inv_s_box_lookup_5 ISUB11 (
.input_word(i_data[47:40]),
.substituted_word(o_data[47:40])
);
inv_s_box_lookup_4 ISUB12 (
.input_word(i_data[39:32]),
.substituted_word(o_data[39:32])
);
inv_s_box_lookup_3 ISUB13 (
.input_word(i_data[31:24]),
.substituted_word(o_data[31:24])
);
inv_s_box_lookup_2 ISUB14 (
.input_word(i_data[23:16]),
.substituted_word(o_data[23:16])
);
inv_s_box_lookup_1 ISUB15 (
.input_word(i_data[15:8]),
.substituted_word(o_data[15:8])
);
inv_s_box_lookup_0 ISUB16 (
.input_word(i_data[7:0]),
.substituted_word(o_data[7:0])
);
endmodule
| 6.81424 |
module AES_toplevel (
HCLK,
HRESETn,
HSELx,
HADDR,
HWDATA,
HBURST,
HPROT,
HSIZE,
HTRANS,
HWRITE,
HRDATA,
HREADY,
HRESP
);
input [31:0] HADDR;
input [31:0] HWDATA;
input [2:0] HBURST;
input [3:0] HPROT;
input [2:0] HSIZE;
input [1:0] HTRANS;
output [31:0] HRDATA;
output [1:0] HRESP;
input HCLK, HRESETn, HSELx, HWRITE;
output HREADY;
wire n2, tx_enq, rcv_deq, is_encrypt_pulse, is_decrypt_pulse, key_in,
tx_fifo_full, tx_fifo_empty, rcv_fifo_full, rcv_fifo_empty,
generation_done, data_done, data_valid, is_encrypt, read_fifo,
mcu_key_in;
wire [ 3:0] status_bits;
wire [127:0] data_in;
wire [127:0] rcv_fifo_out;
wire [127:0] round_key_0;
wire [127:0] round_key_input;
wire [127:0] round_key_10;
wire [ 3:0] read_addr;
assign HRESP[1] = 1'b0;
ahb_fifo_io AHB (
.HCLK(HCLK),
.HRESETn(HRESETn),
.HSELx(HSELx),
.HADDR(HADDR),
.HWDATA(HWDATA),
.HBURST(HBURST),
.HPROT(HPROT),
.HSIZE(HSIZE),
.HTRANS(HTRANS),
.HWRITE(HWRITE),
.status(status_bits),
.data_in(data_in),
.tx_enq(tx_enq),
.rcv_deq(rcv_deq),
.fix_error(1'b0),
.HRDATA(HRDATA),
.HREADY(HREADY),
.HRESP({n2, HRESP[0]}),
.is_encrypt_pulse(is_encrypt_pulse),
.is_decrypt_pulse(is_decrypt_pulse),
.key_in(key_in),
.rcv_fifo_out(rcv_fifo_out),
.tx_fifo_full(tx_fifo_full),
.tx_fifo_empty(tx_fifo_empty),
.rcv_fifo_full(rcv_fifo_full),
.rcv_fifo_empty(rcv_fifo_empty)
);
MCU jhfgd (
.clk(HCLK),
.n_reset(HRESETn),
.generation_done(generation_done),
.key_in(key_in),
.is_decryption_pulse(is_decrypt_pulse),
.is_encryption_pulse(is_encrypt_pulse),
.emptyRx(rcv_fifo_empty),
.fullRx(rcv_fifo_full),
.emptyTx(tx_fifo_empty),
.fullTx(tx_fifo_full),
.data_done(data_done),
.accepted(data_valid),
.is_encrypt(is_encrypt),
.read_fifo(read_fifo),
.rcv_deq(rcv_deq),
.trans_enq(tx_enq),
.mcu_key_in(mcu_key_in),
.status_bits(status_bits)
);
aes_block AES (
.clk(HCLK),
.n_rst(HRESETn),
.read_fifo(read_fifo),
.is_encrypt(is_encrypt),
.tx_fifo_full(tx_fifo_full),
.rx_fifo_out(rcv_fifo_out),
.round_key_0(round_key_0),
.round_key_10(round_key_10),
.round_key_input(round_key_input),
.read_addr(read_addr),
.tx_fifo_in(data_in),
.data_done(data_done),
.data_valid(data_valid)
);
key_generator KEYGEN (
.clk(HCLK),
.n_rst(HRESETn),
.read_addr(read_addr),
.WE_key_generation(mcu_key_in),
.input_key(rcv_fifo_out),
.round_key_0(round_key_0),
.round_key_10(round_key_10),
.round_key_x(round_key_input),
.generation_done(generation_done)
);
endmodule
| 7.323601 |
module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module aes_top(
clk,
rst,
kld,
text_out,
done
);
input clk;
input rst;
input kld;
wire [383:0] tv = 384'h3243f6a8885a308d313198a2e03707342b7e151628aed2a6abf7158809cf4f3cd54e7519474ddb7ff5ee711cbab18dee;
output[127:0] text_out;
wire[127:0] key,text_in,plain,ciph,text_in2,text_out1;
output done;
wire done1;
assign key = tv[383:256];
assign text_in = tv[255:128];
assign text_in2 = tv[127:0];
assign plain = tv[255:128];
assign ciph = tv[127:0];
aes_cipher aes_c(clk,rst,kld,done1,key,text_in,text_out1);
aes_decipher aes_dc(clk,rst,kld,done1,done,key,text_in2,text_out);
endmodule
| 7.612722 |
module aes_top_example (
clk,
reset,
i_enable,
i_enc_dec,
i_key_mode,
i_data,
i_data_sel,
i_data_valid,
o_data_sel,
o_key_ready,
o_ready,
o_data,
o_data_valid
);
//---------------------------------------------------------------------------------------
// module interfaces
// global signals
input clk;
input reset;
// AES core interface
// inputs
input i_enable;
input i_enc_dec;
input [1:0] i_key_mode;
input [31:0] i_data;
input [3:0] i_data_sel;
input i_data_valid;
input [1:0] o_data_sel;
// outputs
output o_key_ready;
output o_ready;
output [31:0] o_data;
output o_data_valid;
//---------------------------------------------------------------------------------------
// registered outputs
reg [ 31:0] o_data;
// internal signals and registers
reg [255:0] int_key;
reg [127:0] int_data;
reg int_key_start, int_data_valid;
wire [127:0] int_o_data;
//---------------------------------------------------------------------------------------
// module implementation
// internal key and data vectors write process
always @(posedge reset or posedge clk) begin
if (reset) begin
int_key <= 256'b0;
int_data <= 128'b0;
int_key_start <= 1'b0;
int_data_valid <= 1'b0;
end else begin
// input key and data write control
if (i_data_valid) begin
case (i_data_sel)
4'h0: int_key[31:0] <= i_data;
4'h1: int_key[63:32] <= i_data;
4'h2: int_key[95:64] <= i_data;
4'h3: int_key[127:96] <= i_data;
4'h4: int_key[159:128] <= i_data;
4'h5: int_key[191:160] <= i_data;
4'h6: int_key[223:192] <= i_data;
4'h7: int_key[255:224] <= i_data;
4'h8: int_data[31:0] <= i_data;
4'h9: int_data[63:32] <= i_data;
4'ha: int_data[95:64] <= i_data;
4'hb: int_data[127:96] <= i_data;
endcase
end
// key expansion start control
if ((i_data_sel == 4'h7) && i_data_valid) int_key_start <= 1'b1;
else int_key_start <= 1'b0;
// encryption / decryption start control
if ((i_data_sel == 4'hb) && i_data_valid) int_data_valid <= 1'b1;
else int_data_valid <= 1'b0;
end
end
// output data read control process
always @(posedge reset or posedge clk) begin
if (reset) o_data <= 32'b0;
else begin
case (o_data_sel)
2'h0: o_data <= int_o_data[31:0];
2'h1: o_data <= int_o_data[63:32];
2'h2: o_data <= int_o_data[95:64];
2'h3: o_data <= int_o_data[127:96];
endcase
end
end
// AES core instance
aes u_aes (
.clk(clk),
.reset(reset),
.i_start(int_key_start),
.i_enable(i_enable),
.i_ende(i_enc_dec),
.i_key(int_key),
.i_key_mode(i_key_mode),
.i_data(int_data),
.i_data_valid(int_data_valid),
.o_ready(o_ready),
.o_data(int_o_data),
.o_data_valid(o_data_valid),
.o_key_ready(o_key_ready)
);
endmodule
| 6.730975 |
module aes_top_wb (
wb_adr_i,
wb_cyc_i,
wb_dat_i,
wb_sel_i,
wb_stb_i,
wb_we_i,
wb_ack_o,
wb_err_o,
wb_dat_o,
wb_clk_i,
wb_rst_i,
int_o
);
parameter DW = 32;
parameter AW = 32;
input wire [AW-1:0] wb_adr_i;
input wire wb_cyc_i;
input wire [DW-1:0] wb_dat_i;
input wire [3:0] wb_sel_i;
input wire wb_stb_i;
input wire wb_we_i;
output wire wb_ack_o;
output wire wb_err_o;
output reg [DW-1:0] wb_dat_o;
output wire int_o;
input wire wb_clk_i;
input wire wb_rst_i;
// As of now, no errors are generated
assign wb_err_o = 1'b0;
// Interrupt is unused
assign int_o = 1'b0;
// Internal registers
reg start, start_r;
reg [ 31:0] pt [0:3];
reg [ 31:0] key [0:5];
wire [127:0] pt_big = {pt[0], pt[1], pt[2], pt[3]};
wire [191:0] key_big = {key[0], key[1], key[2], key[3], key[4], key[5]};
wire [127:0] ct;
wire ct_valid;
reg wb_stb_i_r;
// Generate the acknowledgement signal
assign wb_ack_o = wb_stb_i;
// Implement MD5 I/O memory map interface
// Write side
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
start <= 0;
start_r <= 0;
pt[0] <= 0;
pt[1] <= 0;
pt[2] <= 0;
pt[3] <= 0;
key[0] <= 0;
key[1] <= 0;
key[2] <= 0;
key[3] <= 0;
key[4] <= 0;
key[5] <= 0;
wb_stb_i_r <= 0;
end else begin
// Generate registered version of some signals
start_r <= start;
wb_stb_i_r <= wb_stb_i;
// Perform a write
if (wb_stb_i & wb_we_i) begin
case (wb_adr_i[3:0])
0: start <= wb_dat_i[0];
1: pt[3] <= wb_dat_i;
2: pt[2] <= wb_dat_i;
3: pt[1] <= wb_dat_i;
4: pt[0] <= wb_dat_i;
5: key[5] <= wb_dat_i;
6: key[4] <= wb_dat_i;
7: key[3] <= wb_dat_i;
8: key[2] <= wb_dat_i;
9: key[1] <= wb_dat_i;
10: key[0] <= wb_dat_i;
default: ;
endcase
end else begin // end if wb_stb_i & wb_we_i
start <= 1'b0;
end
end // end else begin
end // always @ (posedge wb_clk_i)
// Implement MD5 I/O memory map interface
// Read side
always @(*) begin
case (wb_adr_i[3:0])
1: wb_dat_o = pt[3];
2: wb_dat_o = pt[2];
3: wb_dat_o = pt[1];
4: wb_dat_o = pt[0];
5: wb_dat_o = key[5];
6: wb_dat_o = key[4];
7: wb_dat_o = key[3];
8: wb_dat_o = key[2];
9: wb_dat_o = key[1];
10: wb_dat_o = key[0];
11: wb_dat_o = {31'b0, ct_valid};
12: wb_dat_o = ct[127:96];
13: wb_dat_o = ct[95:64];
14: wb_dat_o = ct[63:32];
15: wb_dat_o = ct[31:0];
default: wb_dat_o = 32'b0;
endcase
end // always @ (*)
aes_192 aes (
.clk(wb_clk_i),
.rst(wb_rst_i),
.state(pt_big),
.key(key_big),
.start(start && ~start_r), // start on detected position edge
.out(ct),
.out_valid(ct_valid)
);
endmodule
| 7.443134 |
module getinvRoundKeys returns ten 128-bit keys with invRoundKeys[127:0] referring to key for first inverse round
// mKey refers to the (transformed) master key used in first round of encryption
module getInvRoundKeys(output [1279:0] invRoundKeys, input [127:0] mKey);
getRoundKeys g1(.outKey(invRoundKeys[1279:1152]), .inKey(mKey), .roundNum(4'b0000));
getRoundKeys g2(.outKey(invRoundKeys[1151:1024]), .inKey(invRoundKeys[1279:1152]), .roundNum(4'b0001));
getRoundKeys g3(.outKey(invRoundKeys[1023:896]), .inKey(invRoundKeys[1151:1024]), .roundNum(4'b0010));
getRoundKeys g4(.outKey(invRoundKeys[895:768]), .inKey(invRoundKeys[1023:896]), .roundNum(4'b0011));
getRoundKeys g5(.outKey(invRoundKeys[767:640]), .inKey(invRoundKeys[895:768]), .roundNum(4'b0100));
getRoundKeys g6(.outKey(invRoundKeys[639:512]), .inKey(invRoundKeys[767:640]), .roundNum(4'b0101));
getRoundKeys g7(.outKey(invRoundKeys[511:384]), .inKey(invRoundKeys[639:512]), .roundNum(4'b0110));
getRoundKeys g8(.outKey(invRoundKeys[383:256]), .inKey(invRoundKeys[511:384]), .roundNum(4'b0111));
getRoundKeys g9(.outKey(invRoundKeys[255:128]), .inKey(invRoundKeys[383:256]), .roundNum(4'b1000));
getRoundKeys g10(.outKey(invRoundKeys[127:0]), .inKey(invRoundKeys[255:128]), .roundNum(4'b1001));
endmodule
| 7.079177 |
module subBytes (
output [127:0] sub,
input [127:0] data
);
sbox q0 (
.toReplace(data[127:120]),
.sub(sub[127:120])
);
sbox q1 (
.toReplace(data[119:112]),
.sub(sub[119:112])
);
sbox q2 (
.toReplace(data[111:104]),
.sub(sub[111:104])
);
sbox q3 (
.toReplace(data[103:96]),
.sub(sub[103:96])
);
sbox q4 (
.toReplace(data[95:88]),
.sub(sub[95:88])
);
sbox q5 (
.toReplace(data[87:80]),
.sub(sub[87:80])
);
sbox q6 (
.toReplace(data[79:72]),
.sub(sub[79:72])
);
sbox q7 (
.toReplace(data[71:64]),
.sub(sub[71:64])
);
sbox q8 (
.toReplace(data[63:56]),
.sub(sub[63:56])
);
sbox q9 (
.toReplace(data[55:48]),
.sub(sub[55:48])
);
sbox q10 (
.toReplace(data[47:40]),
.sub(sub[47:40])
);
sbox q11 (
.toReplace(data[39:32]),
.sub(sub[39:32])
);
sbox q12 (
.toReplace(data[31:24]),
.sub(sub[31:24])
);
sbox q13 (
.toReplace(data[23:16]),
.sub(sub[23:16])
);
sbox q14 (
.toReplace(data[15:8]),
.sub(sub[15:8])
);
sbox q16 (
.toReplace(data[7:0]),
.sub(sub[7:0])
);
endmodule
| 7.325733 |
module inv_round (
outRound,
data,
rKey
);
output [127:0] outRound;
input [127:0] rKey, data;
//wire [127:0] XORRound, inv_mixed, inv_shifted; //bug???
wire [127:0] XORRoundKey, inv_mixed, inv_shifted;
assign XORRoundKey = rKey ^ data;
inv_mixColumns imc1 (
.aNew(inv_mixed),
.a(XORRoundKey)
);
inv_shiftRow isr1 (
.data(inv_shifted),
.shifted(inv_mixed)
);
inv_subBytes isb1 (
.sub (outRound),
.data(inv_shifted)
);
endmodule
| 7.103645 |
module roundLast (
encryptedData,
data,
inKey,
roundNum
);
output [127:0] encryptedData;
input [127:0] data, inKey;
input [3:0] roundNum;
wire [127:0] sub, shifted, outKey;
getRoundKeys g1 (
.outKey(outKey),
.inKey(inKey),
.roundNum(roundNum)
);
subBytes sb1 (
.sub (sub),
.data(data)
);
shiftRow sr1 (
.shifted(shifted),
.data(sub)
);
assign encryptedData = outKey ^ shifted;
endmodule
| 6.623808 |
module aes_v1_latency (
input wire g_clk,
input wire g_resetn,
input wire valid, // Input data valid
input wire dec, // Encrypt (0) or decrypt (1)
input wire mix, // Do MixColumns (1) or SubBytes (0)
input wire [31:0] rs1, // Input source register
output wire ready, // Finished computing?
output wire [31:0] rd // Output destination register value.
);
// Enable the decryption instructions.
parameter DECRYPT_EN = 1;
wire decrypt = DECRYPT_EN && dec;
wire [7:0] rs1_0, rs1_1, rs1_2, rs1_3;
wire [7:0] rd_0, rd_1, rd_2, rd_3;
assign ready = valid;
assign {rs1_3, rs1_2, rs1_1, rs1_0} = rs1;
wire [31:0] result_subbytes = {rd_3, rd_2, rd_1, rd_0};
wire [31:0] result_mixcols;
assign rd = mix ? result_mixcols : result_subbytes;
aes_sbox #(
.DECRYPT_EN(DECRYPT_EN)
) i_aes_sbox_0 (
.in (rs1_0),
.inv(decrypt),
.out(rd_0)
);
aes_sbox #(
.DECRYPT_EN(DECRYPT_EN)
) i_aes_sbox_1 (
.in (rs1_1),
.inv(decrypt),
.out(rd_1)
);
aes_sbox #(
.DECRYPT_EN(DECRYPT_EN)
) i_aes_sbox_2 (
.in (rs1_2),
.inv(decrypt),
.out(rd_2)
);
aes_sbox #(
.DECRYPT_EN(DECRYPT_EN)
) i_aes_sbox_3 (
.in (rs1_3),
.inv(decrypt),
.out(rd_3)
);
aes_mixcolumn #(
.DECRYPT_EN(DECRYPT_EN)
) i_aes_mixcolumn (
.col_in(rs1),
.dec(decrypt),
.col_out(result_mixcols)
);
endmodule
| 7.517149 |
module aes_v1_size (
input wire g_clk,
input wire g_resetn,
input wire valid, // Input data valid
input wire dec, // Encrypt (0) or decrypt (1)
input wire mix, // Do MixColumns (1) or SubBytes (0)
input wire [31:0] rs1, // Input source register
output wire ready, // Finished computing?
output wire [31:0] rd // Output destination register value.
);
// Enable the decryption instructions.
parameter DECRYPT_EN = 1;
localparam FSM_IDLE = 3'd0;
localparam FSM_B0 = 3'd1;
localparam FSM_B1 = 3'd2;
localparam FSM_B2 = 3'd3;
localparam FSM_B3 = 3'd4;
reg [2:0] fsm;
reg [2:0] n_fsm;
wire [7:0] sb_in;
wire [7:0] sb_out;
wire decrypt = dec && DECRYPT_EN;
// Intermediate value storage registers.
reg [7:0] r0, r1, r2, r3;
wire [31:0] result_sb = {r3, r2, r1, r0};
wire [31:0] result_mc;
assign rd = mix ? result_mc : result_sb;
// Shift down RS1 per byte to get input to SBOX.
/* verilator lint_off WIDTH */
assign sb_in = rs1 >> {fsm, 3'b000};
/* verilator lint_on WIDTH */
// Have we finished computing every SBOX?
assign ready = mix ? 1'b1 : fsm == FSM_B3;
// Intermediate value load enable registers.
wire r0_ld_en = (fsm == FSM_IDLE) && valid;
wire r1_ld_en = (fsm == FSM_B0);
wire r2_ld_en = (fsm == FSM_B1);
wire r3_ld_en = (fsm == FSM_B2);
//
// FSM Next state.
always @(*) begin
case (fsm)
FSM_IDLE: n_fsm = valid && !mix ? FSM_B0 : FSM_IDLE;
FSM_B0: n_fsm = FSM_B1;
FSM_B1: n_fsm = FSM_B2;
FSM_B2: n_fsm = FSM_B3;
FSM_B3: n_fsm = FSM_IDLE;
default: n_fsm = FSM_IDLE;
endcase
end
//
// FSM State register progression.
always @(posedge g_clk) begin
if (!g_resetn) begin
fsm <= FSM_IDLE;
end else begin
fsm <= n_fsm;
end
end
//
// Intermediate value storage registers.
always @(posedge g_clk) begin
if (!g_resetn) begin
r0 <= 8'b0;
r1 <= 8'b0;
r2 <= 8'b0;
r3 <= 8'b0;
end else begin
if (r0_ld_en) r0 <= sb_out;
if (r1_ld_en) r1 <= sb_out;
if (r2_ld_en) r2 <= sb_out;
if (r3_ld_en) r3 <= sb_out;
end
end
//
// Single SBOX instance.
aes_sbox #(
.DECRYPT_EN(DECRYPT_EN)
) i_aes_sbox (
.in (sb_in),
.inv(decrypt),
.out(sb_out)
);
aes_mixcolumn #(
.DECRYPT_EN(DECRYPT_EN)
) i_aes_mixcolumn (
.col_in(rs1),
.dec(decrypt),
.col_out(result_mc)
);
endmodule
| 7.809908 |
module: aes_v2
//
// Latency (clock cycles) optimised.
//
module aes_v2_latency (
input wire g_clk ,
input wire g_resetn ,
input wire valid , // Are the inputs valid?
input wire sub , // Sub if set, Mix if clear
input wire enc , // Perform encrypt (set) or decrypt (clear).
input wire [31:0] rs1 , // Input source register 1
input wire [31:0] rs2 , // Input source register 2
output wire ready , // Is the instruction complete?
output wire [31:0] rd //
);
// Enable the decryption instructions.
parameter DECRYPT_EN=1;
// Single cycle implementation
assign ready = valid;
wire decrypt = !enc && DECRYPT_EN;
//
// SBox Instruction
// ------------------------------------------------------------
// Output of SBox Computation
wire [31:0] sb_out;
aes_sbox i_aes_sbox_0(.in (rs1[ 7: 0]), .inv(decrypt), .out(sb_out[ 7: 0]) );
aes_sbox i_aes_sbox_1(.in (rs2[15: 8]), .inv(decrypt), .out(sb_out[15: 8]) );
aes_sbox i_aes_sbox_2(.in (rs1[23:16]), .inv(decrypt), .out(sb_out[23:16]) );
aes_sbox i_aes_sbox_3(.in (rs2[31:24]), .inv(decrypt), .out(sb_out[31:24]) );
//
// Mix Instruction
// ------------------------------------------------------------
//
// Multiply by 2 in GF(2^8) modulo 8'h1b
function [7:0] xt2;
input [7:0] a;
xt2 = (a << 1) ^ (a[7] ? 8'h1b : 8'b0) ;
endfunction
//
// Paired down multiply by X in GF(2^8)
function [7:0] xtN;
input[7:0] a;
input[3:0] b;
xtN = (b[0] ? a : 0) ^
(b[1] ? xt2( a) : 0) ^
(b[2] ? xt2(xt2( a)) : 0) ^
(b[3] ? xt2(xt2(xt2(a))): 0) ;
endfunction
//
// Performs the mix column transformation on a single word.
function [7:0] mixcolumn_enc;
input [7:0] b0, b1, b2, b3;
mixcolumn_enc = xt2(b0) ^ (xt2(b1) ^ b1) ^ b2 ^ b3;
endfunction
//
// Performs the mix column transformation on a single word.
function [7:0] mixcolumn_dec;
input [7:0] b0, b1, b2, b3;
mixcolumn_dec = xtN(b0,4'he) ^ xtN(b1,4'hb) ^ xtN(b2,4'hd) ^ xtN(b3,4'h9);
endfunction
//
// Mix operation input selection
wire [ 7:0] mix_0 = rs1[ 7: 0];
wire [ 7:0] mix_1 = rs1[15: 8];
wire [ 7:0] mix_2 = rs2[23:16];
wire [ 7:0] mix_3 = rs2[31:24];
//
// Mix instruction - encrypt.
wire [ 7:0] mix_enc_0 = mixcolumn_enc(mix_0, mix_1, mix_2, mix_3);
wire [ 7:0] mix_enc_1 = mixcolumn_enc(mix_1, mix_2, mix_3, mix_0);
wire [ 7:0] mix_enc_2 = mixcolumn_enc(mix_2, mix_3, mix_0, mix_1);
wire [ 7:0] mix_enc_3 = mixcolumn_enc(mix_3, mix_0, mix_1, mix_2);
wire [31:0] mix_enc = {mix_enc_3, mix_enc_2, mix_enc_1, mix_enc_0};
//
// Mix instruction - decrypt.
wire [31:0] mix_dec ;
generate if(DECRYPT_EN) begin : decrypt_enabled_mix
wire [ 7:0] mix_dec_0 = mixcolumn_dec(mix_0, mix_1, mix_2, mix_3);
wire [ 7:0] mix_dec_1 = mixcolumn_dec(mix_1, mix_2, mix_3, mix_0);
wire [ 7:0] mix_dec_2 = mixcolumn_dec(mix_2, mix_3, mix_0, mix_1);
wire [ 7:0] mix_dec_3 = mixcolumn_dec(mix_3, mix_0, mix_1, mix_2);
assign mix_dec = {mix_dec_3, mix_dec_2, mix_dec_1, mix_dec_0};
end else begin : decrypt_disabled_mix
assign mix_dec = 32'b0;
end endgenerate
//
// Mix instruction - result
wire [31:0] mix_result = enc ? mix_enc : mix_dec;
//
// Result Selection
// ------------------------------------------------------------
assign rd = sub ? sb_out : mix_result;
endmodule
| 7.701265 |
module: aes_v2
//
// Size optimised
//
module aes_v2_size(
input wire g_clk ,
input wire g_resetn ,
input wire valid , // Are the inputs valid?
input wire sub , // Sub if set, Mix if clear
input wire [31:0] rs1 , // Input source register 1
input wire [31:0] rs2 , // Input source register 2
input wire enc , // Perform encrypt (set) or decrypt (clear).
output wire ready , // Is the instruction complete?
output wire [31:0] rd //
);
// Enable the decryption instructions.
parameter DECRYPT_EN=1;
wire decrypt = !enc && DECRYPT_EN;
//
// SBox Instruction
// ------------------------------------------------------------
wire [ 7:0] sb_in =
{8{fsm_idle}} & rs1[ 7: 0] |
{8{fsm_s1 }} & rs2[15: 8] |
{8{fsm_s2 }} & rs1[23:16] |
{8{fsm_s3 }} & rs2[31:24] ;
wire [ 7:0] sb_out ;
aes_sbox i_aes_sbox(.in (sb_in), .inv(decrypt), .out(sb_out) );
//
// MixColumns Instruction
// ------------------------------------------------------------
//
// Multiply by 2 in GF(2^8) modulo 8'h1b
function [7:0] xt2;
input [7:0] a;
xt2 = (a << 1) ^ (a[7] ? 8'h1b : 8'b0) ;
endfunction
//
// Paired down multiply by X in GF(2^8)
function [7:0] xtN;
input[7:0] a;
input[3:0] b;
xtN = (b[0] ? a : 0) ^
(b[1] ? xt2( a) : 0) ^
(b[2] ? xt2(xt2( a)) : 0) ^
(b[3] ? xt2(xt2(xt2(a))): 0) ;
endfunction
wire [ 7:0] mix_0 = rs1[ 7: 0];
wire [ 7:0] mix_1 = rs1[15: 8];
wire [ 7:0] mix_2 = rs2[23:16];
wire [ 7:0] mix_3 = rs2[31:24];
wire [ 7:0] mb0 = {8{fsm_idle}} & mix_0 |
{8{fsm_s1 }} & mix_1 |
{8{fsm_s2 }} & mix_2 |
{8{fsm_s3 }} & mix_3 ;
wire [ 7:0] mb1 = {8{fsm_idle}} & mix_1 |
{8{fsm_s1 }} & mix_2 |
{8{fsm_s2 }} & mix_3 |
{8{fsm_s3 }} & mix_0 ;
wire [ 7:0] mb2 = {8{fsm_idle}} & mix_2 |
{8{fsm_s1 }} & mix_3 |
{8{fsm_s2 }} & mix_0 |
{8{fsm_s3 }} & mix_1 ;
wire [ 7:0] mb3 = {8{fsm_idle}} & mix_3 |
{8{fsm_s1 }} & mix_0 |
{8{fsm_s2 }} & mix_1 |
{8{fsm_s3 }} & mix_2 ;
wire [31:0] mix_in = {mb0, mb1, mb2, mb3};
wire [ 7:0] mix_enc;
wire [ 7:0] mix_dec;
wire [ 7:0] mix_out = enc ? mix_enc : mix_dec;
aes_mixcolumn_byte_enc i_mc_enc(.col_in(mix_in), .byte_out(mix_enc));
generate if(DECRYPT_EN) begin : decrypt_enabled
aes_mixcolumn_byte_dec i_mc_dec(.col_in(mix_in), .byte_out(mix_dec));
end else begin : decrypt_disabled
assign mix_dec = 8'b0;
end endgenerate
//
// Temporary Storage
// ------------------------------------------------------------
reg [ 7:0] t0;
reg [ 7:0] t1;
reg [ 7:0] t2;
wire [ 7:0] n_tmp = sub ? sb_out : mix_out;
always @(posedge g_clk) if(fsm_idle && valid) t0 <= n_tmp;
always @(posedge g_clk) if(fsm_s1 ) t1 <= n_tmp;
always @(posedge g_clk) if(fsm_s2 ) t2 <= n_tmp;
//
// Control FSM
// ------------------------------------------------------------
reg [ 1:0] fsm;
reg [ 1:0] n_fsm;
localparam FSM_IDLE = 2'b00;
localparam FSM_S1 = 2'b01;
localparam FSM_S2 = 2'b10;
localparam FSM_S3 = 2'b11;
wire fsm_idle = fsm == FSM_IDLE;
wire fsm_s1 = fsm == FSM_S1 ;
wire fsm_s2 = fsm == FSM_S2 ;
wire fsm_s3 = fsm == FSM_S3 ;
assign ready = fsm_s3;
assign rd = {n_tmp, t2, t1, t0};
always @(*) case(fsm)
FSM_IDLE : n_fsm = valid ? FSM_S1 : FSM_IDLE;
FSM_S1 : n_fsm = FSM_S2;
FSM_S2 : n_fsm = FSM_S3;
FSM_S3 : n_fsm = FSM_IDLE;
endcase
always @(posedge g_clk) begin
if(!g_resetn) begin
fsm <= 2'b00;
end else begin
fsm <= n_fsm;
end
end
endmodule
| 7.701265 |
module aes_v3_1 (
input wire valid, // Are the inputs valid? Used for logic gating.
input wire dec, // Encrypt (clear) or decrypt (set)
input wire mix, // Perform MixColumn transformation (if set)
input wire [31:0] rs1, // Source register 1
input wire [31:0] rs2, // Source register 2
input wire [ 1:0] bs, // Byte select immediate
output wire [31:0] rd, // output destination register value.
output wire ready // Compute finished?
);
// Enable the decryption instructions.
parameter DECRYPT_EN = 1;
wire decrypt = dec && DECRYPT_EN;
wire [7:0] bytes_in [3:0] ;
// Always finish in a single cycle.
assign ready = valid;
assign bytes_in[0] = rs2[7:0];
assign bytes_in[1] = rs2[15:8];
assign bytes_in[2] = rs2[23:16];
assign bytes_in[3] = rs2[31:24];
wire [7:0] sel_byte = bytes_in[bs];
wire [7:0] sbox_out;
//
// Multiply by 2 in GF(2^8) modulo 8'h1b
function [7:0] xtime2;
input [7:0] a;
xtime2 = {a[6:0], 1'b0} ^ (a[7] ? 8'h1b : 8'b0);
endfunction
//
// Paired down multiply by X in GF(2^8)
function [7:0] xtimeN;
input [7:0] a;
input [3:0] b;
xtimeN = (b[0] ? a : 0) ^ (b[1] ? xtime2(
a
) : 0) ^ (b[2] ? xtime2(
xtime2(a)
) : 0) ^ (b[3] ? xtime2(
xtime2(xtime2(a))
) : 0);
endfunction
wire [7:0] mix_b3 = xtimeN(sbox_out, (decrypt ? 11 : 3));
wire [7:0] mix_b2 = decrypt ? xtimeN(sbox_out, (13)) : sbox_out;
wire [7:0] mix_b1 = decrypt ? xtimeN(sbox_out, (9)) : sbox_out;
wire [7:0] mix_b0 = xtimeN(sbox_out, (decrypt ? 14 : 2));
wire [31:0] result_mix = {mix_b3, mix_b2, mix_b1, mix_b0};
wire [31:0] result = mix ? result_mix : {24'b0, sbox_out};
wire [31:0] rotated =
{32{bs == 2'b00}} & {result } |
{32{bs == 2'b01}} & {result[23:0], result[31:24] } |
{32{bs == 2'b10}} & {result[15:0], result[31:16] } |
{32{bs == 2'b11}} & {result[ 7:0], result[31: 8] } ;
assign rd = rotated ^ rs1;
//
// Single SBOX instance
aes_sbox i_aes_sbox (
.inv(decrypt),
.in (sel_byte),
.out(sbox_out)
);
endmodule
| 7.298698 |
module AES_W (
Clock,
Reset,
DataIn,
DataInValid,
DataInReady,
Key,
DataOut,
DataOutValid
);
`include "PathORAM.vh"
parameter W = 1;
parameter AESWIn_Width = AESEntropy;
//--------------------------------------------------------------------------
// System I/O
//--------------------------------------------------------------------------
input Clock, Reset;
//--------------------------------------------------------------------------
// Interface 1
//--------------------------------------------------------------------------
input [AESWIn_Width-1:0] DataIn;
input DataInValid;
output DataInReady;
input [AESWidth-1:0] Key;
output [W*AESWidth-1:0] DataOut;
output DataOutValid;
//--------------------------------------------------------------------------
// wires and regs
//--------------------------------------------------------------------------
localparam D = 21;
wire ValidOut;
wire [W*AESWidth-1:0] AESRes;
//carry the valid signal from input for D cycles
ShiftRegister #(
.PWidth(D),
.SWidth(1)
) V_shift (
.Clock (Clock),
.Reset (Reset),
.Load (1'b0),
.Enable(1'b1),
.SIn (DataInValid),
.SOut (ValidOut)
);
genvar k;
generate
for (k = 0; k < W; k = k + 1) begin : AES
aes_128 aes (
.clk(Clock),
.state({
{(AESWidth - AESWIn_Width) {1'b0}}, DataIn
}), // TODO: 1'b0, the padding, should really be unique for each k
.key(Key),
.out(AESRes[(k+1)*AESWidth-1:k*AESWidth])
);
end
endgenerate
//IO assignment
assign DataInReady = 1'b1;
assign DataOut = AESRes;
assign DataOutValid = ValidOut;
endmodule
| 6.789286 |
module AFA (
input x1,
x2,
cin,
output sum,
cout
);
wire w;
assign w = x1 | x2;
assign sum = w ^ cin;
assign cout = w & cin;
endmodule
| 7.190925 |
module AFE_ADS_TOP (
//--- GLOBAL ---
input sys_rst_n, //reset input, low is valid
input sys_clk, //system clock
//--- AFE PORTS ---
//-- control ports --
output AFE_CLK, //outputs the analog voltage from each integrator channel on each rising edge
output AFE_INTG, //integrate pixel signal when high
output AFE_IRST, //Resets the AFE on rising edge
output AFE_SHS, //samples signal on rising edge
output AFE_SHR, //samples ‘reset’ level of integrator on rising edge
output AFE_PDZ, //power down set
output AFE_NAPZ, //sleep mode set
output AFE_ENTRI, //High on this pin enables tri-state of analog output drivers after shift out of data for all 64 channels
input AFE_STO,
input AFE_EOC,
//-- mode ports --
output AFE_SMT_MD, // read mode set
output AFE_INPUTZ,
//-- compensation set --
output AFE_DF_SM, //Digital control to dump compensation charge on integrator capacitor,
//-- PGA set --
output [2:0] AFE_PGA,
//--- ADS PORTS ---
output ADS_CLK,
output ADS_CS_N,
input ADS_BUSY,
output ADS_RD,
output ADS_SDI,
input ADS_SDOA,
input ADS_SDOB,
output [1:0] ADS_M,
output ADS_CONVST
);
wire CLK_100M, CLK_RST, CLK_ADS;
wire ADS_INIT_OK;
wire CLK_AFE;
wire [15:0] ADS_ADATA, ADS_BDATA;
wire ADS_AVLAID, ADS_BVLAID;
assign AFE_CLK = CLK_AFE;
CLK_GRT CLK_GRT (
.sys_rst_n(sys_rst_n),
.sys_clk (sys_clk),
.CLK_100M (CLK_100M),
.CLK_ADS (CLK_ADS),
.CLK_RST (CLK_RST)
);
AFE_CTL AFE_CTL (
.CLK_RST(CLK_RST),
.CLK_100M(CLK_100M),
.ADS_INIT_OK(ADS_INIT_OK),
.AFE_CLK(CLK_AFE),
.AFE_INTG(AFE_INTG),
.AFE_IRST(AFE_IRST),
.AFE_SHS(AFE_SHS),
.AFE_SHR(AFE_SHR),
.AFE_PDZ(AFE_PDZ),
.AFE_NAPZ(AFE_NAPZ),
.AFE_ENTRI(AFE_ENTRI),
.AFE_STI(AFE_STI),
.AFE_STO(AFE_STO),
.AFE_EOC(AFE_EOC),
.AFE_SMT_MD(AFE_SMT_MD),
.AFE_INPUTZ(AFE_INPUTZ),
.AFE_DF_SM(AFE_DF_SM),
.AFE_PGA(AFE_PGA)
);
ADS_CTL ADS_CTL (
.CLK_RST (CLK_RST),
.CLK_ADS (CLK_ADS),
.CLK_AFE (CLK_AFE),
.CLK_100M (CLK_100M),
.ADS_CLK (ADS_CLK),
.ADS_CS_N (ADS_CS_N),
.ADS_BUSY (ADS_BUSY),
.ADS_RD (ADS_RD),
.ADS_SDI (ADS_SDI),
.ADS_SDOA (ADS_SDOA),
.ADS_SDOB (ADS_SDOB),
.ADS_M (ADS_M),
.ADS_CONVST (ADS_CONVST),
.ADS_ADATA (ADS_ADATA),
.ADS_AVLAID (ADS_AVLAID),
.ADS_BDATA (ADS_BDATA),
.ADS_BVLAID (ADS_BVLAID),
.ADS_INIT_OK(ADS_INIT_OK)
);
endmodule
| 7.459986 |
module afe_command_controller (
input clk,
reset_n,
input enable,
input serial_ready,
input [3:0] command,
output [7:0] rom_address,
output start_transaction,
output done
);
// Controller commands from afe_command_rom
parameter COMMAND_TO_SEND = 4'b0001, SEQUENCE_DONE = 4'b0000;
// State machine parameterized states
parameter
init_state = 3'd0,
wait_state = 3'd1,
fetch_state = 3'd2,
trigger_state = 3'd3,
delay_state = 3'd4,
increment_state = 3'd5,
done_state = 3'd6;
// State machine state storage
reg [2:0] state, next_state;
// System outputs
reg start_transaction_reg, done_reg;
reg [7:0] current_address;
assign start_transaction = start_transaction_reg;
assign done = done_reg;
assign rom_address = current_address;
// State machine control
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
state <= init_state;
end else begin
state <= next_state;
end
end
// Combinational next-state calculation
always @(state, enable, serial_ready, command) begin
case (state)
init_state: begin
if (enable) begin
// Once enabled, can wait for serial module to be ready
next_state = wait_state;
end else begin
next_state = init_state;
end
end
wait_state: begin
if (serial_ready) begin
// When the serial is ready, fetch the next command
next_state = fetch_state;
end else begin
next_state = wait_state;
end
end
fetch_state: begin
if (command == COMMAND_TO_SEND) begin
// With a valid command, trigger the serial module
next_state = trigger_state;
end else if (command == SEQUENCE_DONE) begin
next_state = done_state;
end else begin
// Terminate on invalid state machine command
next_state = done_state;
end
end
trigger_state: begin
// Always transition to delay before incrementing
next_state = delay_state;
end
delay_state: begin
// Always transition to increment
next_state = increment_state;
end
increment_state: begin
// Always transition to wait for next serial_ready
next_state = wait_state;
end
// done_state uses default
default: begin
next_state = done_state;
end
endcase
end
// Control all the outputs based on state machine
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
current_address <= 7'b0;
start_transaction_reg <= 1'b0;
done_reg <= 1'b0;
end else begin
// Control the current_address
case (state)
increment_state: begin
current_address <= current_address + 1'b1;
end
default: begin
current_address <= current_address;
end
endcase
// Control the start_transaction
case (state)
trigger_state: begin
start_transaction_reg <= 1'b1;
end
default: begin
start_transaction_reg <= 1'b0;
end
endcase
// Control the done
case (state)
done_state: begin
done_reg <= 1'b1;
end
default: begin
done_reg <= 1'b0;
end
endcase
end
end
endmodule
| 8.070643 |
module afe_command_rom (
input clk,
reset_n,
input [7:0] address,
output [3:0] controller_command,
output [19:0] afe_shift_data
);
// Memory variable
reg [23:0] rom[255:0];
reg [23:0] command_reg;
assign controller_command = command_reg[23:20];
assign afe_shift_data = command_reg[19:0];
// ROM initialization
initial begin
// Read hex memory from file
// Relative path from this Verilog file
$readmemh("../rom_data/afe_configuration_rom_data.txt", rom);
end
// ROM controller
always @(posedge clk) begin
command_reg <= rom[address];
end
endmodule
| 7.26605 |
module afe_configure (
input clk,
reset_n,
input miso,
output device_reset,
output pdn,
output cs_n,
output mosi,
output device_sync,
output configure_done
);
wire reset_done;
wire transaction_done;
wire start_transaction;
wire command_transactions_done;
assign configure_done = command_transactions_done;
assign pdn = ~configure_done;
wire [ 3:0] controller_command;
wire [19:0] afe_command;
wire [ 7:0] rom_address;
afe_reset_timer reset_timer (
.clk(clk),
.reset_n(reset_n),
.device_reset(device_reset),
.done(reset_done)
);
afe_sync sync (
.clk(clk),
.reset_n(reset_n),
.enable(command_transactions_done),
.sync(device_sync)
);
afe_command_controller command_controller (
.clk(clk),
.reset_n(reset_n),
.enable(reset_done),
.serial_ready(transaction_done),
.command(controller_command),
.rom_address(rom_address),
.start_transaction(start_transaction),
.done(command_transactions_done)
);
afe_command_rom command_rom (
.clk(clk),
.reset_n(reset_n),
.address(rom_address),
.controller_command(controller_command),
.afe_shift_data(afe_command)
);
afe_serial_out serial_out (
.clk(clk),
.reset_n(reset_n),
.enable(reset_done),
.start_transaction(start_transaction),
.parallel_input(afe_command),
.cs_n(cs_n),
.mosi(mosi),
.transaction_done(transaction_done)
);
endmodule
| 6.541046 |
module afe_reset_timer (
input clk,
reset_n,
output device_reset,
output done
);
reg [15:0] counter;
reg device_reset_reg, done_reg;
assign device_reset = device_reset_reg;
assign done = done_reg;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
counter <= 16'hFFFF;
device_reset_reg <= 1'b1; // Default to resetting device
done_reg <= 1'b0;
end else begin
// Count down, then stop
if (counter != 16'b0) begin
counter <= counter - 1'b1;
end
// Run the reset for some more cycles
if (counter > 16'hFFF0) begin
// Maintaining active-high reset
device_reset_reg <= 1'b1;
end else begin
device_reset_reg <= 1'b0;
end
// Declare the reset done when the counter hits zero
done_reg <= (counter == 16'b0);
end
end
endmodule
| 6.613985 |
module afe_serial_out (
input clk,
reset_n,
input enable,
input start_transaction,
input [19:0] parallel_input,
output cs_n,
output mosi,
output transaction_done
);
// State machine parameterized states
parameter idle_state = 3'd0, load_state = 3'd1, shifting_state = 3'd2, delay_state = 3'd3;
reg cs_reg, transaction_done_reg;
assign cs_n = ~cs_reg; // Active low conversion
assign transaction_done = transaction_done_reg;
// State machine state storage
reg [2:0] state, next_state;
reg [4:0] shift_out_count;
// State machine internal control signals
reg enable_shift, load_shift;
// Manual instantiation of the lpm_shiftreg
lpm_shiftreg shiftreg20 (
.clock(clk),
.aclr(~reset_n),
.data(parallel_input),
.load(load_shift),
.enable(enable_shift),
.shiftout(mosi)
// synopsys translate_off
, .aset(),
.q(),
.sclr(),
.shiftin(),
.sset()
// synopsys translate_on
);
defparam shiftreg20.lpm_direction = "LEFT", shiftreg20.lpm_type = "LPM_SHIFTREG",
shiftreg20.lpm_width = 20;
// Registered processes
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
state <= idle_state;
enable_shift <= 1'b0;
load_shift <= 1'b0;
shift_out_count <= 5'b0;
transaction_done_reg <= 1'b0;
cs_reg <= 1'b0;
end else begin
state <= next_state;
case (state)
idle_state: begin
enable_shift <= 1'b0;
load_shift <= 1'b0;
shift_out_count <= 5'd19;
// disable done-ness when starting
transaction_done_reg <= ~start_transaction;
cs_reg <= 1'b0;
end
load_state: begin
enable_shift <= 1'b1;
load_shift <= 1'b1;
shift_out_count <= 5'd19;
transaction_done_reg <= 1'b0;
cs_reg <= 1'b0;
end
shifting_state: begin
enable_shift <= 1'b1;
load_shift <= 1'b0;
shift_out_count <= shift_out_count - 1'b1;
transaction_done_reg <= 1'b0;
cs_reg <= 1'b1;
end
// delay_state uses default
default: begin
enable_shift <= 1'b0;
load_shift <= 1'b0;
shift_out_count <= 5'd19;
transaction_done_reg <= 1'b1;
cs_reg <= 1'b0;
end
endcase
end
end
// Combinational next-state calculation
always @(state, start_transaction, shift_out_count, enable) begin
case (state)
idle_state: begin
if (start_transaction & enable) begin
next_state = load_state;
end else begin
next_state = idle_state;
end
end
load_state: begin
next_state = shifting_state;
end
shifting_state: begin
if (shift_out_count == 1'b0) begin
next_state = delay_state;
end else begin
// A single cycle to ensure deadtime between transactions
next_state = shifting_state;
end
end
// delay_state uses default
default: begin
next_state = idle_state;
end
endcase
end
endmodule
| 8.216108 |
module AFIFO #(
parameter DSIZE = 8,
parameter ASIZE = 4
) (
//Input Port
rst_n,
//Input Port (read)
rclk,
rinc,
//Input Port (write)
wclk,
winc,
wdata,
//Output Port (read)
rempty,
rdata,
//Output Port (write)
wfull
);
//-----------------------------------------------------------------------------------------------------------------
// PORT DECLARATION
//-----------------------------------------------------------------------------------------------------------------
input rst_n, rclk, rinc, wclk, winc;
input [DSIZE-1:0] wdata;
output rempty, wfull;
output [DSIZE-1:0] rdata;
//-----------------------------------------------------------------------------------------------------------------
// LOGIC DECLARATION
//-----------------------------------------------------------------------------------------------------------------
wire [ASIZE-1:0] waddr, raddr;
wire [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr;
//-----------------------------------------------------------------------------------------------------------------
// Design
//-----------------------------------------------------------------------------------------------------------------
sync_r2w sync_r2w_m0 (
.wq2_rptr(wq2_rptr),
.rptr(rptr),
.wclk(wclk),
.rst_n(rst_n)
);
sync_w2r sync_w2r_m0 (
.rq2_wptr(rq2_wptr),
.wptr(wptr),
.rclk(rclk),
.rst_n(rst_n)
);
fifomem #(DSIZE, ASIZE) fifomem_m0 (
.rdata (rdata),
.wdata (wdata),
.waddr (waddr),
.raddr (raddr),
.wclken(winc),
.wfull (wfull),
.wclk (wclk)
);
rptr_empty #(ASIZE) rptr_empty_m0 (
.rempty(rempty),
.raddr(raddr),
.rptr(rptr),
.rq2_wptr(rq2_wptr),
.rinc(rinc),
.rclk(rclk),
.rst_n(rst_n)
);
wptr_full #(ASIZE) wptr_full_m0 (
.wfull(wfull),
.waddr(waddr),
.wptr(wptr),
.wq2_rptr(wq2_rptr),
.winc(winc),
.wclk(wclk),
.rst_n(rst_n)
);
endmodule
| 7.320306 |
module afifo16 (
reset_ni,
rd_clk_i,
rd_en_i,
rd_data_o,
wr_clk_i,
wr_en_i,
wr_data_i,
rempty_o,
wfull_o
);
parameter WIDTH = 16;
input reset_ni;
input rd_clk_i;
input rd_en_i;
output [WIDTH-1:0] rd_data_o;
input wr_clk_i;
input wr_en_i;
input [WIDTH-1:0] wr_data_i;
output rempty_o;
output wfull_o;
fifo_dc_gray #(WIDTH, 4, 16) FIFO0 (
.rd_clk(rd_clk_i),
.wr_clk(wr_clk_i),
.rst(reset_ni),
.clr(1'b0),
.din(wr_data_i),
.we(wr_en_i),
.dout(rd_data_o),
.re(rd_en_i),
.full(wfull_o),
.empty(rempty_o),
.wr_level(),
.rd_level()
);
endmodule
| 6.586682 |
module afifo18 (
input wire [17:0] Data,
input wire WrClock,
input wire RdClock,
input wire WrEn,
input wire RdEn,
input wire Reset,
input wire RPReset,
output wire [17:0] Q,
output wire Empty,
output wire Full
);
asfifo #(
.DATA_WIDTH(18),
.ADDRESS_WIDTH(13)
) asfifo_inst (
.dout(Q),
.empty(Empty),
.rd_en(RdEn),
.rd_clk(RdClock),
.din(Data),
.full(Full),
.wr_en(WrEn),
.wr_clk(WrClock),
.rst(Reset)
);
endmodule
| 6.847937 |
module afifo18_7 (
input wire [17:0] Data,
input wire WrClock,
input wire RdClock,
input wire WrEn,
input wire RdEn,
input wire Reset,
input wire RPReset,
output wire [17:0] Q,
output wire Empty,
output wire Full
);
asfifo #(
.DATA_WIDTH(18),
.ADDRESS_WIDTH(7)
) asfifo_inst (
.dout(Q),
.empty(Empty),
.rd_en(RdEn),
.rd_clk(RdClock),
.din(Data),
.full(Full),
.wr_en(WrEn),
.wr_clk(WrClock),
.rst(Reset)
);
endmodule
| 6.903262 |
module afifo72_w156_r250 (
input wire rst,
input wire wr_clk,
input wire rd_clk,
input wire [71:0] din,
input wire wr_en,
input wire rd_en,
output wire [71:0] dout,
output wire full,
output wire empty
);
asfifo #(
.DATA_WIDTH(72),
.ADDRESS_WIDTH(12)
) asfifo_inst (
.dout(dout),
.empty(empty),
.rd_en(rd_en),
.rd_clk(rd_clk),
.din(din),
.full(full),
.wr_en(wr_en),
.wr_clk(wr_clk),
.rst(rst)
);
endmodule
| 7.091994 |
module afifo72_w250_r156 (
input wire rst,
input wire wr_clk,
input wire rd_clk,
input wire [71:0] din,
input wire wr_en,
input wire rd_en,
output wire [71:0] dout,
output wire full,
output wire empty
);
asfifo #(
.DATA_WIDTH(72),
.ADDRESS_WIDTH(12)
) asfifo_inst (
.dout(dout),
.empty(empty),
.rd_en(rd_en),
.rd_clk(rd_clk),
.din(din),
.full(full),
.wr_en(wr_en),
.wr_clk(wr_clk),
.rst(rst)
);
endmodule
| 7.083324 |
module afifo9 (
input wire [8:0] Data,
input wire WrClock,
input wire RdClock,
input wire WrEn,
input wire RdEn,
input wire Reset,
input wire RPReset,
output wire [8:0] Q,
output wire Empty,
output wire Full
);
asfifo #(
.DATA_WIDTH(9),
.ADDRESS_WIDTH(10)
) asfifo_inst (
.dout(Q),
.empty(Empty),
.rd_en(RdEn),
.rd_clk(RdClock),
.din(Data),
.full(Full),
.wr_en(WrEn),
.wr_clk(WrClock),
.rst(Reset)
);
endmodule
| 7.060125 |
module afifo_16i_64o_256 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [63:0] q;
output rdempty;
output [5:0] rdusedw;
output wrfull;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [63:0] sub_wire0;
wire sub_wire1;
wire [5:0] sub_wire2;
wire sub_wire3;
wire [7:0] sub_wire4;
wire [63:0] q = sub_wire0[63:0];
wire rdempty = sub_wire1;
wire [5:0] rdusedw = sub_wire2[5:0];
wire wrfull = sub_wire3;
wire [7:0] wrusedw = sub_wire4[7:0];
dcfifo_mixed_widths dcfifo_mixed_widths_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdusedw (sub_wire2),
.wrfull (sub_wire3),
.wrusedw (sub_wire4),
.eccstatus (),
.rdfull (),
.wrempty ());
defparam
dcfifo_mixed_widths_component.intended_device_family = "Cyclone IV E",
dcfifo_mixed_widths_component.lpm_numwords = 256,
dcfifo_mixed_widths_component.lpm_showahead = "OFF",
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
dcfifo_mixed_widths_component.lpm_width = 16,
dcfifo_mixed_widths_component.lpm_widthu = 8,
dcfifo_mixed_widths_component.lpm_widthu_r = 6,
dcfifo_mixed_widths_component.lpm_width_r = 64,
dcfifo_mixed_widths_component.overflow_checking = "ON",
dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
dcfifo_mixed_widths_component.read_aclr_synch = "OFF",
dcfifo_mixed_widths_component.underflow_checking = "ON",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
endmodule
| 6.691314 |
module afifo_16_256 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw
);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [7:0] rdusedw;
output wrfull;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire sub_wire1;
wire [7:0] sub_wire2;
wire sub_wire3;
wire [7:0] sub_wire4;
wire [15:0] q = sub_wire0[15:0];
wire rdempty = sub_wire1;
wire [7:0] rdusedw = sub_wire2[7:0];
wire wrfull = sub_wire3;
wire [7:0] wrusedw = sub_wire4[7:0];
dcfifo dcfifo_component (
.aclr(aclr),
.data(data),
.rdclk(rdclk),
.rdreq(rdreq),
.wrclk(wrclk),
.wrreq(wrreq),
.q(sub_wire0),
.rdempty(sub_wire1),
.rdusedw(sub_wire2),
.wrfull(sub_wire3),
.wrusedw(sub_wire4),
.eccstatus(),
.rdfull(),
.wrempty()
);
defparam dcfifo_component.intended_device_family = "Cyclone IV E",
dcfifo_component.lpm_numwords = 256, dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 16,
dcfifo_component.lpm_widthu = 8, dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4, dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF", dcfifo_component.wrsync_delaypipe = 4;
endmodule
| 6.557148 |
module afifo_16_512 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw
);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [8:0] rdusedw;
output wrfull;
output [8:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire sub_wire1;
wire [8:0] sub_wire2;
wire sub_wire3;
wire [8:0] sub_wire4;
wire [15:0] q = sub_wire0[15:0];
wire rdempty = sub_wire1;
wire [8:0] rdusedw = sub_wire2[8:0];
wire wrfull = sub_wire3;
wire [8:0] wrusedw = sub_wire4[8:0];
dcfifo dcfifo_component (
.aclr(aclr),
.data(data),
.rdclk(rdclk),
.rdreq(rdreq),
.wrclk(wrclk),
.wrreq(wrreq),
.q(sub_wire0),
.rdempty(sub_wire1),
.rdusedw(sub_wire2),
.wrfull(sub_wire3),
.wrusedw(sub_wire4),
.eccstatus(),
.rdfull(),
.wrempty()
);
defparam dcfifo_component.intended_device_family = "Cyclone IV E",
dcfifo_component.lpm_numwords = 512, dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 16,
dcfifo_component.lpm_widthu = 9, dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4, dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF", dcfifo_component.wrsync_delaypipe = 4;
endmodule
| 6.948456 |
module afifo_64i_16o_64 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [63:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [7:0] rdusedw;
output wrfull;
output [5:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire sub_wire1;
wire [7:0] sub_wire2;
wire sub_wire3;
wire [5:0] sub_wire4;
wire [15:0] q = sub_wire0[15:0];
wire rdempty = sub_wire1;
wire [7:0] rdusedw = sub_wire2[7:0];
wire wrfull = sub_wire3;
wire [5:0] wrusedw = sub_wire4[5:0];
dcfifo_mixed_widths dcfifo_mixed_widths_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdusedw (sub_wire2),
.wrfull (sub_wire3),
.wrusedw (sub_wire4),
.eccstatus (),
.rdfull (),
.wrempty ());
defparam
dcfifo_mixed_widths_component.intended_device_family = "Cyclone IV E",
dcfifo_mixed_widths_component.lpm_numwords = 64,
dcfifo_mixed_widths_component.lpm_showahead = "OFF",
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
dcfifo_mixed_widths_component.lpm_width = 64,
dcfifo_mixed_widths_component.lpm_widthu = 6,
dcfifo_mixed_widths_component.lpm_widthu_r = 8,
dcfifo_mixed_widths_component.lpm_width_r = 16,
dcfifo_mixed_widths_component.overflow_checking = "ON",
dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
dcfifo_mixed_widths_component.read_aclr_synch = "OFF",
dcfifo_mixed_widths_component.underflow_checking = "ON",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
endmodule
| 6.9074 |
module afifo_8i_16o_1024 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [8:0] rdusedw;
output wrfull;
output [9:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire sub_wire1;
wire [8:0] sub_wire2;
wire sub_wire3;
wire [9:0] sub_wire4;
wire [15:0] q = sub_wire0[15:0];
wire rdempty = sub_wire1;
wire [8:0] rdusedw = sub_wire2[8:0];
wire wrfull = sub_wire3;
wire [9:0] wrusedw = sub_wire4[9:0];
dcfifo_mixed_widths dcfifo_mixed_widths_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdusedw (sub_wire2),
.wrfull (sub_wire3),
.wrusedw (sub_wire4),
.eccstatus (),
.rdfull (),
.wrempty ());
defparam
dcfifo_mixed_widths_component.intended_device_family = "Cyclone IV E",
dcfifo_mixed_widths_component.lpm_numwords = 1024,
dcfifo_mixed_widths_component.lpm_showahead = "OFF",
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
dcfifo_mixed_widths_component.lpm_width = 8,
dcfifo_mixed_widths_component.lpm_widthu = 10,
dcfifo_mixed_widths_component.lpm_widthu_r = 9,
dcfifo_mixed_widths_component.lpm_width_r = 16,
dcfifo_mixed_widths_component.overflow_checking = "ON",
dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
dcfifo_mixed_widths_component.read_aclr_synch = "OFF",
dcfifo_mixed_widths_component.underflow_checking = "ON",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
endmodule
| 7.262557 |
module afifo_8i_16o_1024 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw
);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [8:0] rdusedw;
output wrfull;
output [9:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 7.262557 |
module afifo_8i_32o_1024 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output [7:0] rdusedw;
output wrfull;
output [9:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire sub_wire1;
wire [7:0] sub_wire2;
wire sub_wire3;
wire [9:0] sub_wire4;
wire [31:0] q = sub_wire0[31:0];
wire rdempty = sub_wire1;
wire [7:0] rdusedw = sub_wire2[7:0];
wire wrfull = sub_wire3;
wire [9:0] wrusedw = sub_wire4[9:0];
dcfifo_mixed_widths dcfifo_mixed_widths_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdusedw (sub_wire2),
.wrfull (sub_wire3),
.wrusedw (sub_wire4),
.eccstatus (),
.rdfull (),
.wrempty ());
defparam
dcfifo_mixed_widths_component.intended_device_family = "Cyclone IV E",
dcfifo_mixed_widths_component.lpm_numwords = 1024,
dcfifo_mixed_widths_component.lpm_showahead = "OFF",
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
dcfifo_mixed_widths_component.lpm_width = 8,
dcfifo_mixed_widths_component.lpm_widthu = 10,
dcfifo_mixed_widths_component.lpm_widthu_r = 8,
dcfifo_mixed_widths_component.lpm_width_r = 32,
dcfifo_mixed_widths_component.overflow_checking = "ON",
dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
dcfifo_mixed_widths_component.read_aclr_synch = "OFF",
dcfifo_mixed_widths_component.underflow_checking = "ON",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
endmodule
| 7.218815 |
module afifo_8i_32o_1024 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw
);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output [7:0] rdusedw;
output wrfull;
output [9:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 7.218815 |
module gray_counter_assim #(
parameter COUNTER_WIDTH = 4
) (
input wire rst, //Count reset.
input wire clk,
input wire en, //Count enable.
output [COUNTER_WIDTH-1:0] data_out
);
reg [COUNTER_WIDTH-1:0] bin_counter;
reg [COUNTER_WIDTH-1:0] gray_counter;
assign data_out = gray_counter;
always @(posedge clk, posedge rst)
if (rst) begin
bin_counter <= 1;
gray_counter <= 0;
end else if (en) begin
bin_counter <= bin_counter + 1'b1;
gray_counter <= {
bin_counter[COUNTER_WIDTH-1],
bin_counter[COUNTER_WIDTH-2:0] ^ bin_counter[COUNTER_WIDTH-1:1]
};
end
endmodule
| 7.789595 |
module afifo_assim_tb;
//Inputs
reg reset;
reg read;
bit rclk;
reg [`W_DATA_W-1:0] data_in;
reg write;
bit wclk;
//Outputs
reg [`R_DATA_W-1:0] data_out;
wire empty_out;
wire [`R_ADDR_W-1:0] level_r;
wire full_out;
wire [`W_ADDR_W-1:0] level_w;
integer i;
parameter clk_per = 10; // clk period = 10 timeticks
initial begin
// optional VCD
`ifdef VCD
$dumpfile("afifo.vcd");
$dumpvars();
`endif
$display("%c[1;34m", 27);
`ifdef WR_RATIO
$display("Assimetric Asynchronout Fifo testbench.\n\tWR_RATIO=%0d", `WR_RATIO);
`else
$display("Assimetric Asynchronout Fifo testbench.\n\tRW_RATIO=%0d", `RW_RATIO);
`endif
$display("%c[0m", 27);
//Initialize Inputs
rclk = 0;
wclk = 1;
reset = 0;
data_in = 0;
read = 0;
write = 0;
//Write all the locations of FIFO
#clk_per;
@(posedge wclk) #1;
reset = 1;
@(posedge wclk) #1;
reset = 0;
@(posedge wclk) #1;
write = 1;
for (i = 0; i < 2 ** `W_ADDR_W - 1; i = i + 1) begin
if (level_w != i) begin
$display("Test failed: write error in data_in.\n \t i=%0d; data=%0d; level_w=%0d", i,
data_in, level_w);
$finish;
end
`ifdef WR_RATIO
data_in = i;
`else // RW_RATIO
data_in = i / `RW_RATIO * ((i % `RW_RATIO) == 0);
`endif
@(posedge wclk) #1;
end
@(posedge wclk) #1;
write = 0; //Fifo is now full
if (full_out != 1 || level_w != 2 ** `W_ADDR_W - 1) begin
$display("Test failed: fifo not full.");
$finish;
end
#clk_per @(posedge rclk) #1;
read = 1;
`ifdef WR_RATIO
//Read all the locations of RAM.
for (i = 0; i < `WR_RATIO * ((2 ** `W_ADDR_W) - 1); i = i + 1) begin
// Result will only be available in the next cycle
@(posedge rclk) #1;
if(data_out != i/`WR_RATIO*((i%`WR_RATIO)==0) || level_r != (((2**`W_ADDR_W)-1)*`WR_RATIO)-1-i) begin
$display(
"Test failed: read error in data_out.\n \t i=%0d; data=%0d; exp=%0d; lvl=%0d, levl=%0d",
i, data_out, i / `WR_RATIO * ((i % `WR_RATIO) == 0),
(((2 ** `W_ADDR_W) - 1) * `WR_RATIO) - i, level_r);
// $finish;
end
end
`else // RW_RATIO
//Read all the locations of RAM.
for (i = 0; i < ((2 ** `W_ADDR_W) / `RW_RATIO) - 1; i = i + 1) begin
// Result will only be available in the next cycle
@(posedge rclk) #1;
if (data_out != i || level_r != ((2 ** `R_ADDR_W) - 2) - i) begin
$display("Test failed: read error in data_out.\n \t i=%0d; data=%0d", i, data_out);
// $finish;
end
end
`endif
@(posedge rclk) #1;
read = 0; //Fifo is now empty
@(posedge rclk) #1;
if (empty_out != 1 || level_r != 0) begin
$display("Test failed: fifo not empty.\n \t");
$finish;
end
#clk_per $display("%c[1;34m", 27);
$display("Test completed successfully.");
$display("%c[0m", 27);
#(5 * clk_per) $finish;
end
// Instantiate the Unit Under Test (UUT)
iob_afifo_assim #(
.W_DATA_W(`W_DATA_W),
.R_DATA_W(`R_DATA_W),
.ADDR_W (`FIFO_ADDR_W)
) uut (
.rst(reset),
.data_out(data_out),
.empty(empty_out),
.level_r(level_r),
.read_en(read),
.rclk(rclk),
.data_in(data_in),
.full(full_out),
.level_w(level_w),
.write_en(write),
.wclk(wclk)
);
// system clock
always #(clk_per / 2) wclk = ~wclk;
always #(clk_per / 2) rclk = ~rclk;
endmodule
| 7.084496 |
module aFifo_negedge #(
parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 4,
FIFO_DEPTH = (1 << ADDRESS_WIDTH)
)
//Reading port
(
output wire [DATA_WIDTH-1:0] q,
output reg rdempty,
input wire rdreq,
input wire rdclk,
//Writing port.
input wire [DATA_WIDTH-1:0] data,
output reg wrfull,
input wire wrreq,
input wire wrclk,
input wire clear
);
/////Internal connections & variables//////
reg [DATA_WIDTH-1:0] Mem[FIFO_DEPTH-1:0];
wire [ADDRESS_WIDTH-1:0] pNextWordToWrite, pNextWordToRead;
wire EqualAddresses;
wire NextWriteAddressEn, NextReadAddressEn;
wire Set_Status, Rst_Status;
reg Status;
wire PresetFull, PresetEmpty;
reg q_int;
//////////////Code///////////////
//Data ports logic:
//(Uses a dual-port RAM).
//'q' logic:
always @(posedge rdclk, posedge rdclk) if (rdreq & !rdempty) q_int <= #5 Mem[pNextWordToRead];
assign #5 q = Mem[pNextWordToRead];
//'data' logic:
always @(posedge wrclk) if (wrreq & !wrfull) Mem[pNextWordToWrite] <= data;
//Fifo addresses support logic:
//'Next Addresses' enable logic:
assign NextWriteAddressEn = wrreq & ~wrfull;
assign NextReadAddressEn = rdreq & ~rdempty;
//Addreses (Gray counters) logic:
GrayCounter GrayCounter_pWr (
.GrayCount_out(pNextWordToWrite),
.Enable_in(NextWriteAddressEn),
.Clear_in (clear),
.Clk(wrclk)
);
GrayCounter GrayCounter_pRd (
.GrayCount_out(pNextWordToRead),
.Enable_in(NextReadAddressEn),
.Clear_in(clear),
.Clk(rdclk)
);
//'EqualAddresses' logic:
assign EqualAddresses = (pNextWordToWrite == pNextWordToRead);
//'Quadrant selectors' logic:
assign Set_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ~^ pNextWordToRead[ADDRESS_WIDTH-1]) &
(pNextWordToWrite[ADDRESS_WIDTH-1] ^ pNextWordToRead[ADDRESS_WIDTH-2]);
assign Rst_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ^ pNextWordToRead[ADDRESS_WIDTH-1]) &
(pNextWordToWrite[ADDRESS_WIDTH-1] ~^ pNextWordToRead[ADDRESS_WIDTH-2]);
//'Status' latch logic:
always @(Set_Status, Rst_Status, clear) //D Latch w/ Asynchronous Clear & Preset.
if (Rst_Status | clear) Status = 0; //Going 'Empty'.
else if (Set_Status) Status = 1; //Going 'Full'.
//'wrfull' logic for the writing port:
assign PresetFull = Status & EqualAddresses; //'Full' Fifo.
always @(posedge wrclk, posedge PresetFull, negedge Status) //D Flip-Flop w/ Asynchronous Preset.
if (PresetFull) wrfull <= 1;
else wrfull <= 0;
//'rdempty' logic for the reading port:
assign PresetEmpty = ~Status & EqualAddresses; //'Empty' Fifo.
always @(negedge rdclk, posedge PresetEmpty) //D Flip-Flop w/ Asynchronous Preset.
if (PresetEmpty) rdempty <= 1;
else rdempty <= 0;
endmodule
| 7.197214 |
module afifo_sync_dff (
clk_d,
rst_d_n,
init_d_n,
data_s,
test,
data_d
);
parameter WIDTH = 1; // RANGE 1 to 1024
parameter F_SYNC_TYPE = 2; // RANGE 0 to 4
parameter TST_MODE = 0; // RANGE 0 to 1
parameter VERIF_EN = 1; // RANGE 0 to 4
input clk_d; // clock input from destination domain
input rst_d_n; // active low asynchronous reset from destination domain
input init_d_n; // active low synchronous reset from destination domain
input [WIDTH-1:0] data_s; // data to be synchronized from source domain
input test; // test input
output [WIDTH-1:0] data_d; // data synchronized to destination domain
reg [WIDTH-1:0] sample_nsyncf;
reg [WIDTH-1:0] sample_syncf;
reg [WIDTH-1:0] sample_syncm1;
reg [WIDTH-1:0] sample_syncm2;
reg [WIDTH-1:0] sample_syncl;
reg [WIDTH-1:0] test_hold;
wire [WIDTH-1:0] tst_mode_selected;
wire [WIDTH-1:0] f_sync_type_is_0_data;
wire [WIDTH-1:0] next_sample_syncf;
wire [WIDTH-1:0] next_sample_syncm1;
wire [WIDTH-1:0] next_sample_syncm2;
wire [WIDTH-1:0] next_sample_syncl;
assign tst_mode_selected = (TST_MODE == 1) ? test_hold : data_s;
assign f_sync_type_is_0_data = (test == 1'b1) ? tst_mode_selected : data_s;
assign next_sample_syncf = (test == 1'b0) ? data_s : tst_mode_selected;
assign next_sample_syncm1 = ((F_SYNC_TYPE & 7) == 1) ? sample_nsyncf : sample_syncf;
assign next_sample_syncm2 = sample_syncm1;
assign next_sample_syncl = ((F_SYNC_TYPE & 7) == 3) ? sample_syncm1 :
((F_SYNC_TYPE & 7) == 4) ? sample_syncm2 : next_sample_syncm1;
always @(negedge clk_d or negedge rst_d_n) begin : PROC_negedge_registers
if (rst_d_n == 1'b0) begin
sample_nsyncf <= {WIDTH{1'b0}};
test_hold <= {WIDTH{1'b0}};
end else if (init_d_n == 1'b0) begin
sample_nsyncf <= {WIDTH{1'b0}};
test_hold <= {WIDTH{1'b0}};
end else begin
sample_nsyncf <= data_s;
test_hold <= data_s;
end
end
always @(posedge clk_d or negedge rst_d_n) begin : PROC_posedge_registers
if (rst_d_n == 1'b0) begin
sample_syncf <= {WIDTH{1'b0}};
sample_syncm1 <= {WIDTH{1'b0}};
sample_syncm2 <= {WIDTH{1'b0}};
sample_syncl <= {WIDTH{1'b0}};
end else if (init_d_n == 1'b0) begin
sample_syncf <= {WIDTH{1'b0}};
sample_syncm1 <= {WIDTH{1'b0}};
sample_syncm2 <= {WIDTH{1'b0}};
sample_syncl <= {WIDTH{1'b0}};
end else begin
sample_syncf <= next_sample_syncf;
sample_syncm1 <= next_sample_syncm1;
sample_syncm2 <= next_sample_syncm2;
sample_syncl <= next_sample_syncl;
end
end
assign data_d = ((F_SYNC_TYPE & 7) == 0) ? f_sync_type_is_0_data : sample_syncl;
endmodule
| 8.320194 |
module async_fifo_tb;
//Inputs
reg reset;
reg read;
bit rclk;
reg [`DATA_W-1:0] data_in;
reg write;
bit wclk;
//Outputs
reg [`DATA_W-1:0] data_out;
wire empty_out;
wire [`ADDR_W-1:0] level_r;
wire full_out;
wire [`ADDR_W-1:0] level_w;
integer i;
parameter clk_per = 10; // clk period = 10 timeticks
initial begin
// optional VCD
`ifdef VCD
$dumpfile("afifo.vcd");
$dumpvars();
`endif
//Initialize Inputs
rclk = 0;
wclk = 1;
reset = 0;
data_in = 0;
read = 0;
write = 0;
//Write all the locations of FIFO
#clk_per;
@(posedge wclk) #1;
reset = 1;
@(posedge wclk) #1;
reset = 0;
@(posedge wclk) #1;
write = 1;
for (i = 0; i < 15; i = i + 1) begin
if (level_w != i) begin
$display("Test failed: write error in data_in.\n \t i=%0d; data=%0d; level_w=%0d", i,
data_in, level_w);
$finish;
end
data_in = i;
@(posedge wclk) #1;
end
@(posedge wclk) #1;
write = 0; //Fifo is now full
if (full_out != 1 || level_w != 15) begin
$display("Test failed: fifo not full.");
$finish;
end
#clk_per @(posedge rclk) #1;
read = 1;
//Read all the locations of RAM.
for (i = 0; i < 15; i = i + 1) begin
// Result will only be available in the next cycle
@(posedge rclk) #1;
if (data_out != i || level_r != 14 - i) begin
$display("Test failed: read error in data_out.\n \t i=%0d; data=%0d", i, data_out);
$finish;
end
end
@(posedge rclk) #1;
read = 0; //Fifo is now empty
@(posedge rclk) #1;
if (empty_out != 1 || level_r != 0) begin
$display("Test failed: fifo not empty.\n \t");
$finish;
end
#clk_per $display("%c[1;34m", 27);
$display("Test completed successfully.");
$display("%c[0m", 27);
#(5 * clk_per) $finish;
end
// Instantiate the Unit Under Test (UUT)
iob_async_fifo #(
.DATA_WIDTH(`DATA_W),
.ADDRESS_WIDTH(`ADDR_W)
) uut (
.rst(reset),
.data_out(data_out),
.empty(empty_out),
.level_r(level_r),
.read_en(read),
.rclk(rclk),
.data_in(data_in),
.full(full_out),
.level_w(level_w),
.write_en(write),
.wclk(wclk)
);
// system clock
always #(clk_per / 2) wclk = ~wclk;
always #(clk_per / 2) rclk = ~rclk;
endmodule
| 6.523155 |
modules just wrap around. Only deadly if
// run_filter _doesn't_ show up more often than every 1024 cycles.
module afilter_siso #(
parameter pcw = 10
) (
input clk,
input reset, // XXX unimplemented, would be nice to have the ability to force filter state to zero
input run_filter,
input signed [17:0] u_in,
output signed [17:0] y_out,
output filter_done,
output res_clip, // raw, not latched, warning signal that saturation happened
`AUTOMATIC_self
);
// Create suitably timed start pulses for three submodules
wire start_out, start_res, start_dot;
reg_delay #(.dw(1), .len(3)) start_out_g(.clk(clk), .reset(1'b0), .gate(1'b1), .din(run_filter), .dout(start_out));
reg_delay #(.dw(1), .len(1)) start_res_g(.clk(clk), .reset(1'b0), .gate(1'b1), .din(run_filter), .dout(start_res));
reg_delay #(.dw(1), .len(10)) start_dot_g(.clk(clk), .reset(1'b0), .gate(1'b1), .din(run_filter), .dout(start_dot));
// Take input detuning, expand to drive each filter
wire signed [17:0] x_drive;
(* lb_automatic *)
outer_prod #(.pcw(pcw)) outer_prod // auto
(.clk(clk), .start(start_out),
.x(u_in), .result(x_drive),
`AUTOMATIC_outer_prod
);
// Filter bank
wire signed [17:0] res_x;
(* lb_automatic *)
resonator #(.pcw(pcw)) resonator // auto
(.clk(clk), .start(start_res),
.drive(x_drive),
.position(res_x), .clip(res_clip),
`AUTOMATIC_resonator
);
// Combine bank results to get piezo drive
(* lb_automatic *)
dot_prod #(.pcw(pcw)) dot // auto
(.clk(clk), .start(start_dot), .x(res_x),
.result(y_out), .strobe(filter_done),
`AUTOMATIC_dot
);
endmodule
| 7.235163 |
module afilter_siso_tb;
reg clk;
wire lb_clk = clk;
integer cc;
`ifdef SIMULATE
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("afilter_siso.vcd");
$dumpvars(5, afilter_siso_tb);
end
for (cc = 0; cc < 400; cc = cc + 1) begin
clk = 0;
#4;
clk = 1;
#4;
end
$display(
"WARNING: Not a self-checking testbench. Will always PASS. Relies on external post-processing.");
$display("PASS");
end
`endif // `ifdef SIMULATE
// Local bus
reg [31:0] lb_data = 0;
reg [14:0] lb_addr = 0;
reg lb_write = 0;
`AUTOMATIC_decode
// DSP trigger
reg run_filter = 0;
always @(posedge clk) run_filter <= (cc % 20 == 3) && (cc > 50);
reg signed [17:0] u_in = 0;
always @(posedge clk) if (cc > 60) u_in <= 30000;
// always @(posedge clk) u_in <= 9000+cc;
// Device Under Test
wire filter_done, res_clip;
wire signed [17:0] y_out;
(* lb_automatic *)
afilter_siso afilter_siso // auto
(
.clk(clk),
.reset(1'b0),
.run_filter(run_filter),
.u_in(u_in),
.y_out(y_out),
.filter_done(filter_done),
.res_clip(res_clip),
`AUTOMATIC_afilter_siso
);
`ifdef SIMULATE
// Read localbus commands from external file
reg [255:0] file1_name;
integer file1;
initial begin
if (!$value$plusargs("dfile=%s", file1_name)) file1_name = "afilter_siso_in.dat";
file1 = $fopen(file1_name, "r");
end
integer rc = 2;
integer ca, cd;
integer control_cnt = 0;
integer wait_horizon = 5;
always @(posedge clk) begin
lb_write <= 0;
lb_data <= 32'bx;
lb_addr <= 15'bx;
control_cnt <= control_cnt + 1;
if (control_cnt > wait_horizon && control_cnt % 3 == 1 && rc == 2) begin
`ifdef SIMULATE
rc = $fscanf(file1, "%d %x\n", ca, cd);
`endif
if (rc == 2) begin
// https://en.wikipedia.org/wiki/555_timer_IC
if (ca == 555) begin
$display("stall %d cycles", cd);
wait_horizon = control_cnt + cd;
end else begin
$display("local bus[%d] = 0x%x (%d)", ca, cd, cd);
lb_addr <= ca;
lb_data <= cd;
lb_write <= 1;
end
end
end
end
always @(negedge clk) if (filter_done) $display("output %d %d", $time, y_out);
`endif
endmodule
| 6.554122 |
module is Offset Binary
// [It is perhaps stupid to have that here and it should be moved into another module]
// CONCEPT: The mid point along the circle of a of 2 complex numbers that already lie
// on a circle is not a plain average. To obtain the (real/imaginary) component
// of this mid-point one has to multiply by what is called "coeff"
// k = 0.5*sec(theta) .. where theta is the angle between the complex numbers
`timescale 1ns / 1ns
module afterburner(
input clk, // timespec 6.0 ns
input signed [16:0] data, // This is level set data [.. a_n1, a_n2 ..]
input signed [15:0] coeff, // Coefficient to correct for interpolation
output [15:0] data_out0, // Interpolated [coeff*[..(a_n1+a_n2), (a_n2+a_n3),..]]
output [15:0] data_out1 // Untouched [.. a_n1, a_n2 ..]
);
parameter triple=0;
// concept: a1 k*(a1+a2) a2 k*(a2+a3) a3 ...
// where k = 0.5*sec(theta) = 0.5*sec(2*pi*11/28) = -0.63952
// to handle 55 MHz output at 70 MHz clk (140 MS/s data rate to DAC)
// num = 2 % or 8 for L-band
// den = 11
// coeff = floor(32768*0.5*sec(pi*num/den)+0.5)
// 19476 % or -25019 for L-band
reg signed [17:0] avg=0;
reg signed [16:0] data1=0, data2=0, data3=0, data4=0;
wire signed [16:0] thru = triple ? data4 : data3;
reg signed [33:0] prod=0;
reg signed [15:0] sat=0;
always @(posedge clk) begin
data1 <= data;
data2 <= data1;
data3 <= data2;
data4 <= data3;
avg <= data + (triple ? data3 : data1);
prod <= avg * coeff; // scale by 32768
sat <= (~(|prod[33:31]) | (&prod[33:31])) ? prod[31:16] : {prod[33],{15{~prod[33]}}};
end
// send offset binary to DAC (someone else needs to instantiate the DDR output cells)
assign data_out0 = ({~sat[15], sat[14:0]});
assign data_out1 = ({~thru[16], thru[15:1]});
endmodule
| 6.526246 |
module afterburner2 (
input clk, // timespec 6.0 ns
input signed [16:0] data,
output [15:0] data_out0,
output [15:0] data_out1
);
parameter coeff = `AFTERBURNER_COEFF;
// concept: a1 k*(a1+a2) a2 k*(a2+a3) a3 ...
// where k = 0.5*sec(theta) = 0.5*sec(2*pi*11/28) = -0.63952
// to handle 55 MHz output at 70 MHz clk (140 MS/s data rate to DAC)
reg signed [17:0] avg = 0;
reg signed [16:0] data1 = 0, data2 = 0, data3 = 0;
`ifdef AFTERBURNER_TRIPLE
reg signed [16:0] data4 = 0;
wire signed [16:0] thru = data4;
`else
wire signed [16:0] thru = data3;
`endif
reg signed [33:0] prod = 0;
reg signed [15:0] sat = 0;
always @(posedge clk) begin
data1 <= data;
data2 <= data1;
data3 <= data2;
`ifdef AFTERBURNER_TRIPLE
data4 <= data3;
avg <= data + data3;
`else
avg <= data + data1;
`endif
prod <= avg * coeff; // scale by 32768
sat <= (~(|prod[33:31]) | (&prod[33:31])) ? prod[31:16] : {prod[33], {15{~prod[33]}}};
end
// send offset binary to DAC (someone else needs to instantiate the DDR output cells)
assign data_out1 = ({~thru[16], thru[15:1]});
assign data_out0 = ({~sat[15], sat[14:0]});
endmodule
| 7.199949 |
module afu_csr (
input wire clk,
input wire reset_n,
input wire spl_reset,
// RX, afu_io --> afu_csr
input wire io_rx_csr_valid,
input wire [13:0] io_rx_csr_addr,
input wire [31:0] io_rx_csr_data,
// afu_csr-->afu_core, afu_id
output reg csr_id_valid,
input wire csr_id_done,
output reg [31:0] csr_id_addr,
// afu_csr-->afu_core, afu_ctx_base
output reg csr_ctx_base_valid,
output reg [57:0] csr_ctx_base
);
localparam [5:0] AFU_CSR_DSR_BASEL = 6'b00_0000, //10'h280, // a00
AFU_CSR_DSR_BASEH = 6'b00_0001, //10'h281, // a04
AFU_CSR_CTX_BASEL = 6'b00_0010, //10'h282, // a08
AFU_CSR_CTX_BASEH = 6'b00_0011, //10'h283, // a0c
AFU_CSR_SCRATCH = 6'b11_1111; //10'h2bf; // afc
reg [31:0] afu_dsr_base;
//--------------------------------------------------------------------
// RX - afu_csr<--afu_io
//--------------------------------------------------------------------
always @(posedge clk) begin
if ((~reset_n) | spl_reset) begin
csr_id_valid <= 1'b0;
csr_ctx_base_valid <= 1'b0;
end else begin
if (csr_id_done) csr_id_valid <= 1'b0;
if (io_rx_csr_valid) begin
if (io_rx_csr_addr[13:6] == 8'h8a) begin
case (io_rx_csr_addr[5:0])
AFU_CSR_DSR_BASEH: begin
afu_dsr_base[31:26] <= io_rx_csr_data[5:0];
// synthesis translate_off
assert (io_rx_csr_data[31:6] == 26'b0)
else $fatal("afu_dsr_baseh = %x is out of 256GB range", io_rx_csr_data);
// synthesis translate_on
end
AFU_CSR_DSR_BASEL: begin
afu_dsr_base[25:0] <= io_rx_csr_data[31:6];
csr_id_valid <= 1'b1;
csr_id_addr <= {afu_dsr_base[31:26], io_rx_csr_data[31:6]};
// synthesis translate_off
assert (io_rx_csr_data[5:0] == 6'b0)
else $fatal("afu_dsr_basel = %x is not CL aligned", io_rx_csr_data);
// synthesis translate_on
end
AFU_CSR_CTX_BASEH: begin
csr_ctx_base[57:26] <= io_rx_csr_data;
end
AFU_CSR_CTX_BASEL: begin
csr_ctx_base[25:0] <= io_rx_csr_data[31:6];
csr_ctx_base_valid <= 1'b1;
// synthesis translate_off
assert (io_rx_csr_data[5:0] == 6'b0)
else
$fatal(
"csr_afu_ctx_base = %x is not CL aligned", {csr_ctx_base[57:26], io_rx_csr_data}
);
// synthesis translate_on
end
endcase
end
end
end
end // rx csr
endmodule
| 6.558658 |
module af_data_buffer (
input wire i_clk,
input wire i_valid,
input wire [39:0] i_inputData,
output reg [39:0] o_outputData
);
always @(posedge i_clk) begin
o_outputData <= (i_valid ? i_inputData[39:32] : o_outputData);
end
endmodule
| 6.655606 |
module and_gate (
input a,
input b,
output reg y
);
always @(*) begin
assign y = a & b;
end
endmodule
| 8.887051 |
module AGC (
input wire clk,
input wire rst,
input wire [ 7:0] a_coef,
input wire [15:0] reference,
input wire signed [15:0] x_in,
output wire signed [15:0] y_out
);
wire [31:0] x_mod;
wire [31:0] ref_rms;
wire signed [ 8:0] a_coef_s;
wire signed [32:0] tmp_level;
wire signed [32:0] feedback_level;
reg signed [32:0] zreg;
assign ref_rms = (reference[15:1] * reference[15:1]);
assign a_coef_s = {1'b0, a_coef};
assign x_mod = (y_out * y_out);
assign tmp_level = ($signed(ref_rms - x_mod)) >>> 18;
assign feedback_level = (tmp_level * a_coef_s) >>> 8;
always @(posedge clk or negedge rst) begin
if (!rst) zreg <= 'h0;
else zreg <= zreg + feedback_level;
end
assign y_out = (zreg * x_in) >>> 16;
endmodule
| 7.320386 |
module agc_sim ();
parameter CLK_PRD = 10;
parameter DATA_DEP = 16384 * 5;
reg clk;
reg reset_n;
reg [9:0] data_I_in;
reg [9:0] data_Q_in;
reg agc_en;
task clock_gen;
begin
clk = 1'b0;
forever #(CLK_PRD / 2) clk = ~clk;
end
endtask
task reset_gen;
begin
reset_n = 1'b0;
#(10 * CLK_PRD) reset_n = 1'b1;
$display("reset end");
end
endtask
task read_data_in;
integer i;
reg [31:0] mem_data_i[0:DATA_DEP-1];
reg [31:0] mem_data_q[0:DATA_DEP-1];
reg [31:0] temp;
//initial
begin
$readmemh("../../tb/pattern/data_in_i.dat", mem_data_i);
$readmemh("../../tb/pattern/data_in_q.dat", mem_data_q);
#(10 * CLK_PRD)
for (i = 0; i < DATA_DEP; i = i + 1) begin
temp = mem_data_i[i];
data_I_in = temp[9:0];
temp = mem_data_q[i];
data_Q_in = temp[9:0];
#(CLK_PRD) temp = 0;
end
#(100 * CLK_PRD) $finish;
end
endtask
task dump_fsdb;
begin
$fsdbDumpfile("agc.fsdb");
$fsdbDumpvars;
$fsdbDumpflush;
end
endtask
initial
fork
clock_gen;
reset_gen;
dump_fsdb;
read_data_in;
join
reg pwm_ena;
initial begin
pwm_ena = 0;
agc_en = 0;
#(40 * CLK_PRD) pwm_ena = 1'b1;
agc_en = 1'b1;
end
agc u_agc (
.clk (clk),
.reset_n (reset_n),
.data_I_in (data_I_in),
.data_Q_in (data_Q_in),
.agc_en (agc_en),
.pwr_req_val(9'b10_1101_001),
.pwr_est_prd(2'b00),
.pwr_range (8'b00000_101),
.pwr_est_val(),
.agc_fix (),
.pwm_step (2'b1),
.pwm_ena (pwm_ena),
.pwm_inv (1'b0),
.pwm_th_ena (1'b0),
.pwm_th_in (8'h3f),
.pwm_max_val(8'h7f),
.pwm_min_val(8'h00),
.pwm_th_out ()
);
endmodule
| 6.853351 |
module agearr #(
parameter HEIGHT = 16,
parameter WIDTH = 16
) (
input clk,
input rst,
input set_row_valid,
input [HEIGHT-1:0] set_row_sel,
input clear_col_valid,
input [WIDTH-1:0] clear_col_sel,
input [HEIGHT-1:0] row_sel,
output [HEIGHT-1:0] col_sel
);
wire [WIDTH-1:0] matrix[0:HEIGHT-1];
wire [HEIGHT-1:0] set_row_en = {HEIGHT{set_row_valid}} & set_row_sel;
wire [WIDTH-1:0] clear_col_en = {WIDTH{clear_col_valid}} & clear_col_sel;
genvar row, col;
generate
for (row = 0; row < HEIGHT; row = row + 1)
for (col = 0; col < WIDTH; col = col + 1)
flop matrix_r (
.clk(clk),
.rst(clear_col_en[col] | rst),
.set(set_row_en[row]),
.enable(1'b0),
.d(1'b0),
.q(matrix[row][col])
);
endgenerate
/*verilator lint_off UNOPTFLAT*/
wire [WIDTH-1:0] steps[0:HEIGHT];
assign steps[0] = 0;
genvar i;
generate
for (i = 0; i < HEIGHT; i = i + 1)
assign steps[i+1] = steps[i] | ({WIDTH{row_sel[i]}} & matrix[i]);
endgenerate
/*verilator lint_on UNOPTFLAT*/
assign col_sel = steps[HEIGHT];
endmodule
| 7.71801 |
module AgenLsu (
input clk,
input reset,
input ctrlMispredict_i,
input [`CHECKPOINTS_LOG-1:0] ctrlSMTid_i,
input [`CHECKPOINTS+`LDST_TYPES_LOG+`EXECUTION_FLAGS+`SIZE_PHYSICAL_LOG+`SIZE_ACTIVELIST_LOG+`SIZE_DATA+`SIZE_ISSUEQ_LOG+
`SIZE_LSQ_LOG+`CHECKPOINTS_LOG+`SIZE_CTI_LOG+`SIZE_PC:0] exePacket_i,
input exePacketValid_i,
output agenPacketValid0_o,
output [`LDST_TYPES_LOG+`EXECUTION_FLAGS+`SIZE_PHYSICAL_LOG+`SIZE_ACTIVELIST_LOG+`SIZE_DATA+`SIZE_ISSUEQ_LOG+
`SIZE_LSQ_LOG+`CHECKPOINTS_LOG+`SIZE_CTI_LOG+`SIZE_PC:0] agenPacket0_o
);
/* Follwoing defines the pipeline registers between AGEN and LSU.
*/
reg [`CHECKPOINTS+`LDST_TYPES_LOG+`EXECUTION_FLAGS+`SIZE_PHYSICAL_LOG+`SIZE_ACTIVELIST_LOG+
`SIZE_DATA+`SIZE_ISSUEQ_LOG+`SIZE_LSQ_LOG+`CHECKPOINTS_LOG+`SIZE_CTI_LOG+`SIZE_PC:0] exePacket3;
reg exePacketValid3;
/* wires and regs definition for combinational logic. */
reg invalidateLsuPacket;
/* Following packet goes to Load-Store unit.
*/
assign agenPacketValid0_o = exePacketValid3 & ~invalidateLsuPacket;
assign agenPacket0_o = exePacket3;
always @(*)
begin:INVALIDATE_ON_MISPREDICT
reg [`CHECKPOINTS-1:0] lsuBranchMask;
lsuBranchMask = exePacket3[`CHECKPOINTS+`LDST_TYPES_LOG+`EXECUTION_FLAGS+`SIZE_PHYSICAL_LOG+`SIZE_ACTIVELIST_LOG+
`SIZE_DATA+`SIZE_ISSUEQ_LOG+`SIZE_LSQ_LOG+`CHECKPOINTS_LOG+`SIZE_CTI_LOG+`SIZE_PC:
`LDST_TYPES_LOG+`EXECUTION_FLAGS+`SIZE_PHYSICAL_LOG+`SIZE_ACTIVELIST_LOG+`SIZE_DATA+`SIZE_ISSUEQ_LOG+
`SIZE_LSQ_LOG+`CHECKPOINTS_LOG+`SIZE_CTI_LOG+`SIZE_PC+1];
if(ctrlMispredict_i && lsuBranchMask[ctrlSMTid_i])
invalidateLsuPacket = 1'b1;
else
invalidateLsuPacket = 1'b0;
end
always @(posedge clk)
begin
if(reset)
begin
exePacketValid3 <= 0;
exePacket3 <= 0;
end
else
begin
exePacketValid3 <= exePacketValid_i;
if(exePacketValid_i)
exePacket3 <= exePacket_i;
`ifdef VERIFY
else
exePacket3 <= 0;
`endif
end
end
endmodule
| 7.113476 |
module age_set_ctr (
clk,
rst,
re,
we,
hit,
miss,
access_addr,
write_addr,
age_1D
);
parameter k = 3; /////////////age counter width//////////
parameter j = 2; /////////////set counter width- will be used for Age Granularity//////////
parameter A = 2; //////////////Age Granularity/////////////
parameter accessCtrWidth = 13;
parameter N = 2 ** k; /////number of rows
input clk;
input rst;
input re;
input we;
input hit;
input miss;
input [4:0] write_addr;
input [4:0] access_addr;
output reg [32*k - 1 : 0] age_1D;
reg [(k - 1):0] age[0:31]; ////k-bit age for each line/////
reg [(j - 1):0] setCtr[0:31]; /////j-bit set counter/////////////
/////////////////********** 2D_array to 1D_array conversion **********/////////////////
integer w;
always @(*) begin
if (rst) begin
age_1D = 0;
end else begin
for (w = 0; w < 32; w = w + 1) begin
age_1D[w*k+:k] = age[w];
end
end
end
//////////////// ****************** /////////////////////////
/////////////////********** age and setCtr logic **********/////////////////
integer x;
integer y;
integer z;
always @(posedge clk) begin
#0.1
if (rst) begin
for (x = 0; x < 32; x = x + 1) begin
age[x] <= {(k) {1'b0}};
setCtr[x] <= {(j) {1'b0}};
end
end else if (we) begin
age[write_addr] = {(k) {1'b0}};
setCtr[write_addr] <= {(j) {1'b0}};
end else if (re) begin
if (hit) begin
for (y = 0; y < 32; y = y + 1) begin
if (access_addr == y) begin
setCtr[y] = {(j) {1'b0}};
age[y] = {(k) {1'b0}};
for (z = 0; z < 32; z = z + 1) begin
if (z != y) begin
if (setCtr[z] == A) begin
setCtr[z] = {(j) {1'b0}};
if (age[z] == N - 1) begin
age[z] <= age[z];
end else begin
age[z] = age[z] + 1;
end
end else begin
setCtr[z] = setCtr[z] + 1;
end
end
end
end
end
end else begin
for (y = 0; y < 32; y = y + 1) begin
if (setCtr[y] == A) begin
setCtr[y] = {(j) {1'b0}};
if (age[y] == N - 1) begin
age[y] <= age[y];
end else begin
age[y] = age[y] + 1;
end
end else begin
setCtr[y] = setCtr[y] + 1;
end
end
end
end
end
////////////////// ****************** /////////////////////////////
endmodule
| 7.17768 |
module aggregator (
input [9:0] in_use,
input [159:0] samples,
input clk,
reset,
//compiles the average of all samples
output [15:0] sample_out,
output [15:0] sample_out_left,
output [15:0] sample_out_right
);
wire [ 3:0] numSamples;
wire [25:0] interMed;
wire [25:0] pre_interMed1;
wire [25:0] pre_interMed2;
wire [25:0] post_interMed1;
wire [25:0] post_interMed2;
reg [25:0] interMed2;
//add up all the samples should be zero if not in use
assign pre_interMed1 = $signed(
samples[15:0]
) + $signed(
samples[31:16]
) + $signed(
samples[47:32]
) + $signed(
samples[63:48]
) + $signed(
samples[79:64]
);
assign pre_interMed2 = $signed(
samples[95:80]
) + $signed(
samples[111:96]
) + $signed(
samples[127:112]
) + $signed(
samples[143:128]
) + $signed(
samples[159:144]
);
dffr #(52) addition_wait (
.clk(clk),
.r (reset),
.d ({pre_interMed1, pre_interMed2}),
.q ({post_interMed1, post_interMed2})
);
assign interMed = post_interMed1 + post_interMed2;
//counts the number of samples
assign numSamples = in_use[0] + in_use[1] + in_use[2] + in_use[3] + in_use[4] + in_use[5] +
in_use[6] + in_use[7] + in_use[8] + in_use[9];
always @(*) begin
case (numSamples)
4'd1: interMed2 = $signed(interMed);
4'd2: interMed2 = ($signed(interMed) * $signed(40'd512)) / $signed(40'd1024);
4'd3: interMed2 = ($signed(interMed) * $signed(40'd256)) / $signed(40'd1024);
//interMed2 = ($signed(interMed) * $signed(40'd342)) / $signed(40'd1024);
4'd4: interMed2 = ($signed(interMed) * $signed(40'd256)) / $signed(40'd1024);
4'd5: interMed2 = ($signed(interMed) * $signed(40'd256)) / $signed(40'd1024);
//interMed2 = ($signed(interMed) * $signed(40'd205)) / $signed(40'd1024);
4'd6: interMed2 = ($signed(interMed) * $signed(40'd256)) / $signed(40'd1024);
//interMed2 = ($signed(interMed) * $signed(40'd171)) / $signed(40'd1024);
4'd7: interMed2 = ($signed(interMed) * $signed(40'd256)) / $signed(40'd1024);
//interMed2 = ($signed(interMed) * $signed(40'd147)) / $signed(40'd1024);
4'd8: interMed2 = ($signed(interMed) * $signed(40'd128)) / $signed(40'd1024);
4'd9: interMed2 = ($signed(interMed) * $signed(40'd128)) / $signed(40'd1024);
//interMed2 = ($signed(interMed) * $signed(40'd114)) / $signed(40'd1024);
4'd10: interMed2 = ($signed(interMed) * $signed(40'd128)) / $signed(40'd1024);
//interMed2 = ($signed(interMed) * $signed(40'd103)) / $signed(40'd1024);
default: interMed2 = $signed(interMed);
endcase
end
assign sample_out = {interMed2[25], interMed2[14:0]};
stereo our_stereo (
.clk(clk),
.reset(reset),
.codec_sample(sample_out),
.codec_sample_right(sample_out_right),
.codec_sample_left(sample_out_left)
);
endmodule
| 7.870736 |
module aggregator_tb;
reg clk;
reg rst_n;
wire [`DATA_WIDTH - 1 : 0] fifo_dout;
wire fifo_empty_n;
wire fifo_deq;
wire [`FETCH_WIDTH * `DATA_WIDTH - 1 : 0] receiver_din;
reg [`FETCH_WIDTH * `DATA_WIDTH - 1 : 0] expected_dout;
reg receiver_full_n;
wire receiver_enq;
reg [`DATA_WIDTH - 1 : 0] fifo_din;
wire fifo_enq;
wire fifo_full_n;
reg stall;
reg fifo_valid;
reg [1:0] iseven;
wire even;
reg [2:0] local_fetch_width;
reg change_fetch_width;
logic [`DSIZE-1:0] rdata;
logic wfull_n;
logic rempty_n;
logic [`DSIZE-1:0] wdata;
logic winc, wclk, wrst_n;
logic rinc, rrst_n;
always #6.666666667 clk = ~clk; //Conceptually, rlck = clk (read clock is normal clock)
always #20 wclk = ~wclk;
aggregator #(
.DATA_WIDTH (`DATA_WIDTH),
.FETCH_WIDTH(`FETCH_WIDTH)
) aggregator_inst (
.clk(clk),
.rst_n(rst_n),
.sender_data(rdata),
.sender_empty_n(rempty_n),
.sender_deq(fifo_deq),
.receiver_data(receiver_din),
.receiver_full_n(receiver_full_n),
.receiver_enq(receiver_enq),
.change_fetch_width(change_fetch_width),
.input_fetch_width(local_fetch_width)
);
SyncFIFO #(`DATA_WIDTH, 4, 2) dut (
.sCLK(wclk),
.sRST(wrst_n),
.dCLK(clk),
.sENQ(fifo_enq),
.sD_IN(wdata),
.sFULL_N(wfull_n),
.dDEQ(fifo_deq),
.dD_OUT(rdata),
.dEMPTY_N(rempty_n)
);
initial begin
winc = 1'b0;
iseven = 2'b10;
wdata = '0;
wrst_n = 1'b0;
rst_n = 1'b0;
local_fetch_width = 2;
change_fetch_width = 0;
repeat (5) @(posedge wclk);
//#5
wrst_n = 1'b1;
rst_n = 1'b1;
#40
//iseven = 1'b0;
change_fetch_width = 1'b1;
local_fetch_width = 3'd4;
#40 change_fetch_width = 1'b0;
#820 local_fetch_width = 3'd1;
change_fetch_width = 1'b1;
#40 change_fetch_width = 1'b0;
end
reg [1:0] state;
initial begin
rinc = 1'b0;
rrst_n = 1'b0;
repeat (8) @(posedge clk);
rrst_n = 1'b1;
end
initial begin
clk <= 0;
wclk <= 0;
wdata <= 11'b0;
fifo_valid <= 0;
//rst_n <= 0;
stall <= 0;
expected_dout <= 11'b0;
receiver_full_n <= 0;
#20 //rst_n <= 0;
receiver_full_n <= 1;
#20 //rst_n <= 1;
fifo_valid <= 1;
end
//comment
assign fifo_enq = wrst_n && (wfull_n);
always @(posedge wclk) begin
if (wrst_n) begin
stall <= $urandom % 2;
receiver_full_n <= 1;
if (fifo_enq) begin
wdata <= wdata + 11'b1;
end
end else begin
wdata <= 0;
end
end
genvar i;
generate
for (i = 0; i < 4; i++) begin
always @(posedge clk) begin
if (receiver_enq && (state == 2'b01)) begin
assert (receiver_din[(i+1)*`DATA_WIDTH-1 : i*`DATA_WIDTH] == expected_dout + i);
$display("%t: (1) received = %d, expected = %d", $time,
receiver_din[(i+1)*`DATA_WIDTH-1 : i*`DATA_WIDTH], expected_dout + i);
end
end
end
endgenerate
genvar i;
generate
for (i = 0; i < 1; i++) begin
always @(posedge clk) begin
if (receiver_enq && (state == 2'b10)) begin
assert (receiver_din[(i+1)*`DATA_WIDTH-1 : i*`DATA_WIDTH] == expected_dout + i);
$display("%t: (2) received = %d, expected = %d", $time,
receiver_din[(i+1)*`DATA_WIDTH-1 : i*`DATA_WIDTH], expected_dout + i);
end
end
end
endgenerate
always @(posedge clk) begin
if (receiver_enq) begin
expected_dout <= expected_dout + local_fetch_width + 1;
end
end
always @(posedge wclk) begin
if (!rst_n) begin
state <= 0;
end else if (change_fetch_width) begin
state <= state + 1;
end
end
initial begin
$dumpfile("dump.vcd");
$dumpvars;
// $vcdplusmemon();
// $vcdpluson(0, aggregator_tb);
#2000;
$finish(2);
end
endmodule
| 6.525058 |
module agitador (
input clk_i, //@100MHz
input onOff_i,
input selbtn_i,
input upbtn_i,
input downbtn_i,
input rx_i,
inout zero_i,
output motor_o,
output heater_o,
output motor_d,
output heater_d,
output tx_o,
output [7:0] SEG_o,
output [3:0] AN_o
);
wire update;
wire [9:0] signal; //Actually 12 bits from 0 to 1.25 V.
PT100_ADC ADC_U0 (
.clk_i(clk_i),
.rx_i(rx_i),
.updated(update),
.ADC_o(signal)
);
wire [9:0] signal_f;
filter_4 FILTER_U0 (
.clk_i(update),
.signal_i(signal),
.signal_o(signal_f)
);
wire [7:0] temp;
pt100 PT100_U0 (
.ADC_i (signal_f),
.temp_o(temp)
);
wire selbtn_deb;
debouncer DEB_U0 (
.clk_i (clk_i),
.signal_i (selbtn_i),
.signal_o (selbtn_deb)
);
wire upbtn_deb;
debouncer DEB_U1 (
.clk_i (clk_i),
.signal_i (upbtn_i),
.signal_o (upbtn_deb)
);
wire downbtn_deb;
debouncer DEB_U2 (
.clk_i (clk_i),
.signal_i (downbtn_i),
.signal_o (downbtn_deb)
);
wire [2:0] tempMode;
wire [2:0] velMode;
wire dot;
modeCont MCONT_U0 (
.clk_i (clk_i),
.sel_i (~selbtn_deb),
.rst_i (onOff_i),
.up_i (~upbtn_deb),
.down_i (~downbtn_deb),
.tempMode_o (tempMode),
.velMode_o (velMode),
.btnState_d (dot)
);
tempCont CONT_U0 (
.clk_i (clk_i), //@100 MHz
.rst_i (zero_i),
.temp_i (temp),
.tempCase_i(tempMode), //40, 70, 100, 127, 150
.PWM_o (heater_o)
);
velCont CONT_U1 (
.clk_i(clk_i),
.velCase_i(velMode),
.PWM_o(motor_o)
);
wire [31:0] display;
messages MESS_U0 (
.clk_i(clk_i),
.state0_i(dot),
.state1_i(tempMode),
.state2_i(velMode),
.temp_i(temp),
.SEg_o(display)
);
disp7 DISP_U0 (
.clk_i(clk_i),
.number_i(display), //4x 7-seg data cluster
.seg_o(SEG_o),
.an_o(AN_o)
);
BTGUI BT_U0 (
.clk_i(clk_i),
.velMode_i(velMode),
.tempMode_i(tempMode),
.temp_i(temp),
.tx_o(tx_o)
);
assign motor_d = motor_o;
assign heater_d = heater_o;
endmodule
| 6.527058 |
module agnus_audiodma (
input wire clk, // bus clock
input wire clk7_en, // 7MHz clock enable
output wire dma, // true if audio dma engine uses it's cycle
input wire [ 4-1:0] audio_dmal, // audio dma data transfer request (from Paula)
input wire [ 4-1:0] audio_dmas, // audio dma location pointer restart (from Paula)
input wire [ 9-1:0] hpos, // horizontal beam counter
input wire [ 9-1:1] reg_address_in, // register address inputs
output reg [ 9-1:1] reg_address_out, // register address outputs
input wire [16-1:0] data_in, // bus data in
output wire [21-1:1] address_out // chip address out
);
// register names and adresses
parameter AUD0DAT_REG = 9'h0AA;
parameter AUD1DAT_REG = 9'h0BA;
parameter AUD2DAT_REG = 9'h0CA;
parameter AUD3DAT_REG = 9'h0DA;
// local signals
wire audlcena; // audio dma location pointer register address enable
wire [1:0] audlcsel; // audio dma location pointer select
reg [20:16] audlch[3:0]; // audio dma location pointer bank (high word)
reg [15:1] audlcl[3:0]; // audio dma location pointer bank (low word)
wire [20:1] audlcout; // audio dma location pointer bank output
reg [20:1] audpt[3:0]; // audio dma pointer bank
wire [20:1] audptout; // audio dma pointer bank output
reg [1:0] channel; // audio dma channel select
reg dmal;
reg dmas;
// location registers address enable
// active when any of the location registers is addressed
// $A0-$A3, $B0-$B3, $C0-$C3, $D0-$D3,
assign audlcena = ~reg_address_in[8] & reg_address_in[7] & (reg_address_in[6]^reg_address_in[5]) & ~reg_address_in[3] & ~reg_address_in[2];
// location register channel select
assign audlcsel = {~reg_address_in[5], reg_address_in[4]};
// audio location register bank
always @(posedge clk) begin
if (clk7_en) begin
if (audlcena & ~reg_address_in[1]) // AUDxLCH
audlch[audlcsel] <= #1 data_in[4:0];
end
end
always @(posedge clk) begin
if (clk7_en) begin
if (audlcena & reg_address_in[1]) // AUDxLCL
audlcl[audlcsel] <= #1 data_in[15:1];
end
end
// get audio location pointer
assign audlcout = {audlch[channel], audlcl[channel]};
// dma cycle allocation
always @(*) begin
case (hpos)
9'b0001_0010_1: dmal = audio_dmal[0]; //$0E
9'b0001_0100_1: dmal = audio_dmal[1]; //$10
9'b0001_0110_1: dmal = audio_dmal[2]; //$12
9'b0001_1000_1: dmal = audio_dmal[3]; //$14
default: dmal = 0;
endcase
end
// dma cycle request
assign dma = dmal;
// channel dmas encoding
always @(*) begin
case (hpos)
9'b0001_0010_1: dmas = audio_dmas[0]; //$0E
9'b0001_0100_1: dmas = audio_dmas[1]; //$10
9'b0001_0110_1: dmas = audio_dmas[2]; //$12
9'b0001_1000_1: dmas = audio_dmas[3]; //$14
default: dmas = 0;
endcase
end
// dma channel select
always @(*) begin
case (hpos[3:2])
2'b01: channel = 0; //$0E
2'b10: channel = 1; //$10
2'b11: channel = 2; //$12
2'b00: channel = 3; //$14
endcase
end
// memory address output
assign address_out[20:1] = audptout[20:1];
// audio pointers register bank (implemented using distributed ram) and ALU
always @(posedge clk) begin
if (clk7_en) begin
if (dmal) audpt[channel] <= #1 dmas ? audlcout[20:1] : audptout[20:1] + 1'b1;
end
end
// audio pointer output
assign audptout[20:1] = audpt[channel];
// register address output multiplexer
always @(*) begin
case (channel)
0: reg_address_out[8:1] = AUD0DAT_REG[8:1];
1: reg_address_out[8:1] = AUD1DAT_REG[8:1];
2: reg_address_out[8:1] = AUD2DAT_REG[8:1];
3: reg_address_out[8:1] = AUD3DAT_REG[8:1];
endcase
end
endmodule
| 6.567104 |
module can shift 0-15 positions to the right (normal mode) or to the left (descending mode).
//Multipliers are used to save logic.
module agnus_blitter_barrelshifter
(
input desc, // select descending mode (shift to the left)
input [3:0] shift, // shift value (0 to 15)
input [15:0] new_val, // barrel shifter data in
input [15:0] old_val, // barrel shifter data in
output [15:0] out // barrel shifter data out
);
wire [35:0] shifted_new; // shifted new data
wire [35:0] shifted_old; // shifted old data
reg [17:0] shift_onehot; // one-hot shift value for multipliers
//one-hot shift value encoding
always @(desc or shift)
case ({desc,shift[3:0]})
5'h00 : shift_onehot = 18'h10000;
5'h01 : shift_onehot = 18'h08000;
5'h02 : shift_onehot = 18'h04000;
5'h03 : shift_onehot = 18'h02000;
5'h04 : shift_onehot = 18'h01000;
5'h05 : shift_onehot = 18'h00800;
5'h06 : shift_onehot = 18'h00400;
5'h07 : shift_onehot = 18'h00200;
5'h08 : shift_onehot = 18'h00100;
5'h09 : shift_onehot = 18'h00080;
5'h0A : shift_onehot = 18'h00040;
5'h0B : shift_onehot = 18'h00020;
5'h0C : shift_onehot = 18'h00010;
5'h0D : shift_onehot = 18'h00008;
5'h0E : shift_onehot = 18'h00004;
5'h0F : shift_onehot = 18'h00002;
5'h10 : shift_onehot = 18'h00001;
5'h11 : shift_onehot = 18'h00002;
5'h12 : shift_onehot = 18'h00004;
5'h13 : shift_onehot = 18'h00008;
5'h14 : shift_onehot = 18'h00010;
5'h15 : shift_onehot = 18'h00020;
5'h16 : shift_onehot = 18'h00040;
5'h17 : shift_onehot = 18'h00080;
5'h18 : shift_onehot = 18'h00100;
5'h19 : shift_onehot = 18'h00200;
5'h1A : shift_onehot = 18'h00400;
5'h1B : shift_onehot = 18'h00800;
5'h1C : shift_onehot = 18'h01000;
5'h1D : shift_onehot = 18'h02000;
5'h1E : shift_onehot = 18'h04000;
5'h1F : shift_onehot = 18'h08000;
endcase
/*
MULT18X18 multiplier_1
(
.dataa({2'b00,new_val[15:0]}), // 18-bit multiplier input
.datab(shift_onehot), // 18-bit multiplier input
.result(shifted_new) // 36-bit multiplier output
);
*/
assign shifted_new = ({2'b00,new_val[15:0]})*shift_onehot;
/*
MULT18X18 multiplier_2
(
.dataa({2'b00,old_val[15:0]}), // 18-bit multiplier input
.datab(shift_onehot), // 18-bit multiplier input
.result(shifted_old) // 36-bit multiplier output
);
*/
assign shifted_old = ({2'b00,old_val[15:0]})*shift_onehot;
assign out = desc ? shifted_new[15:0] | shifted_old[31:16] : shifted_new[31:16] | shifted_old[15:0];
endmodule
| 7.166817 |
module has 2 modes,inclusive fill and exclusive fill.
//Both share the same xor operation but in inclusive fill mode,
//the output of the xor-filler is or-ed with the input data.
module agnus_blitter_fill
(
input ife, //inclusive fill enable
input efe, //exclusive fill enable
input fci, //fill carry input
output fco, //fill carry output
input [15:0]in, //data in
output reg [15:0]out //data out
);
//local signals
reg [15:0]carry;
//generate all fill carry's
integer j;
always @(fci or in[0])//least significant bit
carry[0] = fci ^ in[0];
always @(in or carry)//rest of bits
for (j=1;j<=15;j=j+1)
carry[j] = carry[j-1] ^ in[j];
//fill carry output
assign fco = carry[15];
//fill data output
always @(ife or efe or carry or in)
if (efe)//exclusive fill
out[15:0] = carry[15:0];
else if (ife)//inclusive fill
out[15:0] = carry[15:0] | in[15:0];
else//bypass,no filling
out[15:0] = in[15:0];
endmodule
| 7.451104 |
module agnus_diskdma (
input clk, //bus clock
input clk7_en,
output dma, //true if disk dma engine uses it's cycle
input dmal, //Paula requests dma
input dmas, //Paula special dma
input speed,
input [ 8:0] hpos, //horizontal beam counter (advanced by 4 CCKs)
output wr, //write (disk dma writes to memory)
input [ 8:1] reg_address_in, //register address inputs
output [ 8:1] reg_address_out, //register address outputs
input [15:0] data_in, //bus data in
output reg [20:1] address_out //chip address out current disk dma pointer
);
//register names and adresses
parameter DSKPTH = 9'h020;
parameter DSKPTL = 9'h022;
parameter DSKDAT = 9'h026;
parameter DSKDATR = 9'h008;
//local signals
wire [20:1] address_outnew; //new disk dma pointer
reg dmaslot; //indicates if the current slot can be used to transfer data
//--------------------------------------------------------------------------------------
//dma cycle allocation
//nominally disk DMA uses 3 slots: 08, 0A and 0C
//refresh slots: 00, 02, 04 and 06 are used for higher transfer speed
//hint: Agnus hpos counter is advanced by 4 CCK cycles
always @(*)
case (hpos[8:1])
8'h04: dmaslot = speed;
8'h06: dmaslot = speed;
8'h08: dmaslot = speed;
8'h0A: dmaslot = speed;
8'h0C: dmaslot = 1;
8'h0E: dmaslot = 1;
8'h10: dmaslot = 1;
default: dmaslot = 0;
endcase
//dma request
assign dma = dmal & dmaslot & hpos[0];
//write signal
assign wr = ~dmas;
//--------------------------------------------------------------------------------------
//address_out input multiplexer and ALU
assign address_outnew[20:1] = dma ? address_out[20:1] + 1'b1 : {data_in[4:0], data_in[15:1]};
//disk pointer control
always @(posedge clk)
if (clk7_en) begin
if (dma || (reg_address_in[8:1] == DSKPTH[8:1]))
address_out[20:16] <= address_outnew[20:16]; //high 5 bits
end
always @(posedge clk)
if (clk7_en) begin
if (dma || (reg_address_in[8:1] == DSKPTL[8:1]))
address_out[15:1] <= address_outnew[15:1]; //low 15 bits
end
//--------------------------------------------------------------------------------------
//register address output
assign reg_address_out[8:1] = wr ? DSKDATR[8:1] : DSKDAT[8:1];
//--------------------------------------------------------------------------------------
endmodule
| 6.84107 |
module agtb_16 (
input wire clk
, input wire [15:0] inpa
, input wire [15:0] inpb
, output reg out_agtb
);
// break this troublesome compare in half
wire [7:0] inpa_hi, inpa_lo;
wire [7:0] inpb_hi, inpb_lo;
assign {inpb_hi, inpb_lo} = inpb;
assign {inpa_hi, inpa_lo} = inpa;
reg inpa_gt_inpb_1 = 1'b0;
reg inpa_gt_inpb_2 = 1'b0;
reg inpa_gt_inpb_3 = 1'b0;
always @(posedge clk) begin
inpa_gt_inpb_1 <= inpa_hi > inpb_hi;
inpa_gt_inpb_2 <= inpa_hi == inpb_hi;
inpa_gt_inpb_3 <= inpa_lo > inpb_lo;
end
always @(posedge clk) begin
out_agtb <= inpa_gt_inpb_1 || (inpa_gt_inpb_2 && inpa_gt_inpb_3);
end
// ____________________________________________________________________________________________________________
//
endmodule
| 6.801099 |
module agtb_8 (
input wire clk
, input wire [07:0] inpa
, input wire [07:0] inpb
, output reg out_agtb
);
// break this troublesome compare in half
wire [3:0] inpa_hi, inpa_lo;
wire [3:0] inpb_hi, inpb_lo;
assign {inpb_hi, inpb_lo} = inpb;
assign {inpa_hi, inpa_lo} = inpa;
reg inpa_gt_inpb_1 = 1'b0;
reg inpa_gt_inpb_2 = 1'b0;
reg inpa_gt_inpb_3 = 1'b0;
always @(posedge clk) begin
inpa_gt_inpb_1 <= inpa_hi > inpb_hi;
inpa_gt_inpb_2 <= inpa_hi == inpb_hi;
inpa_gt_inpb_3 <= inpa_lo > inpb_lo;
end
always @(posedge clk) begin
out_agtb <= inpa_gt_inpb_1 || (inpa_gt_inpb_2 && inpa_gt_inpb_3);
end
// ____________________________________________________________________________________________________________
//
endmodule
| 6.713251 |
module agu (
input [XLEN - 1 : 0] base_i,
input [XLEN - 1 : 0] offset_i,
output [VIRTUAL_ADDR_LEN - 1 : 0] addr_o
);
assign addr_o = base_i[VIRTUAL_ADDR_LEN-1 : 0] + offset_i[VIRTUAL_ADDR_LEN-1 : 0];
endmodule
| 6.726108 |
module agucam_ram0 (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
localparam DATA_WIDTH = (3 + 3 * `mOp_width) / 2 + 1;
localparam ADDR_WIDTH = 3;
localparam ADDR_COUNT = 8;
input clk;
input rst;
input read_clkEn;
input [ADDR_WIDTH-1:0] read_addr;
output [DATA_WIDTH-1:0] read_data;
input [ADDR_WIDTH-1:0] write_addr;
input [DATA_WIDTH-1:0] write_data;
input write_wen;
reg [DATA_WIDTH-1:0] ram[7:0];
reg [ADDR_WIDTH-1:0] read_addr_reg;
assign read_data = ram[read_addr_reg];
always @(posedge clk) begin
if (rst) read_addr_reg <= {ADDR_WIDTH{1'b0}};
else if (read_clkEn) read_addr_reg <= read_addr;
if (write_wen) ram[write_addr] <= write_data;
end
endmodule
| 7.941291 |
module agucam_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
localparam DATA_WIDTH = 3 + 3 * `mOp_width;
localparam ADDR_WIDTH = 3;
localparam ADDR_COUNT = 8;
input clk;
input rst;
input read_clkEn;
input [ADDR_WIDTH-1:0] read_addr;
output [DATA_WIDTH-1:0] read_data;
input [ADDR_WIDTH-1:0] write_addr;
input [DATA_WIDTH-1:0] write_data;
input write_wen;
//verilator lint_off WIDTH
agucam_ram0 ramA (
clk,
rst,
read_clkEn,
read_addr,
read_data[DATA_WIDTH/2-1:0],
write_addr,
write_data[DATA_WIDTH/2-1:0],
write_wen
);
agucam_ram0 ramB (
clk,
rst,
read_clkEn,
read_addr,
read_data[DATA_WIDTH-1:DATA_WIDTH/2],
write_addr,
write_data[DATA_WIDTH-1:DATA_WIDTH/2],
write_wen
);
//verilator lint_on WIDTH
endmodule
| 7.378573 |
module agusec_range (
input [63:0] ptr,
input cin_secq,
input diff,
output cout_secq
);
wire [7:0] low = {ptr[`ptr_low], 1'b0};
wire [7:0] high = {ptr[`ptr_hi], 1'b1};
//wire diff=ptr[`ptr_hi_less];
wire hi_pass = diff && ptr[`ptr_on_low];
wire lo_lass = diff && ~ptr[`ptr_on_low];
wire [7:0] bits;
wire cout_low, cout_hio;
get_carry #(8) cmpLow_mod (
~low,
bits,
1'b1,
cout_low
);
get_carry #(8) cmpHio_mod (
high,
~bits,
1'b1,
cout_hio
);
agusec_shift8 sh_mod (
ptr[`ptr_exp],
ptr[43:4],
bits
);
assign cout_secq = cin_secq && cout_low | lo_lass && cout_hio | hi_pass;
endmodule
| 7.056686 |
module
// with baseclk frequency ~ 10 x phi_0
`define AG6502_EXTERNAL_CLOCK
`ifndef AG6502_EXTERNAL_CLOCK
module ag6502_clock(input phi_0, output phi_1, output phi_2);
wire phi_01;
not#3(phi_1,phi_0);
or(phi_01,~phi_0, phi_1);
not#1(phi_2, phi_01);
endmodule
| 6.600709 |
module ag6502_phase_shift (
input baseclk,
input phi_0,
output reg phi_1
);
parameter DELAY = 1; // delay in waves of baseclk
initial phi_1 = 0;
integer cnt = 0;
always @(posedge baseclk) begin
if (phi_0 != phi_1) begin
if (!cnt) begin
phi_1 <= phi_0;
cnt <= DELAY;
end else cnt <= cnt - 1;
end
end
endmodule
| 6.54584 |
module ag6502_ext_clock(input baseclk, input phi_0, output phi_1, output phi_2);
parameter DELAY1 = 3, DELAY2 = 1; // delays in waves of baseclk
wire phi_1_neg, phi_01;
ag6502_phase_shift#DELAY1 d1(baseclk, phi_0, phi_1_neg);
assign phi_1 = ~phi_1_neg;
and(phi_01, phi_0, phi_1_neg);
ag6502_phase_shift#DELAY2 d2(baseclk, phi_01, phi_2);
endmodule
| 6.804942 |
module ag6502_decimal (
ADD,
D_IN,
NEG,
CORR
);
input wire [4:0] ADD;
input wire D_IN, NEG;
output wire [4:0] CORR;
wire C9 = {ADD[4] ^ NEG, ADD[3:0]} > 5'd9;
assign CORR = D_IN ? {C9 ^ NEG, C9 ? ADD[3:0] + (NEG ? 4'd10 : 4'd6) : ADD[3:0]} : ADD;
endmodule
| 6.971945 |
module signal_filter (
input clk,
input in,
output reg out
);
always @(posedge clk) begin
out <= in;
end
endmodule
| 6.764118 |
module ps2_keyb_driver (
ps2_clk,
ps2_data,
ps2_code,
ps2_up,
ps2_ext,
ps2_event
);
input wire ps2_clk, ps2_data;
output reg [7:0] ps2_code = 0;
output reg ps2_up = 0, ps2_ext = 0, ps2_event = 0;
reg [10:0] shreg = 11'b11111111111;
wire [10:0] shnew = {ps2_data, shreg[10:1]};
wire start = shnew[0], stop = shnew[10], parity = shnew[9];
wire [7:0] data = shnew[8:1];
always @(negedge ps2_clk) begin
if (!start && stop && (parity == ~^data)) begin
if (data == 8'hE0) begin
ps2_ext <= 1;
end else if (data == 8'hF0) begin
ps2_up <= 1;
end else begin
ps2_code <= data;
ps2_event <= 1;
end
shreg <= 11'b11111111111;
end else begin
if (ps2_event) begin
ps2_up <= 0;
ps2_ext <= 0;
ps2_event <= 0;
end
shreg <= shnew;
end
end
endmodule
| 7.489071 |
module ag_reg_decoder (
keyb_in,
shift,
ctrl,
keyb_out
);
input wire [6:0] keyb_in;
input wire shift, ctrl;
output wire [6:0] keyb_out;
wire is_alpha = keyb_in[6] && !keyb_in[5];
wire is_digit = !keyb_in[6] && keyb_in[5] && keyb_in[3:0];
assign keyb_out =
is_alpha?
(shift?{1'b1,1'b1,keyb_in[4:0]}:
ctrl?{1'b0,1'b0,keyb_in[4:0]}:
keyb_in):
is_digit?
(shift?{1'b0,1'b1,~keyb_in[4],keyb_in[3:0]}:
keyb_in):
keyb_in;
endmodule
| 7.044385 |
module ag_keyb (
clk,
ps2_bus,
keyb_reg,
keyb_clear,
keyb_rus,
keyb_rst,
keyb_pause
);
input clk;
input wire [1:0] ps2_bus;
output wire [7:0] keyb_reg;
input wire keyb_clear;
output wire keyb_rus;
output wire keyb_rst;
output wire keyb_pause;
wire ps2_clk, ps2_data;
assign {ps2_clk, ps2_data} = ps2_bus;
reg [7:0] keyb_code;
reg clr = 0, got = 0;
reg lshift = 0, rshift = 0, ctrl = 0, alt = 0, rus = 0, rst = 0, pause = 0;
wire [7:0] ps2_code;
wire ps2_up, ps2_ext, ps2_event;
assign keyb_reg = clr ? 0 : keyb_code;
assign keyb_rus = rus;
assign keyb_rst = rst;
assign keyb_pause = pause;
wire [6:0] dec_code;
ps2_keyb_driver kd (
ps2_clk,
ps2_data,
ps2_code,
ps2_up,
ps2_ext,
ps2_event
);
ag_keyb_decoder dec (
ps2_code,
ps2_ext,
lshift | rshift,
ctrl,
alt,
rus,
dec_code
);
always @(posedge clk) begin
if (keyb_clear) clr <= 1;
if (ps2_event && !got) begin
if (!ps2_up) begin
if (ps2_code == 8'h12 && ctrl) rus <= 0;
else if (ps2_code == 8'h14 && lshift) rus <= 0;
else if (ps2_code == 8'h59 && ctrl) rus <= 1;
else if (ps2_code == 8'h14 && rshift) rus <= 1;
clr <= 0;
keyb_code <= {|dec_code, dec_code};
end
if (ps2_code == 8'h12) lshift <= ~ps2_up;
else if (ps2_code == 8'h59) rshift <= ~ps2_up;
else if (ps2_code == 8'h14 || ps2_code == 8'h0D) ctrl <= ~ps2_up; // ctrl or tab
else if (ps2_code == 8'h11) alt <= ~ps2_up;
else if (ps2_code == 8'h7E) pause <= ~ps2_up;
if (ps2_code == 8'h76 && ctrl) rst <= ~ps2_up;
got <= 1;
end
if (!ps2_event) got <= 0;
end
endmodule
| 7.390119 |
module RAM2kx8 (
input CLK,
input [10:0] AB,
input CS,
input READ,
output [7:0] DO,
input [7:0] DI
);
reg [7:0] mem[0:2047];
reg [7:0] R;
assign DO = CS ? R : 8'bZ;
initial begin
`include "monitor7.v"
// mem['h7FA] = 8'h58;
// mem['h7FB] = 8'hF9;
mem['h7FC] = 8'h00;
mem['h7FD] = 8'h18;
end
always @(posedge CLK)
if (CS)
if (READ) R <= mem[AB];
else mem[AB] <= DI;
endmodule
| 6.924805 |
module RAM4kx8 (
input CLK,
input [11:0] AB,
input CS,
input READ,
output [7:0] DO,
input [7:0] DI
);
reg [7:0] mem[0:4095];
reg [7:0] R;
assign DO = CS ? R : 8'bZ;
always @(posedge CLK)
if (CS)
if (READ) R <= mem[AB];
else mem[AB] <= DI;
endmodule
| 7.142793 |
module RAM8kx8 (
input CLK,
input [12:0] AB,
input CS,
input READ,
output [7:0] DO,
input [7:0] DI
);
reg [7:0] mem[0:8191];
reg [7:0] R;
assign DO = CS ? R : 8'bZ;
always @(posedge CLK)
if (CS)
if (READ) R <= mem[AB];
else mem[AB] <= DI;
endmodule
| 7.295068 |
module RAM1Kx1 (
input CLK1,
input [9:0] AB1,
input CS1,
input READ,
output DO1,
input DI1,
input CLK2,
input [9:0] AB2,
input CS2,
output DO2
);
parameter FILL = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC;
reg mem[0:'h3FF];
integer i;
initial for (i = 0; i < 'h400; i = i + 1) mem[i] = (FILL & (256'b01 << (i & 'hFF))) ? 1'b1 : 1'b0;
assign DO1 = (CS1 && READ) ? mem[AB1] : 1'bZ;
assign DO2 = CS2 ? mem[AB2] : 1'bZ;
always @(posedge CLK1) if (CS1 && !READ) mem[AB1] <= DI1;
endmodule
| 6.503124 |
module RAM32Kx8x16 (
input CLK1,
input [14:0] AB1,
input CS1,
input READ,
output [7:0] DO1,
input [7:0] DI1,
input CLK2,
input [13:0] AB2,
input CS2,
output [15:0] DO2
);
wire [ 1:0] CSM = {(~AB1[0]) & CS1, AB1[0] & CS1}; // CS for modules
wire [13:0] AB1x = AB1[14:1];
`include "juke-box.v"
/* RAM16Kx1 ram0(CLK1, AB1x, CSM[0], READ, DO1[0], DI1[0], CLK2, AB2, CS2, DO2[0]);
RAM16Kx1 ram1(CLK1, AB1x, CSM[0], READ, DO1[1], DI1[1], CLK2, AB2, CS2, DO2[1]);
RAM16Kx1 ram2(CLK1, AB1x, CSM[0], READ, DO1[2], DI1[2], CLK2, AB2, CS2, DO2[2]);
RAM16Kx1 ram3(CLK1, AB1x, CSM[0], READ, DO1[3], DI1[3], CLK2, AB2, CS2, DO2[3]);
RAM16Kx1 ram4(CLK1, AB1x, CSM[0], READ, DO1[4], DI1[4], CLK2, AB2, CS2, DO2[4]);
RAM16Kx1 ram5(CLK1, AB1x, CSM[0], READ, DO1[5], DI1[5], CLK2, AB2, CS2, DO2[5]);
RAM16Kx1 ram6(CLK1, AB1x, CSM[0], READ, DO1[6], DI1[6], CLK2, AB2, CS2, DO2[6]);
RAM16Kx1 ram7(CLK1, AB1x, CSM[0], READ, DO1[7], DI1[7], CLK2, AB2, CS2, DO2[7]);
RAM16Kx1 ram8(CLK1, AB1x, CSM[1], READ, DO1[0], DI1[0], CLK2, AB2, CS2, DO2[8]);
RAM16Kx1 ram9(CLK1, AB1x, CSM[1], READ, DO1[1], DI1[1], CLK2, AB2, CS2, DO2[9]);
RAM16Kx1 ramA(CLK1, AB1x, CSM[1], READ, DO1[2], DI1[2], CLK2, AB2, CS2, DO2[10]);
RAM16Kx1 ramB(CLK1, AB1x, CSM[1], READ, DO1[3], DI1[3], CLK2, AB2, CS2, DO2[11]);
RAM16Kx1 ramC(CLK1, AB1x, CSM[1], READ, DO1[4], DI1[4], CLK2, AB2, CS2, DO2[12]);
RAM16Kx1 ramD(CLK1, AB1x, CSM[1], READ, DO1[5], DI1[5], CLK2, AB2, CS2, DO2[13]);
RAM16Kx1 ramE(CLK1, AB1x, CSM[1], READ, DO1[6], DI1[6], CLK2, AB2, CS2, DO2[14]);
RAM16Kx1 ramF(CLK1, AB1x, CSM[1], READ, DO1[7], DI1[7], CLK2, AB2, CS2, DO2[15]);*/
endmodule
| 7.702713 |
module FONT_ROM (
input [10:0] adr,
input cs,
output [7:0] DO
);
reg [7:0] mem[0:2047];
assign DO = cs ? mem[adr] : 8'bZ;
initial begin
`include "agathe7.v"
end
endmodule
| 8.099762 |
module AHA (
input x1,
x2,
output sum,
cout
);
assign sum = x1 | x2;
assign cout = x1 & x2;
endmodule
| 8.27824 |
module AhaAhbCodeRegion (
// Inputs
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire HREADY,
input wire [ 1:0] HTRANS,
input wire [ 2:0] HSIZE,
input wire HWRITE,
input wire [31:0] HADDR,
input wire [31:0] HWDATA,
// Outputs
output wire HREADYOUT,
output wire [ 1:0] HRESP,
output wire [31:0] HRDATA
);
//
// Internal Signals
//
wire sram_hreadyout;
wire [ 1:0] sram_hresp;
wire [31:0] sram_hrdata;
wire sram_hsel;
reg [31:0] int_addr;
wire default_sel;
assign default_sel = (|int_addr[31:17]);
assign sram_hsel = ~(|HADDR[31:17]) & HSEL;
//
// SRAM Wrapper Instantiation
//
AhaAhbRam128K #(
.IMAGE_FILE("ROM.hex")
) u_aha_ahb_ram_128k (
.HCLK (HCLK),
.HRESETn(HRESETn),
.HSEL (sram_hsel),
.HREADY(HREADY),
.HTRANS(HTRANS),
.HSIZE (HSIZE),
.HWRITE(HWRITE),
.HADDR (HADDR),
.HWDATA(HWDATA),
.HREADYOUT(sram_hreadyout),
.HRESP (sram_hresp),
.HRDATA (sram_hrdata)
);
//
// Target Selector
//
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) int_addr <= {32{1'b0}};
else if (HTRANS[1] & sram_hreadyout) int_addr <= HADDR;
end
assign HREADYOUT = default_sel ? 1'b1 : sram_hreadyout;
assign HRESP = default_sel ? 2'b01 : sram_hresp;
assign HRDATA = default_sel ? {32{1'b0}} : sram_hrdata;
endmodule
| 7.742278 |
module AhaAhbRam128K #(
parameter IMAGE_FILE = "None"
) (
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire HREADY,
input wire [ 1:0] HTRANS,
input wire [ 2:0] HSIZE,
input wire HWRITE,
input wire [31:0] HADDR,
input wire [31:0] HWDATA,
output wire HREADYOUT,
output wire [ 1:0] HRESP,
output wire [31:0] HRDATA
);
//
// Internal Signals
//
wire [14:0] sram_addr;
wire [31:0] sram_rdata;
wire [31:0] sram_wdata;
wire [ 3:0] sram_we;
wire sram_ce;
//
// AHB to SRAM Converter
//
cmsdk_ahb_to_sram #(
.AW(17)
) u_ahb_to_sram (
.HCLK (HCLK),
.HRESETn(HRESETn),
.HSEL (HSEL),
.HREADY(HREADY),
.HTRANS(HTRANS),
.HSIZE (HSIZE),
.HWRITE(HWRITE),
.HADDR (HADDR[16:0]),
.HWDATA(HWDATA),
.HREADYOUT(HREADYOUT),
.HRESP (HRESP[0]),
.HRDATA (HRDATA),
.SRAMRDATA(sram_rdata),
.SRAMADDR (sram_addr),
.SRAMWEN (sram_we),
.SRAMWDATA(sram_wdata),
.SRAMCS (sram_ce)
);
//
// SRAM Wrapper Instantiation
//
AhaSram32Kx32 #(
.IMAGE_FILE(IMAGE_FILE)
) u_aha_sram_32kx32 (
.CLK (HCLK),
.RESETn(HRESETn),
.CEn (~sram_ce),
.WEn (~sram_we),
.A (sram_addr),
.D (sram_wdata),
.Q (sram_rdata)
);
//
// Output Assignments
//
assign HRESP[1] = 1'b0;
endmodule
| 7.029429 |
module AhaAHBToParallel #(
parameter ADDR_WIDTH = 12
) (
// AHB Interface
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [ 1:0] HTRANS,
input wire HWRITE,
input wire [ 2:0] HSIZE,
input wire [ 2:0] HBURST,
input wire [ 3:0] HPROT,
input wire [ 3:0] HMASTER,
input wire [31:0] HWDATA,
input wire HMASTLOCK,
input wire HREADYMUX,
output wire [31:0] HRDATA,
output wire HREADYOUT,
output wire [ 1:0] HRESP,
// Ordt Parallel Interface
output wire [ADDR_WIDTH-1:0] PAR_ADDR,
output wire PAR_RD_EN,
output wire PAR_WR_EN,
output wire [ 3:0] PAR_WR_STRB,
output wire [ 31:0] PAR_WR_DATA,
input wire [ 31:0] PAR_RD_DATA,
input wire PAR_ACK,
input wire PAR_NACK
);
// Unused Wires (to avoid Lint warnings)
wire unused = (|HBURST) | (|HPROT) | (|HMASTER) | (|HMASTLOCK);
// Internal
wire trans_valid;
wire read_valid;
wire write_valid;
reg [ 3:0] byte_enable;
reg [ADDR_WIDTH-1:0] addr;
reg rd_en_r;
reg wr_en_r;
reg [ 3:0] wr_strb_r;
// Valid transaction signals
assign trans_valid = HSEL & HREADYMUX & HTRANS[1];
assign read_valid = trans_valid & ~HWRITE;
assign write_valid = trans_valid & HWRITE;
// Generate byte enable signals
always @(*) begin
case (HSIZE)
3'b000: begin
case (HADDR[1:0])
2'b00: byte_enable = 4'b0001;
2'b01: byte_enable = 4'b0010;
2'b10: byte_enable = 4'b0100;
2'b11: byte_enable = 4'b1000;
endcase
end
3'b001: begin
case (HADDR[1])
1'b0: byte_enable = 4'b0011;
1'b1: byte_enable = 4'b1100;
endcase
end
3'b010: byte_enable = 4'b1111;
default: byte_enable = 4'b0000;
endcase
end
// Transaction Control Registering (Address Phase)
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) begin
rd_en_r <= 1'b0;
wr_en_r <= 1'b0;
wr_strb_r <= 4'h0;
addr <= {ADDR_WIDTH{1'b0}};
end else begin
rd_en_r <= read_valid;
wr_en_r <= write_valid;
wr_strb_r <= byte_enable & {4{trans_valid}};
addr <= HADDR[ADDR_WIDTH-1:0];
end
end
// AHB Assignments
assign HRDATA = PAR_RD_DATA;
assign HRESP = 2'b00;
assign HREADYOUT = PAR_ACK | PAR_NACK;
// Parallel Interface Assignments
assign PAR_ADDR = addr;
assign PAR_RD_EN = rd_en_r;
assign PAR_WR_EN = wr_en_r;
assign PAR_WR_STRB = wr_strb_r;
assign PAR_WR_DATA = HWDATA;
endmodule
| 8.233608 |
module AhaAsyncPulseGen (
input wire CLK,
input wire RESETn,
input wire D,
output wire RISE_PULSE,
output wire FALL_PULSE
);
wire d_sync;
reg d_r;
AhaDataSync u_data_sync (
.CLK (CLK),
.RESETn(RESETn),
.D (D),
.Q (d_sync)
);
always @(posedge CLK or negedge RESETn) begin
if (~RESETn) d_r <= 1'b0;
else d_r <= d_sync;
end
assign RISE_PULSE = d_sync & ~d_r;
assign FALL_PULSE = ~d_sync & d_r;
endmodule
| 7.754295 |
module AhaAxiToSifRead (
input wire ACLK,
input wire ARESETn,
input wire [ 3:0] ARID,
input wire [31:0] ARADDR,
input wire [ 7:0] ARLEN,
input wire [ 2:0] ARSIZE,
input wire [ 1:0] ARBURST,
input wire ARLOCK,
input wire [ 3:0] ARCACHE,
input wire [ 2:0] ARPROT,
input wire ARVALID,
output wire ARREADY,
output wire [ 3:0] RID,
output wire [63:0] RDATA,
output wire [ 1:0] RRESP,
output wire RLAST,
output wire RVALID,
input wire RREADY,
output wire [31:0] SIF_ADDR,
output wire SIF_RE,
input wire [63:0] SIF_DATA,
input wire SIF_VALID
);
//
// Internal Signals
//
wire ARREADY_w;
wire RVALID_w;
wire RLAST_w;
wire [63:0] RDATA_w;
reg [ 3:0] RID_r;
//
// ID Reflection
//
always @(posedge ACLK or negedge ARESETn)
if (!ARESETn) RID_r <= 4'h0;
else if (ARVALID & ARREADY_w) RID_r <= ARID;
//
// Address Generator
//
AhaAxiToSifReadAddrGen u_addr_gen (
.ACLK (ACLK),
.ARESETn(ARESETn),
.ARADDR (ARADDR),
.ARBURST(ARBURST),
.ARSIZE (ARSIZE),
.ARLEN (ARLEN),
.ARVALID(ARVALID),
.ARREADY(ARREADY_w),
.RVALID (RVALID_w),
.RREADY (RREADY),
.RLAST (RLAST_w),
.SIF_RD_ADDR(SIF_ADDR),
.SIF_RD_EN (SIF_RE)
);
//
// Data
//
AhaAxiToSifReadData u_data (
.ACLK (ACLK),
.ARESETn(ARESETn),
.ARLEN (ARLEN),
.ARVALID(ARVALID),
.ARREADY(ARREADY_w),
.RREADY (RREADY),
.RVALID (RVALID_w),
.RLAST (RLAST_w),
.RDATA (RDATA_w),
.SIF_RD_DATA (SIF_DATA),
.SIF_RD_VALID(SIF_VALID)
);
//
// Output Assignments
//
assign ARREADY = ARREADY_w;
assign RVALID = RVALID_w;
assign RLAST = RLAST_w;
assign RID = RID_r;
assign RDATA = RDATA_w;
assign RRESP = 2'b00;
endmodule
| 7.36763 |
module AhaAxiToSifReadAddrGen (
input wire ACLK,
input wire ARESETn,
input wire [31:0] ARADDR,
input wire [ 1:0] ARBURST,
input wire [ 2:0] ARSIZE,
input wire [ 7:0] ARLEN,
input wire ARVALID,
output wire ARREADY,
input wire RVALID,
input wire RREADY,
input wire RLAST,
output wire [31:0] SIF_RD_ADDR,
output wire SIF_RD_EN
);
wire unused = (|ARBURST);
reg src_sel;
reg arready_r;
reg [31:0] AddrIncr;
reg [31:0] FinalAddr;
reg [31:0] NextRdAddr;
reg NextRdEn;
always @(posedge ACLK or negedge ARESETn) begin
if (~ARESETn) src_sel <= 1'b0;
else if (ARVALID & arready_r) src_sel <= 1'b1;
else if (RVALID & RREADY & RLAST) src_sel <= 1'b0;
end
always @(posedge ACLK or negedge ARESETn) begin
if (~ARESETn) arready_r <= 1'b1;
else if (ARVALID & arready_r) arready_r <= 1'b0;
else if (RVALID & RREADY & RLAST) arready_r <= 1'b1;
end
always @(posedge ACLK or negedge ARESETn) begin
if (~ARESETn) AddrIncr <= 32'h0;
else if (ARVALID & arready_r) begin
case (ARSIZE)
3'b000: AddrIncr <= {{28{1'b0}}, 4'h1};
3'b001: AddrIncr <= {{28{1'b0}}, 4'h2};
3'b010: AddrIncr <= {{28{1'b0}}, 4'h4};
3'b011: AddrIncr <= {{28{1'b0}}, 4'h8};
default: AddrIncr <= {32{1'bx}};
endcase
end
end
always @(posedge ACLK or negedge ARESETn) begin
if (~ARESETn) FinalAddr <= {32{1'b0}};
else if (ARVALID & arready_r) begin
case (ARSIZE)
3'b000: FinalAddr <= ARADDR + {{24{1'b0}}, ARLEN};
3'b001: FinalAddr <= ARADDR + {{23{1'b0}}, ARLEN, 1'b0};
3'b010: FinalAddr <= ARADDR + {{22{1'b0}}, ARLEN, 2'b00};
3'b011: FinalAddr <= ARADDR + {{21{1'b0}}, ARLEN, 3'b000};
default: FinalAddr <= {32{1'bx}};
endcase
end
end
always @(posedge ACLK or negedge ARESETn) begin
if (~ARESETn) NextRdAddr <= {32{1'b0}};
else if (ARVALID & arready_r) NextRdAddr <= ARADDR;
else if (src_sel && NextRdAddr < FinalAddr) NextRdAddr <= NextRdAddr + AddrIncr;
end
always @(posedge ACLK or negedge ARESETn) begin
if (~ARESETn) NextRdEn <= 1'b0;
else if (ARVALID & arready_r) NextRdEn <= 1'b1;
else if (src_sel && NextRdAddr < FinalAddr) NextRdEn <= 1'b1;
else NextRdEn <= 1'b0;
end
assign ARREADY = arready_r;
assign SIF_RD_EN = NextRdEn;
assign SIF_RD_ADDR = {NextRdAddr[31:3], 3'b000};
endmodule
| 7.36763 |
module AhaAxiToSifReadData (
input wire ACLK,
input wire ARESETn,
input wire [7:0] ARLEN,
input wire ARVALID,
input wire ARREADY,
input wire RREADY,
output wire RVALID,
output wire RLAST,
output wire [63:0] RDATA,
input wire [63:0] SIF_RD_DATA,
input wire SIF_RD_VALID
);
wire empty;
wire rvalid_w;
wire rlast_w;
wire push_req_n;
wire pop_req_n;
reg [7:0] count;
assign push_req_n = ~SIF_RD_VALID;
wire [63:0] rdata_w;
assign RDATA = rdata_w;
CW_fifo_s1_sf #(
.width(64),
.depth(32)
) u_fifo (
.clk (ACLK),
.rst_n(ARESETn),
.push_req_n(push_req_n),
.pop_req_n (pop_req_n),
.diag_n (1'b1),
.data_in (SIF_RD_DATA),
.empty (empty),
.almost_empty(),
.half_full (),
.almost_full (),
.full (),
.error (),
.data_out (rdata_w)
);
always @(posedge ACLK or negedge ARESETn) begin
if (~ARESETn) count <= 8'h00;
else if (ARVALID & ARREADY) count <= ARLEN;
else if (rvalid_w && RREADY && count > 8'h00) count <= count - 1'b1;
end
//always @(posedge ACLK or negedge ARESETn) begin
// if(~ARESETn) pop_req_n <= 1'b1;
// else if(RREADY & rvalid_w) pop_req_n <= 1'b0;
// else pop_req_n <= 1'b1;
//end
assign pop_req_n = ~(~empty & RREADY);
assign rvalid_w = ~empty;
assign rlast_w = rvalid_w && (count == 8'h00);
assign RVALID = rvalid_w;
assign RLAST = rlast_w;
endmodule
| 7.36763 |
module AhaAxiToSifWrite (
input wire ACLK,
input wire ARESETn,
input wire [ 3:0] AWID,
input wire [31:0] AWADDR,
input wire [ 7:0] AWLEN,
input wire [ 2:0] AWSIZE,
input wire [ 1:0] AWBURST,
input wire AWLOCK,
input wire [ 3:0] AWCACHE,
input wire [ 2:0] AWPROT,
input wire AWVALID,
output wire AWREADY,
input wire [63:0] WDATA,
input wire [ 7:0] WSTRB,
input wire WLAST,
input wire WVALID,
output wire WREADY,
output wire [3:0] BID,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
output wire [31:0] SIF_ADDR,
output wire [ 7:0] SIF_STRB,
output wire SIF_WE,
output wire [63:0] SIF_DATA
);
//
// Internal Signals
//
wire sram_ce_n;
wire sram_we_n;
wire [ 7:0] sram_wbe_n;
wire [31:0] sram_addr;
wire [63:0] sram_wdata;
//
// AXI to SRAM Converter
//
AXItoSRAM u_axi_to_sram (
.ACLK (ACLK),
.ARESETn(ARESETn),
.S_AXI_AWID (AWID),
.S_AXI_AWADDR (AWADDR),
.S_AXI_AWLEN (AWLEN),
.S_AXI_AWSIZE (AWSIZE),
.S_AXI_AWBURST(AWBURST),
.S_AXI_AWLOCK (AWLOCK),
.S_AXI_AWCACHE(AWCACHE),
.S_AXI_AWPROT (AWPROT),
.S_AXI_AWVALID(AWVALID),
.S_AXI_AWREADY(AWREADY),
.S_AXI_WDATA (WDATA),
.S_AXI_WSTRB (WSTRB),
.S_AXI_WLAST (WLAST),
.S_AXI_WVALID (WVALID),
.S_AXI_WREADY (WREADY),
.S_AXI_BID (BID),
.S_AXI_BRESP (BRESP),
.S_AXI_BVALID (BVALID),
.S_AXI_BREADY (BREADY),
.S_AXI_ARID (4'h0),
.S_AXI_ARADDR (32'h0),
.S_AXI_ARLEN (8'h0),
.S_AXI_ARSIZE (3'h0),
.S_AXI_ARBURST(2'h0),
.S_AXI_ARLOCK (1'b0),
.S_AXI_ARCACHE(4'h0),
.S_AXI_ARPROT (3'h0),
.S_AXI_ARVALID(1'b0),
.S_AXI_ARREADY(),
.S_AXI_RID (),
.S_AXI_RDATA (),
.S_AXI_RRESP (),
.S_AXI_RLAST (),
.S_AXI_RVALID (),
.S_AXI_RREADY (1'b1),
.SRAM_CEn (sram_ce_n),
.SRAM_ADDR (sram_addr),
.SRAM_WDATA(sram_wdata),
.SRAM_WEn (sram_we_n),
.SRAM_WBEn (sram_wbe_n),
.SRAM_RDATA(64'h0)
);
//
// Output Assignments
//
assign SIF_ADDR = sram_addr;
assign SIF_STRB = ~sram_wbe_n;
assign SIF_WE = ~(sram_ce_n | sram_we_n);
assign SIF_DATA = sram_wdata;
endmodule
| 6.797945 |
module AhaClockDivider (
// Inputs
input wire CLK_IN,
input wire RESETn,
// Outputs
output wire CLK_by_1,
output wire CLK_by_1_EN,
output wire CLK_by_2,
output wire CLK_by_2_EN,
output wire CLK_by_4,
output wire CLK_by_4_EN,
output wire CLK_by_8,
output wire CLK_by_8_EN,
output wire CLK_by_16,
output wire CLK_by_16_EN,
output wire CLK_by_32,
output wire CLK_by_32_EN
);
// Generated Clocks
wire clk_by_1_en_w;
wire clk_by_2_w;
wire clk_by_2_en_w;
wire clk_by_4_w;
wire clk_by_4_en_w;
wire clk_by_8_w;
wire clk_by_8_en_w;
wire clk_by_16_w;
wire clk_by_16_en_w;
wire clk_by_32_w;
wire clk_by_32_en_w;
// Reset Synchonization
wire reset_sync_n;
AhaResetSync u_rst_sync (
.CLK(CLK_IN),
.Dn (RESETn),
.Qn (reset_sync_n)
);
// Generated Clocks
AhaFreqDivider u_aha_freq_divider (
.CLK (CLK_IN),
.RESETn(RESETn),
.By2CLK (clk_by_2_w),
.By4CLK (clk_by_4_w),
.By8CLK (clk_by_8_w),
.By16CLK(clk_by_16_w),
.By32CLK(clk_by_32_w)
);
// Enable Signals
AhaEnGenerator u_aha_en_generator (
.CLK (CLK_IN),
.RESETn(RESETn),
.By2CLKEN (clk_by_2_en_w),
.By4CLKEN (clk_by_4_en_w),
.By8CLKEN (clk_by_8_en_w),
.By16CLKEN(clk_by_16_en_w),
.By32CLKEN(clk_by_32_en_w)
);
assign CLK_by_1 = CLK_IN;
assign CLK_by_1_EN = 1'b1;
assign CLK_by_2 = clk_by_2_w;
assign CLK_by_2_EN = clk_by_2_en_w;
assign CLK_by_4 = clk_by_4_w;
assign CLK_by_4_EN = clk_by_4_en_w;
assign CLK_by_8 = clk_by_8_w;
assign CLK_by_8_EN = clk_by_8_en_w;
assign CLK_by_16 = clk_by_16_w;
assign CLK_by_16_EN = clk_by_16_en_w;
assign CLK_by_32 = clk_by_32_w;
assign CLK_by_32_EN = clk_by_32_en_w;
endmodule
| 7.467431 |
module AhaClockEnGate (
input wire PORESETn,
input wire TE,
input wire E,
input wire CP, // clock associated with the clock enable signal
input wire CE, // clock enable signal
output wire Q
);
// Internal Wires and Regs
wire reset_n;
wire en;
reg en_r;
assign en = TE | E;
AhaResetSync u_rst_sync (
.CLK(CP),
.Dn (PORESETn),
.Qn (reset_n)
);
always @(posedge CP or negedge reset_n) begin
if (~reset_n) en_r <= 1'b0;
else en_r <= en;
end
// Output
assign Q = CE & en_r;
endmodule
| 7.200709 |
module AhaClockGate (
input wire TE,
input wire E,
input wire CP,
output wire Q
);
// Internal Wires and Regs
wire en;
reg en_r;
assign en = TE | E;
// Logic
always @(CP or en) begin
if (CP == 1'b0) en_r <= en;
end
// Output
assign Q = CP & en_r;
endmodule
| 6.821352 |
module AhaClockSwitch (
// Clock Signals
input wire CLK,
input wire CLK_EN,
// State of Other Clock Signals
input wire ALT_CLK_EN1,
input wire ALT_CLK_EN2,
input wire ALT_CLK_EN3,
input wire ALT_CLK_EN4,
input wire ALT_CLK_EN5,
// Selector Lines
input wire [2:0] SELECT_REQ,
input wire [2:0] SELECT_VAL,
// Output Clock Signals
output wire CLK_OUT,
output wire CLK_EN_OUT,
output wire SELECT_ACK
);
//
// Internal Signals
//
wire w_SEL;
wire w_OTHERS_SEL;
reg r_EN_STAGE0_SYNC;
reg r_EN_STATEG1;
reg r_EN;
wire w_CLK_OUT;
//
// Clock Selection Conditions
//
assign w_SEL = {1{SELECT_REQ == SELECT_VAL}};
assign w_OTHERS_SEL = ALT_CLK_EN1 | ALT_CLK_EN2 | ALT_CLK_EN3 | ALT_CLK_EN4 | ALT_CLK_EN5;
//
// Clock Selection Input Stages (Synchronization)
//
always @(posedge CLK) begin
r_EN_STAGE0_SYNC <= w_SEL & ~w_OTHERS_SEL;
r_EN_STATEG1 <= r_EN_STAGE0_SYNC;
end
//
// Clock Selection Output Stage (Clock Gating)
//
always @(negedge CLK) r_EN <= r_EN_STATEG1;
AhaClockGate u_clock_gate_CLK (
.TE(1'b0),
.E (r_EN),
.CP(CLK),
.Q (w_CLK_OUT)
);
//
// Output Assignments
//
assign CLK_OUT = w_CLK_OUT;
assign CLK_EN_OUT = CLK_EN & r_EN;
assign SELECT_ACK = r_EN;
endmodule
| 9.473661 |
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