code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Mux2x1 (
a,
b,
s,
c
);
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module DLatch (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, s, r, x, y;
AndGate S (
d,
d,
s
);
NotGate R (
d,
r
);
nand (x, c, s);
nand (y, c, r);
nand (q, q_, x);
nand (q_, q, y);
endmodule
| 6.957096 |
module DFlipFlopRE (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, Q, Q_;
NotGate C_ (
c,
c_
);
DLatch D1 (
d,
c_,
Q,
Q_
);
DLatch D2 (
Q,
c,
q,
q_
);
endmodule
| 7.021098 |
module Reg16Bit (
DIn,
clk,
cs,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, cs, w, r;
BinaryCell B[15:0] (
DIn,
clk,
cs,
w,
r,
DOut
);
endmodule
| 8.10144 |
module DeCoder2 (
e,
i,
o
);
output [1:0] o;
input e, i;
wire i_;
NotGate Ne (
i,
i_
);
AndGate O1 (
i_,
e,
o[0]
);
AndGate O2 (
i,
e,
o[1]
);
endmodule
| 7.055917 |
module DeCoder4 (
e,
i,
o
);
output [3:0] o;
input [1:0] i;
input e;
wire [1:0] t;
DeCoder2 D1 (
e,
i[1],
t[1:0]
);
DeCoder2 D2 (
t[1],
i[0],
o[3:2]
);
DeCoder2 D3 (
t[0],
i[0],
o[1:0]
);
endmodule
| 7.437067 |
module DeCoder8 (
e,
i,
o
);
output [7:0] o;
input [2:0] i;
input e;
wire [1:0] t;
DeCoder2 D1 (
e,
i[2],
t[1:0]
);
DeCoder4 D2 (
t[0],
i[1:0],
o[3:0]
);
DeCoder4 D3 (
t[1],
i[1:0],
o[7:4]
);
endmodule
| 7.495716 |
module Mux4x1 (
i0,
i1,
i2,
i3,
s1,
s0,
o
);
output o;
input i0, i1, i2, i3;
input s1, s0;
wire x, y;
Mux2x1 M_1 (
i0,
i1,
s1,
x
);
Mux2x1 M_2 (
i2,
i3,
s1,
y
);
Mux2x1 M_3 (
x,
y,
s0,
o
);
endmodu... | 8.038083 |
module Mux4x1_16 (
i0,
i1,
i2,
i3,
s,
o
);
output [15:0] o;
input [15:0] i0, i1, i2, i3;
input [1:0] s;
Mux4x1 M[15:0] (
i0,
i1,
i2,
i3,
s[0],
s[1],
o
);
endmodule
| 7.425005 |
module Mux8x1 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s0,
s1,
s2,
o
);
output o;
input i1, i2, i3, i4, i5, i6, i7, i8;
input s2, s1, s0;
wire x, y;
Mux4x1 M1 (
i1,
i2,
i3,
i4,
s0,
s1,
x
);
Mux4x1 M2 (
i5,
i6,... | 7.627269 |
module Mux8x1_16 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s,
o
);
output [15:0] o;
input [15:0] i1, i2, i3, i4, i5, i6, i7, i8;
input [2:0] s;
Mux8x1 M[15:0] (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s[0],
s[1],
s[2],
... | 8.13978 |
module RAM8 (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [2:0] addr;
wire [7:0] cs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 Addr (
e,
addr,
cs
);
Reg16Bit r1 (
DIn,
clk,
... | 6.996489 |
module RAM64 (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [5:0] addr;
wire [7:0] rs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 RAddr (
e,
addr[5:3],
rs
);
RAM8 R1 (
rs[0],
DIn,
... | 6.898444 |
module RAM512 (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [8:0] addr;
wire [7:0] rs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 RAddr (
e,
addr[8:6],
rs
);
RAM64 R1 (
rs[0],
DIn... | 6.993289 |
module RAM4K (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [11:0] addr;
wire [7:0] rs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 RAddr (
e,
addr[11:9],
rs
);
RAM512 R1 (
rs[0],
D... | 6.685573 |
module RAM16K (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [13:0] addr;
wire [3:0] rs;
wire [15:0] o1, o2, o3, o4;
DeCoder4 RAddr (
e,
addr[13:12],
rs
);
RAM4K R1 (
rs[0],
DIn,
clk,
... | 7.005768 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module XorGate (
a,
b,
c
);
output c;
input a, b;
wire a_, b_, x, y;
NotGate Na (
a,
a_
);
NotGate Nb (
b,
b_
);
AndGate A1 (
a,
b_,
x
);
AndGate A2 (
a_,
b,
y
);
OrGate O (
x,
y,
c
);
endmodule
| 7.413558 |
module DLatch (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, s, r, x, y;
AndGate S (
d,
d,
s
);
NotGate R (
d,
r
);
nand (x, c, s);
nand (y, c, r);
nand (q, q_, x);
nand (q_, q, y);
endmodule
| 6.957096 |
module DFlipFlopRE (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, Q, Q_;
NotGate C_ (
c,
c_
);
DLatch D1 (
d,
c_,
Q,
Q_
);
DLatch D2 (
Q,
c,
q,
q_
);
endmodule
| 7.021098 |
module Reg16Bit (
DIn,
clk,
cs,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, cs, w, r;
BinaryCell B[15:0] (
DIn,
clk,
cs,
w,
r,
DOut
);
endmodule
| 8.10144 |
module Mux2x1 (
a,
b,
s,
c
); // 12
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module RAM (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output reg [31:0] DOut;
input [15:0] DIn;
input [1:0] addr;
input r, w, clk, e;
reg [15:0] ram [1:0];
reg [31:0] ram_;
always @(posedge clk) begin
if (w) ram[addr] = DIn;
if (r) begin
if (addr > 1) DOut = ram_;
... | 6.786955 |
module StimModule2a;
wire [15:0] c;
reg clk;
reg [15:0] a, b;
Mod2a M (
a,
b,
c,
clk
);
initial begin
clk = 0;
end
always begin
clk = ~clk;
#1;
end
initial begin
a = 0;
b = 0;
#10;
a = 100;
#50;
b = 2;
#50;
a = 5;
#50;
... | 6.554988 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module XorGate (
a,
b,
c
);
output c;
input a, b;
wire a_, b_, x, y;
NotGate Na (
a,
a_
);
NotGate Nb (
b,
b_
);
AndGate A1 (
a,
b_,
x
);
AndGate A2 (
a_,
b,
y
);
OrGate O (
x,
y,
c
);
endmodule
| 7.413558 |
module Nand3 (
a,
b,
c,
o
);
output o;
input a, b, c;
wire x, y;
AndGate A (
a,
b,
x
);
AndGate B (
x,
c,
y
);
NotGate C (
y,
o
);
endmodule
| 6.937178 |
module DeCoder2 (
e,
i,
o
);
output [1:0] o;
input e, i;
wire i_;
NotGate Ne (
i,
i_
);
AndGate O1 (
i_,
e,
o[0]
);
AndGate O2 (
i,
e,
o[1]
);
endmodule
| 7.055917 |
module DeCoder4 (
e,
i,
o
);
output [3:0] o;
input [1:0] i;
input e;
wire [1:0] t;
DeCoder2 D1 (
e,
i[1],
t[1:0]
);
DeCoder2 D2 (
t[1],
i[0],
o[3:2]
);
DeCoder2 D3 (
t[0],
i[0],
o[1:0]
);
endmodule
| 7.437067 |
module DeCoder8 (
e,
i,
o
);
output [7:0] o;
input [2:0] i;
input e;
wire [1:0] t;
DeCoder2 D1 (
e,
i[2],
t[1:0]
);
DeCoder4 D2 (
t[0],
i[1:0],
o[3:0]
);
DeCoder4 D3 (
t[1],
i[1:0],
o[7:4]
);
endmodule
| 7.495716 |
module DLatch (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, s, r, x, y;
AndGate S (
d,
d,
s
);
NotGate R (
d,
r
);
nand (x, c, s);
nand (y, c, r);
nand (q, q_, x);
nand (q_, q, y);
endmodule
| 6.957096 |
module DFlipFlopRE (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, Q, Q_;
NotGate C_ (
c,
c_
);
DLatch D1 (
d,
c_,
Q,
Q_
);
DLatch D2 (
Q,
c,
q,
q_
);
endmodule
| 7.021098 |
module Reg16Bit (
DIn,
clk,
cs,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, cs, w, r;
BinaryCell B[15:0] (
DIn,
clk,
cs,
w,
r,
DOut
);
endmodule
| 8.10144 |
module Mux2x1 (
a,
b,
s,
c
);
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module Mux4x1 (
i0,
i1,
i2,
i3,
s1,
s0,
o
);
output o;
input i0, i1, i2, i3;
input s1, s0;
wire x, y;
Mux2x1 M_1 (
i0,
i1,
s1,
x
);
Mux2x1 M_2 (
i2,
i3,
s1,
y
);
Mux2x1 M_3 (
x,
y,
s0,
o
);
endmodu... | 8.038083 |
module Mux4x1_16 (
i0,
i1,
i2,
i3,
s,
o
);
output [15:0] o;
input [15:0] i0, i1, i2, i3;
input [1:0] s;
Mux4x1 M[15:0] (
i0,
i1,
i2,
i3,
s[0],
s[1],
o
);
endmodule
| 7.425005 |
module Mux8x1 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s0,
s1,
s2,
o
);
output o;
input i1, i2, i3, i4, i5, i6, i7, i8;
input s2, s1, s0;
wire x, y;
Mux4x1 M1 (
i1,
i2,
i3,
i4,
s0,
s1,
x
);
Mux4x1 M2 (
i5,
i6,... | 7.627269 |
module Mux8x1_16 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s,
o
);
output [15:0] o;
input [15:0] i1, i2, i3, i4, i5, i6, i7, i8;
input [2:0] s;
Mux8x1 M[15:0] (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s[0],
s[1],
s[2],
... | 8.13978 |
module RAM8 (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [2:0] addr;
wire [7:0] cs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 Addr (
e,
addr,
cs
);
Reg16Bit r1 (
DIn,
clk,
... | 6.996489 |
module StimModule2b;
wire [15:0] c;
reg clk;
reg [15:0] a, b;
Mod2b M (
a,
b,
c,
clk
);
initial begin
clk = 0;
end
always begin
clk = ~clk;
#1;
end
initial begin
a = 0;
b = 0;
#10;
a = 8;
#50;
b = 2;
#50;
a = 8;
#50;
b ... | 6.572711 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module XorGate (
a,
b,
c
);
output c;
input a, b;
wire a_, b_, x, y;
NotGate Na (
a,
a_
);
NotGate Nb (
b,
b_
);
AndGate A1 (
a,
b_,
x
);
AndGate A2 (
a_,
b,
y
);
OrGate O (
x,
y,
c
);
endmodule
| 7.413558 |
module Nand3 (
a,
b,
c,
o
);
output o;
input a, b, c;
wire x, y;
AndGate A (
a,
b,
x
);
AndGate B (
x,
c,
y
);
NotGate C (
y,
o
);
endmodule
| 6.937178 |
module DeCoder2 (
e,
i,
o
);
output [1:0] o;
input e, i;
wire i_;
NotGate Ne (
i,
i_
);
AndGate O1 (
i_,
e,
o[0]
);
AndGate O2 (
i,
e,
o[1]
);
endmodule
| 7.055917 |
module DeCoder4 (
e,
i,
o
);
output [3:0] o;
input [1:0] i;
input e;
wire [1:0] t;
DeCoder2 D1 (
e,
i[1],
t[1:0]
);
DeCoder2 D2 (
t[1],
i[0],
o[3:2]
);
DeCoder2 D3 (
t[0],
i[0],
o[1:0]
);
endmodule
| 7.437067 |
module DeCoder8 (
e,
i,
o
);
output [7:0] o;
input [2:0] i;
input e;
wire [1:0] t;
DeCoder2 D1 (
e,
i[2],
t[1:0]
);
DeCoder4 D2 (
t[0],
i[1:0],
o[3:0]
);
DeCoder4 D3 (
t[1],
i[1:0],
o[7:4]
);
endmodule
| 7.495716 |
module DLatch (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, s, r, x, y;
AndGate S (
d,
d,
s
);
NotGate R (
d,
r
);
nand (x, c, s);
nand (y, c, r);
nand (q, q_, x);
nand (q_, q, y);
endmodule
| 6.957096 |
module DFlipFlopRE (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, Q, Q_;
NotGate C_ (
c,
c_
);
DLatch D1 (
d,
c_,
Q,
Q_
);
DLatch D2 (
Q,
c,
q,
q_
);
endmodule
| 7.021098 |
module Reg16Bit (
DIn,
clk,
cs,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, cs, w, r;
BinaryCell B[15:0] (
DIn,
clk,
cs,
w,
r,
DOut
);
endmodule
| 8.10144 |
module Mux2x1 (
a,
b,
s,
c
);
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module Mux4x1 (
i0,
i1,
i2,
i3,
s1,
s0,
o
);
output o;
input i0, i1, i2, i3;
input s1, s0;
wire x, y;
Mux2x1 M_1 (
i0,
i1,
s1,
x
);
Mux2x1 M_2 (
i2,
i3,
s1,
y
);
Mux2x1 M_3 (
x,
y,
s0,
o
);
endmodu... | 8.038083 |
module Mux4x1_16 (
i0,
i1,
i2,
i3,
s,
o
);
output [15:0] o;
input [15:0] i0, i1, i2, i3;
input [1:0] s;
Mux4x1 M[15:0] (
i0,
i1,
i2,
i3,
s[0],
s[1],
o
);
endmodule
| 7.425005 |
module Mux8x1 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s0,
s1,
s2,
o
);
output o;
input i1, i2, i3, i4, i5, i6, i7, i8;
input s2, s1, s0;
wire x, y;
Mux4x1 M1 (
i1,
i2,
i3,
i4,
s0,
s1,
x
);
Mux4x1 M2 (
i5,
i6,... | 7.627269 |
module Mux8x1_16 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s,
o
);
output [15:0] o;
input [15:0] i1, i2, i3, i4, i5, i6, i7, i8;
input [2:0] s;
Mux8x1 M[15:0] (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s[0],
s[1],
s[2],
... | 8.13978 |
module RAM8 (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [2:0] addr;
wire [7:0] cs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 Addr (
e,
addr,
cs
);
Reg16Bit r1 (
DIn,
clk,
... | 6.996489 |
module Mod2d (
X,
Y,
Out,
clk
);
output [15:0] Out;
input [15:0] X, Y;
input clk;
reg [15:0] temp, diff;
initial begin
temp = 0;
diff = 0;
end
always @(X or Y) begin
diff = X - Y;
#5 temp = X;
end
Mod2b M (
temp,
diff,
Out,
clk
);
endmodu... | 6.740863 |
module AjustareExponent (
exponent,
valoarea2,
exponent_out
);
input wire [4:0] exponent;
input wire valoarea2;
output reg [4:0] exponent_out;
always @(exponent | valoarea2) begin
if (valoarea2 == 1'b1) begin
exponent_out = exponent + 1'b1;
end else begin
exponent_out = exponen... | 6.94024 |
module ajusta_bits (
switches,
ajusta_out
);
input [6:0] switches;
output reg [31:0] ajusta_out;
always @(*) begin
ajusta_out = {{28{1'b0}}, switches[3:0]};
end
endmodule
| 7.460056 |
module akiko (
input clk,
input cs,
input rd,
input wr,
input [ 5:1] addr,
input [15:0] din,
output reg [15:0] dout
);
wire c2p_sel = (addr[5:2] == 'b1110);
reg [7:0] buff[32];
reg [3:0] rptr = 0, wptr = 0;
always @(posedge... | 7.74058 |
module al422_bam_oe_processor(
in_nrst, in_clk, module_start, bit_counter, module_is_busy, led_oe
);
parameter OE_PRESCALER;
parameter OE_PREDELAY;
parameter OE_POSTDELAY;
parameter BITS_IN_COUNTER;
input wire in_nrst;
input wire in_clk;
input wire module_start;
input wire [BITS_IN_COUNTER - 1:0] bit_counte... | 7.629186 |
module ALARM_STATE_MACHINE (
input wire reset_n,
clk,
//set_time,
alarm,
//Toggle_switch,
hours_set,
mins_set,
//output reg [4 : 0] hour,
// reg [5 : 0] mins,
output reg hours,
mins
);
parameter first = 2'b00, second = 2'b01, third = 2'b10, four = 2'b11;
reg [... | 7.587361 |
module Alarma (
clk,
rx,
Hora_actual,
sensores,
Activada,
Sonando,
accion,
dutty,
done,
an,
sseg,
init
);
input clk;
input rx;
input [23:0] Hora_actual;
input sensores;
output Activada;
output Sonando;
output [1:0] accion;
output [15:0] dutty;
output do... | 7.218662 |
module AlarmaAnimal (
input m,
input ta,
input tb,
output alarma
);
assign alarma = (m & ta) | tb;
endmodule
| 7.155666 |
module Alarma_FSM (
clk,
Hora_actual,
Hora_alarma,
sensores,
Activada,
Sonando,
accion,
dutty
);
input clk;
input [23:0] Hora_actual;
input [23:0] Hora_alarma;
input sensores;
output reg Activada;
output reg Sonando;
output reg [1:0] accion;
output reg [15:0] dutty;
r... | 6.617418 |
module alarmBuzz (
uclock,
msClock,
tobuzzer,
buzzer
);
input msClock;
input uclock;
input tobuzzer;
output reg buzzer;
reg [9:0] waitTime;
reg [3:0] state;
reg [3:0] nextState;
// Begin with all Registers at 0
initial begin
waitTime = 0;
state = 0;
nextState = 0;
end
... | 7.413856 |
module DigitalClock_12hrFormat (
input clk,
input center,
input right,
input left,
input up,
input down,
input M_00,
input M_01,
input M_02,
input M_03,
input M_10,
input M_11,
input M_12,
input H_00,
input H_01,
input H_02,
input H_10,
input H_11,... | 7.319542 |
module alarming (
alarmSwitch,
alarmStatus,
alarmRing,
buzzer,
uclock,
a0,
a1,
a2,
a3,
t0,
t1,
t2,
t3,
switch,
switch2
);
input alarmSwitch, uclock, switch, switch2;
input [3:0] a0, a1, a2, a3, t0, t1, t2, t3;
output reg alarmStatus, alarmRing, buzzer;
... | 6.536672 |
module AlarmRun (
input [5:0] hour_set,
input [5:0] minute_set,
input [5:0] second_set, //用于设定闹钟的变量
input [5:0] hour,
input [5:0] minute,
input [5:0] second,
input CLK_50,
input alarm_set,
input one_second_clk, // 每秒的时钟周期
output [3:0] LEDR,
output reg LEDAlarm, // 测试用... | 8.750687 |
module alarm_clk(
Clock_1sec, Reset, LoadTime, LoadAlm, AlarmEnable,
Set_AM_PM, Alarm_AM_PM_In,
SetSecs, SetMins, AlarmMinsIn, SetHours, AlarmHoursIn,
AM_PM, Alarm, Secs_C, Mins_C, Hours_C);
input Clock_1sec, Reset, LoadTime, LoadAlm, Set_AM_PM,... | 7.201232 |
module alarm_clock_top (
input clock,
reset,
time_button,
alarm_button,
fast_watch,
input [3:0] key,
output [7:0] ms_hour,
ls_hour,
ms_minute,
ls_minute,
output alarm_sound
);
//Define the Interconnecting internal wires
wire reset_count, one_minute, one_second, load_new_c... | 7.307734 |
module alarm_fsm #(
parameter SIZE = 4
) (
input rst,
input sec_clk,
input enable,
input [SIZE-1:0] max,
output [SIZE-1:0] count,
output alarm
);
reg [SIZE-1:0] count_ff;
reg alarm_ff;
reg alarm_nxt;
assign count... | 7.131 |
module alarm_fsm_test ();
localparam SIZE = 4;
reg rst, enable, sec_clk;
reg [SIZE-1:0] max;
wire [SIZE-1:0] count;
wire alarm;
vlog_tb_utils vlog_tb_utils0 ();
initial begin
rst = 0;
enable = 0;
sec_clk = 0;
max = 4'b0;
end
always #5 sec_clk = !sec_clk;
initial begin
#15 r... | 7.131584 |
module alarm_len_conved (
enable,
sec_clk,
cur_sec,
tar_sec,
len_s,
off,
alarming
);
input enable, sec_clk, off;
input [16:0] cur_sec, tar_sec;
input [1:0] len_s;
reg [5:0] len;
output reg alarming = 0;
reg alarm_off = 0;
always @(posedge sec_clk) begin
case (len_s)
... | 6.906836 |
module alarm_register (
input [15:0] set_data,
input load_alarm,
clk,
reset,
output reg [15:0] alarm_data
);
always @(posedge clk, negedge reset) begin
if (!reset) alarm_data <= 0;
else if (load_alarm) alarm_data <= set_data;
else alarm_data <= 0;
end
endmodule
| 8.958344 |
module ALARM_SM (
input wire reset_n,
clk,
Toggle_switch,
RINGER1,
output reg SPEAKER_OUT
);
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
SPEAKER_OUT = 0;
end else begin
if (Toggle_switch & RINGER1) SPEAKER_OUT = 1;
else SPEAKER_OUT = 0;
end... | 7.932963 |
module ALARM_SM_2 (
input wire reset_n,
clk,
Toggle_switch,
MATCH, // flag of alarm time equal to current time
output reg SPEAKER_OUT
);
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
SPEAKER_OUT = 0;
end else begin
if (Toggle_switch & MATCH) SPEAKER_OUT = ... | 7.837466 |
module ALARM_STATE_MACHINE (
input wire reset_n,
clk,
alarm,
hours_set,
mins_set,
output reg hours,
mins
);
parameter IDLE = 2'b00, MINS_S = 2'b01, HOURS_S = 2'b10, BOTH = 2'b11;
reg [1 : 0] state;
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
hours = ... | 7.587361 |
module alarm_system (
input wire CLK,
RESET,
bt_inc,
bt_sel,
bt_mode,
uart_rx,
output wire uart_tx,
output wire [7:0] leds,
output wire [6:0] seg7s0,
seg7s1,
seg7m0,
seg7m1,
seg7h0,
seg7h1
);
system alarmSystem (
bt_inc,
bt_mode,
bt_sel,
... | 6.899929 |
module: alarm
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alarm_tb;
// Inputs
reg N;
reg X;
reg W;
reg D;
reg G;
// Outputs
wire A;
integer i;
// Instantiate the Uni... | 7.187895 |
module ALARM_TIME_CONT (
RESETN,
CLK,
IN_TIME,
FLAG,
UP,
DOWN,
OUT_TIME
);
input RESETN, CLK;
input [16:0] IN_TIME;
input [2:0] FLAG;
input [2:0] UP, DOWN;
output wire [16:0] OUT_TIME;
/* FLAG */
parameter FLAG_ALARM_CONTROL_STATE = 3'b011;
/* CONTROL SELECTER LIST */
pa... | 7.592128 |
module alarm_tone #(
parameter CLK_FREQ = 12_000_000
) (
input clk,
output reg speaker
);
localparam divider0 = CLK_FREQ / 220 / 2;
reg [$clog2(divider0)-1:0] counter0;
always @(posedge clk) begin
if (!counter0) begin
counter0 <= divider0 - 1;
end else begin
counter0 <= counter0 ... | 7.316437 |
module alarm_wrap (
clk,
rst,
btn,
speaker,
onehz,
seg_en,
seg_out
);
input clk, rst, btn;
output speaker, onehz;
output [7:0] seg_en, seg_out;
wire [16:0] cur_sec;
reg [16:0] tar_sec = 10;
reg [ 5:0] len = 60;
wire [3:0] h1, h2, m1, m2, s1, s2;
gene_1hz gen (
clk... | 6.728706 |
module alaw_coder #(
parameter DATA_IN_W = 15, // Data input width
parameter DATA_OUT_W = 8 // Data output width
) (
// System
input wire clk, // System clock
input wire rst, // System reset
// Input data
input wire [ DATA_IN_W-1:0] data_... | 8.189844 |
module alaw_decoder (
input_alaw,
output_lin
);
input [7:0] input_alaw;
output [12:0] output_lin;
reg [11:0] output_unsigned;
reg [ 3:0] bits;
always @(input_alaw) begin
bits = input_alaw[3:0];
case (input_alaw[6:4])
3'b000: output_unsigned = {7'b000_0000, bits, 1'b1};
3'b001: ... | 7.191147 |
module ALC (
out,
sample,
multiply
);
output wire [15:0] out;
input [15:0] sample;
input [15:0] multiply;
wire [47:0] result;
wire [15:0] pos_sample;
assign pos_sample = sample[15] ? (~sample + 1'b1) : sample; // convert to positive if negative
assign result = pos_sample * multiply; // ... | 7.271343 |
module alct_lfsr_rng (
clock,
ce,
reset,
lfsr
);
// Generic
// parameter LFSR_LENGTH = 56;
parameter LFSR_LENGTH = 49;
// Ports
input clock; // 40 Mhz clock
input ce; // Clock enable
input reset; // Restart series
output reg [LFSR_LENGTH-1:0] lfsr; // Random series
// LFSR Rand... | 7.437358 |
module ALEGen (
input clk,
input rst_n,
output reg ALE
);
reg [2:0] cnt;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
ALE <= 1'b1;
cnt <= 3'b0;
end else begin
if (cnt == 1) begin
ALE <= ~ALE;
cnt <= cnt + 1;
end else begin
... | 7.922969 |
module alejandro (
input [3:0] D,
output reg [7:0] SEG
);
always @(*) begin
case (D)
4'd0: SEG <= 8'b00010001;
4'd1: SEG <= 8'b11100011;
4'd2: SEG <= 8'b01100001;
4'd3: SEG <= 8'b10001111;
4'd4: SEG <= 8'b00010001;
4'd5: SEG <= 8'b00010011;
4'd6: SEG <= 8'b100001... | 6.817937 |
module alert_player (
input clk,
rst,
set,
output buzzer
);
parameter hz = 12'd440;
parameter length = 12'd400;
wire ms_clk, ms_edge;
clk_div #(100_000) ms_clk_inst (
clk,
rst,
ms_clk
);
edge_gen ms_edge_gen_inst (
clk,
ms_clk,
ms_edge
);
reg [11:0... | 7.504681 |
module alex (
frequency_HZ,
ATTEN,
SPI_data,
PTT_out,
Tx_load_strobe,
Rx_load_strobe,
SPI_clock,
clock
);
input [31:0] frequency_HZ;
input [1:0] ATTEN;
input PTT_out;
output SPI_data;
output Tx_load_strobe;
output Rx_load_strobe;
output SPI_clock;
input clock;
wire [... | 8.143994 |
module Alex_relays (
TX_relay,
RX_relay,
Rout,
ANT1,
ANT2,
ANT3,
Rx_1_out,
Rx_1_in,
Rx_2_in,
Transverter
);
input [1:0] TX_relay;
input [1:0] RX_relay;
input Rout;
output ANT1;
output ANT2;
output ANT3;
output Rx_1_out;
output Rx_1_in;
output Rx_2_in;
output ... | 6.771213 |
module Alfa_desc (
Tom,
notas1,
notas2,
notas3,
saida1,
saida2,
saida3,
saida4,
saida5,
saida6,
saida7
);
input wire Tom;
input wire notas1, notas2, notas3; //B, C e D
output reg saida1, saida2, saida3, saida4, saida5, saida6, saida7;
always @(*) begin
saida1 =... | 6.747634 |
module spmv_PP #(
parameter PIPE_DEPTH = 5,
parameter URAM_DATA_W = 32,
parameter PAR_SIZE_W = 10,
parameter EDGE_W = 96
) (
input wire clk,
input wire rst,
input wire [ 1:0] control,
input wire [URAM_DATA_W-1:0] buffer_Din,
input w... | 6.633763 |
module spmv_gather_pipe #(
parameter PIPE_DEPTH = 3,
parameter PAR_SIZE_W = 18
) (
input wire clk,
input wire rst,
input wire [ 31:0] update_value,
input wire [ 31:0] update_dest,
input wire [ 63:0] dest_attr,
input wire ... | 8.017521 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.