code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Mux2x1 (
a,
b,
s,
c
);
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module DLatch (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, s, r, x, y;
AndGate S (
d,
d,
s
);
NotGate R (
d,
r
);
nand (x, c, s);
nand (y, c, r);
nand (q, q_, x);
nand (q_, q, y);
endmodule
| 6.957096 |
module DFlipFlopRE (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, Q, Q_;
NotGate C_ (
c,
c_
);
DLatch D1 (
d,
c_,
Q,
Q_
);
DLatch D2 (
Q,
c,
q,
q_
);
endmodule
| 7.021098 |
module Reg16Bit (
DIn,
clk,
cs,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, cs, w, r;
BinaryCell B[15:0] (
DIn,
clk,
cs,
w,
r,
DOut
);
endmodule
| 8.10144 |
module DeCoder2 (
e,
i,
o
);
output [1:0] o;
input e, i;
wire i_;
NotGate Ne (
i,
i_
);
AndGate O1 (
i_,
e,
o[0]
);
AndGate O2 (
i,
e,
o[1]
);
endmodule
| 7.055917 |
module DeCoder4 (
e,
i,
o
);
output [3:0] o;
input [1:0] i;
input e;
wire [1:0] t;
DeCoder2 D1 (
e,
i[1],
t[1:0]
);
DeCoder2 D2 (
t[1],
i[0],
o[3:2]
);
DeCoder2 D3 (
t[0],
i[0],
o[1:0]
);
endmodule
| 7.437067 |
module DeCoder8 (
e,
i,
o
);
output [7:0] o;
input [2:0] i;
input e;
wire [1:0] t;
DeCoder2 D1 (
e,
i[2],
t[1:0]
);
DeCoder4 D2 (
t[0],
i[1:0],
o[3:0]
);
DeCoder4 D3 (
t[1],
i[1:0],
o[7:4]
);
endmodule
| 7.495716 |
module Mux4x1 (
i0,
i1,
i2,
i3,
s1,
s0,
o
);
output o;
input i0, i1, i2, i3;
input s1, s0;
wire x, y;
Mux2x1 M_1 (
i0,
i1,
s1,
x
);
Mux2x1 M_2 (
i2,
i3,
s1,
y
);
Mux2x1 M_3 (
x,
y,
s0,
o
);
endmodule
| 8.038083 |
module Mux4x1_16 (
i0,
i1,
i2,
i3,
s,
o
);
output [15:0] o;
input [15:0] i0, i1, i2, i3;
input [1:0] s;
Mux4x1 M[15:0] (
i0,
i1,
i2,
i3,
s[0],
s[1],
o
);
endmodule
| 7.425005 |
module Mux8x1 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s0,
s1,
s2,
o
);
output o;
input i1, i2, i3, i4, i5, i6, i7, i8;
input s2, s1, s0;
wire x, y;
Mux4x1 M1 (
i1,
i2,
i3,
i4,
s0,
s1,
x
);
Mux4x1 M2 (
i5,
i6,
i7,
i8,
s0,
s1,
y
);
Mux2x1 M3 (
x,
y,
s2,
o
);
endmodule
| 7.627269 |
module Mux8x1_16 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s,
o
);
output [15:0] o;
input [15:0] i1, i2, i3, i4, i5, i6, i7, i8;
input [2:0] s;
Mux8x1 M[15:0] (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s[0],
s[1],
s[2],
o
);
endmodule
| 8.13978 |
module RAM8 (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [2:0] addr;
wire [7:0] cs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 Addr (
e,
addr,
cs
);
Reg16Bit r1 (
DIn,
clk,
cs[0],
w,
r,
o1
);
Reg16Bit r2 (
DIn,
clk,
cs[1],
w,
r,
o2
);
Reg16Bit r3 (
DIn,
clk,
cs[2],
w,
r,
o3
);
Reg16Bit r4 (
DIn,
clk,
cs[3],
w,
r,
o4
);
Reg16Bit r5 (
DIn,
clk,
cs[4],
w,
r,
o5
);
Reg16Bit r6 (
DIn,
clk,
cs[5],
w,
r,
o6
);
Reg16Bit r7 (
DIn,
clk,
cs[6],
w,
r,
o7
);
Reg16Bit r8 (
DIn,
clk,
cs[7],
w,
r,
o8
);
Mux8x1_16 M (
o1,
o2,
o3,
o4,
o5,
o6,
o7,
o8,
addr,
DOut
);
endmodule
| 6.996489 |
module RAM64 (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [5:0] addr;
wire [7:0] rs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 RAddr (
e,
addr[5:3],
rs
);
RAM8 R1 (
rs[0],
DIn,
clk,
addr[2:0],
w,
r,
o1
);
RAM8 R2 (
rs[1],
DIn,
clk,
addr[2:0],
w,
r,
o2
);
RAM8 R3 (
rs[2],
DIn,
clk,
addr[2:0],
w,
r,
o3
);
RAM8 R4 (
rs[3],
DIn,
clk,
addr[2:0],
w,
r,
o4
);
RAM8 R5 (
rs[4],
DIn,
clk,
addr[2:0],
w,
r,
o5
);
RAM8 R6 (
rs[5],
DIn,
clk,
addr[2:0],
w,
r,
o6
);
RAM8 R7 (
rs[6],
DIn,
clk,
addr[2:0],
w,
r,
o7
);
RAM8 R8 (
rs[7],
DIn,
clk,
addr[2:0],
w,
r,
o8
);
Mux8x1_16 M (
o1,
o2,
o3,
o4,
o5,
o6,
o7,
o8,
addr[5:3],
DOut
);
endmodule
| 6.898444 |
module RAM512 (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [8:0] addr;
wire [7:0] rs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 RAddr (
e,
addr[8:6],
rs
);
RAM64 R1 (
rs[0],
DIn,
clk,
addr[5:0],
w,
r,
o1
);
RAM64 R2 (
rs[1],
DIn,
clk,
addr[5:0],
w,
r,
o2
);
RAM64 R3 (
rs[2],
DIn,
clk,
addr[5:0],
w,
r,
o3
);
RAM64 R4 (
rs[3],
DIn,
clk,
addr[5:0],
w,
r,
o4
);
RAM64 R5 (
rs[4],
DIn,
clk,
addr[5:0],
w,
r,
o5
);
RAM64 R6 (
rs[5],
DIn,
clk,
addr[5:0],
w,
r,
o6
);
RAM64 R7 (
rs[6],
DIn,
clk,
addr[5:0],
w,
r,
o7
);
RAM64 R8 (
rs[7],
DIn,
clk,
addr[5:0],
w,
r,
o8
);
Mux8x1_16 M (
o1,
o2,
o3,
o4,
o5,
o6,
o7,
o8,
addr[8:6],
DOut
);
endmodule
| 6.993289 |
module RAM4K (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [11:0] addr;
wire [7:0] rs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 RAddr (
e,
addr[11:9],
rs
);
RAM512 R1 (
rs[0],
DIn,
clk,
addr[8:0],
w,
r,
o1
);
RAM512 R2 (
rs[1],
DIn,
clk,
addr[8:0],
w,
r,
o2
);
RAM512 R3 (
rs[2],
DIn,
clk,
addr[8:0],
w,
r,
o3
);
RAM512 R4 (
rs[3],
DIn,
clk,
addr[8:0],
w,
r,
o4
);
RAM512 R5 (
rs[4],
DIn,
clk,
addr[8:0],
w,
r,
o5
);
RAM512 R6 (
rs[5],
DIn,
clk,
addr[8:0],
w,
r,
o6
);
RAM512 R7 (
rs[6],
DIn,
clk,
addr[8:0],
w,
r,
o7
);
RAM512 R8 (
rs[7],
DIn,
clk,
addr[8:0],
w,
r,
o8
);
Mux8x1_16 M (
o1,
o2,
o3,
o4,
o5,
o6,
o7,
o8,
addr[11:9],
DOut
);
endmodule
| 6.685573 |
module RAM16K (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [13:0] addr;
wire [3:0] rs;
wire [15:0] o1, o2, o3, o4;
DeCoder4 RAddr (
e,
addr[13:12],
rs
);
RAM4K R1 (
rs[0],
DIn,
clk,
addr[11:0],
w,
r,
o1
);
RAM4K R2 (
rs[1],
DIn,
clk,
addr[11:0],
w,
r,
o2
);
RAM4K R3 (
rs[2],
DIn,
clk,
addr[11:0],
w,
r,
o3
);
RAM4K R4 (
rs[3],
DIn,
clk,
addr[11:0],
w,
r,
o4
);
Mux4x1_16 M (
o1,
o2,
o3,
o4,
addr[13:12],
DOut
);
endmodule
| 7.005768 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module XorGate (
a,
b,
c
);
output c;
input a, b;
wire a_, b_, x, y;
NotGate Na (
a,
a_
);
NotGate Nb (
b,
b_
);
AndGate A1 (
a,
b_,
x
);
AndGate A2 (
a_,
b,
y
);
OrGate O (
x,
y,
c
);
endmodule
| 7.413558 |
module DLatch (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, s, r, x, y;
AndGate S (
d,
d,
s
);
NotGate R (
d,
r
);
nand (x, c, s);
nand (y, c, r);
nand (q, q_, x);
nand (q_, q, y);
endmodule
| 6.957096 |
module DFlipFlopRE (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, Q, Q_;
NotGate C_ (
c,
c_
);
DLatch D1 (
d,
c_,
Q,
Q_
);
DLatch D2 (
Q,
c,
q,
q_
);
endmodule
| 7.021098 |
module Reg16Bit (
DIn,
clk,
cs,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, cs, w, r;
BinaryCell B[15:0] (
DIn,
clk,
cs,
w,
r,
DOut
);
endmodule
| 8.10144 |
module Mux2x1 (
a,
b,
s,
c
); // 12
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module RAM (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output reg [31:0] DOut;
input [15:0] DIn;
input [1:0] addr;
input r, w, clk, e;
reg [15:0] ram [1:0];
reg [31:0] ram_;
always @(posedge clk) begin
if (w) ram[addr] = DIn;
if (r) begin
if (addr > 1) DOut = ram_;
else DOut = {{32 - 16{1'b0}}, ram[addr]};
end
end
reg [31:0] product;
reg [15:0] multiplicand, multiplier;
integer i;
always @(ram[0] or ram[1]) begin
assign multiplicand = ram[0];
assign multiplier = ram[1];
product = 0;
for (i = 0; i < 16; i = i + 1) begin
if (multiplier[i]) product = product + (multiplicand << i);
end
ram_ = product;
end
endmodule
| 6.786955 |
module StimModule2a;
wire [15:0] c;
reg clk;
reg [15:0] a, b;
Mod2a M (
a,
b,
c,
clk
);
initial begin
clk = 0;
end
always begin
clk = ~clk;
#1;
end
initial begin
a = 0;
b = 0;
#10;
a = 100;
#50;
b = 2;
#50;
a = 5;
#50;
b = 6;
#50;
end
endmodule
| 6.554988 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module XorGate (
a,
b,
c
);
output c;
input a, b;
wire a_, b_, x, y;
NotGate Na (
a,
a_
);
NotGate Nb (
b,
b_
);
AndGate A1 (
a,
b_,
x
);
AndGate A2 (
a_,
b,
y
);
OrGate O (
x,
y,
c
);
endmodule
| 7.413558 |
module Nand3 (
a,
b,
c,
o
);
output o;
input a, b, c;
wire x, y;
AndGate A (
a,
b,
x
);
AndGate B (
x,
c,
y
);
NotGate C (
y,
o
);
endmodule
| 6.937178 |
module DeCoder2 (
e,
i,
o
);
output [1:0] o;
input e, i;
wire i_;
NotGate Ne (
i,
i_
);
AndGate O1 (
i_,
e,
o[0]
);
AndGate O2 (
i,
e,
o[1]
);
endmodule
| 7.055917 |
module DeCoder4 (
e,
i,
o
);
output [3:0] o;
input [1:0] i;
input e;
wire [1:0] t;
DeCoder2 D1 (
e,
i[1],
t[1:0]
);
DeCoder2 D2 (
t[1],
i[0],
o[3:2]
);
DeCoder2 D3 (
t[0],
i[0],
o[1:0]
);
endmodule
| 7.437067 |
module DeCoder8 (
e,
i,
o
);
output [7:0] o;
input [2:0] i;
input e;
wire [1:0] t;
DeCoder2 D1 (
e,
i[2],
t[1:0]
);
DeCoder4 D2 (
t[0],
i[1:0],
o[3:0]
);
DeCoder4 D3 (
t[1],
i[1:0],
o[7:4]
);
endmodule
| 7.495716 |
module DLatch (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, s, r, x, y;
AndGate S (
d,
d,
s
);
NotGate R (
d,
r
);
nand (x, c, s);
nand (y, c, r);
nand (q, q_, x);
nand (q_, q, y);
endmodule
| 6.957096 |
module DFlipFlopRE (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, Q, Q_;
NotGate C_ (
c,
c_
);
DLatch D1 (
d,
c_,
Q,
Q_
);
DLatch D2 (
Q,
c,
q,
q_
);
endmodule
| 7.021098 |
module Reg16Bit (
DIn,
clk,
cs,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, cs, w, r;
BinaryCell B[15:0] (
DIn,
clk,
cs,
w,
r,
DOut
);
endmodule
| 8.10144 |
module Mux2x1 (
a,
b,
s,
c
);
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module Mux4x1 (
i0,
i1,
i2,
i3,
s1,
s0,
o
);
output o;
input i0, i1, i2, i3;
input s1, s0;
wire x, y;
Mux2x1 M_1 (
i0,
i1,
s1,
x
);
Mux2x1 M_2 (
i2,
i3,
s1,
y
);
Mux2x1 M_3 (
x,
y,
s0,
o
);
endmodule
| 8.038083 |
module Mux4x1_16 (
i0,
i1,
i2,
i3,
s,
o
);
output [15:0] o;
input [15:0] i0, i1, i2, i3;
input [1:0] s;
Mux4x1 M[15:0] (
i0,
i1,
i2,
i3,
s[0],
s[1],
o
);
endmodule
| 7.425005 |
module Mux8x1 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s0,
s1,
s2,
o
);
output o;
input i1, i2, i3, i4, i5, i6, i7, i8;
input s2, s1, s0;
wire x, y;
Mux4x1 M1 (
i1,
i2,
i3,
i4,
s0,
s1,
x
);
Mux4x1 M2 (
i5,
i6,
i7,
i8,
s0,
s1,
y
);
Mux2x1 M3 (
x,
y,
s2,
o
);
endmodule
| 7.627269 |
module Mux8x1_16 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s,
o
);
output [15:0] o;
input [15:0] i1, i2, i3, i4, i5, i6, i7, i8;
input [2:0] s;
Mux8x1 M[15:0] (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s[0],
s[1],
s[2],
o
);
endmodule
| 8.13978 |
module RAM8 (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [2:0] addr;
wire [7:0] cs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 Addr (
e,
addr,
cs
);
Reg16Bit r1 (
DIn,
clk,
cs[0],
w,
r,
o1
);
Reg16Bit r2 (
DIn,
clk,
cs[1],
w,
r,
o2
);
Reg16Bit r3 (
DIn,
clk,
cs[2],
w,
r,
o3
);
Reg16Bit r4 (
DIn,
clk,
cs[3],
w,
r,
o4
);
Reg16Bit r5 (
DIn,
clk,
cs[4],
w,
r,
o5
);
Reg16Bit r6 (
DIn,
clk,
cs[5],
w,
r,
o6
);
Reg16Bit r7 (
DIn,
clk,
cs[6],
w,
r,
o7
);
Reg16Bit r8 (
DIn,
clk,
cs[7],
w,
r,
o8
);
Mux8x1_16 M (
o1,
o2,
o3,
o4,
o5,
o6,
o7,
o8,
addr,
DOut
);
endmodule
| 6.996489 |
module StimModule2b;
wire [15:0] c;
reg clk;
reg [15:0] a, b;
Mod2b M (
a,
b,
c,
clk
);
initial begin
clk = 0;
end
always begin
clk = ~clk;
#1;
end
initial begin
a = 0;
b = 0;
#10;
a = 8;
#50;
b = 2;
#50;
a = 8;
#50;
b = 3;
#50;
a = 5;
#50;
b = 2;
#50;
a = 6;
#50;
b = 7;
#50;
end
endmodule
| 6.572711 |
module NotGate (
a,
b
);
output b;
input a;
nand (b, a, a);
endmodule
| 7.369983 |
module AndGate (
a,
b,
c
);
output c;
input a, b;
wire x;
nand (x, a, b);
nand (c, x, x);
endmodule
| 7.746256 |
module OrGate (
a,
b,
c
);
output c;
input a, b;
wire x, y;
nand (x, a, a);
nand (y, b, b);
nand (c, x, y);
endmodule
| 6.50457 |
module XorGate (
a,
b,
c
);
output c;
input a, b;
wire a_, b_, x, y;
NotGate Na (
a,
a_
);
NotGate Nb (
b,
b_
);
AndGate A1 (
a,
b_,
x
);
AndGate A2 (
a_,
b,
y
);
OrGate O (
x,
y,
c
);
endmodule
| 7.413558 |
module Nand3 (
a,
b,
c,
o
);
output o;
input a, b, c;
wire x, y;
AndGate A (
a,
b,
x
);
AndGate B (
x,
c,
y
);
NotGate C (
y,
o
);
endmodule
| 6.937178 |
module DeCoder2 (
e,
i,
o
);
output [1:0] o;
input e, i;
wire i_;
NotGate Ne (
i,
i_
);
AndGate O1 (
i_,
e,
o[0]
);
AndGate O2 (
i,
e,
o[1]
);
endmodule
| 7.055917 |
module DeCoder4 (
e,
i,
o
);
output [3:0] o;
input [1:0] i;
input e;
wire [1:0] t;
DeCoder2 D1 (
e,
i[1],
t[1:0]
);
DeCoder2 D2 (
t[1],
i[0],
o[3:2]
);
DeCoder2 D3 (
t[0],
i[0],
o[1:0]
);
endmodule
| 7.437067 |
module DeCoder8 (
e,
i,
o
);
output [7:0] o;
input [2:0] i;
input e;
wire [1:0] t;
DeCoder2 D1 (
e,
i[2],
t[1:0]
);
DeCoder4 D2 (
t[0],
i[1:0],
o[3:0]
);
DeCoder4 D3 (
t[1],
i[1:0],
o[7:4]
);
endmodule
| 7.495716 |
module DLatch (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, s, r, x, y;
AndGate S (
d,
d,
s
);
NotGate R (
d,
r
);
nand (x, c, s);
nand (y, c, r);
nand (q, q_, x);
nand (q_, q, y);
endmodule
| 6.957096 |
module DFlipFlopRE (
d,
c,
q,
q_
);
output q, q_;
input d, c;
wire c_, Q, Q_;
NotGate C_ (
c,
c_
);
DLatch D1 (
d,
c_,
Q,
Q_
);
DLatch D2 (
Q,
c,
q,
q_
);
endmodule
| 7.021098 |
module Reg16Bit (
DIn,
clk,
cs,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, cs, w, r;
BinaryCell B[15:0] (
DIn,
clk,
cs,
w,
r,
DOut
);
endmodule
| 8.10144 |
module Mux2x1 (
a,
b,
s,
c
);
output c;
input a, b, s;
wire x, y, z;
NotGate NG_1 (
s,
z
);
AndGate AG_1 (
a,
z,
x
);
AndGate AG_2 (
b,
s,
y
);
OrGate OG_1 (
x,
y,
c
);
endmodule
| 6.963017 |
module Mux4x1 (
i0,
i1,
i2,
i3,
s1,
s0,
o
);
output o;
input i0, i1, i2, i3;
input s1, s0;
wire x, y;
Mux2x1 M_1 (
i0,
i1,
s1,
x
);
Mux2x1 M_2 (
i2,
i3,
s1,
y
);
Mux2x1 M_3 (
x,
y,
s0,
o
);
endmodule
| 8.038083 |
module Mux4x1_16 (
i0,
i1,
i2,
i3,
s,
o
);
output [15:0] o;
input [15:0] i0, i1, i2, i3;
input [1:0] s;
Mux4x1 M[15:0] (
i0,
i1,
i2,
i3,
s[0],
s[1],
o
);
endmodule
| 7.425005 |
module Mux8x1 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s0,
s1,
s2,
o
);
output o;
input i1, i2, i3, i4, i5, i6, i7, i8;
input s2, s1, s0;
wire x, y;
Mux4x1 M1 (
i1,
i2,
i3,
i4,
s0,
s1,
x
);
Mux4x1 M2 (
i5,
i6,
i7,
i8,
s0,
s1,
y
);
Mux2x1 M3 (
x,
y,
s2,
o
);
endmodule
| 7.627269 |
module Mux8x1_16 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s,
o
);
output [15:0] o;
input [15:0] i1, i2, i3, i4, i5, i6, i7, i8;
input [2:0] s;
Mux8x1 M[15:0] (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
s[0],
s[1],
s[2],
o
);
endmodule
| 8.13978 |
module RAM8 (
e,
DIn,
clk,
addr,
w,
r,
DOut
);
output [15:0] DOut;
input [15:0] DIn;
input clk, w, r, e;
input [2:0] addr;
wire [7:0] cs;
wire [15:0] o1, o2, o3, o4, o5, o6, o7, o8;
DeCoder8 Addr (
e,
addr,
cs
);
Reg16Bit r1 (
DIn,
clk,
cs[0],
w,
r,
o1
);
Reg16Bit r2 (
DIn,
clk,
cs[1],
w,
r,
o2
);
Reg16Bit r3 (
DIn,
clk,
cs[2],
w,
r,
o3
);
Reg16Bit r4 (
DIn,
clk,
cs[3],
w,
r,
o4
);
Reg16Bit r5 (
DIn,
clk,
cs[4],
w,
r,
o5
);
Reg16Bit r6 (
DIn,
clk,
cs[5],
w,
r,
o6
);
Reg16Bit r7 (
DIn,
clk,
cs[6],
w,
r,
o7
);
Reg16Bit r8 (
DIn,
clk,
cs[7],
w,
r,
o8
);
Mux8x1_16 M (
o1,
o2,
o3,
o4,
o5,
o6,
o7,
o8,
addr,
DOut
);
endmodule
| 6.996489 |
module Mod2d (
X,
Y,
Out,
clk
);
output [15:0] Out;
input [15:0] X, Y;
input clk;
reg [15:0] temp, diff;
initial begin
temp = 0;
diff = 0;
end
always @(X or Y) begin
diff = X - Y;
#5 temp = X;
end
Mod2b M (
temp,
diff,
Out,
clk
);
endmodule
| 6.740863 |
module AjustareExponent (
exponent,
valoarea2,
exponent_out
);
input wire [4:0] exponent;
input wire valoarea2;
output reg [4:0] exponent_out;
always @(exponent | valoarea2) begin
if (valoarea2 == 1'b1) begin
exponent_out = exponent + 1'b1;
end else begin
exponent_out = exponent;
end
end
endmodule
| 6.94024 |
module ajusta_bits (
switches,
ajusta_out
);
input [6:0] switches;
output reg [31:0] ajusta_out;
always @(*) begin
ajusta_out = {{28{1'b0}}, switches[3:0]};
end
endmodule
| 7.460056 |
module akiko (
input clk,
input cs,
input rd,
input wr,
input [ 5:1] addr,
input [15:0] din,
output reg [15:0] dout
);
wire c2p_sel = (addr[5:2] == 'b1110);
reg [7:0] buff[32];
reg [3:0] rptr = 0, wptr = 0;
always @(posedge clk) begin
if ((wr | rd) & cs & c2p_sel) begin
if (wr) begin
rptr <= 0;
wptr <= wptr + 1'd1;
{buff[{wptr, 1'b0}], buff[{wptr, 1'b1}]} <= din;
end else begin
wptr <= 0;
rptr <= rptr + 1'd1;
end
end
end
always begin
reg [4:0] i;
dout = 0;
if (cs) begin
if (addr == 0) dout = 16'hC0CA;
if (addr == 1) dout = 16'hCAFE;
if (c2p_sel) for (i = 0; i < 16; i = i + 1'd1) dout[i] = buff[{rptr[0], ~i[3:0]}][rptr[3:1]];
end
end
endmodule
| 7.74058 |
module al422_bam_oe_processor(
in_nrst, in_clk, module_start, bit_counter, module_is_busy, led_oe
);
parameter OE_PRESCALER;
parameter OE_PREDELAY;
parameter OE_POSTDELAY;
parameter BITS_IN_COUNTER;
input wire in_nrst;
input wire in_clk;
input wire module_start;
input wire [BITS_IN_COUNTER - 1:0] bit_counter;
output wire module_is_busy;
output wire led_oe;
parameter PRESCALER_COUNTER_WIDTH = (OE_PRESCALER > 1) ? $clog2(OE_PRESCALER) : 1;
parameter PREDELAY_COUNTER_WIDTH = $clog2(OE_PREDELAY);
parameter POSTDELAY_COUNTER_WIDTH = $clog2(OE_POSTDELAY);
parameter tmpmax1 = (PRESCALER_COUNTER_WIDTH > PREDELAY_COUNTER_WIDTH) ? PRESCALER_COUNTER_WIDTH : PREDELAY_COUNTER_WIDTH;
parameter FS_COUNTER_WIDTH = (tmpmax1 > POSTDELAY_COUNTER_WIDTH) ? tmpmax1 : POSTDELAY_COUNTER_WIDTH;
parameter MAIN_COUNTER_WIDTH = (1 << BITS_IN_COUNTER);
reg [MAIN_COUNTER_WIDTH - 1:0] main_counter;
reg [FS_COUNTER_WIDTH - 1:0] fs_counter;
reg [1:0] phase_cntr;
wire phase_idle, phase_pre, phase_main;
assign phase_idle = (phase_cntr == 2'h0);
assign phase_pre = (phase_cntr == 2'h1);
assign phase_main = (phase_cntr == 2'h2);
assign led_oe = phase_main;
assign module_is_busy = !phase_idle;
wire local_reset;
assign local_reset = !module_is_busy & module_start;
wire fs_counter_is_zero;
assign fs_counter_is_zero = (fs_counter == 0);
wire main_counter_is_one;
assign main_counter_is_one = (main_counter == 1);
always @(posedge in_clk or negedge in_nrst)
if (~in_nrst)
phase_cntr <= 2'b0;
else
if (local_reset)
phase_cntr <= 2'b1;
else
if ((fs_counter_is_zero & !phase_idle & (main_counter_is_one | !phase_main)))
phase_cntr <= phase_cntr + 1'b1;
parameter predelay_preload = OE_PREDELAY - 1'b1;
parameter prescaler_preload = OE_PRESCALER - 1'b1;
parameter postdelay_preload = OE_POSTDELAY - 1'b1;
always @(posedge in_clk or negedge in_nrst)
if (~in_nrst)
fs_counter <= predelay_preload[FS_COUNTER_WIDTH - 1:0];
else
if (local_reset)
fs_counter <= predelay_preload[FS_COUNTER_WIDTH - 1:0];
else
if (fs_counter_is_zero)
if (phase_pre | (phase_main & !main_counter_is_one))
fs_counter <= prescaler_preload[FS_COUNTER_WIDTH - 1:0];
else
fs_counter <= postdelay_preload[FS_COUNTER_WIDTH - 1:0];
else
if (module_is_busy & !phase_idle)
fs_counter <= fs_counter - 1'b1;
wire [MAIN_COUNTER_WIDTH - 1:0] oe_duration;
assign oe_duration = (1'b1 << bit_counter);
always @(posedge in_clk or negedge in_nrst)
if (~in_nrst)
main_counter <= 8'hFF;
else
if (local_reset)
main_counter <= oe_duration;
else
if (module_is_busy & phase_main & fs_counter_is_zero)
main_counter <= main_counter - 1'b1;
endmodule
| 7.629186 |
module ALARM_STATE_MACHINE (
input wire reset_n,
clk,
//set_time,
alarm,
//Toggle_switch,
hours_set,
mins_set,
//output reg [4 : 0] hour,
// reg [5 : 0] mins,
output reg hours,
mins
);
parameter first = 2'b00, second = 2'b01, third = 2'b10, four = 2'b11;
reg [1 : 0] state;
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
hours = 0;
mins = 0;
state = 0;
end else if (alarm) begin
case (state)
first: begin
case ({
hours_set, mins_set
})
first: begin
state = first;
hours = 0;
mins = 0;
end
second: begin
state = second;
hours = 0;
mins = 0;
end
third: begin
state = third;
hours = 0;
mins = 0;
end
four: begin
state = first;
hours = 0;
mins = 0;
end
endcase
end
second: begin
case ({
hours_set, mins_set
})
first: begin
state = first;
hours = 0;
mins = 1;
end
second: begin
state = second;
hours = 0;
mins = 0;
end
third: begin
state = third;
hours = 0;
mins = 1;
end
four: begin
state = first;
hours = 0;
mins = 0;
end
endcase
end
third: begin
case ({
hours_set, mins_set
})
first: begin
state = first;
hours = 1;
mins = 0;
end
second: begin
state = second;
hours = 1;
mins = 0;
end
third: begin
state = third;
hours = 0;
mins = 0;
end
four: begin
state = first;
hours = 0;
mins = 0;
end
endcase
end
endcase
end else begin
hours = 0;
mins = 0;
state = 0;
end
end
endmodule
| 7.587361 |
module Alarma (
clk,
rx,
Hora_actual,
sensores,
Activada,
Sonando,
accion,
dutty,
done,
an,
sseg,
init
);
input clk;
input rx;
input [23:0] Hora_actual;
input sensores;
output Activada;
output Sonando;
output [1:0] accion;
output [15:0] dutty;
output done;
output [7:0] an;
output [6:0] sseg;
output reg init = 1'b1;
wire [47:0] Ascii;
wire [7:0] dato;
wire DONE;
wire [23:0] Hora_alarma;
reg [27:0] counter;
reg [6:0] counter2;
reg clk_s;
Uart_rx(
clk, rx, init, dato
);
Obtener_Ha ob (
clk,
dato,
init,
Ascii,
DONE
);
Ascii2BCD_reloj re (
clk,
Ascii,
Hora_alarma,
init,
DONE,
done
);
Alarma_FSM(
clk, Hora_actual, Hora_alarma, sensores, Activada, Sonando, accion, dutty
); Display_a(
clk, an, Hora_alarma, sseg
);
always @(posedge clk) begin //clk con periodo de 1 segundo
counter = counter + 1;
if (counter < 50_000_000) begin
if (counter < 25_000_000) begin
clk_s = 1'b1;
end else begin
clk_s = 1'b0;
end
end else begin
counter = 0;
end
end
always @(posedge clk_s) begin
counter2 = counter2 + 1;
if (done) begin
init = 0;
end
if (!done && !init) begin
init = 1;
end
if (counter2 == 20) begin
init = 0;
counter2 = 0;
end
end
endmodule
| 7.218662 |
module AlarmaAnimal (
input m,
input ta,
input tb,
output alarma
);
assign alarma = (m & ta) | tb;
endmodule
| 7.155666 |
module Alarma_FSM (
clk,
Hora_actual,
Hora_alarma,
sensores,
Activada,
Sonando,
accion,
dutty
);
input clk;
input [23:0] Hora_actual;
input [23:0] Hora_alarma;
input sensores;
output reg Activada;
output reg Sonando;
output reg [1:0] accion;
output reg [15:0] dutty;
reg [1:0] status;
reg act;
reg des;
reg son;
reg [27:0] counter;
reg clk_s;
reg [11:0] counter2;
parameter DESACTIVADA = 2'b00, ACTIVADA = 2'b01, SONANDO = 2'b10;
always @(posedge clk) begin //maquina de estados
case (status)
DESACTIVADA: begin
act = 1'b0;
des = 1'b1;
son = 1'b0;
if (Hora_alarma[3:0] == 4'b0001) status = ACTIVADA;
end
ACTIVADA: begin
act = 1'b1;
des = 1'b0;
son = 1'b0;
if (Hora_alarma[3:0] == 4'b0000) status = DESACTIVADA;
if (Hora_actual == Hora_alarma) status = SONANDO;
end
SONANDO: begin
act = 1'b0;
des = 1'b0;
son = 1'b1;
if (sensores) status = ACTIVADA;
end
endcase
end
always @(posedge clk) begin //clk con periodo de 1 segundo
counter = counter + 1;
if (counter < 50_000_000) begin
if (counter < 25_000_000) begin
clk_s = 1'b1;
end else begin
clk_s = 1'b0;
end
end else begin
counter = 0;
end
end
always @(posedge clk_s) begin //estado activada
if (act) begin
Activada = 1'b1;
end else begin
Activada = 1'b0;
end
end
always @(posedge clk_s) begin //estado sonando
if (son) begin
Sonando = 1'b1;
counter2 = counter2 + 1;
accion = 2'b00;
case (counter2)
12'd1: begin
dutty = 16'd2000;
accion = 2'b10;
end
12'd10: begin
dutty = 16'd6000;
accion = 2'b10;
end
12'd20: begin
dutty = 16'd12000;
accion = 2'b10;
end
12'd30: begin
dutty = 16'd18000;
accion = 2'b10;
end
12'd40: begin
dutty = 16'd24000;
accion = 2'b10;
end
12'd50: begin
dutty = 16'd36000;
accion = 2'b10;
end
12'd60: begin
dutty = 16'd40000;
accion = 2'b10;
end
12'd70: begin
dutty = 16'd50000;
accion = 2'b10;
end
endcase
end else begin
Sonando = 1'b0;
counter2 = 0;
dutty = 2'b00;
accion = 2'b00;
end
end
endmodule
| 6.617418 |
module alarmBuzz (
uclock,
msClock,
tobuzzer,
buzzer
);
input msClock;
input uclock;
input tobuzzer;
output reg buzzer;
reg [9:0] waitTime;
reg [3:0] state;
reg [3:0] nextState;
// Begin with all Registers at 0
initial begin
waitTime = 0;
state = 0;
nextState = 0;
end
// Assign state to next state at posedge of userclock
always @(posedge uclock) begin
state <= nextState; //FSM
end
// Controlling the waitTime Counter
always @(posedge msClock) begin
if (waitTime >= 1020) waitTime <= 0; // Reset at the Limit
if (tobuzzer) waitTime <= waitTime + 1; // WaitTime Counter
else waitTime <= 0; // Keep at Zero
end
// State machine to determine the nextstate
always @(msClock) begin
if (state == 0 && tobuzzer) begin
nextState <= 1;
buzzer <= 0;
end
if (state == 1 && tobuzzer)
if (waitTime < 80 || waitTime >= 1020) begin
nextState <= 1;
buzzer <= 1;
end else nextState <= 2; // Buzz 1
if (state == 2 && tobuzzer)
if (waitTime < 140) begin
nextState <= 2;
buzzer <= 0;
end else nextState <= 3;
if (state == 3 && tobuzzer)
if (waitTime < 220) begin
nextState <= 3;
buzzer <= 1;
end else nextState <= 4; // Buzz 2
if (state == 4 && tobuzzer)
if (waitTime < 280) begin
nextState <= 4;
buzzer <= 0;
end else nextState <= 5;
if (state == 5 && tobuzzer)
if (waitTime < 360) begin
nextState <= 5;
buzzer <= 1;
end else nextState <= 6; // Buzz 3
if (state == 6 && tobuzzer)
if (waitTime < 420) begin
nextState <= 6;
buzzer <= 0;
end else nextState <= 7;
if (state == 7 && tobuzzer)
if (waitTime < 500) begin
nextState <= 7;
buzzer <= 1;
end else nextState <= 8; // Buzz 4
if (state == 8 && tobuzzer)
if (waitTime < 1020) begin
nextState <= 8;
buzzer <= 0;
end else nextState <= 1; // Long Wait
if (!tobuzzer) begin
buzzer <= 0;
nextState <= 0;
end // If tobuzzer is off do not buzz
end
endmodule
| 7.413856 |
module DigitalClock_12hrFormat (
input clk,
input center,
input right,
input left,
input up,
input down,
input M_00,
input M_01,
input M_02,
input M_03,
input M_10,
input M_11,
input M_12,
input H_00,
input H_01,
input H_02,
input H_10,
input H_11,
output [6:0] seg,
output [3:0] an,
output AMPM_indicator_led,
output clock_mode_indicator_led,
output Alarm1,
output Alarm2,
output Alarm3,
output Alarm4,
output Alarm5,
input stop
);
reg [31:0] counter = 0;
parameter max_count = 25_000_000;
reg [3:0] H_in1;
reg [3:0] H_in0;
reg [3:0] M_in1;
reg [3:0] M_in0;
always @(*) begin
H_in1 = H_10 + H_11 * 2;
H_in0 = H_00 + H_01 * 2 + H_02 * 4;
M_in1 = M_10 + M_11 * 2 + M_12 * 4;
M_in0 = M_00 + M_01 * 2 + M_02 * 4 + M_03 * 8;
end
reg [5:0] hrs, min, sec = 0;
reg [3:0] min_ones, min_tens, hrs_ones, hrs_tens = 0;
reg toggle = 0; //0 min 1 hour
reg x = 0;
assign Alarm1 = x;
assign Alarm2 = x;
assign Alarm3 = x;
assign Alarm4 = x;
assign Alarm5 = x;
always @(*) begin
if (stop) x <= 0;
if ({H_in1, H_in0, M_in1, M_in0} == {hrs_tens, hrs_ones, min_tens, min_ones}) begin
if (stop == 0) x <= 1;
else x <= 0;
end
end
reg pm = 0;
assign AMPM_indicator_led = pm;
reg clock_mode = 0;
assign clock_mode_indicator_led = clock_mode;
seven_segment SSM (
clk,
min_ones,
min_tens,
hrs_ones,
hrs_tens,
seg,
an
);
parameter display_time = 1'b0;
parameter set_time = 1'b1;
reg current_mode = set_time;
always @(posedge clk) begin
case (current_mode)
display_time: begin
if (center) begin
clock_mode <= 0;
current_mode <= set_time;
counter <= 0;
toggle <= 0;
sec <= 0;
end
if (counter < max_count) begin
counter <= counter + 1;
end else begin
counter <= 0;
sec <= sec + 1;
end
end
set_time: begin
if (center) begin
clock_mode <= 1;
current_mode <= display_time;
end
if (counter < (12_500_000)) begin
counter <= counter + 1;
end else begin
counter <= 0;
case (toggle)
1'b0: begin
if (up) begin
min <= min + 1;
end
if (down) begin
if (min > 0) begin
min <= min - 1;
end else if (hrs > 1) begin
hrs <= hrs - 1;
min <= 59;
end else if (hrs == 1) begin
hrs <= 12;
min <= 59;
end
end
if (left || right) begin
toggle <= 1;
end
end
1'b1: begin
if (up) begin
hrs <= hrs + 1;
end
if (down) begin
if (hrs > 1) begin
hrs <= hrs - 1;
end else if (hrs == 1) begin
hrs <= 12;
end
end
if (right || left) begin
toggle <= 0;
end
end
endcase
end
end
endcase
if (sec >= 60) begin
sec <= 0;
min <= min + 1;
end
if (min >= 60) begin
min <= 0;
hrs <= hrs + 1;
end
if (hrs >= 24) begin
hrs <= 0;
end else begin
min_ones <= min % 10;
min_tens <= min / 10;
if (hrs < 12) begin
if (hrs == 0) begin
hrs_ones <= 2;
hrs_tens <= 1;
end else begin
hrs_ones <= hrs % 10;
hrs_tens <= hrs / 10;
end
pm <= 0;
end else begin
if (hrs == 12) begin
hrs_ones <= 2;
hrs_tens <= 1;
end else begin
hrs_ones <= (hrs - 12) % 10;
hrs_tens <= (hrs - 12) / 10;
end
pm <= 1;
end
end
end
endmodule
| 7.319542 |
module alarming (
alarmSwitch,
alarmStatus,
alarmRing,
buzzer,
uclock,
a0,
a1,
a2,
a3,
t0,
t1,
t2,
t3,
switch,
switch2
);
input alarmSwitch, uclock, switch, switch2;
input [3:0] a0, a1, a2, a3, t0, t1, t2, t3;
output reg alarmStatus, alarmRing, buzzer;
reg almstate;
initial begin
almstate = 0;
end
always @(posedge uclock) begin
alarmStatus = almstate;
end
// Convert Switch to Button
always @(posedge alarmSwitch) if (!switch && switch2) almstate = ~almstate;
always @(posedge uclock) begin
if (almstate) begin
if (a0 == t0 && a1 == t1 && a2 == t2 && a3 == t3) begin
alarmRing = 1;
buzzer = 1;
end else begin
alarmRing = 0;
buzzer = 0;
end
end else begin
alarmRing = 0;
buzzer = 0;
end
end
endmodule
| 6.536672 |
module AlarmRun (
input [5:0] hour_set,
input [5:0] minute_set,
input [5:0] second_set, //็จไบ่ฎพๅฎ้น้็ๅ้
input [5:0] hour,
input [5:0] minute,
input [5:0] second,
input CLK_50,
input alarm_set,
input one_second_clk, // ๆฏ็ง็ๆถ้ๅจๆ
output [3:0] LEDR,
output reg LEDAlarm, // ๆต่ฏ็จ็LED้น้่พๅบ
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK, // ้ณ้ขๅฎ้ชๆ้่ฆ็ๅคง้ๅผ่
output FPGA_I2C_SCLK,
inout FPGA_I2C_SDAT
);
reg [5:0] alarm_hour;
reg [5:0] alarm_minute;
reg [5:0] alarm_second;
reg [2:0] count;
initial begin
LEDAlarm = 1'b0;
alarm_hour = 6'b0;
alarm_minute = 6'b0;
alarm_second = 6'b0;
count = 3'b0;
end
always @(posedge one_second_clk) begin
if (alarm_set == 1'b1) // ๆญคๆถๆฏ้่ฆ่ฎพๅฎ้น้็ๆถๅ
begin
alarm_hour = hour_set;
alarm_minute = minute_set;
alarm_second = second_set;
end
else if (hour == alarm_hour && minute == alarm_minute && second == alarm_second)
// ๆญคๆถๆฏ้น้่ฎพๅฎ็ๆถ้ด
begin
count = 3'b1; // countๅ ไธ่ฟ่ก่ฎกๆฐ
LEDAlarm = 1'b1;
end else if (count != 3'b0) begin
count = count + 1;
//LEDAlarm <= 1'b1;
end else if (count == 1'b0) begin
LEDAlarm = 1'b0;
end
end
sound_sample Sound (
.CLOCK_50(CLK_50),
.LEDR(LEDR),
.AUD_BCLK(AUD_BCLK),
.AUD_DACDAT(AUD_DACDAT),
.AUD_DACLRCK(AUD_DACLRCK),
.AUD_XCK(AUD_XCK),
.FPGA_I2C_SCLK(FPGA_I2C_SCLK),
.FPGA_I2C_SDAT(FPGA_I2C_SDAT),
.en_count(count)
);
endmodule
| 8.750687 |
module alarm_clk(
Clock_1sec, Reset, LoadTime, LoadAlm, AlarmEnable,
Set_AM_PM, Alarm_AM_PM_In,
SetSecs, SetMins, AlarmMinsIn, SetHours, AlarmHoursIn,
AM_PM, Alarm, Secs_C, Mins_C, Hours_C);
input Clock_1sec, Reset, LoadTime, LoadAlm, Set_AM_PM, Alartm_AM_PM_In, AlarmEnable
input[5:0] SecSecs, SetMins, AlarmMinsIn;
input[3:0] SetHours, AlarmHoursIn;
output reg AM_PM, Alarm;
output reg[5:0] Secs_C, Mins_C;
output reg[3:0] Hours_C;
always @(posedge Clock_1sec or negedge Reset) begin
if(!Reset) begin
/*์ด๊ธฐํ*/
AM_PM <= 1;
Alarm <= 0;
Secs_C <= 0;
Mins_C <= 0;
Hours_C <= 0;
end
else begin
/*ํ์์ ์ํ: ์๊ฐ ์ ์ง, ์๋ ๋์ ์ ์ง*/
Secs_C <= Secs_C;
Alarm <= Alarm;
if(LoadTime) begin //์๊ฐ setting
AM_PM <= Set_AM_PM;
Secs_C <= SetSecs;
Mins_C <= SetMins;
Hours_C <= SetHours;
end
else if(!LoadTime) begin //์๊ณ ๋์
Secs_C <= Secs_C + 1;
if(Secs_C == 59) begin
Mins_C <= Mins_C + 1; //59์ด์์ 1๋ถ์ผ๋ก
if(Mins_C == 59) begin
Hours_C <= Hours_C + 1; //59๋ถ์์ 1์๊ฐ์ผ๋ก
/*59์ด์ด๊ณ 59๋ถ์ธ ์ํ์์ 11์์ผ ๋(11:59:59)*/
if(Hours_C==11) AM_PM <= ~AM_PM; //์ค์ /์คํ ๋ฐ๊พธ๊ธฐ
if(Hours_C==13) Hours_C <= 1; //12์๊ฐ ๋์ด๊ฐ๋ฉด ๋ค์ 1์๋ถํฐ
Mins_C <= 0; //๋ค์ 0๋ถ๋ถํฐ
end
Secs_C <= 0; //๋ค์ 0์ด๋ถํฐ
end
end
/*์๋์ด ์ธ๋ฆด ์๊ฐ์ testbench์์ settingํ๋ค.*/
if(AlarmEnable) begin //์๋ ๋์
if(!LoadAlm) begin
if((AM_PM==Alarm_AM_PM_In) && (Hours_C==AlarmHoursIn)) begin
/*์๋ ์๊ฐ์ด ๋ 0์ด ์์ ๋ถํฐ ์๋์ด ์ธ๋ฆฐ๋ค.(1)*/
if((Mins_C==(AlarmMinsIn-1)) && (Secs_C==59)) begin
Alarm <= 1;
end
/*์๋ ์๊ฐ์ด ๋๊ณ 59์ด ์์ ๊น์ง๋ง ์๋์ด ์ธ๋ฆฐ๋ค.(1->0)*/
if((Mins_C==AlarmMinsIn) && (Secs_C==59)) begin
Alarm <= 0;
end
end
end
end
end
end
endmodule
| 7.201232 |
module alarm_clock_top (
input clock,
reset,
time_button,
alarm_button,
fast_watch,
input [3:0] key,
output [7:0] ms_hour,
ls_hour,
ms_minute,
ls_minute,
output alarm_sound
);
//Define the Interconnecting internal wires
wire reset_count, one_minute, one_second, load_new_c, show_current_time, show_a, load_new_a, shift;
wire [3:0] alarm_time_ms_hr, alarm_time_ls_hr, alarm_time_ms_min, alarm_time_ls_min,
current_time_ms_hr, current_time_ms_min, current_time_ls_hr, current_time_ls_min,
key_buffer_ls_min, key_buffer_ms_min, key_buffer_ls_hr, key_buffer_ms_hr;
// Instantiate the timing generator module
aclk_timegen timegen (
clock,
reset,
reset_count,
fast_watch,
one_minute,
one_second
);
// Instantiate the counter module
aclk_counter counter (
clock,
reset,
one_minute,
load_new_c,
key_buffer_ms_hr,
key_buffer_ms_min,
key_buffer_ls_hr,
key_buffer_ls_min,
current_time_ms_hr,
current_time_ms_min,
current_time_ls_hr,
current_time_ls_min
);
// Instantiate the alarm register module
aclk_areg alrm_reg (
load_new_a,
clock,
reset,
key_buffer_ms_hr,
key_buffer_ls_hr,
key_buffer_ms_min,
key_buffer_ls_min,
alarm_time_ms_hr,
alarm_time_ls_hr,
alarm_time_ms_min,
alarm_time_ls_min
);
// Instantiate the key register module
aclk_keyreg key_reg (
reset,
clock,
shift,
key,
key_buffer_ls_min,
key_buffer_ms_min,
key_buffer_ls_hr,
key_buffer_ms_hr
);
// Instantiate the FSM controller
aclk_controller fsm (
clock,
reset,
one_second,
alarm_button,
time_button,
key,
reset_count,
load_new_c,
show_current_time,
show_a,
load_new_a,
shift
);
// Instantiate the lcd_driver_4 module
aclk_lcd_display display (
alarm_time_ms_hr,
alarm_time_ls_hr,
alarm_time_ms_min,
alarm_time_ls_min,
current_time_ms_hr,
current_time_ls_hr,
current_time_ms_min,
current_time_ls_min,
key_buffer_ms_hr,
key_buffer_ls_hr,
key_buffer_ms_min,
key_buffer_ls_min,
show_a,
show_current_time,
ms_hour,
ls_hour,
ms_minute,
ls_minute, //done
alarm_sound
);
endmodule
| 7.307734 |
module alarm_fsm #(
parameter SIZE = 4
) (
input rst,
input sec_clk,
input enable,
input [SIZE-1:0] max,
output [SIZE-1:0] count,
output alarm
);
reg [SIZE-1:0] count_ff;
reg alarm_ff;
reg alarm_nxt;
assign count = count_ff;
assign alarm = alarm_ff;
always @(*) begin
if (rst) begin
alarm_nxt = 1'b0;
end else if (enable && (max == count)) begin
alarm_nxt = 1'b1;
end else alarm_nxt = alarm_ff;
end
always @(posedge sec_clk or posedge rst)
if (rst) begin
count_ff <= {SIZE{1'b0}};
alarm_ff <= 1'b0;
end else begin
count_ff <= count_ff + 1'b1;
alarm_ff <= alarm_nxt;
end
endmodule
| 7.131 |
module alarm_fsm_test ();
localparam SIZE = 4;
reg rst, enable, sec_clk;
reg [SIZE-1:0] max;
wire [SIZE-1:0] count;
wire alarm;
vlog_tb_utils vlog_tb_utils0 ();
initial begin
rst = 0;
enable = 0;
sec_clk = 0;
max = 4'b0;
end
always #5 sec_clk = !sec_clk;
initial begin
#15 rst = 1;
#5 rst = 0;
#20 max = 4'b0101;
#30 enable = 1;
#60 enable = 0;
#10 rst = 1;
#10 rst = 0;
#20 $finish;
end
alarm_fsm #(
.SIZE(SIZE)
) alarm_fsmi (
.rst(rst),
.sec_clk(sec_clk),
.enable(enable),
.max(max),
.count(count),
.alarm(alarm)
);
endmodule
| 7.131584 |
module alarm_len_conved (
enable,
sec_clk,
cur_sec,
tar_sec,
len_s,
off,
alarming
);
input enable, sec_clk, off;
input [16:0] cur_sec, tar_sec;
input [1:0] len_s;
reg [5:0] len;
output reg alarming = 0;
reg alarm_off = 0;
always @(posedge sec_clk) begin
case (len_s)
0: len = 15;
1: len = 30;
2: len = 45;
3: len = 60;
endcase
if (enable)
if (tar_sec - 1 <= cur_sec && cur_sec <= tar_sec + len - 1) begin
if (alarm_off == 0 && off == 1) alarm_off = 1;
if (alarm_off == 0) alarming = 1;
else alarming = 0;
end else begin
alarming = 0;
alarm_off = 0;
end
end
endmodule
| 6.906836 |
module alarm_register (
input [15:0] set_data,
input load_alarm,
clk,
reset,
output reg [15:0] alarm_data
);
always @(posedge clk, negedge reset) begin
if (!reset) alarm_data <= 0;
else if (load_alarm) alarm_data <= set_data;
else alarm_data <= 0;
end
endmodule
| 8.958344 |
module ALARM_SM (
input wire reset_n,
clk,
Toggle_switch,
RINGER1,
output reg SPEAKER_OUT
);
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
SPEAKER_OUT = 0;
end else begin
if (Toggle_switch & RINGER1) SPEAKER_OUT = 1;
else SPEAKER_OUT = 0;
end
end
endmodule
| 7.932963 |
module ALARM_SM_2 (
input wire reset_n,
clk,
Toggle_switch,
MATCH, // flag of alarm time equal to current time
output reg SPEAKER_OUT
);
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
SPEAKER_OUT = 0;
end else begin
if (Toggle_switch & MATCH) SPEAKER_OUT = 1;
else SPEAKER_OUT = 0;
end
end
endmodule
| 7.837466 |
module ALARM_STATE_MACHINE (
input wire reset_n,
clk,
alarm,
hours_set,
mins_set,
output reg hours,
mins
);
parameter IDLE = 2'b00, MINS_S = 2'b01, HOURS_S = 2'b10, BOTH = 2'b11;
reg [1 : 0] state;
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
hours = 0;
mins = 0;
state = 0;
end else if (alarm) begin
case (state)
IDLE: begin
case ({
hours_set, mins_set
})
IDLE: begin
state = IDLE;
hours = 0;
mins = 0;
end
MINS_S: begin
state = MINS_S;
hours = 0;
mins = 0;
end
HOURS_S: begin
state = HOURS_S;
hours = 0;
mins = 0;
end
BOTH: begin
state = IDLE;
hours = 0;
mins = 0;
end
endcase
end
MINS_S: begin
case ({
hours_set, mins_set
})
IDLE: begin
state = IDLE;
hours = 0;
mins = 1;
end
MINS_S: begin
state = MINS_S;
hours = 0;
mins = 0;
end
HOURS_S: begin
state = HOURS_S;
hours = 0;
mins = 1;
end
BOTH: begin
state = IDLE;
hours = 0;
mins = 0;
end
endcase
end
HOURS_S: begin
case ({
hours_set, mins_set
})
IDLE: begin
state = IDLE;
hours = 1;
mins = 0;
end
MINS_S: begin
state = MINS_S;
hours = 1;
mins = 0;
end
HOURS_S: begin
state = HOURS_S;
hours = 0;
mins = 0;
end
BOTH: begin
state = IDLE;
hours = 0;
mins = 0;
end
endcase
end
endcase
end else begin
hours = 0;
mins = 0;
state = 0;
end
end
endmodule
| 7.587361 |
module alarm_system (
input wire CLK,
RESET,
bt_inc,
bt_sel,
bt_mode,
uart_rx,
output wire uart_tx,
output wire [7:0] leds,
output wire [6:0] seg7s0,
seg7s1,
seg7m0,
seg7m1,
seg7h0,
seg7h1
);
system alarmSystem (
bt_inc,
bt_mode,
bt_sel,
CLK,
leds,
RESET,
seg7h0,
seg7h1,
seg7m0,
seg7m1,
seg7s0,
seg7s1,
uart_rx,
uart_tx
);
endmodule
| 6.899929 |
module: alarm
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alarm_tb;
// Inputs
reg N;
reg X;
reg W;
reg D;
reg G;
// Outputs
wire A;
integer i;
// Instantiate the Unit Under Test (UUT)
alarm uut (
.N(N),
.X(X),
.W(W),
.D(D),
.G(G),
.A(A)
);
initial
begin
for(i=0;i<32;i=i+1)
begin
{N,X,W,D,G}=i;
#10;
end
end
endmodule
| 7.187895 |
module ALARM_TIME_CONT (
RESETN,
CLK,
IN_TIME,
FLAG,
UP,
DOWN,
OUT_TIME
);
input RESETN, CLK;
input [16:0] IN_TIME;
input [2:0] FLAG;
input [2:0] UP, DOWN;
output wire [16:0] OUT_TIME;
/* FLAG */
parameter FLAG_ALARM_CONTROL_STATE = 3'b011;
/* CONTROL SELECTER LIST */
parameter CONT_NO = 3'b000,
CONT_HOUR = 3'b001,
CONT_MIN = 3'b010,
CONT_SEC = 3'b011,
CONT_MERIDIAN = 3'b100;
reg MERIDIAN;
reg [3:0] HOUR;
reg [5:0] MIN, SEC;
parameter AM = 8'b01000001, PM = 8'b01000010;
/* TIME FORMAT LIST */
parameter FORMAT_24 = 0, FORMAT_12 = 1;
always @(posedge CLK or negedge RESETN) begin
if (~RESETN) begin
HOUR = IN_TIME[15:12];
MIN = IN_TIME[11:6];
SEC = IN_TIME[5:0];
MERIDIAN = AM;
end else begin
if (FLAG == FLAG_ALARM_CONTROL_STATE)
// Up part
case (UP)
CONT_HOUR: begin
if (HOUR >= 23) HOUR = 0;
else HOUR = HOUR + 1;
end
CONT_MIN: begin
if (MIN >= 59) MIN = 0;
else MIN = MIN + 1;
end
CONT_SEC: begin
if (SEC >= 59) SEC = 0;
else SEC = SEC + 1;
end
CONT_MERIDIAN: begin
if (MERIDIAN == AM) MERIDIAN = PM;
else MERIDIAN = AM;
end
default: begin
HOUR = IN_TIME[15:12];
MIN = IN_TIME[11:6];
SEC = IN_TIME[5:0];
MERIDIAN = AM;
end
endcase
// DOWN part
case (DOWN)
CONT_HOUR: begin
if (HOUR <= 0) HOUR = 23;
else HOUR = HOUR - 1;
end
CONT_MIN: begin
if (MIN <= 0) MIN = 59;
else MIN = MIN - 1;
end
CONT_SEC: begin
if (SEC <= 0) SEC = 59;
else SEC = SEC - 1;
end
CONT_MERIDIAN: begin
if (MERIDIAN == AM) MERIDIAN = PM;
else MERIDIAN = AM;
end
default: begin
HOUR = IN_TIME[15:12];
MIN = IN_TIME[11:6];
SEC = IN_TIME[5:0];
MERIDIAN = AM;
end
endcase
end
end
assign OUT_TIME = {MERIDIAN, HOUR, MIN, SEC};
endmodule
| 7.592128 |
module alarm_tone #(
parameter CLK_FREQ = 12_000_000
) (
input clk,
output reg speaker
);
localparam divider0 = CLK_FREQ / 220 / 2;
reg [$clog2(divider0)-1:0] counter0;
always @(posedge clk) begin
if (!counter0) begin
counter0 <= divider0 - 1;
end else begin
counter0 <= counter0 - 1;
end
end
reg enable = 1;
reg [$clog2(CLK_FREQ) -1:0] sys_cycles;
wire tick = (CLK_FREQ / 2 - 1) == sys_cycles;
always @(posedge clk) begin
if (tick) sys_cycles <= 0;
else sys_cycles <= sys_cycles + 1;
enable <= enable ^ tick;
end
always @(posedge clk) begin
if (!counter0 & enable) speaker <= ~speaker;
end
endmodule
| 7.316437 |
module alarm_wrap (
clk,
rst,
btn,
speaker,
onehz,
seg_en,
seg_out
);
input clk, rst, btn;
output speaker, onehz;
output [7:0] seg_en, seg_out;
wire [16:0] cur_sec;
reg [16:0] tar_sec = 10;
reg [ 5:0] len = 60;
wire [3:0] h1, h2, m1, m2, s1, s2;
gene_1hz gen (
clk,
0,
onehz
);
time_goes_by sec_cnt (
cur_sec,
onehz,
rst
);
time_convert conv (
cur_sec,
h1,
h2,
m1,
m2,
s1,
s2
);
display disp (
clk,
4'h0,
4'h0,
h1,
h2,
m1,
m2,
s1,
s2,
8'b00111111,
seg_en,
seg_out
);
wire sound;
alarm al (
1,
onehz,
cur_sec,
tar_sec,
len,
btn,
sound
);
liangzhu so (
speaker,
clk,
sound
);
endmodule
| 6.728706 |
module alaw_coder #(
parameter DATA_IN_W = 15, // Data input width
parameter DATA_OUT_W = 8 // Data output width
) (
// System
input wire clk, // System clock
input wire rst, // System reset
// Input data
input wire [ DATA_IN_W-1:0] data_in, // Data input
input wire valid_in, // Data input is valid
// Output data
output reg [DATA_OUT_W-1:0] data_out, // Data output
output reg valid_out // Output data is valid
);
//-----------------------------------------------------------------------------
// Local parameters
//-----------------------------------------------------------------------------
localparam EXP_W = 3;
localparam MANT_W = DATA_OUT_W - EXP_W;
//-----------------------------------------------------------------------------
// Local variables
//-----------------------------------------------------------------------------
reg pre_valid_out;
reg [DATA_IN_W-1:0] data_shifter;
reg [ EXP_W-1:0] shift_cnt;
reg busy;
wire done;
//-----------------------------------------------------------------------------
// Coder
//-----------------------------------------------------------------------------
assign done = data_shifter[DATA_IN_W-1] || (shift_cnt == 0);
always @(posedge clk or posedge rst) begin
if (rst) busy <= 1'b0;
else if (!busy && valid_in && (!data_in[DATA_IN_W-1])) busy <= 1'b1;
else if (busy && done) busy <= 1'b0;
end
always @(posedge clk or posedge rst) begin
if (rst) data_shifter <= 0;
else if (busy && (shift_cnt > 1) && !done) data_shifter <= {data_shifter[DATA_IN_W-2:0], 1'b0};
else if (valid_in) data_shifter <= data_in;
end
always @(posedge clk or posedge rst) begin
if (rst) shift_cnt <= {EXP_W{1'b1}};
else if (busy && !done) shift_cnt <= shift_cnt - 1;
else if (pre_valid_out) shift_cnt <= {EXP_W{1'b1}};
end
always @(posedge clk or posedge rst) begin
if (rst) data_out <= 0;
else if (pre_valid_out) data_out <= {shift_cnt, data_shifter[DATA_IN_W-2-:MANT_W]};
end
//-----------------------------------------------------------------------------
// Output valid
//-----------------------------------------------------------------------------
always @(posedge clk or posedge rst) begin
if (rst) pre_valid_out <= 1'b0;
else if (busy && done) pre_valid_out <= 1'b1;
else if (valid_in && data_in[DATA_IN_W-1]) pre_valid_out <= 1'b1;
else pre_valid_out <= 1'b0;
end
always @(posedge clk or posedge rst) begin
if (rst) valid_out <= 1'b0;
else valid_out <= pre_valid_out;
end
endmodule
| 8.189844 |
module alaw_decoder (
input_alaw,
output_lin
);
input [7:0] input_alaw;
output [12:0] output_lin;
reg [11:0] output_unsigned;
reg [ 3:0] bits;
always @(input_alaw) begin
bits = input_alaw[3:0];
case (input_alaw[6:4])
3'b000: output_unsigned = {7'b000_0000, bits, 1'b1};
3'b001: output_unsigned = {7'b000_0001, bits, 1'b1};
3'b010: output_unsigned = {6'b00_0001, bits, 2'b10};
3'b011: output_unsigned = {5'b0_0001, bits, 3'b100};
3'b100: output_unsigned = {4'b0001, bits, 4'b1000};
3'b101: output_unsigned = {3'b001, bits, 5'b1_0000};
3'b110: output_unsigned = {2'b01, bits, 6'b10_0000};
3'b111: output_unsigned = {1'b1, bits, 7'b100_0000};
default: output_unsigned = {7'b000_0000, bits, 1'b1};
endcase
end
assign output_lin = {input_alaw[7], output_unsigned};
endmodule
| 7.191147 |
module ALC (
out,
sample,
multiply
);
output wire [15:0] out;
input [15:0] sample;
input [15:0] multiply;
wire [47:0] result;
wire [15:0] pos_sample;
assign pos_sample = sample[15] ? (~sample + 1'b1) : sample; // convert to positive if negative
assign result = pos_sample * multiply; // B0 * B16 scalar (single 16 by 16 bit multiply)
assign out = sample[15] ? ~result[31:16] + 16'b1 : result[31:16]; // or result >> 16
endmodule
| 7.271343 |
module alct_lfsr_rng (
clock,
ce,
reset,
lfsr
);
// Generic
// parameter LFSR_LENGTH = 56;
parameter LFSR_LENGTH = 49;
// Ports
input clock; // 40 Mhz clock
input ce; // Clock enable
input reset; // Restart series
output reg [LFSR_LENGTH-1:0] lfsr; // Random series
// LFSR Random Pattern Generator
// wire [LFSR_LENGTH-1:0] lfsr_seed = 56'h123456789ABCDE;
wire [LFSR_LENGTH-1:0] lfsr_seed = 49'h123456789ABCD;
// wire feedback = ~(lfsr[15] ^ lfsr[14] ^ lfsr[12] ^ lfsr[ 3]); // 16 bit version
// wire feedback = ~(lfsr[55] ^ lfsr[54] ^ lfsr[34] ^ lfsr[33]); // 56 bit version 2x28
wire feedback = ~(lfsr[48] ^ lfsr[39]); // 49 bit version
always @(posedge clock) begin
if (reset) lfsr <= lfsr_seed;
else if (ce) lfsr <= {lfsr[LFSR_LENGTH-2:0], feedback};
end
//----------------------------------------------------------------------------------------------------------------
endmodule
| 7.437358 |
module ALEGen (
input clk,
input rst_n,
output reg ALE
);
reg [2:0] cnt;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
ALE <= 1'b1;
cnt <= 3'b0;
end else begin
if (cnt == 1) begin
ALE <= ~ALE;
cnt <= cnt + 1;
end else begin
if (cnt == 5) begin
ALE <= ~ALE;
cnt <= 3'b0;
end else begin
cnt <= cnt + 1'b1;
end
end
end
end
endmodule
| 7.922969 |
module alejandro (
input [3:0] D,
output reg [7:0] SEG
);
always @(*) begin
case (D)
4'd0: SEG <= 8'b00010001;
4'd1: SEG <= 8'b11100011;
4'd2: SEG <= 8'b01100001;
4'd3: SEG <= 8'b10001111;
4'd4: SEG <= 8'b00010001;
4'd5: SEG <= 8'b00010011;
4'd6: SEG <= 8'b10000101;
4'd7: SEG <= 8'b01110011;
default: SEG <= 8'b11111111;
endcase
end
endmodule
| 6.817937 |
module alert_player (
input clk,
rst,
set,
output buzzer
);
parameter hz = 12'd440;
parameter length = 12'd400;
wire ms_clk, ms_edge;
clk_div #(100_000) ms_clk_inst (
clk,
rst,
ms_clk
);
edge_gen ms_edge_gen_inst (
clk,
ms_clk,
ms_edge
);
reg [11:0] cnt;
reg [11:0] play_hz;
reg playing;
buzzer_player player_inst (
clk,
play_hz,
buzzer
);
always @(posedge clk) begin
if (rst) begin
cnt <= 0;
play_hz <= 0;
playing <= 0;
end else if (set) begin
cnt <= 0;
play_hz <= hz;
playing <= 1;
end else if (playing && ms_edge) begin
if (cnt == length) begin
cnt <= 0;
play_hz <= 0;
playing <= 0;
end else begin
cnt <= cnt + 1;
end
end
end
endmodule
| 7.504681 |
module alex (
frequency_HZ,
ATTEN,
SPI_data,
PTT_out,
Tx_load_strobe,
Rx_load_strobe,
SPI_clock,
clock
);
input [31:0] frequency_HZ;
input [1:0] ATTEN;
input PTT_out;
output SPI_data;
output Tx_load_strobe;
output Rx_load_strobe;
output SPI_clock;
input clock;
wire [ 6:0] LPF;
wire [ 5:0] select_HPF;
wire [31:0] frequency_plus_IF; // add PowerSDR IF frequecy (9kHz) to current frequency
// The frequency sent by PowerSDR is the indicated frequency
// less the 9kHz IF. In order to select filters at the correct
// frequency we need to add the IF offset to the current frequency.
assign frequency_plus_IF = frequency_HZ + 32'd9000; // add 9kHz IF offset
// select the appropriate HPF and LPF based on frequency
LPF_select Alex_LPF_inst (
.frequency(frequency_plus_IF),
.LPF(LPF)
);
HPF_select Alex_HPF_inst (
.frequency(frequency_plus_IF),
.HPF(select_HPF)
);
// Alex Antenna relay selection
wire ANT1;
wire ANT2;
wire ANT3;
wire Rx_1_out;
wire Transverter;
wire Rx_2_in;
wire Rx_1_in;
wire [1:0] TX_relay;
wire [1:0] RX_relay;
wire Rout;
Alex_relays Alex_relays_inst (
.TX_relay(TX_relay),
.RX_relay(RX_relay),
.Rout(Rout),
.ANT1(ANT1),
.ANT2(ANT2),
.ANT3(ANT3),
.Rx_1_out(Rx_1_out),
.Rx_1_in(Rx_1_in),
.Rx_2_in(Rx_2_in),
.Transverter(Transverter)
);
// Alex SPI interface
wire _6m_preamp;
wire Tx_yellow_led = 1'b1; // indicate we have some SPI data
wire Rx_yellow_led = 1'b1; // ditto
wire Tx_red_led;
wire Rx_red_led;
wire TR_relay;
wire [15:0] Alex_Tx_data;
wire [15:0] Alex_Rx_data;
// assign attenuators
wire _10dB_atten = ATTEN[0];
wire _20dB_atten = ATTEN[1];
// define and concatinate the Tx data to send to Alex via SPI
assign Tx_red_led = PTT_out; // turn red led on when we Tx
assign TR_relay = PTT_out; // turn on TR relay when PTT active
assign Alex_Tx_data = {
LPF[6:4], Tx_red_led, TR_relay, ANT3, ANT2, ANT1, LPF[3:0], Tx_yellow_led, 3'b000
};
// define and concatinate the Rx data to send to Alex via SPI
assign Rx_red_led = PTT_out; // turn red led on when we Tx
// turn 6m preamp on if frequency > 50MHz
assign _6m_preamp = (frequency_plus_IF > 50000000) ? 1'b1 : 1'b0;
// if 6m preamp selected disconnect all filters
wire [5:0] HPF;
assign HPF = _6m_preamp ? 6'd0 : select_HPF;
// V3 Alex hardware
assign Alex_Rx_data = {
Rx_red_led,
_10dB_atten,
_20dB_atten,
HPF[5],
Rx_1_out,
Rx_1_in,
Rx_2_in,
Transverter,
1'b0,
HPF[4:2],
_6m_preamp,
HPF[1:0],
Rx_yellow_led
};
// concatinate Tx and Rx data and send to SPI interface. SPI interface only sends on a change of Alex_data.
// All data is sent in about 120uS.
wire [31:0] Alex_data;
assign Alex_data = {Alex_Tx_data[15:0], Alex_Rx_data[15:0]};
SPI Alex_SPI_Tx (
.Alex_data(Alex_data),
.SPI_data(SPI_data),
.SPI_clock(SPI_clock),
.Tx_load_strobe(Tx_load_strobe),
.Rx_load_strobe(Rx_load_strobe),
.spi_clock(clock)
);
endmodule
| 8.143994 |
module Alex_relays (
TX_relay,
RX_relay,
Rout,
ANT1,
ANT2,
ANT3,
Rx_1_out,
Rx_1_in,
Rx_2_in,
Transverter
);
input [1:0] TX_relay;
input [1:0] RX_relay;
input Rout;
output ANT1;
output ANT2;
output ANT3;
output Rx_1_out;
output Rx_1_in;
output Rx_2_in;
output Transverter;
assign Rx_1_out = Rout;
assign ANT1 = (TX_relay == 2'b00) ? 1'b1 : 1'b0; // select Tx antenna 1
assign ANT2 = (TX_relay == 2'b01) ? 1'b1 : 1'b0; // select Tx antenna 2
assign ANT3 = (TX_relay == 2'b10) ? 1'b1 : 1'b0; // select Tx antenna 3
assign Rx_1_in = (RX_relay == 2'b01) ? 1'b1 : 1'b0; // select Rx antenna 1
assign Rx_2_in = (RX_relay == 2'b10) ? 1'b1 : 1'b0; // select Rx antenna 2
assign Transverter = (RX_relay == 2'b11) ? 1'b1 : 1'b0; // select Transverter input
endmodule
| 6.771213 |
module Alfa_desc (
Tom,
notas1,
notas2,
notas3,
saida1,
saida2,
saida3,
saida4,
saida5,
saida6,
saida7
);
input wire Tom;
input wire notas1, notas2, notas3; //B, C e D
output reg saida1, saida2, saida3, saida4, saida5, saida6, saida7;
always @(*) begin
saida1 = Tom | (~notas1 & ~notas2 & ~notas3);
saida2 = (~Tom & ~notas2) | (~notas2 & ~notas3) | (~notas1 & ~notas2) | (~Tom & notas1 & ~notas3) | (Tom & ~notas1 & ~notas3);
saida3 = (~notas2 & ~notas3) | (Tom & notas3) | (notas1 & notas2 & notas3);
saida4 = (~Tom & ~notas1) | (~Tom & notas1 & notas3) | (notas1 & notas2 & ~notas3) | (~notas1 & ~notas2 & ~notas3);
saida5 = (~notas2 & ~notas3) | (~Tom & ~notas1 & notas2 & notas3) | (Tom & notas1 & notas2) | (notas1 & notas2 & ~notas3);
saida6 = (~Tom & ~notas2 & ~notas3) | (Tom & ~notas1) | (~Tom & ~notas1 & notas3) | (Tom & notas2 & ~notas3);
saida7 = (~notas1 & ~notas2 & ~notas3) | (notas1 & ~notas2 & notas3) | (~Tom & ~notas1 & notas2);
end
endmodule
| 6.747634 |
module spmv_PP #(
parameter PIPE_DEPTH = 5,
parameter URAM_DATA_W = 32,
parameter PAR_SIZE_W = 10,
parameter EDGE_W = 96
) (
input wire clk,
input wire rst,
input wire [ 1:0] control,
input wire [URAM_DATA_W-1:0] buffer_Din,
input wire buffer_Din_valid,
input wire [ EDGE_W-1:0] input_word,
input wire [ 0:0] input_valid,
output wire [URAM_DATA_W-1:0] buffer_Dout,
output wire [ PAR_SIZE_W-1:0] buffer_Dout_Addr,
output wire buffer_Dout_valid,
output wire [ 63:0] output_word,
output wire [ 0:0] output_valid,
output wire [ 0:0] par_active
);
reg [EDGE_W-1:0] input_word_reg;
reg [0:0] input_valid_reg;
always @(posedge clk) begin
if (rst) begin
input_word_reg <= 0;
input_valid_reg <= 0;
end else begin
input_word_reg <= input_word;
input_valid_reg <= input_valid;
end
end
spmv_scatter_pipe #(
.PIPE_DEPTH (PIPE_DEPTH),
.URAM_DATA_W(URAM_DATA_W)
) scatter_unit (
.clk(clk),
.rst(rst),
.edge_weight(input_word_reg[95:64]),
.src_attr(buffer_Dout),
.edge_dest(input_word_reg[63:32]),
.input_valid(input_valid_reg && buffer_Din_valid && control == 1),
.update_value(output_word[63:32]),
.update_dest(output_word[31:0]),
.output_valid(output_valid)
);
spmv_gather_pipe #(
.PIPE_DEPTH(PIPE_DEPTH),
.PAR_SIZE_W(PAR_SIZE_W)
) gather_unit (
.clk(clk),
.rst(rst),
.update_value(input_word_reg[63:32]),
.update_dest(input_word_reg[31:0]),
.dest_attr(buffer_Din),
.input_valid(input_valid_reg && buffer_Din_valid && control == 2),
.WData(buffer_Dout),
.WAddr(buffer_Dout_Addr),
.Wvalid(buffer_Dout_valid),
.par_active(par_active)
);
endmodule
| 6.633763 |
module spmv_gather_pipe #(
parameter PIPE_DEPTH = 3,
parameter PAR_SIZE_W = 18
) (
input wire clk,
input wire rst,
input wire [ 31:0] update_value,
input wire [ 31:0] update_dest,
input wire [ 63:0] dest_attr,
input wire [ 0:0] input_valid,
output wire [ 63:0] WData,
output wire [PAR_SIZE_W-1:0] WAddr,
output wire [ 0:0] Wvalid,
output wire [ 0:0] par_active
);
reg [ 0:0] valid_reg[PIPE_DEPTH-1:0];
reg [31:0] dest_reg [PIPE_DEPTH-1:0];
assign WAddr = dest_reg[PIPE_DEPTH-1][PAR_SIZE_W-1:0];
assign par_active = 1'b1;
reg [31:0] dest_attr_reg[PIPE_DEPTH-1:0];
integer i;
always @(posedge clk) begin
if (rst) begin
for (i = 0; i < PIPE_DEPTH; i = i + 1) begin
dest_reg[i] <= 0;
dest_attr_reg[i] <= 0;
end
end else begin
for (i = 1; i < PIPE_DEPTH; i = i + 1) begin
dest_reg[i] <= dest_reg[i-1];
dest_attr_reg[i] <= dest_attr_reg[i-1];
end
dest_reg[0] <= update_dest;
dest_attr_reg[0] <= dest_attr[63:32];
end
end
fp_add adder (
.aclk(clk),
.s_axis_a_tvalid(input_valid),
.s_axis_a_tdata(update_value),
.s_axis_b_tvalid(input_valid),
.s_axis_b_tdata(dest_attr[31:0]),
.m_axis_result_tvalid(Wvalid),
.m_axis_result_tready(1'b1),
.m_axis_result_tdata(WData[31:0])
);
assign WData[63:32] = dest_attr_reg[PIPE_DEPTH-1];
endmodule
| 8.017521 |
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