code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module alpha2_input_butterfly_47 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_48 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_49 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_5 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_50 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_51 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_52 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_53 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_54 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_55 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_56 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_57 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_58 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_59 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_6 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_60 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_61 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_62 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_63 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_64 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_7 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_8 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alpha2_input_butterfly_9 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Product_in0; // sfix11_En6
wire signed [11:0] Product_cast; // sfix12_En6
wire signed [10:0] Product_out1; // sfix11_En6
wire signed [11:0] Sum_add_cast; // sfix12_En6
wire signed [11:0] Sum_add_cast_1; // sfix12_En6
wire signed [11:0] Sum_add_temp; // sfix12_En6
wire signed [ 9:0] Sum_out1; // sfix10_En4
wire signed [11:0] Sum1_sub_cast; // sfix12_En6
wire signed [11:0] Sum1_sub_cast_1; // sfix12_En6
wire signed [11:0] Sum1_sub_temp; // sfix12_En6
wire signed [ 9:0] Sum1_out1; // sfix10_En4
assign Product_in0 = (Const_input == 1'b1 ? In2 : 11'sb00000000000);
assign Product_cast = {Product_in0[10], Product_in0};
assign Product_out1 = Product_cast[10:0];
assign Sum_add_cast = {In1[10], In1};
assign Sum_add_cast_1 = {Product_out1[10], Product_out1};
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = Sum_add_temp[11:2];
assign Out1 = Sum_out1;
assign Sum1_sub_cast = {In1[10], In1};
assign Sum1_sub_cast_1 = {Product_out1[10], Product_out1};
assign Sum1_sub_temp = Sum1_sub_cast - Sum1_sub_cast_1;
assign Sum1_out1 = Sum1_sub_temp[11:2];
assign Out2 = Sum1_out1;
endmodule
| 6.698209 |
module alphabet_decoder (
input [2:0] alphabet_order,
output reg [24:0] display_code
);
always @(*) begin
case (alphabet_order)
3'd0: display_code = 25'b01111_10001_10011_10000_01111; // "G"
3'd1: display_code = 25'b10001_11111_10001_01010_00100; // "A"
3'd2: display_code = 25'b10001_10001_10101_11011_10001; // "M"
3'd3: display_code = 25'b11111_10000_11100_10000_11111; // "E"
3'd4: display_code = 25'b01110_10001_10001_10001_01110; // "O"
3'd5: display_code = 25'b00100_01010_10001_10001_10001; // "V"
3'd6: display_code = 25'b10001_10001_11110_10001_11110; // "R"
endcase
end
endmodule
| 7.319748 |
module AlphaCPU (
input wire clk,
rst
);
wire W_regfile_wea;
wire [2:0] W_alu_sel;
wire [3:0] W_mem_wea;
wire W_wb_regsrc_sel;
wire W_ex_rt_sel;
wire W_write_src_sel;
wire [1:0] W_branch;
wire [1:0] W_j_branch;
wire W_imme_sign_extend;
wire W_jal_en;
wire [5:0] W_instr_op;
wire [5:0] W_instr_funct;
wire [1:0] W_shift;
DataPath datapath (
clk,
rst,
W_regfile_wea,
W_alu_sel,
W_mem_wea,
W_wb_regsrc_sel,
W_ex_rt_sel,
W_write_src_sel,
W_branch,
W_j_branch,
W_imme_sign_extend,
W_shift,
W_jal_en,
W_instr_op,
W_instr_funct
);
Controller controller (
W_instr_op,
W_instr_funct,
W_regfile_wea,
W_alu_sel,
W_mem_wea,
W_wb_regsrc_sel,
W_ex_rt_sel,
W_write_src_sel,
W_branch,
W_j_branch,
W_imme_sign_extend,
W_shift,
W_jal_en
);
endmodule
| 6.619408 |
module AlphaMissionCoreClocks_Cen (
input wire i_clk,
output wire clk_13p4_cen,
output wire clk_13p4,
output wire clk_13p4b_cen,
output wire clk_13p4b,
output wire clk_6p7_cen,
output wire clk_6p7b_cen,
output wire clk_3p35_cen,
output wire clk_3p35b_cen,
output wire clk_4_cen,
output wire clk_4b_cen
);
reg ck_stb1 = 1'b0;
reg ck_stb2 = 1'b0;
reg ck_stb3 = 1'b0;
reg ck_stb4 = 1'b0;
reg ck_stb5 = 1'b0;
reg ck_stb6 = 1'b0;
reg ck_stb7 = 1'b0;
reg ck_stb8 = 1'b0;
//--------- 13.4 MHz ---------
reg [3:0] counter1 = 4'h4; //16'hC000
reg clk_13p4_r = 0;
reg [3:0] counter2 = 4'hC; //16'h4000
reg clk_13p4b_r = 0;
//-------- 6.7 MHz ---------
reg [3:0] counter3 = 4'hE; //16'hE000
reg [3:0] counter4 = 4'h6; //16'h6000
//-------- 3.35 MHz---------
reg [3:0] counter5 = 4'hF; //16'hF000
reg [3:0] counter6 = 4'h7; //16'h7000
//---3---- 4 MHz ------------
reg [15:0] counter7 = 16'd63583;
reg [15:0] counter8 = 16'd30815;
//--------- 13.4 MHz ---------
always @(negedge i_clk) begin
{ck_stb1, counter1} <= counter1 + 4'h4; //13.4MHz
end
assign clk_13p4_cen = ck_stb1;
always @(posedge i_clk)
if (clk_13p4_cen || clk_13p4b_cen) begin
clk_13p4_r <= ~clk_13p4_r;
clk_13p4b_r <= ~clk_13p4b_r;
end
assign clk_13p4 = clk_13p4_r;
assign clk_13p4b = clk_13p4b_r;
always @(negedge i_clk) begin
{ck_stb2, counter2} <= counter2 + 4'h4; //13.4MHz 180degrees shifted
end
assign clk_13p4b_cen = ck_stb2;
//--------- 6.7 MHz ----------
always @(negedge i_clk) begin
{ck_stb3, counter3} <= counter3 + 4'h2; //6.7MHz
end
always @(negedge i_clk) begin
{ck_stb4, counter4} <= counter4 + 4'h2; //6.7MHz 180 degrees shifted
end
assign clk_6p7_cen = ck_stb3;
assign clk_6p7b_cen = ck_stb4;
//--------- 3.35 MHz ---------
always @(negedge i_clk) begin
{ck_stb5, counter5} <= counter5 + 4'h1; //3.35MHz
end
always @(negedge i_clk) begin
{ck_stb6, counter6} <= counter6 + 4'h1; //3.35MHz 180 degrees shifted
end
assign clk_3p35_cen = ck_stb5;
assign clk_3p35b_cen = ck_stb6;
//--------- 4 MHz ------------
always @(negedge i_clk) begin
{ck_stb7, counter7} <= counter7 + 16'd4891; //4MHz
end
always @(negedge i_clk) begin
{ck_stb8, counter8} <= counter8 + 16'd4891; //4MHz 180 degrees shifted
end
assign clk_4_cen = ck_stb7;
assign clk_4b_cen = ck_stb8;
endmodule
| 7.304941 |
module alpha_blend (
input sys_clk,
input i_h_sync,
input i_v_sync,
input i_de,
input [7 : 0] i_back_ground_0_8b,
input [7 : 0] i_back_ground_1_8b,
input [7 : 0] i_back_ground_2_8b,
input [7 : 0] i_alpha_8b,
input [7 : 0] i_front_ground_0_8b,
input [7 : 0] i_front_ground_1_8b,
input [7 : 0] i_front_ground_2_8b,
//output
output reg o_h_sync,
output reg o_v_sync,
output reg o_de,
output wire [7 : 0] o_data_0_8b,
output wire [7 : 0] o_data_1_8b,
output wire [7 : 0] o_data_2_8b,
output [11:0] o_x,
output [11:0] o_y
);
/*******************************************************************************/
reg [7 : 0] alpha_8b;
wire [7 : 0] alpha_n_8b;
reg [7 : 0] front_ground_0_8b_delay_1;
reg [7 : 0] front_ground_1_8b_delay_1;
reg [7 : 0] front_ground_2_8b_delay_1;
reg [7 : 0] back_ground_0_8b_delay_1;
reg [7 : 0] back_ground_1_8b_delay_1;
reg [7 : 0] back_ground_2_8b_delay_1;
reg [15:0] mult_front_ground_0_16b;
reg [15:0] mult_front_ground_1_16b;
reg [15:0] mult_front_ground_2_16b;
reg [15:0] mult_back_ground_0_16b;
reg [15:0] mult_back_ground_1_16b;
reg [15:0] mult_back_ground_2_16b;
reg [16 : 0] add_data_0_17b;
reg [16 : 0] add_data_1_17b;
reg [16 : 0] add_data_2_17b;
reg [8:0] data_0_tmp;
reg [8:0] data_1_tmp;
reg [8:0] data_2_tmp;
reg h_sync_delay_1;
reg h_sync_delay_2;
reg h_sync_delay_3;
reg v_sync_delay_1;
reg v_sync_delay_2;
reg v_sync_delay_3;
reg de_delay_1;
reg de_delay_2;
reg de_delay_3;
assign alpha_n_8b = ~alpha_8b;
/*******************************************************************************/
//LV1
always @(posedge sys_clk) begin
front_ground_0_8b_delay_1 <= i_front_ground_0_8b;
front_ground_1_8b_delay_1 <= i_front_ground_1_8b;
front_ground_2_8b_delay_1 <= i_front_ground_2_8b;
back_ground_0_8b_delay_1 <= i_back_ground_0_8b;
back_ground_1_8b_delay_1 <= i_back_ground_1_8b;
back_ground_2_8b_delay_1 <= i_back_ground_2_8b;
alpha_8b <= i_alpha_8b;
end
//LV2:mult
always @(posedge sys_clk) begin
mult_front_ground_0_16b <= front_ground_0_8b_delay_1 * alpha_8b;
mult_front_ground_1_16b <= front_ground_1_8b_delay_1 * alpha_8b;
mult_front_ground_2_16b <= front_ground_2_8b_delay_1 * alpha_8b;
mult_back_ground_0_16b <= back_ground_0_8b_delay_1 * alpha_n_8b;
mult_back_ground_1_16b <= back_ground_1_8b_delay_1 * alpha_n_8b;
mult_back_ground_2_16b <= back_ground_2_8b_delay_1 * alpha_n_8b;
end
//LV3:add
always @(posedge sys_clk) begin
add_data_0_17b <= {1'b0, mult_front_ground_0_16b} + {1'b0, mult_back_ground_0_16b};
add_data_1_17b <= {1'b0, mult_front_ground_1_16b} + {1'b0, mult_back_ground_1_16b};
add_data_2_17b <= {1'b0, mult_front_ground_2_16b} + {1'b0, mult_back_ground_2_16b};
end
always @(posedge sys_clk) begin
data_0_tmp <= add_data_0_17b[16:8] + {8'd0, {|add_data_0_17b[7:5]}};
data_1_tmp <= add_data_1_17b[16:8] + {8'd0, {|add_data_1_17b[7:5]}};
data_2_tmp <= add_data_2_17b[16:8] + {8'd0, {|add_data_2_17b[7:5]}};
end
assign o_data_0_8b = data_0_tmp[8] ? 8'hff : data_0_tmp[7 : 0];
assign o_data_1_8b = data_1_tmp[8] ? 8'hff : data_1_tmp[7 : 0];
assign o_data_2_8b = data_2_tmp[8] ? 8'hff : data_2_tmp[7 : 0];
/*******************************************************************************/
always @(posedge sys_clk) begin
h_sync_delay_1 <= i_h_sync;
h_sync_delay_2 <= h_sync_delay_1;
h_sync_delay_3 <= h_sync_delay_2;
o_h_sync <= h_sync_delay_3;
v_sync_delay_1 <= i_v_sync;
v_sync_delay_2 <= v_sync_delay_1;
v_sync_delay_3 <= v_sync_delay_2;
o_v_sync <= v_sync_delay_3;
de_delay_1 <= i_de;
de_delay_2 <= de_delay_1;
de_delay_3 <= de_delay_2;
o_de <= de_delay_3;
end
timing_gen_xy timing_gen_xy_m0 (
.rst_n(1'b1),
.clk(sys_clk),
.i_hs(h_sync_delay_2),
.i_vs(v_sync_delay_2),
.i_de(de_delay_2),
.i_data(),
.o_hs(),
.o_vs(),
.o_de(),
.o_data(),
.x(o_x),
.y(o_y)
);
endmodule
| 6.658663 |
module alpha_clkmgr (
input wire gclk, // signal from clock pin
output wire sys_clk, // buffered system clock output
output wire sys_rst_n // system reset output (async set, sync clear, active-low)
);
//
// Parameters
//
parameter CLK_OUT_MUL = 20.0;
parameter CLK_OUT_DIV = 20.0;
//
// Wrapper for Xilinx-specific MMCM (Mixed Mode Clock Manager) primitive.
//
wire gclk_int; // buffered input clock
wire mmcm_reset; // reset input
wire mmcm_locked; // output clock valid
wire gclk_missing; // input clock stopped
clkmgr_mmcm #(
.CLK_OUT_MUL(CLK_OUT_MUL), // 2..64
.CLK_OUT_DIV(CLK_OUT_DIV) // 1..128
) mmcm (
.clk_in (gclk),
.reset_in(mmcm_reset),
.gclk_out (gclk_int),
.gclk_missing_out(gclk_missing),
.clk_out (sys_clk),
.clk_valid_out(mmcm_locked)
);
//
// MMCM Reset Logic
//
/* MMCM should be reset on power-up and when the input clock is stopped.
* Note that MMCM requires active-high reset, so the shift register is
* preloaded with 1's and then gradually filled with 0's.
*/
reg [15:0] mmcm_rst_shreg = {16{1'b1}}; // 16-bit shift register
always @(posedge gclk_int or posedge gclk_missing)
//
if ((gclk_missing == 1'b1))
mmcm_rst_shreg <= {16{1'b1}};
else mmcm_rst_shreg <= {mmcm_rst_shreg[14:0], 1'b0};
assign mmcm_reset = mmcm_rst_shreg[15];
//
// System Reset Logic
//
/* System reset is asserted for 16 cycles whenever MMCM aquires lock. Note
* that system reset is active-low, so the shift register is preloaded with
* 0's and gradually filled with 1's.
*/
reg [15:0] sys_rst_shreg = {16{1'b0}}; // 16-bit shift register
always @(posedge sys_clk or posedge gclk_missing or negedge mmcm_locked)
//
if ((gclk_missing == 1'b1) || (mmcm_locked == 1'b0))
sys_rst_shreg <= {16{1'b0}};
else if (mmcm_locked == 1'b1) sys_rst_shreg <= {sys_rst_shreg[14:0], 1'b1};
assign sys_rst_n = sys_rst_shreg[15];
endmodule
| 7.611036 |
module board_regs (
// Clock and reset.
input wire clk,
input wire reset_n,
// Control.
input wire cs,
input wire we,
// Data ports.
input wire [ 7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// API addresses.
localparam ADDR_CORE_NAME0 = 8'h00;
localparam ADDR_CORE_NAME1 = 8'h01;
localparam ADDR_CORE_VERSION = 8'h02;
localparam ADDR_DUMMY_REG = 8'hFF; // general-purpose register
// Core ID constants.
localparam CORE_NAME0 = 32'h414c5048; // "ALPH"
localparam CORE_NAME1 = 32'h41202020; // "A "
localparam CORE_VERSION = 32'h302e3130; // "0.10"
//----------------------------------------------------------------
// Registers.
//----------------------------------------------------------------
reg [ 31:0] tmp_read_data;
reg write_error;
reg read_error;
// dummy register to check that you can actually write something
reg [ 31:0] reg_dummy;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire [31 : 0] core_name0 = CORE_NAME0;
wire [31 : 0] core_name1 = CORE_NAME1;
wire [31 : 0] core_version = CORE_VERSION;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign error = write_error | read_error;
//----------------------------------------------------------------
// storage registers for mapping memory to core interface
//----------------------------------------------------------------
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
reg_dummy <= {32{1'b0}};
end else if (cs && we) begin
write_error <= 0;
// write operations
case (address)
ADDR_DUMMY_REG: reg_dummy <= write_data;
default: write_error <= 1;
endcase
end
end
always @* begin
tmp_read_data = 32'h00000000;
read_error = 0;
if (cs && !we) begin
// read operations
case (address)
ADDR_CORE_NAME0: tmp_read_data = core_name0;
ADDR_CORE_NAME1: tmp_read_data = core_name1;
ADDR_CORE_VERSION: tmp_read_data = core_version;
ADDR_DUMMY_REG: tmp_read_data = reg_dummy;
default: read_error = 1;
endcase
end
end
endmodule
| 7.886152 |
module alram1x (
clk, //clock
rst,
rdo, //data from ram
ra, //read address
wdi, //data to ram
wa, //write address
we //write enable
);
// =============================================================================
// == Parameter declarations
// =============================================================================
parameter WID = 4; // 10-bit long data
parameter AWID = 2; // 2-bit long address (4 addresses)
parameter DEP = 1 << AWID; // DEP = 2**AWID
// ==========================================================================
// == Port Declarations
// ==========================================================================
input clk;
input rst;
output reg [WID-1:0] rdo;
input [AWID-1:0] ra;
input [WID-1:0] wdi;
input [AWID-1:0] wa;
input we;
// ==========================================================================
// == Signal Declarations
// ==========================================================================
// force M10K ram style
reg [WID-1:0] mem[DEP-1:0] /* synthesis ramstyle = "no_rw_check, M10K" */; // memory size
integer i;
// ==========================================================================
// == Architecture
// ==========================================================================
always @(posedge clk) begin
if (rst) begin
for (i = 0; i < DEP; i = i + 1) begin
mem[i] <= {WID{1'b0}};
end
end else if (we) begin
mem[wa] <= wdi;
end
rdo <= mem[ra]; // delays 1 clock cycle
end
endmodule
| 7.129739 |
module ALS (
input clk,
input MISO,
input rst,
output SCLK,
output CS,
output [7:0] led
);
parameter refresh_period = 75_000;
wire d_rdy;
wire [15:0] d;
reg rd;
reg [31:0] rd_count;
simpleSPI SPI1 (
.clk(clk),
.MISO(MISO),
.rd(rd),
.rst(rst),
.SCLK(SCLK),
.CS(CS),
.d_rdy(d_rdy),
.d(d)
);
assign led = d[12:5];
initial begin
rd = 0;
rd_count = 0;
end
always @(posedge SCLK) begin
if ((d_rdy == 1) && (rd == 1)) begin
rd <= 0;
end
// Read four times per second;
if (rd_count > refresh_period) begin
rd <= 1;
rd_count <= 0;
end else begin
rd_count <= rd_count + 1;
end
end
endmodule
| 7.124875 |
module normalize32( in, dist, out );
input [31:0] in;
output [4:0] dist;
output [31:0] out;
wire [3:1] reduce8s;
wire [4:0] dist;
wire [31:0] normTo8, out;
assign reduce8s[3] = ( in[31:24] != 0 );
assign reduce8s[2] = ( in[23:16] != 0 );
assign reduce8s[1] = ( in[15:8] != 0 );
assign dist[4] = ( reduce8s[3:2] == 0 );
assign dist[3] = ~ reduce8s[3] & ( reduce8s[2] | ~ reduce8s[1] );
assign normTo8 =
( reduce8s[3] ? in : 0 )
| ( ( reduce8s[3:2] == 2'b01 ) ? in<<8 : 0 )
| ( ( reduce8s == 3'b001 ) ? in<<16 : 0 )
| ( ( reduce8s == 3'b000 ) ? in<<24 : 0 );
assign dist[2] = ( normTo8[31:28] == 0 );
assign dist[1] =
( normTo8[31:30] == 0 )
& ( ( normTo8[29:28] != 0 ) || ( normTo8[27:26] == 0 ) );
assign dist[0] =
~ normTo8[31]
& ( normTo8[30]
| ( ~ normTo8[29]
& ( normTo8[28]
| ( ~ normTo8[27] & ( normTo8[26] | ~ normTo8[25] ) ) )
)
);
assign out =
( normTo8[31] ? normTo8 : 0 )
| ( ( normTo8[31:30] == 2'b01 ) ? normTo8<<1 : 0 )
| ( ( normTo8[31:29] == 3'b001 ) ? normTo8<<2 : 0 )
| ( ( normTo8[31:28] == 4'b0001 ) ? normTo8<<3 : 0 )
| ( ( normTo8[31:27] == 5'b00001 ) ? normTo8<<4 : 0 )
| ( ( normTo8[31:26] == 6'b000001 ) ? normTo8<<5 : 0 )
| ( ( normTo8[31:25] == 7'b0000001 ) ? normTo8<<6 : 0 )
| ( ( normTo8[31:25] == 7'b0000000 ) ? normTo8<<7 : 0 );
endmodule
| 6.784075 |
module ltd_counter (
// General signals
clk, // x1 mode = tx_clk
// x4 and x8 mode = refclk_out
// single width = 250 MHz
// double width mode = 125 MHz
reset_n, // IP reset
// Control
threshold, // Configurable: should remain static
reset_ltd_counter, // Resets counter: controlled by LTR LTD FSM
ltd_counter_done // Indicates when threshold delay has been reached.
// Remains asserted until reset_wait_counter is aserted
);
//********************************************************************************
// INCLUDE STATEMENTS
//********************************************************************************
//********************************************************************************
// I/O SIGNALS
//********************************************************************************
// General signals
input clk;
input reset_n;
// Control
input [15:0] threshold;
input reset_ltd_counter;
output ltd_counter_done;
// output
reg ltd_counter_done;
// Counter
reg [15:0] threshold_reg;
reg [15:0] counter;
//********************************************************************************
// ASSIGN STATEMENTS
//********************************************************************************
// Register threshold
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
threshold_reg <= 16'h0;
end else begin
threshold_reg <= threshold;
end
end
//Counter: reset value is offset by 2 due to FSM reaction time
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
counter <= 16'h0;
end else begin
if (reset_ltd_counter) counter <= 16'h0002;
else counter <= counter + 16'h0001;
end
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
ltd_counter_done <= 1'b0;
end else begin
if (threshold_reg == 16'h0000) ltd_counter_done <= 1'b1;
else if (threshold_reg == 16'h0001) ltd_counter_done <= 1'b1;
else if (reset_ltd_counter) ltd_counter_done <= 1'b0;
else if (counter == threshold_reg) ltd_counter_done <= 1'b1;
else ltd_counter_done <= ltd_counter_done;
end
end
endmodule
| 6.771525 |
module alta_ufm (
input i_ufm_set,
input i_program,
input i_erase,
input i_osc_ena,
input i_arclk,
input i_arshift,
input i_ardin,
input i_drdin,
input i_drclk,
input i_drshift,
input i_tdo_u,
output o_tdi_u,
output o_tms_u,
output o_tck_u,
output o_shift_u,
output o_update_u,
output o_runidle_u,
output o_rtp_busy,
output o_ufm_busy,
output o_osc,
output o_drdout,
output o_user1_valid,
output o_user0_valid,
);
endmodule
| 7.694658 |
module alta_pll (
input clkin,
input clkfb,
input pllen,
input resetn,
input pfden,
output clkout0,
output clkout1,
output lock,
);
parameter CLKIN_DIV = 6'b000000;
parameter CLKFB_DIV = 6'b000000;
parameter CLKOUT0_EN = 1'b0;
parameter CLKOUT1_EN = 1'b0;
parameter CLKOUT0_DIV = 6'b000000;
parameter CLKOUT1_DIV = 6'b000000;
parameter CLKOUT0_DEL = 6'b000000;
parameter CLKOUT1_DEL = 6'b000000;
parameter CLKOUT0_PHASE = 3'b000;
parameter CLKOUT1_PHASE = 3'b000;
parameter FEEDBACK_MODE = 1'b0;
parameter FEEDBACK_CLOCK = 1'b0;
endmodule
| 7.086106 |
module alta_pllx (
input clkin,
input clkfb,
input pllen,
input resetn,
input clkout0en,
input clkout1en,
input clkout2en,
input clkout3en,
output clkout0,
output clkout1,
output clkout2,
output clkout3,
output lock,
);
parameter CLKIN_DIV = 6'b000000;
parameter CLKFB_DIV = 6'b000000;
parameter CLKDIV0_EN = 1'b0;
parameter CLKDIV1_EN = 1'b0;
parameter CLKDIV2_EN = 1'b0;
parameter CLKDIV3_EN = 1'b0;
parameter CLKOUT0_DIV = 6'b000000;
parameter CLKOUT1_DIV = 6'b000000;
parameter CLKOUT2_DIV = 6'b000000;
parameter CLKOUT3_DIV = 6'b000000;
parameter CLKOUT0_DEL = 6'b000000;
parameter CLKOUT1_DEL = 6'b000000;
parameter CLKOUT2_DEL = 6'b000000;
parameter CLKOUT3_DEL = 6'b000000;
parameter CLKOUT0_PHASE = 3'b000;
parameter CLKOUT1_PHASE = 3'b000;
parameter CLKOUT2_PHASE = 3'b000;
parameter CLKOUT3_PHASE = 3'b000;
parameter FEEDBACK_MODE = 1'b0;
parameter FEEDBACK_CLOCK = 2'b00;
endmodule
| 7.145606 |
module alta_pllv (
input clkin,
input clkfb,
input pllen,
input resetn,
input clkout0en,
input clkout1en,
input clkout2en,
input clkout3en,
input clkout4en,
output clkout0,
output clkout1,
output clkout2,
output clkout3,
output clkout4,
output clkfbout,
output lock,
);
parameter CLKIN_DIV = 9'b000000000;
parameter CLKFB_DIV = 9'b000000000;
parameter CLKDIV0_EN = 1'b0;
parameter CLKDIV1_EN = 1'b0;
parameter CLKDIV2_EN = 1'b0;
parameter CLKDIV3_EN = 1'b0;
parameter CLKDIV4_EN = 1'b0;
parameter CLKOUT0_HIGH = 8'b00000000;
parameter CLKOUT0_LOW = 8'b00000000;
parameter CLKOUT0_TRIM = 1'b0;
parameter CLKOUT0_BYPASS = 1'b0;
parameter CLKOUT1_HIGH = 8'b00000000;
parameter CLKOUT1_LOW = 8'b00000000;
parameter CLKOUT1_TRIM = 1'b0;
parameter CLKOUT1_BYPASS = 1'b0;
parameter CLKOUT2_HIGH = 8'b00000000;
parameter CLKOUT2_LOW = 8'b00000000;
parameter CLKOUT2_TRIM = 1'b0;
parameter CLKOUT2_BYPASS = 1'b0;
parameter CLKOUT3_HIGH = 8'b00000000;
parameter CLKOUT3_LOW = 8'b00000000;
parameter CLKOUT3_TRIM = 1'b0;
parameter CLKOUT3_BYPASS = 1'b0;
parameter CLKOUT4_HIGH = 8'b00000000;
parameter CLKOUT4_LOW = 8'b00000000;
parameter CLKOUT4_TRIM = 1'b0;
parameter CLKOUT4_BYPASS = 1'b0;
parameter CLKOUT0_DEL = 8'b00000000;
parameter CLKOUT1_DEL = 8'b00000000;
parameter CLKOUT2_DEL = 8'b00000000;
parameter CLKOUT3_DEL = 8'b00000000;
parameter CLKOUT4_DEL = 8'b00000000;
parameter CLKOUT0_PHASE = 3'b000;
parameter CLKOUT1_PHASE = 3'b000;
parameter CLKOUT2_PHASE = 3'b000;
parameter CLKOUT3_PHASE = 3'b000;
parameter CLKOUT4_PHASE = 3'b000;
parameter CLKFB_DEL = 8'b00000000;
parameter CLKFB_PHASE = 3'b000;
parameter CLKFB_TRIM = 1'b0;
parameter FEEDBACK_MODE = 3'b000;
parameter FBDELAY_VAL = 3'b000;
parameter PLLOUTP_EN = 1'b0;
parameter PLLOUTN_EN = 1'b0;
parameter CLKOUT1_CASCADE = 1'b0;
parameter CLKOUT2_CASCADE = 1'b0;
parameter CLKOUT3_CASCADE = 1'b0;
parameter CLKOUT4_CASCADE = 1'b0;
parameter CP = 3'b000;
parameter RREF = 2'b00;
parameter RVI = 2'b00;
endmodule
| 7.257119 |
module alta_pllve (
input clkin,
input clkfb,
input pfden,
input resetn,
input [2:0] phasecounterselect,
input phaseupdown,
input phasestep,
input scanclk,
input scanclkena,
input scandata,
input configupdate,
output clkout0,
output clkout1,
output clkout2,
output clkout3,
output clkout4,
output clkfbout,
output lock,
output scandataout,
output scandone,
output phasedone,
);
parameter CLKIN_HIGH = 8'b00000000;
parameter CLKIN_LOW = 8'b00000000;
parameter CLKIN_TRIM = 1'b0;
parameter CLKIN_BYPASS = 1'b0;
parameter CLKFB_HIGH = 8'b00000000;
parameter CLKFB_LOW = 8'b00000000;
parameter CLKFB_TRIM = 1'b0;
parameter CLKFB_BYPASS = 1'b0;
parameter CLKDIV0_EN = 1'b0;
parameter CLKDIV1_EN = 1'b0;
parameter CLKDIV2_EN = 1'b0;
parameter CLKDIV3_EN = 1'b0;
parameter CLKDIV4_EN = 1'b0;
parameter CLKOUT0_HIGH = 8'b00000000;
parameter CLKOUT0_LOW = 8'b00000000;
parameter CLKOUT0_TRIM = 1'b0;
parameter CLKOUT0_BYPASS = 1'b0;
parameter CLKOUT1_HIGH = 8'b00000000;
parameter CLKOUT1_LOW = 8'b00000000;
parameter CLKOUT1_TRIM = 1'b0;
parameter CLKOUT1_BYPASS = 1'b0;
parameter CLKOUT2_HIGH = 8'b00000000;
parameter CLKOUT2_LOW = 8'b00000000;
parameter CLKOUT2_TRIM = 1'b0;
parameter CLKOUT2_BYPASS = 1'b0;
parameter CLKOUT3_HIGH = 8'b00000000;
parameter CLKOUT3_LOW = 8'b00000000;
parameter CLKOUT3_TRIM = 1'b0;
parameter CLKOUT3_BYPASS = 1'b0;
parameter CLKOUT4_HIGH = 8'b00000000;
parameter CLKOUT4_LOW = 8'b00000000;
parameter CLKOUT4_TRIM = 1'b0;
parameter CLKOUT4_BYPASS = 1'b0;
parameter CLKOUT0_DEL = 8'b00000000;
parameter CLKOUT1_DEL = 8'b00000000;
parameter CLKOUT2_DEL = 8'b00000000;
parameter CLKOUT3_DEL = 8'b00000000;
parameter CLKOUT4_DEL = 8'b00000000;
parameter CLKOUT0_PHASE = 3'b000;
parameter CLKOUT1_PHASE = 3'b000;
parameter CLKOUT2_PHASE = 3'b000;
parameter CLKOUT3_PHASE = 3'b000;
parameter CLKOUT4_PHASE = 3'b000;
parameter CLKFB_DEL = 8'b00000000;
parameter CLKFB_PHASE = 3'b000;
parameter FEEDBACK_MODE = 3'b000;
parameter FBDELAY_VAL = 3'b000;
parameter PLLOUTP_EN = 1'b0;
parameter PLLOUTN_EN = 1'b0;
parameter CLKOUT1_CASCADE = 1'b0;
parameter CLKOUT2_CASCADE = 1'b0;
parameter CLKOUT3_CASCADE = 1'b0;
parameter CLKOUT4_CASCADE = 1'b0;
parameter VCO_POST_DIV = 1'b0;
parameter REG_CTRL = 2'b00;
parameter CP = 3'b000;
parameter RREF = 2'b00;
parameter RVI = 2'b00;
endmodule
| 7.608924 |
module alta_mult (
input [8:0] DataInA0,
input [8:0] DataInA1,
input [8:0] DataInB0,
input [8:0] DataInb0,
input SignA,
input SignB,
input Clk,
input ClkEn,
input AsyncReset,
output [17:0] DataOut0,
output [17:0] DataOut1,
);
parameter MULT_MODE = 1'b0;
parameter PORTA_INREG0 = 1'b0;
parameter PORTA_INREG1 = 1'b0;
parameter PORTB_INREG0 = 1'b0;
parameter PORTB_INREG1 = 1'b0;
parameter SIGNA_REG = 1'b0;
parameter SIGNB_REG = 1'b0;
parameter OUTREG0 = 1'b0;
parameter OUTREG1 = 1'b0;
parameter ClkCFG = 2'b00;
endmodule
| 6.514713 |
module alta_i2c (
input Clk,
input Rst,
input Strobe,
input WrRdn,
input [7:0] Address,
input [7:0] DataIn,
input Scli,
input Sdai,
output Ack,
output Irq,
output Wakeup,
output Sclo,
output Sdao,
output [7:0] DataOut,
);
parameter SLOT_ID = 4'b0000;
parameter ClkCFG = 2'b00;
endmodule
| 8.182431 |
module alta_spi (
input Clk,
input Rst,
input Strobe,
input WrRdn,
input [7:0] Address,
input [7:0] DataIn,
input Mi,
input Si,
input Scki,
input Csi,
output Ack,
output Irq,
output Wakeup,
output [7:0] DataOut,
output So,
output Soe,
output Mo,
output Moe,
output Scko,
output Sckoe,
output [3:0] Cso,
output [3:0] Csoe,
);
parameter SLOT_ID = 4'b0000;
parameter ClkCFG = 2'b00;
endmodule
| 6.884698 |
module alta_irda (
input ir_clk,
input ir_reset,
input cal_en,
input pu_ivref,
input pu_pga,
input pu_dac,
input tia_reset,
input vip,
input vin,
output irx_data,
output cal_ready,
output [7:0] dac_cal_reg,
);
parameter CFG_IRIP_EN = 1'b0;
parameter CLK_SEL_SYS = 1'b0;
parameter CLK_DIV_CMP_SYS = 3'b0;
parameter CLK_DIV_SYS = 3'b0;
parameter PU_HYSTER_SYS = 1'b0;
parameter REG_BYPASS_SYS = 1'b0;
parameter OUTPUT_SEL_SYS = 1'b0;
parameter CAL_READY_REG_SYS = 1'b0;
parameter CAL_READY_DR_SYS = 1'b0;
parameter CAL_TIME_SYS = 2'b0;
parameter CAL_DELAY_SYS = 2'b0;
parameter CAL_SPEED_SYS = 2'b0;
parameter DC_ACC_GAIN_SYS = 3'b0;
parameter BYPASS_DC_CALC_SYS = 1'b0;
parameter DC_TIME_SEL_SYS = 3'b0;
parameter REG_VBIT_SYS = 2'b0;
parameter RX_CAL_BIT_SYS = 8'b0;
parameter RX_CAL_BIT_DR_SYS = 1'b0;
parameter RX_DC_POLARITY_SYS = 1'b0;
parameter RX_CAL_POLARITY_SYS = 1'b0;
parameter DC_GAIN_SYS = 5'b0;
parameter DAC_GAIN_SYS = 2'b0;
parameter DAC_RANGE_SYS = 2'b0;
parameter PGA_CAP_BIT_SYS = 4'b0;
parameter PGA_CAP_EN_SYS = 1'b0;
parameter PGA_CAL_MODE_SYS = 1'b0;
parameter PGA_GAIN2_SYS = 2'b0;
parameter PGA_GAIN_SYS = 3'b0;
parameter DIFF_EN_SYS = 1'b0;
parameter TIA_GAIN_SYS = 2'b0;
parameter BG_SEL_SYS = 1'b0;
endmodule
| 6.503688 |
module alta_io (
input datain,
input oe,
output combout,
input padio,
);
parameter PRG_DELAYB = 1'b0;
parameter PRG_DELAYB_P = 1'b0;
parameter PRG_DELAYB_N = 1'b0;
parameter RX_SEL = 1'b0;
parameter RX_SEL_P = 1'b0;
parameter RX_SEL_N = 1'b0;
parameter PDCNTL = 2'b00;
parameter PDCNTL_P = 2'b00;
parameter PDCNTL_N = 2'b00;
parameter NDCNTL = 2'b00;
parameter NDCNTL_P = 2'b00;
parameter NDCNTL_N = 2'b00;
parameter PRG_SLR = 1'b0;
parameter PRG_SLR_P = 1'b0;
parameter PRG_SLR_N = 1'b0;
parameter CFG_KEEP = 2'b00;
parameter CFG_KEEP_N = 2'b00;
parameter CFG_KEEP_P = 2'b00;
parameter PU = 4'b0000;
parameter LVDS_RSDS_IREF = 12'b000000000000;
parameter CFG_LVDS_RSDS_EN = 1'b0;
endmodule
| 6.637447 |
module alta_dio (
input datain,
input datainh,
input oe,
output combout,
output regout,
input outclk,
input outclkena,
input inclk,
input inclkena,
input areset,
input sreset,
input padio,
);
parameter IN_ASYNC_MODE = 1'b0;
parameter IN_SYNC_MODE = 1'b0;
parameter IN_POWERUP = 1'b0;
parameter IN_ASYNC_DISABLE = 1'b0;
parameter IN_SYNC_DISABLE = 1'b0;
parameter OUT_REG_MODE = 1'b0;
parameter OUT_ASYNC_MODE = 1'b0;
parameter OUT_SYNC_MODE = 1'b0;
parameter OUT_POWERUP = 1'b0;
parameter OUT_CLKEN_DISABLE = 1'b0;
parameter OUT_ASYNC_DISABLE = 1'b0;
parameter OUT_SYNC_DISABLE = 1'b0;
parameter OUT_DDIO = 1'b0;
parameter OE_REG_MODE = 1'b0;
parameter OE_ASYNC_MODE = 1'b0;
parameter OE_SYNC_MODE = 1'b0;
parameter OE_POWERUP = 1'b0;
parameter OE_CLKEN_DISABLE = 1'b0;
parameter OE_ASYNC_DISABLE = 1'b0;
parameter OE_SYNC_DISABLE = 1'b0;
parameter OE_DDIO = 1'b0;
parameter inclkCFG = 2'b00;
parameter outclkCFG = 2'b00;
parameter CFG_TRI_INPUT = 1'b0;
parameter CFG_PULL_UP = 1'b0;
parameter CFG_OPEN_DRAIN = 1'b0;
parameter CFG_ROCT_CAL_EN = 1'b0;
parameter CFG_PDRV = 7'b0000000;
parameter CFG_NDRV = 7'b0000000;
parameter CFG_KEEP = 2'b00;
parameter CFG_LVDS_OUT_EN = 1'b0;
parameter CFG_LVDS_SEL_CUA = 3'b000;
parameter CFG_LVDS_IREF = 10'b0000000000;
parameter CFG_LVDS_IN_EN = 1'b0;
parameter CFG_SSTL_OUT_EN = 1'b0;
parameter CFG_SSTL_INPUT_EN = 1'b0;
parameter CFG_SSTL_SEL_CUA = 3'b000;
parameter CFG_OSCDIV = 2'b00;
parameter CFG_ROCTUSR = 1'b0;
parameter CFG_SEL_CUA = 1'b0;
parameter CFG_ROCT_EN = 1'b0;
parameter DPCLK_DELAY = 4'b0000;
parameter OUT_DELAY = 1'b0;
parameter IN_DATA_DELAY = 3'b000;
parameter IN_REG_DELAY = 3'b000;
endmodule
| 6.509055 |
module alta_indel (
input in,
output out,
);
endmodule
| 6.652631 |
module alta_slice (
input A,
input B,
input C,
input D,
output LutOut,
output Q,
input Cin,
output Cout,
input SyncReset,
input SyncLoad,
input Clk,
input AsyncReset,
input Qin,
input ShiftData,
);
parameter ClkMux = 2'b00;
parameter AsyncResetMux = 2'b00;
parameter SyncResetMux = 2'b0;
parameter SyncLoadMux = 2'b0;
parameter modeMux = 1'b0;
parameter FeedbackMux = 1'b0;
parameter ShiftMux = 1'b0;
parameter BypassEn = 1'b0;
parameter CarryEnb = 1'b0;
endmodule
| 7.398493 |
module alta_sram (
input [3:0] RAddr,
input [3:0] WAddr,
input [3:0] Din,
input WClk,
input WEna,
output [3:0] Dout,
);
parameter INIT_VAL = 64'h0;
endmodule
| 6.902908 |
module alta_asyncctrl (
input Din,
output Dout,
);
parameter AsyncCtrlMux = 2'b00;
endmodule
| 7.0483 |
module alta_io_gclk (
input inclk,
output outclk,
);
endmodule
| 6.587431 |
module alta_ufm_gddd (
input in,
output out,
);
endmodule
| 6.9667 |
module alta_clk_delay_ctrl ();
endmodule
| 6.922885 |
module alta_mac_out ();
endmodule
| 7.456496 |
module alta_mac_mult ();
endmodule
| 6.684394 |
module alta_ram_block ();
endmodule
| 8.129447 |
module alta_crcblock ();
endmodule
| 7.591494 |
module alta_jtag (
input tdouser,
output tmsutap,
output tckutap,
output tdiutap,
output shiftuser,
output clkdruser,
output updateuser,
output runidleuser,
output usr1user,
);
endmodule
| 6.911715 |
module alta_oct (
input clkusr,
input rstnusr,
output octdone,
output octdoneuser,
output rupcompout,
output rdncompout,
output rupoctcalnout,
output rdnoctcalnout,
);
parameter OCT_EN = 1'b0;
parameter OCT_CLKDIV = 2'b00;
parameter OCT_USR = 1'b0;
endmodule
| 7.44494 |
module altair_tb ();
reg clk = 0;
reg reset;
reg rx = 1'b1;
wire tx;
altair machine (
.clk(clk),
.reset(reset),
.rx(rx),
.tx(tx)
);
always #(5) clk <= !clk;
initial begin
$dumpfile("altair_tb.vcd");
$dumpvars(0, altair_tb);
reset = 1;
#20 reset = 0;
#2200000 $finish;
end
endmodule
| 6.512504 |
module alta_asyncctrl (
Din,
Dout
);
parameter AsyncCtrlMux = 2'b10;
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_asyncctrl";
input Din;
output Dout;
endmodule
| 7.0483 |
module alta_slice (
A,
B,
C,
D,
Cin,
Qin,
Clk,
AsyncReset,
SyncReset,
ShiftData,
SyncLoad,
LutOut,
Cout,
Q
);
// The following 10 bits are actually in LB, will be propagated to each slice by packer for software
// purpose only. 00: gnd, 01: vcc, 10: signal, 11: !signal
parameter ClkMux = 2'b10;
parameter AsyncResetMux = 2'b10;
parameter SyncResetMux = 2'b10;
parameter SyncLoadMux = 2'b10;
// These control bits are within each slice
parameter mode = "logic";
parameter modeMux = 1'b0; // Duplicat of mode
parameter FeedbackMux = 1'b0;
parameter ShiftMux = 1'b0;
parameter BypassEn = 1'b0;
parameter CarryEnb = 1'b0;
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_slice";
parameter mask = 16'hFFFF;
input A, B, C, D, Cin, Qin;
input Clk, AsyncReset, SyncReset, ShiftData, SyncLoad;
output Cout, LutOut, Q;
endmodule
| 7.398493 |
module alta_ufm_gddd (
in,
out
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_ufm_gddd";
input in;
output out;
endmodule
| 6.9667 |
module alta_io_gclk (
inclk,
outclk
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_io_gclk";
parameter clock_type = "global clock";
parameter ena_register_mode = "none";
input inclk;
output outclk;
endmodule
| 6.587431 |
module alta_ufm (
i_ufm_set,
i_program,
i_erase,
i_osc_ena,
i_arclk,
i_arshift,
i_ardin,
i_drdin,
i_drclk,
i_drshift,
i_tdo_u,
o_tdi_u,
o_tms_u,
o_tck_u,
o_shift_u,
o_update_u,
o_runidle_u,
o_rtp_busy,
o_ufm_busy,
o_osc,
o_drdout,
o_user1_valid,
o_user0_valid
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_ufm";
input i_ufm_set; //1: ufm is instantiated by user 0:not
input i_program; //Signal that initiates a program sequence
input i_erase; //Signal that initiates an erase sequence
input i_osc_ena ;//This signal turns on the internal oscillator in the UFM block, and is optional but required when the OSC output is used.
input i_arclk; //Clock input that controls the address register
input i_arshift ;//Signal that determines whether to shift the address register or increment it on an ARCLK edge.
input i_ardin; //Serial input to the address register
input i_drdin ;//Serial input to the data register. It is used to enter a data word when writing to the UFM.
input i_drclk ;//Clock input that controls the data register
input i_drshift ;//Signal that determines whether to shift the data register or load it on a DRCLK edge.
input i_tdo_u;
output o_tdi_u;
output o_tms_u;
output o_tck_u;
output o_shift_u;
output o_update_u;
output o_runidle_u;
output o_rtp_busy ;//This output signal is optional and only needed if the real-time ISP feature is used.
output o_ufm_busy ;//Signal that indicates when the memory is BUSY performing a PROGRAM or ERASE instruction.
output o_osc; //Output of the internal oscillator.
output o_drdout; //Serial output of the data register.
output o_user1_valid;
output o_user0_valid;
endmodule
| 7.694658 |
module alta_sram (
WEna,
WClk,
Din,
WAddr,
RAddr,
Dout,
devpor,
devclrn,
devoe
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_sram";
parameter INIT_VAL = 64'h0;
input WEna, WClk;
input [3:0] Din;
input [3:0] WAddr;
input [3:0] RAddr;
output [3:0] Dout;
input devclrn, devpor, devoe;
endmodule
| 6.902908 |
module alta_wram (
WEna,
WClk,
Din,
WAddr,
RAddr,
Dout,
devpor,
devclrn,
devoe
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_wram";
parameter INIT_VAL = 128'h0;
input WEna, WClk;
input [7:0] Din;
input [3:0] WAddr;
input [3:0] RAddr;
output [7:0] Dout;
input devclrn, devpor, devoe;
endmodule
| 6.749375 |
module alta_pll (
clkin,
clkfb,
pllen,
resetn,
pfden,
clkout0,
clkout1,
lock,
devpor,
devclrn,
devoe
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_pll";
parameter CLKIN_DIV = 6'h1;
parameter CLKFB_DIV = 6'h1;
parameter CLKOUT0_DIV = 6'h3f;
parameter CLKOUT1_DIV = 6'h3f;
parameter CLKOUT0_DEL = 6'h0;
parameter CLKOUT1_DEL = 6'h0;
parameter CLKOUT0_PHASE = 3'h0;
parameter CLKOUT1_PHASE = 3'h0;
parameter FEEDBACK_MODE = 1'b0;
parameter FEEDBACK_CLOCK = 1'b0;
parameter CLKOUT0_EN = 1'h1;
parameter CLKOUT1_EN = 1'h1;
parameter CLKIN_FREQ = 10;
parameter CLKFB_FREQ = 10;
parameter CLKOUT0_FREQ = 10;
parameter CLKOUT1_FREQ = 10;
input clkin, clkfb;
input pllen, resetn, pfden;
output clkout0, clkout1;
output lock;
input devclrn, devpor, devoe;
endmodule
| 7.086106 |
module alta_pllx (
clkin,
clkfb,
pllen,
resetn,
clkout0en,
clkout1en,
clkout2en,
clkout3en,
clkout0,
clkout1,
clkout2,
clkout3,
lock,
devpor,
devclrn,
devoe
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_pllx";
parameter CLKIN_DIV = 6'h1;
parameter CLKFB_DIV = 6'h1;
parameter CLKDIV0_EN = 1'b0;
parameter CLKDIV1_EN = 1'b0;
parameter CLKDIV2_EN = 1'b0;
parameter CLKDIV3_EN = 1'b0;
parameter CLKOUT0_DIV = 6'h3f;
parameter CLKOUT1_DIV = 6'h3f;
parameter CLKOUT2_DIV = 6'h3f;
parameter CLKOUT3_DIV = 6'h3f;
parameter CLKOUT0_DEL = 6'h0;
parameter CLKOUT1_DEL = 6'h0;
parameter CLKOUT2_DEL = 6'h0;
parameter CLKOUT3_DEL = 6'h0;
parameter CLKOUT0_PHASE = 3'h0;
parameter CLKOUT1_PHASE = 3'h0;
parameter CLKOUT2_PHASE = 3'h0;
parameter CLKOUT3_PHASE = 3'h0;
parameter FEEDBACK_MODE = 1'b0;
parameter FEEDBACK_CLOCK = 2'b0;
parameter CLKIN_FREQ = 10;
parameter CLKFB_FREQ = 10;
parameter CLKOUT0_FREQ = 10;
parameter CLKOUT1_FREQ = 10;
parameter CLKOUT2_FREQ = 10;
parameter CLKOUT3_FREQ = 10;
input clkin, clkfb;
input pllen, resetn;
input clkout0en, clkout1en, clkout2en, clkout3en;
output clkout0, clkout1, clkout2, clkout3;
output lock;
input devclrn, devpor, devoe;
endmodule
| 7.145606 |
module alta_mac_mult (
dataa,
datab,
signa,
signb,
clk,
aclr,
ena,
dataout,
devclrn,
devpor
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_mac_mult";
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataa_clock = "none";
parameter datab_clock = "none";
parameter signa_clock = "none";
parameter signb_clock = "none";
parameter lpm_hint = "true";
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
input clk;
input aclr;
input ena;
input devclrn;
input devpor;
output [dataa_width+datab_width-1:0] dataout;
endmodule
| 6.684394 |
module alta_crcblock (
clk,
shiftnld,
ldsrc,
crcerror,
regout
);
input clk;
input shiftnld;
input ldsrc;
output crcerror;
output regout;
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_crcblock";
parameter oscillator_divider = 1;
endmodule
| 7.591494 |
module alta_ram_block (
portadatain,
portaaddr,
portawe,
portbdatain,
portbaddr,
portbrewe,
clk0,
clk1,
ena0,
ena1,
clr0,
clr1,
portabyteenamasks,
portbbyteenamasks,
portaaddrstall,
portbaddrstall,
devclrn,
devpor,
portadataout,
portbdataout
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_ram_block";
parameter operation_mode = "single_port";
parameter mixed_port_feed_through_mode = "dont_care";
parameter ram_block_type = "auto";
parameter logical_ram_name = "ram_name";
parameter init_file = "init_file.hex";
parameter init_file_layout = "none";
parameter data_interleave_width_in_bits = 1;
parameter data_interleave_offset_in_bits = 1;
parameter port_a_logical_ram_depth = 0;
parameter port_a_logical_ram_width = 0;
parameter port_a_first_address = 0;
parameter port_a_last_address = 0;
parameter port_a_first_bit_number = 0;
parameter port_a_data_out_clear = "none";
parameter port_a_data_out_clock = "none";
parameter port_a_data_width = 64;
parameter port_a_address_width = 32;
parameter port_a_byte_enable_mask_width = 8;
parameter port_b_logical_ram_depth = 0;
parameter port_b_logical_ram_width = 0;
parameter port_b_first_address = 0;
parameter port_b_last_address = 0;
parameter port_b_first_bit_number = 0;
parameter port_b_data_in_clear = "none";
parameter port_b_address_clear = "none";
parameter port_b_read_enable_write_enable_clear = "none";
parameter port_b_byte_enable_clear = "none";
parameter port_b_data_out_clear = "none";
parameter port_b_data_in_clock = "clock1";
parameter port_b_address_clock = "clock1";
parameter port_b_read_enable_write_enable_clock = "clock1";
parameter port_b_byte_enable_clock = "clock1";
parameter port_b_data_out_clock = "none";
parameter port_b_data_width = 64;
parameter port_b_address_width = 32;
parameter port_b_byte_enable_mask_width = 8;
parameter power_up_uninitialized = "false";
parameter lpm_hint = "true";
parameter connectivity_checking = "off";
parameter mem_init0 = 2048'b0;
parameter mem_init1 = 2560'b0;
parameter port_a_byte_size = 0;
parameter port_a_disable_ce_on_input_registers = "off";
parameter port_a_disable_ce_on_output_registers = "off";
parameter port_b_byte_size = 0;
parameter port_b_disable_ce_on_input_registers = "off";
parameter port_b_disable_ce_on_output_registers = "off";
parameter safe_write = "err_on_2clk";
parameter init_file_restructured = "unused";
parameter port_a_data_in_clear = "none";
parameter port_a_address_clear = "none";
parameter port_a_write_enable_clear = "none";
parameter port_a_byte_enable_clear = "none";
parameter port_a_data_in_clock = "clock0";
parameter port_a_address_clock = "clock0";
parameter port_a_write_enable_clock = "clock0";
parameter port_a_byte_enable_clock = "clock0";
input portawe;
input [port_a_data_width - 1:0] portadatain;
input [port_a_address_width - 1:0] portaaddr;
input [port_a_byte_enable_mask_width - 1:0] portabyteenamasks;
input portbrewe;
input [port_b_data_width - 1:0] portbdatain;
input [port_b_address_width - 1:0] portbaddr;
input [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks;
input clr0, clr1;
input clk0, clk1;
input ena0, ena1;
input devclrn, devpor;
input portaaddrstall;
input portbaddrstall;
output [port_a_data_width - 1:0] portadataout;
output [port_b_data_width - 1:0] portbdataout;
endmodule
| 8.129447 |
module alta_jtag (
tdouser,
tmsutap,
tckutap,
tdiutap,
shiftuser,
clkdruser,
updateuser,
runidleuser,
usr1user
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_jtag";
input tdouser;
output tmsutap;
output tckutap;
output tdiutap;
output shiftuser;
output clkdruser;
output updateuser;
output runidleuser;
output usr1user;
endmodule
| 6.911715 |
module alta_mac_out (
dataa,
clk,
aclr,
ena,
dataout,
devclrn,
devpor
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_mac_out";
parameter dataa_width = 36;
parameter lpm_hint = "true";
parameter output_clock = "none";
input [dataa_width-1:0] dataa;
output [dataa_width-1:0] dataout;
input clk;
input aclr;
input ena;
input devclrn;
input devpor;
endmodule
| 7.456496 |
module alta_clk_delay_ctrl (
clk,
delayctrlin,
disablecalibration,
pllcalibrateclkdelayedin,
devpor,
devclrn,
clkout
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_clk_delay_ctrl";
parameter behavioral_sim_delay = 0;
parameter delay_chain = "54"; // or "1362ps"
parameter delay_chain_mode = "static";
parameter uses_calibration = "false";
parameter use_new_style_dq_detection = "false";
parameter tan_delay_under_delay_ctrl_signal = "unused";
parameter delay_ctrl_sim_delay_15_0 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter delay_ctrl_sim_delay_31_16 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter delay_ctrl_sim_delay_47_32 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter delay_ctrl_sim_delay_63_48 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
input clk;
input [5:0] delayctrlin;
input disablecalibration;
input pllcalibrateclkdelayedin;
input devpor;
input devclrn;
output clkout;
endmodule
| 6.922885 |
module alta_dio (
padio,
datain,
datainh,
oe,
outclk,
outclkena,
inclk,
inclkena,
areset,
sreset,
combout,
regout,
devclrn,
devpor,
devoe,
differentialin,
differentialout,
linkin,
linkout
);
inout padio;
input datain, datainh, oe, outclk, outclkena, inclk, inclkena, areset, sreset;
output combout, regout;
input devclrn, devpor, devoe;
input linkin;
input differentialin;
output differentialout;
output linkout;
parameter lpm_type = "alta_dio";
parameter IN_ASYNC_MODE = 1'b0;
parameter IN_SYNC_MODE = 1'b0;
parameter IN_POWERUP = 1'b0;
parameter IN_ASYNC_DISABLE = 1'b0;
parameter IN_SYNC_DISABLE = 1'b0;
parameter OUT_REG_MODE = 1'b0;
parameter OUT_ASYNC_MODE = 1'b0;
parameter OUT_SYNC_MODE = 1'b0;
parameter OUT_POWERUP = 1'b0;
parameter OUT_CLKEN_DISABLE = 1'b0;
parameter OUT_ASYNC_DISABLE = 1'b0;
parameter OUT_SYNC_DISABLE = 1'b0;
parameter OUT_DDIO = 1'b0;
parameter OE_REG_MODE = 1'b0;
parameter OE_ASYNC_MODE = 1'b0;
parameter OE_SYNC_MODE = 1'b0;
parameter OE_POWERUP = 1'b0;
parameter OE_CLKEN_DISABLE = 1'b0;
parameter OE_ASYNC_DISABLE = 1'b0;
parameter OE_SYNC_DISABLE = 1'b0;
parameter OE_DDIO = 1'b0;
parameter inclkCFG = 2'b0;
parameter outclkCFG = 2'b0;
parameter CFG_TRI_INPUT = 1'b0;
parameter CFG_PULL_UP = 1'b0;
parameter CFG_OPEN_DRAIN = 1'b0;
parameter CFG_ROCT_CAL_EN = 1'b0;
parameter CFG_PDRV = 7'b0010000;
parameter CFG_NDRV = 7'b0010000;
parameter CFG_KEEP = 2'b0;
parameter CFG_LVDS_OUT_EN = 1'b0;
parameter CFG_LVDS_SEL_CUA = 3'b0;
parameter CFG_LVDS_IREF = 10'b0110000000;
parameter CFG_LVDS_IN_EN = 1'b0;
parameter CFG_SSTL_OUT_EN = 1'b0;
parameter CFG_SSTL_INPUT_EN = 1'b0;
parameter CFG_SSTL_SEL_CUA = 3'b011;
parameter CFG_OSCDIV = 2'b0;
parameter CFG_ROCTUSR = 1'b0;
parameter CFG_SEL_CUA = 1'b0;
parameter CFG_ROCT_EN = 1'b0;
parameter OUT_DELAY = 1'b0;
parameter IN_DATA_DELAY = 3'b0;
parameter IN_REG_DELAY = 3'b0;
parameter DPCLK_DELAY = 4'b0;
endmodule
| 6.509055 |
module alta_mult (
Clk,
ClkEn,
AsyncReset,
SignA,
SignB,
DataInA0,
DataInB0,
DataInA1,
DataInB1,
DataOut0,
DataOut1,
devpor,
devclrn,
devoe
);
input Clk, ClkEn, AsyncReset;
input SignA, SignB;
input [8:0] DataInA0, DataInB0, DataInA1, DataInB1;
output [17:0] DataOut0, DataOut1;
input devclrn, devpor, devoe;
parameter lpm_type = "alta_mult";
parameter MULT_MODE = 1'b0; // 0: 18x18, 1: 9x9
parameter PORTA_INREG0 = 1'b0;
parameter PORTA_INREG1 = 1'b0;
parameter PORTB_INREG0 = 1'b0;
parameter PORTB_INREG1 = 1'b0;
parameter SIGNA_REG = 1'b0;
parameter SIGNB_REG = 1'b0;
parameter OUTREG0 = 1'b0;
parameter OUTREG1 = 1'b0;
parameter ClkCFG = 2'b0;
endmodule
| 6.514713 |
module alta_i2c (
Clk,
Rst,
WrRdn,
Strobe,
Sdai,
Scli,
DataIn,
Address,
Wakeup,
Irq,
Ack,
Sdao,
Sclo,
DataOut,
devpor,
devclrn,
devoe
);
input Clk, Rst;
input WrRdn, Strobe;
input Sdai, Scli;
input [7:0] DataIn;
input [7:0] Address;
output Wakeup, Irq, Ack;
output Sdao, Sclo;
output [7:0] DataOut;
input devclrn, devpor, devoe;
parameter lpm_type = "alta_i2c";
parameter SLOT_ID = 4'b0000;
parameter ClkCFG = 2'b0;
endmodule
| 8.182431 |
module alta_spi (
Clk,
Rst,
WrRdn,
Strobe,
DataIn,
Address,
Mi,
Si,
Scki,
Csi,
Wakeup,
Irq,
Ack,
So,
Soe,
Mo,
Moe,
Scko,
Sckoe,
Cso,
Csoe,
DataOut,
devpor,
devclrn,
devoe
);
input Clk, Rst;
input WrRdn, Strobe;
input [7:0] DataIn;
input [7:0] Address;
input Mi, Si, Scki, Csi;
output Wakeup, Irq, Ack;
output So, Soe, Mo, Moe, Scko, Sckoe;
output [3:0] Cso;
output [3:0] Csoe;
output [7:0] DataOut;
input devclrn, devpor, devoe;
parameter lpm_type = "alta_spi";
parameter SLOT_ID = 4'b0000;
parameter ClkCFG = 2'b0;
endmodule
| 6.884698 |
module alta_irda (
ir_clk,
ir_reset,
cal_en,
tia_reset,
pu_ivref,
pu_pga,
pu_dac,
vip,
vin,
irx_data,
cal_ready,
dac_cal_reg,
devpor,
devclrn,
devoe
);
input ir_clk;
input ir_reset;
input cal_en;
input pu_ivref;
input pu_pga;
input pu_dac;
input tia_reset;
input vip;
input vin;
output irx_data;
output cal_ready;
output [7:0] dac_cal_reg;
input devclrn, devpor, devoe;
parameter lpm_type = "alta_irda";
parameter CFG_IRIP_EN = 1'b1;
parameter CLK_SEL_SYS = 1'b0;
parameter CLK_DIV_CMP_SYS = 3'b010;
parameter CLK_DIV_SYS = 3'b010;
parameter PU_HYSTER_SYS = 1'b0;
parameter REG_BYPASS_SYS = 1'b0;
parameter OUTPUT_SEL_SYS = 1'b0;
parameter CAL_READY_REG_SYS = 1'b0;
parameter CAL_READY_DR_SYS = 1'b0;
parameter CAL_TIME_SYS = 2'b10;
parameter CAL_DELAY_SYS = 2'b10;
parameter CAL_SPEED_SYS = 2'b10;
parameter DC_ACC_GAIN_SYS = 3'b001;
parameter BYPASS_DC_CALC_SYS = 1'b0;
parameter DC_TIME_SEL_SYS = 3'b0;
parameter REG_VBIT_SYS = 2'b01;
parameter RX_CAL_BIT_SYS = 8'b10000000;
parameter RX_CAL_BIT_DR_SYS = 1'b0;
parameter RX_DC_POLARITY_SYS = 1'b0;
parameter RX_CAL_POLARITY_SYS = 1'b0;
parameter DC_GAIN_SYS = 5'b10000;
parameter DAC_GAIN_SYS = 2'b01;
parameter DAC_RANGE_SYS = 2'b01;
parameter PGA_CAP_BIT_SYS = 4'b1000;
parameter PGA_CAP_EN_SYS = 1'b0;
parameter PGA_CAL_MODE_SYS = 1'b0;
parameter PGA_GAIN2_SYS = 2'b01;
parameter PGA_GAIN_SYS = 3'b100;
parameter DIFF_EN_SYS = 1'b0;
parameter TIA_GAIN_SYS = 2'b01;
parameter BG_SEL_SYS = 1'b0;
endmodule
| 6.503688 |
module alta_pllv (
clkin,
clkfb,
pllen,
resetn,
clkout0en,
clkout1en,
clkout2en,
clkout3en,
clkout4en,
clkout0,
clkout1,
clkout2,
clkout3,
clkout4,
clkfbout,
lock,
devpor,
devclrn,
devoe
);
input clkin;
input clkfb;
input pllen;
input resetn;
input clkout0en;
input clkout1en;
input clkout2en;
input clkout3en;
input clkout4en;
output clkout0;
output clkout1;
output clkout2;
output clkout3;
output clkout4;
output clkfbout;
output lock;
input devpor, devclrn, devoe;
parameter CLKIN_FREQ = "20.0";
parameter CLKIN_DIV = 9'b0;
parameter CLKFB_DIV = 9'b0;
parameter CLKDIV0_EN = 1'b0;
parameter CLKDIV1_EN = 1'b0;
parameter CLKDIV2_EN = 1'b0;
parameter CLKDIV3_EN = 1'b0;
parameter CLKDIV4_EN = 1'b0;
parameter CLKOUT0_HIGH = 8'b0;
parameter CLKOUT0_LOW = 8'b0;
parameter CLKOUT0_TRIM = 1'b0;
parameter CLKOUT0_BYPASS = 1'b0;
parameter CLKOUT1_HIGH = 8'b0;
parameter CLKOUT1_LOW = 8'b0;
parameter CLKOUT1_TRIM = 1'b0;
parameter CLKOUT1_BYPASS = 1'b0;
parameter CLKOUT2_HIGH = 8'b0;
parameter CLKOUT2_LOW = 8'b0;
parameter CLKOUT2_TRIM = 1'b0;
parameter CLKOUT2_BYPASS = 1'b0;
parameter CLKOUT3_HIGH = 8'b0;
parameter CLKOUT3_LOW = 8'b0;
parameter CLKOUT3_TRIM = 1'b0;
parameter CLKOUT3_BYPASS = 1'b0;
parameter CLKOUT4_HIGH = 8'b0;
parameter CLKOUT4_LOW = 8'b0;
parameter CLKOUT4_TRIM = 1'b0;
parameter CLKOUT4_BYPASS = 1'b0;
parameter CLKOUT0_DEL = 8'b0;
parameter CLKOUT1_DEL = 8'b0;
parameter CLKOUT2_DEL = 8'b0;
parameter CLKOUT3_DEL = 8'b0;
parameter CLKOUT4_DEL = 8'b0;
parameter CLKOUT0_PHASE = 3'b0;
parameter CLKOUT1_PHASE = 3'b0;
parameter CLKOUT2_PHASE = 3'b0;
parameter CLKOUT3_PHASE = 3'b0;
parameter CLKOUT4_PHASE = 3'b0;
parameter CLKFB_DEL = 8'b0;
parameter CLKFB_PHASE = 3'b0;
parameter CLKFB_TRIM = 1'b0;
parameter FEEDBACK_MODE = 3'b0;
parameter FBDELAY_VAL = 3'b0;
parameter PLLOUTP_EN = 1'b0;
parameter PLLOUTN_EN = 1'b0;
parameter CLKOUT1_CASCADE = 1'b0;
parameter CLKOUT2_CASCADE = 1'b0;
parameter CLKOUT3_CASCADE = 1'b0;
parameter CLKOUT4_CASCADE = 1'b0;
parameter CP = 3'b111;
parameter RREF = 2'b00;
parameter RVI = 2'b00;
endmodule
| 7.257119 |
module alta_pllve (
clkin,
clkfb,
pfden,
resetn,
phasecounterselect,
phaseupdown,
phasestep,
scanclk,
scanclkena,
scandata,
configupdate,
scandataout,
scandone,
phasedone,
clkout0,
clkout1,
clkout2,
clkout3,
clkout4,
clkfbout,
lock,
devpor,
devclrn,
devoe
);
input clkin;
input clkfb;
input pfden;
input resetn;
input [2:0] phasecounterselect;
input phaseupdown, phasestep;
input scanclk, scanclkena, scandata, configupdate;
output scandataout, scandone, phasedone;
output clkout0;
output clkout1;
output clkout2;
output clkout3;
output clkout4;
output clkfbout;
output lock;
input devpor, devclrn, devoe;
parameter CLKIN_FREQ = "20.0";
parameter CLKIN_HIGH = 8'b0;
parameter CLKIN_LOW = 8'b0;
parameter CLKIN_TRIM = 1'b0;
parameter CLKIN_BYPASS = 1'b0;
parameter CLKFB_HIGH = 8'b0;
parameter CLKFB_LOW = 8'b0;
parameter CLKFB_TRIM = 1'b0;
parameter CLKFB_BYPASS = 1'b0;
parameter CLKDIV0_EN = 1'b0;
parameter CLKDIV1_EN = 1'b0;
parameter CLKDIV2_EN = 1'b0;
parameter CLKDIV3_EN = 1'b0;
parameter CLKDIV4_EN = 1'b0;
parameter CLKOUT0_HIGH = 8'b0;
parameter CLKOUT0_LOW = 8'b0;
parameter CLKOUT0_TRIM = 1'b0;
parameter CLKOUT0_BYPASS = 1'b0;
parameter CLKOUT1_HIGH = 8'b0;
parameter CLKOUT1_LOW = 8'b0;
parameter CLKOUT1_TRIM = 1'b0;
parameter CLKOUT1_BYPASS = 1'b0;
parameter CLKOUT2_HIGH = 8'b0;
parameter CLKOUT2_LOW = 8'b0;
parameter CLKOUT2_TRIM = 1'b0;
parameter CLKOUT2_BYPASS = 1'b0;
parameter CLKOUT3_HIGH = 8'b0;
parameter CLKOUT3_LOW = 8'b0;
parameter CLKOUT3_TRIM = 1'b0;
parameter CLKOUT3_BYPASS = 1'b0;
parameter CLKOUT4_HIGH = 8'b0;
parameter CLKOUT4_LOW = 8'b0;
parameter CLKOUT4_TRIM = 1'b0;
parameter CLKOUT4_BYPASS = 1'b0;
parameter CLKOUT0_DEL = 8'b0;
parameter CLKOUT1_DEL = 8'b0;
parameter CLKOUT2_DEL = 8'b0;
parameter CLKOUT3_DEL = 8'b0;
parameter CLKOUT4_DEL = 8'b0;
parameter CLKOUT0_PHASE = 3'b0;
parameter CLKOUT1_PHASE = 3'b0;
parameter CLKOUT2_PHASE = 3'b0;
parameter CLKOUT3_PHASE = 3'b0;
parameter CLKOUT4_PHASE = 3'b0;
parameter CLKFB_DEL = 8'b0;
parameter CLKFB_PHASE = 3'b0;
parameter FEEDBACK_MODE = 3'b0;
parameter FBDELAY_VAL = 3'b0;
parameter PLLOUTP_EN = 1'b0;
parameter PLLOUTN_EN = 1'b0;
parameter CLKOUT1_CASCADE = 1'b0;
parameter CLKOUT2_CASCADE = 1'b0;
parameter CLKOUT3_CASCADE = 1'b0;
parameter CLKOUT4_CASCADE = 1'b0;
parameter VCO_POST_DIV = 1'b0;
parameter REG_CTRL = 2'bxx;
parameter CP = 3'bxxx;
parameter RREF = 2'bxx;
parameter RVI = 2'bxx;
parameter IVCO = 3'bxxx;
endmodule
| 7.608924 |
module alta_oct (
clkusr,
rstnusr,
octdone,
octdoneuser,
rupcompout,
rdncompout,
rupoctcalnout,
rdnoctcalnout
);
input clkusr, rstnusr;
output octdone, octdoneuser;
output rupcompout, rdncompout;
output rupoctcalnout, rdnoctcalnout;
parameter OCT_CLKDIV = 2'b00;
parameter OCT_EN = 1'b0;
parameter OCT_USR = 1'b0;
endmodule
| 7.44494 |
module alta_rv32 (
sys_clk,
mem_ahb_hready,
mem_ahb_hreadyout,
mem_ahb_htrans,
mem_ahb_hsize,
mem_ahb_hburst,
mem_ahb_hwrite,
mem_ahb_haddr,
mem_ahb_hwdata,
mem_ahb_hresp,
mem_ahb_hrdata,
slave_ahb_hsel,
slave_ahb_hready,
slave_ahb_hreadyout,
slave_ahb_htrans,
slave_ahb_hsize,
slave_ahb_hburst,
slave_ahb_hwrite,
slave_ahb_haddr,
slave_ahb_hwdata,
slave_ahb_hresp,
slave_ahb_hrdata,
gpio0_io_in,
gpio0_io_out_data,
gpio0_io_out_en,
gpio1_io_in,
gpio1_io_out_data,
gpio1_io_out_en,
sys_ctrl_clkSource,
sys_ctrl_hseEnable,
sys_ctrl_hseBypass,
sys_ctrl_pllEnable,
sys_ctrl_pllReady,
sys_ctrl_sleep,
sys_ctrl_stop,
sys_ctrl_standby,
gpio2_io_in,
gpio2_io_out_data,
gpio2_io_out_en,
gpio3_io_in,
gpio3_io_out_data,
gpio3_io_out_en,
gpio4_io_in,
gpio4_io_out_data,
gpio4_io_out_en,
gpio5_io_in,
gpio5_io_out_data,
gpio5_io_out_en,
gpio6_io_in,
gpio6_io_out_data,
gpio6_io_out_en,
gpio7_io_in,
gpio7_io_out_data,
gpio7_io_out_en,
gpio8_io_in,
gpio8_io_out_data,
gpio8_io_out_en,
gpio9_io_in,
gpio9_io_out_data,
gpio9_io_out_en,
ext_resetn,
resetn_out,
dmactive,
swj_JTAGNSW,
swj_JTAGSTATE,
swj_JTAGIR,
ext_int,
ext_dma_DMACBREQ,
ext_dma_DMACLBREQ,
ext_dma_DMACSREQ,
ext_dma_DMACLSREQ,
ext_dma_DMACCLR,
ext_dma_DMACTC,
local_int,
test_mode,
usb0_xcvr_clk,
usb0_id,
devpor,
devclrn,
devoe
);
input devclrn, devpor, devoe;
input sys_clk;
output mem_ahb_hready;
input mem_ahb_hreadyout;
output [1:0] mem_ahb_htrans;
output [2:0] mem_ahb_hsize;
output [2:0] mem_ahb_hburst;
output mem_ahb_hwrite;
output [31:0] mem_ahb_haddr;
output [31:0] mem_ahb_hwdata;
input mem_ahb_hresp;
input [31:0] mem_ahb_hrdata;
input slave_ahb_hsel;
input slave_ahb_hready;
output slave_ahb_hreadyout;
input [1:0] slave_ahb_htrans;
input [2:0] slave_ahb_hsize;
input [2:0] slave_ahb_hburst;
input slave_ahb_hwrite;
input [31:0] slave_ahb_haddr;
input [31:0] slave_ahb_hwdata;
output slave_ahb_hresp;
output [31:0] slave_ahb_hrdata;
input [7:0] gpio0_io_in;
output [7:0] gpio0_io_out_data;
output [7:0] gpio0_io_out_en;
input [7:0] gpio1_io_in;
output [7:0] gpio1_io_out_data;
output [7:0] gpio1_io_out_en;
output [1:0] sys_ctrl_clkSource;
output sys_ctrl_hseEnable;
output sys_ctrl_hseBypass;
output sys_ctrl_pllEnable;
input sys_ctrl_pllReady;
output sys_ctrl_sleep;
output sys_ctrl_stop;
output sys_ctrl_standby;
input [7:0] gpio2_io_in;
output [7:0] gpio2_io_out_data;
output [7:0] gpio2_io_out_en;
input [7:0] gpio3_io_in;
output [7:0] gpio3_io_out_data;
output [7:0] gpio3_io_out_en;
input [7:0] gpio4_io_in;
output [7:0] gpio4_io_out_data;
output [7:0] gpio4_io_out_en;
input [7:0] gpio5_io_in;
output [7:0] gpio5_io_out_data;
output [7:0] gpio5_io_out_en;
input [7:0] gpio6_io_in;
output [7:0] gpio6_io_out_data;
output [7:0] gpio6_io_out_en;
input [7:0] gpio7_io_in;
output [7:0] gpio7_io_out_data;
output [7:0] gpio7_io_out_en;
input [7:0] gpio8_io_in;
output [7:0] gpio8_io_out_data;
output [7:0] gpio8_io_out_en;
input [7:0] gpio9_io_in;
output [7:0] gpio9_io_out_data;
output [7:0] gpio9_io_out_en;
input ext_resetn;
output resetn_out;
output dmactive;
output swj_JTAGNSW;
output [3:0] swj_JTAGSTATE;
output [3:0] swj_JTAGIR;
input [7:0] ext_int;
input [3:0] ext_dma_DMACBREQ;
input [3:0] ext_dma_DMACLBREQ;
input [3:0] ext_dma_DMACSREQ;
input [3:0] ext_dma_DMACLSREQ;
output [3:0] ext_dma_DMACCLR;
output [3:0] ext_dma_DMACTC;
input [3:0] local_int;
input [1:0] test_mode;
input usb0_xcvr_clk;
input usb0_id;
endmodule
| 7.267946 |
module alta_adc (
devpor,
devclrn,
devoe,
enb,
sclk,
insel,
stop,
db,
eoc
);
input devclrn, devpor, devoe;
input enb, sclk, stop;
input [4:0] insel;
output [11:0] db;
output eoc;
endmodule
| 6.628961 |
module alta_cmp (
devpor,
devclrn,
devoe,
enb1,
imsel1,
ipsel1,
hyst1,
mode1,
enb2,
imsel2,
ipsel2,
hyst2,
mode2,
out1,
out2,
stop
);
input devclrn, devpor, devoe;
input enb1, enb2, hyst1, hyst2, mode1, mode2, stop;
input [2:0] imsel1, imsel2;
input [1:0] ipsel1, ipsel2;
output out1, out2;
endmodule
| 6.506983 |
module altddio_in
#(
parameter WIDTH=1
)
(
`IOB_INPUT(inclock, 1),
`IOB_OUTPUT(dataout_l, WIDTH),
`IOB_OUTPUT(dataout_h, WIDTH),
`IOB_INPUT(datain, WIDTH)
);
`IOB_VAR(dataout_l_reg, WIDTH)
`IOB_VAR(dataout_h_reg, WIDTH)
always @(posedge inclock)
dataout_h_reg <= datain;
always @(negedge inclock)
dataout_l_reg <= datain;
assign dataout_l = dataout_l_reg;
assign dataout_h = dataout_h_reg;
endmodule
| 7.30907 |
module altddio_out
#(
parameter WIDTH=1
)
(
`IOB_INPUT(outclock, 1),
`IOB_INPUT(datain_l, WIDTH),
`IOB_INPUT(datain_h, WIDTH),
`IOB_OUTPUT(dataout, WIDTH)
);
`IOB_VAR(datain_l_reg, WIDTH)
`IOB_VAR(datain_h_reg, WIDTH)
always @(posedge outclock)
datain_h_reg <= datain_h;
always @(negedge outclock)
datain_l_reg <= datain_l;
assign dataout = outclock ? datain_h_reg: datain_l_reg;
endmodule
| 7.581103 |
module AlteraDivider (
denom,
numer,
quotient,
remain
);
input [15:0] denom;
input [31:0] numer;
output [31:0] quotient;
output [15:0] remain;
wire [31:0] sub_wire0;
wire [15:0] sub_wire1;
wire [31:0] quotient = sub_wire0[31:0];
wire [15:0] remain = sub_wire1[15:0];
lpm_divide LPM_DIVIDE_component (
.denom(denom),
.numer(numer),
.quotient(sub_wire0),
.remain(sub_wire1),
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
);
defparam LPM_DIVIDE_component.lpm_drepresentation = "UNSIGNED", LPM_DIVIDE_component.lpm_hint =
"LPM_REMAINDERPOSITIVE=TRUE", LPM_DIVIDE_component.lpm_nrepresentation = "UNSIGNED",
LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE", LPM_DIVIDE_component.lpm_widthd = 16,
LPM_DIVIDE_component.lpm_widthn = 32;
endmodule
| 7.946487 |
module AlteraDivider (
denom,
numer,
quotient,
remain
);
input [15:0] denom;
input [31:0] numer;
output [31:0] quotient;
output [15:0] remain;
endmodule
| 7.946487 |
module AlteraMultiplier (
dataa,
datab,
result
);
input [15:0] dataa;
input [15:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
lpm_mult lpm_mult_component (
.dataa(dataa),
.datab(datab),
.result(sub_wire0),
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0),
.sum(1'b0)
);
defparam lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5", lpm_mult_component.lpm_representation =
"SIGNED", lpm_mult_component.lpm_type = "LPM_MULT", lpm_mult_component.lpm_widtha = 16,
lpm_mult_component.lpm_widthb = 16, lpm_mult_component.lpm_widthp = 32;
endmodule
| 6.542651 |
module AlteraMultiplier (
dataa,
datab,
result
);
input [15:0] dataa;
input [15:0] datab;
output [31:0] result;
endmodule
| 6.542651 |
module AlteraRAM8Kx8 (
address,
clock,
data,
wren,
q);
input [12:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "redforth_reloc.rif"
`else
altsyncram_component.init_file = "redforth_reloc.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=RAM",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8096,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 13,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
| 6.559793 |
module AlteraRAM8Kx8 (
address,
clock,
data,
wren,
q
);
input [12:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.559793 |
module AlteraRAM_64Kx8 (
address,
clock,
data,
wren,
q
);
input [15:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a(address),
.clock0(clock),
.data_a(data),
.wren_a(wren),
.q_a(sub_wire0),
.aclr0(1'b0),
.aclr1(1'b0),
.address_b(1'b1),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a(1'b1),
.byteena_b(1'b1),
.clock1(1'b1),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
.data_b(1'b1),
.eccstatus(),
.q_b(),
.rden_a(1'b1),
.rden_b(1'b1),
.wren_b(1'b0)
);
defparam altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone II", altsyncram_component.lpm_hint =
"ENABLE_RUNTIME_MOD=NO", altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 65536, altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE", altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE", altsyncram_component.widthad_a = 16,
altsyncram_component.width_a = 8, altsyncram_component.width_byteena_a = 1;
endmodule
| 6.765616 |
module AlteraRAM_64Kx8 (
address,
clock,
data,
wren,
q
);
input [15:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.765616 |
module altera_asmi_rom (
input wire [23:0] addr, // addr.addr
output wire busy, // busy.busy
input wire clkin, // clkin.clk
output wire data_valid, // data_valid.data_valid
output wire [ 7:0] dataout, // dataout.dataout
input wire rden, // rden.rden
input wire read, // read.read
input wire reset // reset.reset
);
altera_asmi_rom_asmi_parallel_0 asmi_parallel_0 (
.clkin (clkin), // clkin.clk
.read (read), // read.read
.rden (rden), // rden.rden
.addr (addr), // addr.addr
.reset (reset), // reset.reset
.dataout (dataout), // dataout.dataout
.busy (busy), // busy.busy
.data_valid(data_valid) // data_valid.data_valid
);
endmodule
| 6.859843 |
module altera_asmi_rom (
clkin,
read,
rden,
addr,
reset,
dataout,
busy,
data_valid
);
input clkin;
input read;
input rden;
input [23:0] addr;
input reset;
output [7:0] dataout;
output busy;
output data_valid;
endmodule
| 6.859843 |
module altera_avalon_i2c_fifo #(
parameter DSIZE = 8,
parameter FIFO_DEPTH = 256,
parameter FIFO_DEPTH_LOG2 = 8,
parameter LATENCY = 2
) (
input clk,
input rst_n,
input s_rst,
input [DSIZE-1:0] wdata,
input put,
input get,
output full,
output empty,
output empty_dly,
output [FIFO_DEPTH_LOG2:0] navail,
output [ DSIZE-1:0] rdata
);
reg [FIFO_DEPTH_LOG2-1:0] write_address;
reg [FIFO_DEPTH_LOG2-1:0] read_address;
reg [FIFO_DEPTH_LOG2:0] internal_used;
reg empty_d1;
reg empty_d2;
wire internal_full;
wire internal_empty;
wire [(DSIZE/8)-1:0] write_byteenables;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
write_address <= 0;
end else begin
if (s_rst) begin
write_address <= 0;
end else if (put == 1) begin
write_address <= write_address + 1'b1;
end
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
read_address <= 0;
end else begin
if (s_rst) begin
read_address <= 0;
end else if (get == 1) begin
read_address <= read_address + 1'b1;
end
end
end
assign write_byteenables = {(DSIZE / 8) {1'b1}};
// TODO: Change this to an inferrered RAM when Quartus II supports byte enables for inferred RAM
altsyncram the_dp_ram (
.clock0(clk),
.wren_a(put),
.byteena_a(write_byteenables),
.data_a(wdata),
.address_a(write_address),
.q_b(rdata),
.address_b(read_address)
);
defparam the_dp_ram.operation_mode = "DUAL_PORT"; // simple dual port (one read, one write port)
defparam the_dp_ram.lpm_type = "altsyncram";
defparam the_dp_ram.read_during_write_mode_mixed_ports = "DONT_CARE";
defparam the_dp_ram.power_up_uninitialized = "TRUE";
defparam the_dp_ram.byte_size = 8;
defparam the_dp_ram.width_a = DSIZE;
defparam the_dp_ram.width_b = DSIZE;
defparam the_dp_ram.widthad_a = FIFO_DEPTH_LOG2;
defparam the_dp_ram.widthad_b = FIFO_DEPTH_LOG2;
defparam the_dp_ram.width_byteena_a = (DSIZE/8);
defparam the_dp_ram.numwords_a = FIFO_DEPTH;
defparam the_dp_ram.numwords_b = FIFO_DEPTH;
defparam the_dp_ram.address_reg_b = "CLOCK0";
defparam the_dp_ram.outdata_reg_b = (LATENCY == 2)? "CLOCK0" : "UNREGISTERED";
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
internal_used <= 0;
end else begin
if (s_rst) begin
internal_used <= 0;
end else begin
case ({
put, get
})
2'b01: internal_used <= internal_used - 1'b1;
2'b10: internal_used <= internal_used + 1'b1;
default: internal_used <= internal_used;
endcase
end
end
end
assign internal_empty = (read_address == write_address) & (internal_used == 0);
assign internal_full = (write_address == read_address) & (internal_used != 0);
assign navail = internal_used; // this signal reflects the number of words in the FIFO
assign empty = internal_empty; // combinational so it'll glitch a little bit
assign full = internal_full; // dito
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
empty_d1 <= 1'b1;
empty_d2 <= 1'b1;
end else begin
empty_d1 <= empty;
empty_d2 <= empty_d1;
end
end
assign empty_dly = empty | empty_d1 | empty_d2;
endmodule
| 7.767945 |
module altera_avalon_i2c_spksupp (
input clk,
input rst_n,
input [7:0] spike_len,
input sda_in,
input scl_in,
output sda_int,
output scl_int
);
// Status Register bit definition
// wires & registers declaration
reg [7:0] scl_spike_cnt;
reg scl_int_reg;
reg scl_doublesync_a;
reg [7:0] sda_spike_cnt;
reg sda_int_reg;
reg sda_doublesync_a;
reg scl_in_synced;
reg sda_in_synced;
wire scl_clear_cnt;
wire scl_cnt_limit;
wire scl_int_next;
wire sda_clear_cnt;
wire sda_cnt_limit;
wire sda_int_next;
// double sync flops for scl
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
scl_doublesync_a <= 1'b1;
scl_in_synced <= 1'b1;
end else begin
scl_doublesync_a <= scl_in;
scl_in_synced <= scl_doublesync_a;
end
end
//assign scl_in_synced = scl_doublesync_b;
// XOR: return 1 to increase counter ; return 0 to reset counter
assign scl_clear_cnt = ~(scl_in_synced ^ scl_int_next);
// scl counter
always @(posedge clk or negedge rst_n) begin
if (!rst_n) scl_spike_cnt <= 8'h0;
else if (scl_clear_cnt) scl_spike_cnt <= 8'h0;
else scl_spike_cnt <= scl_spike_cnt + 8'h1;
end
// to allow scl_in pass through to scl_int when the comparator returns 1
// if disallow to pass through, scl_int returns the prev value
// to make the scl_in pass through at the same clock as the counter reaching the limit value of suppression length
assign scl_cnt_limit = (scl_spike_cnt >= spike_len);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) scl_int_reg <= 1'b1;
else scl_int_reg <= scl_int_next;
end
assign scl_int_next = scl_cnt_limit ? scl_in_synced : scl_int_reg;
//assign scl_int = scl_cnt_limit ? scl_in_synced : scl_int_reg ;
assign scl_int = scl_int_reg; // Using the registered version to improve timing
// double sync flops for sda
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
sda_doublesync_a <= 1'b1;
sda_in_synced <= 1'b1;
end else begin
sda_doublesync_a <= sda_in;
sda_in_synced <= sda_doublesync_a;
end
end
// assign sda_in_synced = sda_doublesync_b;
// XOR: return 1 to increase counter ; return 0 to reset counter
assign sda_clear_cnt = ~(sda_in_synced ^ sda_int_next);
// sda counter
always @(posedge clk or negedge rst_n) begin
if (!rst_n) sda_spike_cnt <= 8'h0;
else if (sda_clear_cnt) sda_spike_cnt <= 8'h0;
else sda_spike_cnt <= sda_spike_cnt + 8'h1;
end
// to allow scl_in pass through to scl_int when the comparator returns 1
// if disallow to pass through, scl_int returns the prev value
// to make the scl_in pass through at the same clock as the counter reaching the limit value of suppression length
assign sda_cnt_limit = (sda_spike_cnt >= spike_len);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) sda_int_reg <= 1'b1;
else sda_int_reg <= sda_int_next;
end
assign sda_int_next = sda_cnt_limit ? sda_in_synced : sda_int_reg;
//assign sda_int = sda_cnt_limit ? sda_in_synced : sda_int_reg ;
assign sda_int = sda_int_reg; // Using the registered version to improve timing
endmodule
| 7.767945 |
module altera_avalon_i2c_txout (
input clk,
input rst_n,
input [15:0] sda_hold,
input start_sda_out,
input restart_sda_out,
input stop_sda_out,
input mst_tx_sda_out,
input mst_rx_sda_out,
input restart_scl_out,
input stop_scl_out,
input mst_tx_scl_out,
input mst_rx_scl_out,
input pop_tx_fifo_state,
input pop_tx_fifo_state_dly,
output sda_oe,
output scl_oe
);
reg data_oe;
reg clk_oe;
reg clk_oe_nxt_dly;
reg [15:0] sda_hold_cnt;
reg [15:0] sda_hold_cnt_nxt;
wire data_oe_nxt;
wire clk_oe_nxt;
wire clk_oe_nxt_hl;
wire load_sda_hold_cnt;
wire sda_hold_en;
assign data_oe_nxt = ~start_sda_out |
~restart_sda_out |
~stop_sda_out |
~mst_tx_sda_out |
~mst_rx_sda_out;
assign clk_oe_nxt = ~restart_scl_out | ~stop_scl_out | ~mst_tx_scl_out | ~mst_rx_scl_out;
assign clk_oe_nxt_hl = clk_oe_nxt & ~clk_oe_nxt_dly;
assign load_sda_hold_cnt = clk_oe_nxt_hl;
assign sda_hold_en = (sda_hold_cnt_nxt != 16'h0) | pop_tx_fifo_state | pop_tx_fifo_state_dly;
assign sda_oe = data_oe;
assign scl_oe = clk_oe;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) clk_oe_nxt_dly <= 1'b0;
else clk_oe_nxt_dly <= clk_oe_nxt;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) data_oe <= 1'b0;
else if (sda_hold_en) data_oe <= data_oe;
else data_oe <= data_oe_nxt;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) clk_oe <= 1'b0;
else if (pop_tx_fifo_state_dly) clk_oe <= clk_oe;
else clk_oe <= clk_oe_nxt;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) sda_hold_cnt <= 16'h0;
else sda_hold_cnt <= sda_hold_cnt_nxt;
end
always @* begin
if (load_sda_hold_cnt) sda_hold_cnt_nxt = (sda_hold - 16'h1);
else if (sda_hold_cnt != 16'h0) sda_hold_cnt_nxt = sda_hold_cnt - 16'h1;
else sda_hold_cnt_nxt = sda_hold_cnt;
end
endmodule
| 7.767945 |
module altera_avalon_jtag_uart_2pkhqydp_log_module (
// inputs:
clk,
data,
strobe,
valid
);
input clk;
input [7:0] data;
input strobe;
input valid;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
reg [31:0] text_handle; // for $fopen
initial text_handle = $fopen("altera_avalon_jtag_uart_2pkhqydp_output_stream.dat");
always @(posedge clk) begin
if (valid && strobe) begin
$fwrite(text_handle, "%b\n", data);
// echo raw binary strings to file as ascii to screen
$write("%s", ((data == 8'hd) ? 8'ha : data));
// non-standard; poorly documented; required to get real data stream.
$fflush(text_handle);
end
end // clk
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 7.767945 |
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