code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module alpha2_input_butterfly_47 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_48 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_49 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_5 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pro... | 6.698209 |
module alpha2_input_butterfly_50 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_51 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_52 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_53 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_54 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_55 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_56 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_57 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_58 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_59 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_6 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pro... | 6.698209 |
module alpha2_input_butterfly_60 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_61 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_62 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_63 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_64 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pr... | 6.698209 |
module alpha2_input_butterfly_7 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pro... | 6.698209 |
module alpha2_input_butterfly_8 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pro... | 6.698209 |
module alpha2_input_butterfly_9 (
In1,
In2,
Const_input,
Out1,
Out2
);
input signed [10:0] In1; // sfix11_En6
input signed [10:0] In2; // sfix11_En6
input Const_input; // ufix1
output signed [9:0] Out1; // sfix10_En4
output signed [9:0] Out2; // sfix10_En4
wire signed [10:0] Pro... | 6.698209 |
module alphabet_decoder (
input [2:0] alphabet_order,
output reg [24:0] display_code
);
always @(*) begin
case (alphabet_order)
3'd0: display_code = 25'b01111_10001_10011_10000_01111; // "G"
3'd1: display_code = 25'b10001_11111_10001_01010_00100; // "A"
3'd2: display_code = 25'b10001_1... | 7.319748 |
module AlphaCPU (
input wire clk,
rst
);
wire W_regfile_wea;
wire [2:0] W_alu_sel;
wire [3:0] W_mem_wea;
wire W_wb_regsrc_sel;
wire W_ex_rt_sel;
wire W_write_src_sel;
wire [1:0] W_branch;
wire [1:0] W_j_branch;
wire W_imme_sign_extend;
wire W_jal_en;
wire [5:0] W_instr_op;
wire [5:0] W... | 6.619408 |
module AlphaMissionCoreClocks_Cen (
input wire i_clk,
output wire clk_13p4_cen,
output wire clk_13p4,
output wire clk_13p4b_cen,
output wire clk_13p4b,
output wire clk_6p7_cen,
output wire clk_6p7b_cen,
output wire clk_3p35_cen,
output wire clk_3p35b_cen,
output wire clk_4_cen,
... | 7.304941 |
module alpha_blend (
input sys_clk,
input i_h_sync,
input i_v_sync,
input i_de,
input [7 : 0] i_back_ground_0_8b,
input [7 : 0] i_back_ground_1_8b,
input [7 : 0] i_back_ground_2_8b,
input [7 : 0] i_alpha_8b,
input [7 : 0] i_front_ground_0_8b,
input [7 : 0] i_front_ground_1_8b... | 6.658663 |
module alpha_clkmgr (
input wire gclk, // signal from clock pin
output wire sys_clk, // buffered system clock output
output wire sys_rst_n // system reset output (async set, sync clear, active-low)
);
//
// Parameters
//
parameter CLK_OUT_MUL = 20.0;
parameter CLK_OUT_DIV = 20.0;
//
//... | 7.611036 |
module board_regs (
// Clock and reset.
input wire clk,
input wire reset_n,
// Control.
input wire cs,
input wire we,
// Data ports.
input wire [ 7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error
);
//----------... | 7.886152 |
module alram1x (
clk, //clock
rst,
rdo, //data from ram
ra, //read address
wdi, //data to ram
wa, //write address
we //write enable
);
// =============================================================================
// == Parameter declarations
// ==============================... | 7.129739 |
module ALS (
input clk,
input MISO,
input rst,
output SCLK,
output CS,
output [7:0] led
);
parameter refresh_period = 75_000;
wire d_rdy;
wire [15:0] d;
reg rd;
reg [31:0] rd_count;
simpleSPI SPI1 (
.clk(clk),
.MISO(MISO),
.rd(rd),
.rst(rst),
.SCLK(S... | 7.124875 |
module normalize32( in, dist, out );
input [31:0] in;
output [4:0] dist;
output [31:0] out;
wire [3:1] reduce8s;
wire [4:0] dist;
wire [31:0] normTo8, out;
assign reduce8s[3] = ( in[31:24] != 0 );
assign reduce8s[2] = ( in[23:16] != 0 );
assign reduce8s[1] = ( in[15:8] != 0 )... | 6.784075 |
module ltd_counter (
// General signals
clk, // x1 mode = tx_clk
// x4 and x8 mode = refclk_out
// single width = 250 MHz
// double width mode = 125 MHz
reset_n, // IP reset
// Control
threshold, // Configurable: should remain static
reset_ltd_counter, // Resets counter: contr... | 6.771525 |
module alta_ufm (
input i_ufm_set,
input i_program,
input i_erase,
input i_osc_ena,
input i_arclk,
input i_arshift,
input i_ardin,
input i_drdin,
input i_drclk,
input i_drshift,
input i_tdo_u,
output o_tdi_u,
output o_tms_u,
output o_tck_u,
output o_shift_u,
output o_update_u,
output o... | 7.694658 |
module alta_pll (
input clkin,
input clkfb,
input pllen,
input resetn,
input pfden,
output clkout0,
output clkout1,
output lock,
);
parameter CLKIN_DIV = 6'b000000;
parameter CLKFB_DIV = 6'b000000;
parameter CLKOUT0_EN = 1'b0;
parameter CLKOUT1_EN = 1'b0;
parameter CLKOUT0_DIV = 6'b000000;
p... | 7.086106 |
module alta_pllx (
input clkin,
input clkfb,
input pllen,
input resetn,
input clkout0en,
input clkout1en,
input clkout2en,
input clkout3en,
output clkout0,
output clkout1,
output clkout2,
output clkout3,
output lock,
);
parameter CLKIN_DIV = 6'b000000;
parameter CLKFB_DIV = 6'b000000;
pa... | 7.145606 |
module alta_pllv (
input clkin,
input clkfb,
input pllen,
input resetn,
input clkout0en,
input clkout1en,
input clkout2en,
input clkout3en,
input clkout4en,
output clkout0,
output clkout1,
output clkout2,
output clkout3,
output clkout4,
output clkfbout,
output lock,
);
parameter CLKIN_... | 7.257119 |
module alta_pllve (
input clkin,
input clkfb,
input pfden,
input resetn,
input [2:0] phasecounterselect,
input phaseupdown,
input phasestep,
input scanclk,
input scanclkena,
input scandata,
input configupdate,
output clkout0,
output clkout1,
output clkout2,
output clkout3,
output clkout4... | 7.608924 |
module alta_mult (
input [8:0] DataInA0,
input [8:0] DataInA1,
input [8:0] DataInB0,
input [8:0] DataInb0,
input SignA,
input SignB,
input Clk,
input ClkEn,
input AsyncReset,
output [17:0] DataOut0,
output [17:0] DataOut1,
);
parameter MULT_MODE = 1'b0;
parameter PORTA_INREG0 = 1'b0;
paramet... | 6.514713 |
module alta_i2c (
input Clk,
input Rst,
input Strobe,
input WrRdn,
input [7:0] Address,
input [7:0] DataIn,
input Scli,
input Sdai,
output Ack,
output Irq,
output Wakeup,
output Sclo,
output Sdao,
output [7:0] DataOut,
);
parameter SLOT_ID = 4'b0000;
parameter ClkCFG = 2'b00;
endmodule
| 8.182431 |
module alta_spi (
input Clk,
input Rst,
input Strobe,
input WrRdn,
input [7:0] Address,
input [7:0] DataIn,
input Mi,
input Si,
input Scki,
input Csi,
output Ack,
output Irq,
output Wakeup,
output [7:0] DataOut,
output So,
output Soe,
output Mo,
output Moe,
output Scko,
output Sc... | 6.884698 |
module alta_irda (
input ir_clk,
input ir_reset,
input cal_en,
input pu_ivref,
input pu_pga,
input pu_dac,
input tia_reset,
input vip,
input vin,
output irx_data,
output cal_ready,
output [7:0] dac_cal_reg,
);
parameter CFG_IRIP_EN = 1'b0;
parameter CLK_SEL_SYS = 1'b0;
parameter CLK_DIV_CM... | 6.503688 |
module alta_io (
input datain,
input oe,
output combout,
input padio,
);
parameter PRG_DELAYB = 1'b0;
parameter PRG_DELAYB_P = 1'b0;
parameter PRG_DELAYB_N = 1'b0;
parameter RX_SEL = 1'b0;
parameter RX_SEL_P = 1'b0;
parameter RX_SEL_N = 1'b0;
parameter PDCNTL = 2'b00;
parameter PDCNTL_P = 2'b00;... | 6.637447 |
module alta_dio (
input datain,
input datainh,
input oe,
output combout,
output regout,
input outclk,
input outclkena,
input inclk,
input inclkena,
input areset,
input sreset,
input padio,
);
parameter IN_ASYNC_MODE = 1'b0;
parameter IN_SYNC_MODE = 1'b0;
parameter IN_POWERUP = 1'b0;
para... | 6.509055 |
module alta_indel (
input in,
output out,
);
endmodule
| 6.652631 |
module alta_slice (
input A,
input B,
input C,
input D,
output LutOut,
output Q,
input Cin,
output Cout,
input SyncReset,
input SyncLoad,
input Clk,
input AsyncReset,
input Qin,
input ShiftData,
);
parameter ClkMux = 2'b00;
parameter AsyncResetMux = 2'b00;
parameter SyncResetMux = 2'b0... | 7.398493 |
module alta_sram (
input [3:0] RAddr,
input [3:0] WAddr,
input [3:0] Din,
input WClk,
input WEna,
output [3:0] Dout,
);
parameter INIT_VAL = 64'h0;
endmodule
| 6.902908 |
module alta_asyncctrl (
input Din,
output Dout,
);
parameter AsyncCtrlMux = 2'b00;
endmodule
| 7.0483 |
module alta_io_gclk (
input inclk,
output outclk,
);
endmodule
| 6.587431 |
module alta_ufm_gddd (
input in,
output out,
);
endmodule
| 6.9667 |
module alta_clk_delay_ctrl ();
endmodule
| 6.922885 |
module alta_mac_out ();
endmodule
| 7.456496 |
module alta_mac_mult ();
endmodule
| 6.684394 |
module alta_ram_block ();
endmodule
| 8.129447 |
module alta_crcblock ();
endmodule
| 7.591494 |
module alta_jtag (
input tdouser,
output tmsutap,
output tckutap,
output tdiutap,
output shiftuser,
output clkdruser,
output updateuser,
output runidleuser,
output usr1user,
);
endmodule
| 6.911715 |
module alta_oct (
input clkusr,
input rstnusr,
output octdone,
output octdoneuser,
output rupcompout,
output rdncompout,
output rupoctcalnout,
output rdnoctcalnout,
);
parameter OCT_EN = 1'b0;
parameter OCT_CLKDIV = 2'b00;
parameter OCT_USR = 1'b0;
endmodule
| 7.44494 |
module altair_tb ();
reg clk = 0;
reg reset;
reg rx = 1'b1;
wire tx;
altair machine (
.clk(clk),
.reset(reset),
.rx(rx),
.tx(tx)
);
always #(5) clk <= !clk;
initial begin
$dumpfile("altair_tb.vcd");
$dumpvars(0, altair_tb);
reset = 1;
#20 reset = 0;
#220... | 6.512504 |
module alta_asyncctrl (
Din,
Dout
);
parameter AsyncCtrlMux = 2'b10;
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_asyncctrl";
input Din;
output Dout;
endmodule
| 7.0483 |
module alta_slice (
A,
B,
C,
D,
Cin,
Qin,
Clk,
AsyncReset,
SyncReset,
ShiftData,
SyncLoad,
LutOut,
Cout,
Q
);
// The following 10 bits are actually in LB, will be propagated to each slice by packer for software
// purpose only. 00: gnd, 01: vcc, 10: signal, ... | 7.398493 |
module alta_ufm_gddd (
in,
out
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_ufm_gddd";
input in;
output out;
endmodule
| 6.9667 |
module alta_io_gclk (
inclk,
outclk
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_io_gclk";
parameter clock_type = "global clock";
parameter ena_register_mode = "none";
input inclk;
output outclk;
endmodule
| 6.587431 |
module alta_ufm (
i_ufm_set,
i_program,
i_erase,
i_osc_ena,
i_arclk,
i_arshift,
i_ardin,
i_drdin,
i_drclk,
i_drshift,
i_tdo_u,
o_tdi_u,
o_tms_u,
o_tck_u,
o_shift_u,
o_update_u,
o_runidle_u,
o_rtp_busy,
o_ufm_busy,
o_osc,
o_drdout,
o... | 7.694658 |
module alta_sram (
WEna,
WClk,
Din,
WAddr,
RAddr,
Dout,
devpor,
devclrn,
devoe
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_sram";
parameter INIT_VAL = 64'h0;
input WEna, WClk;
input [3:0] Din;
input [3... | 6.902908 |
module alta_wram (
WEna,
WClk,
Din,
WAddr,
RAddr,
Dout,
devpor,
devclrn,
devoe
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_wram";
parameter INIT_VAL = 128'h0;
input WEna, WClk;
input [7:0] Din;
input [... | 6.749375 |
module alta_pll (
clkin,
clkfb,
pllen,
resetn,
pfden,
clkout0,
clkout1,
lock,
devpor,
devclrn,
devoe
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_pll";
parameter CLKIN_DIV = 6'h1;
parameter CLKFB_DIV... | 7.086106 |
module alta_pllx (
clkin,
clkfb,
pllen,
resetn,
clkout0en,
clkout1en,
clkout2en,
clkout3en,
clkout0,
clkout1,
clkout2,
clkout3,
lock,
devpor,
devclrn,
devoe
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter... | 7.145606 |
module alta_mac_mult (
dataa,
datab,
signa,
signb,
clk,
aclr,
ena,
dataout,
devclrn,
devpor
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_mac_mult";
parameter dataa_width = 18;
parameter datab_width = 18;... | 6.684394 |
module alta_crcblock (
clk,
shiftnld,
ldsrc,
crcerror,
regout
);
input clk;
input shiftnld;
input ldsrc;
output crcerror;
output regout;
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_crcblock";
parameter oscillator_div... | 7.591494 |
module alta_ram_block (
portadatain,
portaaddr,
portawe,
portbdatain,
portbaddr,
portbrewe,
clk0,
clk1,
ena0,
ena1,
clr0,
clr1,
portabyteenamasks,
portbbyteenamasks,
portaaddrstall,
portbaddrstall,
devclrn,
devpor,
portadataout,
portbdataou... | 8.129447 |
module alta_jtag (
tdouser,
tmsutap,
tckutap,
tdiutap,
shiftuser,
clkdruser,
updateuser,
runidleuser,
usr1user
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_jtag";
input tdouser;
output tmsutap;
output tck... | 6.911715 |
module alta_mac_out (
dataa,
clk,
aclr,
ena,
dataout,
devclrn,
devpor
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_mac_out";
parameter dataa_width = 36;
parameter lpm_hint = "true";
parameter output_clock = "none"... | 7.456496 |
module alta_clk_delay_ctrl (
clk,
delayctrlin,
disablecalibration,
pllcalibrateclkdelayedin,
devpor,
devclrn,
clkout
);
//parameter coord_x = 0;
//parameter coord_y = 0;
//parameter coord_z = 0;
parameter lpm_type = "alta_clk_delay_ctrl";
parameter behavioral_sim_delay = 0;
... | 6.922885 |
module alta_dio (
padio,
datain,
datainh,
oe,
outclk,
outclkena,
inclk,
inclkena,
areset,
sreset,
combout,
regout,
devclrn,
devpor,
devoe,
differentialin,
differentialout,
linkin,
linkout
);
inout padio;
input datain, datainh, oe, outclk, ... | 6.509055 |
module alta_mult (
Clk,
ClkEn,
AsyncReset,
SignA,
SignB,
DataInA0,
DataInB0,
DataInA1,
DataInB1,
DataOut0,
DataOut1,
devpor,
devclrn,
devoe
);
input Clk, ClkEn, AsyncReset;
input SignA, SignB;
input [8:0] DataInA0, DataInB0, DataInA1, DataInB1;
output [17:... | 6.514713 |
module alta_i2c (
Clk,
Rst,
WrRdn,
Strobe,
Sdai,
Scli,
DataIn,
Address,
Wakeup,
Irq,
Ack,
Sdao,
Sclo,
DataOut,
devpor,
devclrn,
devoe
);
input Clk, Rst;
input WrRdn, Strobe;
input Sdai, Scli;
input [7:0] DataIn;
input [7:0] Address;
output ... | 8.182431 |
module alta_spi (
Clk,
Rst,
WrRdn,
Strobe,
DataIn,
Address,
Mi,
Si,
Scki,
Csi,
Wakeup,
Irq,
Ack,
So,
Soe,
Mo,
Moe,
Scko,
Sckoe,
Cso,
Csoe,
DataOut,
devpor,
devclrn,
devoe
);
input Clk, Rst;
input WrRdn, Strobe;
inp... | 6.884698 |
module alta_irda (
ir_clk,
ir_reset,
cal_en,
tia_reset,
pu_ivref,
pu_pga,
pu_dac,
vip,
vin,
irx_data,
cal_ready,
dac_cal_reg,
devpor,
devclrn,
devoe
);
input ir_clk;
input ir_reset;
input cal_en;
input pu_ivref;
input pu_pga;
input pu_dac;
input ... | 6.503688 |
module alta_pllv (
clkin,
clkfb,
pllen,
resetn,
clkout0en,
clkout1en,
clkout2en,
clkout3en,
clkout4en,
clkout0,
clkout1,
clkout2,
clkout3,
clkout4,
clkfbout,
lock,
devpor,
devclrn,
devoe
);
input clkin;
input clkfb;
input pllen;
input r... | 7.257119 |
module alta_pllve (
clkin,
clkfb,
pfden,
resetn,
phasecounterselect,
phaseupdown,
phasestep,
scanclk,
scanclkena,
scandata,
configupdate,
scandataout,
scandone,
phasedone,
clkout0,
clkout1,
clkout2,
clkout3,
clkout4,
clkfbout,
lock,
... | 7.608924 |
module alta_oct (
clkusr,
rstnusr,
octdone,
octdoneuser,
rupcompout,
rdncompout,
rupoctcalnout,
rdnoctcalnout
);
input clkusr, rstnusr;
output octdone, octdoneuser;
output rupcompout, rdncompout;
output rupoctcalnout, rdnoctcalnout;
parameter OCT_CLKDIV = 2'b00;
parameter OC... | 7.44494 |
module alta_rv32 (
sys_clk,
mem_ahb_hready,
mem_ahb_hreadyout,
mem_ahb_htrans,
mem_ahb_hsize,
mem_ahb_hburst,
mem_ahb_hwrite,
mem_ahb_haddr,
mem_ahb_hwdata,
mem_ahb_hresp,
mem_ahb_hrdata,
slave_ahb_hsel,
slave_ahb_hready,
slave_ahb_hreadyout,
slave_ahb_htrans,... | 7.267946 |
module alta_adc (
devpor,
devclrn,
devoe,
enb,
sclk,
insel,
stop,
db,
eoc
);
input devclrn, devpor, devoe;
input enb, sclk, stop;
input [4:0] insel;
output [11:0] db;
output eoc;
endmodule
| 6.628961 |
module alta_cmp (
devpor,
devclrn,
devoe,
enb1,
imsel1,
ipsel1,
hyst1,
mode1,
enb2,
imsel2,
ipsel2,
hyst2,
mode2,
out1,
out2,
stop
);
input devclrn, devpor, devoe;
input enb1, enb2, hyst1, hyst2, mode1, mode2, stop;
input [2:0] imsel1, imsel2;
inpu... | 6.506983 |
module altddio_in
#(
parameter WIDTH=1
)
(
`IOB_INPUT(inclock, 1),
`IOB_OUTPUT(dataout_l, WIDTH),
`IOB_OUTPUT(dataout_h, WIDTH),
`IOB_INPUT(datain, WIDTH)
);
`IOB_VAR(dataout_l_reg, WIDTH)
`IOB_VAR(dataout_h_reg, WIDTH)
always @(posedge inclock)
dataout_h_reg <= datain;
... | 7.30907 |
module altddio_out
#(
parameter WIDTH=1
)
(
`IOB_INPUT(outclock, 1),
`IOB_INPUT(datain_l, WIDTH),
`IOB_INPUT(datain_h, WIDTH),
`IOB_OUTPUT(dataout, WIDTH)
);
`IOB_VAR(datain_l_reg, WIDTH)
`IOB_VAR(datain_h_reg, WIDTH)
always @(posedge outclock)
datain_h_reg <= datain_h;
... | 7.581103 |
module AlteraDivider (
denom,
numer,
quotient,
remain
);
input [15:0] denom;
input [31:0] numer;
output [31:0] quotient;
output [15:0] remain;
wire [31:0] sub_wire0;
wire [15:0] sub_wire1;
wire [31:0] quotient = sub_wire0[31:0];
wire [15:0] remain = sub_wire1[15:0];
lpm_divide LPM_D... | 7.946487 |
module AlteraDivider (
denom,
numer,
quotient,
remain
);
input [15:0] denom;
input [31:0] numer;
output [31:0] quotient;
output [15:0] remain;
endmodule
| 7.946487 |
module AlteraMultiplier (
dataa,
datab,
result
);
input [15:0] dataa;
input [15:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
lpm_mult lpm_mult_component (
.dataa(dataa),
.datab(datab),
.result(sub_wire0),
.aclr(1'b0),
... | 6.542651 |
module AlteraMultiplier (
dataa,
datab,
result
);
input [15:0] dataa;
input [15:0] datab;
output [31:0] result;
endmodule
| 6.542651 |
module AlteraRAM8Kx8 (
address,
clock,
data,
wren,
q);
input [12:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire ... | 6.559793 |
module AlteraRAM8Kx8 (
address,
clock,
data,
wren,
q
);
input [12:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.559793 |
module AlteraRAM_64Kx8 (
address,
clock,
data,
wren,
q
);
input [15:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:... | 6.765616 |
module AlteraRAM_64Kx8 (
address,
clock,
data,
wren,
q
);
input [15:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
... | 6.765616 |
module altera_asmi_rom (
input wire [23:0] addr, // addr.addr
output wire busy, // busy.busy
input wire clkin, // clkin.clk
output wire data_valid, // data_valid.data_valid
output wire [ 7:0] dataout, // dataout.dataout
input w... | 6.859843 |
module altera_asmi_rom (
clkin,
read,
rden,
addr,
reset,
dataout,
busy,
data_valid
);
input clkin;
input read;
input rden;
input [23:0] addr;
input reset;
output [7:0] dataout;
output busy;
output data_valid;
endmodule
| 6.859843 |
module altera_avalon_i2c_fifo #(
parameter DSIZE = 8,
parameter FIFO_DEPTH = 256,
parameter FIFO_DEPTH_LOG2 = 8,
parameter LATENCY = 2
) (
input clk,
input rst_n,
input s_rst,
input [DSIZE-1:0] wdata,
input put,
input ge... | 7.767945 |
module altera_avalon_i2c_spksupp (
input clk,
input rst_n,
input [7:0] spike_len,
input sda_in,
input scl_in,
output sda_int,
output scl_int
);
// Status Register bit definition
// wires & registers declaration
reg [7:0] scl_spike_cnt;
reg... | 7.767945 |
module altera_avalon_i2c_txout (
input clk,
input rst_n,
input [15:0] sda_hold,
input start_sda_out,
input restart_sda_out,
input stop_sda_out,
input mst_tx_sda_out,
input mst_rx_sda_out,
input restart_scl_out,
input ... | 7.767945 |
module altera_avalon_jtag_uart_2pkhqydp_log_module (
// inputs:
clk,
data,
strobe,
valid
);
input clk;
input [7:0] data;
input strobe;
input valid;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
reg [31:0] text_handle; // for $fopen
initial text_handle = $fop... | 7.767945 |
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