code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module altera_pli_streaming (
clk,
reset_n,
// source out
source_valid,
source_data,
source_ready,
// sink in
sink_valid,
sink_data,
sink_ready,
// resetrequest
resetrequest
);
parameter PLI_PORT = 50000;
parameter PURPOSE = 0;
input clk;
input reset_n;
output reg source_valid;
output reg [7 : 0] source_data;
input source_ready;
input sink_valid;
input [7 : 0] sink_data;
output reg sink_ready;
output reg resetrequest;
//synthesis translate_off
reg pli_out_valid;
reg pli_in_ready;
reg [7 : 0] pli_out_data;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
pli_out_valid <= 0;
pli_out_data <= 'b0;
pli_in_ready <= 0;
end else begin
`ifdef MODEL_TECH
$do_transaction(PLI_PORT, pli_out_valid, source_ready, pli_out_data, sink_valid,
pli_in_ready, sink_data);
`endif
end
end
//synthesis translate_on
wire [7:0] jtag_source_data;
wire jtag_source_valid;
wire jtag_sink_ready;
wire jtag_resetrequest;
altera_jtag_dc_streaming #(
.PURPOSE(PURPOSE)
) jtag_dc_streaming (
.clk(clk),
.reset_n(reset_n),
.source_data(jtag_source_data),
.source_valid(jtag_source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(jtag_sink_ready),
.resetrequest(jtag_resetrequest)
);
always @* begin
source_valid = jtag_source_valid;
source_data = jtag_source_data;
sink_ready = jtag_sink_ready;
resetrequest = jtag_resetrequest;
//synthesis translate_off
source_valid = pli_out_valid;
source_data = pli_out_data;
sink_ready = pli_in_ready;
resetrequest = 0;
//synthesis translate_on
end
endmodule
| 7.509563 |
module self_reset (
input wire mgmt_reset,
input wire clk,
output wire reset,
output wire init_reset
);
localparam RESET_COUNTER_VALUE = 3'd2;
localparam INITIAL_WAIT_VALUE = 9'd340;
reg [9:0] counter;
reg local_reset;
reg usr_mode_init_wait;
initial begin
local_reset = 1'b1;
counter = 0;
usr_mode_init_wait = 0;
end
always @(posedge clk) begin
if (mgmt_reset) begin
counter <= 0;
end else begin
if (!usr_mode_init_wait) begin
if (counter == INITIAL_WAIT_VALUE) begin
local_reset <= 0;
usr_mode_init_wait <= 1'b1;
counter <= 0;
end else begin
counter <= counter + 1'b1;
end
end else begin
if (counter == RESET_COUNTER_VALUE) local_reset <= 0;
else counter <= counter + 1'b1;
end
end
end
assign reset = mgmt_reset | local_reset;
assign init_reset = local_reset;
endmodule
| 7.046284 |
module dprio_mux (
// Inputs from init block
input [ 5:0] init_dprio_address,
input init_dprio_read,
input [ 1:0] init_dprio_byteen,
input init_dprio_write,
input [15:0] init_dprio_writedata,
input init_atpgmode,
input init_mdio_dis,
input init_scanen,
input init_ser_shift_load,
input dprio_init_done,
// Inputs from avmm master
input [ 5:0] avmm_dprio_address,
input avmm_dprio_read,
input [ 1:0] avmm_dprio_byteen,
input avmm_dprio_write,
input [15:0] avmm_dprio_writedata,
input avmm_atpgmode,
input avmm_mdio_dis,
input avmm_scanen,
input avmm_ser_shift_load,
// Outputs to fpll
output [ 5:0] dprio_address,
output dprio_read,
output [ 1:0] dprio_byteen,
output dprio_write,
output [15:0] dprio_writedata,
output atpgmode,
output mdio_dis,
output scanen,
output ser_shift_load
);
assign dprio_address = dprio_init_done ? avmm_dprio_address : init_dprio_address;
assign dprio_read = dprio_init_done ? avmm_dprio_read : init_dprio_read;
assign dprio_byteen = dprio_init_done ? avmm_dprio_byteen : init_dprio_byteen;
assign dprio_write = dprio_init_done ? avmm_dprio_write : init_dprio_write;
assign dprio_writedata = dprio_init_done ? avmm_dprio_writedata : init_dprio_writedata;
assign atpgmode = init_atpgmode;
assign scanen = init_scanen;
assign mdio_dis = init_mdio_dis;
assign ser_shift_load = init_ser_shift_load;
endmodule
| 7.63543 |
module generic_lcell_comb #(
//parameter
parameter family = "Stratix V",
parameter lut_mask = 64'hAAAAAAAAAAAAAAAA,
parameter dont_touch = "on"
) (
input dataa,
input datab,
input datac,
input datad,
input datae,
input dataf,
output combout
);
generate
if (family == "Stratix V") begin
stratixv_lcell_comb lcell_inst (
.dataa (dataa),
.datab (datab),
.datac (datac),
.datad (datad),
.datae (datae),
.dataf (dataf),
.combout(combout)
);
defparam lcell_inst.lut_mask = lut_mask; defparam lcell_inst.dont_touch = dont_touch;
end else if (family == "Arria V") begin
arriav_lcell_comb lcell_inst (
.dataa (dataa),
.datab (datab),
.datac (datac),
.datad (datad),
.datae (datae),
.dataf (dataf),
.combout(combout)
);
defparam lcell_inst.lut_mask = lut_mask; defparam lcell_inst.dont_touch = dont_touch;
end else if (family == "Arria V GZ") begin
arriavgz_lcell_comb lcell_inst (
.dataa (dataa),
.datab (datab),
.datac (datac),
.datad (datad),
.datae (datae),
.dataf (dataf),
.combout(combout)
);
defparam lcell_inst.lut_mask = lut_mask; defparam lcell_inst.dont_touch = dont_touch;
end else if (family == "Cyclone V") begin
cyclonev_lcell_comb lcell_inst (
.dataa (dataa),
.datab (datab),
.datac (datac),
.datad (datad),
.datae (datae),
.dataf (dataf),
.combout(combout)
);
defparam lcell_inst.lut_mask = lut_mask; defparam lcell_inst.dont_touch = dont_touch;
end
endgenerate
endmodule
| 7.311042 |
module altera_pll_wb_clkgen #(
parameter INPUT_FREQUENCY,
parameter WB_CLK_FREQUENCY
) (
// Main clocks in, depending on board
input sys_clk_pad_i,
// Asynchronous, active low reset in
input rst_n_pad_i,
// Input reset - through a buffer, asynchronous
output async_rst_o,
// Wishbone clock and reset out
output wb_clk_o,
output wb_rst_o
);
// First, deal with the asychronous reset
wire async_rst;
wire async_rst_n;
assign async_rst_n = rst_n_pad_i;
assign async_rst = ~async_rst_n;
// Everyone likes active-high reset signals...
assign async_rst_o = ~async_rst_n;
//
// Declare synchronous reset wires here
//
// An active-low synchronous reset signal (usually a PLL lock signal)
wire sync_rst_n;
wire pll_lock;
wrapped_altera_pll #(
.INPUT_FREQUENCY(INPUT_FREQUENCY),
.OUTPUT_CLOCK0_FREQUENCY(WB_CLK_FREQUENCY)
) wrapped_altera_pll (
.refclk(sys_clk_pad_i),
.rst(async_rst),
.outclk_0(wb_clk_o),
.locked(pll_lock)
);
assign sync_rst_n = pll_lock;
//
// Reset generation
//
// Reset generation for wishbone
reg [15:0] wb_rst_shr;
always @(posedge wb_clk_o or posedge async_rst)
if (async_rst) wb_rst_shr <= 16'hffff;
else wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
assign wb_rst_o = wb_rst_shr[15];
endmodule
| 10.244358 |
module altera_pmon_counters #(
parameter BC_W = 5
) (
input if_clock,
input if_reset,
input if_read,
input if_write,
input [BC_W-1:0] if_burstcount,
input if_waitrequest,
input if_readdatavalid,
input [1:0] address,
input toglin,
output reg toglout,
output reg [31:0] count_data
);
reg [31:0] read_xfrs;
reg [31:0] read_cycles;
reg [31:0] write_xfrs;
reg [31:0] write_cycles;
reg [31:0] selected_counter;
reg [15:0] readcount;
wire toglin_s;
altera_std_synchronizer #(
.depth(2)
) sync_toglin (
.clk (if_clock),
.reset_n(~if_reset),
.din (toglin),
.dout (toglin_s)
);
always @(posedge if_clock or posedge if_reset) begin
if (if_reset) begin
toglout <= 0;
count_data <= 32'h0;
end else begin
toglout <= toglin_s;
if (toglout != toglin_s) count_data <= selected_counter;
end
end
always @(*) begin
case (address)
2'h0: selected_counter = read_xfrs;
2'h1: selected_counter = read_cycles;
2'h2: selected_counter = write_xfrs;
2'h3: selected_counter = write_cycles;
endcase
end
//read xfrs counter
always @(posedge if_clock or posedge if_reset) begin
if (if_reset) read_xfrs <= 0;
else if (if_readdatavalid) read_xfrs <= read_xfrs + 1'b1;
end
//readcount indicates how many readdatavalid cycles are to come
always @(posedge if_clock or posedge if_reset) begin
if (if_reset) readcount <= 16'h0; //smaller???
else if (if_read && ~if_waitrequest) begin
if (if_readdatavalid) readcount <= readcount + if_burstcount - 1'b1;
else readcount <= readcount + if_burstcount;
end else if (if_readdatavalid) readcount <= readcount - 1'b1;
end
//read cycles counter
always @(posedge if_clock or posedge if_reset) begin
if (if_reset) read_cycles <= 32'h0;
else if (if_read || (readcount > 16'h0)) read_cycles <= read_cycles + 1'b1;
end
//write xfrs counter
always @(posedge if_clock or posedge if_reset) begin
if (if_reset) write_xfrs <= 0;
else if (if_write && !if_waitrequest) write_xfrs <= write_xfrs + 1'b1;
end
//write burst state tracker
localparam WIDLE = 1'b0, WIP = 1'b1;
reg wstate, nx_wstate;
reg [10:0] wburstcnt;
reg load, decr, write_in_progress;
always @(posedge if_clock or posedge if_reset) begin
if (if_reset) begin
wstate <= WIDLE;
wburstcnt <= 11'h0;
end else begin
wstate <= nx_wstate;
if (load) begin
if (~if_waitrequest) wburstcnt <= if_burstcount - 1'b1;
else wburstcnt <= if_burstcount;
end else if (decr) wburstcnt <= wburstcnt - 1'b1;
end
end
wire newburst = (wburstcnt == 11'h0);
always @(*) begin
nx_wstate = wstate;
decr = 1'b0;
load = 1'b0;
case (wstate)
WIDLE: begin
write_in_progress = 1'b0;
if (if_write && newburst) begin
load = 1'b1;
write_in_progress = 1'b1;
if (if_waitrequest || (if_burstcount > {{BC_W - 1{1'b0}}, 1'b1})) nx_wstate = WIP;
end
end
WIP: begin //write in progress
write_in_progress = 1'b1;
if (if_write && ~if_waitrequest) begin //valid write cycle
decr = 1'b1;
if (wburstcnt == 11'h1) nx_wstate = WIDLE;
end
end
endcase
end
//write cycles counter (cycles used in completing a write burst, from first
//write command, to last accepted write cycle of burst
always @(posedge if_clock or posedge if_reset) begin
if (if_reset) write_cycles <= 32'h0;
else if (write_in_progress) write_cycles <= write_cycles + 1'b1;
end
endmodule
| 7.025613 |
module altera_pmon_count_csr (
input avs_clock,
input avs_reset,
input avs_read,
input [ 3:2] avs_address,
output reg avs_waitrequest,
output reg [31:0] avs_readdata,
output reg toglout,
output reg [ 1:0] address,
input toglin,
input [31:0] count_data
);
reg togl;
wire toglin_s;
reg toglin_sa;
always @(posedge avs_clock or posedge avs_reset) begin
if (avs_reset) begin
toglout <= 1'b0;
address <= 2'h0;
end else begin
if (togl) begin
toglout <= !toglout;
address <= avs_address;
end
end
end
altera_std_synchronizer #(
.depth(2)
) sync_toglin (
.clk (avs_clock),
.reset_n(~avs_reset),
.din (toglin),
.dout (toglin_s)
);
localparam IDLE = 1'b0, RIP = 1'b1;
reg state, nxstate;
always @(posedge avs_clock or posedge avs_reset) begin
if (avs_reset) begin
state <= IDLE;
avs_waitrequest <= 1'b1;
toglin_sa <= 1'b0;
end else begin
state <= nxstate;
toglin_sa <= toglin_s;
if (toglin_s != toglin_sa) avs_waitrequest <= 1'b0;
else avs_waitrequest <= 1'b1;
end
end
always @(*) begin
nxstate = state;
togl = 1'b0;
avs_readdata = 32'h0;
case (state)
IDLE: begin
if (avs_read) begin
nxstate = RIP;
togl = 1'b1;
end
end
RIP: begin //read in progress
avs_readdata = count_data;
if (~avs_waitrequest) nxstate = IDLE;
end
endcase
end
endmodule
| 7.025613 |
module carry (
in,
out
);
input in;
output out;
assign out = in;
endmodule
| 6.67808 |
module soft (in, out);
input in;
output out;
assign out = in;
endmodule
| 6.665932 |
module row_global (
in,
out
);
input in;
output out;
assign out = in;
endmodule
| 6.744872 |
module latch (
d,
ena,
q
);
input d, ena;
output q;
reg q;
initial q = 1'b0;
always @(d or ena) begin
if (ena) q <= d;
end
endmodule
| 6.780285 |
module dlatch (
d,
ena,
clrn,
prn,
q
);
input d, ena, clrn, prn;
output q;
reg q;
initial q = 1'b0;
always @(d or ena or clrn or prn) begin
if (clrn == 1'b0) q <= 1'b0;
else if (prn == 1'b0) q <= 1'b1;
else if (ena) q <= d;
end
endmodule
| 6.890541 |
module prim_gdff (
q,
d,
clk,
ena,
clr,
pre,
ald,
adt,
sclr,
sload
);
input d, clk, ena, clr, pre, ald, adt, sclr, sload;
output q;
reg q;
reg clk_pre;
initial q = 1'b0;
always @(clk or clr or pre or ald or adt) begin
if (clr == 1'b1) q <= 1'b0;
else if (pre == 1'b1) q <= 1'b1;
else if (ald == 1'b1) q <= adt;
else if ((clk == 1'b1) && (clk_pre == 1'b0)) begin
if (ena == 1'b1) begin
if (sclr == 1'b1) q <= 1'b0;
else if (sload == 1'b1) q <= adt;
else q <= d;
end
end
clk_pre <= clk;
end
endmodule
| 6.561297 |
module dff (
d,
clk,
clrn,
prn,
q
);
input d, clk, clrn, prn;
output q;
wire q;
tri1 prn, clrn;
prim_gdff inst (
q,
d,
clk,
1'b1,
!clrn,
!prn,
1'b0,
1'b0,
1'b0,
1'b0
);
endmodule
| 7.361383 |
module dffea (
d,
clk,
ena,
clrn,
prn,
aload,
adata,
q
);
input d, clk, ena, clrn, prn, aload, adata;
output q;
wire q;
tri0 aload;
tri1 prn, clrn, ena;
reg stalled_adata;
initial begin
stalled_adata = adata;
end
always @(adata) begin
#1 stalled_adata = adata;
end
prim_gdff inst (
q,
d,
clk,
ena,
!clrn,
!prn,
aload,
stalled_adata,
1'b0,
1'b0
);
endmodule
| 6.622625 |
module tff (
t,
clk,
clrn,
prn,
q
);
input t, clk, clrn, prn;
output q;
wire q;
tri1 prn, clrn;
prim_gtff inst (
q,
t,
clk,
1'b1,
!clrn,
!prn
);
endmodule
| 6.565161 |
module jkff (
j,
k,
clk,
clrn,
prn,
q
);
input j, k, clk, clrn, prn;
output q;
wire q;
tri1 prn, clrn;
prim_gjkff inst (
q,
j,
k,
clk,
1'b1,
!clrn,
!prn
);
endmodule
| 6.559482 |
module jkffe (
j,
k,
clk,
ena,
clrn,
prn,
q
);
input j, k, clk, ena, clrn, prn;
output q;
wire q;
tri1 prn, clrn, ena;
prim_gjkff inst (
q,
j,
k,
clk,
ena,
!clrn,
!prn
);
endmodule
| 6.564724 |
module alt_inbuf (
i,
o
);
input i;
output o;
parameter io_standard = "NONE";
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_inbuf";
assign o = i;
endmodule
| 6.532949 |
module alt_outbuf (
i,
o
);
input i;
output o;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter slow_slew_rate = "NONE";
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_outbuf";
assign o = i;
endmodule
| 7.424847 |
module alt_outbuf_tri (
i,
oe,
o
);
input i;
input oe;
output o;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter slow_slew_rate = "NONE";
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_outbuf_tri";
bufif1 (o, i, oe);
endmodule
| 8.389274 |
module alt_iobuf (
i,
oe,
io,
o
);
input i;
input oe;
inout io;
output o;
reg o;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter slow_slew_rate = "NONE";
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter input_termination = "NONE";
parameter output_termination = "NONE";
parameter lpm_type = "alt_iobuf";
always @(io) begin
o = io;
end
assign io = (oe == 1) ? i : 1'bz;
endmodule
| 7.605409 |
module alt_inbuf_diff (
i,
ibar,
o
);
input i;
input ibar;
output o;
parameter io_standard = "NONE";
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_inbuf_diff";
reg out_tmp;
always @(i or ibar) begin
casex ({
i, ibar
})
2'b00: out_tmp = 1'bx;
2'b01: out_tmp = 1'b0;
2'b10: out_tmp = 1'b1;
2'b11: out_tmp = 1'bx;
default: out_tmp = 1'bx;
endcase
end
assign o = out_tmp;
endmodule
| 6.599161 |
module alt_outbuf_diff (
i,
o,
obar
);
input i;
output o;
output obar;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_outbuf_diff";
assign o = i;
assign obar = !i;
endmodule
| 8.051467 |
module alt_outbuf_tri_diff (
i,
oe,
o,
obar
);
input i;
input oe;
output o;
output obar;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_outbuf_tri_diff";
bufif1 (o, i, oe);
bufif1 (obar, !i, oe);
endmodule
| 8.389274 |
module alt_iobuf_diff (
i,
oe,
io,
iobar,
o
);
input i;
input oe;
inout io;
inout iobar;
output o;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter input_termination = "NONE";
parameter output_termination = "NONE";
parameter lpm_type = "alt_iobuf_diff";
reg out_tmp;
always @(io or iobar) begin
casex ({
io, iobar
})
2'b00: out_tmp = 1'bx;
2'b01: out_tmp = 1'b0;
2'b10: out_tmp = 1'b1;
2'b11: out_tmp = 1'bx;
default: out_tmp = 1'bx;
endcase
end
assign o = out_tmp;
assign io = (oe === 1'b1) ? i : (oe === 1'b0) ? 1'bz : 1'bx;
assign iobar = (oe == 1'b1) ? !i : (oe == 1'b0) ? 1'bz : 1'bx;
endmodule
| 7.671053 |
module alt_bidir_diff (
oe,
bidirin,
io,
iobar
);
input oe;
inout bidirin;
inout io;
inout iobar;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter input_termination = "NONE";
parameter output_termination = "NONE";
parameter lpm_type = "alt_bidir_diff";
reg out_tmp;
always @(io or iobar) begin
casex ({
io, iobar
})
2'b00: out_tmp = 1'bx;
2'b01: out_tmp = 1'b0;
2'b10: out_tmp = 1'b1;
2'b11: out_tmp = 1'bx;
default: out_tmp = 1'bx;
endcase
end
assign bidirin = (oe === 1'b0) ? out_tmp : (oe === 1'b1) ? 1'bz : 1'bx;
assign io = (oe === 1'b1) ? bidirin : (oe === 1'b0) ? 1'bz : 1'bx;
assign iobar = (oe == 1'b1) ? !bidirin : (oe == 1'b0) ? 1'bz : 1'bx;
endmodule
| 6.617503 |
module carry (
in,
out
);
input in;
output out;
assign out = in;
endmodule
| 6.67808 |
module soft (in, out);
input in;
output out;
assign out = in;
endmodule
| 6.665932 |
module row_global (
in,
out
);
input in;
output out;
assign out = in;
endmodule
| 6.744872 |
module latch (
d,
ena,
q
);
input d, ena;
output q;
reg q;
initial q = 1'b0;
always @(d or ena) begin
if (ena) q <= d;
end
endmodule
| 6.780285 |
module dlatch (
d,
ena,
clrn,
prn,
q
);
input d, ena, clrn, prn;
output q;
reg q;
initial q = 1'b0;
always @(d or ena or clrn or prn) begin
if (clrn == 1'b0) q <= 1'b0;
else if (prn == 1'b0) q <= 1'b1;
else if (ena) q <= d;
end
endmodule
| 6.890541 |
module prim_gdff (
q,
d,
clk,
ena,
clr,
pre,
ald,
adt,
sclr,
sload
);
input d, clk, ena, clr, pre, ald, adt, sclr, sload;
output q;
reg q;
reg clk_pre;
initial q = 1'b0;
always @(clk or clr or pre or ald or adt) begin
if (clr == 1'b1) q <= 1'b0;
else if (pre == 1'b1) q <= 1'b1;
else if (ald == 1'b1) q <= adt;
else if ((clk == 1'b1) && (clk_pre == 1'b0)) begin
if (ena == 1'b1) begin
if (sclr == 1'b1) q <= 1'b0;
else if (sload == 1'b1) q <= adt;
else q <= d;
end
end
clk_pre <= clk;
end
endmodule
| 6.561297 |
module dff (
d,
clk,
clrn,
prn,
q
);
input d, clk, clrn, prn;
output q;
wire q;
tri1 prn, clrn;
prim_gdff inst (
q,
d,
clk,
1'b1,
!clrn,
!prn,
1'b0,
1'b0,
1'b0,
1'b0
);
endmodule
| 7.361383 |
module dffea (
d,
clk,
ena,
clrn,
prn,
aload,
adata,
q
);
input d, clk, ena, clrn, prn, aload, adata;
output q;
wire q;
tri0 aload;
tri1 prn, clrn, ena;
reg stalled_adata;
initial begin
stalled_adata = adata;
end
always @(adata) begin
#1 stalled_adata = adata;
end
prim_gdff inst (
q,
d,
clk,
ena,
!clrn,
!prn,
aload,
stalled_adata,
1'b0,
1'b0
);
endmodule
| 6.622625 |
module tff (
t,
clk,
clrn,
prn,
q
);
input t, clk, clrn, prn;
output q;
wire q;
tri1 prn, clrn;
prim_gtff inst (
q,
t,
clk,
1'b1,
!clrn,
!prn
);
endmodule
| 6.565161 |
module jkff (
j,
k,
clk,
clrn,
prn,
q
);
input j, k, clk, clrn, prn;
output q;
wire q;
tri1 prn, clrn;
prim_gjkff inst (
q,
j,
k,
clk,
1'b1,
!clrn,
!prn
);
endmodule
| 6.559482 |
module jkffe (
j,
k,
clk,
ena,
clrn,
prn,
q
);
input j, k, clk, ena, clrn, prn;
output q;
wire q;
tri1 prn, clrn, ena;
prim_gjkff inst (
q,
j,
k,
clk,
ena,
!clrn,
!prn
);
endmodule
| 6.564724 |
module alt_inbuf (
i,
o
);
input i;
output o;
parameter io_standard = "NONE";
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_inbuf";
assign o = i;
endmodule
| 6.532949 |
module alt_outbuf (
i,
o
);
input i;
output o;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter slow_slew_rate = "NONE";
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_outbuf";
assign o = i;
endmodule
| 7.424847 |
module alt_outbuf_tri (
i,
oe,
o
);
input i;
input oe;
output o;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter slow_slew_rate = "NONE";
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_outbuf_tri";
bufif1 (o, i, oe);
endmodule
| 8.389274 |
module alt_iobuf (
i,
oe,
io,
o
);
input i;
input oe;
inout io;
output o;
reg o;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter slow_slew_rate = "NONE";
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter input_termination = "NONE";
parameter output_termination = "NONE";
parameter lpm_type = "alt_iobuf";
always @(io) begin
o = io;
end
assign io = (oe == 1) ? i : 1'bz;
endmodule
| 7.605409 |
module alt_inbuf_diff (
i,
ibar,
o
);
input i;
input ibar;
output o;
parameter io_standard = "NONE";
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_inbuf_diff";
reg out_tmp;
always @(i or ibar) begin
casex ({
i, ibar
})
2'b00: out_tmp = 1'bx;
2'b01: out_tmp = 1'b0;
2'b10: out_tmp = 1'b1;
2'b11: out_tmp = 1'bx;
default: out_tmp = 1'bx;
endcase
end
assign o = out_tmp;
endmodule
| 6.599161 |
module alt_outbuf_diff (
i,
o,
obar
);
input i;
output o;
output obar;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_outbuf_diff";
assign o = i;
assign obar = !i;
endmodule
| 8.051467 |
module alt_outbuf_tri_diff (
i,
oe,
o,
obar
);
input i;
input oe;
output o;
output obar;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_outbuf_tri_diff";
bufif1 (o, i, oe);
bufif1 (obar, !i, oe);
endmodule
| 8.389274 |
module alt_iobuf_diff (
i,
oe,
io,
iobar,
o
);
input i;
input oe;
inout io;
inout iobar;
output o;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter input_termination = "NONE";
parameter output_termination = "NONE";
parameter lpm_type = "alt_iobuf_diff";
reg out_tmp;
always @(io or iobar) begin
casex ({
io, iobar
})
2'b00: out_tmp = 1'bx;
2'b01: out_tmp = 1'b0;
2'b10: out_tmp = 1'b1;
2'b11: out_tmp = 1'bx;
default: out_tmp = 1'bx;
endcase
end
assign o = out_tmp;
assign io = (oe === 1'b1) ? i : (oe === 1'b0) ? 1'bz : 1'bx;
assign iobar = (oe == 1'b1) ? !i : (oe == 1'b0) ? 1'bz : 1'bx;
endmodule
| 7.671053 |
module alt_bidir_diff (
oe,
bidirin,
io,
iobar
);
input oe;
inout bidirin;
inout io;
inout iobar;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter input_termination = "NONE";
parameter output_termination = "NONE";
parameter lpm_type = "alt_bidir_diff";
reg out_tmp;
always @(io or iobar) begin
casex ({
io, iobar
})
2'b00: out_tmp = 1'bx;
2'b01: out_tmp = 1'b0;
2'b10: out_tmp = 1'b1;
2'b11: out_tmp = 1'bx;
default: out_tmp = 1'bx;
endcase
end
assign bidirin = (oe === 1'b0) ? out_tmp : (oe === 1'b1) ? 1'bz : 1'bx;
assign io = (oe === 1'b1) ? bidirin : (oe === 1'b0) ? 1'bz : 1'bx;
assign iobar = (oe == 1'b1) ? !bidirin : (oe == 1'b0) ? 1'bz : 1'bx;
endmodule
| 6.617503 |
module altera_primitive_dualram_512bit_16word (
byteena_a,
clock,
data,
rdaddress,
wraddress,
wren,
q);
input [63:0] byteena_a;
input clock;
input [511:0] data;
input [3:0] rdaddress;
input [3:0] wraddress;
input wren;
output [511:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [63:0] byteena_a;
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [511:0] sub_wire0;
wire [511:0] q = sub_wire0[511:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.byteena_a (byteena_a),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({512{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16,
altsyncram_component.numwords_b = 16,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 4,
altsyncram_component.widthad_b = 4,
altsyncram_component.width_a = 512,
altsyncram_component.width_b = 512,
altsyncram_component.width_byteena_a = 64;
endmodule
| 7.310839 |
module altera_primitive_ram_64bit_32768word (
address,
byteena,
clock,
data,
wren,
q);
input [14:0] address;
input [7:0] byteena;
input clock;
input [63:0] data;
input wren;
output [63:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [7:0] byteena;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [63:0] sub_wire0;
wire [63:0] q = sub_wire0[63:0];
altsyncram altsyncram_component (
.address_a (address),
.byteena_a (byteena),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32768,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.widthad_a = 15,
altsyncram_component.width_a = 64,
altsyncram_component.width_byteena_a = 8;
endmodule
| 7.310839 |
module altera_primitive_sync_fifo_showahead_97in_97out_32depth (
aclr,
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q,
usedw
);
input aclr;
input clock;
input [96:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [96:0] q;
output [4:0] usedw;
wire sub_wire0;
wire sub_wire1;
wire [96:0] sub_wire2;
wire [4:0] sub_wire3;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [96:0] q = sub_wire2[96:0];
wire [4:0] usedw = sub_wire3[4:0];
scfifo scfifo_component (
.aclr(aclr),
.clock(clock),
.data(data),
.rdreq(rdreq),
.sclr(sclr),
.wrreq(wrreq),
.empty(sub_wire0),
.full(sub_wire1),
.q(sub_wire2),
.usedw(sub_wire3),
.almost_empty(),
.almost_full(),
.eccstatus()
);
defparam scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Cyclone IV E", scfifo_component.lpm_numwords = 32,
scfifo_component.lpm_showahead = "ON", scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 97, scfifo_component.lpm_widthu = 5,
scfifo_component.overflow_checking = "OFF", scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
| 7.310839 |
module altera_primitive_sync_fifo_showahead_97in_97out_32depth (
aclr,
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q,
usedw
);
input aclr;
input clock;
input [96:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [96:0] q;
output [4:0] usedw;
endmodule
| 7.310839 |
module altera_reset_synchronizer #(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
) (
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate
if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
| 8.176669 |
module altera_reset_synchronizer #(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
) (
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate
if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
| 8.176669 |
module altera_reset_synchronizer_0 #(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
) (
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate
if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
| 8.176669 |
module RxD_fifo #(
parameter Dw = 72, //data_width
parameter B = 10 // buffer num
) (
din,
wr_en,
rd_en,
dout,
full,
nearly_full,
empty,
reset,
clk
);
function integer log2;
input integer number;
begin
log2 = (number <= 1) ? 1 : 0;
while (2 ** log2 < number) begin
log2 = log2 + 1;
end
end
endfunction // log2
localparam B_1 = B - 1, Bw = log2(B), DEPTHw = log2(B + 1);
localparam [Bw-1 : 0] Bint = B_1[Bw-1 : 0];
input [Dw-1:0] din; // Data in
input wr_en; // Write enable
input rd_en; // Read the next word
output reg [Dw-1:0] dout; // Data out
output full;
output nearly_full;
output empty;
input reset;
input clk;
reg [ Dw-1 : 0] queue [B-1 : 0] /* synthesis ramstyle = "no_rw_check" */;
reg [ Bw- 1 : 0] rd_ptr;
reg [ Bw- 1 : 0] wr_ptr;
reg [DEPTHw-1 : 0] depth;
// Sample the data
always @(posedge clk) begin
if (wr_en) queue[wr_ptr] <= din;
if (rd_en)
dout <=
//synthesis translate_off
//synopsys translate_off
#1
//synopsys translate_on
//synthesis translate_on
queue[rd_ptr];
end
always @(posedge clk) begin
if (reset) begin
rd_ptr <= {Bw{1'b0}};
wr_ptr <= {Bw{1'b0}};
depth <= {DEPTHw{1'b0}};
end else begin
if (wr_en) wr_ptr <= (wr_ptr == Bint) ? {Bw{1'b0}} : wr_ptr + 1'b1;
if (rd_en) rd_ptr <= (rd_ptr == Bint) ? {Bw{1'b0}} : rd_ptr + 1'b1;
if (wr_en & ~rd_en)
depth <=
//synthesis translate_off
//synopsys translate_off
#1
//synopsys translate_on
//synthesis translate_on
depth + 1'b1;
else if (~wr_en & rd_en)
depth <=
//synthesis translate_off
//synopsys translate_off
#1
//synopsys translate_on
//synthesis translate_on
depth - 1'b1;
end
end
//assign dout = queue[rd_ptr];
assign full = depth == B;
assign nearly_full = depth >= B - 1;
assign empty = depth == {DEPTHw{1'b0}};
//synthesis translate_off
//synopsys translate_off
always @(posedge clk) begin
if (~reset) begin
if (wr_en && depth == B && !rd_en)
$display(" %t: ERROR: Attempt to write to full FIFO: %m", $time);
if (rd_en && depth == {DEPTHw{1'b0}})
$display("%t: ERROR: Attempt to read an empty FIFO: %m", $time);
end //~reset
end
//synopsys translate_on
//synthesis translate_on
endmodule
| 6.524137 |
module altera_spram #(
parameter DEVICE_ID = "Stratix IV" , //
BRAM_TYPE = "M9K" , //
RAM_DO_REG = 0 , //
RAM_WIDTH = 8 , //
RAM_DEEP = 10 //
)(
input reset , //i1: reset only for mlab
input clock , //i1: single port ram clock
input wren , //i1: write enable
input [RAM_WIDTH - 1:0] wdata , //i[RAM_WIDTH]:
input [RAM_DEEP - 1:0] address , //i[RAM_WIDTH]:
input ren , //i1: read enable
output wire [RAM_WIDTH - 1:0] q //o[RAM_WIDTH]:
);
//--------------------------
// parameters
//--------------------------
localparam RAM_DOUT_REG = (RAM_DO_REG == 1) ? "CLOCK0" : "UNREGISTERED";
//--------------------------
// signals
//--------------------------
//-------------------------------------------------------------
// process
//-------------------------------------------------------------
altsyncram altsyncram_component (
.address_a (address ),
.clock0 (clock ),
.data_a (wdata ),
.rden_a (ren ),
.wren_a (wren ),
.q_a (q ),
.address_b (1'b1 ),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (clock),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.enable_ecc = "FALSE",
altsyncram_component.intended_device_family = DEVICE_ID,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2**RAM_DEEP,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = RAM_DOUT_REG,
altsyncram_component.read_during_write_mode_port_a = "OLD_DATA",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = BRAM_TYPE,
altsyncram_component.widthad_a = RAM_DEEP,
altsyncram_component.width_a = RAM_WIDTH,
altsyncram_component.width_byteena_a = 1;
endmodule
| 6.545549 |
module altera_std_synchronizer (
clk,
reset_n,
din,
dout
);
parameter depth = 3; // This value must be >= 2 !
input clk;
input reset_n;
input din;
output dout;
// QuartusII synthesis directives:
// 1. Preserve all registers ie. do not touch them.
// 2. Do not merge other flip-flops with synchronizer flip-flops.
// QuartusII TimeQuest directives:
// 1. Identify all flip-flops in this module as members of the synchronizer
// to enable automatic metastability MTBF analysis.
// 2. Cut all timing paths terminating on data input pin of the first flop din_s1.
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON; -name SDC_STATEMENT \"set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]\" "} *)
reg din_s1;
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
//synthesis translate_off
initial begin
if (depth < 2) begin
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
end
end
// the first synchronizer register is either a simple D flop for synthesis
// and non-metastable simulation or a D flop with a method to inject random
// metastable events resulting in random delay of [0,1] cycles
`ifdef __ALTERA_STD__METASTABLE_SIM
reg [31:0] RANDOM_SEED = 123456;
wire next_din_s1;
wire dout;
reg din_last;
reg random;
event metastable_event; // hook for debug monitoring
initial begin
$display("%m: Info: Metastable event injection simulation mode enabled");
end
always @(posedge clk) begin
if (reset_n == 0) random <= $random(RANDOM_SEED);
else random <= $random;
end
assign next_din_s1 = (din_last ^ din) ? random : din;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) din_last <= 1'b0;
else din_last <= din;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) din_s1 <= 1'b0;
else din_s1 <= next_din_s1;
end
`else
//synthesis translate_on
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) din_s1 <= 1'b0;
else din_s1 <= din;
end
//synthesis translate_off
`endif
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
always @(*) begin
if (reset_n && (din_last != din) && (random != din)) begin
$display("%m: Verbose Info: metastable event @ time %t", $time);
->metastable_event;
end
end
`endif
//synthesis translate_on
// the remaining synchronizer registers form a simple shift register
// of length depth-1
generate
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) dreg <= {depth - 1{1'b0}};
else dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) dreg <= {depth - 1{1'b0}};
else dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
assign dout = dreg[depth-2];
endmodule
| 7.854645 |
module altera_sync_ram_1p (
clk_i,
adr_i,
be_i,
wren_i,
dat_i,
dat_o
);
parameter AW = 10;
parameter DW = 32;
parameter INIT_MEM_FILE = "";
localparam DEPTH = (1 << AW);
input clk_i;
input [AW-1:0] adr_i;
input [(DW/8)-1:0] be_i;
input wren_i;
input [DW-1:0] dat_i;
output [DW-1:0] dat_o;
// data q is not register output
// if data q is register output,
// data is ready after 2T
altsyncram altsyncram_component (
.aclr0 (1'b0),
.aclr1 (1'b0),
.clock0 (clk_i),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.address_a (adr_i),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (be_i),
.byteena_b (1'b1),
.data_a (dat_i),
.data_b (1'b1),
.q_a (dat_o),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (wren_i),
.wren_b (1'b0),
.eccstatus ());
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = INIT_MEM_FILE,
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=SRAM0",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = DEPTH,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "OLD_DATA",
altsyncram_component.widthad_a = (AW),
altsyncram_component.width_a = (DW),
altsyncram_component.width_byteena_a = (DW/8);
endmodule
| 6.775597 |
module altera_sync_rom_1p (
clk_i,
adr_i,
dat_o
);
parameter AW = 10;
parameter DW = 32;
parameter INIT_MEM_FILE = "";
localparam DEPTH = (1 << AW);
input clk_i;
input [AW-1:0] adr_i;
output [DW-1:0] dat_o;
// data q is not register output
// if data q is register output,
// data is ready after 2T
altsyncram altsyncram_component (
.aclr0(1'b0),
.aclr1(1'b0),
.clock0(clk_i),
.clock1(1'b1),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
.address_a(adr_i),
.address_b(1'b1),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a(1'b1),
.byteena_b(1'b1),
.data_a({32{1'b1}}),
.data_b(1'b1),
.q_a(dat_o),
.q_b(),
.rden_a(1'b1),
.rden_b(1'b1),
.wren_a(1'b0),
.wren_b(1'b0),
.eccstatus()
);
defparam altsyncram_component.address_aclr_a = "NONE", altsyncram_component.clock_enable_input_a =
"BYPASS", altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = INIT_MEM_FILE, altsyncram_component.intended_device_family =
"Stratix IV", altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=ROM0",
altsyncram_component.lpm_type = "altsyncram", altsyncram_component.numwords_a = DEPTH,
altsyncram_component.operation_mode = "ROM", altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED", altsyncram_component.widthad_a = (AW),
altsyncram_component.width_a = (DW), altsyncram_component.width_byteena_a = 1;
endmodule
| 6.775597 |
module designed to retun values based for trace.
// address used is variabel size (based on number of distilers.
`default_nettype none
module altera_trace_rom #(
parameter NUM_REGS = 2,
parameter REG_VALUE_STRING = "FEDCBA9876543210", // also used as default value
parameter ADDR_WIDTH = 2,
parameter DATA_WIDTH = 32,
parameter DP_REG_VALUE_BITS = hex_string_to_vector(REG_VALUE_STRING)
)(
input wire clk,
input wire arst_n,
input wire rom_read,
input wire [ADDR_WIDTH-1:0] rom_address,
output reg [DATA_WIDTH-1:0] rom_readdata
);
function [NUM_REGS * 32 -1 : 0] hex_string_to_vector( input [NUM_REGS * 64 -1 : 0] sting_val);
begin : func_inner
reg [NUM_REGS * 32 -1 : 0] retval;
reg [7:0] char;
integer regnum;
integer nibble_num;
reg [3:0] nibble_value;
for (regnum = 0; regnum < NUM_REGS; regnum = regnum + 1) begin
for (nibble_num = 0; nibble_num < 8; nibble_num = nibble_num + 1) begin
char = sting_val[(regnum * 64) + (nibble_num * 8) +: 8];
nibble_value = 4'h0; // 4'hX; // better default is it means software is OK and gets 0 instead of a compile-time generated value
//lookup table below converts a 8 bit ASCI char into a hex nibble.
case (char)
"0" : begin nibble_value = 4'h0; end
"1" : begin nibble_value = 4'h1; end
"2" : begin nibble_value = 4'h2; end
"3" : begin nibble_value = 4'h3; end
"4" : begin nibble_value = 4'h4; end
"5" : begin nibble_value = 4'h5; end
"6" : begin nibble_value = 4'h6; end
"7" : begin nibble_value = 4'h7; end
"8" : begin nibble_value = 4'h8; end
"9" : begin nibble_value = 4'h9; end
"A" : begin nibble_value = 4'hA; end
"B" : begin nibble_value = 4'hB; end
"C" : begin nibble_value = 4'hC; end
"D" : begin nibble_value = 4'hD; end
"E" : begin nibble_value = 4'hE; end
"F" : begin nibble_value = 4'hF; end
default : begin
//synthesis translate_off
$error("function can not decode the ASCII for 0x:%2x", char);
//synthesis translate_on
end
endcase
retval[(regnum * 32) + (nibble_num * 4)+:4] = nibble_value[0+:4];
end // nibble exteraction
end
hex_string_to_vector = retval;
//return(retval);
end
endfunction
// TODO: are we better off making read_addr only update when rom_read == 1'b1 it may have toggle rate implications..
(* dont_merge *) reg [ADDR_WIDTH-1:0] read_addr;
(* dont_merge *) reg rom_read_1t;
always @(posedge clk or negedge arst_n) begin
if (1'b0 == arst_n) begin
read_addr <= {ADDR_WIDTH{1'b0}};
rom_readdata <= {DATA_WIDTH{1'b0}};
rom_read_1t <= 1'b0;
end else begin
if (rom_read_1t == 1'b1)begin
rom_readdata[0+:DATA_WIDTH] <= DP_REG_VALUE_BITS[DATA_WIDTH * read_addr[ADDR_WIDTH -1:0] +:DATA_WIDTH];
end else begin
rom_readdata <= {DATA_WIDTH{1'b0}};
end
rom_read_1t <= rom_read;
read_addr <= rom_address;
end
end
endmodule
| 7.539467 |
module altera_tse_alt4gxb_gige (
cal_blk_clk,
fixedclk,
fixedclk_fast,
gxb_powerdown,
pll_inclk,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_datain,
rx_digitalreset,
rx_seriallpbken,
tx_ctrlenable,
tx_datain,
tx_digitalreset,
reconfig_fromgxb,
rx_clkout,
rx_ctrldetect,
rx_dataout,
rx_disperr,
rx_errdetect,
rx_patterndetect,
rx_rlv,
rx_rmfifodatadeleted,
rx_rmfifodatainserted,
rx_runningdisp,
rx_syncstatus,
tx_clkout,
tx_dataout
) /* synthesis synthesis_clearbox = 1 */;
input cal_blk_clk;
input fixedclk;
input [5:0] fixedclk_fast;
input [0:0] gxb_powerdown;
input pll_inclk;
input reconfig_clk;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [0:0] rx_cruclk;
input [0:0] rx_datain;
input [0:0] rx_digitalreset;
input [0:0] rx_seriallpbken;
input [0:0] tx_ctrlenable;
input [7:0] tx_datain;
input [0:0] tx_digitalreset;
output [16:0] reconfig_fromgxb;
output rx_clkout;
output [0:0] rx_ctrldetect;
output [7:0] rx_dataout;
output [0:0] rx_disperr;
output [0:0] rx_errdetect;
output [0:0] rx_patterndetect;
output [0:0] rx_rlv;
output [0:0] rx_rmfifodatadeleted;
output [0:0] rx_rmfifodatainserted;
output [0:0] rx_runningdisp;
output [0:0] rx_syncstatus;
output [0:0] tx_clkout;
output [0:0] tx_dataout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [0:0] rx_cruclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
endmodule
| 7.477524 |
module altera_tse_altgxb #(
parameter DEVICE_FAMILY = "ARRIAGX", // The device family the the core is targetted for.
parameter STARTING_CHANNEL_NUMBER = 0,
parameter ENABLE_ALT_RECONFIG = 0,
parameter ENABLE_SGMII = 1, // Use to determine rate match FIFO in ALTGX GIGE mode
parameter RECONFIG_TOGXB_WIDTH = 4, // Port width for reconfig_togxb
parameter RECONFIG_FROMGXB_WIDTH = 17 // Port width for reconfig_fromgxb
) (
input ref_clk,
input rx_analogreset_sqcnr,
input rx_digitalreset_sqcnr_rx_clk,
input sd_loopback,
input tx_kchar,
input [7:0] tx_frame,
input tx_digitalreset_sqcnr_tx_clk,
output pll_locked,
output rx_freqlocked,
output rx_kchar,
output rx_pcs_clk,
output [7:0] rx_frame,
output rx_disp_err,
output rx_char_err_gx,
output rx_patterndetect,
output rx_runlengthviolation,
output rx_syncstatus,
output tx_pcs_clk,
output rx_rmfifodatadeleted,
output rx_rmfifodatainserted,
output rx_runningdisp,
output gxb_pwrdn_in_to_pcs,
output reconfig_busy_to_pcs,
input pcs_pwrdn_out_from_pcs,
// SERDES control signals
output rx_recovclkout,
input gxb_pwrdn_in,
input reconfig_clk,
input [RECONFIG_TOGXB_WIDTH - 1:0] reconfig_togxb,
input reconfig_busy,
output pcs_pwrdn_out,
output [RECONFIG_FROMGXB_WIDTH -1:0] reconfig_fromgxb,
// Calibration block clock
input gxb_cal_blk_clk,
// Serial signals
output txp,
input rxp
);
wire [ 3:0] reconfig_togxb_wire;
wire [16:0] reconfig_fromgxb_wire;
// We are not using these signals, but for the sake of building the conduit interface
// we take it in and send it to PCS
assign gxb_pwrdn_in_to_pcs = gxb_pwrdn_in;
assign reconfig_busy_to_pcs = reconfig_busy;
assign pcs_pwrdn_out = pcs_pwrdn_out_from_pcs;
// Let us handle the width different for reconfig_togxb and reconfig_fromgxb port
// due to different device.
generate
if (RECONFIG_TOGXB_WIDTH > 4) begin
// Append zero to the upper bits if the reconfig_togxb width is less than 4
assign reconfig_togxb_wire = {{{4 - RECONFIG_TOGXB_WIDTH} {1'b0}}, reconfig_togxb};
end else begin
assign reconfig_togxb_wire = reconfig_togxb;
end
endgenerate
assign reconfig_fromgxb = reconfig_fromgxb_wire[RECONFIG_FROMGXB_WIDTH-1:0];
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst (
.cal_blk_clk(gxb_cal_blk_clk),
.gxb_powerdown(gxb_pwrdn_in),
.pll_inclk(ref_clk),
.reconfig_clk(reconfig_clk),
.reconfig_togxb(reconfig_togxb_wire),
.rx_analogreset(rx_analogreset_sqcnr),
.rx_cruclk(ref_clk),
.rx_datain(rxp),
.rx_digitalreset(rx_digitalreset_sqcnr_rx_clk),
.rx_seriallpbken(sd_loopback),
.tx_ctrlenable(tx_kchar),
.tx_datain(tx_frame),
.tx_digitalreset(tx_digitalreset_sqcnr_tx_clk),
.pll_powerdown(gxb_pwrdn_in),
.pll_locked(pll_locked),
.rx_freqlocked(rx_freqlocked),
.reconfig_fromgxb(reconfig_fromgxb_wire),
.rx_ctrldetect(rx_kchar),
.rx_clkout(rx_pcs_clk),
.rx_dataout(rx_frame),
.rx_disperr(rx_disp_err),
.rx_errdetect(rx_char_err_gx),
.rx_patterndetect(rx_patterndetect),
.rx_rlv(rx_runlengthviolation),
.rx_syncstatus(rx_syncstatus),
.tx_clkout(tx_pcs_clk),
.tx_dataout(txp),
.rx_recovclkout(rx_recovclkout),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.rx_runningdisp(rx_runningdisp)
);
defparam the_altera_tse_gxb_gige_inst.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER,
the_altera_tse_gxb_gige_inst.DEVICE_FAMILY = DEVICE_FAMILY,
the_altera_tse_gxb_gige_inst.ENABLE_SGMII = ENABLE_SGMII;
endmodule
| 7.477524 |
module altera_tse_fake_master (
// Clock and reset
input clk,
input reset,
// Avalon MM master interface
output [8:0] phy_mgmt_address,
output phy_mgmt_read,
input [31:0] phy_mgmt_readdata,
output phy_mgmt_write,
output reg [31:0] phy_mgmt_writedata,
input phy_mgmt_waitrequest,
// Serial data loopback control
input sd_loopback
);
//////////////////////////////////internal registers and paramaters//////////////////////////////////
reg [1:0] state;
reg [1:0] next_state;
reg sd_loopback_r1, sd_loopback_r2;
reg bit_event;
localparam IDLE = 2'b0;
localparam WRITE_DATA = 2'b1;
////////////////////to detect the toggled data from sd_loopback //////////
always @(posedge clk or posedge reset) begin
if (reset) begin
sd_loopback_r1 <= 1'b0;
sd_loopback_r2 <= 1'b0;
end else begin
sd_loopback_r2 <= sd_loopback_r1;
sd_loopback_r1 <= sd_loopback;
end
end
// bit_event is the bit to remember there is an event happening at the sd_loopback
// and used to trigger IDLE -> WRITE_DATA state transition
// This bit is only cleared during WRITE_DATA -> IDLE transition and make sure that
// phy_mgmt_writedata[0] value is equal to sd_loopback data
// This is to ensure that our Avalon MM write transaction is always in sync with sd_loopback value
always @(posedge clk or posedge reset) begin
if (reset) begin
bit_event <= 0;
end else begin
if (sd_loopback_r1 != sd_loopback_r2) begin
bit_event <= 1'b1;
end else begin
if (next_state == IDLE && state == WRITE_DATA && phy_mgmt_writedata[0] == sd_loopback) begin
bit_event <= 1'b0;
end
end
end
end
// State machine
always @(posedge clk or posedge reset) begin
if (reset) state <= IDLE;
else state <= next_state;
end
// next_state logic
always @(*) begin
case (state)
IDLE: begin
if (bit_event) next_state = WRITE_DATA;
else next_state = IDLE;
end
WRITE_DATA: begin
if (!phy_mgmt_waitrequest) next_state = IDLE;
else next_state = WRITE_DATA;
end
default: next_state = IDLE;
endcase
end
// Connection to PHYIP (Avalon MM master signals)
assign phy_mgmt_write = (state == WRITE_DATA) ? 1'b1 : 1'b0;
assign phy_mgmt_read = 1'b0;
assign phy_mgmt_address = (state == WRITE_DATA) ? 9'h61 : 9'h0;
always @(posedge clk or posedge reset) begin
if (reset) begin
phy_mgmt_writedata <= 32'b0;
end else begin
if (state == IDLE && next_state == WRITE_DATA) begin
phy_mgmt_writedata <= {31'b0, sd_loopback};
end else if (state == WRITE_DATA && next_state == IDLE) begin
phy_mgmt_writedata <= 32'b0;
end
end
end
endmodule
| 9.018435 |
module altera_tse_lvds_reset_sequencer (
clk,
reset,
rx_locked,
rx_channel_data_align,
pll_areset,
rx_reset,
rx_cda_reset
);
input clk;
input reset;
input rx_locked;
output rx_channel_data_align;
output pll_areset;
output rx_reset;
output rx_cda_reset;
reg rx_channel_data_align;
reg pll_areset;
reg rx_reset;
reg rx_cda_reset;
wire rx_locked_sync;
reg rx_locked_sync_d1;
reg rx_locked_sync_d2;
reg rx_locked_sync_d3;
reg rx_locked_stable;
reg [2:0] pulse_count;
reg [2:0] state;
reg [2:0] nextstate;
// State Definitions
parameter [2:0] stm_idle = 3'b000; //0
parameter [2:0] stm_pll_areset = 3'b001; //1
parameter [2:0] stm_rx_reset = 3'b010; //2
parameter [2:0] stm_rx_cda_reset = 3'b011; //3
parameter [2:0] stm_word_alignment = 3'b100; //4
altera_std_synchronizer #(2) rx_locked_altera_std_synchronizer (
.clk(clk),
.reset_n(~reset),
.din(rx_locked),
.dout(rx_locked_sync)
);
always @(posedge clk or posedge reset) begin
if (reset == 1'b1) begin
rx_locked_sync_d1 <= 1'b0;
rx_locked_sync_d2 <= 1'b0;
rx_locked_sync_d3 <= 1'b0;
end else begin
rx_locked_sync_d1 <= rx_locked_sync;
rx_locked_sync_d2 <= rx_locked_sync_d1;
rx_locked_sync_d3 <= rx_locked_sync_d2;
end
end
always @(posedge clk or posedge reset) begin
if (reset == 1'b1) begin
rx_locked_stable <= 1'b0;
end else begin
rx_locked_stable <= rx_locked_sync & rx_locked_sync_d1 & rx_locked_sync_d2 & rx_locked_sync_d3;
end
end
// FSM
always @(posedge clk or posedge reset) begin
if (reset == 1'b1) begin
state <= stm_pll_areset;
end else begin
state <= nextstate;
end
end
always @(*) begin
case (state)
stm_idle:
if (reset == 1'b1) begin
nextstate = stm_pll_areset;
end else begin
nextstate = stm_idle;
end
stm_pll_areset: begin
nextstate = stm_rx_reset;
end
stm_rx_reset:
if (rx_locked_stable == 1'b0) begin
nextstate = stm_rx_reset;
end else begin
nextstate = stm_rx_cda_reset;
end
stm_rx_cda_reset: begin
nextstate = stm_word_alignment;
end
stm_word_alignment:
if (pulse_count == 4) begin
nextstate = stm_idle;
end else begin
nextstate = stm_word_alignment;
end
default: begin
nextstate = stm_idle;
end
endcase
end
always @(posedge clk or posedge reset) begin
if (reset == 1'b1) begin
pll_areset <= 1'b1;
rx_reset <= 1'b1;
rx_cda_reset <= 1'b0;
rx_channel_data_align <= 1'b0;
pulse_count <= 3'b000;
end else begin
case (nextstate)
stm_idle: begin
pll_areset <= 1'b0;
rx_reset <= 1'b0;
rx_cda_reset <= 1'b0;
rx_channel_data_align <= 1'b0;
pulse_count <= 3'b000;
end
stm_pll_areset: begin
pll_areset <= 1'b1;
rx_reset <= 1'b1;
rx_cda_reset <= 1'b0;
rx_channel_data_align <= 1'b0;
pulse_count <= 3'b000;
end
stm_rx_reset: begin
pll_areset <= 1'b0;
rx_cda_reset <= 1'b0;
rx_channel_data_align <= 1'b0;
pulse_count <= 3'b000;
end
stm_rx_cda_reset: begin
pll_areset <= 1'b0;
rx_reset <= 1'b0;
rx_cda_reset <= 1'b1;
rx_channel_data_align <= 1'b0;
pulse_count <= 3'b000;
end
stm_word_alignment: begin
pll_areset <= 1'b0;
rx_reset <= 1'b0;
rx_cda_reset <= 1'b0;
rx_channel_data_align <= ~rx_channel_data_align;
pulse_count <= pulse_count + 1'b1;
end
default: begin
pll_areset <= 1'b0;
rx_reset <= 1'b0;
rx_cda_reset <= 1'b0;
rx_channel_data_align <= 1'b0;
pulse_count <= 3'b000;
end
endcase
end
end
endmodule
| 8.126096 |
module altera_tse_reset_synchronizer #(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
) (
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,R105\"" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
// Please check the false paths setting in TSE SDC
(*preserve*) reg [DEPTH-1:0] altera_tse_reset_synchronizer_chain;
reg altera_tse_reset_synchronizer_chain_out;
generate
if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_tse_reset_synchronizer_chain <= {DEPTH{1'b1}};
altera_tse_reset_synchronizer_chain_out <= 1'b1;
end else begin
altera_tse_reset_synchronizer_chain[DEPTH-2:0] <= altera_tse_reset_synchronizer_chain[DEPTH-1:1];
altera_tse_reset_synchronizer_chain[DEPTH-1] <= 0;
altera_tse_reset_synchronizer_chain_out <= altera_tse_reset_synchronizer_chain[0];
end
end
assign reset_out = altera_tse_reset_synchronizer_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_tse_reset_synchronizer_chain[DEPTH-2:0] <= altera_tse_reset_synchronizer_chain[DEPTH-1:1];
altera_tse_reset_synchronizer_chain[DEPTH-1] <= reset_in;
altera_tse_reset_synchronizer_chain_out <= altera_tse_reset_synchronizer_chain[0];
end
assign reset_out = altera_tse_reset_synchronizer_chain_out;
end
endgenerate
endmodule
| 7.285704 |
module.
//
// Parameters:
// SYNC_CHAIN_LENGTH
// - Specifies the length of the synchronizer chain for metastability
// retiming.
// WIDTH
// - Specifies the number of bits you want to synchronize. Controls the width of the
// d and q ports.
// SLOW_CLOCK - USE WITH CAUTION.
// - Leaving this setting at its default will create a standard resynch circuit that
// merely passes the input data through a chain of flip-flops. This setting assumes
// that the input data has a pulse width longer than one clock cycle sufficient to
// satisfy setup and hold requirements on at least one clock edge.
// - By setting this to 1 (USE CAUTION) you are creating an asynchronous
// circuit that will capture the input data regardless of the pulse width and
// its relationship to the clock. However it is more difficult to apply static
// timing constraints as it ties the data input to the clock input of the flop.
// This implementation assumes the data rate is slow enough
//
module altera_tse_xcvr_resync #(
parameter SYNC_CHAIN_LENGTH = 2, // Number of flip-flops for retiming
parameter WIDTH = 1, // Number of bits to resync
parameter SLOW_CLOCK = 0 // See description above
) (
input wire clk,
input wire [WIDTH-1:0] d,
output wire [WIDTH-1:0] q
);
localparam INT_LEN = (SYNC_CHAIN_LENGTH > 0) ? SYNC_CHAIN_LENGTH : 1;
genvar ig;
// Generate a synchronizer chain for each bit
generate begin
for(ig=0;ig<WIDTH;ig=ig+1) begin : resync_chains
wire d_in; // Input to sychronization chain.
reg [INT_LEN-1:0] r = {INT_LEN{1'b0}};
wire [INT_LEN :0] next_r; // One larger real chain
assign q[ig] = r[INT_LEN-1]; // Output signal
assign next_r = {r,d_in};
always @(posedge clk)
r <= next_r[INT_LEN-1:0];
// Generate asynchronous capture circuit if specified.
if(SLOW_CLOCK == 0) begin
assign d_in = d[ig];
end else begin
wire d_clk;
reg d_r;
wire clr_n;
assign d_clk = d[ig];
assign d_in = d_r;
assign clr_n = ~q[ig] | d_clk; // Clear when output is logic 1 and input is logic 0
// Asynchronously latch the input signal.
always @(posedge d_clk or negedge clr_n)
if(!clr_n) d_r <= 1'b0;
else if(d_clk) d_r <= 1'b1;
end // SLOW_CLOCK
end // for loop
end // generate
endgenerate
endmodule
| 8.162755 |
module RxD_fifo #(
parameter Dw = 72, //data_width
parameter B = 10 // buffer num
) (
din,
wr_en,
rd_en,
dout,
full,
nearly_full,
empty,
reset,
clk
);
function integer log2;
input integer number;
begin
log2 = (number <= 1) ? 1 : 0;
while (2 ** log2 < number) begin
log2 = log2 + 1;
end
end
endfunction // log2
localparam B_1 = B - 1, Bw = log2(B), DEPTHw = log2(B + 1);
localparam [Bw-1 : 0] Bint = B_1[Bw-1 : 0];
input [Dw-1:0] din; // Data in
input wr_en; // Write enable
input rd_en; // Read the next word
output [Dw-1:0] dout; // Data out
output full;
output nearly_full;
output empty;
input reset;
input clk;
reg [ Dw-1 : 0] queue [B-1 : 0] /* synthesis ramstyle = "no_rw_check" */;
reg [ Bw- 1 : 0] rd_ptr;
reg [ Bw- 1 : 0] wr_ptr;
reg [DEPTHw-1 : 0] depth;
// Sample the data
always @(posedge clk) begin
if (wr_en) queue[wr_ptr] <= din;
end
assign dout = queue[rd_ptr];
always @(posedge clk) begin
if (reset) begin
rd_ptr <= {Bw{1'b0}};
wr_ptr <= {Bw{1'b0}};
depth <= {DEPTHw{1'b0}};
end else begin
if (wr_en) wr_ptr <= (wr_ptr == Bint) ? {Bw{1'b0}} : wr_ptr + 1'b1;
if (rd_en) rd_ptr <= (rd_ptr == Bint) ? {Bw{1'b0}} : rd_ptr + 1'b1;
if (wr_en & ~rd_en)
depth <=
//synthesis translate_off
//synopsys translate_off
#1
//synopsys translate_on
//synthesis translate_on
depth + 1'b1;
else if (~wr_en & rd_en)
depth <=
//synthesis translate_off
//synopsys translate_off
#1
//synopsys translate_on
//synthesis translate_on
depth - 1'b1;
end
end
//assign dout = queue[rd_ptr];
assign full = depth == B;
assign nearly_full = depth >= B - 1;
assign empty = depth == {DEPTHw{1'b0}};
//synthesis translate_off
//synopsys translate_off
always @(posedge clk) begin
if (~reset) begin
if (wr_en && depth == B && !rd_en)
$display(" %t: ERROR: Attempt to write to full FIFO: %m", $time);
if (rd_en && depth == {DEPTHw{1'b0}})
$display("%t: ERROR: Attempt to read an empty FIFO: %m", $time);
end //~reset
end
//synopsys translate_on
//synthesis translate_on
endmodule
| 6.524137 |
module Altera_unique_chip_ID (
input wire clkin, // clkin.clk
input wire reset, // reset.reset
output wire data_valid, // output.valid
output wire [63:0] chip_id // .data
);
altchip_id #(
.DEVICE_FAMILY("MAX 10"),
.ID_VALUE (64'b1111111111111111111111111111111111111111111111111111111111111111),
.ID_VALUE_STR ("00000000ffffffff")
) altera_unique_chip_id_inst (
.clkin (clkin), // clkin.clk
.reset (reset), // reset.reset
.data_valid(data_valid), // output.valid
.chip_id (chip_id) // .data
);
endmodule
| 7.184465 |
module is a rom for auto initializing the accelerometer on the *
* DE-Nano. *
* *
******************************************************************************/
module altera_up_accelerometer_spi_auto_init (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 4: 0] rom_address;
// Bidirectionals
// Outputs
output [15: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
reg [13: 0] data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
// Output Assignments
assign rom_data = {2'h0, data[13: 0]};
// Internal Assignments
always @(*)
begin
case (rom_address)
0 : data <= {6'h24, 8'h04}; // Activity value threshold.
1 : data <= {6'h25, 8'h02}; // Inactivity value threshold.
2 : data <= {6'h26, 8'h02}; // Activity time threshold.
3 : data <= {6'h27, 8'hFF}; // AC coupling for thresholds.
4 : data <= {6'h28, 8'h09}; // Free fall value threshold.
5 : data <= {6'h29, 8'h46}; // Free fall time threshold.
6 : data <= {6'h2C, 8'h0A}; // Output data rate: 100 Hz.
7 : data <= {6'h2E, 8'h18}; // Enabling ACTIVITY and INACTIVITY interrupts.
8 : data <= {6'h2F, 8'h10}; // Sends the ACTIVITY interrupt to the INT2 pin.
9 : data <= {6'h31, 8'h4B}; // 3-Wire SPI mode, 16G, full resolution.
10 : data <= {6'h2D, 8'h08}; // Start measuring.
default : data <= 14'h0000;
endcase
end
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
| 7.432195 |
module loads data into the Audio and Video chips' control *
* registers after system reset. *
* *
******************************************************************************/
module altera_up_accelerometer_spi_auto_init_ctrl (
// Inputs
clk,
reset,
clear_error,
ack,
transfer_complete,
rom_data,
// Bidirectionals
// Outputs
data_out,
transfer_data,
rom_address,
auto_init_complete,
auto_init_error,
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter ROM_SIZE = 50;
parameter AW = 5; // Auto Initialize ROM's address width
parameter DW = 23; // Auto Initialize ROM's datawidth
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input clear_error;
input ack;
input transfer_complete;
input [DW: 0] rom_data;
// Bidirectionals
// Outputs
output reg [DW: 0] data_out;
output reg transfer_data;
output reg [AW: 0] rom_address;
output reg auto_init_complete;
output reg auto_init_error;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire toggle_next_transfer;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
data_out <= 'h0;
else
data_out <= rom_data;
end
always @(posedge clk)
begin
if (reset)
transfer_data <= 1'b0;
else if (auto_init_complete | transfer_complete)
transfer_data <= 1'b0;
else
transfer_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
rom_address <= 'h0;
else if (toggle_next_transfer)
rom_address <= rom_address + 'h1;
end
always @(posedge clk)
begin
if (reset)
auto_init_complete <= 1'b0;
else if (toggle_next_transfer & (rom_address == (ROM_SIZE - 1)))
auto_init_complete <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
auto_init_error <= 1'b0;
else if (toggle_next_transfer & ack)
auto_init_error <= 1'b1;
else if (clear_error)
auto_init_error <= 1'b0;
end
// Internal Registers
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
assign toggle_next_transfer = transfer_data & transfer_complete;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
| 6.814331 |
module counts which bits for serial audio transfers. The module *
* assume that the data format is I2S, as it is described in the audio *
* chip's datasheet. *
* *
******************************************************************************/
module Altera_UP_Audio_Bit_Counter (
// Inputs
clk,
reset,
bit_clk_rising_edge,
bit_clk_falling_edge,
left_right_clk_rising_edge,
left_right_clk_falling_edge,
// Bidirectionals
// Outputs
counting
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter BIT_COUNTER_INIT = 5'h0F;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input bit_clk_rising_edge;
input bit_clk_falling_edge;
input left_right_clk_rising_edge;
input left_right_clk_falling_edge;
// Bidirectionals
// Outputs
output reg counting;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire reset_bit_counter;
// Internal Registers
reg [4:0] bit_counter;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
bit_counter <= 5'h00;
else if (reset_bit_counter == 1'b1)
bit_counter <= BIT_COUNTER_INIT;
else if ((bit_clk_falling_edge == 1'b1) && (bit_counter != 5'h00))
bit_counter <= bit_counter - 5'h01;
end
always @(posedge clk)
begin
if (reset == 1'b1)
counting <= 1'b0;
else if (reset_bit_counter == 1'b1)
counting <= 1'b1;
else if ((bit_clk_falling_edge == 1'b1) && (bit_counter == 5'h00))
counting <= 1'b0;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign reset_bit_counter = left_right_clk_rising_edge |
left_right_clk_falling_edge;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
| 8.853421 |
module is used to create a reset from the clock locked signal. *
* *
******************************************************************************/
module altera_up_avalon_reset_from_locked_signal (
// Inputs
locked,
// Bidirectional
// Outputs
reset
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input locked;
// Bidirectionals
// Outputs
output reset;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign reset = ~locked;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
| 7.719387 |
module is an adapter for the UP Video DMA Controller. It translates *
* the address of the front and back buffers by a fixed offset. This is *
* required when the addresses to memory differ for the DMA and the *
* processor, as in the case of the ARM processor. *
* *
******************************************************************************/
module altera_up_avalon_video_dma_ctrl_address_translation (
// Inputs
clk,
reset,
slave_address,
slave_byteenable,
slave_read,
slave_write,
slave_writedata,
master_readdata,
master_waitrequest,
// Bi-Directional
// Outputs
slave_readdata,
slave_waitrequest,
master_address,
master_byteenable,
master_read,
master_write,
master_writedata
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
// Parameters
parameter ADDRESS_TRANSLATION_MASK = 32'hC0000000;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 1: 0] slave_address;
input [ 3: 0] slave_byteenable;
input slave_read;
input slave_write;
input [31: 0] slave_writedata;
input [31: 0] master_readdata;
input master_waitrequest;
// Bi-Directional
// Outputs
output [31: 0] slave_readdata;
output slave_waitrequest;
output [ 1: 0] master_address;
output [ 3: 0] master_byteenable;
output master_read;
output master_write;
output [31: 0] master_writedata;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign slave_readdata = (slave_address[1] == 1'b0) ?
master_readdata | ADDRESS_TRANSLATION_MASK :
master_readdata;
assign slave_waitrequest = master_waitrequest;
assign master_address = slave_address;
assign master_byteenable = slave_byteenable;
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = (slave_address[1] == 1'b0) ?
slave_writedata & ~ADDRESS_TRANSLATION_MASK :
slave_writedata;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
| 8.31907 |
module is an adapter for the UP Video DMA Controller. It translates *
* the address of the front and back buffers by a fixed offset. This is *
* required when the addresses to memory differ for the DMA and the *
* processor, as in the case of the ARM processor. *
* *
******************************************************************************/
module altera_up_avalon_video_dma_ctrl_addr_trans (
// Inputs
clk,
reset,
slave_address,
slave_byteenable,
slave_read,
slave_write,
slave_writedata,
master_readdata,
master_waitrequest,
// Bi-Directional
// Outputs
slave_readdata,
slave_waitrequest,
master_address,
master_byteenable,
master_read,
master_write,
master_writedata
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
// Parameters
parameter ADDRESS_TRANSLATION_MASK = 32'hC0000000;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 1: 0] slave_address;
input [ 3: 0] slave_byteenable;
input slave_read;
input slave_write;
input [31: 0] slave_writedata;
input [31: 0] master_readdata;
input master_waitrequest;
// Bi-Directional
// Outputs
output [31: 0] slave_readdata;
output slave_waitrequest;
output [ 1: 0] master_address;
output [ 3: 0] master_byteenable;
output master_read;
output master_write;
output [31: 0] master_writedata;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign slave_readdata = (slave_address[1] == 1'b0) ?
master_readdata | ADDRESS_TRANSLATION_MASK :
master_readdata;
assign slave_waitrequest = master_waitrequest;
assign master_address = slave_address;
assign master_byteenable = slave_byteenable;
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = (slave_address[1] == 1'b0) ?
slave_writedata & ~ADDRESS_TRANSLATION_MASK :
slave_writedata;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
| 8.31907 |
module loads data into the Audio and Video chips' control *
* registers after system reset. *
* *
******************************************************************************/
module altera_up_av_config_auto_init (
// Inputs
clk,
reset,
clear_error,
ack,
transfer_complete,
rom_data,
// Bidirectionals
// Outputs
data_out,
transfer_data,
rom_address,
auto_init_complete,
auto_init_error,
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter ROM_SIZE = 50;
parameter AW = 5; // Auto Initialize ROM's address width
parameter DW = 23; // Auto Initialize ROM's datawidth
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input clear_error;
input ack;
input transfer_complete;
input [DW: 0] rom_data;
// Bidirectionals
// Outputs
output reg [DW: 0] data_out;
output reg transfer_data;
output reg [AW: 0] rom_address;
output reg auto_init_complete;
output reg auto_init_error;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire toggle_next_transfer;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
data_out <= 'h0;
else
data_out <= rom_data;
end
always @(posedge clk)
begin
if (reset)
transfer_data <= 1'b0;
else if (auto_init_complete | transfer_complete)
transfer_data <= 1'b0;
else
transfer_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
rom_address <= 'h0;
else if (toggle_next_transfer)
rom_address <= rom_address + 'h1;
end
always @(posedge clk)
begin
if (reset)
auto_init_complete <= 1'b0;
else if (toggle_next_transfer & (rom_address == (ROM_SIZE - 1)))
auto_init_complete <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
auto_init_error <= 1'b0;
else if (toggle_next_transfer & ack)
auto_init_error <= 1'b1;
else if (clear_error)
auto_init_error <= 1'b0;
end
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
assign toggle_next_transfer = transfer_data & transfer_complete;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
| 6.814331 |
module is a rom for auto initializing the TRDB LTM lcd screen. *
* *
******************************************************************************/
module altera_up_av_config_auto_init_ltm (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 4: 0] rom_address;
// Bidirectionals
// Outputs
output [23: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
reg [23: 0] data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = {data[13: 8], 2'h0,
data[ 7: 0]};
// Internal Assignments
always @(*)
begin
case (rom_address)
0 : data <= {6'h02, 8'h07};
1 : data <= {6'h03, 8'hDF};
2 : data <= {6'h04, 8'h17};
3 : data <= {6'h11, 8'h00};
4 : data <= {6'h12, 8'h5B};
5 : data <= {6'h13, 8'hFF};
6 : data <= {6'h14, 8'h00};
7 : data <= {6'h15, 8'h20};
8 : data <= {6'h16, 8'h40};
9 : data <= {6'h17, 8'h80};
10 : data <= {6'h18, 8'h00};
11 : data <= {6'h19, 8'h80};
12 : data <= {6'h1A, 8'h00};
13 : data <= {6'h1B, 8'h00};
14 : data <= {6'h1C, 8'h80};
15 : data <= {6'h1D, 8'hC0};
16 : data <= {6'h1E, 8'hE0};
17 : data <= {6'h1F, 8'hFF};
18 : data <= {6'h20, 8'hD2};
19 : data <= {6'h21, 8'hD2};
default : data <= 14'h0000;
endcase
end
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
| 7.432195 |
module is a rom for auto initializing the on board audio chip. *
* *
******************************************************************************/
module altera_up_av_config_auto_init_ob_audio (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter AUD_LINE_IN_LC = 9'h01A;
parameter AUD_LINE_IN_RC = 9'h01A;
parameter AUD_LINE_OUT_LC = 9'h07B;
parameter AUD_LINE_OUT_RC = 9'h07B;
parameter AUD_ADC_PATH = 9'h0F8;
parameter AUD_DAC_PATH = 9'h006;
parameter AUD_POWER = 9'h000;
parameter AUD_DATA_FORMAT = 9'h001;
parameter AUD_SAMPLE_CTRL = 9'h002;
parameter AUD_SET_ACTIVE = 9'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 5: 0] rom_address;
// Bidirectionals
// Outputs
output [26: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
reg [23: 0] data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = {data[23:16], 1'b0,
data[15: 8], 1'b0,
data[ 7: 0], 1'b0};
// Internal Assignments
always @(*)
begin
case (rom_address)
// Audio Config Data
0 : data <= {8'h34, 7'h0, AUD_LINE_IN_LC};
1 : data <= {8'h34, 7'h1, AUD_LINE_IN_RC};
2 : data <= {8'h34, 7'h2, AUD_LINE_OUT_LC};
3 : data <= {8'h34, 7'h3, AUD_LINE_OUT_RC};
4 : data <= {8'h34, 7'h4, AUD_ADC_PATH};
5 : data <= {8'h34, 7'h5, AUD_DAC_PATH};
6 : data <= {8'h34, 7'h6, AUD_POWER};
7 : data <= {8'h34, 7'h7, AUD_DATA_FORMAT};
8 : data <= {8'h34, 7'h8, AUD_SAMPLE_CTRL};
9 : data <= {8'h34, 7'h9, AUD_SET_ACTIVE};
default : data <= {8'h00, 7'h0, 9'h000};
endcase
end
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
| 7.432195 |
module is a rom for auto initializing the on board periphal devices *
* on the DE10-Standard board. *
* *
******************************************************************************/
module altera_up_av_config_auto_init_ob_de10_standard (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter AUD_LINE_IN_LC = 9'h01A;
parameter AUD_LINE_IN_RC = 9'h01A;
parameter AUD_LINE_OUT_LC = 9'h07B;
parameter AUD_LINE_OUT_RC = 9'h07B;
parameter AUD_ADC_PATH = 9'h0F8;
parameter AUD_DAC_PATH = 9'h006;
parameter AUD_POWER = 9'h000;
parameter AUD_DATA_FORMAT = 9'h001;
parameter AUD_SAMPLE_CTRL = 9'h002;
parameter AUD_SET_ACTIVE = 9'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 5: 0] rom_address;
// Bidirectionals
// Outputs
output [26: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [26: 0] audio_rom_data;
wire [26: 0] video_rom_data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = audio_rom_data | video_rom_data;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_av_config_auto_init_ob_audio Auto_Init_Audio_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (audio_rom_data)
);
defparam
Auto_Init_Audio_ROM.AUD_LINE_IN_LC = AUD_LINE_IN_LC,
Auto_Init_Audio_ROM.AUD_LINE_IN_RC = AUD_LINE_IN_RC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_LC = AUD_LINE_OUT_LC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_RC = AUD_LINE_OUT_RC,
Auto_Init_Audio_ROM.AUD_ADC_PATH = AUD_ADC_PATH,
Auto_Init_Audio_ROM.AUD_DAC_PATH = AUD_DAC_PATH,
Auto_Init_Audio_ROM.AUD_POWER = AUD_POWER,
Auto_Init_Audio_ROM.AUD_DATA_FORMAT = AUD_DATA_FORMAT,
Auto_Init_Audio_ROM.AUD_SAMPLE_CTRL = AUD_SAMPLE_CTRL,
Auto_Init_Audio_ROM.AUD_SET_ACTIVE = AUD_SET_ACTIVE;
altera_up_av_config_auto_init_ob_adv7180 Auto_Init_Video_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (video_rom_data)
);
endmodule
| 7.432195 |
module is a rom for auto initializing the on board periphal devices *
* on the DE1-SoC board. *
* *
******************************************************************************/
module altera_up_av_config_auto_init_ob_de1_soc (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter AUD_LINE_IN_LC = 9'h01A;
parameter AUD_LINE_IN_RC = 9'h01A;
parameter AUD_LINE_OUT_LC = 9'h07B;
parameter AUD_LINE_OUT_RC = 9'h07B;
parameter AUD_ADC_PATH = 9'h0F8;
parameter AUD_DAC_PATH = 9'h006;
parameter AUD_POWER = 9'h000;
parameter AUD_DATA_FORMAT = 9'h001;
parameter AUD_SAMPLE_CTRL = 9'h002;
parameter AUD_SET_ACTIVE = 9'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 5: 0] rom_address;
// Bidirectionals
// Outputs
output [26: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [26: 0] audio_rom_data;
wire [26: 0] video_rom_data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = audio_rom_data | video_rom_data;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_av_config_auto_init_ob_audio Auto_Init_Audio_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (audio_rom_data)
);
defparam
Auto_Init_Audio_ROM.AUD_LINE_IN_LC = AUD_LINE_IN_LC,
Auto_Init_Audio_ROM.AUD_LINE_IN_RC = AUD_LINE_IN_RC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_LC = AUD_LINE_OUT_LC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_RC = AUD_LINE_OUT_RC,
Auto_Init_Audio_ROM.AUD_ADC_PATH = AUD_ADC_PATH,
Auto_Init_Audio_ROM.AUD_DAC_PATH = AUD_DAC_PATH,
Auto_Init_Audio_ROM.AUD_POWER = AUD_POWER,
Auto_Init_Audio_ROM.AUD_DATA_FORMAT = AUD_DATA_FORMAT,
Auto_Init_Audio_ROM.AUD_SAMPLE_CTRL = AUD_SAMPLE_CTRL,
Auto_Init_Audio_ROM.AUD_SET_ACTIVE = AUD_SET_ACTIVE;
altera_up_av_config_auto_init_ob_adv7180 Auto_Init_Video_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (video_rom_data)
);
endmodule
| 7.432195 |
module is a rom for auto initializing the on board periphal devices *
* on the DE2i-150 board. *
* *
******************************************************************************/
module altera_up_av_config_auto_init_ob_de2i_150 (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter AUD_LINE_IN_LC = 9'h01A;
parameter AUD_LINE_IN_RC = 9'h01A;
parameter AUD_LINE_OUT_LC = 9'h07B;
parameter AUD_LINE_OUT_RC = 9'h07B;
parameter AUD_ADC_PATH = 9'h0F8;
parameter AUD_DAC_PATH = 9'h006;
parameter AUD_POWER = 9'h000;
parameter AUD_DATA_FORMAT = 9'h001;
parameter AUD_SAMPLE_CTRL = 9'h002;
parameter AUD_SET_ACTIVE = 9'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 5: 0] rom_address;
// Bidirectionals
// Outputs
output [26: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [26: 0] audio_rom_data;
wire [26: 0] video_rom_data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = audio_rom_data | video_rom_data;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_av_config_auto_init_ob_audio Auto_Init_Audio_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (audio_rom_data)
);
defparam
Auto_Init_Audio_ROM.AUD_LINE_IN_LC = AUD_LINE_IN_LC,
Auto_Init_Audio_ROM.AUD_LINE_IN_RC = AUD_LINE_IN_RC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_LC = AUD_LINE_OUT_LC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_RC = AUD_LINE_OUT_RC,
Auto_Init_Audio_ROM.AUD_ADC_PATH = AUD_ADC_PATH,
Auto_Init_Audio_ROM.AUD_DAC_PATH = AUD_DAC_PATH,
Auto_Init_Audio_ROM.AUD_POWER = AUD_POWER,
Auto_Init_Audio_ROM.AUD_DATA_FORMAT = AUD_DATA_FORMAT,
Auto_Init_Audio_ROM.AUD_SAMPLE_CTRL = AUD_SAMPLE_CTRL,
Auto_Init_Audio_ROM.AUD_SET_ACTIVE = AUD_SET_ACTIVE;
altera_up_av_config_auto_init_ob_adv7180 Auto_Init_Video_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (video_rom_data)
);
endmodule
| 7.432195 |
module is a rom for auto initializing the on board periphal devices *
* on the DE2-115 board. *
* *
******************************************************************************/
module altera_up_av_config_auto_init_ob_de2_115 (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter AUD_LINE_IN_LC = 9'h01A;
parameter AUD_LINE_IN_RC = 9'h01A;
parameter AUD_LINE_OUT_LC = 9'h07B;
parameter AUD_LINE_OUT_RC = 9'h07B;
parameter AUD_ADC_PATH = 9'h0F8;
parameter AUD_DAC_PATH = 9'h006;
parameter AUD_POWER = 9'h000;
parameter AUD_DATA_FORMAT = 9'h001;
parameter AUD_SAMPLE_CTRL = 9'h002;
parameter AUD_SET_ACTIVE = 9'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 5: 0] rom_address;
// Bidirectionals
// Outputs
output [26: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [26: 0] audio_rom_data;
wire [26: 0] video_rom_data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = audio_rom_data | video_rom_data;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_av_config_auto_init_ob_audio Auto_Init_Audio_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (audio_rom_data)
);
defparam
Auto_Init_Audio_ROM.AUD_LINE_IN_LC = AUD_LINE_IN_LC,
Auto_Init_Audio_ROM.AUD_LINE_IN_RC = AUD_LINE_IN_RC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_LC = AUD_LINE_OUT_LC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_RC = AUD_LINE_OUT_RC,
Auto_Init_Audio_ROM.AUD_ADC_PATH = AUD_ADC_PATH,
Auto_Init_Audio_ROM.AUD_DAC_PATH = AUD_DAC_PATH,
Auto_Init_Audio_ROM.AUD_POWER = AUD_POWER,
Auto_Init_Audio_ROM.AUD_DATA_FORMAT = AUD_DATA_FORMAT,
Auto_Init_Audio_ROM.AUD_SAMPLE_CTRL = AUD_SAMPLE_CTRL,
Auto_Init_Audio_ROM.AUD_SET_ACTIVE = AUD_SET_ACTIVE;
altera_up_av_config_auto_init_ob_adv7180 Auto_Init_Video_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (video_rom_data)
);
endmodule
| 7.432195 |
module is a rom for auto initializing the on board periphal devices *
* on the DE2-70 board. *
* *
******************************************************************************/
module altera_up_av_config_auto_init_ob_de2_70 (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter AUD_LINE_IN_LC = 9'h01A;
parameter AUD_LINE_IN_RC = 9'h01A;
parameter AUD_LINE_OUT_LC = 9'h07B;
parameter AUD_LINE_OUT_RC = 9'h07B;
parameter AUD_ADC_PATH = 9'h0F8;
parameter AUD_DAC_PATH = 9'h006;
parameter AUD_POWER = 9'h000;
parameter AUD_DATA_FORMAT = 9'h001;
parameter AUD_SAMPLE_CTRL = 9'h002;
parameter AUD_SET_ACTIVE = 9'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 5: 0] rom_address;
// Bidirectionals
// Outputs
output [26: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [26: 0] audio_rom_data;
wire [26: 0] video_rom_data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = audio_rom_data | video_rom_data;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_av_config_auto_init_ob_audio Auto_Init_Audio_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (audio_rom_data)
);
defparam
Auto_Init_Audio_ROM.AUD_LINE_IN_LC = AUD_LINE_IN_LC,
Auto_Init_Audio_ROM.AUD_LINE_IN_RC = AUD_LINE_IN_RC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_LC = AUD_LINE_OUT_LC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_RC = AUD_LINE_OUT_RC,
Auto_Init_Audio_ROM.AUD_ADC_PATH = AUD_ADC_PATH,
Auto_Init_Audio_ROM.AUD_DAC_PATH = AUD_DAC_PATH,
Auto_Init_Audio_ROM.AUD_POWER = AUD_POWER,
Auto_Init_Audio_ROM.AUD_DATA_FORMAT = AUD_DATA_FORMAT,
Auto_Init_Audio_ROM.AUD_SAMPLE_CTRL = AUD_SAMPLE_CTRL,
Auto_Init_Audio_ROM.AUD_SET_ACTIVE = AUD_SET_ACTIVE;
altera_up_av_config_auto_init_ob_adv7180 Auto_Init_Video_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (video_rom_data)
);
endmodule
| 7.432195 |
module finds clock edges of one clock at the frequency of *
* another clock. *
* *
******************************************************************************/
module Altera_UP_Clock_Edge (
// Inputs
clk,
reset,
test_clk,
// Bidirectionals
// Outputs
rising_edge,
falling_edge
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input test_clk;
// Bidirectionals
// Outputs
output rising_edge;
output falling_edge;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire found_edge;
// Internal Registers
reg cur_test_clk;
reg last_test_clk;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
cur_test_clk <= test_clk;
always @(posedge clk)
last_test_clk <= cur_test_clk;
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
// Output Assignments
assign rising_edge = found_edge & cur_test_clk;
assign falling_edge = found_edge & last_test_clk;
// Internal Assignments
assign found_edge = last_test_clk ^ cur_test_clk;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
| 9.523667 |
module is a FIFO with same clock for both reads and writes. *
* *
******************************************************************************/
module Altera_UP_SYNC_FIFO (
// Inputs
clk,
reset,
write_en,
write_data,
read_en,
// Bidirectionals
// Outputs
fifo_is_empty,
fifo_is_full,
words_used,
read_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DATA_WIDTH = 32;
parameter DATA_DEPTH = 128;
parameter ADDR_WIDTH = 7;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input write_en;
input [DATA_WIDTH:1] write_data;
input read_en;
// Bidirectionals
// Outputs
output fifo_is_empty;
output fifo_is_full;
output [ADDR_WIDTH:1] words_used;
output [DATA_WIDTH:1] read_data;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Sync_FIFO (
// Inputs
.clock (clk),
.sclr (reset),
.data (write_data),
.wrreq (write_en),
.rdreq (read_en),
// Bidirectionals
// Outputs
.empty (fifo_is_empty),
.full (fifo_is_full),
.usedw (words_used),
.q (read_data)
// Unused
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full ()
// synopsys translate_on
);
defparam
Sync_FIFO.add_ram_output_register = "OFF",
Sync_FIFO.intended_device_family = "Cyclone II",
Sync_FIFO.lpm_numwords = DATA_DEPTH,
Sync_FIFO.lpm_showahead = "ON",
Sync_FIFO.lpm_type = "scfifo",
Sync_FIFO.lpm_width = DATA_WIDTH,
Sync_FIFO.lpm_widthu = ADDR_WIDTH,
Sync_FIFO.overflow_checking = "OFF",
Sync_FIFO.underflow_checking = "OFF",
Sync_FIFO.use_eab = "ON";
endmodule
| 7.352627 |
module contains a character map for 128 different ASCII characters. *
* *
******************************************************************************/
module altera_up_video_ascii_rom_128 (
// Inputs
clk,
clk_en,
character,
x_coordinate,
y_coordinate,
// Bidirectionals
// Outputs
character_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input clk_en;
input [ 6: 0] character;
input [ 2: 0] x_coordinate;
input [ 2: 0] y_coordinate;
// Bidirectionals
// Outputs
output reg character_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [12: 0] character_address;
// Internal Registers
reg rom [8191:0];
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
initial
begin
$readmemb("altera_up_video_ascii_rom_128.txt", rom);
end
always @ (posedge clk)
begin
if (clk_en)
character_data <= rom[character_address];
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign character_address = {character, y_coordinate, x_coordinate};
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
| 7.224432 |
module store the video input stream to be processed. *
* *
*****************************************************************************/
module Altera_UP_Video_In_Buffer (
// Inputs
system_clk,
video_in_clk,
reset,
Y_in,
CrCb_in,
pixel_info_in,
valid_pixel,
read_buffer,
// Bidirectional
// Outputs
buffer_has_data,
Y_out,
CrCb_out,
pixel_info_out
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input system_clk;
input video_in_clk;
input reset;
input [7:0] Y_in;
input [7:0] CrCb_in;
input [1:0] pixel_info_in;
input valid_pixel;
input read_buffer;
// Bidirectional
// Outputs
output buffer_has_data;
output [7:0] Y_out;
output [7:0] CrCb_out;
output [1:0] pixel_info_out;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire [17:0] data_to_fifo;
wire [17:0] data_from_fifo;
wire [7:0] read_used;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
// Output Assignments
assign buffer_has_data = (|(read_used[7:4]));
assign Y_out = data_from_fifo[ 7: 0];
assign CrCb_out = data_from_fifo[15: 8];
assign pixel_info_out = data_from_fifo[17:16];
// Internal Assignments
assign data_to_fifo[ 7: 0] = Y_in;
assign data_to_fifo[15: 8] = CrCb_in;
assign data_to_fifo[17:16] = pixel_info_in;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Dual_Clock_FIFO Video_In_Buffer (
// Inputs
.wrclk (video_in_clk),
.wrreq (valid_pixel),
.data (data_to_fifo),
.rdclk (system_clk),
.rdreq (read_buffer),
// Bidirectional
// Outputs
.rdusedw (read_used),
.q (data_from_fifo)
);
endmodule
| 7.608421 |
module resizes a video in stream. *
* *
*****************************************************************************/
module Altera_UP_Video_In_Resize (
// Inputs
clk,
reset,
pixel_data_in,
pixel_info_in,
pixel_en_in,
// Bidirectional
// Outputs
pixel_data_out,
pixel_info_out,
pixel_en_out
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [15:0] pixel_data_in;
input [1:0] pixel_info_in;
input pixel_en_in;
// Bidirectional
// Outputs
output reg [15:0] pixel_data_out;
output reg [1:0] pixel_info_out;
output reg pixel_en_out;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg keep_pixel;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
pixel_data_out <= pixel_data_in;
always @(posedge clk)
pixel_info_out <= pixel_info_in;
always @(posedge clk)
pixel_en_out <= (pixel_en_in & keep_pixel) |
(pixel_en_in & pixel_info_in[1]);
// Internal Registers
always @(posedge clk)
begin
if (reset)
keep_pixel <= 1'b0;
else if (pixel_en_in & pixel_info_in[1])
keep_pixel <= 1'b0;
else if (pixel_en_in)
keep_pixel <= keep_pixel ^ 1'b1;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
| 6.622394 |
module virtual_wire (
probe,
source
);
parameter WIDTH = 1;
parameter PROBE_WIDTH = 1;
parameter INITIAL_VALUE = " 0";
parameter INSTANCE_ID = "NONE";
input [0:PROBE_WIDTH-1] probe;
output [0:WIDTH-1] source;
`ifdef SIM
assign source = 0;
`else
altsource_probe altsource_probe_component (
.probe(probe),
.source(source)
// synopsys translate_off
, .clrn(),
.ena(),
.ir_in(),
.ir_out(),
.jtag_state_cdr(),
.jtag_state_cir(),
.jtag_state_e1dr(),
.jtag_state_sdr(),
.jtag_state_tlr(),
.jtag_state_udr(),
.jtag_state_uir(),
.raw_tck(),
.source_clk(),
.source_ena(),
.tdi(),
.tdo(),
.usr1()
// synopsys translate_on
);
defparam altsource_probe_component.enable_metastability = "NO",
altsource_probe_component.instance_id = INSTANCE_ID, altsource_probe_component.probe_width =
PROBE_WIDTH, altsource_probe_component.sld_auto_instance_index = "YES",
altsource_probe_component.sld_instance_index = 0,
altsource_probe_component.source_initial_value = INITIAL_VALUE,
altsource_probe_component.source_width = WIDTH;
`endif
endmodule
| 6.624546 |
module altera_wb_ram_8x2k (
aclr,
address,
clock,
data,
wren,
q);
input aclr;
input [10:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.aclr0 (aclr),
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "CLEAR0",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
| 6.526956 |
module altera_wb_ram_8x2k (
aclr,
address,
clock,
data,
wren,
q
);
input aclr;
input [10:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.526956 |
module sevensegment (
datain,
grounds,
display,
clk
);
input wire [15:0] datain;
output reg [3:0] grounds;
output reg [6:0] display;
input clk;
reg [ 3:0] data [3:0];
reg [ 1:0] count;
reg [25:0] clk1;
always @(posedge clk1[15]) begin
grounds <= {grounds[2:0], grounds[3]};
count <= count + 1;
end
always @(posedge clk) clk1 <= clk1 + 1;
always @(*)
case (data[count])
0: display = 7'b1111110; //starts with a, ends with g
1: display = 7'b0110000;
2: display = 7'b1101101;
3: display = 7'b1111001;
4: display = 7'b0110011;
5: display = 7'b1011011;
6: display = 7'b1011111;
7: display = 7'b1110000;
8: display = 7'b1111111;
9: display = 7'b1111011;
'ha: display = 7'b1110111;
'hb: display = 7'b0011111;
'hc: display = 7'b0110111;
'hd: display = 7'b0111101;
'he: display = 7'b1001111;
'hf: display = 7'b1000111;
//'hx:display=7';
default display = 7'b1111111;
endcase
always @* begin
data[0] = datain[15:12];
data[1] = datain[11:8];
data[2] = datain[7:4];
data[3] = datain[3:0];
end
initial begin
count = 2'b0;
grounds = 4'b1110;
clk1 = 0;
end
endmodule
| 7.484815 |
module fadd64_altbarrel_shift_32e (
aclr,
clk_en,
clock,
data,
distance,
result
);
input aclr;
input clk_en;
input clock;
input [54:0] data;
input [5:0] distance;
output [54:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dir_pipe;
reg [54:0] sbit_piper1d;
wire [6:0] dir_w;
wire direction_w;
wire [31:0] pad_w;
wire [384:0] sbit_w;
wire [5:0] sel_w;
wire [329:0] smux_w;
// synopsys translate_off
initial dir_pipe = 0;
// synopsys translate_on
always @(posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 1'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[5]};
// synopsys translate_off
initial sbit_piper1d = 0;
// synopsys translate_on
always @(posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 55'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[329:275];
assign dir_w = {
dir_pipe[0], dir_w[4:0], direction_w
},
direction_w = 1'b0,
pad_w = {32{1'b0}},
result = sbit_w[384:330],
sbit_w = {
sbit_piper1d, smux_w[274:0], data
},
sel_w = {
distance[5:0]
},
smux_w = {
((({55{(sel_w[5] & (~ dir_w[5]))}} & {sbit_w[297:275], pad_w[31:0]}) | ({55{(sel_w[5] & dir_w[5])}} & {pad_w[31:0], sbit_w[329:307]})) | ({55{(~ sel_w[5])}} & sbit_w[329:275])),
((({55{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[258:220], pad_w[15:0]}) | ({55{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[274:236]})) | ({55{(~ sel_w[4])}} & sbit_w[274:220])),
((({55{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[211:165], pad_w[7:0]}) | ({55{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[219:173]})) | ({55{(~ sel_w[3])}} & sbit_w[219:165])),
((({55{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[160:110], pad_w[3:0]}) | ({55{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[164:114]})) | ({55{(~ sel_w[2])}} & sbit_w[164:110])),
((({55{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[107:55], pad_w[1:0]}) | ({55{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[109:57]})) | ({55{(~ sel_w[1])}} & sbit_w[109:55])),
((({55{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[53:0], pad_w[0]}) | ({55{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[54:1]})) | ({55{(~ sel_w[0])}} & sbit_w[54:0]))
};
endmodule
| 6.531433 |
module fadd64_altbarrel_shift_95g (
aclr,
clk_en,
clock,
data,
distance,
result
);
input aclr;
input clk_en;
input clock;
input [54:0] data;
input [5:0] distance;
output [54:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dir_pipe;
reg [54:0] sbit_piper1d;
reg sel_pipec3r1d;
reg sel_pipec4r1d;
reg sel_pipec5r1d;
wire [6:0] dir_w;
wire direction_w;
wire [31:0] pad_w;
wire [384:0] sbit_w;
wire [5:0] sel_w;
wire [329:0] smux_w;
// synopsys translate_off
initial dir_pipe = 0;
// synopsys translate_on
always @(posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 1'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[2]};
// synopsys translate_off
initial sbit_piper1d = 0;
// synopsys translate_on
always @(posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 55'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[164:110];
// synopsys translate_off
initial sel_pipec3r1d = 0;
// synopsys translate_on
always @(posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec3r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec3r1d <= distance[3];
// synopsys translate_off
initial sel_pipec4r1d = 0;
// synopsys translate_on
always @(posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec4r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec4r1d <= distance[4];
// synopsys translate_off
initial sel_pipec5r1d = 0;
// synopsys translate_on
always @(posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec5r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec5r1d <= distance[5];
assign dir_w = {
dir_w[5:3], dir_pipe[0], dir_w[1:0], direction_w
},
direction_w = 1'b1,
pad_w = {32{1'b0}},
result = sbit_w[384:330],
sbit_w = {
smux_w[329:165], sbit_piper1d, smux_w[109:0], data
},
sel_w = {
sel_pipec5r1d, sel_pipec4r1d, sel_pipec3r1d, distance[2:0]
},
smux_w = {
((({55{(sel_w[5] & (~ dir_w[5]))}} & {sbit_w[297:275], pad_w[31:0]}) | ({55{(sel_w[5] & dir_w[5])}} & {pad_w[31:0], sbit_w[329:307]})) | ({55{(~ sel_w[5])}} & sbit_w[329:275])),
((({55{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[258:220], pad_w[15:0]}) | ({55{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[274:236]})) | ({55{(~ sel_w[4])}} & sbit_w[274:220])),
((({55{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[211:165], pad_w[7:0]}) | ({55{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[219:173]})) | ({55{(~ sel_w[3])}} & sbit_w[219:165])),
((({55{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[160:110], pad_w[3:0]}) | ({55{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[164:114]})) | ({55{(~ sel_w[2])}} & sbit_w[164:110])),
((({55{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[107:55], pad_w[1:0]}) | ({55{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[109:57]})) | ({55{(~ sel_w[1])}} & sbit_w[109:55])),
((({55{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[53:0], pad_w[0]}) | ({55{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[54:1]})) | ({55{(~ sel_w[0])}} & sbit_w[54:0]))
};
endmodule
| 6.531433 |
module fadd_altbarrel_shift_02e (
aclr,
clk_en,
clock,
data,
distance,
result
);
input aclr;
input clk_en;
input clock;
input [25:0] data;
input [4:0] distance;
output [25:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dir_pipe;
reg [25:0] sbit_piper1d;
wire [5:0] dir_w;
wire direction_w;
wire [15:0] pad_w;
wire [155:0] sbit_w;
wire [4:0] sel_w;
wire [129:0] smux_w;
// synopsys translate_off
initial dir_pipe = 0;
// synopsys translate_on
always @(posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 1'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[4]};
// synopsys translate_off
initial sbit_piper1d = 0;
// synopsys translate_on
always @(posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 26'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[129:104];
assign dir_w = {
dir_pipe[0], dir_w[3:0], direction_w
},
direction_w = 1'b0,
pad_w = {16{1'b0}},
result = sbit_w[155:130],
sbit_w = {
sbit_piper1d, smux_w[103:0], data
},
sel_w = {
distance[4:0]
},
smux_w = {
((({26{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[113:104], pad_w[15:0]}) | ({26{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[129:120]})) | ({26{(~ sel_w[4])}} & sbit_w[129:104])),
((({26{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[95:78], pad_w[7:0]}) | ({26{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[103:86]})) | ({26{(~ sel_w[3])}} & sbit_w[103:78])),
((({26{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[73:52], pad_w[3:0]}) | ({26{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[77:56]})) | ({26{(~ sel_w[2])}} & sbit_w[77:52])),
((({26{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[49:26], pad_w[1:0]}) | ({26{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[51:28]})) | ({26{(~ sel_w[1])}} & sbit_w[51:26])),
((({26{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[24:0], pad_w[0]}) | ({26{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[25:1]})) | ({26{(~ sel_w[0])}} & sbit_w[25:0]))
};
endmodule
| 6.629105 |
module fadd_altbarrel_shift_65g (
aclr,
clk_en,
clock,
data,
distance,
result
);
input aclr;
input clk_en;
input clock;
input [25:0] data;
input [4:0] distance;
output [25:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dir_pipe;
reg [25:0] sbit_piper1d;
reg sel_pipec3r1d;
reg sel_pipec4r1d;
wire [5:0] dir_w;
wire direction_w;
wire [15:0] pad_w;
wire [155:0] sbit_w;
wire [4:0] sel_w;
wire [129:0] smux_w;
// synopsys translate_off
initial dir_pipe = 0;
// synopsys translate_on
always @(posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 1'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[2]};
// synopsys translate_off
initial sbit_piper1d = 0;
// synopsys translate_on
always @(posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 26'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[77:52];
// synopsys translate_off
initial sel_pipec3r1d = 0;
// synopsys translate_on
always @(posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec3r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec3r1d <= distance[3];
// synopsys translate_off
initial sel_pipec4r1d = 0;
// synopsys translate_on
always @(posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec4r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec4r1d <= distance[4];
assign dir_w = {
dir_w[4:3], dir_pipe[0], dir_w[1:0], direction_w
},
direction_w = 1'b1,
pad_w = {16{1'b0}},
result = sbit_w[155:130],
sbit_w = {
smux_w[129:78], sbit_piper1d, smux_w[51:0], data
},
sel_w = {
sel_pipec4r1d, sel_pipec3r1d, distance[2:0]
},
smux_w = {
((({26{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[113:104], pad_w[15:0]}) | ({26{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[129:120]})) | ({26{(~ sel_w[4])}} & sbit_w[129:104])),
((({26{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[95:78], pad_w[7:0]}) | ({26{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[103:86]})) | ({26{(~ sel_w[3])}} & sbit_w[103:78])),
((({26{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[73:52], pad_w[3:0]}) | ({26{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[77:56]})) | ({26{(~ sel_w[2])}} & sbit_w[77:52])),
((({26{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[49:26], pad_w[1:0]}) | ({26{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[51:28]})) | ({26{(~ sel_w[1])}} & sbit_w[51:26])),
((({26{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[24:0], pad_w[0]}) | ({26{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[25:1]})) | ({26{(~ sel_w[0])}} & sbit_w[25:0]))
};
endmodule
| 6.629105 |
module fadd (
add_sub,
clk_en,
clock,
dataa,
datab,
result
);
input add_sub;
input clk_en;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fadd_altfp_add_sub_a0l fadd_altfp_add_sub_a0l_component (
.add_sub(add_sub),
.clk_en (clk_en),
.clock (clock),
.datab (datab),
.dataa (dataa),
.result (sub_wire0)
);
endmodule
| 6.513141 |
module altfp_convert (
aclr,
clock,
dataa,
result
);
input aclr;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
altfp_convera_altfp_convert_nfn altfp_convera_altfp_convert_nfn_component (
.aclr (aclr),
.clock (clock),
.dataa (dataa),
.result(sub_wire0)
);
endmodule
| 6.507968 |
module altfp_truncate (
clk_en,
clock,
dataa,
result
);
input clk_en;
input clock;
input [63:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
altfp_truncate_altfp_convert_bpn altfp_truncate_altfp_convert_bpn_component (
.clk_en(clk_en),
.clock (clock),
.dataa (dataa),
.result(sub_wire0)
);
endmodule
| 7.196904 |
module altfp_truncate_3 (
clk_en,
clock,
dataa,
result
);
input clk_en;
input clock;
input [63:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
altfp_truncate_altfp_convert_bpn altfp_truncate_altfp_convert_bpn_component (
.clk_en(clk_en),
.clock (clock),
.dataa (dataa),
.result(sub_wire0)
);
endmodule
| 7.196904 |
module altmemddr_ex_lfsr8 (
clk,
reset_n,
enable,
pause,
load,
data,
ldata
);
parameter seed = 32;
input clk;
input reset_n;
input enable;
input pause;
input load;
output [8 - 1:0] data;
wire [8 - 1:0] data;
input [8 - 1:0] ldata;
reg [8 - 1:0] lfsr_data;
assign data = lfsr_data;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
// Reset - asynchronously reset to seed value
lfsr_data <= seed[7:0];
end else begin
if (!enable) begin
lfsr_data <= seed[7:0];
end else begin
if (load) begin
lfsr_data <= ldata;
end else begin
// Registered mode - synchronous propagation of signals
if (!pause) begin
lfsr_data[0] <= lfsr_data[7];
lfsr_data[1] <= lfsr_data[0];
lfsr_data[2] <= lfsr_data[1] ^ lfsr_data[7];
lfsr_data[3] <= lfsr_data[2] ^ lfsr_data[7];
lfsr_data[4] <= lfsr_data[3] ^ lfsr_data[7];
lfsr_data[5] <= lfsr_data[4];
lfsr_data[6] <= lfsr_data[5];
lfsr_data[7] <= lfsr_data[6];
end
end
end
end
end
endmodule
| 7.534299 |
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