code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module altera_pli_streaming (
clk,
reset_n,
// source out
source_valid,
source_data,
source_ready,
// sink in
sink_valid,
sink_data,
sink_ready,
// resetrequest
resetrequest
);
parameter PLI_PORT = 50000;
parameter PURPOSE = 0;
input clk;
input reset_n;
ou... | 7.509563 |
module self_reset (
input wire mgmt_reset,
input wire clk,
output wire reset,
output wire init_reset
);
localparam RESET_COUNTER_VALUE = 3'd2;
localparam INITIAL_WAIT_VALUE = 9'd340;
reg [9:0] counter;
reg local_reset;
reg usr_mode_init_wait;
initial begin
local_reset = 1'b1;
coun... | 7.046284 |
module dprio_mux (
// Inputs from init block
input [ 5:0] init_dprio_address,
input init_dprio_read,
input [ 1:0] init_dprio_byteen,
input init_dprio_write,
input [15:0] init_dprio_writedata,
input init_atpgmode,
input init_mdio_dis,
input init_scanen,
input init_s... | 7.63543 |
module generic_lcell_comb #(
//parameter
parameter family = "Stratix V",
parameter lut_mask = 64'hAAAAAAAAAAAAAAAA,
parameter dont_touch = "on"
) (
input dataa,
input datab,
input datac,
input datad,
input datae,
input dataf,
output combout
);
generate
if (fami... | 7.311042 |
module altera_pll_wb_clkgen #(
parameter INPUT_FREQUENCY,
parameter WB_CLK_FREQUENCY
) (
// Main clocks in, depending on board
input sys_clk_pad_i,
// Asynchronous, active low reset in
input rst_n_pad_i,
// Input reset - through a buffer, asynchronous
output async_rst_o,
// Wishbo... | 10.244358 |
module altera_pmon_counters #(
parameter BC_W = 5
) (
input if_clock,
input if_reset,
input if_read,
input if_write,
input [BC_W-1:0] if_burstcount,
input if_waitrequest,
input if_readdatavalid,
input [1:0] addre... | 7.025613 |
module altera_pmon_count_csr (
input avs_clock,
input avs_reset,
input avs_read,
input [ 3:2] avs_address,
output reg avs_waitrequest,
output reg [31:0] avs_readdata,
output reg toglout,
output reg [ 1:0] address,
input ... | 7.025613 |
module carry (
in,
out
);
input in;
output out;
assign out = in;
endmodule
| 6.67808 |
module soft (in, out);
input in;
output out;
assign out = in;
endmodule
| 6.665932 |
module row_global (
in,
out
);
input in;
output out;
assign out = in;
endmodule
| 6.744872 |
module latch (
d,
ena,
q
);
input d, ena;
output q;
reg q;
initial q = 1'b0;
always @(d or ena) begin
if (ena) q <= d;
end
endmodule
| 6.780285 |
module dlatch (
d,
ena,
clrn,
prn,
q
);
input d, ena, clrn, prn;
output q;
reg q;
initial q = 1'b0;
always @(d or ena or clrn or prn) begin
if (clrn == 1'b0) q <= 1'b0;
else if (prn == 1'b0) q <= 1'b1;
else if (ena) q <= d;
end
endmodule
| 6.890541 |
module prim_gdff (
q,
d,
clk,
ena,
clr,
pre,
ald,
adt,
sclr,
sload
);
input d, clk, ena, clr, pre, ald, adt, sclr, sload;
output q;
reg q;
reg clk_pre;
initial q = 1'b0;
always @(clk or clr or pre or ald or adt) begin
if (clr == 1'b1) q <= 1'b0;
else if (pre ... | 6.561297 |
module dff (
d,
clk,
clrn,
prn,
q
);
input d, clk, clrn, prn;
output q;
wire q;
tri1 prn, clrn;
prim_gdff inst (
q,
d,
clk,
1'b1,
!clrn,
!prn,
1'b0,
1'b0,
1'b0,
1'b0
);
endmodule
| 7.361383 |
module dffea (
d,
clk,
ena,
clrn,
prn,
aload,
adata,
q
);
input d, clk, ena, clrn, prn, aload, adata;
output q;
wire q;
tri0 aload;
tri1 prn, clrn, ena;
reg stalled_adata;
initial begin
stalled_adata = adata;
end
always @(adata) begin
#1 stalled_adata = adata;... | 6.622625 |
module tff (
t,
clk,
clrn,
prn,
q
);
input t, clk, clrn, prn;
output q;
wire q;
tri1 prn, clrn;
prim_gtff inst (
q,
t,
clk,
1'b1,
!clrn,
!prn
);
endmodule
| 6.565161 |
module jkff (
j,
k,
clk,
clrn,
prn,
q
);
input j, k, clk, clrn, prn;
output q;
wire q;
tri1 prn, clrn;
prim_gjkff inst (
q,
j,
k,
clk,
1'b1,
!clrn,
!prn
);
endmodule
| 6.559482 |
module jkffe (
j,
k,
clk,
ena,
clrn,
prn,
q
);
input j, k, clk, ena, clrn, prn;
output q;
wire q;
tri1 prn, clrn, ena;
prim_gjkff inst (
q,
j,
k,
clk,
ena,
!clrn,
!prn
);
endmodule
| 6.564724 |
module alt_inbuf (
i,
o
);
input i;
output o;
parameter io_standard = "NONE";
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_inbuf";
assign o = i;
endmodule
| 6.532949 |
module alt_outbuf (
i,
o
);
input i;
output o;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter slow_slew_rate = "NONE";
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
paramete... | 7.424847 |
module alt_outbuf_tri (
i,
oe,
o
);
input i;
input oe;
output o;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter slow_slew_rate = "NONE";
parameter location = "NONE";
parameter enable_bus_h... | 8.389274 |
module alt_iobuf (
i,
oe,
io,
o
);
input i;
input oe;
inout io;
output o;
reg o;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter slow_slew_rate = "NONE";
parameter location = "NONE";
... | 7.605409 |
module alt_inbuf_diff (
i,
ibar,
o
);
input i;
input ibar;
output o;
parameter io_standard = "NONE";
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_inbuf_diff";
reg out... | 6.599161 |
module alt_outbuf_diff (
i,
o,
obar
);
input i;
output o;
output obar;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_... | 8.051467 |
module alt_outbuf_tri_diff (
i,
oe,
o,
obar
);
input i;
input oe;
output o;
output obar;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter location = "NONE";
parameter enable_bus_hold = "... | 8.389274 |
module alt_iobuf_diff (
i,
oe,
io,
iobar,
o
);
input i;
input oe;
inout io;
inout iobar;
output o;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter location = "NONE";
parameter ena... | 7.671053 |
module alt_bidir_diff (
oe,
bidirin,
io,
iobar
);
input oe;
inout bidirin;
inout io;
inout iobar;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter location = "NONE";
parameter enable_bus... | 6.617503 |
module carry (
in,
out
);
input in;
output out;
assign out = in;
endmodule
| 6.67808 |
module soft (in, out);
input in;
output out;
assign out = in;
endmodule
| 6.665932 |
module row_global (
in,
out
);
input in;
output out;
assign out = in;
endmodule
| 6.744872 |
module latch (
d,
ena,
q
);
input d, ena;
output q;
reg q;
initial q = 1'b0;
always @(d or ena) begin
if (ena) q <= d;
end
endmodule
| 6.780285 |
module dlatch (
d,
ena,
clrn,
prn,
q
);
input d, ena, clrn, prn;
output q;
reg q;
initial q = 1'b0;
always @(d or ena or clrn or prn) begin
if (clrn == 1'b0) q <= 1'b0;
else if (prn == 1'b0) q <= 1'b1;
else if (ena) q <= d;
end
endmodule
| 6.890541 |
module prim_gdff (
q,
d,
clk,
ena,
clr,
pre,
ald,
adt,
sclr,
sload
);
input d, clk, ena, clr, pre, ald, adt, sclr, sload;
output q;
reg q;
reg clk_pre;
initial q = 1'b0;
always @(clk or clr or pre or ald or adt) begin
if (clr == 1'b1) q <= 1'b0;
else if (pre ... | 6.561297 |
module dff (
d,
clk,
clrn,
prn,
q
);
input d, clk, clrn, prn;
output q;
wire q;
tri1 prn, clrn;
prim_gdff inst (
q,
d,
clk,
1'b1,
!clrn,
!prn,
1'b0,
1'b0,
1'b0,
1'b0
);
endmodule
| 7.361383 |
module dffea (
d,
clk,
ena,
clrn,
prn,
aload,
adata,
q
);
input d, clk, ena, clrn, prn, aload, adata;
output q;
wire q;
tri0 aload;
tri1 prn, clrn, ena;
reg stalled_adata;
initial begin
stalled_adata = adata;
end
always @(adata) begin
#1 stalled_adata = adata;... | 6.622625 |
module tff (
t,
clk,
clrn,
prn,
q
);
input t, clk, clrn, prn;
output q;
wire q;
tri1 prn, clrn;
prim_gtff inst (
q,
t,
clk,
1'b1,
!clrn,
!prn
);
endmodule
| 6.565161 |
module jkff (
j,
k,
clk,
clrn,
prn,
q
);
input j, k, clk, clrn, prn;
output q;
wire q;
tri1 prn, clrn;
prim_gjkff inst (
q,
j,
k,
clk,
1'b1,
!clrn,
!prn
);
endmodule
| 6.559482 |
module jkffe (
j,
k,
clk,
ena,
clrn,
prn,
q
);
input j, k, clk, ena, clrn, prn;
output q;
wire q;
tri1 prn, clrn, ena;
prim_gjkff inst (
q,
j,
k,
clk,
ena,
!clrn,
!prn
);
endmodule
| 6.564724 |
module alt_inbuf (
i,
o
);
input i;
output o;
parameter io_standard = "NONE";
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_inbuf";
assign o = i;
endmodule
| 6.532949 |
module alt_outbuf (
i,
o
);
input i;
output o;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter slow_slew_rate = "NONE";
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
paramete... | 7.424847 |
module alt_outbuf_tri (
i,
oe,
o
);
input i;
input oe;
output o;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter slow_slew_rate = "NONE";
parameter location = "NONE";
parameter enable_bus_h... | 8.389274 |
module alt_iobuf (
i,
oe,
io,
o
);
input i;
input oe;
inout io;
output o;
reg o;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter slow_slew_rate = "NONE";
parameter location = "NONE";
... | 7.605409 |
module alt_inbuf_diff (
i,
ibar,
o
);
input i;
input ibar;
output o;
parameter io_standard = "NONE";
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_inbuf_diff";
reg out... | 6.599161 |
module alt_outbuf_diff (
i,
o,
obar
);
input i;
output o;
output obar;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_... | 8.051467 |
module alt_outbuf_tri_diff (
i,
oe,
o,
obar
);
input i;
input oe;
output o;
output obar;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter location = "NONE";
parameter enable_bus_hold = "... | 8.389274 |
module alt_iobuf_diff (
i,
oe,
io,
iobar,
o
);
input i;
input oe;
inout io;
inout iobar;
output o;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter location = "NONE";
parameter ena... | 7.671053 |
module alt_bidir_diff (
oe,
bidirin,
io,
iobar
);
input oe;
inout bidirin;
inout io;
inout iobar;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter location = "NONE";
parameter enable_bus... | 6.617503 |
module altera_primitive_dualram_512bit_16word (
byteena_a,
clock,
data,
rdaddress,
wraddress,
wren,
q);
input [63:0] byteena_a;
input clock;
input [511:0] data;
input [3:0] rdaddress;
input [3:0] wraddress;
input wren;
output [511:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endi... | 7.310839 |
module altera_primitive_ram_64bit_32768word (
address,
byteena,
clock,
data,
wren,
q);
input [14:0] address;
input [7:0] byteena;
input clock;
input [63:0] data;
input wren;
output [63:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [7:0] byteena;
tri1 clock;
`ifndef AL... | 7.310839 |
module altera_primitive_sync_fifo_showahead_97in_97out_32depth (
aclr,
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q,
usedw
);
input aclr;
input clock;
input [96:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [96:0] q;
outp... | 7.310839 |
module altera_primitive_sync_fifo_showahead_97in_97out_32depth (
aclr,
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q,
usedw
);
input aclr;
input clock;
input [96:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [96:0] q;
outp... | 7.310839 |
module altera_reset_synchronizer #(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
) (
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. W... | 8.176669 |
module altera_reset_synchronizer #(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
) (
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. W... | 8.176669 |
module altera_reset_synchronizer_0 #(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
) (
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain.... | 8.176669 |
module RxD_fifo #(
parameter Dw = 72, //data_width
parameter B = 10 // buffer num
) (
din,
wr_en,
rd_en,
dout,
full,
nearly_full,
empty,
reset,
clk
);
function integer log2;
input integer number;
begin
log2 = (number <= 1) ? 1 : 0;
while (2 ** log2... | 6.524137 |
module altera_spram #(
parameter DEVICE_ID = "Stratix IV" , //
BRAM_TYPE = "M9K" , //
RAM_DO_REG = 0 , //
RAM_WIDTH = 8 , //
RAM_DEEP = 10 //
)(
input ... | 6.545549 |
module altera_std_synchronizer (
clk,
reset_n,
din,
dout
);
parameter depth = 3; // This value must be >= 2 !
input clk;
input reset_n;
input din;
output dout;
// QuartusII synthesis directives:
// 1. Preserve all registers ie. do not touch them.
// 2. Do not merge other flip... | 7.854645 |
module altera_sync_ram_1p (
clk_i,
adr_i,
be_i,
wren_i,
dat_i,
dat_o
);
parameter AW = 10;
parameter DW = 32;
parameter INIT_MEM_FILE = "";
localparam DEPTH = (1 << AW);
input clk_i;
input [AW-1:0] adr_i;
input [(DW/8)-1:0] be_i;
input wren_i;
input [DW-1:0] dat_i;
output [DW-1:0] dat_o;
// data... | 6.775597 |
module altera_sync_rom_1p (
clk_i,
adr_i,
dat_o
);
parameter AW = 10;
parameter DW = 32;
parameter INIT_MEM_FILE = "";
localparam DEPTH = (1 << AW);
input clk_i;
input [AW-1:0] adr_i;
output [DW-1:0] dat_o;
// data q is not register output
// if data q is register output,
// data is r... | 6.775597 |
module designed to retun values based for trace.
// address used is variabel size (based on number of distilers.
`default_nettype none
module altera_trace_rom #(
parameter NUM_REGS = 2,
parameter REG_VALUE_STRING = "FEDCBA9876543210", // also used as default value
parameter ADDR_WIDTH ... | 7.539467 |
module altera_tse_alt4gxb_gige (
cal_blk_clk,
fixedclk,
fixedclk_fast,
gxb_powerdown,
pll_inclk,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_datain,
rx_digitalreset,
rx_seriallpbken,
tx_ctrlenable,
tx_datain,
tx_digitalreset,
reconfig_fromg... | 7.477524 |
module altera_tse_altgxb #(
parameter DEVICE_FAMILY = "ARRIAGX", // The device family the the core is targetted for.
parameter STARTING_CHANNEL_NUMBER = 0,
parameter ENABLE_ALT_RECONFIG = 0,
parameter ENABLE_SGMII = 1, // Use to determine rate match FIFO in ALTGX GIGE mode
parameter RECONFIG_TO... | 7.477524 |
module altera_tse_fake_master (
// Clock and reset
input clk,
input reset,
// Avalon MM master interface
output [8:0] phy_mgmt_address,
output phy_mgmt_read,
input [31:0] phy_mgmt_readdata,
output phy_mgmt_write,
output reg [31:0] phy_mgmt_writedata,
input phy_mgmt_waitrequest,
... | 9.018435 |
module altera_tse_lvds_reset_sequencer (
clk,
reset,
rx_locked,
rx_channel_data_align,
pll_areset,
rx_reset,
rx_cda_reset
);
input clk;
input reset;
input rx_locked;
output rx_channel_data_align;
output pll_areset;
output rx_reset;
output rx_cda_reset;
reg rx_channel_data_a... | 8.126096 |
module altera_tse_reset_synchronizer #(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
) (
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,R105\"" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer regi... | 7.285704 |
module.
//
// Parameters:
// SYNC_CHAIN_LENGTH
// - Specifies the length of the synchronizer chain for metastability
// retiming.
// WIDTH
// - Specifies the number of bits you want to synchronize. Controls the width of the
// d and q ports.
// SLOW_CLOCK - USE WITH CAUTION.
// ... | 8.162755 |
module RxD_fifo #(
parameter Dw = 72, //data_width
parameter B = 10 // buffer num
) (
din,
wr_en,
rd_en,
dout,
full,
nearly_full,
empty,
reset,
clk
);
function integer log2;
input integer number;
begin
log2 = (number <= 1) ? 1 : 0;
while (2 ** log2... | 6.524137 |
module Altera_unique_chip_ID (
input wire clkin, // clkin.clk
input wire reset, // reset.reset
output wire data_valid, // output.valid
output wire [63:0] chip_id // .data
);
altchip_id #(
.DEVICE_FAMILY("MAX 10"),
.ID_VALUE (64'b1111111... | 7.184465 |
module is a rom for auto initializing the accelerometer on the *
* DE-Nano. *
* *
******************************************************************************/
module... | 7.432195 |
module loads data into the Audio and Video chips' control *
* registers after system reset. *
* *
******************************************************************************/
module... | 6.814331 |
module counts which bits for serial audio transfers. The module *
* assume that the data format is I2S, as it is described in the audio *
* chip's datasheet. *
* *
*********... | 8.853421 |
module is used to create a reset from the clock locked signal. *
* *
******************************************************************************/
module altera_up_avalon_reset_from_locked_signal (
// Inputs
locked,
// Bidirectiona... | 7.719387 |
module is an adapter for the UP Video DMA Controller. It translates *
* the address of the front and back buffers by a fixed offset. This is *
* required when the addresses to memory differ for the DMA and the *
* processor, as in the case of the ARM processor. *
* ... | 8.31907 |
module is an adapter for the UP Video DMA Controller. It translates *
* the address of the front and back buffers by a fixed offset. This is *
* required when the addresses to memory differ for the DMA and the *
* processor, as in the case of the ARM processor. *
* ... | 8.31907 |
module loads data into the Audio and Video chips' control *
* registers after system reset. *
* *
******************************************************************************/
module... | 6.814331 |
module is a rom for auto initializing the TRDB LTM lcd screen. *
* *
******************************************************************************/
module altera_up_av_config_auto_init_ltm (
// Inputs
rom_address,
// Bidirectional... | 7.432195 |
module is a rom for auto initializing the on board audio chip. *
* *
******************************************************************************/
module altera_up_av_config_auto_init_ob_audio (
// Inputs
rom_address,
// Bidirect... | 7.432195 |
module is a rom for auto initializing the on board periphal devices *
* on the DE10-Standard board. *
* *
******************************************************************************/
module... | 7.432195 |
module is a rom for auto initializing the on board periphal devices *
* on the DE1-SoC board. *
* *
******************************************************************************/
module... | 7.432195 |
module is a rom for auto initializing the on board periphal devices *
* on the DE2i-150 board. *
* *
******************************************************************************/
modul... | 7.432195 |
module is a rom for auto initializing the on board periphal devices *
* on the DE2-115 board. *
* *
******************************************************************************/
module... | 7.432195 |
module is a rom for auto initializing the on board periphal devices *
* on the DE2-70 board. *
* *
******************************************************************************/
module... | 7.432195 |
module finds clock edges of one clock at the frequency of *
* another clock. *
* *
******************************************************************************/
module... | 9.523667 |
module is a FIFO with same clock for both reads and writes. *
* *
******************************************************************************/
module Altera_UP_SYNC_FIFO (
// Inputs
clk,
reset,
write_en,
write_data,
read_... | 7.352627 |
module contains a character map for 128 different ASCII characters. *
* *
******************************************************************************/
module altera_up_video_ascii_rom_128 (
// Inputs
clk,
clk_en,
character,
x_coord... | 7.224432 |
module store the video input stream to be processed. *
* *
*****************************************************************************/
module Altera_UP_Video_In_Buffer (
// Inputs
system_clk,
video_in_clk,
reset,
Y_in,
CrC... | 7.608421 |
module resizes a video in stream. *
* *
*****************************************************************************/
module Altera_UP_Video_In_Resize (
// Inputs
clk,
reset,
pixel_data_in,
pixel_info_in,
... | 6.622394 |
module virtual_wire (
probe,
source
);
parameter WIDTH = 1;
parameter PROBE_WIDTH = 1;
parameter INITIAL_VALUE = " 0";
parameter INSTANCE_ID = "NONE";
input [0:PROBE_WIDTH-1] probe;
output [0:WIDTH-1] source;
`ifdef SIM
assign source = 0;
`else
altsource_probe altsource_probe_component (
... | 6.624546 |
module altera_wb_ram_8x2k (
aclr,
address,
clock,
data,
wren,
q);
input aclr;
input [10:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate... | 6.526956 |
module altera_wb_ram_8x2k (
aclr,
address,
clock,
data,
wren,
q
);
input aclr;
input [10:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// ... | 6.526956 |
module sevensegment (
datain,
grounds,
display,
clk
);
input wire [15:0] datain;
output reg [3:0] grounds;
output reg [6:0] display;
input clk;
reg [ 3:0] data [3:0];
reg [ 1:0] count;
reg [25:0] clk1;
always @(posedge clk1[15]) begin
grounds <= {grounds[2:0], grounds[3]};
coun... | 7.484815 |
module fadd64_altbarrel_shift_32e (
aclr,
clk_en,
clock,
data,
distance,
result
);
input aclr;
input clk_en;
input clock;
input [54:0] data;
input [5:0] distance;
output [54:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 c... | 6.531433 |
module fadd64_altbarrel_shift_95g (
aclr,
clk_en,
clock,
data,
distance,
result
);
input aclr;
input clk_en;
input clock;
input [54:0] data;
input [5:0] distance;
output [54:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 c... | 6.531433 |
module fadd_altbarrel_shift_02e (
aclr,
clk_en,
clock,
data,
distance,
result
);
input aclr;
input clk_en;
input clock;
input [25:0] data;
input [4:0] distance;
output [25:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clo... | 6.629105 |
module fadd_altbarrel_shift_65g (
aclr,
clk_en,
clock,
data,
distance,
result
);
input aclr;
input clk_en;
input clock;
input [25:0] data;
input [4:0] distance;
output [25:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clo... | 6.629105 |
module fadd (
add_sub,
clk_en,
clock,
dataa,
datab,
result
);
input add_sub;
input clk_en;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fadd_altfp_add_sub_a0l fadd_altfp_add_sub_a0l_co... | 6.513141 |
module altfp_convert (
aclr,
clock,
dataa,
result
);
input aclr;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
altfp_convera_altfp_convert_nfn altfp_convera_altfp_convert_nfn_component (
.aclr (aclr),
.cl... | 6.507968 |
module altfp_truncate (
clk_en,
clock,
dataa,
result
);
input clk_en;
input clock;
input [63:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
altfp_truncate_altfp_convert_bpn altfp_truncate_altfp_convert_bpn_component (
.clk_en(clk_en),
... | 7.196904 |
module altfp_truncate_3 (
clk_en,
clock,
dataa,
result
);
input clk_en;
input clock;
input [63:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
altfp_truncate_altfp_convert_bpn altfp_truncate_altfp_convert_bpn_component (
.clk_en(clk_en)... | 7.196904 |
module altmemddr_ex_lfsr8 (
clk,
reset_n,
enable,
pause,
load,
data,
ldata
);
parameter seed = 32;
input clk;
input reset_n;
input enable;
input pause;
input load;
output [8 - 1:0] data;
wire [8 - 1:0] data;
input [8 - 1:0] ldata;
reg [8 - 1:0] lfsr_data;
assign data... | 7.534299 |
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