code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module mux2to1_16 (
input [15:0] inp1,
input [15:0] inp2,
input sel,
output reg [15:0] muxOut
);
always @(inp1, inp2, sel) begin
if (sel == 1'b0) muxOut = inp1;
else muxOut = inp2;
end
endmodule
| 7.41547 |
module mux3to1 (
input [15:0] inp1,
inp2,
inp3,
input [1:0] sel,
output reg [15:0] muxOut
);
always @(inp1, inp2, inp3, sel) begin
if (sel == 2'b00) muxOut = inp1;
else if (sel == 2'b01) muxOut = inp2;
else muxOut = inp3;
end
endmodule
| 6.860137 |
module PCMux3to1 (
input [15:0] inp1,
inp2,
inp3,
input [1:0] sel,
output reg [15:0] muxOut
);
always @(inp1, inp2, inp3, sel) begin
if (sel == 2'b01) muxOut = inp2;
else if (sel == 2'b10) muxOut = inp3;
else muxOut = inp1;
end
endmodule
| 6.594744 |
module forwardingUnit (
input [2:0] presentRs,
input [2:0] presentRt,
input [2:0] exmemRd,
input [2:0] memwbRd,
input exmemregwrite,
input memwbregwrite,
output reg [1:0] muxsourcea
);
always @(presentRs, presentRt, exmemRd, memwbRd, exmemregwrite, memwbregwrite) begin
if (exmemregwrite == 1 && exmemRd == presentRs) muxsourcea = 2'b01;
else begin
if (memwbregwrite == 1 && memwbRd == presentRs) muxsourcea = 2'b10;
else muxsourcea = 2'b00;
end
/* if(exmemregwrite == 1 && exmemRd == presentRt)
muxsourceb = 2'b01;
else
begin
if( memwbregwrite == 1 && memwbRd == presentRt)
muxsourceb = 2'b10;
else
muxsourceb = 2'b00;
end */
end
endmodule
| 6.627011 |
module dataMem (
input clk,
input reset,
input regWrite,
input decOut1b,
input [7:0] init,
input [7:0] d_in,
output [7:0] q_out
);
D_ff_Mem dMem0 (
clk,
reset,
regWrite,
decOut1b,
init[0],
d_in[0],
q_out[0]
);
D_ff_Mem dMem1 (
clk,
reset,
regWrite,
decOut1b,
init[1],
d_in[1],
q_out[1]
);
D_ff_Mem dMem2 (
clk,
reset,
regWrite,
decOut1b,
init[2],
d_in[2],
q_out[2]
);
D_ff_Mem dMem3 (
clk,
reset,
regWrite,
decOut1b,
init[3],
d_in[3],
q_out[3]
);
D_ff_Mem dMem4 (
clk,
reset,
regWrite,
decOut1b,
init[4],
d_in[4],
q_out[4]
);
D_ff_Mem dMem5 (
clk,
reset,
regWrite,
decOut1b,
init[5],
d_in[5],
q_out[5]
);
D_ff_Mem dMem6 (
clk,
reset,
regWrite,
decOut1b,
init[6],
d_in[6],
q_out[6]
);
D_ff_Mem dMem7 (
clk,
reset,
regWrite,
decOut1b,
init[7],
d_in[7],
q_out[7]
);
endmodule
| 6.754704 |
module alu (
opcode, // alu function select
a, // a operand
b, // b operand
cin, // carry input
ya, // data output
yb, // data output
cvnz_a, // a output flags
cvnz_b // b output flags
);
input [2:0] opcode;
input [31:0] a;
input [31:0] b;
input cin;
output [31:0] ya;
reg [31:0] ya;
output [31:0] yb;
reg [31:0] yb;
output [3:0] cvnz_a;
output [3:0] cvnz_b;
// Flags: c: indicates that a carry has occurred
// z: indicates that the result is zero
// v: indicates that an overflow has occurred
// n: indicates a negative result
reg c_flag_a; // c flag for output a
reg v_flag_a; // v flag for output a
wire n_flag_a; // n flag for output a
wire z_flag_a; // z flag for output a
reg c_flag_b; // c flag for output b
reg v_flag_b; // v flag for output b
wire n_flag_b; // n flag for output b
wire z_flag_b; // z flag for output b
assign cvnz_a = {c_flag_a, v_flag_a, n_flag_a, z_flag_a};
assign cvnz_b = {c_flag_b, v_flag_b, n_flag_b, z_flag_b};
wire [31:0] b_se; // b input sign extended from 16-bits
// Operations:
//
// Opcode Function ya yb
// ------ ---------- ------------- -------------
// 000 pass a b
// 001 add a + b a + b(se)
// 010 sub a - b a - b(se)
// 011 mult a * b [31:0] a * b [63:32]
// 100 and/or a & b a | b
// 101 xor/xnor a ^ b ~(a ^ b)
// 110 (reserved) --- ---
// 111 flip_pass a[15:0,31:16] b[15:0,31:16]
assign b_se = {{16{b[15]}}, b[15:0]};
always @(opcode or a or b or b_se or cin) begin
ya = 'b0;
yb = 'b0;
c_flag_a = 'b0;
v_flag_a = 'b0;
c_flag_b = 'b0;
v_flag_b = 'b0;
case (opcode)
3'd0: begin // pass through (similar to a noop)
ya = a;
yb = b;
end
3'd1: begin // add
{c_flag_a, ya} = a + b + cin;
{c_flag_b, yb} = a + b_se + cin;
v_flag_a = (~a[31] && ~b[31] && ya[31]) || (a[31] && b[31] && ~ya[31]);
v_flag_b = (~a[31] && ~b_se[31] && yb[31]) || (a[31] && b_se[31] && ~yb[31]);
end
3'd2: begin // subtract
ya = a - b - cin;
yb = a - b_se - cin;
if (b + cin > a) c_flag_a = 1'b1;
if (b_se + cin > a) c_flag_b = 1'b1;
v_flag_a = (~a[31] & b[31] & ya[31]) || (a[31] & ~b[31] & ~ya[31]);
v_flag_b = (~a[31] & b[31] & yb[31]) || (a[31] & ~b[31] & ~yb[31]);
end
3'd3: begin //mult
{yb, ya} = a * b;
end
3'd4: begin // logical and / or of a, b
ya = a & b;
yb = a | b;
end
3'd5: begin // logical xor of a, b
ya = a ^ b;
yb = ~(a ^ b);
end
3'd7: begin // byte-flipped pass through
ya = {a[15:0], a[31:16]};
yb = {b[15:0], b[31:16]};
end
endcase
end
assign n_flag_a = ya[31];
assign z_flag_a = !ya;
assign n_flag_b = yb[31];
assign z_flag_b = !yb;
endmodule
| 7.673494 |
module testALU (
x,
y,
opcode,
f,
overflow,
cout,
zero
);
input [31:0] f;
input cout, overflow, zero;
output [31:0] x, y;
output [2:0] opcode;
reg [31:0] x, y;
reg [2:0] opcode;
assign overflow = 0;
always @(f) begin
$display($time);
end
initial begin
if ($value$plusargs(
"x=%b", x
) && $value$plusargs(
"y=%b", y
) && $value$plusargs(
"opcode=%b", opcode
)) begin
//$display("x=%b, y=%b, opcode=%d",x,y,opcode);
assign x = x;
assign y = y;
assign opcode = opcode;
end
end
endmodule
| 7.063407 |
module alu (
x,
y,
opcode,
f,
overflow,
cout,
zero
);
input [31:0] x, y;
input [2:0] opcode;
output overflow, zero, cout;
output [31:0] f;
wire [2:0] opoverflow;
wire [31:0] f0, f1, f2, f3, f4, result;
wire w5, zero, isoverflowed, cout;
add op0 (
x,
y,
f0,
opoverflow[0],
zero
);
bitwiseor op1 (
x,
y,
f1
);
bitwiseand op2 (
x,
y,
f2
);
sub op3 (
x,
y,
f3,
opoverflow[1]
);
slt op4 (
x,
y,
f4,
opoverflow[2]
);
out outputselector (
f0,
f1,
f2,
f3,
f4,
opcode[0],
opcode[1],
opcode[2],
opoverflow[0],
opoverflow[1],
opoverflow[2],
f,
isoverflowed,
cout
);
iszero zerochecker (
f,
zero
);
endmodule
| 7.914753 |
module fulladder (
a,
b,
c,
s,
cout
);
input a, b, c;
output s, cout;
xor #3 g1 (w1, a, b), g2 (s, w1, c);
and #2 g3 (w2, c, b), g4 (w3, c, a), g5 (w4, a, b);
or #6 g6 (cout, w2, w3, w4);
endmodule
| 7.454465 |
module mux8to1 (
d0,
d1,
d2,
d3,
d4,
d5,
d6,
d7,
s0,
s1,
s2,
f
);
input d0, d1, d2, d3, d4, d5, d6, d7, s0, s1, s2;
output f;
mux4to1 mux0 (
d0,
d1,
d2,
d3,
s0,
s1,
w1
);
mux4to1 mux1 (
d4,
d5,
d6,
d7,
s0,
s1,
w2
);
mux2to1 mux2 (
w1,
w2,
s2,
f
);
endmodule
| 7.465042 |
module mux4to1 (
d0,
d1,
d2,
d3,
s0,
s1,
f
);
input d0, d1, d2, d3, s0, s1;
output f;
mux2to1 mux0 (
d0,
d1,
s0,
w1
);
mux2to1 mux1 (
d2,
d3,
s0,
w2
);
mux2to1 mux2 (
w1,
w2,
s1,
f
);
endmodule
| 7.010477 |
module mux2to1 (
d0,
d1,
s0,
f
);
input d0, d1, s0;
output f;
and #2(w17, d1, s0);
not #1(w15, s0);
and #2(w18, w15, d0);
or #6(f, w17, w18);
endmodule
| 7.107199 |
module testALU (
x,
y,
opcode,
f,
overflow,
cout,
zero
);
input [31:0] f;
input cout, overflow, zero;
output [31:0] x, y;
output [2:0] opcode;
reg [31:0] x, y;
reg [2:0] opcode;
assign overflow = 0;
initial begin
/*
$display("====================================================================================");
$display(" 32 bit ALU Functional Simulation (unit delay) ");
$display(" Author: Robert Shannon ");
$display(" Email: rshannon@buffalo.edu ");
$display("====================================================================================");
*/
// Example #1 - ADD
x = 1024;
y = 128;
opcode = 0;
#94
$display(
$time,
,
"1. x=%d, y=%d, opcode=%b, f=%d, overflow=%b, zero=%d, cout=%b",
x,
y,
opcode,
f,
overflow,
zero,
cout
);
x = 842;
y = 986;
opcode = 0;
#113
$display(
$time,
,
"1. x=%d, y=%d, opcode=%b, f=%d, overflow=%b, zero=%d, cout=%b",
x,
y,
opcode,
f,
overflow,
zero,
cout
);
x = 1024;
y = 128;
opcode = 0;
#93
$display(
$time,
,
"1. x=%d, y=%d, opcode=%b, f=%d, overflow=%b, zero=%d, cout=%b",
x,
y,
opcode,
f,
overflow,
zero,
cout
);
// Example #2 - SUB
/*
x=8108; y=9375; opcode=3;
#202 $display ($time,,"1. x=%d, y=%d, opcode=%b, f=%b, overflow=%b, zero=%d, cout=%b",x,y,opcode,f,overflow, zero,cout);
x=842; y=986; opcode=3;
#231 $display ($time,,"1. x=%d, y=%d, opcode=%b, f=%b, overflow=%b, zero=%d, cout=%b",x,y,opcode,f,overflow, zero,cout);
x=8108; y=9375; opcode=3;
#199 $display ($time,,"1. x=%d, y=%d, opcode=%b, f=%b, overflow=%b, zero=%d, cout=%b",x,y,opcode,f,overflow, zero,cout);
*/
// Example #3 - AND
/*
x=32'b00100011100011101000111010110101; y=32'b10111101011001001101011111110110; opcode=2;
#57 $display ($time,,"1. x=%b, y=%b, opcode=%b, f=%b, overflow=%b, zero=%d, cout=%b",x,y,opcode,f,overflow, zero,cout);
x=32'b10101011100100001101011000001011; y=32'b00010100011110101110000000010011; opcode=2;
#57 $display ($time,,"1. x=%b, y=%b, opcode=%b, f=%b, overflow=%b, zero=%d, cout=%b",x,y,opcode,f,overflow, zero,cout);
x=32'b00100011100011101000111010110101; y=32'b10111101011001001101011111110110; opcode=2;
#57 $display ($time,,"1. x=%b, y=%b, opcode=%b, f=%b, overflow=%b, zero=%d, cout=%b",x,y,opcode,f,overflow, zero,cout);
*/
// Example #4 - OR
/*
x=32'b10111101111011000011100011101110; y=32'b11101011110011110011111101010100; opcode=1;
#61 $display ($time,,"1. x=%b, y=%b, opcode=%b, f=%b, overflow=%b, zero=%d, cout=%b",x,y,opcode,f,overflow, zero,cout);
x=32'b00010110010000100000101010001111; y=32'b11001111111010000100011000111011; opcode=1;
#61 $display ($time,,"1. x=%b, y=%b, opcode=%b, f=%b, overflow=%b, zero=%d, cout=%b",x,y,opcode,f,overflow, zero,cout);
x=32'b10111101111011000011100011101110; y=32'b11101011110011110011111101010100; opcode=1;
#61 $display ($time,,"1. x=%b, y=%b, opcode=%b, f=%b, overflow=%b, zero=%d, cout=%b",x,y,opcode,f,overflow, zero,cout);
*/
// Example #5 - SLT
/*
x=71; y=57; opcode=4;
#273 $display ($time,,"1. x=%d, y=%d, opcode=%b, f=%d, overflow=%b, zero=%d, cout=%b",x,y,opcode,f,overflow, zero,cout);
x=11; y=57; opcode=4;
#278 $display ($time,,"1. x=%d, y=%d, opcode=%b, f=%d, overflow=%b, zero=%d, cout=%b",x,y,opcode,f,overflow, zero,cout);
x=71; y=57; opcode=4;
#273 $display ($time,,"1. x=%d, y=%d, opcode=%b, f=%d, overflow=%b, zero=%d, cout=%b",x,y,opcode,f,overflow, zero,cout);
*/
end
endmodule
| 7.063407 |
module alu (
x,
y,
opcode,
f,
overflow,
cout,
zero
);
input [31:0] x, y;
input [2:0] opcode;
output overflow, zero, cout;
output [31:0] f;
wire [2:0] opoverflow;
wire [31:0] f0, f1, f2, f3, f4, result;
wire w5, zero, isoverflowed, cout;
add op0 (
x,
y,
f0,
opoverflow[0],
zero
);
bitwiseor op1 (
x,
y,
f1
);
bitwiseand op2 (
x,
y,
f2
);
sub op3 (
x,
y,
f3,
opoverflow[1]
);
slt op4 (
x,
y,
f4,
opoverflow[2]
);
out outputselector (
f0,
f1,
f2,
f3,
f4,
opcode[0],
opcode[1],
opcode[2],
opoverflow[0],
opoverflow[1],
opoverflow[2],
f,
isoverflowed,
cout
);
iszero zerochecker (
f,
zero
);
endmodule
| 7.914753 |
module fulladder (
a,
b,
c,
s,
cout
);
input a, b, c;
output s, cout;
xor #3 g1 (w1, a, b), g2 (s, w1, c);
and #2 g3 (w2, c, b), g4 (w3, c, a), g5 (w4, a, b);
or #6 g6 (cout, w2, w3, w4);
endmodule
| 7.454465 |
module mux8to1 (
d0,
d1,
d2,
d3,
d4,
d5,
d6,
d7,
s0,
s1,
s2,
f
);
input d0, d1, d2, d3, d4, d5, d6, d7, s0, s1, s2;
output f;
mux4to1 mux0 (
d0,
d1,
d2,
d3,
s0,
s1,
w1
);
mux4to1 mux1 (
d4,
d5,
d6,
d7,
s0,
s1,
w2
);
mux2to1 mux2 (
w1,
w2,
s2,
f
);
endmodule
| 7.465042 |
module mux4to1 (
d0,
d1,
d2,
d3,
s0,
s1,
f
);
input d0, d1, d2, d3, s0, s1;
output f;
mux2to1 mux0 (
d0,
d1,
s0,
w1
);
mux2to1 mux1 (
d2,
d3,
s0,
w2
);
mux2to1 mux2 (
w1,
w2,
s1,
f
);
endmodule
| 7.010477 |
module mux2to1 (
d0,
d1,
s0,
f
);
input d0, d1, s0;
output f;
and #2(w17, d1, s0);
not #1(w15, s0);
and #2(w18, w15, d0);
or #6(f, w17, w18);
endmodule
| 7.107199 |
module ALU_reg (
clk,
alu_out,
alu_out_reg,
dm_addr,
dm_addr_reg
); //存储ALU计算结果和dm地址
input clk;
input [31:0] alu_out;
output reg [31:0] alu_out_reg;
input [9:0] dm_addr;
output reg [9:0] dm_addr_reg;
always @(posedge clk) begin
alu_out_reg <= alu_out;
dm_addr_reg <= dm_addr;
end
endmodule
| 7.556625 |
module ALU_Reg1_Mux (
sel,
reg1_val,
mem_forward,
wb_forward,
alu_val1
);
input [1:0] sel;
input [15:0] reg1_val, mem_forward, wb_forward;
output reg [15:0] alu_val1;
always @(*) begin
case (sel)
0: alu_val1 = reg1_val;
1: alu_val1 = mem_forward;
2: alu_val1 = wb_forward;
endcase
end
endmodule
| 7.362679 |
module ALU_Reg2_Mux (
sel,
reg2_val,
mem_forward,
wb_forward,
se_const,
alu_val2
);
input [1:0] sel;
input [15:0] reg2_val, mem_forward, wb_forward, se_const;
output reg [15:0] alu_val2;
always @(*) begin
case (sel)
0: alu_val2 = reg2_val;
1: alu_val2 = mem_forward;
2: alu_val2 = wb_forward;
3: alu_val2 = se_const;
endcase
end
endmodule
| 7.38686 |
module ALU_Register (
// System Signals
input clk,
input rst,
// Values In
input [7:0] bus,
// Control signals registers
input AI,
input BI,
input SUB,
// Flags
output CARRY,
output ZERO,
// Output Values
output [7:0] A_out,
output [7:0] B_out,
output [7:0] E_out
);
ALU ALU (
.A(A_out),
.B(B_out),
.SUB(SUB),
.data_out(E_out),
.CARRY(CARRY),
.ZERO (ZERO)
);
register_array register_array (
.clk(clk),
.rst(rst),
.bus(bus),
.AI(AI),
.BI(BI),
.A(A_out),
.B(B_out)
);
endmodule
| 6.599559 |
module ALU_registerfile (
clk,
reset_n,
wAddr,
wData,
we,
rAddr,
rData
); //register file with 16 data
input clk, reset_n, we;
input [3:0] wAddr, rAddr;
input [31:0] wData;
output reg [31:0] rData;
reg [31:0] data0;
reg [31:0] data1;
reg [31:0] data2;
reg [31:0] data3;
reg [31:0] data4;
reg [31:0] data5;
reg [31:0] data6;
reg [31:0] data7;
reg [31:0] data8;
reg [31:0] data9;
reg [31:0] data10;
reg [31:0] data11;
reg [31:0] data12;
reg [31:0] data13;
reg [31:0] data14;
reg [31:0] data15; //16 data
always @(posedge clk or negedge reset_n) begin
if (reset_n == 1'b0) begin
data0 = 32'h0000_0000;
data1 = 32'h0000_0000;
data2 = 32'h0000_0000;
data3 = 32'h0000_0000;
data4 = 32'h0000_0000;
data5 = 32'h0000_0000;
data6 = 32'h0000_0000;
data7 = 32'h0000_0000;
data8 = 32'h0000_0000;
data9 = 32'h0000_0000;
data10 = 32'h0000_0000;
data11 = 32'h0000_0000;
data12 = 32'h0000_0000;
data13 = 32'h0000_0000;
data14 = 32'h0000_0000;
data15 = 32'h0000_0000; //reset all data
end else if (clk == 1'b1) begin
if (we == 1'b1) //write
begin
case (wAddr)
4'b0000: data0 = wData;
4'b0001: data1 = wData;
4'b0010: data2 = wData;
4'b0011: data3 = wData;
4'b0100: data4 = wData;
4'b0101: data5 = wData;
4'b0110: data6 = wData;
4'b0111: data7 = wData;
4'b1000: data8 = wData;
4'b1001: data9 = wData;
4'b1010: data10 = wData;
4'b1011: data11 = wData;
4'b1100: data12 = wData;
4'b1101: data13 = wData;
4'b1110: data14 = wData;
4'b1111: data15 = wData;
endcase
end
else if (we == 1'b0) //read
begin
case (rAddr)
4'b0000: rData = data0;
4'b0001: rData = data1;
4'b0010: rData = data2;
4'b0011: rData = data3;
4'b0100: rData = data4;
4'b0101: rData = data5;
4'b0110: rData = data6;
4'b0111: rData = data7;
4'b1000: rData = data8;
4'b1001: rData = data9;
4'b1010: rData = data10;
4'b1011: rData = data11;
4'b1100: rData = data12;
4'b1101: rData = data13;
4'b1110: rData = data14;
4'b1111: rData = data15;
endcase
end
end
end
endmodule
| 6.636963 |
module ALU_registerfile_2 (
clk,
reset_n,
wAddr,
wData,
we,
re,
rAddr,
rData
); //register file with 16 data
input clk, reset_n, we, re;
input [3:0] wAddr, rAddr;
input [31:0] wData;
output reg [31:0] rData;
reg [31:0] data0;
reg [31:0] data1;
reg [31:0] data2;
reg [31:0] data3;
reg [31:0] data4;
reg [31:0] data5;
reg [31:0] data6;
reg [31:0] data7;
reg [31:0] data8;
reg [31:0] data9;
reg [31:0] data10;
reg [31:0] data11;
reg [31:0] data12;
reg [31:0] data13;
reg [31:0] data14;
reg [31:0] data15; //16 data
always @(posedge clk or negedge reset_n) begin
if (reset_n == 1'b0) begin
data0 = 32'h0000_0000;
data1 = 32'h0000_0000;
data2 = 32'h0000_0000;
data3 = 32'h0000_0000;
data4 = 32'h0000_0000;
data5 = 32'h0000_0000;
data6 = 32'h0000_0000;
data7 = 32'h0000_0000;
data8 = 32'h0000_0000;
data9 = 32'h0000_0000;
data10 = 32'h0000_0000;
data11 = 32'h0000_0000;
data12 = 32'h0000_0000;
data13 = 32'h0000_0000;
data14 = 32'h0000_0000;
data15 = 32'h0000_0000; //reset all data
end else if (clk == 1'b1) begin
if (we == 1'b1) //write
begin
case (wAddr)
4'b0000: data0 = wData;
4'b0001: data1 = wData;
4'b0010: data2 = wData;
4'b0011: data3 = wData;
4'b0100: data4 = wData;
4'b0101: data5 = wData;
4'b0110: data6 = wData;
4'b0111: data7 = wData;
4'b1000: data8 = wData;
4'b1001: data9 = wData;
4'b1010: data10 = wData;
4'b1011: data11 = wData;
4'b1100: data12 = wData;
4'b1101: data13 = wData;
4'b1110: data14 = wData;
4'b1111: data15 = wData;
endcase
end
else if (re == 1'b1) //read
begin
case (rAddr)
4'b0000: rData = data0;
4'b0001: rData = data1;
4'b0010: rData = data2;
4'b0011: rData = data3;
4'b0100: rData = data4;
4'b0101: rData = data5;
4'b0110: rData = data6;
4'b0111: rData = data7;
4'b1000: rData = data8;
4'b1001: rData = data9;
4'b1010: rData = data10;
4'b1011: rData = data11;
4'b1100: rData = data12;
4'b1101: rData = data13;
4'b1110: rData = data14;
4'b1111: rData = data15;
endcase
end
end
end
endmodule
| 6.636963 |
module alu_register_immediate (
input clock,
input alu_register_immediate_enable,
input [ 2:0] funct3,
input [31:0] rs1_value,
input [31:0] immediate12_itype,
output reg [31:0] rd_value
);
parameter [2:0] ADDI = 3'h0;
parameter [2:0] SLTI = 3'h2;
parameter [2:0] SLTU = 3'h3;
parameter [2:0] XORI = 3'h4;
parameter [2:0] ORI = 3'h6;
parameter [2:0] ANDI = 3'h7;
always @(posedge clock & alu_register_immediate_enable) begin
case (funct3)
ADDI: rd_value <= rs1_value + $signed(immediate12_itype);
SLTI: rd_value <= $signed(rs1_value) < $signed(immediate12_itype) ? `ONE : `ZERO;
SLTU: rd_value <= rs1_value < immediate12_itype ? `ONE : `ZERO;
XORI: rd_value <= rs1_value ^ immediate12_itype;
ORI: rd_value <= rs1_value | immediate12_itype;
ANDI: rd_value <= rs1_value & immediate12_itype;
default: rd_value <= `ZERO;
endcase
end
always @(posedge clock & !alu_register_immediate_enable) begin
rd_value <= `HIGH_IMPEDANCE;
end
endmodule
| 6.725706 |
module alu_register_register (
input clock,
input alu_register_register_enable,
input [ 2:0] funct3,
input [ 6:0] funct7,
input [31:0] rs1_value,
input [31:0] rs2_value,
output [31:0] rd_value
);
alu_select alu_select_0 (
.clock(clock),
.alu_select_enable(alu_register_register_enable),
.funct7(funct7),
.alu_base_enable(alu_base_enable),
.alu_extra_enable(alu_extra_enable)
);
alu_base alu_base_0 (
.clock(clock),
.alu_base_enable(alu_base_enable),
.funct3(funct3),
.rs1_value(rs1_value),
.rs2_value(rs2_value),
.rd_value(rd_value)
);
alu_extra alu_extra_0 (
.clock(clock),
.alu_extra_enable(alu_extra_enable),
.funct3(funct3),
.rs1_value(rs1_value),
.rs2_value(rs2_value),
.rd_value(rd_value)
);
endmodule
| 6.725706 |
module alu_reg_ram (
READA,
READB,
clock,
write,
reset,
writeReg,
data,
readA,
readB,
sel,
muxSel,
cin,
writeRam,
ramOut,
Cout,
status,
aluOut
);
input clock;
input write;
input reset;
input [4:0] writeReg;
input [63:0] data;
input [4:0] readA;
input [4:0] readB;
input [4:0] sel;
input muxSel;
input cin;
input writeRam;
output [63:0] ramOut;
output Cout;
output [3:0] status;
output [63:0] aluOut;
output [63:0] READA;
output [63:0] READB;
wire [63:0] A_out, B_out, mux_2_1_out, alu_out, mux2_to_1_out;
assign aluOut = alu_out;
assign READA = A_out;
assign READB = B_out;
regfile_32x64 u1 (
clock,
write,
reset,
writeReg,
data,
readA,
A_out,
readB,
B_out
);
mux_Aout_2to1 u2 (
A_out,
writeReg,
muxSel,
mux2_to_1_out
);
aluFile u3 (
mux2_to_1_out,
B_out,
cin,
sel,
alu_out,
Cout,
status
);
ram_test u4 (
alu_out[7:0],
clock,
A_out,
writeRam,
ramOut
);
endmodule
| 7.20598 |
module mux_Aout_2to1 (
A_reg_out,
Writeregister,
Sel,
out
);
input [63:0] A_reg_out;
input [4:0] Writeregister;
input Sel;
output wire [63:0] out;
assign out = Sel == 0 ? A_reg_out : Sel == 1 ? Writeregister : 1'bx;
endmodule
| 7.427807 |
module alu_reg_ram_testbench ();
reg clock;
reg write;
reg reset;
reg [4:0] writeReg;
reg [63:0] data;
reg [4:0] readA;
reg [4:0] readB;
reg [4:0] sel;
reg muxSel;
reg cin;
reg writeRam;
wire [63:0] ramOut;
wire Cout;
wire [3:0] status;
wire [63:0] aluOut;
wire [63:0] READA;
wire [63:0] READB;
alu_reg_ram dut (
READA,
READB,
clock,
write,
reset,
writeReg,
data,
readA,
readB,
sel,
muxSel,
cin,
writeRam,
ramOut,
Cout,
status,
aluOut
);
initial begin
reset <= 1'b1;
clock <= 1'b1;
write <= 1'b1;
data <= 64'b0;
readA <= 5'd30;
readB <= 5'd29;
#20 reset <= 1'b0;
#320 write <= 1'b0;
#320 $stop;
end
always #10 clock <= ~clock;
always begin
#10 // load in data into regfile, write it to reg 29
write <= 1'b1;
data <= 64'd14;
writeReg <= 5'd29;
#10 data <= 64'd14;
writeReg <= 5'd30; // load in the same value onto reg 30
//disable write, the value in regfile will not write
#10 // now we have to select what goes into alu on a side, operation, and enable writeram
muxSel <= 1'b0;
sel <= 5'b10000; //a+b
cin <= 1'b0;
writeRam = 1'b0;
#10 //a-b
muxSel <= 1'b0;
sel <= 5'b10010;
cin <= 1'b1;
writeRam = 1'b1;
#10 // shift right
muxSel <= 1'b0;
sel <= 5'b10100;
cin <= 1'b0;
writeRam = 1'b1;
//#20 reset <= 1'b0;
//#320 write <= 1'b0;
end
/*always
begin
#5 data <= {$random,$random};
writeReg <= writeReg + 5'b1;
readA <= readA+5'b1;
readB <= readB+5'b1;
#5;
end
always
begin
write <= 1'b1;
writeRam <= 1'b1;
readA <= 5'b1;
readB <= 5'b1;
writeReg <= 5'b00110;
reset <= 1'b0;
clock <= 1'b1;
sel <= 5'b10000; //A+B
cin <= 1'b0;
muxSel <= 1'b0;
//writeregister <= 5'b00010;
#5;
#500 $stop;
end
*/
endmodule
| 7.109342 |
module Alu_RISC (
alu_zero_flag,
alu_out,
data_1,
data_2,
sel
);
parameter word_size = 10, op_size = 4;
parameter data_size = 8;
// Opcodes
// Opcodes
parameter ADD = 0, SUB = 1, AND = 2, OR = 3, NOT = 4;
parameter JUMP = 4'b011x, STORE = 4'b100x, LOAD = 4'b101x, SAVE = 4'b11xx;
output alu_zero_flag;
output [data_size-1:0] alu_out;
input [data_size-1:0] data_1, data_2;
input [op_size-1:0] sel;
reg [data_size-1:0] alu_out_temp;
assign alu_out = alu_out_temp;
assign alu_zero_flag = ~|alu_out_temp;
always @(sel or data_1 or data_2)
casex (sel)
ADD: alu_out_temp = data_1 + data_2;
SUB: alu_out_temp = data_2 - data_1;
AND: alu_out_temp = data_1 & data_2;
OR: alu_out_temp = data_1 | data_2;
NOT: alu_out_temp = ~data_2;
default: alu_out_temp = 0;
endcase
endmodule
| 7.962632 |
module alu_ror (
input [15:0] operand1,
input [3:0] immediate_offset,
output reg [15:0] dout
);
always @(*) begin
case (immediate_offset)
4'd0: dout = operand1;
4'd1: dout = {operand1[0], operand1[15:1]};
4'd2: dout = {operand1[1:0], operand1[15:2]};
4'd3: dout = {operand1[2:0], operand1[15:3]};
4'd4: dout = {operand1[3:0], operand1[15:4]};
4'd5: dout = {operand1[4:0], operand1[15:5]};
4'd6: dout = {operand1[5:0], operand1[15:6]};
4'd7: dout = {operand1[6:0], operand1[15:7]};
4'd8: dout = {operand1[7:0], operand1[15:8]};
4'd9: dout = {operand1[8:0], operand1[15:9]};
4'd10: dout = {operand1[9:0], operand1[15:10]};
4'd11: dout = {operand1[10:0], operand1[15:11]};
4'd12: dout = {operand1[11:0], operand1[15:12]};
4'd13: dout = {operand1[12:0], operand1[15:13]};
4'd14: dout = {operand1[13:0], operand1[15:14]};
4'd15: dout = {operand1[14:0], operand1[15]};
default: dout = 16'bx;
endcase
end
endmodule
| 6.515871 |
module alu_rs2_mux (
input clock,
input reset,
input [31:0] io_pc,
input [31:0] io_imm_s,
input [31:0] io_imm_i,
input [31:0] io_rs2,
input [1:0] io_rs2_mux_sel,
output [31:0] io_to_alu_b
);
wire _T_14;
wire _T_15;
wire _T_16;
wire [31:0] _T_19;
wire [31:0] _T_20;
wire [31:0] _T_21;
assign io_to_alu_b = _T_21;
assign _T_14 = io_rs2_mux_sel == 2'h0;
assign _T_15 = io_rs2_mux_sel == 2'h1;
assign _T_16 = io_rs2_mux_sel == 2'h2;
assign _T_19 = _T_16 ? io_imm_i : io_rs2;
assign _T_20 = _T_15 ? io_imm_s : _T_19;
assign _T_21 = _T_14 ? io_pc : _T_20;
endmodule
| 6.856232 |
module alu_rs2_mux_tb ();
reg clk;
reg rst;
reg [31:0] pc;
reg [31:0] imm_s;
reg [31:0] imm_i;
reg [31:0] rs2;
reg [ 1:0] sel;
wire [31:0] to_alu_b;
alu_rs2_mux rs2_mux (
.clock(clk),
.reset(rst),
.io_rs2(rs2),
.io_imm_s(imm_s),
.io_imm_i(imm_i),
.io_pc(pc),
.io_rs2_mux_sel(sel),
.io_to_alu_b(to_alu_b)
);
initial begin
clk = 1'b0;
rst = 1'b0;
pc = $random;
imm_s = $random;
imm_i = $random;
rs2 = $random;
sel = 0;
#10 pc = $random;
imm_s = $random;
imm_i = $random;
rs2 = $random;
sel = 1;
#10 pc = $random;
imm_s = $random;
imm_i = $random;
rs2 = $random;
sel = 2;
#10 pc = $random;
imm_s = $random;
imm_i = $random;
rs2 = $random;
sel = 3;
#10 $finish;
end
always begin
clk = ~clk;
#5;
end
endmodule
| 6.892984 |
module alu_rv (
input clock,
// feed from decode
input [31:0] instruction,
input alu_branch_enable,
input alu_unconditional_jalr_enable,
input alu_unconditional_jal_enable,
input alu_upper_immediate_lui_enable,
input alu_upper_immediate_auipc_enable,
input alu_register_immediate_enable,
input alu_register_register_enable,
// Register File
input [31:0] rs1_value,
input [31:0] rs2_value,
output [31:0] rd_value,
// PC interactions
input [31:0] pc,
output next_pc_valid,
output [31:0] next_pc
);
wire clock;
wire [31:0] instruction;
wire [ 2:0] funct3;
wire [ 6:0] funct7;
wire [ 6:0] opcode;
// unconnected because repeated decode_field module in top bench
wire [ 4:0] rs1;
wire [ 4:0] rs2;
wire [ 4:0] rd;
// end unconnected because repeated decode_field module in top bench
wire [31:0] immediate12_itype;
wire [31:0] immediate12_stype;
wire [31:0] immediate12_btype;
wire [31:0] immediate20_utype;
wire [31:0] immediate20_jtype;
decode_field decode_field_0 (
.clock(clock),
.instruction(instruction),
.funct3(funct3),
.funct7(funct7),
.opcode(opcode),
.rs1(rs1),
.rs2(rs2),
.rd(rd),
.immediate12_itype(immediate12_itype),
.immediate12_stype(immediate12_stype),
.immediate12_btype(immediate12_btype),
.immediate20_utype(immediate20_utype),
.immediate20_jtype(immediate20_jtype)
);
alu_branch alu_branch_0 (
.clock(clock),
.alu_branch_enable(alu_branch_enable),
.funct3(funct3),
.rs1_value(rs1_value),
.rs2_value(rs2_value),
.immediate12_btype(immediate12_btype),
.pc(pc),
.next_pc(next_pc)
);
alu_unconditional_jalr alu_unconditional_jalr_0 (
.clock(clock),
.alu_unconditional_jalr_enable(alu_unconditional_jalr_enable),
.immediate12_itype(immediate12_itype),
.rs1_value(rs1_value),
.funct3(funct3),
.rd_value(rd_value),
.pc(pc),
.next_pc(next_pc)
);
alu_unconditional_jal alu_unconditional_jal_0 (
.clock(clock),
.alu_unconditional_jal_enable(alu_unconditional_jal_enable),
.immediate20_jtype(immediate20_jtype),
.rd_value(rd_value),
.pc(pc),
.next_pc(next_pc)
);
alu_upper_immediate_lui alu_upper_immediate_lui_0 (
.clock(clock),
.alu_upper_immediate_lui_enable(alu_upper_immediate_lui_enable),
.immediate20_utype(immediate20_utype),
.rs1_value(rs1_value),
.rd_value(rd_value),
.pc(pc)
);
alu_upper_immediate_auipc alu_upper_immediate_auipc_0 (
.clock(clock),
.alu_upper_immediate_auipc_enable(alu_upper_immediate_auipc_enable),
.rs1_value(rs1_value),
.rd_value(rd_value),
.pc(pc)
);
alu_register_immediate alu_register_immediate_0 (
.clock(clock),
.alu_register_immediate_enable(alu_register_immediate_enable),
.funct3(funct3),
.rs1_value(rs1_value),
.immediate12_itype(immediate12_itype),
.rd_value(rd_value)
);
alu_register_register alu_register_register_0 (
.clock(clock),
.alu_register_register_enable(alu_register_register_enable),
.funct3(funct3),
.funct7(funct7),
.rs1_value(rs1_value),
.rs2_value(rs2_value),
.rd_value(rd_value)
);
endmodule
| 6.807046 |
module ALU_RV32I #(
parameter n = 32
) (
input [n-1:0] op1,
op2,
input [3:0] op_code,
output reg [n-1:0] dout,
output zero_flag,
sign_out,
output reg cry_out
);
wire [4:0] shift_amount = op2[4:0];
wire [n-1:0] shift_l_1, shift_l_2, shift_l_4, shift_l_8, shift_l;
wire [n-1:0] shift_r_1, shift_r_2, shift_r_4, shift_r_8, shift_r;
always @(op1, op2, op_code, shift_l, shift_r) begin
cry_out = 0;
case (op_code)
4'b0000: dout = op1 & op2; // and
4'b0001: dout = op1 | op2; // or
4'b0010: dout = op1 ^ op2; // xor
4'b0011: dout = $signed(op1) < $signed(op2); //signed compares (less than) SLT
4'b0100: {cry_out, dout} = op1 + op2; // addition
4'b0101: {cry_out, dout} = op1 - op2; // subtraction
4'b0110: dout = shift_l; // 16-bit shift left
4'b0111: dout = shift_r; // 16-bit shift right
4'b1000: dout = op1 < op2; //unsigned compares (less than) SLTU
default: dout = op1;
endcase
end
assign shift_l_1 = shift_amount[0] ? {op1[30:0], 1'b0} : op1;
assign shift_l_2 = shift_amount[1] ? {op1[29:0], 2'b00} : shift_l_1;
assign shift_l_4 = shift_amount[2] ? {op1[27:0], 4'b0000} : shift_l_2;
assign shift_l_8 = shift_amount[3] ? {op1[23:0], 8'b0000_0000} : shift_l_4;
assign shift_l = shift_amount[4] ? {op1[15:0], 16'b0000_0000_0000_0000} : shift_l_8;
assign shift_r_1 = shift_amount[0] ? {1'b0, op1[31:1]} : op1;
assign shift_r_2 = shift_amount[1] ? {2'b00, op1[31:2]} : shift_r_1;
assign shift_r_4 = shift_amount[2] ? {4'b0000, op1[31:4]} : shift_r_2;
assign shift_r_8 = shift_amount[3] ? {8'b0000_0000, op1[31:8]} : shift_r_4;
assign shift_r = shift_amount[4] ? {16'b0000_0000_0000_0000, op1[31:16]} : shift_r_8;
assign zero_flag = dout ? 0 : 1;
assign sign_out = dout[31];
endmodule
| 7.540216 |
module alu (
A,
B,
C,
Opcode,
Flags
);
input [3:0] A, B;
input [1:0] Opcode;
output reg [3:0] C;
output reg [4:0] Flags;
parameter ADDU = 2'b00;
parameter ADD = 2'b01;
parameter SUB = 2'b10;
parameter CMP = 2'b11;
always @(A, B, Opcode) begin
case (Opcode)
ADDU: begin
{Flags[3], C} = A + B;
// perhaps if ({Flags[3], C} == 5'b00000) ....
if (C == 4'b0000) Flags[4] = 1'b1;
else Flags[4] = 1'b0;
Flags[2:0] = 3'b000;
end
ADD: begin
C = A + B;
if (C == 4'b0000) Flags[4] = 1'b1;
else Flags[4] = 1'b0;
if ((~A[3] & ~B[3] & C[3]) | (A[3] & B[3] & ~C[3])) Flags[2] = 1'b1;
else Flags[2] = 1'b0;
Flags[1:0] = 2'b00;
Flags[3] = 1'b0;
end
SUB: begin
C = A - B;
if (C == 4'b0000) Flags[4] = 1'b1;
else Flags[4] = 1'b0;
if ((~A[3] & ~B[3] & C[3]) | (A[3] & B[3] & ~C[3])) Flags[2] = 1'b1;
else Flags[2] = 1'b0;
Flags[1:0] = 2'b00;
Flags[3] = 1'b0;
end
CMP: begin
if ($signed(A) < $signed(B)) Flags[1:0] = 2'b11;
else Flags[1:0] = 2'b00;
C = 4'b0000;
Flags[4:2] = 3'b000;
// both positive or both negative
/*if( A[3] == B[3] )
begin
if (A < B) Flags[1:0] = 2'b11;
else Flags[1:0] = 2'b00;
end
else if (A[3] == 1'b0) Flags[1:0] = 2'b00;
else Flags[1:0] = 2'b01;
Flags[4:2] = 3'b000;
// C = ?? if I don;t specify, then I'm in trouble.
C = 4'b0000;
*/
end
default: begin
C = 4'b0000;
Flags = 5'b00000;
end
endcase
end
endmodule
| 7.41692 |
module alu_sel (
input alu1_sel,
input alu2_sel,
input [31:0] rs1_data,
input [31:0] rs2_data,
input [31:0] pc,
input [31:0] imm,
output [31:0] alu1_data,
output [31:0] alu2_data
);
assign alu1_data = alu1_sel ? pc : rs1_data;
assign alu2_data = alu2_sel ? imm : rs2_data;
endmodule
| 8.153317 |
module alu_select (
ctl_alu_oe,
ctl_alu_shift_oe,
ctl_alu_op2_oe,
ctl_alu_res_oe,
ctl_alu_op1_oe,
ctl_alu_bs_oe,
ctl_alu_op1_sel_bus,
ctl_alu_op1_sel_low,
ctl_alu_op1_sel_zero,
ctl_alu_op2_sel_zero,
ctl_alu_op2_sel_bus,
ctl_alu_op2_sel_lq,
ctl_alu_sel_op2_neg,
ctl_alu_sel_op2_high,
ctl_alu_core_R,
ctl_alu_core_V,
ctl_alu_core_S,
alu_oe,
alu_shift_oe,
alu_op2_oe,
alu_res_oe,
alu_op1_oe,
alu_bs_oe,
alu_op1_sel_bus,
alu_op1_sel_low,
alu_op1_sel_zero,
alu_op2_sel_zero,
alu_op2_sel_bus,
alu_op2_sel_lq,
alu_sel_op2_neg,
alu_sel_op2_high,
alu_core_R,
alu_core_V,
alu_core_S
);
input wire ctl_alu_oe;
input wire ctl_alu_shift_oe;
input wire ctl_alu_op2_oe;
input wire ctl_alu_res_oe;
input wire ctl_alu_op1_oe;
input wire ctl_alu_bs_oe;
input wire ctl_alu_op1_sel_bus;
input wire ctl_alu_op1_sel_low;
input wire ctl_alu_op1_sel_zero;
input wire ctl_alu_op2_sel_zero;
input wire ctl_alu_op2_sel_bus;
input wire ctl_alu_op2_sel_lq;
input wire ctl_alu_sel_op2_neg;
input wire ctl_alu_sel_op2_high;
input wire ctl_alu_core_R;
input wire ctl_alu_core_V;
input wire ctl_alu_core_S;
output wire alu_oe;
output wire alu_shift_oe;
output wire alu_op2_oe;
output wire alu_res_oe;
output wire alu_op1_oe;
output wire alu_bs_oe;
output wire alu_op1_sel_bus;
output wire alu_op1_sel_low;
output wire alu_op1_sel_zero;
output wire alu_op2_sel_zero;
output wire alu_op2_sel_bus;
output wire alu_op2_sel_lq;
output wire alu_sel_op2_neg;
output wire alu_sel_op2_high;
output wire alu_core_R;
output wire alu_core_V;
output wire alu_core_S;
assign alu_oe = ctl_alu_oe;
assign alu_shift_oe = ctl_alu_shift_oe;
assign alu_op2_oe = ctl_alu_op2_oe;
assign alu_res_oe = ctl_alu_res_oe;
assign alu_op1_oe = ctl_alu_op1_oe;
assign alu_bs_oe = ctl_alu_bs_oe;
assign alu_op1_sel_bus = ctl_alu_op1_sel_bus;
assign alu_op1_sel_low = ctl_alu_op1_sel_low;
assign alu_op1_sel_zero = ctl_alu_op1_sel_zero;
assign alu_op2_sel_zero = ctl_alu_op2_sel_zero;
assign alu_op2_sel_bus = ctl_alu_op2_sel_bus;
assign alu_op2_sel_lq = ctl_alu_op2_sel_lq;
assign alu_sel_op2_neg = ctl_alu_sel_op2_neg;
assign alu_sel_op2_high = ctl_alu_sel_op2_high;
assign alu_core_R = ctl_alu_core_R;
assign alu_core_V = ctl_alu_core_V;
assign alu_core_S = ctl_alu_core_S;
endmodule
| 6.697911 |
module Rev 0.0 06/13/2012 **/
/** **/
/*******************************************************************************************/
module alu_shft (shft_c, shft_out, alub_in, aluop_reg, carry_bit);
input carry_bit; /* carry flag input */
input [7:0] alub_in; /* alu b input */
input [`AOP_IDX:0] aluop_reg; /* alu operation control subset */
output shft_c; /* alu shifter carry output */
output [7:0] shft_out; /* alu shifter output */
/*****************************************************************************************/
/* */
/* signal declarations */
/* */
/*****************************************************************************************/
reg shft_c; /* shifter carry output */
reg [7:0] shft_out; /* shifter output */
/*****************************************************************************************/
/* */
/* alu shifter function */
/* */
/*****************************************************************************************/
always @ (aluop_reg or alub_in) begin
casex (aluop_reg) //synopsys parallel_case
`AOP_RL,
`AOP_RLA: shft_c = alub_in[7];
`AOP_RLC,
`AOP_RLCA: shft_c = alub_in[7];
`AOP_RR,
`AOP_RRA: shft_c = alub_in[0];
`AOP_RRC,
`AOP_RRCA: shft_c = alub_in[0];
`AOP_SLL,
`AOP_SLA: shft_c = alub_in[7];
`AOP_SRA: shft_c = alub_in[0];
`AOP_SRL: shft_c = alub_in[0];
default: shft_c = 1'b0;
endcase
end
always @ (aluop_reg or alub_in or carry_bit) begin
casex (aluop_reg) //synopsys parallel_case
`AOP_RL,
`AOP_RLA: shft_out = {alub_in[6:0], carry_bit};
`AOP_RLC,
`AOP_RLCA: shft_out = {alub_in[6:0], alub_in[7]};
`AOP_RR,
`AOP_RRA: shft_out = {carry_bit, alub_in[7:1]};
`AOP_RRC,
`AOP_RRCA: shft_out = {alub_in[0], alub_in[7:1]};
`AOP_SLA: shft_out = {alub_in[6:0], 1'b0};
`AOP_SLL: shft_out = {alub_in[6:0], 1'b1};
`AOP_SRA: shft_out = {alub_in[7], alub_in[7:1]};
`AOP_SRL: shft_out = {1'b0, alub_in[7:1]};
default: shft_out = 8'h00;
endcase
end
endmodule
| 8.238592 |
module alu_shift (
a_in,
b_in,
op_in,
z_flag_in,
s_flag_in,
c_flag_in,
ovr_flag_in,
c_out,
z_flag_out,
s_flag_out,
c_flag_out,
ovr_flag_out,
op_active
);
parameter data_wl = 16;
parameter op_wl = 8;
input [data_wl-1:0] a_in;
input [data_wl-1:0] b_in;
input [op_wl -1:0] op_in;
input z_flag_in;
input s_flag_in;
input c_flag_in;
input ovr_flag_in;
output [data_wl-1:0] c_out;
output z_flag_out;
output s_flag_out;
output c_flag_out;
output ovr_flag_out;
output op_active;
reg [data_wl-1:0] c_reg;
reg z_flag_out;
reg s_flag_out;
reg c_flag_out;
reg op_active_int;
// shift ops
parameter I_SHR0 = 8'h80;
parameter I_SHR1 = 8'h81;
parameter I_SHRA = 8'h82;
parameter I_SHRC = 8'h83;
parameter I_ROTR = 8'h84;
parameter I_ROTRC = 8'h85;
parameter I_SHL0 = 8'h88;
parameter I_SHL1 = 8'h89;
parameter I_SHLA = 8'h8A;
parameter I_SHLC = 8'h8B;
parameter I_ROTL = 8'h8C;
parameter I_ROTLC = 8'h8D;
assign ovr_flag_out = ovr_flag_in;
always @(op_in or b_in or c_flag_in) begin
op_active_int = 1'b0;
case (op_in)
I_SHR0: // shift right, shift-in '0'
begin
c_reg[data_wl-2:0] = b_in[data_wl-1:1];
c_reg[data_wl-1] = 1'b0;
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_SHR1: // shift right, shift-in '1'
begin
c_reg [data_wl-2:0] = b_in [data_wl-1:1];
c_reg [data_wl-1] = 1'b1;
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_SHRA: // shift right, shift-in MSB of B
begin
c_reg[data_wl-2:0] = b_in[data_wl-1:1];
c_reg[data_wl-1] = b_in[data_wl-1];
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_SHRC: // shift right, shift-in carry
begin
c_reg[data_wl-2:0] = b_in[data_wl-1:1];
c_reg[data_wl-1] = c_flag_in;
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_ROTR: // shift right, shift-in LSB of B (rotate)
begin
c_reg [data_wl-2:0] = b_in [data_wl-1:1];
c_reg [data_wl-1] = b_in [0];
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_ROTRC: begin
c_reg [data_wl-2:0] = b_in [data_wl-1:1];
c_reg [data_wl-1] = c_flag_in;
c_flag_out = b_in[0];
op_active_int = 1'b1;
end
I_SHL0: begin
c_reg [data_wl-1:1] = b_in [data_wl-2:0];
c_reg [0] = 1'b0;
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_SHL1: begin
c_reg [data_wl-1:1] = b_in [data_wl-2:0];
c_reg [0] = 1'b1;
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_SHLA: begin
c_reg [data_wl-1:1] = b_in [data_wl-2:0];
c_reg [0] = b_in [0]; //Correction c_reg [0]= b_in [data_wl-1];
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_SHLC: begin
c_reg [data_wl-1:1] = b_in [data_wl-2:0];
c_reg [0] = c_flag_in;
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_ROTL: begin
c_reg [data_wl-1:1] = b_in [data_wl-2:0];
c_reg [0] = b_in [data_wl-1];
c_flag_out = c_flag_in;
op_active_int = 1'b1;
end
I_ROTLC: begin
c_reg [data_wl-1:1] = b_in [data_wl-2:0];
c_reg [0] = c_flag_in;
c_flag_out = b_in [data_wl-1];
op_active_int = 1'b1;
end
default: begin
c_reg = 0;
c_flag_out = 1'b0;
end
endcase
if (c_reg == 0) z_flag_out = 1'b1;
else z_flag_out = 1'b0;
s_flag_out = c_reg[data_wl-1];
end
assign c_out = c_reg;
assign op_active = op_active_int;
endmodule
| 7.914769 |
module ALU_Shifts_1_tb (
output wire done,
error
);
ALU_Shifts_base_tb #(
.DATA_WIDTH (32),
.FILE_SOURCE ("../testbench/data/core/ALU_Shifts_1_tb_data.txt"),
.FILE_COMPARE("../testbench/data/core/ALU_Shifts_1_tb_compare.txt")
) dut (
.done (done),
.error(error)
);
endmodule
| 7.323472 |
module ALU_Shifts_base_tb #(
parameter DATA_WIDTH = 8,
parameter FILE_SOURCE = "",
parameter FILE_COMPARE = ""
) (
output wire done,
error
);
localparam FLAGS_WIDTH = 4;
localparam OPCODE_WIDTH = 4;
localparam FS_DATA_WIDTH = (2 * DATA_WIDTH) + OPCODE_WIDTH + 1;
localparam FC_DATA_WIDTH = (FLAGS_WIDTH - 1) + DATA_WIDTH;
reg clk = 0;
reg fs_go = 0;
reg fs_pause = 1;
reg first_run = 1;
wire fs_done;
wire valid;
wire [DATA_WIDTH-1:0] data_a, data_b;
wire [ 3:0] opcode;
wire result_valid;
wire [ DATA_WIDTH-1:0] result;
wire [FLAGS_WIDTH-1:0] result_flags;
always #2.5 clk <= ~clk;
initial #50 fs_pause <= 1'b0;
always @(posedge clk) begin
if (fs_pause) begin
fs_go <= 0;
end else begin
if (first_run) begin
if (fs_go) begin
fs_go <= 0;
first_run <= 0;
end else begin
fs_go <= 1;
end
end else begin
fs_go <= result_valid;
end
end
end
FileSource #(
.DATA_WIDTH(FS_DATA_WIDTH),
.FILE_PATH (FILE_SOURCE)
) source (
.clk (clk),
.ready(fs_go),
.valid(valid),
.empty(fs_done),
.data ({data_valid, opcode, data_a, data_b})
);
FileCompare #(
.DATA_WIDTH(FC_DATA_WIDTH),
.FILE_PATH (FILE_COMPARE)
) compare (
.clk (clk),
.valid(result_valid),
.data ({result_flags[2:0], result}),
.done (done),
.error(error)
);
W0RM_ALU_Shifts #(
.SINGLE_CYCLE(0),
.DATA_WIDTH (DATA_WIDTH)
) dut (
.clk(clk),
.data_valid(valid & data_valid),
.opcode(opcode),
.data_a(data_a),
.data_b(data_b),
.result(result),
.result_valid(result_valid),
.result_flags(result_flags)
);
endmodule
| 8.364816 |
module ALU_SLAVE (
clk,
reset_n,
s_sel,
s_wr,
s_addr,
s_din,
s_dout,
s_interrupt,
op_start,
opdone_clear,
status,
result_pop,
wr_en_inst,
inst,
result,
rAddr,
rData,
wAddr,
wData,
we_rf,
rd_ack_result
);
input clk, reset_n, s_sel, s_wr, rd_ack_result;
input [1:0] status;
input [15:0] s_addr;
input [31:0] s_din, rData, result;
output op_start, opdone_clear, s_interrupt;
output [31:0] s_dout;
output reg wr_en_inst, result_pop, we_rf;
output reg [3:0] rAddr, wAddr;
output reg [31:0] wData, inst;
wire [31:0] OPERATION_START, INTERRUPT, INTERRUPT_ENABLE, INSTRUCTION, ALU_STATUS;
reg [31:0] s_dout_ff, result_temp;
reg [4:0] to_reg;
//////////// Address Decoder ////////// WRITE ENABLE
always @(s_sel or s_wr or s_addr[7:0]) begin
if (s_sel == 1'b1 && s_wr == 1'b1) begin
case (s_addr[7:0])
8'h00: to_reg <= 5'b0_0001;
8'h01: to_reg <= 5'b0_0010;
8'h02: to_reg <= 5'b0_0100;
8'h03: to_reg <= 5'b0_1000;
8'h04: to_reg <= 5'b1_1000;
default: to_reg <= 0;
endcase
end else to_reg <= 0;
end
dff32_r_en_c U0_OP_START (
clk,
reset_n,
to_reg[0],
opdone_clear,
{31'h0, s_din[0]},
OPERATION_START
);
dff32_r_en_en U1_INTERRUPT (
clk,
reset_n,
to_reg[1],
status,
{31'h0, s_din[0]},
INTERRUPT
);
dff32_r_en U2_INTERRUPT_EN (
clk,
reset_n,
to_reg[2],
{31'h0, s_din[0]},
INTERRUPT_ENABLE
);
dff32_r_en U3_INSTRUCTION (
clk,
reset_n,
to_reg[3],
s_din,
INSTRUCTION
);
dff32_r U4_ALU_STATUS (
clk,
reset_n,
{30'h0, status},
ALU_STATUS
);
/////////// 7-to-1 MUX //////////////
always @(posedge clk) begin
if (s_sel == 1'b1 && s_wr == 1'b0) begin
casex (s_addr[7:0])
8'h00: s_dout_ff = OPERATION_START;
8'h01: s_dout_ff = INTERRUPT;
8'h02: s_dout_ff = INTERRUPT_ENABLE;
8'h03: s_dout_ff = INSTRUCTION;
8'h05: s_dout_ff = ALU_STATUS;
8'h1x: s_dout_ff = rData;
default: s_dout_ff = 0;
endcase
end else s_dout_ff <= 0;
end
assign s_dout = (rd_ack_result == 1'b1) ? result : s_dout_ff;
////////// Data from result fifo ////////////
always @(s_sel, s_wr, s_addr[7:0], INTERRUPT[0]) begin
if (s_sel == 1'b1 && s_wr == 1'b0 && s_addr[7:0] == 8'h04) begin
result_pop <= 1'b1;
end else result_pop <= 1'b0;
end
//////////// register file write & read ///////////////
always @(s_sel, s_wr, s_addr[7:0], s_din) begin
if (s_sel == 1'b1 && s_addr[4] == 1'b1) begin //Register select
if (s_wr == 1'b1) begin //write
we_rf <= 1'b1;
wAddr <= s_addr[3:0];
wData <= s_din;
rAddr <= 0;
end else begin
we_rf <= 0;
wAddr <= 0;
wData <= 0;
rAddr <= s_addr[3:0];
end
end else begin
we_rf <= 0;
wAddr <= 0;
wData <= 0;
rAddr <= 0;
end
end
//////////// instruction push /////////////
always @(s_sel, s_wr, s_addr[7:0], status, s_din) begin
if (s_sel == 1'b1 && s_wr == 1'b1 && s_addr[7:0] == 8'h03 && status == 2'b00) begin
wr_en_inst <= 1'b1;
inst <= s_din;
end else begin
wr_en_inst <= 1'b0;
inst <= 0;
end
end
//////////// interrupt //////////
assign s_interrupt = INTERRUPT[0] & INTERRUPT_ENABLE[0];
//////////// op_start & opdone_clear /////////////
assign op_start = OPERATION_START[0];
assign opdone_clear = ~INTERRUPT[0];
endmodule
| 6.703122 |
module alu_sll_16bit (
A,
S,
Z
);
parameter N = 32;
//port definitions
input wire [(N-1):0] A;
input wire [4:0] S;
output wire [(N-1):0] Z;
wire [(N-1):0] sl2, sl4, sl8, sl16;
alu_sl_16bit #(
.N(N)
) MUX5 (
.A(A),
.S(S[4]),
.Z(sl16)
);
alu_sl_8bit #(
.N(N)
) MUX4 (
.A(sl16),
.S(S[3]),
.Z(sl8)
);
alu_sl_4bit #(
.N(N)
) MUX3 (
.A(sl8),
.S(S[2]),
.Z(sl4)
);
alu_sl_2bit #(
.N(N)
) MUX2 (
.A(sl4),
.S(S[1]),
.Z(sl2)
);
alu_sl_1bit #(
.N(N)
) MUX1 (
.A(sl2),
.S(S[0]),
.Z(Z)
);
endmodule
| 6.746768 |
module: alu_shift_1bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_sll_16bit_test;
// parameter width
parameter N = 32;
// testing variables
reg [N:0] i;
reg [N:0] j;
// Inputs
reg [N-1:0] A;
reg [4:0] S;
// Outputs
wire [N-1:0] Z;
// Instantiate the Unit Under Test (UUT)
alu_sll_16bit #(.N(N)) uut (
.A(A),
.S(S),
.Z(Z)
);
initial begin
// Insert the dumps here
$dumpfile("alu_all_16bit_test.vcd");
$dumpvars(0, alu_all_16bit_test);
// Initialize Inputs
A = 32'h00000000;
S = 5'b00000;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for (j = 0; j <= 16; j = j + 1) begin
for (i = 0; i <= 16; i = i + 1) begin
A = i;
S = j;
#100;
$display("Input: %d; Shift: %d; Output: %d;", A, S, Z);
end
end
$finish;
end
endmodule
| 6.550056 |
module alu_sll_4bit (
A,
S,
Z
);
parameter N = 32;
//port definitions
input wire [(N-1):0] A;
input wire [2:0] S;
output wire [(N-1):0] Z;
wire [(N-1):0] sl2, sl4, sl8, sl16;
alu_sl_4bit #(
.N(N)
) MUX3 (
.A(A),
.S(S[2]),
.Z(sl4)
);
alu_sl_2bit #(
.N(N)
) MUX2 (
.A(sl4),
.S(S[1]),
.Z(sl2)
);
alu_sl_1bit #(
.N(N)
) MUX1 (
.A(sl2),
.S(S[0]),
.Z(Z)
);
endmodule
| 6.511646 |
module: alu_shift_1bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_sll_4bit_test;
// parameter width
parameter N = 32;
// testing variables
reg [N:0] i;
reg [N:0] j;
// Inputs
reg [N-1:0] A;
reg [2:0] S;
// Outputs
wire [N-1:0] Z;
// Instantiate the Unit Under Test (UUT)
alu_sll_4bit #(.N(N)) uut (
.A(A),
.S(S),
.Z(Z)
);
initial begin
// Insert the dumps here
$dumpfile("alu_sll_4bit_test.vcd");
$dumpvars(0, alu_sll_4bit_test);
// Initialize Inputs
A = 32'h00000000;
S = 5'b00000;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for (j = 0; j <= 8; j = j + 1) begin
for (i = 0; i <= 8; i = i + 1) begin
A = i;
S = j;
#100;
$display("Input: %b; Shift: %d; Output: %b;", A, S, Z);
end
end
$finish;
end
endmodule
| 6.550056 |
module alu_sll_8bit (
A,
S,
Z
);
parameter N = 32;
//port definitions
input wire [(N-1):0] A;
input wire [3:0] S;
output wire [(N-1):0] Z;
wire [(N-1):0] sl2, sl4, sl8, sl16;
alu_sl_8bit #(
.N(N)
) MUX4 (
.A(A),
.S(S[3]),
.Z(sl8)
);
alu_sl_4bit #(
.N(N)
) MUX3 (
.A(sl8),
.S(S[2]),
.Z(sl4)
);
alu_sl_2bit #(
.N(N)
) MUX2 (
.A(sl4),
.S(S[1]),
.Z(sl2)
);
alu_sl_1bit #(
.N(N)
) MUX1 (
.A(sl2),
.S(S[0]),
.Z(Z)
);
endmodule
| 6.640502 |
module: alu_shift_1bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_sll_8bit_test;
// parameter width
parameter N = 32;
// testing variables
reg [N:0] i;
reg [N:0] j;
// Inputs
reg [N-1:0] A;
reg [3:0] S;
// Outputs
wire [N-1:0] Z;
// Instantiate the Unit Under Test (UUT)
alu_sll_8bit #(.N(N)) uut (
.A(A),
.S(S),
.Z(Z)
);
initial begin
// Insert the dumps here
$dumpfile("alu_sll_8bit_test.vcd");
$dumpvars(0, alu_sll_8bit_test);
// Initialize Inputs
A = 32'h00000000;
S = 5'b00000;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for (j = 0; j <= 16; j = j + 1) begin
for (i = 0; i <= 16; i = i + 1) begin
A = i;
S = j;
#100;
$display("Input: %d; Shift: %d; Output: %d;", A, S, Z);
end
end
$finish;
end
endmodule
| 6.550056 |
module: alu_shift_1bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_sll_test;
// parameter width
parameter N = 32;
// testing variables
reg [N:0] i;
reg [N:0] j;
// Inputs
reg [N-1:0] A;
reg [5:0] S;
// Outputs
wire [N-1:0] Z;
// Instantiate the Unit Under Test (UUT)
alu_sll #(.N(N)) uut (
.A(A),
.S(S),
.Z(Z)
);
initial begin
// Insert the dumps here
$dumpfile("alu_sll_test.vcd");
$dumpvars(0, alu_sll_test);
// Initialize Inputs
A = 32'h00000000;
S = 5'b00000;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for (j = 0; j <= 32; j = j + 1) begin
for (i = 0; i <= 32; i = i + 1) begin
A = i;
S = j;
#100;
$display("Input: %b; Shift: %d; Output: %b;", A, S, Z);
end
end
$finish;
end
endmodule
| 6.550056 |
module alu_slt (
A,
B,
Z
);
parameter WIDTH = 32;
//port definitions
input wire [(WIDTH - 1):0] A, B;
output wire [(WIDTH - 1):0] Z;
// Wires to compute the subtraction
wire [(WIDTH - 1):0] AminusB;
wire OF;
alu_sub_32bit SUB (
.A (A),
.B (B),
.S (AminusB),
.OF(OF)
);
assign Z = ~A[31] & ~B[31] & AminusB[31] | A[31] & ~B[31] | A[31] & B[31] & AminusB[31];
endmodule
| 6.541333 |
module alu_sl_8bit (
A,
S,
Z
);
parameter N = 2;
//port definitions
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[7:0] = 8'b0;
assign B[N-1:8] = A[N-9:0];
mux_2to1 #(
.N(N)
) MUX (
.X(A),
.Y(B),
.S(S),
.Z(Z)
);
endmodule
| 6.652799 |
module ALU_small (
a,
b,
out
);
parameter DATA_WIDTH = 8;
input [DATA_WIDTH - 1:0] a;
input [DATA_WIDTH - 1:0] b;
output [DATA_WIDTH:0] out;
wire tmp;
FS_8 FS_8_0 (
.a(a),
.b(b),
.out(out[DATA_WIDTH-1:0]),
.cin(1'b0),
.cout(out[DATA_WIDTH])
);
endmodule
| 8.217661 |
module alu_somma (
output [N-1:0] z,
input [N-1:0] x,
input [N-1:0] y
);
parameter N = 32;
assign #5 z = x + y;
endmodule
| 7.269742 |
module alu_sra (
A,
S,
Z
);
parameter N = 32;
input wire [(N-1):0] A;
input wire [4:0] S;
output wire [(N-1):0] Z;
wire [(N-1):0] shifted2, shifted4, shifted8, shifted16;
wire sign;
assign sign = A[31];
alu_sra_16bit #(
.N(N)
) MUX5 (
.A(A),
.S(S[4]),
.Z(shifted16),
.sign(sign)
);
alu_sra_8bit #(
.N(N)
) MUX4 (
.A(shifted16),
.S(S[3]),
.Z(shifted8),
.sign(sign)
);
alu_sra_4bit #(
.N(N)
) MUX3 (
.A(shifted8),
.S(S[2]),
.Z(shifted4),
.sign(sign)
);
alu_sra_2bit #(
.N(N)
) MUX2 (
.A(shifted4),
.S(S[1]),
.Z(shifted2),
.sign(sign)
);
alu_sra_1bit #(
.N(N)
) MUX1 (
.A(shifted2),
.S(S[0]),
.Z(Z),
.sign(sign)
);
endmodule
| 6.905444 |
module alu_sra_16bit (
A,
S,
Z,
sign
);
parameter N = 2;
//port definitions
input wire sign;
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[N-17:0] = A[N-1:16];
assign B[N-1:N-16] = {16{sign}};
mux_2to1 #(
.N(N)
) MUX (
.X(A),
.Y(B),
.S(S),
.Z(Z)
);
endmodule
| 8.139889 |
module alu_sra_1bit (
A,
S,
Z,
sign
);
parameter N = 2;
//port definitions
input wire sign;
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[(N-2):0] = A[N-1:1];
assign B[(N-1)] = sign;
mux_2to1 #(
.N(N)
) MUX (
.X(A),
.Y(B),
.S(S),
.Z(Z)
);
endmodule
| 7.347886 |
module alu_sra_2bit (
A,
S,
Z,
sign
);
parameter N = 2;
//port definitions
input wire sign;
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[N-3:0] = A[N-1:2];
assign B[N-1:N-2] = {2{sign}};
mux_2to1 #(
.N(N)
) MUX (
.X(A),
.Y(B),
.S(S),
.Z(Z)
);
endmodule
| 7.958679 |
module alu_sra_32bit (
A,
S,
Z
);
parameter N = 2;
//port definitions
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[N-1:0] = 32'hffffffff;
mux_2to1 #(
.N(N)
) MUX (
.X(A),
.Y(B),
.S(S),
.Z(Z)
);
endmodule
| 7.367412 |
module alu_sra_4bit (
A,
S,
Z,
sign
);
parameter N = 2;
//port definitions
input wire sign;
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[N-5:0] = A[N-1:4];
assign B[N-1:N-4] = {4{sign}};
mux_2to1 #(
.N(N)
) MUX (
.X(A),
.Y(B),
.S(S),
.Z(Z)
);
endmodule
| 7.767157 |
module alu_sra_8bit (
A,
S,
Z,
sign
);
parameter N = 2;
//port definitions
input wire sign;
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[N-9:0] = A[N-1:8];
assign B[N-1:N-8] = {8{sign}};
mux_2to1 #(
.N(N)
) MUX (
.X(A),
.Y(B),
.S(S),
.Z(Z)
);
endmodule
| 8.214987 |
module: alu_shift_1bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_sra_test;
// parameter width
parameter N = 32;
// testing variables
reg [N:0] i;
reg [N:0] j;
// Inputs
reg [N-1:0] A;
reg [5:0] S;
// Outputs
wire [N-1:0] Z;
// Instantiate the Unit Under Test (UUT)
alu_sra #(.N(N)) uut (
.A(A),
.S(S),
.Z(Z)
);
initial begin
// Insert the dumps here
$dumpfile("alu_sra.vcd");
$dumpvars(0, alu_sra_test);
// Initialize Inputs
A = 32'h00000000;
S = 5'b00000;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for (j = 0; j <= 32; j = j + 1) begin
for (i = 0; i <= 32; i = i + 1) begin
A = i;
S = j;
#100;
$display("Input: %b; Shift: %b; Output: %b;", A, S, Z);
end
end
$finish;
end
endmodule
| 6.550056 |
module alu_src (
input [31:0] busA,
busB,
PC,
imm,
input ALUAsrc,
input [1:0] ALUBsrc,
output reg [31:0] ALUA,
ALUB
);
always @(*) begin
ALUA = (ALUAsrc ? PC : busA);
end
always @(*) begin
case (ALUBsrc)
2'b00: ALUB = busB;
2'b01: ALUB = imm;
2'b10: ALUB = 32'd4;
default: ALUB = 32'd0;
endcase
end
endmodule
| 7.234612 |
module alu_src_selector (
// input [1:0] ID_EX_ALU_srcA,
input [1:0] forward_A,
input [1:0] forward_B,
input [31:0] ID_EX_rdata1,
input [31:0] ID_EX_rdata2,
input [31:0] EX_MEM_ALU_Result,
input [31:0] WB_wdata,
input [31:0] WB_wdata_reg,
input [31:0] ID_EX_U_sign_extend,
input [31:0] ID_EX_I_sign_extend,
input [31:0] ID_EX_S_sign_extend,
// output reg [31:0] alu_a,
// output reg [31:0] alu_b,
output reg [31:0] the_right_rdata1,
output reg [31:0] the_right_rdata2
);
// get the real read datas
always @(*) begin
case (forward_A)
2'b00: the_right_rdata1 = ID_EX_rdata1;
2'b01: the_right_rdata1 = WB_wdata;
2'b10: the_right_rdata1 = EX_MEM_ALU_Result;
2'b11: the_right_rdata1 = WB_wdata_reg;
endcase
case (forward_B)
2'b00: the_right_rdata2 = ID_EX_rdata2;
2'b01: the_right_rdata2 = WB_wdata;
2'b10: the_right_rdata2 = EX_MEM_ALU_Result;
2'b11: the_right_rdata2 = WB_wdata_reg;
endcase
end
endmodule
| 8.270262 |
module alu_srl (
A,
S,
Z
);
parameter N = 32;
//port definitions
input wire [(N-1):0] A;
input wire [4:0] S;
output wire [(N-1):0] Z;
wire [(N-1):0] sr2, sr4, sr8, sr16;
alu_sr_16bit #(
.N(N)
) MUX5 (
.A(A),
.S(S[4]),
.Z(sr16)
);
alu_sr_8bit #(
.N(N)
) MUX4 (
.A(sr16),
.S(S[3]),
.Z(sr8)
);
alu_sr_4bit #(
.N(N)
) MUX3 (
.A(sr8),
.S(S[2]),
.Z(sr4)
);
alu_sr_2bit #(
.N(N)
) MUX2 (
.A(sr4),
.S(S[1]),
.Z(sr2)
);
alu_sr_1bit #(
.N(N)
) MUX1 (
.A(sr2),
.S(S[0]),
.Z(Z)
);
endmodule
| 6.539311 |
module alu_srl_32bit (
A,
S,
Z
);
parameter N = 32;
//port definitions
input wire [(N-1):0] A;
input wire [5:0] S;
output wire [(N-1):0] Z;
wire [(N-1):0] shifted2;
alu_shift_16bit #(
.N(N)
) MUX5 (
.A(A),
.S(S[4]),
.Z(shifted2)
);
alu_shift_8bit #(
.N(N)
) MUX4 (
.A(A),
.S(S[3]),
.Z(shifted2)
);
alu_shift_4bit #(
.N(N)
) MUX3 (
.A(A),
.S(S[2]),
.Z(shifted2)
);
alu_shift_2bit #(
.N(N)
) MUX2 (
.A(A),
.S(S[1]),
.Z(shifted2)
);
alu_shift_1bit #(
.N(N)
) MUX1 (
.A(shifted2),
.S(S[0]),
.Z(Z)
);
endmodule
| 6.756015 |
module: alu_shift_1bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_srl_32bit_test;
// parameter width
parameter N = 32;
// testing variables
reg [N:0] i;
reg [6:0] j;
// Inputs
reg [N-1:0] A;
reg [5:0] S;
// Outputs
wire [N-1:0] Z;
// Instantiate the Unit Under Test (UUT)
alu_srl_32bit #(.N(N)) uut (
.A(A),
.S(S),
.Z(Z)
);
initial begin
// Insert the dumps here
$dumpfile("alu_srl_32bit_test.vcd");
$dumpvars(0, alu_srl_32bit_test);
// Initialize Inputs
i = 0;
A = 4'b0000;
S = 5'b00000;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for (j = 0; j < 32; j = j + 1) begin
for (i = 0; i < 16; i = i + 1) begin
A = i;
S = j;
#100;
$display("Input: %d; Shift: %d; Output: %d;", A, S, Z);
end
end
$finish;
end
endmodule
| 6.550056 |
module: alu_shift_1bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_srl_test;
// parameter width
parameter N = 32;
// testing variables
reg [N:0] i;
reg [N:0] j;
// Inputs
reg [N-1:0] A;
reg [5:0] S;
// Outputs
wire [N-1:0] Z;
// Instantiate the Unit Under Test (UUT)
alu_srl #(.N(N)) uut (
.A(A),
.S(S),
.Z(Z)
);
initial begin
// Insert the dumps here
$dumpfile("alu_srl_test.vcd");
$dumpvars(0, alu_srl_test);
// Initialize Inputs
A = 32'h00000000;
S = 5'b00000;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for (j = 0; j <= 32; j = j + 1) begin
for (i = 0; i <= 32; i = i + 1) begin
A = i;
S = j;
#100;
$display("Input: %d; Shift: %d; Output: %d;", A, S, Z);
end
end
$finish;
end
endmodule
| 6.550056 |
module alu_sr_16bit (
A,
S,
Z
);
parameter N = 2;
//port definitions
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[N-17:0] = A[N-1:16];
assign B[N-1:N-16] = 16'b0;
mux_2to1 #(
.N(N)
) MUX (
.X(A),
.Y(B),
.S(S),
.Z(Z)
);
endmodule
| 7.026969 |
module alu_sr_1bit (
A,
S,
Z
);
parameter N = 2;
//port definitions
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[(N-2):0] = A[N-1:1];
assign B[(N-1)] = 1'b0;
mux_2to1 #(
.N(N)
) MUX (
.X(A),
.Y(B),
.S(S),
.Z(Z)
);
endmodule
| 6.741968 |
module alu_sr_2bit (
A,
S,
Z
);
parameter N = 2;
//port definitions
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[N-3:0] = A[N-1:2];
assign B[N-1:N-2] = 2'b0;
mux_2to1 #(
.N(N)
) MUX (
.X(A),
.Y(B),
.S(S),
.Z(Z)
);
endmodule
| 6.784963 |
module alu_sr_32bit (
A,
S,
Z
);
parameter N = 2;
//port definitions
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[N-1:0] = 32'd0;
mux_2to1 #(
.N(N)
) MUX (
.X(A),
.Y(B),
.S(S),
.Z(Z)
);
endmodule
| 6.774447 |
module alu_sr_4bit (
A,
S,
Z
);
parameter N = 2;
//port definitions
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[N-5:0] = A[N-1:4];
assign B[N-1:N-4] = 4'b0;
mux_2to1 #(
.N(N)
) MUX (
.X(A),
.Y(B),
.S(S),
.Z(Z)
);
endmodule
| 6.709153 |
module alu_sr_8bit (
A,
S,
Z
);
parameter N = 2;
//port definitions
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[N-9:0] = A[N-1:8];
assign B[N-1:N-8] = 8'b0;
mux_2to1 #(
.N(N)
) MUX (
.X(A),
.Y(B),
.S(S),
.Z(Z)
);
endmodule
| 7.271255 |
module ALU_stage (
input clk,
input [15:0] register_content1,
input [15:0] register_content2,
input [7:0] immediate_value,
input [2:0] alu_control_signal,
input alu_src_signal,
output reg [15:0] result_buf,
output reg [15:0] result_buf2
);
wire carry, zero, neg;
wire [15:0] out;
reg [15:0] result;
ALU alu_1 (
register_content1,
register_content2,
alu_control_signal,
out,
carry,
zero,
neg
);
always @(negedge clk) begin
// Buffering
result_buf2 = result_buf;
result_buf = result;
end
always @(posedge clk) begin
result = out;
end
endmodule
| 7.084587 |
module alu_stim (
output reg [15:0] in_1,
output reg [15:0] in_2,
output reg carry_in,
output reg enable,
output reg [4:0] select,
input wire [15:0] data,
input wire carry_out,
input wire zero_flag
);
parameter T = 10;
initial begin
// all inputs are zero
carry_in = 0;
select = 0;
in_1 = 16'b0;
in_2 = 16'b0;
enable = 0;
#T
if (data == 16'bz) begin
$display("test 1 passed");
end else begin
$display("test 1 failed");
end
// first input is all ones and we invert it
carry_in = 0;
select = 5;
in_1 = 16'hffff;
in_2 = 16'h0000;
enable = 1;
#T
if ((data == 16'b0) && (carry_out == 1) && (zero_flag == 1)) begin
$display("test 2 passed");
end else begin
$display("test 2 failed");
end
carry_in = 0;
select = 0;
in_1 = 16'b0;
in_2 = 16'b0;
enable = 0;
#T
// add 5 plus 3
carry_in = 0;
select = 0;
in_1 = 16'd5;
in_2 = 16'd3;
enable = 1;
#T
if ((data == 16'd8) && (carry_out == 0) && (zero_flag == 0)) begin
$display("test 3 passed");
end else begin
$display("test 3 failed");
end
carry_in = 0;
select = 0;
in_1 = 16'b0;
in_2 = 16'b0;
enable = 0;
#T
// subtract 6035 and 3127
carry_in = 0;
select = 1;
in_1 = 16'd6035;
in_2 = 16'd3127;
enable = 1;
#T
if ((data == 16'd2908) && (carry_out == 0) && (zero_flag == 0)) begin
$display("test 4 passed");
end else begin
$display("test 4 failed");
end
carry_in = 0;
select = 0;
in_1 = 16'b0;
in_2 = 16'b0;
enable = 0;
#T
// add with carry in
carry_in = 1;
select = 0;
in_1 = 16'd4941;
in_2 = 16'd1259;
enable = 1;
#T
if ((data == 16'd6201) && (carry_out == 0) && (zero_flag == 0)) begin
$display("test 5 passed");
end else begin
$display("test 5 failed");
end
carry_in = 0;
select = 0;
in_1 = 16'b0;
in_2 = 16'b0;
enable = 0;
#T
// add with carry in
carry_in = 0;
select = 7;
in_1 = 16'd1;
in_2 = 16'd0;
enable = 1;
#T
if ((data == 16'd0) && (carry_out == 0) && (zero_flag == 1)) begin
$display("test 6 passed");
end else begin
$display("test 6 failed");
end
end
endmodule
| 7.211623 |
module alu_structural #(
parameter WIDTH = 4,
parameter SHIFT = 2
) (
input [WIDTH - 1:0] x,
y,
input [SHIFT - 1:0] shamt,
input [ 1:0] operation,
input carry_in,
output zero,
output overflow,
output [WIDTH - 1:0] result
);
wire [4 * WIDTH - 1:0] t; // This ALU supports 4 operations
//Bitwise AND
bitwise_and #(
.WIDTH(WIDTH)
) i_and (
.x(x),
.y(y),
.z(t[WIDTH-1 : 0])
);
//Adder
adder #(
.WIDTH(WIDTH)
) i_adder (
.x (x),
.y (y),
.carry_in (carry_in),
.z (t[2*WIDTH-1 : WIDTH]),
.carry_out(overflow)
);
//Shifter
left_shifter #(
.WIDTH(WIDTH),
.SHIFT(SHIFT)
) i_shifter (
.x (x),
.shamt(shamt),
.z (t[3*WIDTH-1 : 2*WIDTH])
);
//SLT
slt #(
.WIDTH(WIDTH)
) i_slt (
.x(x),
.y(y),
.z(t[4*WIDTH-1 : 3*WIDTH])
);
//Multiplexer
bn_mux_n_1_generate #(
.DATA_WIDTH(WIDTH),
.SEL_WIDTH (2)
) i_mux (
.data(t),
.sel (operation),
.y (result)
);
//Flags
assign zero = (result == 0);
endmodule
| 8.034374 |
module ALUSync (
input wire clk,
input wire reset,
input wire [ 7:0] op, // Operation
input wire [15:0] X, // First Operand
input wire [15:0] Y, // Second Operand
input wire enable,
input wire writeA,
input wire writeF,
output reg [15:0] A,
output wire [15:0] O,
output reg [ 7:0] F
);
wire [3:0] OutF;
// Our device under test
ALU alu (
op,
X,
Y,
F[3:0],
OutF,
O
);
always @(posedge clk) begin
if (reset) begin
A <= 0;
F <= 0;
end else begin
if (enable) begin
if (writeA) A <= O;
F <= {4'b0000, OutF};
end else begin
if (writeA) A <= {8'b0, X[7:0]};
if (writeF) F <= {4'b0, X[11:8]};
end
end
end
// Only for simulation expose the registers
generate
genvar idx;
for (idx = 0; idx < 4; idx = idx + 1) begin : register
wire tmp;
assign tmp = F[idx];
end
endgenerate
endmodule
| 7.755235 |
module: ALU
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALU_T;
// Inputs
reg [31:0] A;
reg [31:0] B;
reg [5:0] func;
reg [1:0] ALUop;
// Outputs
wire zero;
wire [31:0] out;
// Instantiate the Unit Under Test (UUT)
ALU uut (
.A(A),
.B(B),
.func(func),
.ALUop(ALUop),
.zero(zero),
.out(out)
);
initial begin
// Initialize Inputs
A = 32'h12345678;
B = 32'h00001111;
func = 6'b100000;
ALUop = 2'b10;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.795848 |
module ALU_tb;
`include "../src/utils/Assert.vh"
`include "../src/Parameters.vh"
// Input stimulus
reg [XLEN - 1 : 0] A;
reg [XLEN - 1 : 0] B;
reg [2 : 0] control;
// Output
wire [XLEN - 1 : 0] result;
ALU DUT (
.result(result),
.A(A),
.B(B),
.control(control)
);
initial begin
// Group 1 : A = 0, B = -1
#1 $display("Test Group1\n");
control <= ADD_OPCODE;
A <= 32'h00000000;
B <= 32'hFFFFFFFF;
#1 `ASSERT(result, 32'hFFFFFFFF) // A + B
#1 control <= SUB_OPCODE;
#1 `ASSERT(result, 32'h00000001) // A - B
#1 control <= AND_OPCODE;
#1 `ASSERT(result, 32'h00000000) // A & B
#1 control <= OR_OPCODE;
#1 `ASSERT(result, 32'hFFFFFFFF) // A | B
$stop;
end
endmodule
| 6.772917 |
module: alu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`include "mips_16_defs.v"
module alu_tb_0_v;
// Inputs
reg [15:0] a;
reg [15:0] b;
reg [2:0] cmd;
// Outputs
wire [15:0] r;
reg [15:0] rand;
integer i;
// Instantiate the Unit Under Test (UUT)
alu uut (
.a(a),
.b(b),
.cmd(cmd),
.r(r)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
cmd = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
i=0;
while(i<10) begin
test_NC;
test_ADD;
test_SUB;
test_AND;
test_OR;
test_XOR;
test_SL;
test_SR;
test_SRU;
i = i+1;
end
$stop;
$finish;
end
task test_NC;
begin
$write(" ALU_NC \t");
a = $random % 32768;
b = $random % 32768;
cmd = `ALU_NC;
#10
// if(r == 16'bxxxxxxxxxxxxxxxx)
$write("ok ");
// else
// $write("error @ %t , get %d, expect %d", $time, r, a b);
$write("\n");
end
endtask
task test_ADD;
begin
$write(" ALU_ADD \t");
a = $random % 32768;
b = $random % 32768;
cmd = `ALU_ADD;
#10
if(r == a + b)
$write("ok ");
else
$write("error @ %t , get %d, expect %d", $time, r, a+b);
$write("\n");
end
endtask
task test_SUB;
begin
$write(" ALU_SUB \t");
a = $random % 32768;
b = $random % 32768;
cmd = `ALU_SUB;
#10
if(r == a - b)
$write("ok ");
else
$write("error @ %t , get %d, expect %d", $time, r, a-b);
$write("\n");
end
endtask
task test_AND;
begin
$write(" ALU_AND \t");
// a = $random % 32768;
// b = $random % 32768;
a = 16'b0101010101010101;
b = 16'b1010101001010101;
cmd = `ALU_AND;
#10
if(r == 16'b0000000001010101)
// if(r == 16'd85)
$write("ok ");
else
$write("error @ %t , get %d, expect %d", $time, r, a&b);
$write("\n");
end
endtask
task test_OR;
begin
$write(" ALU_OR \t");
a = $random % 32768;
b = $random % 32768;
cmd = `ALU_OR;
#10
if(r == a | b)
$write("ok ");
else
$write("error @ %t , get %d, expect %d", $time, r, a|b);
$write("\n");
end
endtask
task test_XOR;
begin
$write(" ALU_XOR \t");
a = $random % 32768;
b = $random % 32768;
cmd = `ALU_XOR;
#10
if(r == a ^ b)
$write("ok ");
else
$write("error @ %t , get %d, expect %d", $time, r, a^b);
$write("\n");
end
endtask
task test_SL;
begin
$write(" ALU_SL \t");
a = $random % 32768;
b = {$random} % 16;
cmd = `ALU_SL;
#10
if(r == a << b)
$write("ok ");
else
$write("error @ %t , get %d, expect %d", $time, r, a<<b);
$write("\n");
end
endtask
// task test_SR;
// begin
// $write(" ALU_SR \t");
// a = $random % 32768;
// b = {$random} % 16;
// cmd = `ALU_SR;
// #10
// if(r == a / 2**b )
// $write("ok ");
// else
// $write("error @ %t , get %d, expect %d", $time, r, (a/(2**b)));
// $write("\n");
// end
// endtask
task test_SR;
begin
$write(" ALU_SR \t");
a = 16'b1111000011110000;
b = 7;
cmd = `ALU_SR;
#10
if(r == 16'b1111111111100001 )
$write("ok ");
else
$write("error @ %t , get %d, expect %d", $time, r, 16'b1111111111100001);
$write("\n");
end
endtask
task test_SRU;
begin
$write(" ALU_SRU \t");
a = $random % 32768;
b = {$random} % 16;
cmd = `ALU_SRU;
#10
if(r == a >> b )
$write("ok ");
else
$write("error @ %t , get %d, expect %d", $time, r, a >> b);
$write("\n");
end
endtask
endmodule
| 7.023594 |
module alu_test2 (
a,
b,
Cin,
sel,
out,
cOut,
status
);
input [63:0] a, b;
input Cin;
input [4:0] sel;
output [63:0] out;
output cOut;
//-Flags declaration - 4 bits, either true or false
output [3:0] status;
wire [63:0] orOut, andOut, xorOut, adderOut, shiftRight, shiftLeft, a_or_a_invert, b_or_b_invert;
wire flagC = status[0]; // Don't know if "reg" should be added (output reg...)
wire flagZ = status[1]; // Declare "output reg" if it is being assigned in sequential code, such as "always" block.
wire flagO = status[2];
wire flagN = status[3];
assign flagZ = (out == 64'b0);
//assign flagC = (cOut >= sum[64]); //Check if there's a carry out that equals to a size greater than 64 bit sum value. If so, then there's a carry value and Carry flag should cut on.
assign flagC = cOut; //Checks if the result > width.
//assign flagO = ({Cin,Cout[63]} == 64'd64); // Checks if the Carry input and last index (bit) of the carry out, combined, is equal to an overflow bit. (Overflow value may need to be changed)
assign flagO = ~(a_or_a_invert ^ b_or_b_invert) & (a_or_a_invert ^ adderOut);
//({Cin,Cout} < 64'd64); //Checks if the maximum vale of the 64 bit value that can be stored is > than width. If not, then the width is greater which means an overflow.
//assign flagN = (Cout[63] == 1 && (~A || ~B)); //Checks if the last bit of Cout is 1 and if the operation is subtraction. Can add subtraction (1000 - 1111 = 0111) so check if it contains a 1 and then it a negative number. ~A or ~B is -A or -B
assign flagN = out[63]; //((A+B) < 0);
mux_A_2_to_1 u1 (
a,
~a,
sel[0],
a_or_a_invert
);
mux_B_2_to_1 u2 (
b,
~b,
sel[1],
b_or_b_invert
);
orOp u3 (
a_or_a_invert,
b_or_b_invert,
orOut
);
andOp u4 (
a_or_a_invert,
b_or_b_invert,
andOut
);
xorOp u5 (
a_or_a_invert,
b_or_b_invert,
xorOut
);
//Adder u6 (adderOut, cOut, a, b_or_b_invert, Cin);
adder u6 (
a_or_a_invert,
b_or_b_invert,
Cin,
adderOut,
cOut
);
shift_right u7 (
a,
b[5:0],
shiftRight
);
shift_left u8 (
a,
b[5:0],
shiftLeft
);
mux_6_1 u9 (
64'b0,
orOut,
andOut,
xorOut,
adderOut,
shiftRight,
shiftLeft,
64'b0,
sel[4:2],
out
);
endmodule
| 7.455626 |
module mux_A_2_to_1 (
A,
notA,
fsel,
R
);
input [63:0] A, notA;
input fsel;
output reg [63:0] R;
always @(A or notA or fsel) begin
case (fsel)
0: R = A;
1: R = notA;
default: R = 1'bx;
endcase
end
endmodule
| 6.80285 |
module orOp (
A,
B,
result
);
input [63:0] A, B;
output [63:0] result;
assign result = A | B;
//Flags
//Checks if the reuslt is = to 0 that is 64 bit value in binary.
endmodule
| 7.053823 |
module xorOp (
A,
B,
result
);
input [63:0] A, B;
output [63:0] result;
assign result = A ^ B;
//Flags
endmodule
| 6.847488 |
module adder (
addA,
addB,
nic,
sum,
cout
); //by Muhammad
input [63:0] addA, addB;
input nic;
output [63:0] sum;
output cout;
assign {cout, sum} = addA + addB + nic;
endmodule
| 7.4694 |
module full_adder (A, B, Cin, S, Cout);
//input A, B, Cin;
//output S, Cout;
//assign S = A^(B&Cin);
//assign Cout = (A^B)&Cin | A&B;
//endmodule
| 6.882132 |
module Adder(A, B, Cin, S, Cout);
// input [63:0] A, B;
// input Cin;
// output [63:0] S;
// output Cout;
// wire [64:0]carry;
// assign carry[0] = Cin;
// assign Cout = carry[64];
// // use generate block to instantiate 64 full adders
// genvar i;
// generate
// for (i=0; i<64; i=i+1) begin: full_adders // blocks within a generate block need to be named
// full_adder adder_inst (S[i], carry[i+1], A[i], B[i], carry[i]);
// end
// endgenerate
// // this will generate the following code:
// // FullAdder full_adders[0].adder_inst (S[0], carry[1], A[0], B[0], carry[0]);
// // FullAdder full_adders[1].adder_inst (S[1], carry[2], A[1], B[1], carry[1]);
// // ...
// FullAdder full_adders[63].adder_inst (S[63], carry[64], A[63], B[63], carry[63]);
//endmodule
| 7.504432 |
module shift_right (
A_or_B,
shift_amount,
right_shift
);
input [63:0] A_or_B;
input [5:0] shift_amount;
output [63:0] right_shift;
assign right_shift = A_or_B >> shift_amount;
endmodule
| 6.706335 |
module alu_test2_testbench ();
reg [63:0] a, b;
reg Cin;
reg [4:0] sel;
wire [63:0] out;
wire cOut;
wire [3:0] status;
alu_test2 dut (
a,
b,
Cin,
sel,
out,
cOut,
status
);
initial begin
$monitor("sel=%d a=%d b=%d out=%d Cin=%d cOut=%d status=%d", sel, a, b, out, Cin, cOut, status);
#1 a = 64'd3;
b = 64'd1;
sel = 5'b10000;
Cin = 1'd0; //A+1
#1 a = 64'd2;
b = 64'd2;
sel = 5'b10000;
Cin = 1'd0; //A + B
#1 a = 64'd3;
b = 64'd2;
sel = 5'b10010;
Cin = 1'd1; //A - B
#1 a = 64'd3;
b = 64'd1;
sel = 5'b10010;
Cin = 1'd1; //A -1
#1 a = 64'd2;
b = 64'd4;
sel = 5'b10001;
Cin = 1'd1; //-A
#1 a = 64'd0;
b = 64'd0;
sel = 5'b10000;
Cin = 1'd0; // F = 0, also the zero flag
#1 a = 64'd1;
b = 64'd0;
sel = 5'b10000;
Cin = 1'd0; // A
#1 a = 64'd1;
b = 64'd0;
sel = 5'b01110;
Cin = 1'd0; //A~
#1 a = 64'd2;
b = 64'd1;
sel = 5'b10100;
Cin = 1'd0; // A&B
#1 a = 64'd3;
b = 64'd4;
sel = 5'b00100;
Cin = 1'd0; //A|B
#1 a = 64'd2;
b = 64'd5;
sel = 5'b01100;
Cin = 1'd0; //A^B
#1 a = 64'd23;
b = 5'd3;
sel = 5'b10100;
Cin = 1'd0; //shift right
#1 a = 64'd23;
b = 5'd3;
sel = 5'b11000;
Cin = 1'd0; //shift left
#1 a = 64'd2;
b = 64'd4;
sel = 5'b10010;
Cin = 1'd1; //Negative flag
#1 a = 64'd4;
b = 64'd6;
sel = 5'b10000;
Cin = 1'd1; //carry out
#1 a = 64'd7;
b = 64'd2;
sel = 5'b10010;
Cin = 1'd1; //overflow
end
endmodule
| 6.563699 |
module: ALU
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALU_TF;
// Inputs
reg [63:0] A;
reg [63:0] B;
reg [2:0] ALUOp;
// Outputs
wire [63:0] ALUResult;
// Instantiate the Unit Under Test (UUT)
ALU uut (
.A(A),
.B(B),
.ALUOp(ALUOp),
.ALUResult(ALUResult)
);
initial begin
// Initialize Inputs
A = 0;
B = 0;
ALUOp = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.795848 |
module ALU (
input [15:0] A,
input [15:0] B,
input [3:0] opcode_ALU,
input [1:0] alu_mode,
output reg [31:0] Alu_out,
output wire C,
Z,
EQ,
GT,
ZA,
ZB
);
reg [ 3:0] opcode_au;
reg [ 3:0] opcode_lu;
reg [ 3:0] opcode_shifter;
wire [16:0] out_au;
wire [31:0] out_prod;
wire [15:0] out_lu;
wire [15:0] out_shift;
assign Z = (Alu_out == 16'd0) ? 1 : 0;
always @(*) begin
if (alu_mode == 2'b00) begin
opcode_au = opcode_ALU;
Alu_out <= out_au[15:0];
end else if (alu_mode == 2'b01) begin
opcode_lu = opcode_ALU;
Alu_out <= out_lu;
end else if (alu_mode == 2'b10) begin
opcode_shifter = opcode_ALU;
Alu_out <= out_shift;
end else begin
Alu_out <= 16'd0;
end
end
AU m1 (
A,
B,
opcode_au,
Cy,
out_au,
out_prod
);
LU m2 (
A,
B,
opcode_lu,
EQ,
GT,
ZA,
ZB,
out_lu
);
barrelShifter m3 (
A,
B,
opcode_shifter,
out_shift
);
endmodule
| 7.960621 |
module ALU_toplevel (
FS,
A,
B,
out,
zero_flag
);
parameter nBit = 16;
input [2:0] FS;
input [nBit-1:0] A, B;
output reg [nBit-1:0] out;
output reg zero_flag;
wire cout;
wire [nBit-1:0] arith_out;
wire op_sel;
assign op_sel = FS[2] | FS[1];
add_sub #(nBit) CE1 (
.A(A),
.B(B),
.cond(FS[0]),
.out(arith_out),
.cout(cout)
);
always @(*) begin
if (op_sel == 0) out <= arith_out;
else begin
case (FS[1:0])
2'b10: out <= A & B;
2'b11: out <= A | B;
2'b00: out <= A ^ B;
2'b01: out <= ~A;
endcase
end
end
always @(*) begin
if (out != 0) zero_flag <= 1'b0;
else begin
if (op_sel == 0) begin
if (FS[0] == 1 & cout == 1) zero_flag <= 1'b1;
else if (FS[0] == 0 & cout == 0) zero_flag <= 1'b1;
else zero_flag <= 1'b0;
end else zero_flag <= 1'b1;
end
end
endmodule
| 7.412095 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ALU_topmodule(output [W-1:0] R0,
output c_out,
input [2:0] ALUOp,
input [W-1:0] R2,
input [W-1:0] R3,
input clk);
parameter W = 32;
wire [W-1:0] R1;
wire tmp_c_out;
ALU #(.W(W)) alu (R1, tmp_c_out, ALUOp, R2, R3);
Para_Reg #(.W(W)) reg0 (clk, R1, R0);
Para_Reg #(.W(1)) reg1 (clk, tmp_c_out, c_out);
endmodule
| 7.088073 |
module
// Module Name: /ad/eng/users/g/m/gmerritt/Desktop/tmp/Lab5/ALU_topmodule_tb.v
// Project Name: Lab5
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: ALU_topmodule
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALU_topmodule_tb;
parameter W = 8;
// Inputs
reg [2:0] ALUOp;
reg [W-1:0] R2;
reg [W-1:0] R3;
reg clk;
// Outputs
wire [W-1:0] R0;
wire c_out;
wire c_out_verify;
wire [W-1:0] R0_verify;
wire error_flag;
// Instantiate the Unit Under Test (UUT)
ALU_topmodule
#(.W(W))
uut (
.R0(R0),
.c_out(c_out),
.ALUOp(ALUOp),
.R2(R2),
.R3(R3),
.clk(clk)
);
// Verification module
Verification_ALU
#(.W(W))
Verification
(
.R0(R0_verify),
.c_out(c_out_verify),
.ALUOp(ALUOp),
.R2(R2),
.R3(R3),
.clk(clk)
);
// Assign Error_flag
assign error_flag = (c_out != c_out_verify || R0 != R0_verify);
// Verification logic
always@(posedge clk)
begin
if(error_flag)
$display("Error occurs when R2 = %d, R3 = %d\n", R2, R3);
end
// Define clk signal for Verfication purpose
always #5 clk = ~clk;
//always #50 assign ALUOp = ALUOp + 1'b1;
initial begin
// Initialize Inputs
ALUOp = 3'd0;
R2 = 0;
R3 = 0;
clk = 0;
// Wait 100 ns for global reset to finish
#100;
ALUOp = 3'd6;
R2 = 8'hFA;
R3 = 8'h3A;
#40;
R2 = 8'h3A;
R3 = 8'hFA;
#40;
R2 = 8'h00;
R3 = 8'hFA;
#40;
R2 = 8'h00;
R3 = 8'h3A;
#40;
R2 = 8'hFA;
R3 = 8'h00;
#40;
R2 = 8'h3A;
R3 = 8'h00;
// Add stimulus here
end
endmodule
| 6.999332 |
module alu_unconditional_jal (
input clock,
input alu_unconditional_jal_enable,
input [31:0] immediate20_jtype,
output reg [31:0] rd_value,
input [31:0] pc,
output reg [31:0] next_pc
);
always @(posedge clock & alu_unconditional_jal_enable) begin
next_pc <= pc + immediate20_jtype;
rd_value <= pc + 4;
end
always @(posedge clock & !alu_unconditional_jal_enable) begin
next_pc <= `HIGH_IMPEDANCE;
rd_value <= `HIGH_IMPEDANCE;
end
endmodule
| 7.857872 |
module alu_unconditional_jalr (
input clock,
input alu_unconditional_jalr_enable,
input [31:0] immediate12_itype,
input [31:0] rs1_value,
input [ 2:0] funct3,
output reg [31:0] rd_value,
input [31:0] pc,
output reg [31:0] next_pc
);
always @(posedge clock & alu_unconditional_jalr_enable) begin
next_pc <= rs1_value + immediate12_itype;
rd_value <= pc + 4;
end
always @(posedge clock & !alu_unconditional_jalr_enable) begin
next_pc <= `HIGH_IMPEDANCE;
rd_value <= `HIGH_IMPEDANCE;
end
endmodule
| 7.857872 |
module alu_unit #(
parameter WIDTH = 6
) (
input [WIDTH-1:0] a,
b,
input [3:0] func,
output reg [WIDTH-1:0] y,
output reg OF
);
always @(*) begin
case (func)
4'b0000: begin
y = a + b;
OF = (~a[WIDTH-1] & ~b[WIDTH-1] & y[WIDTH-1] | a[WIDTH-1] & b[WIDTH-1] & ~y[WIDTH-1]);
end
4'b0001: begin
y = a - b;
OF = (~a[WIDTH-1] & b[WIDTH-1] & y[WIDTH-1] | a[WIDTH-1] & ~b[WIDTH-1] & ~y[WIDTH-1]);
end
4'b0010: begin
y = (a == b);
OF = 0;
end
4'b0011: begin
y = (a < b);
OF = 0;
end
4'b0100: begin
y = ($signed(a) < $signed(b));
OF = 0;
end
4'b0101: begin
y = a & b;
OF = 0;
end
4'b0110: begin
y = a | b;
OF = 0;
end
4'b0111: begin
y = a ^ b;
OF = 0;
end
4'b1000: begin
y = a >> b;
OF = 0;
end
4'b1001: begin
y = a << b;
OF = 0;
end
default: begin
y = 0;
OF = 0;
end
endcase
end
endmodule
| 7.19177 |
module XOR (
x,
y,
z
);
input [63:0] x, y;
output [63:0] z;
genvar i;
generate
for (i = 0; i < 64; i = i + 1) begin
xor (z[i], x[i], y[i]);
end
endgenerate
endmodule
| 7.095291 |
module AND (
x,
y,
z
);
input [0:63] x, y;
output [0:63] z;
genvar i;
generate
for (i = 0; i < 64; i = i + 1) begin
and (z[i], x[i], y[i]);
end
endgenerate
endmodule
| 6.925853 |
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