code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module mux2to1_16 (
input [15:0] inp1,
input [15:0] inp2,
input sel,
output reg [15:0] muxOut
);
always @(inp1, inp2, sel) begin
if (sel == 1'b0) muxOut = inp1;
else muxOut = inp2;
end
endmodule
| 7.41547 |
module mux3to1 (
input [15:0] inp1,
inp2,
inp3,
input [1:0] sel,
output reg [15:0] muxOut
);
always @(inp1, inp2, inp3, sel) begin
if (sel == 2'b00) muxOut = inp1;
else if (sel == 2'b01) muxOut = inp2;
else muxOut = inp3;
end
endmodule
| 6.860137 |
module PCMux3to1 (
input [15:0] inp1,
inp2,
inp3,
input [1:0] sel,
output reg [15:0] muxOut
);
always @(inp1, inp2, inp3, sel) begin
if (sel == 2'b01) muxOut = inp2;
else if (sel == 2'b10) muxOut = inp3;
else muxOut = inp1;
end
endmodule
| 6.594744 |
module forwardingUnit (
input [2:0] presentRs,
input [2:0] presentRt,
input [2:0] exmemRd,
input [2:0] memwbRd,
input exmemregwrite,
input memwbregwrite,
output reg [1:0] muxsourcea
);
always @(presentRs, presentRt, exmemRd, memwbRd, exmemregwrite, memwbregwrite) begin
if (exmemregwrit... | 6.627011 |
module dataMem (
input clk,
input reset,
input regWrite,
input decOut1b,
input [7:0] init,
input [7:0] d_in,
output [7:0] q_out
);
D_ff_Mem dMem0 (
clk,
reset,
regWrite,
decOut1b,
init[0],
d_in[0],
q_out[0]
);
D_ff_Mem dMem1 (
clk,
... | 6.754704 |
module alu (
opcode, // alu function select
a, // a operand
b, // b operand
cin, // carry input
ya, // data output
yb, // data output
cvnz_a, // a output flags
cvnz_b // b output flags
);
input [2:0] opcode;
input [31:0] a;
input [31:0] b;
input cin;
output [31:0] ya;... | 7.673494 |
module testALU (
x,
y,
opcode,
f,
overflow,
cout,
zero
);
input [31:0] f;
input cout, overflow, zero;
output [31:0] x, y;
output [2:0] opcode;
reg [31:0] x, y;
reg [2:0] opcode;
assign overflow = 0;
always @(f) begin
$display($time);
end
initial begin
if ($value... | 7.063407 |
module alu (
x,
y,
opcode,
f,
overflow,
cout,
zero
);
input [31:0] x, y;
input [2:0] opcode;
output overflow, zero, cout;
output [31:0] f;
wire [2:0] opoverflow;
wire [31:0] f0, f1, f2, f3, f4, result;
wire w5, zero, isoverflowed, cout;
add op0 (
x,
y,
f0,
... | 7.914753 |
module fulladder (
a,
b,
c,
s,
cout
);
input a, b, c;
output s, cout;
xor #3 g1 (w1, a, b), g2 (s, w1, c);
and #2 g3 (w2, c, b), g4 (w3, c, a), g5 (w4, a, b);
or #6 g6 (cout, w2, w3, w4);
endmodule
| 7.454465 |
module mux8to1 (
d0,
d1,
d2,
d3,
d4,
d5,
d6,
d7,
s0,
s1,
s2,
f
);
input d0, d1, d2, d3, d4, d5, d6, d7, s0, s1, s2;
output f;
mux4to1 mux0 (
d0,
d1,
d2,
d3,
s0,
s1,
w1
);
mux4to1 mux1 (
d4,
d5,
d6,
... | 7.465042 |
module mux4to1 (
d0,
d1,
d2,
d3,
s0,
s1,
f
);
input d0, d1, d2, d3, s0, s1;
output f;
mux2to1 mux0 (
d0,
d1,
s0,
w1
);
mux2to1 mux1 (
d2,
d3,
s0,
w2
);
mux2to1 mux2 (
w1,
w2,
s1,
f
);
endmodule
| 7.010477 |
module mux2to1 (
d0,
d1,
s0,
f
);
input d0, d1, s0;
output f;
and #2(w17, d1, s0);
not #1(w15, s0);
and #2(w18, w15, d0);
or #6(f, w17, w18);
endmodule
| 7.107199 |
module testALU (
x,
y,
opcode,
f,
overflow,
cout,
zero
);
input [31:0] f;
input cout, overflow, zero;
output [31:0] x, y;
output [2:0] opcode;
reg [31:0] x, y;
reg [2:0] opcode;
assign overflow = 0;
initial begin
/*
$display("===========================================... | 7.063407 |
module alu (
x,
y,
opcode,
f,
overflow,
cout,
zero
);
input [31:0] x, y;
input [2:0] opcode;
output overflow, zero, cout;
output [31:0] f;
wire [2:0] opoverflow;
wire [31:0] f0, f1, f2, f3, f4, result;
wire w5, zero, isoverflowed, cout;
add op0 (
x,
y,
f0,
... | 7.914753 |
module fulladder (
a,
b,
c,
s,
cout
);
input a, b, c;
output s, cout;
xor #3 g1 (w1, a, b), g2 (s, w1, c);
and #2 g3 (w2, c, b), g4 (w3, c, a), g5 (w4, a, b);
or #6 g6 (cout, w2, w3, w4);
endmodule
| 7.454465 |
module mux8to1 (
d0,
d1,
d2,
d3,
d4,
d5,
d6,
d7,
s0,
s1,
s2,
f
);
input d0, d1, d2, d3, d4, d5, d6, d7, s0, s1, s2;
output f;
mux4to1 mux0 (
d0,
d1,
d2,
d3,
s0,
s1,
w1
);
mux4to1 mux1 (
d4,
d5,
d6,
... | 7.465042 |
module mux4to1 (
d0,
d1,
d2,
d3,
s0,
s1,
f
);
input d0, d1, d2, d3, s0, s1;
output f;
mux2to1 mux0 (
d0,
d1,
s0,
w1
);
mux2to1 mux1 (
d2,
d3,
s0,
w2
);
mux2to1 mux2 (
w1,
w2,
s1,
f
);
endmodule
| 7.010477 |
module mux2to1 (
d0,
d1,
s0,
f
);
input d0, d1, s0;
output f;
and #2(w17, d1, s0);
not #1(w15, s0);
and #2(w18, w15, d0);
or #6(f, w17, w18);
endmodule
| 7.107199 |
module ALU_reg (
clk,
alu_out,
alu_out_reg,
dm_addr,
dm_addr_reg
); //存储ALU计算结果和dm地址
input clk;
input [31:0] alu_out;
output reg [31:0] alu_out_reg;
input [9:0] dm_addr;
output reg [9:0] dm_addr_reg;
always @(posedge clk) begin
alu_out_reg <= alu_out;
dm_addr_reg <= dm_addr;
e... | 7.556625 |
module ALU_Reg1_Mux (
sel,
reg1_val,
mem_forward,
wb_forward,
alu_val1
);
input [1:0] sel;
input [15:0] reg1_val, mem_forward, wb_forward;
output reg [15:0] alu_val1;
always @(*) begin
case (sel)
0: alu_val1 = reg1_val;
1: alu_val1 = mem_forward;
2: alu_val1 = wb_for... | 7.362679 |
module ALU_Reg2_Mux (
sel,
reg2_val,
mem_forward,
wb_forward,
se_const,
alu_val2
);
input [1:0] sel;
input [15:0] reg2_val, mem_forward, wb_forward, se_const;
output reg [15:0] alu_val2;
always @(*) begin
case (sel)
0: alu_val2 = reg2_val;
1: alu_val2 = mem_forward;
... | 7.38686 |
module ALU_Register (
// System Signals
input clk,
input rst,
// Values In
input [7:0] bus,
// Control signals registers
input AI,
input BI,
input SUB,
// Flags
output CARRY,
output ZERO,
// Output Values
output [7:0] A_out,
output [7:0] B_out,
output [7:0... | 6.599559 |
module ALU_registerfile (
clk,
reset_n,
wAddr,
wData,
we,
rAddr,
rData
); //register file with 16 data
input clk, reset_n, we;
input [3:0] wAddr, rAddr;
input [31:0] wData;
output reg [31:0] rData;
reg [31:0] data0;
reg [31:0] data1;
reg [31:0] data2;
reg [31:0] data3;
re... | 6.636963 |
module ALU_registerfile_2 (
clk,
reset_n,
wAddr,
wData,
we,
re,
rAddr,
rData
); //register file with 16 data
input clk, reset_n, we, re;
input [3:0] wAddr, rAddr;
input [31:0] wData;
output reg [31:0] rData;
reg [31:0] data0;
reg [31:0] data1;
reg [31:0] data2;
reg [31:... | 6.636963 |
module alu_register_immediate (
input clock,
input alu_register_immediate_enable,
input [ 2:0] funct3,
input [31:0] rs1_value,
input [31:0] immediate12_itype,
output reg [31:0] rd_value
);
parameter [2:0] ADDI = 3'h0;
parameter [2:0] SLTI = 3'h2;
par... | 6.725706 |
module alu_register_register (
input clock,
input alu_register_register_enable,
input [ 2:0] funct3,
input [ 6:0] funct7,
input [31:0] rs1_value,
input [31:0] rs2_value,
output [31:0] rd_value
);
alu_select alu_select_0 (
.clock(clock),
.alu_select_enable(a... | 6.725706 |
module alu_reg_ram (
READA,
READB,
clock,
write,
reset,
writeReg,
data,
readA,
readB,
sel,
muxSel,
cin,
writeRam,
ramOut,
Cout,
status,
aluOut
);
input clock;
input write;
input reset;
input [4:0] writeReg;
input [63:0] data;
input [4:0] re... | 7.20598 |
module mux_Aout_2to1 (
A_reg_out,
Writeregister,
Sel,
out
);
input [63:0] A_reg_out;
input [4:0] Writeregister;
input Sel;
output wire [63:0] out;
assign out = Sel == 0 ? A_reg_out : Sel == 1 ? Writeregister : 1'bx;
endmodule
| 7.427807 |
module alu_reg_ram_testbench ();
reg clock;
reg write;
reg reset;
reg [4:0] writeReg;
reg [63:0] data;
reg [4:0] readA;
reg [4:0] readB;
reg [4:0] sel;
reg muxSel;
reg cin;
reg writeRam;
wire [63:0] ramOut;
wire Cout;
wire [3:0] status;
wire [63:0] aluOut;
wire [63:0] READA;
wire [63:0... | 7.109342 |
module Alu_RISC (
alu_zero_flag,
alu_out,
data_1,
data_2,
sel
);
parameter word_size = 10, op_size = 4;
parameter data_size = 8;
// Opcodes
// Opcodes
parameter ADD = 0, SUB = 1, AND = 2, OR = 3, NOT = 4;
parameter JUMP = 4'b011x, STORE = 4'b100x, LOAD = 4'b101x, SAVE = 4'b11xx;
outpu... | 7.962632 |
module alu_ror (
input [15:0] operand1,
input [3:0] immediate_offset,
output reg [15:0] dout
);
always @(*) begin
case (immediate_offset)
4'd0: dout = operand1;
4'd1: dout = {operand1[0], operand1[15:1]};
4'd2: dout = {operand1[1:0], operand1[15:2]};
4'd3: dout = {operand1[2:0... | 6.515871 |
module alu_rs2_mux (
input clock,
input reset,
input [31:0] io_pc,
input [31:0] io_imm_s,
input [31:0] io_imm_i,
input [31:0] io_rs2,
input [1:0] io_rs2_mux_sel,
output [31:0] io_to_alu_b
);
wire _T_14;
wire _T_15;
wire _T_16;
wire [31:0] _T_19;
wire [31:0] _T_20;
wire [31:0]... | 6.856232 |
module alu_rs2_mux_tb ();
reg clk;
reg rst;
reg [31:0] pc;
reg [31:0] imm_s;
reg [31:0] imm_i;
reg [31:0] rs2;
reg [ 1:0] sel;
wire [31:0] to_alu_b;
alu_rs2_mux rs2_mux (
.clock(clk),
.reset(rst),
.io_rs2(rs2),
.io_imm_s(imm_s),
.io_imm_i(imm_i),
... | 6.892984 |
module alu_rv (
input clock,
// feed from decode
input [31:0] instruction,
input alu_branch_enable,
input alu_unconditional_jalr_enable,
input alu_unconditional_jal_enable,
input alu_upper_immediate_lui_enable,
input alu_upper_immediate_au... | 6.807046 |
module ALU_RV32I #(
parameter n = 32
) (
input [n-1:0] op1,
op2,
input [3:0] op_code,
output reg [n-1:0] dout,
output zero_flag,
sign_out,
output reg cry_out
);
wire [4:0] shift_amount = op2[4:0];
wire [n-1:0] shift_l_1, shift_l_2, shift_l_4, shift_l_8, shift_l;
wire [n-1:0] shif... | 7.540216 |
module alu (
A,
B,
C,
Opcode,
Flags
);
input [3:0] A, B;
input [1:0] Opcode;
output reg [3:0] C;
output reg [4:0] Flags;
parameter ADDU = 2'b00;
parameter ADD = 2'b01;
parameter SUB = 2'b10;
parameter CMP = 2'b11;
always @(A, B, Opcode) begin
case (Opcode)
ADDU: begin
... | 7.41692 |
module alu_sel (
input alu1_sel,
input alu2_sel,
input [31:0] rs1_data,
input [31:0] rs2_data,
input [31:0] pc,
input [31:0] imm,
output [31:0] alu1_data,
output [31:0] alu2_data
);
assign alu1_data = alu1_sel ? pc : rs1_data;
assign alu2_data = alu2_sel ? imm : rs2_data;
endmodule... | 8.153317 |
module alu_select (
ctl_alu_oe,
ctl_alu_shift_oe,
ctl_alu_op2_oe,
ctl_alu_res_oe,
ctl_alu_op1_oe,
ctl_alu_bs_oe,
ctl_alu_op1_sel_bus,
ctl_alu_op1_sel_low,
ctl_alu_op1_sel_zero,
ctl_alu_op2_sel_zero,
ctl_alu_op2_sel_bus,
ctl_alu_op2_sel_lq,
ctl_alu_sel_op2_neg,
ctl... | 6.697911 |
module Rev 0.0 06/13/2012 **/
/** **/
/*******************************************************************************************/
module alu_shft (shft_c, shft_out, alub_in, aluop_reg,... | 8.238592 |
module alu_shift (
a_in,
b_in,
op_in,
z_flag_in,
s_flag_in,
c_flag_in,
ovr_flag_in,
c_out,
z_flag_out,
s_flag_out,
c_flag_out,
ovr_flag_out,
op_active
);
parameter data_wl = 16;
parameter op_wl = 8;
input [data_wl-1:0] a_in;
input [data_wl-1:0] b_in;
input ... | 7.914769 |
module ALU_Shifts_1_tb (
output wire done,
error
);
ALU_Shifts_base_tb #(
.DATA_WIDTH (32),
.FILE_SOURCE ("../testbench/data/core/ALU_Shifts_1_tb_data.txt"),
.FILE_COMPARE("../testbench/data/core/ALU_Shifts_1_tb_compare.txt")
) dut (
.done (done),
.error(error)
);
endmodule
... | 7.323472 |
module ALU_Shifts_base_tb #(
parameter DATA_WIDTH = 8,
parameter FILE_SOURCE = "",
parameter FILE_COMPARE = ""
) (
output wire done,
error
);
localparam FLAGS_WIDTH = 4;
localparam OPCODE_WIDTH = 4;
localparam FS_DATA_WIDTH = (2 * DATA_WIDTH) + OPCODE_WIDTH + 1;
localparam FC_DATA_WIDTH =... | 8.364816 |
module ALU_SLAVE (
clk,
reset_n,
s_sel,
s_wr,
s_addr,
s_din,
s_dout,
s_interrupt,
op_start,
opdone_clear,
status,
result_pop,
wr_en_inst,
inst,
result,
rAddr,
rData,
wAddr,
wData,
we_rf,
rd_ack_result
);
input clk, reset_n, s_sel, s_... | 6.703122 |
module alu_sll_16bit (
A,
S,
Z
);
parameter N = 32;
//port definitions
input wire [(N-1):0] A;
input wire [4:0] S;
output wire [(N-1):0] Z;
wire [(N-1):0] sl2, sl4, sl8, sl16;
alu_sl_16bit #(
.N(N)
) MUX5 (
.A(A),
.S(S[4]),
.Z(sl16)
);
alu_sl_8bit #(
.N(N... | 6.746768 |
module: alu_shift_1bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_sll_16bit_test;
// parameter width
parameter N = 32;
// testing variables
reg [N:0] i;
reg [N:0] j;
... | 6.550056 |
module alu_sll_4bit (
A,
S,
Z
);
parameter N = 32;
//port definitions
input wire [(N-1):0] A;
input wire [2:0] S;
output wire [(N-1):0] Z;
wire [(N-1):0] sl2, sl4, sl8, sl16;
alu_sl_4bit #(
.N(N)
) MUX3 (
.A(A),
.S(S[2]),
.Z(sl4)
);
alu_sl_2bit #(
.N(N)
... | 6.511646 |
module: alu_shift_1bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_sll_4bit_test;
// parameter width
parameter N = 32;
// testing variables
reg [N:0] i;
reg [N:0] j;
... | 6.550056 |
module alu_sll_8bit (
A,
S,
Z
);
parameter N = 32;
//port definitions
input wire [(N-1):0] A;
input wire [3:0] S;
output wire [(N-1):0] Z;
wire [(N-1):0] sl2, sl4, sl8, sl16;
alu_sl_8bit #(
.N(N)
) MUX4 (
.A(A),
.S(S[3]),
.Z(sl8)
);
alu_sl_4bit #(
.N(N)
... | 6.640502 |
module: alu_shift_1bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_sll_8bit_test;
// parameter width
parameter N = 32;
// testing variables
reg [N:0] i;
reg [N:0] j;
... | 6.550056 |
module: alu_shift_1bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_sll_test;
// parameter width
parameter N = 32;
// testing variables
reg [N:0] i;
reg [N:0] j;
// I... | 6.550056 |
module alu_slt (
A,
B,
Z
);
parameter WIDTH = 32;
//port definitions
input wire [(WIDTH - 1):0] A, B;
output wire [(WIDTH - 1):0] Z;
// Wires to compute the subtraction
wire [(WIDTH - 1):0] AminusB;
wire OF;
alu_sub_32bit SUB (
.A (A),
.B (B),
.S (AminusB),
.OF(OF)... | 6.541333 |
module alu_sl_8bit (
A,
S,
Z
);
parameter N = 2;
//port definitions
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[7:0] = 8'b0;
assign B[N-1:8] = A[N-9:0];
mux_2to1 #(
.N(N)
) MUX (
.X(A),
.Y(B),
.S(S),
.Z(Z)... | 6.652799 |
module ALU_small (
a,
b,
out
);
parameter DATA_WIDTH = 8;
input [DATA_WIDTH - 1:0] a;
input [DATA_WIDTH - 1:0] b;
output [DATA_WIDTH:0] out;
wire tmp;
FS_8 FS_8_0 (
.a(a),
.b(b),
.out(out[DATA_WIDTH-1:0]),
.cin(1'b0),
.cout(out[DATA_WIDTH])
);
endmodule
| 8.217661 |
module alu_somma (
output [N-1:0] z,
input [N-1:0] x,
input [N-1:0] y
);
parameter N = 32;
assign #5 z = x + y;
endmodule
| 7.269742 |
module alu_sra (
A,
S,
Z
);
parameter N = 32;
input wire [(N-1):0] A;
input wire [4:0] S;
output wire [(N-1):0] Z;
wire [(N-1):0] shifted2, shifted4, shifted8, shifted16;
wire sign;
assign sign = A[31];
alu_sra_16bit #(
.N(N)
) MUX5 (
.A(A),
.S(S[4]),
.Z(shifted1... | 6.905444 |
module alu_sra_16bit (
A,
S,
Z,
sign
);
parameter N = 2;
//port definitions
input wire sign;
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[N-17:0] = A[N-1:16];
assign B[N-1:N-16] = {16{sign}};
mux_2to1 #(
.N(N)
) MUX (
... | 8.139889 |
module alu_sra_1bit (
A,
S,
Z,
sign
);
parameter N = 2;
//port definitions
input wire sign;
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[(N-2):0] = A[N-1:1];
assign B[(N-1)] = sign;
mux_2to1 #(
.N(N)
) MUX (
.X(A),
... | 7.347886 |
module alu_sra_2bit (
A,
S,
Z,
sign
);
parameter N = 2;
//port definitions
input wire sign;
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[N-3:0] = A[N-1:2];
assign B[N-1:N-2] = {2{sign}};
mux_2to1 #(
.N(N)
) MUX (
.X(A)... | 7.958679 |
module alu_sra_32bit (
A,
S,
Z
);
parameter N = 2;
//port definitions
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[N-1:0] = 32'hffffffff;
mux_2to1 #(
.N(N)
) MUX (
.X(A),
.Y(B),
.S(S),
.Z(Z)
);
endmodule
| 7.367412 |
module alu_sra_4bit (
A,
S,
Z,
sign
);
parameter N = 2;
//port definitions
input wire sign;
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[N-5:0] = A[N-1:4];
assign B[N-1:N-4] = {4{sign}};
mux_2to1 #(
.N(N)
) MUX (
.X(A)... | 7.767157 |
module alu_sra_8bit (
A,
S,
Z,
sign
);
parameter N = 2;
//port definitions
input wire sign;
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[N-9:0] = A[N-1:8];
assign B[N-1:N-8] = {8{sign}};
mux_2to1 #(
.N(N)
) MUX (
.X(A)... | 8.214987 |
module: alu_shift_1bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_sra_test;
// parameter width
parameter N = 32;
// testing variables
reg [N:0] i;
reg [N:0] j;
// I... | 6.550056 |
module alu_src (
input [31:0] busA,
busB,
PC,
imm,
input ALUAsrc,
input [1:0] ALUBsrc,
output reg [31:0] ALUA,
ALUB
);
always @(*) begin
ALUA = (ALUAsrc ? PC : busA);
end
always @(*) begin
case (ALUBsrc)
2'b00: ALUB = busB;
2'b01: ALUB = imm;
2'b10: ... | 7.234612 |
module alu_src_selector (
// input [1:0] ID_EX_ALU_srcA,
input [1:0] forward_A,
input [1:0] forward_B,
input [31:0] ID_EX_rdata1,
input [31:0] ID_EX_rdata2,
input [31:0] EX_MEM_ALU_Result,
input [31:0] WB_wdata,
input [31:0] WB_wdata_reg,
input [31:0] ID_EX_U_sign_extend,
input... | 8.270262 |
module alu_srl (
A,
S,
Z
);
parameter N = 32;
//port definitions
input wire [(N-1):0] A;
input wire [4:0] S;
output wire [(N-1):0] Z;
wire [(N-1):0] sr2, sr4, sr8, sr16;
alu_sr_16bit #(
.N(N)
) MUX5 (
.A(A),
.S(S[4]),
.Z(sr16)
);
alu_sr_8bit #(
.N(N)
)... | 6.539311 |
module alu_srl_32bit (
A,
S,
Z
);
parameter N = 32;
//port definitions
input wire [(N-1):0] A;
input wire [5:0] S;
output wire [(N-1):0] Z;
wire [(N-1):0] shifted2;
alu_shift_16bit #(
.N(N)
) MUX5 (
.A(A),
.S(S[4]),
.Z(shifted2)
);
alu_shift_8bit #(
.N(N... | 6.756015 |
module: alu_shift_1bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_srl_32bit_test;
// parameter width
parameter N = 32;
// testing variables
reg [N:0] i;
reg [6:0] j;
... | 6.550056 |
module: alu_shift_1bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_srl_test;
// parameter width
parameter N = 32;
// testing variables
reg [N:0] i;
reg [N:0] j;
// I... | 6.550056 |
module alu_sr_16bit (
A,
S,
Z
);
parameter N = 2;
//port definitions
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[N-17:0] = A[N-1:16];
assign B[N-1:N-16] = 16'b0;
mux_2to1 #(
.N(N)
) MUX (
.X(A),
.Y(B),
.S(S),
... | 7.026969 |
module alu_sr_1bit (
A,
S,
Z
);
parameter N = 2;
//port definitions
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[(N-2):0] = A[N-1:1];
assign B[(N-1)] = 1'b0;
mux_2to1 #(
.N(N)
) MUX (
.X(A),
.Y(B),
.S(S),
.... | 6.741968 |
module alu_sr_2bit (
A,
S,
Z
);
parameter N = 2;
//port definitions
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[N-3:0] = A[N-1:2];
assign B[N-1:N-2] = 2'b0;
mux_2to1 #(
.N(N)
) MUX (
.X(A),
.Y(B),
.S(S),
.... | 6.784963 |
module alu_sr_32bit (
A,
S,
Z
);
parameter N = 2;
//port definitions
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[N-1:0] = 32'd0;
mux_2to1 #(
.N(N)
) MUX (
.X(A),
.Y(B),
.S(S),
.Z(Z)
);
endmodule
| 6.774447 |
module alu_sr_4bit (
A,
S,
Z
);
parameter N = 2;
//port definitions
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[N-5:0] = A[N-1:4];
assign B[N-1:N-4] = 4'b0;
mux_2to1 #(
.N(N)
) MUX (
.X(A),
.Y(B),
.S(S),
.... | 6.709153 |
module alu_sr_8bit (
A,
S,
Z
);
parameter N = 2;
//port definitions
input wire [(N-1):0] A;
input wire S;
output wire [(N-1):0] Z;
wire [(N-1):0] B;
assign B[N-9:0] = A[N-1:8];
assign B[N-1:N-8] = 8'b0;
mux_2to1 #(
.N(N)
) MUX (
.X(A),
.Y(B),
.S(S),
.... | 7.271255 |
module ALU_stage (
input clk,
input [15:0] register_content1,
input [15:0] register_content2,
input [7:0] immediate_value,
input [2:0] alu_control_signal,
input alu_src_signal,
output reg [15:0] result_buf,
output reg [15:0] result_buf2
);
wire carry, zero, neg;
wire [15:0] out;
r... | 7.084587 |
module alu_stim (
output reg [15:0] in_1,
output reg [15:0] in_2,
output reg carry_in,
output reg enable,
output reg [4:0] select,
input wire [15:0] data,
input wire carry_out,
input wire zero_flag
);
parameter T = 10;
initial begin
// all inputs are zero
carry_in = 0;
... | 7.211623 |
module alu_structural #(
parameter WIDTH = 4,
parameter SHIFT = 2
) (
input [WIDTH - 1:0] x,
y,
input [SHIFT - 1:0] shamt,
input [ 1:0] operation,
input carry_in,
output zero,
output overflow,
output [WIDTH - 1:0] result
);
... | 8.034374 |
module ALUSync (
input wire clk,
input wire reset,
input wire [ 7:0] op, // Operation
input wire [15:0] X, // First Operand
input wire [15:0] Y, // Second Operand
input wire enable,
input wire writeA,
input wire writeF,
output reg ... | 7.755235 |
module: ALU
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALU_T;
// Inputs
reg [31:0] A;
reg [31:0] B;
reg [5:0] func;
reg [1:0] ALUop;
// Outputs
wire zero;
wire [31:0] ... | 6.795848 |
module ALU_tb;
`include "../src/utils/Assert.vh"
`include "../src/Parameters.vh"
// Input stimulus
reg [XLEN - 1 : 0] A;
reg [XLEN - 1 : 0] B;
reg [2 : 0] control;
// Output
wire [XLEN - 1 : 0] result;
ALU DUT (
.result(result),
.A(A),
.B(B),
.control(control)
);
initial... | 6.772917 |
module: alu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`include "mips_16_defs.v"
module alu_tb_0_v;
// Inputs
reg [15:0] a;
reg [15:0] b;
reg [2:0] cmd;
// ... | 7.023594 |
module alu_test2 (
a,
b,
Cin,
sel,
out,
cOut,
status
);
input [63:0] a, b;
input Cin;
input [4:0] sel;
output [63:0] out;
output cOut;
//-Flags declaration - 4 bits, either true or false
output [3:0] status;
wire [63:0] orOut, andOut, xorOut, adderOut, shiftRight, shiftLeft, ... | 7.455626 |
module mux_A_2_to_1 (
A,
notA,
fsel,
R
);
input [63:0] A, notA;
input fsel;
output reg [63:0] R;
always @(A or notA or fsel) begin
case (fsel)
0: R = A;
1: R = notA;
default: R = 1'bx;
endcase
end
endmodule
| 6.80285 |
module orOp (
A,
B,
result
);
input [63:0] A, B;
output [63:0] result;
assign result = A | B;
//Flags
//Checks if the reuslt is = to 0 that is 64 bit value in binary.
endmodule
| 7.053823 |
module xorOp (
A,
B,
result
);
input [63:0] A, B;
output [63:0] result;
assign result = A ^ B;
//Flags
endmodule
| 6.847488 |
module adder (
addA,
addB,
nic,
sum,
cout
); //by Muhammad
input [63:0] addA, addB;
input nic;
output [63:0] sum;
output cout;
assign {cout, sum} = addA + addB + nic;
endmodule
| 7.4694 |
module full_adder (A, B, Cin, S, Cout);
//input A, B, Cin;
//output S, Cout;
//assign S = A^(B&Cin);
//assign Cout = (A^B)&Cin | A&B;
//endmodule
| 6.882132 |
module Adder(A, B, Cin, S, Cout);
// input [63:0] A, B;
// input Cin;
// output [63:0] S;
// output Cout;
// wire [64:0]carry;
// assign carry[0] = Cin;
// assign Cout = carry[64];
// // use generate block to instantiate 64 full adders
// genvar i;
// generate
// for (i=0; i<64; i=i+1) b... | 7.504432 |
module shift_right (
A_or_B,
shift_amount,
right_shift
);
input [63:0] A_or_B;
input [5:0] shift_amount;
output [63:0] right_shift;
assign right_shift = A_or_B >> shift_amount;
endmodule
| 6.706335 |
module alu_test2_testbench ();
reg [63:0] a, b;
reg Cin;
reg [4:0] sel;
wire [63:0] out;
wire cOut;
wire [3:0] status;
alu_test2 dut (
a,
b,
Cin,
sel,
out,
cOut,
status
);
initial begin
$monitor("sel=%d a=%d b=%d out=%d Cin=%d cOut=%d status=%d", sel, ... | 6.563699 |
module: ALU
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALU_TF;
// Inputs
reg [63:0] A;
reg [63:0] B;
reg [2:0] ALUOp;
// Outputs
wire [63:0] ALUResult;
// Instantiate ... | 6.795848 |
module ALU (
input [15:0] A,
input [15:0] B,
input [3:0] opcode_ALU,
input [1:0] alu_mode,
output reg [31:0] Alu_out,
output wire C,
Z,
EQ,
GT,
ZA,
ZB
);
reg [ 3:0] opcode_au;
reg [ 3:0] opcode_lu;
reg [ 3:0] opcode_shifter;
wire [16:0] out_au;
wire [31:0] out_pr... | 7.960621 |
module ALU_toplevel (
FS,
A,
B,
out,
zero_flag
);
parameter nBit = 16;
input [2:0] FS;
input [nBit-1:0] A, B;
output reg [nBit-1:0] out;
output reg zero_flag;
wire cout;
wire [nBit-1:0] arith_out;
wire op_sel;
assign op_sel = FS[2] | FS[1];
add_sub #(nBit) CE1 (
.A(A)... | 7.412095 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ALU_topmodule(output [W-1:0] R0,
output c_o... | 7.088073 |
module
// Module Name: /ad/eng/users/g/m/gmerritt/Desktop/tmp/Lab5/ALU_topmodule_tb.v
// Project Name: Lab5
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: ALU_topmodule
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional C... | 6.999332 |
module alu_unconditional_jal (
input clock,
input alu_unconditional_jal_enable,
input [31:0] immediate20_jtype,
output reg [31:0] rd_value,
input [31:0] pc,
output reg [31:0] next_pc
);
always @(posedge clock & alu_unconditional_jal_enable) begin
next_pc ... | 7.857872 |
module alu_unconditional_jalr (
input clock,
input alu_unconditional_jalr_enable,
input [31:0] immediate12_itype,
input [31:0] rs1_value,
input [ 2:0] funct3,
output reg [31:0] rd_value,
input [31:0] pc,
output reg [31:0] next_pc
);
always @... | 7.857872 |
module alu_unit #(
parameter WIDTH = 6
) (
input [WIDTH-1:0] a,
b,
input [3:0] func,
output reg [WIDTH-1:0] y,
output reg OF
);
always @(*) begin
case (func)
4'b0000: begin
y = a + b;
OF = (~a[WIDTH-1] & ~b[WIDTH-1] & y[WIDTH-1] | a[WIDTH-1] & b[WIDTH-1] & ~y[WIDTH-1... | 7.19177 |
module XOR (
x,
y,
z
);
input [63:0] x, y;
output [63:0] z;
genvar i;
generate
for (i = 0; i < 64; i = i + 1) begin
xor (z[i], x[i], y[i]);
end
endgenerate
endmodule
| 7.095291 |
module AND (
x,
y,
z
);
input [0:63] x, y;
output [0:63] z;
genvar i;
generate
for (i = 0; i < 64; i = i + 1) begin
and (z[i], x[i], y[i]);
end
endgenerate
endmodule
| 6.925853 |
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