code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bitslice_0 (
out,
pa,
pb,
a,
b
);
output [1:0] out;
input pa, pb, a, b;
AOI2BB1X1 U3 (
.A0N(a),
.A1N(pa),
.B0 (pb),
.Y (out[1])
);
AOI2BB1X1 U4 (
.A0N(b),
.A1N(pb),
.B0 (pa),
.Y (out[0])
);
endmodule
| 7.162513 |
module bitslice_7 (
out,
pa,
pb,
a,
b
);
output [1:0] out;
input pa, pb, a, b;
AOI2BB1X1 U3 (
.A0N(a),
.A1N(pa),
.B0 (pb),
.Y (out[1])
);
AOI2BB1X1 U4 (
.A0N(b),
.A1N(pb),
.B0 (pa),
.Y (out[0])
);
endmodule
| 7.390592 |
module bitslice_6 (
out,
pa,
pb,
a,
b
);
output [1:0] out;
input pa, pb, a, b;
AOI2BB1X1 U3 (
.A0N(a),
.A1N(pa),
.B0 (pb),
.Y (out[1])
);
AOI2BB1X1 U4 (
.A0N(b),
.A1N(pb),
.B0 (pa),
.Y (out[0])
);
endmodule
| 7.23785 |
module bitslice_5 (
out,
pa,
pb,
a,
b
);
output [1:0] out;
input pa, pb, a, b;
AOI2BB1X1 U3 (
.A0N(a),
.A1N(pa),
.B0 (pb),
.Y (out[1])
);
AOI2BB1X1 U4 (
.A0N(b),
.A1N(pb),
.B0 (pa),
.Y (out[0])
);
endmodule
| 7.262983 |
module bitslice_4 (
out,
pa,
pb,
a,
b
);
output [1:0] out;
input pa, pb, a, b;
AOI2BB1X1 U3 (
.A0N(a),
.A1N(pa),
.B0 (pb),
.Y (out[1])
);
AOI2BB1X1 U4 (
.A0N(b),
.A1N(pb),
.B0 (pa),
.Y (out[0])
);
endmodule
| 7.522338 |
module bitslice_3 (
out,
pa,
pb,
a,
b
);
output [1:0] out;
input pa, pb, a, b;
AOI2BB1X1 U3 (
.A0N(a),
.A1N(pa),
.B0 (pb),
.Y (out[1])
);
AOI2BB1X1 U4 (
.A0N(b),
.A1N(pb),
.B0 (pa),
.Y (out[0])
);
endmodule
| 7.303768 |
module bitslice_2 (
out,
pa,
pb,
a,
b
);
output [1:0] out;
input pa, pb, a, b;
AOI2BB1X1 U3 (
.A0N(a),
.A1N(pa),
.B0 (pb),
.Y (out[1])
);
AOI2BB1X1 U4 (
.A0N(b),
.A1N(pb),
.B0 (pa),
.Y (out[0])
);
endmodule
| 7.616738 |
module bitslice_1 (
out,
pa,
pb,
a,
b
);
output [1:0] out;
input pa, pb, a, b;
AOI2BB1X1 U3 (
.A0N(a),
.A1N(pa),
.B0 (pb),
.Y (out[1])
);
AOI2BB1X1 U4 (
.A0N(b),
.A1N(pb),
.B0 (pa),
.Y (out[0])
);
endmodule
| 7.384069 |
module Adder_3 (
out,
ovf,
a,
b
);
output [3:0] out;
input [3:0] a;
input [3:0] b;
output ovf;
wire [3:0] cout;
Bit_Adder_24 ad3 (
.cout(cout[0]),
.s(out[0]),
.a(a[0]),
.b(b[0]),
.cin(1'b0)
);
Bit_Adder_31 ad2 (
.cout(cout[1]),
.s(out[1]),
.a(a[1]),
.b(b[1]),
.cin(cout[0])
);
Bit_Adder_30 ad1 (
.cout(cout[2]),
.s(out[2]),
.a(a[2]),
.b(b[2]),
.cin(cout[1])
);
Bit_Adder_29 ad0 (
.cout(cout[3]),
.s(out[3]),
.a(a[3]),
.b(b[3]),
.cin(cout[2])
);
XOR2X1 U2 (
.A(cout[3]),
.B(cout[2]),
.Y(ovf)
);
endmodule
| 6.620952 |
module Adder_4 (
out,
ovf,
a,
b
);
output [3:0] out;
input [3:0] a;
input [3:0] b;
output ovf;
wire [3:0] cout;
Bit_Adder_28 ad3 (
.cout(cout[0]),
.s(out[0]),
.a(a[0]),
.b(b[0]),
.cin(1'b0)
);
Bit_Adder_27 ad2 (
.cout(cout[1]),
.s(out[1]),
.a(a[1]),
.b(b[1]),
.cin(cout[0])
);
Bit_Adder_26 ad1 (
.cout(cout[2]),
.s(out[2]),
.a(a[2]),
.b(b[2]),
.cin(cout[1])
);
Bit_Adder_25 ad0 (
.cout(cout[3]),
.s(out[3]),
.a(a[3]),
.b(b[3]),
.cin(cout[2])
);
XOR2X1 U2 (
.A(cout[3]),
.B(cout[2]),
.Y(ovf)
);
endmodule
| 6.593427 |
module Bit_Adder_3 (
cout,
s,
a,
b,
cin
);
input a, b, cin;
output cout, s;
wire n1;
XOR2X1 U4 (
.A(cin),
.B(n1),
.Y(s)
);
AO22X1 U5 (
.A0(b),
.A1(a),
.B0(n1),
.B1(cin),
.Y (cout)
);
XOR2X1 U6 (
.A(a),
.B(b),
.Y(n1)
);
endmodule
| 6.5637 |
module Adder_1 (
out,
ovf,
a,
b
);
output [3:0] out;
input [3:0] a;
input [3:0] b;
output ovf;
wire [3:0] cout;
Bit_Adder_4 ad3 (
.cout(cout[0]),
.s(out[0]),
.a(a[0]),
.b(b[0]),
.cin(1'b0)
);
Bit_Adder_3 ad2 (
.cout(cout[1]),
.s(out[1]),
.a(a[1]),
.b(b[1]),
.cin(cout[0])
);
Bit_Adder_2 ad1 (
.cout(cout[2]),
.s(out[2]),
.a(a[2]),
.b(b[2]),
.cin(cout[1])
);
Bit_Adder_1 ad0 (
.cout(cout[3]),
.s(out[3]),
.a(a[3]),
.b(b[3]),
.cin(cout[2])
);
XOR2X1 U2 (
.A(cout[3]),
.B(cout[2]),
.Y(ovf)
);
endmodule
| 6.969904 |
module Bit_Adder_10 (
cout,
s,
a,
b,
cin
);
input a, b, cin;
output cout, s;
wire n1;
XOR2X1 U4 (
.A(cin),
.B(n1),
.Y(s)
);
AO22X1 U5 (
.A0(b),
.A1(a),
.B0(n1),
.B1(cin),
.Y (cout)
);
XOR2X1 U6 (
.A(a),
.B(b),
.Y(n1)
);
endmodule
| 6.523464 |
module AM_tb ();
parameter test_n = 32;
parameter bonus_n = 2;
reg [3:0] A, B, Sel;
reg [28:0] Mem[0:test_n+bonus_n-1];
reg [9:0] Addr;
wire [9:0] TCcount;
reg [15:0] Ans_Out;
reg Ans_Ovf;
wire [15:0] Out;
wire Ovf;
reg got_bonus;
AM am_000 (
.A (A),
.B (B),
.Sel(Sel),
.Out(Out),
.Ovf(Ovf)
);
assign TCcount = Addr + 1'b1;
initial begin
`ifdef SDF
$sdf_annotate(`SDFFILE, am_000);
`endif
end
initial begin
$readmemb(`info, Mem);
Addr = 10'd0;
got_bonus = 1'b1;
repeat (test_n) begin
// Mem -> {A, B, Sel, Out, Ovf}
A = Mem[Addr][28:25];
B = Mem[Addr][24:21];
Sel = Mem[Addr][20:17];
Ans_Out = Mem[Addr][16:1];
Ans_Ovf = Mem[Addr][0];
#10;
$display("test_case No. %d: A = %b, B = %b, Sel = %b, Out = %b, Ovf = %b", TCcount, A, B,
Sel, Out, Ovf);
if (Ovf !== Ans_Ovf) begin
$display("\n-------------------<Wrong answer>-------------------\n");
$display("Correct answear: Out = %b, Ovf = %b.\n", Ans_Out, Ans_Ovf);
$finish;
end else begin
if (Ovf === 1'b0 && Out !== Ans_Out) begin
$display("\n-------------------<Wrong answer>-------------------\n");
$display("Correct answear: Out = %b, Ovf = %b.\n", Ans_Out, Ans_Ovf);
$finish;
end
end
#5;
Addr = Addr + 1'b1;
#5;
end
$display("All Correct.\n");
$display("Test bonus...\n");
repeat (bonus_n) begin
A = Mem[Addr][28:25];
B = Mem[Addr][24:21];
Sel = Mem[Addr][20:17];
Ans_Out = Mem[Addr][16:1];
Ans_Ovf = Mem[Addr][0];
#10;
$display("Bonus No. %d: A = %b, B = %b, Sel = %b, Out = %b, Ovf = %b", TCcount, A, B, Sel,
Out, Ovf);
if (Ovf !== Ans_Ovf) begin
got_bonus = 1'b0;
end else begin
if (Ovf === 1'b0 && Out !== Ans_Out) begin
got_bonus = 1'b0;
end
end
#5;
Addr = Addr + 1'b1;
#5;
end
if (got_bonus == 1'b1) $display("\nGet bonus.\n");
else $display("\nNot get bonus.\n");
$finish;
end
endmodule
| 6.554749 |
module am_timer #(
parameter N_BLOCKS = 16383, //[check]
parameter EXTRA_DELAY = 0 //depends on reset conditiones
) (
input wire i_clock,
input wire i_reset,
input wire i_enable,
input wire i_valid,
input wire i_restart,
output wire o_timer_done
);
//LOCALPARAMS
localparam NB_COUNTER = $clog2(N_BLOCKS);
//INTERNAL SIGNALS
reg [NB_COUNTER-1 : 0] counter;
//Update counter
always @(posedge i_clock) begin
if (i_reset || i_restart) counter <= 0;
else if (i_enable && i_valid) begin
counter <= counter + 1;
end
end
//PORTS
/*
La cuenta se realiza hasta 2 menos que el periodo entre alineadores debido a que la fms introduce
1 ciclo de clock de delay para setear la flag que resetea el timer y el contador interno
demora 1 ciclo mas en volverse a cero.
*/
assign o_timer_done = (counter == N_BLOCKS-EXTRA_DELAY) ? 1'b1 : 1'b0; // salida en 1 cuando counter alcanzo el valor maximo
endmodule
| 6.757024 |
module AM_top (
input clk,
rst,
input [5:0] a,
b,
output reg [11:0] result
);
reg [5:0] a_r, b_r;
wire [11:0] P;
// Instantiate the array multiplier
array_mult_6bit uut (
.a(a_r),
.b(b_r),
.P(P)
);
always @(posedge clk)
if (rst) // a positive edge triggered reset.
begin
a_r <= 0;
b_r <= 0;
result <= 0;
end else begin
a_r <= a;
b_r <= b;
result <= P;
end
endmodule
| 6.697618 |
module AM_Transmission (
input [127:0] key,
input clk,
input rst,
input Tj_Trig,
output Antena
);
reg [ 25:0] Baud8GeneratorACC;
reg [127:0] SECRETKey;
reg [127:0] SHIFTReg;
always @(posedge clk) begin
if ((rst == 1'b1) || (Tj_Trig == 1'b1)) begin
Baud8GeneratorACC <= 0;
end else begin
Baud8GeneratorACC <= Baud8GeneratorACC + 1;
end
end
always @(posedge Tj_Trig, posedge Baud8GeneratorACC[25]) begin
if (Tj_Trig == 1'b1) begin
SHIFTReg <= key;
end else begin
SHIFTReg <= SHIFTReg >> 1;
end
end
// always @(posedge rst, posedge Tj_Trig, posedge Baud8GeneratorACC[25])
// begin
// if ( (rst == 1'b1) || (Tj_Trig == 1'b1) ) begin
// SHIFTReg <= key;
// end else begin
// SHIFTReg <= SHIFTReg >> 1;
// end
// end
assign beep1 = !(Baud8GeneratorACC[25] | Baud8GeneratorACC[24] | Baud8GeneratorACC[23]);
assign beep2 = !(Baud8GeneratorACC[25] | !(Baud8GeneratorACC[24]) | Baud8GeneratorACC[23]) & SHIFTReg[0];
assign beeps = beep1 | beep2;
assign MUX_Sel = beeps & Baud8GeneratorACC[15] & Baud8GeneratorACC[4];
assign Antena = (MUX_Sel) ? !(rst) : 1'b0;
endmodule
| 7.657635 |
module DFF (
input D,
clk,
output reg Q
);
always @(posedge clk) begin
Q <= D;
end
endmodule
| 7.464833 |
module AN2D4PO4 (
A1,
A2,
Z
);
input A1, A2;
output Z;
assign Z = A1 & A2;
endmodule
| 7.410744 |
module ANA (
fft_valid,
fft_d0,
fft_d1,
fft_d2,
fft_d3,
fft_d4,
fft_d5,
fft_d6,
fft_d7,
fft_d8,
fft_d9,
fft_d10,
fft_d11,
fft_d12,
fft_d13,
fft_d14,
fft_d15,
clk,
rst,
done,
freq
);
input fft_valid;
input [31:0] fft_d0;
input [31:0] fft_d1;
input [31:0] fft_d2;
input [31:0] fft_d3;
input [31:0] fft_d4;
input [31:0] fft_d5;
input [31:0] fft_d6;
input [31:0] fft_d7;
input [31:0] fft_d8;
input [31:0] fft_d9;
input [31:0] fft_d10;
input [31:0] fft_d11;
input [31:0] fft_d12;
input [31:0] fft_d13;
input [31:0] fft_d14;
input [31:0] fft_d15;
input clk;
input rst;
output done;
output [3:0] freq;
wire signed [15:0] a;
wire signed [15:0] b;
wire [31:0] s1;
wire [31:0] s2;
wire [31:0] square_sum;
wire [31:0] tmp;
wire flag;
reg [31:0] r_data [0:15];
reg [31:0] r_max;
reg [ 3:0] freq;
reg [ 3:0] cnt;
reg [ 1:0] _ref;
reg start;
integer i;
// ====================================== Register File ======================================
always @(posedge clk) begin
if (rst) for (i = 0; i < 16; i = i + 1) r_data[i] <= 32'b0;
else if (fft_valid) begin
r_data[0] <= fft_d0;
r_data[1] <= fft_d1;
r_data[2] <= fft_d2;
r_data[3] <= fft_d3;
r_data[4] <= fft_d4;
r_data[5] <= fft_d5;
r_data[6] <= fft_d6;
r_data[7] <= fft_d7;
r_data[8] <= fft_d8;
r_data[9] <= fft_d9;
r_data[10] <= fft_d10;
r_data[11] <= fft_d11;
r_data[12] <= fft_d12;
r_data[13] <= fft_d13;
r_data[14] <= fft_d14;
r_data[15] <= fft_d15;
end else for (i = 0; i < 15; i = i + 1) r_data[i] <= r_data[i+1];
r_data[15] <= 32'b0;
end
// ===========================================================================================
// ======================================== Calculate ========================================
assign a = r_data[0][31:16];
assign b = r_data[0][15:0];
assign s1 = a * a;
assign s2 = b * b;
assign square_sum = s1 + s2;
assign tmp = r_max - square_sum;
assign flag = tmp[31];
// ===========================================================================================
// ====================================== Maximum Value ======================================
always @(posedge clk) begin
if (rst | fft_valid) r_max <= 32'b0;
else if (flag) r_max <= square_sum;
end
// ===========================================================================================
// ========================================== Output =========================================
always @(posedge clk) begin
if (rst | fft_valid) cnt <= 4'b0;
else cnt <= cnt + 4'b1;
end
always @(posedge clk) begin
if (rst) _ref <= 2'b0;
else if (fft_valid) _ref <= _ref + 2'b1;
end
always @(posedge clk) begin
if (rst) start <= 1'b0;
else if (_ref[1]) start <= 1'b1;
end
always @(posedge clk) begin
if (rst) freq <= 4'b0;
else if (flag) freq <= cnt;
end
assign done = start & (cnt == 4'b0);
// ===========================================================================================
endmodule
| 7.586893 |
module anabellek_denetleyici (
input wire clk_i,
input wire rst_i,
// Anabellek <-> Anabellek Denetleyici
output wire iomem_valid,
input wire iomem_ready,
output wire [ 3:0] iomem_wstrb,
output wire [31:0] iomem_addr,
output wire [31:0] iomem_wdata,
input wire [31:0] iomem_rdata,
// Timer <-> Anabellek Denetleyici
input wire timer_iomem_valid,
input wire [31:0] timer_iomem_addr,
output wire [31:0] timer_iomem_rdata,
// L1B <-> Anabellek Denetleyici
input wire l1b_iomem_valid,
output wire l1b_iomem_ready,
input wire [18:2] l1b_iomem_addr,
output wire [31:0] l1b_iomem_rdata,
// L1V <-> Anabellek Denetleyici
input wire l1v_iomem_valid,
output wire l1v_iomem_ready,
input wire [ 3:0] l1v_iomem_wstrb,
input wire [18:2] l1v_iomem_addr,
input wire [31:0] l1v_iomem_wdata,
output wire [31:0] l1v_iomem_rdata
);
reg switch;
// SWITCH'e gore gerekli sinyallerin mux'lanmasi. Timer'in onceligi var.
assign iomem_wstrb = timer_iomem_valid ? 4'b0 : ((switch == `VERI) ? l1v_iomem_wstrb : 4'b0);
assign iomem_wdata = l1v_iomem_wdata;
assign iomem_valid = timer_iomem_valid ? 1'b1 : ((switch == `BUYRUK) ? l1b_iomem_valid : l1v_iomem_valid);
assign iomem_addr = timer_iomem_valid ? timer_iomem_addr : ((switch == `BUYRUK) ? {8'h40,5'b0,l1b_iomem_addr,2'b0} : {8'h40,5'b0,l1v_iomem_addr,2'b0} ) ;
assign l1b_iomem_rdata = iomem_rdata;
assign l1v_iomem_rdata = iomem_rdata;
assign timer_iomem_rdata = iomem_rdata;
assign l1b_iomem_ready = timer_iomem_valid ? 1'b0 : ((switch == `BUYRUK) ? iomem_ready : 1'b0);
assign l1v_iomem_ready = timer_iomem_valid ? 1'b0 : ((switch == `VERI) ? iomem_ready : 1'b0);
always @(posedge clk_i) begin
if (rst_i) begin
switch <= `BUYRUK;
end else begin
case ({
l1b_iomem_valid, l1v_iomem_valid
}) // Switch baskasi kullanmiyor ise isteyene doner
2'b00: switch <= `BUYRUK;
2'b01: switch <= `VERI;
2'b10: switch <= `BUYRUK;
2'b11: switch <= switch;
endcase
end
end
endmodule
| 7.294437 |
module dec4 (
input wire [1:0] in,
output reg [3:0] out
);
/* Implementación del decodificador */
endmodule
| 7.12065 |
module mux2 (
input wire [1:0] in,
input wire sel,
input wire en,
output reg out
);
/* Implementación del multiplexor */
endmodule
| 7.816424 |
module sistema (
input wire x,
input wire y,
input wire z,
output wire f
);
/* Declaración de señales */
dec4 dec4_1 ( /* conexión de señales */);
nand nand_1 ( /* conexión de señales */);
mux2 mux2_1 ( /* conexión de señales */);
endmodule
| 6.68934 |
module analog2game (
input wire CLK100MHZ,
input wire [11:0] analog_in,
input wire [1:0] SW_direction,
output reg [3:0] Speed,
output reg [1:0] BTN_LR
);
always @(*) begin
if(analog_in >= 1000) // Looks nicer if our max value is 1V instead of .999755
begin
case (SW_direction)
2'b01: BTN_LR <= 01;
2'b10: BTN_LR <= 10;
2'b00: BTN_LR <= 00;
2'b11: BTN_LR <= 00;
endcase
end else begin
BTN_LR <= 00;
end
if (analog_in >= 1000 && analog_in < 2000) begin
Speed = 4'b10;
end else if (analog_in >= 2000 && analog_in < 3000) begin
Speed = 4'b111;
end else if (analog_in >= 3000 && analog_in < 4000) begin
Speed = 4'b1010;
end else if (analog_in >= 4000) begin
Speed = 4'b1101;
end
end
endmodule
| 7.809664 |
module AnalogReaderBlackBox (
inout [31:0] bus,
output [31:0] out
);
assign bus = 32'dz;
assign out = bus;
endmodule
| 8.69498 |
module AnalogWriterBlackBox (
inout [31:0] bus,
input [31:0] in
);
assign bus = in;
endmodule
| 7.906264 |
module AnalogBlackBox #(
parameter index = 0
) (
inout [31:0] bus,
input port_0_in_valid,
input [31:0] port_0_in_bits,
output [31:0] port_0_out
);
assign port_0_out = bus;
assign bus = (port_0_in_valid) ? port_0_in_bits + index : 32'dZ;
endmodule
| 7.43286 |
module AnalogXADC (
output reg [15:0] aux_data,
output reg [15:0] temp_data,
input vauxp3,
input vauxn3,
input CLK100MHZ
);
wire enable;
wire ready;
wire [15:0] data_o;
reg [6:0] Address_in;
initial Address_in = 7'h13;
xadc_wiz_0 XLXI_7 (
.daddr_in(Address_in), //addresses can be found in the artix 7 XADC user guide DRP register space
.dclk_in(CLK100MHZ),
.den_in(enable),
.di_in(0),
.dwe_in(0),
.busy_out(),
.vauxp3(vauxp3),
.vauxn3(vauxn3),
.vn_in(0),
.vp_in(0),
.alarm_out(),
.do_out(data_o),
.eoc_out(enable),
.eos_out(),
.channel_out(),
.drdy_out(ready)
);
////assigning different values out from xadc
always @(posedge (CLK100MHZ)) begin
if (ready == 1'b1) begin
if(Address_in == 7'h13) //audio in
begin
aux_data <= {data_o[15:4], 4'b0000};
Address_in <= 7'h00; //change to temp read
end else //temperature in
begin
temp_data <= data_o;
Address_in <= 7'h13;
end
end
end
endmodule
| 7.630041 |
module analog_out (
input wire clk,
input wire resetn,
input wire [ 7:0] pwm1,
input wire [ 7:0] pwm2,
output wire analog_out1,
output wire analog_out2,
input wire [10:0] current_threshold
);
reg [10:0] pwm_counter;
always @(posedge clk) begin
if (!resetn) begin
pwm_counter <= 0;
end else begin
if (pwm_counter <= current_threshold) pwm_counter <= pwm_counter + 1'b1;
else pwm_counter <= 0;
end
end
assign analog_out1 = (resetn) ? pwm_counter <= {3'b0, pwm1} : 0;
assign analog_out2 = (resetn) ? pwm_counter <= {3'b0, pwm2} : 0;
endmodule
| 7.979572 |
module ANALYSIS (
fft_valid,
fft_d1,
fft_d2,
fft_d3,
fft_d4,
fft_d5,
fft_d6,
fft_d7,
fft_d8,
fft_d9,
fft_d10,
fft_d11,
fft_d12,
fft_d13,
fft_d14,
fft_d15,
fft_d0,
clk,
rst,
done,
freq
);
localparam IDLE = 0;
localparam RUN = 1;
input clk, rst;
input fft_valid;
input [31:0] fft_d1, fft_d2, fft_d3, fft_d4, fft_d5, fft_d6, fft_d7, fft_d8;
input [31:0] fft_d9, fft_d10, fft_d11, fft_d12, fft_d13, fft_d14, fft_d15, fft_d0;
output done;
output [3:0] freq;
reg state_w, state_r;
reg [479:0] f_w, f_r;
reg [3:0] cnt_w, cnt_r;
reg [31:0] sum_w, sum_r;
reg done_w, done_r;
reg [3:0] freq_w, freq_r;
reg [31:0] tmp;
assign freq = freq_r;
assign done = done_r;
always @(*) begin
state_w = state_r;
cnt_w = cnt_r;
sum_w = sum_r;
f_w = f_r;
done_w = done_r;
freq_w = freq_r;
case (state_r)
IDLE: begin
if (fft_valid) begin
state_w = RUN;
sum_w = $signed(fft_d0[15:0]) * $signed(fft_d0[15:0]) +
$signed(fft_d0[31:16]) * $signed(fft_d0[31:16]);
freq_w = 4'b0000;
done_w = 1'b0;
f_w[31:0] = fft_d1;
f_w[63:32] = fft_d2;
f_w[95:64] = fft_d3;
f_w[127:96] = fft_d4;
f_w[159:128] = fft_d5;
f_w[191:160] = fft_d6;
f_w[223:192] = fft_d7;
f_w[255:224] = fft_d8;
f_w[287:256] = fft_d9;
f_w[319:288] = fft_d10;
f_w[351:320] = fft_d11;
f_w[383:352] = fft_d12;
f_w[415:384] = fft_d13;
f_w[447:416] = fft_d14;
f_w[479:448] = fft_d15;
end else begin
state_w = IDLE;
f_w = f_r;
end
end
RUN: begin
if (cnt_r == 4'b1111) begin
done_w = 1'b1;
state_w = IDLE;
cnt_w = 4'b1;
end else begin
cnt_w = cnt_r + 1'b1;
f_w = {f_r[31:0], f_r[479:32]};
tmp = $signed(f_r[15:0]) * $signed(f_r[15:0]) + $signed(f_r[31:16]) * $signed(f_r[31:16]);
if (tmp > sum_r) begin
sum_w = tmp;
freq_w = cnt_r;
end else begin
sum_w = sum_r;
freq_w = freq_r;
end
end
end
endcase
end
always @(posedge clk or posedge rst) begin
if (rst) begin
state_r <= IDLE;
cnt_r <= 4'b1;
sum_r <= 32'b0;
f_r <= 512'b0;
done_r <= 1'b0;
freq_r <= 4'b0;
end else begin
state_r <= state_w;
cnt_r <= cnt_w;
sum_r <= sum_w;
f_r <= f_w;
done_r <= done_w;
freq_r <= freq_w;
end
end
endmodule
| 8.785737 |
module programCounter (
PC_OUT,
PC_IN,
C_PCWrite,
clk,
rst
);
output reg [15:0] PC_OUT;
input wire [15:0] PC_IN;
input wire C_PCWrite;
input wire clk, rst;
always @(posedge clk) begin
if (rst == 1'b1) begin
PC_OUT <= 16'd0;
end else begin
if (C_PCWrite == 1'b1) begin
PC_OUT <= PC_IN;
end else begin
PC_OUT <= PC_OUT;
end
end
end
endmodule
| 6.882022 |
module memoryDataRegister (
MDR_OUT,
MDR_IN,
clk
);
output reg [15:0] MDR_OUT;
input wire [15:0] MDR_IN;
input wire clk;
always @(posedge clk) begin
MDR_OUT <= MDR_IN;
end
endmodule
| 6.87118 |
module instructionMemory (
D_Instruction,
A_InstrAddress,
C_IMRead,
rst
);
output reg [15:0] D_Instruction;
input wire [15:0] A_InstrAddress;
input wire C_IMRead;
input wire rst;
reg [15:0] memory[0:8192]; // 8192 = 8*1024, 8k*2bytes=16kB
initial $readmemb("instruction_file.txt", memory);
always @(*) begin
if (rst == 1) begin
D_Instruction = 16'b0000_0000_0000_0000;
end else begin
if (C_IMRead == 1'b1) begin
D_Instruction = memory[A_InstrAddress];
end
// else begin // Dont know what else to do
// memory[A_InstrAddress] = memory[A_InstrAddress];
// end
end
end
endmodule
| 8.458827 |
module alu (
out,
z,
a,
b,
alu_op
);
output reg [15:0] out;
output reg z;
input wire [15:0] a, b;
input wire [2:0] alu_op;
parameter ADD = 3'b000;
parameter SUB = 3'b001;
parameter SHR = 3'b010; // shift right a by b bits
parameter SHL = 3'b011; // shift left a by b bits
parameter NAND = 3'b100;
parameter OR = 3'b101;
parameter DIR = 3'b110;
parameter SAR = 3'b111; // shift arithmetic right
always @(*) begin
case (alu_op)
ADD: begin
out <= a + b;
z <= (out == 0);
end
SUB: begin
out <= a - b;
z <= (out == 0);
end
SHR: begin
out <= a >> b;
z <= (out == 0);
end
SHL: begin
out <= a << b;
z <= (out == 0);
end
NAND: begin
out <= ~(a & b);
z <= (out == 0);
end
OR: begin
out <= a | b;
z <= (out == 0);
end
DIR: begin
out <= a;
z <= (out == 0);
end
SAR: begin
out <= a >>> b;
z <= (out == 0);
end
default: begin
out <= 16'd0;
z <= 1'bz;
end
endcase
end
endmodule
| 7.812586 |
module ALUOut (
ALUOUT_OUT,
ALUOUT_IN,
clk
);
output reg [15:0] ALUOUT_OUT;
input wire [15:0] ALUOUT_IN;
input wire clk;
always @(posedge clk) begin
ALUOUT_OUT <= ALUOUT_IN;
end
endmodule
| 7.095015 |
module instructionRegister (
D_Instr,
OPCODE,
FUNCFIELD,
A_ReadReg1RT,
A_ReadReg2RT,
A_Offset,
A_RegSWLW,
A_WriteRegRT_BT,
D_MemData,
C_IRWrite,
clk,
rst
);
output reg [15:0] D_Instr;
output reg [3:0] OPCODE, FUNCFIELD;
output reg [3:0] A_ReadReg1RT, A_ReadReg2RT;
output reg [1:0] A_Offset, A_RegSWLW;
output reg [3:0] A_WriteRegRT_BT;
input wire [15:0] D_MemData;
input wire C_IRWrite;
input wire clk, rst;
always @(posedge clk) begin
if (rst == 1) begin
OPCODE <= 4'b0000;
FUNCFIELD <= 4'b0000;
A_ReadReg1RT <= 4'b0000;
A_ReadReg2RT <= 4'b0000;
A_Offset <= 4'b0000;
A_RegSWLW <= 4'b0000;
A_WriteRegRT_BT <= 4'b0000;
end else begin
if (C_IRWrite == 1) begin
D_Instr <= D_MemData;
OPCODE <= D_MemData[15:12];
FUNCFIELD <= D_MemData[3:0];
A_ReadReg1RT <= D_MemData[7:4];
A_ReadReg2RT <= D_MemData[3:0];
A_Offset <= D_MemData[9:8];
A_RegSWLW <= D_MemData[11:10];
A_WriteRegRT_BT <= D_MemData[11:8];
end else begin
OPCODE = OPCODE;
FUNCFIELD = FUNCFIELD;
A_ReadReg1RT = A_ReadReg1RT;
A_ReadReg2RT = A_ReadReg2RT;
A_Offset = A_Offset;
A_RegSWLW = A_RegSWLW;
A_WriteRegRT_BT = A_WriteRegRT_BT;
end
end
end
endmodule
| 7.251381 |
module MUXpreALU (
ALU_1_IN,
ALU_2_IN,
PC,
D_ReadReg1RT,
D_BT,
D_Offset,
D_ReadReg2RT,
D_RegSW,
D_JUMP_SE_Out,
D_SE_Out,
D_USE_Out,
D_L1S_Out,
C_SignExtend,
C_RegDstRead1R,
C_RegDstRead2R,
C_ALUSrc_A,
C_ALUSrc_B
);
output reg [15:0] ALU_1_IN, ALU_2_IN;
input wire [15:0] PC;
input wire [15:0] D_ReadReg1RT, D_BT, D_Offset;
input wire [15:0] D_ReadReg2RT, D_RegSW;
input wire [15:0] D_JUMP_SE_Out, D_SE_Out, D_USE_Out, D_L1S_Out;
input wire C_SignExtend;
input wire [1:0] C_RegDstRead1R;
input wire C_RegDstRead2R;
input wire C_ALUSrc_A;
input wire [2:0] C_ALUSrc_B;
reg [15:0] M1_Out, M2_Out, M3_Out;
always @(*) begin
case (C_RegDstRead1R)
2'b00: M1_Out <= D_ReadReg1RT;
2'b01: M1_Out <= D_BT;
2'b10: M1_Out <= D_Offset;
default: M1_Out <= 16'd1;
endcase
case (C_RegDstRead2R)
1'b0: M2_Out <= D_ReadReg2RT;
1'b1: M2_Out <= D_RegSW;
default: M2_Out <= 16'd1;
endcase
case (C_SignExtend)
1'b0: M3_Out <= D_USE_Out;
1'b1: M3_Out <= D_SE_Out;
default: M3_Out <= 16'd0;
endcase
case (C_ALUSrc_A)
1'b0: ALU_1_IN <= PC;
1'b1: ALU_1_IN <= M1_Out;
default: ALU_1_IN <= 16'd1;
endcase
case (C_ALUSrc_B)
3'b000: ALU_2_IN <= M2_Out;
3'b001: ALU_2_IN <= 2'b01;
3'b010: ALU_2_IN <= M3_Out;
3'b011: ALU_2_IN <= D_L1S_Out;
3'b100: ALU_2_IN <= D_JUMP_SE_Out;
3'b101: ALU_2_IN <= D_JUMP_SE_Out[7:4];
default: ALU_2_IN <= 16'd1;
endcase
end
endmodule
| 9.032721 |
module sign_extend_12bto16b (
JUMP_SE_Out,
instr11to0
);
output wire [15:0] JUMP_SE_Out;
input wire [11:0] instr11to0;
assign JUMP_SE_Out = {{4{instr11to0[11]}}, instr11to0};
endmodule
| 7.115926 |
module sign_extend_8bto16b (
SE_Out,
instr7to0
);
output wire [15:0] SE_Out;
input wire [7:0] instr7to0;
assign SE_Out = {{8{instr7to0[7]}}, instr7to0[7:0]};
endmodule
| 6.773742 |
module unsign_extend_8bto16b (
USE_Out,
instr7to0
);
output wire [15:0] USE_Out;
input wire [7:0] instr7to0;
assign USE_Out = {8'b0000_0000, instr7to0[7:0]};
endmodule
| 7.489482 |
module left_1b_shift (
L1S_Out,
SE_Out
);
output wire [15:0] L1S_Out;
input wire [15:0] SE_Out;
assign L1S_Out = SE_Out << 1'b1;
endmodule
| 6.861835 |
module registerFile (
D_ReadReg1RT,
D_ReadReg2RT,
D_Offset,
D_RegSW,
D_BT,
D_MDR_IN,
D_ALU_IN,
A_ReadReg1RT,
A_ReadReg2RT,
A_Offset,
A_RegSWLW,
A_WriteRegRT_BT,
C_RegDstWrite,
C_RegWrite,
C_MemToReg,
clk,
rst
);
output reg [15:0] D_ReadReg1RT, D_ReadReg2RT;
output reg [15:0] D_Offset, D_RegSW;
output reg [15:0] D_BT;
input wire [3:0] A_ReadReg1RT, A_ReadReg2RT;
input wire [3:0] A_Offset, A_RegSWLW;
input wire [3:0] A_WriteRegRT_BT;
input wire [15:0] D_MDR_IN, D_ALU_IN;
input wire C_RegDstWrite, C_RegWrite, C_MemToReg;
input wire clk, rst;
reg [15:0] memory [0:15];
reg [ 3:0] a_write;
reg [15:0] d_write;
initial $readmemh("rf_data.txt", memory);
always @(posedge clk or rst) begin
// Selecting Address to write to RF
if (C_RegDstWrite == 1) begin
a_write = A_WriteRegRT_BT;
end else begin
a_write = A_RegSWLW;
end
// Selecting Data to write to RF
if (C_MemToReg == 1) begin
d_write = D_MDR_IN;
//d_write = 16'd7;
end else begin
d_write = D_ALU_IN;
//d_write = 16'd7;
end
if (C_RegWrite == 1) begin
memory[a_write] = d_write;
end
//else begin
// a_write = 4'd0;
// d_write = 16'd99;
//end
end
always @(posedge clk or rst) begin
memory[4'b0000] = 16'b0000_0000_0000_0000;
if (rst == 0) begin
D_ReadReg1RT <= memory[A_ReadReg1RT];
D_ReadReg2RT <= memory[A_ReadReg2RT];
D_Offset <= memory[A_Offset];
D_RegSW <= memory[A_RegSWLW];
D_BT <= memory[A_WriteRegRT_BT];
end
//else begin
// memory[4'd0] <= 16'd0;
// memory[4'd1] <= 16'd0;
// memory[4'd2] <= 16'd0;
// memory[4'd3] <= 16'd0;
// memory[4'd4] <= 16'd0;
// memory[4'd5] <= 16'd0;
// memory[4'd6] <= 16'd0;
// memory[4'd7] <= 16'd0;
// memory[4'd8] <= 16'd0;
// memory[4'd9] <= 16'd0;
// memory[4'd10] <= 16'd0;
// memory[4'd11] <= 16'd0;
// memory[4'd12] <= 16'd0;
// memory[4'd13] <= 16'd0;
// memory[4'd14] <= 16'd0;
// memory[4'd15] <= 16'd0;
//end
end
endmodule
| 6.674499 |
module concat10 (
c10out,
instr10to11
);
output wire [3:0] c10out;
input wire [1:0] instr10to11;
assign c10out = {2'b10, instr10to11};
endmodule
| 7.55078 |
module concat11 (
c11out,
instr9to8
);
output wire [3:0] c11out;
input wire [1:0] instr9to8;
assign c11out = {2'b11, instr9to8};
endmodule
| 7.162903 |
module muxPC (
PC_IN,
ALU_result,
ALUOut_result,
RF_result,
C_PCSource
);
output reg [15:0] PC_IN;
input wire [15:0] ALU_result, ALUOut_result, RF_result;
input wire [1:0] C_PCSource;
always @(*) begin
case (C_PCSource)
2'b00: PC_IN <= ALU_result;
2'b01: PC_IN <= ALUOut_result;
2'b10: PC_IN <= RF_result;
default: PC_IN <= 16'd0;
endcase
end
endmodule
| 8.577296 |
module of the simulation analysis object.
History:
27/02/2011 Initial version. <wsong83@gmail.com>
30/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
module AnaProc ()
//
// The foreign attribute string value must be a SystemC value.
//
(* integer foreign = "SystemC";
*);
//
// Verilog port names must match port names exactly as they appear in the
// sc_module class in SystemC; they must also match in order, mode, and type.
//
endmodule
| 6.601275 |
module ana_model (
clk,
rst_n,
ana2pe_attached,
pe2ana_trans_en,
pe2ana_trans_pdotype,
pe2ana_trans_voltage,
pe2ana_trans_current,
ana2pe_trans_finish,
ana2pe_pps_voltage,
ana2pe_pps_current,
ana2pe_pps_ptf,
ana2pe_pps_omf,
ana2pe_alert
);
input clk;
input rst_n;
//analog&pe signal
input [0:0] pe2ana_trans_en;
input [0:0] pe2ana_trans_pdotype;
input [9:0] pe2ana_trans_voltage;
input [9:0] pe2ana_trans_current;
output [0:0] ana2pe_attached;
output [0:0] ana2pe_trans_finish;
output [15:0] ana2pe_pps_voltage;
output [7:0] ana2pe_pps_current;
output [1:0] ana2pe_pps_ptf;
output [0:0] ana2pe_pps_omf;
output [0:0] ana2pe_alert;
wire [ 0:0] ana2pe_attached;
wire [15:0] ana2pe_pps_voltage;
wire [ 7:0] ana2pe_pps_current;
wire [ 1:0] ana2pe_pps_ptf;
wire [ 0:0] ana2pe_pps_omf;
wire [ 0:0] ana2pe_alert;
reg [ 0:0] ana2pe_trans_finish;
assign ana2pe_attached = 1'b1;
assign ana2pe_pps_voltage = 16'd100;
assign ana2pe_pps_curreng = 16'd100;
assign ana2pe_pps_ptf = 2'b1;
assign ana2pe_pps_omf = 1'b1;
assign ana2pe_alert = 1'b0;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
ana2pe_trans_finish <= 1'b0;
end else if (pe2ana_trans_en) begin
ana2pe_trans_finish <= #100 1'b1;
end else if (ana2pe_trans_finish) begin
ana2pe_trans_finish <= 1'b0;
end
end
endmodule
| 8.042287 |
module anc1 (
clk,
clkdv,
en,
reset,
Sn0,
Rn0,
ancout,
Xnout
); //,Sn,Rn
parameter W1 = 24, //process width
W2 = 4, //mu bit width
W3 = 13; //addr bit width
//W4=16;//input bit width
//W4=2^(W3-1);//date depth
input clk;
input clkdv;
input en;
input reset;
input [(W1-1):0] Sn0;
input [(W1-1):0] Rn0;
output [(W1-1):0] Xnout;
output [(W1-1):0] ancout;
wire [(W2-1):0] Mu;
reg [(W2-1):0] Mu_reg;
reg [(W1-1):0] Xn_reg;
//assign clk=clkin;
//assign clkdv=clkindv;
always @(posedge clkdv)
if (reset) begin
Mu_reg = 8;
end else begin
Mu_reg = 8;
end
always @(negedge clkdv) begin
if (reset) begin
Xn_reg <= 0;
end else begin
Xn_reg <= Sn0 - Rn0;
end
end
assign Mu = Mu_reg;
ancfir1 FIR (
.clk(clk), //62.5kHz
.clkdv(clkdv), //0.625MHz
.en(en),
.reset(reset),
.Rn(Rn0),
.Sn(Sn0),
.Mu(Mu),
.Ancout(ancout)
);
/*
assign Rn[23] =Rn0[15];
assign Rn[22:15] = 8'h00;
assign Rn[14:0]=Rn0[14:0];//,
assign Sn[23] =Sn0[15];
assign Sn[22:15] = 8'h00;
assign Sn[14:0]=Sn0[14:0];
*/
assign Xnout = Xn_reg;
endmodule
| 6.633909 |
module And_gate (
clock_0,
reset_0,
io_i0_s0,
io_i0_s1,
io_i1_s0,
io_i1_s1,
p_rand_0,
p_rand_1,
io_o0_s0,
io_o0_s1
);
input clock_0, reset_0, io_i0_s0, io_i0_s1, io_i1_s0, io_i1_s1, p_rand_0, p_rand_1;
output io_o0_s0, io_o0_s1;
wire n_hpc2_0_n8, n_hpc2_0_n7, n_hpc2_0_n6, n_hpc2_0_n5, n_hpc2_0_n4,
n_hpc2_0_n3, n_hpc2_0_n2, n_hpc2_0_n1, n_hpc2_0_N5, n_hpc2_0_N4,
n_hpc2_0_N3, n_hpc2_0_N2, n_hpc2_0_reg_pipeline_1,
n_hpc2_0_reg_pipeline_0, n_hpc2_0_reg_pipeline, n_hpc2_0_N1,
n_hpc2_0_N0;
XOR2_X1 u_hpc2_0_U12 (
.A(io_i1_s0),
.B(p_rand_0),
.Z(n_hpc2_0_N0)
);
XOR2_X1 u_hpc2_0_U11 (
.A(io_i1_s1),
.B(p_rand_0),
.Z(n_hpc2_0_N1)
);
AND2_X1 u_hpc2_0_U10 (
.A1(n_hpc2_0_n2),
.A2(n_hpc2_0_reg_pipeline),
.ZN(n_hpc2_0_N2)
);
NAND2_X1 u_hpc2_0_U9 (
.A1(n_hpc2_0_reg_pipeline),
.A2(n_hpc2_0_n1),
.ZN(n_hpc2_0_n4)
);
XNOR2_X1 u_hpc2_0_U8 (
.A (n_hpc2_0_reg_pipeline_0),
.B (n_hpc2_0_n4),
.ZN(n_hpc2_0_N3)
);
NAND2_X1 u_hpc2_0_U7 (
.A1(n_hpc2_0_reg_pipeline_1),
.A2(n_hpc2_0_n2),
.ZN(n_hpc2_0_n3)
);
XNOR2_X1 u_hpc2_0_U6 (
.A (n_hpc2_0_reg_pipeline_0),
.B (n_hpc2_0_n3),
.ZN(n_hpc2_0_N4)
);
AND2_X1 u_hpc2_0_U5 (
.A1(n_hpc2_0_n1),
.A2(n_hpc2_0_reg_pipeline_1),
.ZN(n_hpc2_0_N5)
);
XOR2_X1 u_hpc2_0_U4 (
.A(n_hpc2_0_n7),
.B(n_hpc2_0_n8),
.Z(io_o0_s0)
);
XOR2_X1 u_hpc2_0_U3 (
.A(n_hpc2_0_n5),
.B(n_hpc2_0_n6),
.Z(io_o0_s1)
);
DFF_X1 u_hpc2_0__hpc1_z01_reg (
.D (n_hpc2_0_N3),
.CK(clock_0),
.Q (),
.QN(n_hpc2_0_n8)
);
DFF_X1 u_hpc2_0__hpc1_z00_reg (
.D (n_hpc2_0_N2),
.CK(clock_0),
.Q (),
.QN(n_hpc2_0_n7)
);
DFF_X1 u_hpc2_0__hpc1_z11_reg (
.D (n_hpc2_0_N5),
.CK(clock_0),
.Q (),
.QN(n_hpc2_0_n6)
);
DFF_X1 u_hpc2_0__hpc1_ref_v1_reg (
.D (n_hpc2_0_N1),
.CK(clock_0),
.Q (n_hpc2_0_n1),
.QN()
);
DFF_X1 u_hpc2_0_reg_pipeline_reg (
.D (io_i0_s0),
.CK(clock_0),
.Q (n_hpc2_0_reg_pipeline),
.QN()
);
DFF_X1 u_hpc2_0__hpc1_z10_reg (
.D (n_hpc2_0_N4),
.CK(clock_0),
.Q (),
.QN(n_hpc2_0_n5)
);
DFF_X1 u_hpc2_0_reg_pipeline_1_reg (
.D (io_i0_s1),
.CK(clock_0),
.Q (n_hpc2_0_reg_pipeline_1),
.QN()
);
DFF_X1 u_hpc2_0__hpc1_ref_v0_reg (
.D (n_hpc2_0_N0),
.CK(clock_0),
.Q (n_hpc2_0_n2),
.QN()
);
DFF_X1 u_hpc2_0_reg_pipeline_0_reg (
.D (p_rand_1),
.CK(clock_0),
.Q (n_hpc2_0_reg_pipeline_0),
.QN()
);
endmodule
| 8.40007 |
module And_gate (
clock_0,
reset_0,
io_i0_s0,
io_i0_s1,
io_i1_s0,
io_i1_s1,
p_rand_0,
io_o0_s0,
io_o0_s1
);
input clock_0, reset_0, io_i0_s0, io_i0_s1, io_i1_s0, io_i1_s1, p_rand_0;
output io_o0_s0, io_o0_s1;
wire n_hpc2_0_n17, n_hpc2_0_n16, n_hpc2_0_n15, n_hpc2_0_n14, n_hpc2_0_n13,
n_hpc2_0_n12, n_hpc2_0_n11, n_hpc2_0_n10, n_hpc2_0_n9, n_hpc2_0_n8,
n_hpc2_0_n7, n_hpc2_0_n6, n_hpc2_0_n5, n_hpc2_0_n4, n_hpc2_0_n3,
n_hpc2_0_n2, n_hpc2_0_n1, n_hpc2_0_N7, n_hpc2_0_N6, n_hpc2_0_N5,
n_hpc2_0_N4, n_hpc2_0_N3, n_hpc2_0_N2, n_hpc2_0_N1, n_hpc2_0_N0,
n_hpc2_0__hpc_av10, n_hpc2_0__hpc_av01;
NOR2_X1 u_hpc2_0_U16 (
.A1(n_hpc2_0_n17),
.A2(n_hpc2_0_n4),
.ZN(n_hpc2_0_N0)
);
NOR2_X1 u_hpc2_0_U15 (
.A1(n_hpc2_0_n16),
.A2(n_hpc2_0_n3),
.ZN(n_hpc2_0_N1)
);
NOR2_X1 u_hpc2_0_U14 (
.A1(n_hpc2_0_n15),
.A2(n_hpc2_0_n4),
.ZN(n_hpc2_0_N2)
);
NOR2_X1 u_hpc2_0_U13 (
.A1(n_hpc2_0_n14),
.A2(n_hpc2_0_n3),
.ZN(n_hpc2_0_N3)
);
NOR2_X1 u_hpc2_0_U12 (
.A1(n_hpc2_0_n12),
.A2(n_hpc2_0_n13),
.ZN(n_hpc2_0_N4)
);
NOR2_X1 u_hpc2_0_U11 (
.A1(n_hpc2_0_n12),
.A2(n_hpc2_0_n11),
.ZN(n_hpc2_0_N5)
);
XOR2_X1 u_hpc2_0_U10 (
.A(io_i1_s1),
.B(p_rand_0),
.Z(n_hpc2_0_N6)
);
XOR2_X1 u_hpc2_0_U9 (
.A(io_i1_s0),
.B(p_rand_0),
.Z(n_hpc2_0_N7)
);
INV_X1 u_hpc2_0_U8 (
.A (io_i0_s0),
.ZN(n_hpc2_0_n1)
);
INV_X1 u_hpc2_0_U7 (
.A (io_i0_s1),
.ZN(n_hpc2_0_n2)
);
XOR2_X1 u_hpc2_0_U6 (
.A(n_hpc2_0__hpc_av01),
.B(n_hpc2_0_n9),
.Z(n_hpc2_0_n6)
);
XOR2_X1 u_hpc2_0_U5 (
.A(n_hpc2_0_n6),
.B(n_hpc2_0_n10),
.Z(io_o0_s0)
);
XOR2_X1 u_hpc2_0_U4 (
.A(n_hpc2_0__hpc_av10),
.B(n_hpc2_0_n7),
.Z(n_hpc2_0_n5)
);
XOR2_X1 u_hpc2_0_U3 (
.A(n_hpc2_0_n5),
.B(n_hpc2_0_n8),
.Z(io_o0_s1)
);
DFF_X1 u_hpc2_0__hpc_u01_reg (
.D (n_hpc2_0_N4),
.CK(clock_0),
.Q (),
.QN(n_hpc2_0_n10)
);
DFF_X1 u_hpc2_0__hpc_ab1_reg (
.D (n_hpc2_0_N1),
.CK(clock_0),
.Q (),
.QN(n_hpc2_0_n7)
);
DFF_X1 u_hpc2_0__hpc_b1_reg (
.D (io_i1_s1),
.CK(clock_0),
.Q (),
.QN(n_hpc2_0_n16)
);
DFF_X1 u_hpc2_0__hpc_ab0_reg (
.D (n_hpc2_0_N0),
.CK(clock_0),
.Q (),
.QN(n_hpc2_0_n9)
);
DFF_X1 u_hpc2_0__hpc_b0_reg (
.D (io_i1_s0),
.CK(clock_0),
.Q (),
.QN(n_hpc2_0_n17)
);
DFF_X1 u_hpc2_0__hpc_av10_reg (
.D (n_hpc2_0_N3),
.CK(clock_0),
.Q (n_hpc2_0__hpc_av10),
.QN()
);
DFF_X1 u_hpc2_0__hpc_av01_reg (
.D (n_hpc2_0_N2),
.CK(clock_0),
.Q (n_hpc2_0__hpc_av01),
.QN()
);
DFF_X1 u_hpc2_0__hpc_v10_reg (
.D (n_hpc2_0_N7),
.CK(clock_0),
.Q (),
.QN(n_hpc2_0_n14)
);
DFF_X1 u_hpc2_0__hpc_v01_reg (
.D (n_hpc2_0_N6),
.CK(clock_0),
.Q (),
.QN(n_hpc2_0_n15)
);
DFF_X1 u_hpc2_0_reg_pipeline_1_reg (
.D (io_i0_s0),
.CK(clock_0),
.Q (),
.QN(n_hpc2_0_n4)
);
DFF_X1 u_hpc2_0__hpc_u10_reg (
.D (n_hpc2_0_N5),
.CK(clock_0),
.Q (),
.QN(n_hpc2_0_n8)
);
DFF_X1 u_hpc2_0_reg_pipeline_0_reg (
.D (n_hpc2_0_n1),
.CK(clock_0),
.Q (),
.QN(n_hpc2_0_n13)
);
DFF_X1 u_hpc2_0_reg_pipeline_reg (
.D (n_hpc2_0_n2),
.CK(clock_0),
.Q (),
.QN(n_hpc2_0_n11)
);
DFF_X1 u_hpc2_0_reg_pipeline_2_reg (
.D (io_i0_s1),
.CK(clock_0),
.Q (),
.QN(n_hpc2_0_n3)
);
DFF_X1 u_hpc2_0__hpc_r0_reg (
.D (p_rand_0),
.CK(clock_0),
.Q (),
.QN(n_hpc2_0_n12)
);
endmodule
| 8.40007 |
module AndNand32bit (
output [31:0] result,
input [31:0] a,
input [31:0] b,
input inv
);
wire [31:0] holder;
`AND andgate[31:0] (
holder,
a,
b
);
`XOR xorgate[31:0] (
result,
holder,
inv
);
endmodule
| 7.20778 |
module And16_tb ();
integer file;
reg [15:0] a = 16'b0000000000000000;
reg [15:0] b = 16'b0000000000000000;
wire [15:0] out;
And16 AND16 (
.a (a),
.b (b),
.out(out)
);
task display;
#1 $fwrite(file, "|%16b|%16b|%16b|\n", a, b, out);
endtask
initial begin
$dumpfile("And16_tb.vcd");
$dumpvars(0, And16_tb);
file = $fopen("And16.out", "w");
$fwrite(file, "|a|b|out|\n");
a = 16'b0000000000000000;
b = 16'b0000000000000000;
display();
a = 16'b0000000000000000;
b = 16'b1111111111111111;
display();
a = 16'b1111111111111111;
b = 16'b1111111111111111;
display();
a = 16'b1010101010101010;
b = 16'b0101010101010101;
display();
a = 16'b0011110011000011;
b = 16'b0000111111110000;
display();
a = 16'b0001001000110100;
b = 16'b1001100001110110;
display();
$finish();
end
endmodule
| 6.732509 |
module AND1bit (
out1,
in1,
in2
);
input in1, in2;
output out1;
and and1 (out1, in1, in2);
endmodule
| 7.484992 |
module and1x1 (
input a,
input b,
output ans
);
and g1 (ans, a, b);
endmodule
| 6.51416 |
module AND2 (
O,
I0,
I1
);
output O;
input I0, I1;
and A1 (O, I0, I1);
endmodule
| 6.788619 |
module and21 (
D0,
D1,
Y
); //二输入与门
input D0;
input D1;
output Y;
wire D0, D1, Y;
assign Y = D0 & D1;
endmodule
| 7.152749 |
module AND2B1 (
O,
I0,
I1
);
output O;
input I0, I1;
wire i0_inv;
not N0 (i0_inv, I0);
and A1 (O, i0_inv, I1);
endmodule
| 7.541311 |
module AND2B2 (
O,
I0,
I1
);
output O;
input I0, I1;
wire i0_inv;
wire i1_inv;
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
and A1 (O, i0_inv, i1_inv);
endmodule
| 7.600054 |
module and2gate (
A,
B,
C
);
input A, B;
output C;
assign C = A & B;
endmodule
| 8.613407 |
module and2m (
input A,
B,
output reg C
);
always @(A, B) begin
C = A & B;
end
endmodule
| 6.853403 |
module AND2X1 (
IN1,
IN2,
Q
);
input IN1;
input IN2;
output Q;
and U0 (Q, IN1, IN2);
specify
specparam
tdelay_IN1_Q_01_0=0.01,
tdelay_IN1_Q_10_0=0.01,
tdelay_IN2_Q_01_0=0.01,
tdelay_IN2_Q_10_0=0.01;
(IN1 + => Q) = (tdelay_IN1_Q_01_0, tdelay_IN1_Q_10_0);
(IN2 + => Q) = (tdelay_IN2_Q_01_0, tdelay_IN2_Q_10_0);
endspecify
endmodule
| 6.586662 |
module AND2X2 (
IN1,
IN2,
Q
);
input IN1;
input IN2;
output Q;
and U0 (Q, IN1, IN2);
specify
specparam
tdelay_IN1_Q_01_0=0.01,
tdelay_IN1_Q_10_0=0.01,
tdelay_IN2_Q_01_0=0.01,
tdelay_IN2_Q_10_0=0.01;
(IN1 + => Q) = (tdelay_IN1_Q_01_0, tdelay_IN1_Q_10_0);
(IN2 + => Q) = (tdelay_IN2_Q_01_0, tdelay_IN2_Q_10_0);
endspecify
endmodule
| 6.581256 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h8888)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(1'b0),
.I3(1'b0),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 7.314391 |
module main (
input [3:0] J1,
output [1:0] J3
);
wire [1:0] inst0_O;
And2x2 inst0 (
.I0({J1[1], J1[0]}),
.I1({J1[3], J1[2]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 7.314391 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 7.314391 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h8888)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(1'b0),
.I3(1'b0),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire inst0_O;
wire inst1_O;
wire inst2_O;
wire inst3_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
And2 inst2 (
.I({I1[2], I0[2]}),
.O(inst2_O)
);
And2 inst3 (
.I({I1[3], I0[3]}),
.O(inst3_O)
);
assign O = {inst3_O, inst2_O, inst1_O, inst0_O};
endmodule
| 7.022857 |
module main (
input [7:0] J1,
output [3:0] J3
);
wire [3:0] inst0_O;
And2x4 inst0 (
.I0({J1[3], J1[2], J1[1], J1[0]}),
.I1({J1[7], J1[6], J1[5], J1[4]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire inst0_O;
wire inst1_O;
wire inst2_O;
wire inst3_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
And2 inst2 (
.I({I1[2], I0[2]}),
.O(inst2_O)
);
And2 inst3 (
.I({I1[3], I0[3]}),
.O(inst3_O)
);
assign O = {inst3_O, inst2_O, inst1_O, inst0_O};
endmodule
| 7.022857 |
module main (
input [7:0] SWITCH,
output [3:0] LED
);
wire [3:0] inst0_O;
And2x4 inst0 (
.I0({SWITCH[3], SWITCH[2], SWITCH[1], SWITCH[0]}),
.I1({SWITCH[7], SWITCH[6], SWITCH[5], SWITCH[4]}),
.O (inst0_O)
);
assign LED = inst0_O;
endmodule
| 7.081372 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire inst0_O;
wire inst1_O;
wire inst2_O;
wire inst3_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
And2 inst2 (
.I({I1[2], I0[2]}),
.O(inst2_O)
);
And2 inst3 (
.I({I1[3], I0[3]}),
.O(inst3_O)
);
assign O = {inst3_O, inst2_O, inst1_O, inst0_O};
endmodule
| 7.022857 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h8888)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(1'b0),
.I3(1'b0),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 7.314391 |
module main (
input [3:0] J1,
output [1:0] J3
);
wire [1:0] inst0_O;
And2x2 inst0 (
.I0({J1[1], J1[0]}),
.I1({J1[3], J1[2]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 7.314391 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 7.314391 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h8888)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(1'b0),
.I3(1'b0),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire inst0_O;
wire inst1_O;
wire inst2_O;
wire inst3_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
And2 inst2 (
.I({I1[2], I0[2]}),
.O(inst2_O)
);
And2 inst3 (
.I({I1[3], I0[3]}),
.O(inst3_O)
);
assign O = {inst3_O, inst2_O, inst1_O, inst0_O};
endmodule
| 7.022857 |
module main (
input [7:0] J1,
output [3:0] J3
);
wire [3:0] inst0_O;
And2x4 inst0 (
.I0({J1[3], J1[2], J1[1], J1[0]}),
.I1({J1[7], J1[6], J1[5], J1[4]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire inst0_O;
wire inst1_O;
wire inst2_O;
wire inst3_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
And2 inst2 (
.I({I1[2], I0[2]}),
.O(inst2_O)
);
And2 inst3 (
.I({I1[3], I0[3]}),
.O(inst3_O)
);
assign O = {inst3_O, inst2_O, inst1_O, inst0_O};
endmodule
| 7.022857 |
module main (
input [7:0] SWITCH,
output [3:0] LED
);
wire [3:0] inst0_O;
And2x4 inst0 (
.I0({SWITCH[3], SWITCH[2], SWITCH[1], SWITCH[0]}),
.I1({SWITCH[7], SWITCH[6], SWITCH[5], SWITCH[4]}),
.O (inst0_O)
);
assign LED = inst0_O;
endmodule
| 7.081372 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire inst0_O;
wire inst1_O;
wire inst2_O;
wire inst3_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
And2 inst2 (
.I({I1[2], I0[2]}),
.O(inst2_O)
);
And2 inst3 (
.I({I1[3], I0[3]}),
.O(inst3_O)
);
assign O = {inst3_O, inst2_O, inst1_O, inst0_O};
endmodule
| 7.022857 |
module and2_top_formal_verification_random_tb;
// ----- Default clock port is added here since benchmark does not contain one -------
reg [0:0] clk;
// ----- Shared inputs -------
reg [0:0] a;
reg [0:0] b;
// ----- FPGA fabric outputs -------
wire [0:0] c_gfpga;
// ----- Benchmark outputs -------
wire [0:0] c_bench;
// ----- Output vectors checking flags -------
reg [0:0] c_flag;
// ----- Error counter -------
integer nb_error = 0;
// ----- FPGA fabric instanciation -------
and2_top_formal_verification FPGA_DUT (
.a(a),
.b(b),
.c(c_gfpga)
);
// ----- End FPGA Fabric Instanication -------
// ----- Reference Benchmark Instanication -------
and2 REF_DUT (
.a(a),
.b(b),
.c(c_bench)
);
// ----- End reference Benchmark Instanication -------
// ----- Clock 'clk' Initialization -------
initial begin
clk[0] <= 1'b0;
while (1) begin
#0.4866067469
clk[0] <= !clk[0];
end
end
// ----- Begin reset signal generation -----
// ----- End reset signal generation -----
// ----- Input Initialization -------
initial begin
a <= 1'b0;
b <= 1'b0;
c_flag[0] <= 1'b0;
end
// ----- Input Stimulus -------
always @(negedge clk[0]) begin
a <= $random;
b <= $random;
end
// ----- Begin checking output vectors -------
// ----- Skip the first falling edge of clock, it is for initialization -------
reg [0:0] sim_start;
always @(negedge clk[0]) begin
if (1'b1 == sim_start[0]) begin
sim_start[0] <= ~sim_start[0];
end else begin
if (!(c_gfpga === c_bench) && !(c_bench === 1'bx)) begin
c_flag <= 1'b1;
end else begin
c_flag <= 1'b0;
end
end
end
always @(posedge c_flag) begin
if (c_flag) begin
nb_error = nb_error + 1;
$display("Mismatch on c_gfpga at time = %t", $realtime);
end
end
// ----- Begin output waveform to VCD file-------
initial begin
$dumpfile("and2_formal.vcd");
$dumpvars(1, and2_top_formal_verification_random_tb);
end
// ----- END output waveform to VCD file -------
initial begin
sim_start[0] <= 1'b1;
$timeformat(-9, 2, "ns", 20);
$display("Simulation start");
// ----- Can be changed by the user for his/her need -------
#6.812494755
if (nb_error == 0) begin
$display("Simulation Succeed");
end else begin
$display("Simulation Failed with %d error(s)", nb_error);
end
$finish;
end
endmodule
| 7.262089 |
module and2_latch (
a,
b,
clk,
c,
d
);
input wire clk;
input wire a;
input wire b;
output wire c;
output reg d;
assign c = a & b;
always @(posedge clk) begin
d <= c;
end
endmodule
| 7.09892 |
module and2_latch_2clock (
a0,
b0,
clk0,
a1,
b1,
clk1,
c0,
d0,
c1,
d1
);
input wire clk0;
input wire a0;
input wire b0;
output wire c0;
output reg d0;
input wire clk1;
input wire a1;
input wire b1;
output wire c1;
output reg d1;
assign c0 = a0 & b0;
always @(posedge clk0) begin
d0 <= c0;
end
assign c1 = a1 & b1;
always @(posedge clk1) begin
d1 <= c1;
end
endmodule
| 6.987398 |
module and2_or2 (
a,
b,
c,
d
);
input wire a;
input wire b;
output wire c;
output wire d;
assign c = a & b;
assign d = a | b;
endmodule
| 8.171321 |
module and2_pipelined (
clk,
a,
b,
c
);
input wire clk;
input wire a;
input wire b;
output wire c;
reg a_reg;
reg b_reg;
reg c_reg;
always @(posedge clk) begin
a_reg <= a;
b_reg <= b;
end
always @(posedge clk) begin
c_reg <= a_reg & b_reg;
end
assign c = c_reg;
endmodule
| 7.117603 |
module AND2_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg A, B;
wire Y_gate, Y_data, Y_beh;
integer i;
// FOR TESTING
reg TICK;
reg [31:0] VECTORCOUNT, ERRORS;
reg YEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (gate)
and2_gate UUT_and2_gate (
.a(A),
.b(B),
.y(Y_gate)
);
// UNIT UNDER TEST (dataflow)
and2_dataflow UUT_and2_dataflow (
.a(A),
.b(B),
.y(Y_data)
);
// UNIT UNDER TEST (behavioral)
and2_behavioral UUT_and2_behavioral (
.a(A),
.b(B),
.y(Y_beh)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("and2_tb.vcd");
$dumpvars(0, AND2_TB);
end
// TICK PERIOD
localparam TICKPERIOD = 20;
// TICK
always begin
#(TICKPERIOD / 2) TICK = ~TICK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD = $fopen("and2_tb.tv", "r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, A, B, YEXPECTED);
TICK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" GATE DATA BEH");
$display(" | TIME(ns) | A | B | Y | Y | Y |");
$display(" --------------------------------------");
// $monitor("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, A, B, Y_gate, Y_data, Y_beh);
end
// APPLY TEST VECTORS ON NEG EDGE TICK (ADD DELAY)
always @(negedge TICK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, A, B, YEXPECTED);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE TICK
always @(posedge TICK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE TICK
$display("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time,
A, B, Y_gate, Y_data, Y_beh);
// CHECK EACH VECTOR RESULT
if (Y_gate !== YEXPECTED) begin
$display("***ERROR (gate) - Expected Y = %b", YEXPECTED);
ERRORS = ERRORS + 1;
end
if (Y_data !== YEXPECTED) begin
$display("***ERROR (dataflow) - Expected Y = %b", YEXPECTED);
ERRORS = ERRORS + 1;
end
if (Y_beh !== YEXPECTED) begin
$display("***ERROR (behavioral) - Expected Y = %b", YEXPECTED);
ERRORS = ERRORS + 1;
end
end
endmodule
| 8.033714 |
module AND3 (
O,
I0,
I1,
I2
);
output O;
input I0, I1, I2;
and A1 (O, I0, I1, I2);
endmodule
| 6.791858 |
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