code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bitslice_0 (
out,
pa,
pb,
a,
b
);
output [1:0] out;
input pa, pb, a, b;
AOI2BB1X1 U3 (
.A0N(a),
.A1N(pa),
.B0 (pb),
.Y (out[1])
);
AOI2BB1X1 U4 (
.A0N(b),
.A1N(pb),
.B0 (pa),
.Y (out[0])
);
endmodule
| 7.162513 |
module bitslice_7 (
out,
pa,
pb,
a,
b
);
output [1:0] out;
input pa, pb, a, b;
AOI2BB1X1 U3 (
.A0N(a),
.A1N(pa),
.B0 (pb),
.Y (out[1])
);
AOI2BB1X1 U4 (
.A0N(b),
.A1N(pb),
.B0 (pa),
.Y (out[0])
);
endmodule
| 7.390592 |
module bitslice_6 (
out,
pa,
pb,
a,
b
);
output [1:0] out;
input pa, pb, a, b;
AOI2BB1X1 U3 (
.A0N(a),
.A1N(pa),
.B0 (pb),
.Y (out[1])
);
AOI2BB1X1 U4 (
.A0N(b),
.A1N(pb),
.B0 (pa),
.Y (out[0])
);
endmodule
| 7.23785 |
module bitslice_5 (
out,
pa,
pb,
a,
b
);
output [1:0] out;
input pa, pb, a, b;
AOI2BB1X1 U3 (
.A0N(a),
.A1N(pa),
.B0 (pb),
.Y (out[1])
);
AOI2BB1X1 U4 (
.A0N(b),
.A1N(pb),
.B0 (pa),
.Y (out[0])
);
endmodule
| 7.262983 |
module bitslice_4 (
out,
pa,
pb,
a,
b
);
output [1:0] out;
input pa, pb, a, b;
AOI2BB1X1 U3 (
.A0N(a),
.A1N(pa),
.B0 (pb),
.Y (out[1])
);
AOI2BB1X1 U4 (
.A0N(b),
.A1N(pb),
.B0 (pa),
.Y (out[0])
);
endmodule
| 7.522338 |
module bitslice_3 (
out,
pa,
pb,
a,
b
);
output [1:0] out;
input pa, pb, a, b;
AOI2BB1X1 U3 (
.A0N(a),
.A1N(pa),
.B0 (pb),
.Y (out[1])
);
AOI2BB1X1 U4 (
.A0N(b),
.A1N(pb),
.B0 (pa),
.Y (out[0])
);
endmodule
| 7.303768 |
module bitslice_2 (
out,
pa,
pb,
a,
b
);
output [1:0] out;
input pa, pb, a, b;
AOI2BB1X1 U3 (
.A0N(a),
.A1N(pa),
.B0 (pb),
.Y (out[1])
);
AOI2BB1X1 U4 (
.A0N(b),
.A1N(pb),
.B0 (pa),
.Y (out[0])
);
endmodule
| 7.616738 |
module bitslice_1 (
out,
pa,
pb,
a,
b
);
output [1:0] out;
input pa, pb, a, b;
AOI2BB1X1 U3 (
.A0N(a),
.A1N(pa),
.B0 (pb),
.Y (out[1])
);
AOI2BB1X1 U4 (
.A0N(b),
.A1N(pb),
.B0 (pa),
.Y (out[0])
);
endmodule
| 7.384069 |
module Adder_3 (
out,
ovf,
a,
b
);
output [3:0] out;
input [3:0] a;
input [3:0] b;
output ovf;
wire [3:0] cout;
Bit_Adder_24 ad3 (
.cout(cout[0]),
.s(out[0]),
.a(a[0]),
.b(b[0]),
.cin(1'b0)
);
Bit_Adder_31 ad2 (
.cout(cout[1]),
.s(out[1]),
... | 6.620952 |
module Adder_4 (
out,
ovf,
a,
b
);
output [3:0] out;
input [3:0] a;
input [3:0] b;
output ovf;
wire [3:0] cout;
Bit_Adder_28 ad3 (
.cout(cout[0]),
.s(out[0]),
.a(a[0]),
.b(b[0]),
.cin(1'b0)
);
Bit_Adder_27 ad2 (
.cout(cout[1]),
.s(out[1]),
... | 6.593427 |
module Bit_Adder_3 (
cout,
s,
a,
b,
cin
);
input a, b, cin;
output cout, s;
wire n1;
XOR2X1 U4 (
.A(cin),
.B(n1),
.Y(s)
);
AO22X1 U5 (
.A0(b),
.A1(a),
.B0(n1),
.B1(cin),
.Y (cout)
);
XOR2X1 U6 (
.A(a),
.B(b),
.Y(n1)
... | 6.5637 |
module Adder_1 (
out,
ovf,
a,
b
);
output [3:0] out;
input [3:0] a;
input [3:0] b;
output ovf;
wire [3:0] cout;
Bit_Adder_4 ad3 (
.cout(cout[0]),
.s(out[0]),
.a(a[0]),
.b(b[0]),
.cin(1'b0)
);
Bit_Adder_3 ad2 (
.cout(cout[1]),
.s(out[1]),
... | 6.969904 |
module Bit_Adder_10 (
cout,
s,
a,
b,
cin
);
input a, b, cin;
output cout, s;
wire n1;
XOR2X1 U4 (
.A(cin),
.B(n1),
.Y(s)
);
AO22X1 U5 (
.A0(b),
.A1(a),
.B0(n1),
.B1(cin),
.Y (cout)
);
XOR2X1 U6 (
.A(a),
.B(b),
.Y(n1)
... | 6.523464 |
module AM_tb ();
parameter test_n = 32;
parameter bonus_n = 2;
reg [3:0] A, B, Sel;
reg [28:0] Mem[0:test_n+bonus_n-1];
reg [9:0] Addr;
wire [9:0] TCcount;
reg [15:0] Ans_Out;
reg Ans_Ovf;
wire [15:0] Out;
wire Ovf;
reg got_bonus;
AM am_000 (
.A (A),
.B (B),
.Sel(Sel),
... | 6.554749 |
module am_timer #(
parameter N_BLOCKS = 16383, //[check]
parameter EXTRA_DELAY = 0 //depends on reset conditiones
) (
input wire i_clock,
input wire i_reset,
input wire i_enable,
input wire i_valid,
input wire i_restart,
output wire o_timer_done
);
//LOCALPARAMS
localparam NB_COU... | 6.757024 |
module AM_top (
input clk,
rst,
input [5:0] a,
b,
output reg [11:0] result
);
reg [5:0] a_r, b_r;
wire [11:0] P;
// Instantiate the array multiplier
array_mult_6bit uut (
.a(a_r),
.b(b_r),
.P(P)
);
always @(posedge clk)
if (rst) // a positive edge triggered rese... | 6.697618 |
module AM_Transmission (
input [127:0] key,
input clk,
input rst,
input Tj_Trig,
output Antena
);
reg [ 25:0] Baud8GeneratorACC;
reg [127:0] SECRETKey;
reg [127:0] SHIFTReg;
always @(posedge clk) begin
if ((rst == 1'b1) || (Tj_Trig == 1'b1)) begin
Baud8GeneratorACC <= 0;
end ... | 7.657635 |
module DFF (
input D,
clk,
output reg Q
);
always @(posedge clk) begin
Q <= D;
end
endmodule
| 7.464833 |
module AN2D4PO4 (
A1,
A2,
Z
);
input A1, A2;
output Z;
assign Z = A1 & A2;
endmodule
| 7.410744 |
module ANA (
fft_valid,
fft_d0,
fft_d1,
fft_d2,
fft_d3,
fft_d4,
fft_d5,
fft_d6,
fft_d7,
fft_d8,
fft_d9,
fft_d10,
fft_d11,
fft_d12,
fft_d13,
fft_d14,
fft_d15,
clk,
rst,
done,
freq
);
input fft_valid;
input [31:0] fft_d0;
input [31... | 7.586893 |
module anabellek_denetleyici (
input wire clk_i,
input wire rst_i,
// Anabellek <-> Anabellek Denetleyici
output wire iomem_valid,
input wire iomem_ready,
output wire [ 3:0] iomem_wstrb,
output wire [31:0] iomem_addr,
output wire [31:0] iomem_wdata,
inp... | 7.294437 |
module dec4 (
input wire [1:0] in,
output reg [3:0] out
);
/* Implementación del decodificador */
endmodule
| 7.12065 |
module mux2 (
input wire [1:0] in,
input wire sel,
input wire en,
output reg out
);
/* Implementación del multiplexor */
endmodule
| 7.816424 |
module sistema (
input wire x,
input wire y,
input wire z,
output wire f
);
/* Declaración de señales */
dec4 dec4_1 ( /* conexión de señales */);
nand nand_1 ( /* conexión de señales */);
mux2 mux2_1 ( /* conexión de señales */);
endmodule
| 6.68934 |
module analog2game (
input wire CLK100MHZ,
input wire [11:0] analog_in,
input wire [1:0] SW_direction,
output reg [3:0] Speed,
output reg [1:0] BTN_LR
);
always @(*) begin
if(analog_in >= 1000) // Looks nicer if our max value is 1V instead of .999755
begin
case (SW_dire... | 7.809664 |
module AnalogReaderBlackBox (
inout [31:0] bus,
output [31:0] out
);
assign bus = 32'dz;
assign out = bus;
endmodule
| 8.69498 |
module AnalogWriterBlackBox (
inout [31:0] bus,
input [31:0] in
);
assign bus = in;
endmodule
| 7.906264 |
module AnalogBlackBox #(
parameter index = 0
) (
inout [31:0] bus,
input port_0_in_valid,
input [31:0] port_0_in_bits,
output [31:0] port_0_out
);
assign port_0_out = bus;
assign bus = (port_0_in_valid) ? port_0_in_bits + index : 32'dZ;
endmodule
| 7.43286 |
module AnalogXADC (
output reg [15:0] aux_data,
output reg [15:0] temp_data,
input vauxp3,
input vauxn3,
input CLK100MHZ
);
wire enable;
wire ready;
wire [15:0] data_o;
reg [6:0] Address_in;
initial Address_in = 7'h13;
xadc_wiz_0 XLXI_7 (
.daddr_in(Address_in), //addresses c... | 7.630041 |
module analog_out (
input wire clk,
input wire resetn,
input wire [ 7:0] pwm1,
input wire [ 7:0] pwm2,
output wire analog_out1,
output wire analog_out2,
input wire [10:0] current_threshold
);
reg [10:0] pwm_counter;
always @(posedge clk) begin
if (!... | 7.979572 |
module ANALYSIS (
fft_valid,
fft_d1,
fft_d2,
fft_d3,
fft_d4,
fft_d5,
fft_d6,
fft_d7,
fft_d8,
fft_d9,
fft_d10,
fft_d11,
fft_d12,
fft_d13,
fft_d14,
fft_d15,
fft_d0,
clk,
rst,
done,
freq
);
localparam IDLE = 0;
localparam RUN = 1;
... | 8.785737 |
module programCounter (
PC_OUT,
PC_IN,
C_PCWrite,
clk,
rst
);
output reg [15:0] PC_OUT;
input wire [15:0] PC_IN;
input wire C_PCWrite;
input wire clk, rst;
always @(posedge clk) begin
if (rst == 1'b1) begin
PC_OUT <= 16'd0;
end else begin
if (C_PCWrite == 1'b1) begin
... | 6.882022 |
module memoryDataRegister (
MDR_OUT,
MDR_IN,
clk
);
output reg [15:0] MDR_OUT;
input wire [15:0] MDR_IN;
input wire clk;
always @(posedge clk) begin
MDR_OUT <= MDR_IN;
end
endmodule
| 6.87118 |
module instructionMemory (
D_Instruction,
A_InstrAddress,
C_IMRead,
rst
);
output reg [15:0] D_Instruction;
input wire [15:0] A_InstrAddress;
input wire C_IMRead;
input wire rst;
reg [15:0] memory[0:8192]; // 8192 = 8*1024, 8k*2bytes=16kB
initial $readmemb("instruction_file.txt", memory);... | 8.458827 |
module alu (
out,
z,
a,
b,
alu_op
);
output reg [15:0] out;
output reg z;
input wire [15:0] a, b;
input wire [2:0] alu_op;
parameter ADD = 3'b000;
parameter SUB = 3'b001;
parameter SHR = 3'b010; // shift right a by b bits
parameter SHL = 3'b011; // shift left a by b bits
para... | 7.812586 |
module ALUOut (
ALUOUT_OUT,
ALUOUT_IN,
clk
);
output reg [15:0] ALUOUT_OUT;
input wire [15:0] ALUOUT_IN;
input wire clk;
always @(posedge clk) begin
ALUOUT_OUT <= ALUOUT_IN;
end
endmodule
| 7.095015 |
module instructionRegister (
D_Instr,
OPCODE,
FUNCFIELD,
A_ReadReg1RT,
A_ReadReg2RT,
A_Offset,
A_RegSWLW,
A_WriteRegRT_BT,
D_MemData,
C_IRWrite,
clk,
rst
);
output reg [15:0] D_Instr;
output reg [3:0] OPCODE, FUNCFIELD;
output reg [3:0] A_ReadReg1RT, A_ReadReg2RT;
... | 7.251381 |
module MUXpreALU (
ALU_1_IN,
ALU_2_IN,
PC,
D_ReadReg1RT,
D_BT,
D_Offset,
D_ReadReg2RT,
D_RegSW,
D_JUMP_SE_Out,
D_SE_Out,
D_USE_Out,
D_L1S_Out,
C_SignExtend,
C_RegDstRead1R,
C_RegDstRead2R,
C_ALUSrc_A,
C_ALUSrc_B
);
output reg [15:0] ALU_1_IN, ALU_2_... | 9.032721 |
module sign_extend_12bto16b (
JUMP_SE_Out,
instr11to0
);
output wire [15:0] JUMP_SE_Out;
input wire [11:0] instr11to0;
assign JUMP_SE_Out = {{4{instr11to0[11]}}, instr11to0};
endmodule
| 7.115926 |
module sign_extend_8bto16b (
SE_Out,
instr7to0
);
output wire [15:0] SE_Out;
input wire [7:0] instr7to0;
assign SE_Out = {{8{instr7to0[7]}}, instr7to0[7:0]};
endmodule
| 6.773742 |
module unsign_extend_8bto16b (
USE_Out,
instr7to0
);
output wire [15:0] USE_Out;
input wire [7:0] instr7to0;
assign USE_Out = {8'b0000_0000, instr7to0[7:0]};
endmodule
| 7.489482 |
module left_1b_shift (
L1S_Out,
SE_Out
);
output wire [15:0] L1S_Out;
input wire [15:0] SE_Out;
assign L1S_Out = SE_Out << 1'b1;
endmodule
| 6.861835 |
module registerFile (
D_ReadReg1RT,
D_ReadReg2RT,
D_Offset,
D_RegSW,
D_BT,
D_MDR_IN,
D_ALU_IN,
A_ReadReg1RT,
A_ReadReg2RT,
A_Offset,
A_RegSWLW,
A_WriteRegRT_BT,
C_RegDstWrite,
C_RegWrite,
C_MemToReg,
clk,
rst
);
output reg [15:0] D_ReadReg1RT, D_Re... | 6.674499 |
module concat10 (
c10out,
instr10to11
);
output wire [3:0] c10out;
input wire [1:0] instr10to11;
assign c10out = {2'b10, instr10to11};
endmodule
| 7.55078 |
module concat11 (
c11out,
instr9to8
);
output wire [3:0] c11out;
input wire [1:0] instr9to8;
assign c11out = {2'b11, instr9to8};
endmodule
| 7.162903 |
module muxPC (
PC_IN,
ALU_result,
ALUOut_result,
RF_result,
C_PCSource
);
output reg [15:0] PC_IN;
input wire [15:0] ALU_result, ALUOut_result, RF_result;
input wire [1:0] C_PCSource;
always @(*) begin
case (C_PCSource)
2'b00: PC_IN <= ALU_result;
2'b01: PC_IN <= ALUOut... | 8.577296 |
module of the simulation analysis object.
History:
27/02/2011 Initial version. <wsong83@gmail.com>
30/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
module AnaProc ()
//
// The foreign attribute string value must be a SystemC value.
//
(* integer foreign = "SystemC";
*);
//
// ... | 6.601275 |
module ana_model (
clk,
rst_n,
ana2pe_attached,
pe2ana_trans_en,
pe2ana_trans_pdotype,
pe2ana_trans_voltage,
pe2ana_trans_current,
ana2pe_trans_finish,
ana2pe_pps_voltage,
ana2pe_pps_current,
ana2pe_pps_ptf,
ana2pe_pps_omf,
ana2pe_alert
);
input clk;
input rst_n;... | 8.042287 |
module anc1 (
clk,
clkdv,
en,
reset,
Sn0,
Rn0,
ancout,
Xnout
); //,Sn,Rn
parameter W1 = 24, //process width
W2 = 4, //mu bit width
W3 = 13; //addr bit width
//W4=16;//input bit width
//W4=2^(W3-1);//date depth
input clk;
input clkdv;
input en;
input reset;
input ... | 6.633909 |
module And_gate (
clock_0,
reset_0,
io_i0_s0,
io_i0_s1,
io_i1_s0,
io_i1_s1,
p_rand_0,
p_rand_1,
io_o0_s0,
io_o0_s1
);
input clock_0, reset_0, io_i0_s0, io_i0_s1, io_i1_s0, io_i1_s1, p_rand_0, p_rand_1;
output io_o0_s0, io_o0_s1;
wire n_hpc2_0_n8, n_hpc2_0_n7, n_hpc2_0_n6,... | 8.40007 |
module And_gate (
clock_0,
reset_0,
io_i0_s0,
io_i0_s1,
io_i1_s0,
io_i1_s1,
p_rand_0,
io_o0_s0,
io_o0_s1
);
input clock_0, reset_0, io_i0_s0, io_i0_s1, io_i1_s0, io_i1_s1, p_rand_0;
output io_o0_s0, io_o0_s1;
wire n_hpc2_0_n17, n_hpc2_0_n16, n_hpc2_0_n15, n_hpc2_0_n14, n_hpc2... | 8.40007 |
module AndNand32bit (
output [31:0] result,
input [31:0] a,
input [31:0] b,
input inv
);
wire [31:0] holder;
`AND andgate[31:0] (
holder,
a,
b
);
`XOR xorgate[31:0] (
result,
holder,
inv
);
endmodule
| 7.20778 |
module And16_tb ();
integer file;
reg [15:0] a = 16'b0000000000000000;
reg [15:0] b = 16'b0000000000000000;
wire [15:0] out;
And16 AND16 (
.a (a),
.b (b),
.out(out)
);
task display;
#1 $fwrite(file, "|%16b|%16b|%16b|\n", a, b, out);
endtask
initial begin
$dumpfile("And... | 6.732509 |
module AND1bit (
out1,
in1,
in2
);
input in1, in2;
output out1;
and and1 (out1, in1, in2);
endmodule
| 7.484992 |
module and1x1 (
input a,
input b,
output ans
);
and g1 (ans, a, b);
endmodule
| 6.51416 |
module AND2 (
O,
I0,
I1
);
output O;
input I0, I1;
and A1 (O, I0, I1);
endmodule
| 6.788619 |
module and21 (
D0,
D1,
Y
); //二输入与门
input D0;
input D1;
output Y;
wire D0, D1, Y;
assign Y = D0 & D1;
endmodule
| 7.152749 |
module AND2B1 (
O,
I0,
I1
);
output O;
input I0, I1;
wire i0_inv;
not N0 (i0_inv, I0);
and A1 (O, i0_inv, I1);
endmodule
| 7.541311 |
module AND2B2 (
O,
I0,
I1
);
output O;
input I0, I1;
wire i0_inv;
wire i1_inv;
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
and A1 (O, i0_inv, i1_inv);
endmodule
| 7.600054 |
module and2gate (
A,
B,
C
);
input A, B;
output C;
assign C = A & B;
endmodule
| 8.613407 |
module and2m (
input A,
B,
output reg C
);
always @(A, B) begin
C = A & B;
end
endmodule
| 6.853403 |
module AND2X1 (
IN1,
IN2,
Q
);
input IN1;
input IN2;
output Q;
and U0 (Q, IN1, IN2);
specify
specparam
tdelay_IN1_Q_01_0=0.01,
tdelay_IN1_Q_10_0=0.01,
tdelay_IN2_Q_01_0=0.01,
tdelay_IN2_Q_10_0=0.01;
(IN1 + => Q) = (tdelay_IN1_Q_01_0, tdelay_IN1_Q_10_0);
(IN2 + => Q) = (tdelay_IN2_Q_... | 6.586662 |
module AND2X2 (
IN1,
IN2,
Q
);
input IN1;
input IN2;
output Q;
and U0 (Q, IN1, IN2);
specify
specparam
tdelay_IN1_Q_01_0=0.01,
tdelay_IN1_Q_10_0=0.01,
tdelay_IN2_Q_01_0=0.01,
tdelay_IN2_Q_10_0=0.01;
(IN1 + => Q) = (tdelay_IN1_Q_01_0, tdelay_IN1_Q_10_0);
(IN2 + => Q) = (tdelay_IN2_Q_... | 6.581256 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h8888)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(1'b0),
.I3(1'b0),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 7.314391 |
module main (
input [3:0] J1,
output [1:0] J3
);
wire [1:0] inst0_O;
And2x2 inst0 (
.I0({J1[1], J1[0]}),
.I1({J1[3], J1[2]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 7.314391 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 7.314391 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h8888)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(1'b0),
.I3(1'b0),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire inst0_O;
wire inst1_O;
wire inst2_O;
wire inst3_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
And2 inst2 (
.I({I1[2], I0[2]}),
.... | 7.022857 |
module main (
input [7:0] J1,
output [3:0] J3
);
wire [3:0] inst0_O;
And2x4 inst0 (
.I0({J1[3], J1[2], J1[1], J1[0]}),
.I1({J1[7], J1[6], J1[5], J1[4]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire inst0_O;
wire inst1_O;
wire inst2_O;
wire inst3_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
And2 inst2 (
.I({I1[2], I0[2]}),
.... | 7.022857 |
module main (
input [7:0] SWITCH,
output [3:0] LED
);
wire [3:0] inst0_O;
And2x4 inst0 (
.I0({SWITCH[3], SWITCH[2], SWITCH[1], SWITCH[0]}),
.I1({SWITCH[7], SWITCH[6], SWITCH[5], SWITCH[4]}),
.O (inst0_O)
);
assign LED = inst0_O;
endmodule
| 7.081372 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire inst0_O;
wire inst1_O;
wire inst2_O;
wire inst3_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
And2 inst2 (
.I({I1[2], I0[2]}),
.... | 7.022857 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h8888)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(1'b0),
.I3(1'b0),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 7.314391 |
module main (
input [3:0] J1,
output [1:0] J3
);
wire [1:0] inst0_O;
And2x2 inst0 (
.I0({J1[1], J1[0]}),
.I1({J1[3], J1[2]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 7.314391 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire inst0_O;
wire inst1_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
assign O = {inst1_O, inst0_O};
endmodule
| 7.314391 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h8888)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(1'b0),
.I3(1'b0),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire inst0_O;
wire inst1_O;
wire inst2_O;
wire inst3_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
And2 inst2 (
.I({I1[2], I0[2]}),
.... | 7.022857 |
module main (
input [7:0] J1,
output [3:0] J3
);
wire [3:0] inst0_O;
And2x4 inst0 (
.I0({J1[3], J1[2], J1[1], J1[0]}),
.I1({J1[7], J1[6], J1[5], J1[4]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire inst0_O;
wire inst1_O;
wire inst2_O;
wire inst3_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
And2 inst2 (
.I({I1[2], I0[2]}),
.... | 7.022857 |
module main (
input [7:0] SWITCH,
output [3:0] LED
);
wire [3:0] inst0_O;
And2x4 inst0 (
.I0({SWITCH[3], SWITCH[2], SWITCH[1], SWITCH[0]}),
.I1({SWITCH[7], SWITCH[6], SWITCH[5], SWITCH[4]}),
.O (inst0_O)
);
assign LED = inst0_O;
endmodule
| 7.081372 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
module And2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire inst0_O;
wire inst1_O;
wire inst2_O;
wire inst3_O;
And2 inst0 (
.I({I1[0], I0[0]}),
.O(inst0_O)
);
And2 inst1 (
.I({I1[1], I0[1]}),
.O(inst1_O)
);
And2 inst2 (
.I({I1[2], I0[2]}),
.... | 7.022857 |
module and2_top_formal_verification_random_tb;
// ----- Default clock port is added here since benchmark does not contain one -------
reg [0:0] clk;
// ----- Shared inputs -------
reg [0:0] a;
reg [0:0] b;
// ----- FPGA fabric outputs -------
wire [0:0] c_gfpga;
// ----- Benchmark outputs -------
w... | 7.262089 |
module and2_latch (
a,
b,
clk,
c,
d
);
input wire clk;
input wire a;
input wire b;
output wire c;
output reg d;
assign c = a & b;
always @(posedge clk) begin
d <= c;
end
endmodule
| 7.09892 |
module and2_latch_2clock (
a0,
b0,
clk0,
a1,
b1,
clk1,
c0,
d0,
c1,
d1
);
input wire clk0;
input wire a0;
input wire b0;
output wire c0;
output reg d0;
input wire clk1;
input wire a1;
input wire b1;
output wire c1;
output reg d1;
assign c0 = a0 & b0;
... | 6.987398 |
module and2_or2 (
a,
b,
c,
d
);
input wire a;
input wire b;
output wire c;
output wire d;
assign c = a & b;
assign d = a | b;
endmodule
| 8.171321 |
module and2_pipelined (
clk,
a,
b,
c
);
input wire clk;
input wire a;
input wire b;
output wire c;
reg a_reg;
reg b_reg;
reg c_reg;
always @(posedge clk) begin
a_reg <= a;
b_reg <= b;
end
always @(posedge clk) begin
c_reg <= a_reg & b_reg;
end
assign c = c_reg;
... | 7.117603 |
module AND2_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg A, B;
wire Y_gate, Y_data, Y_beh;
integer i;
// FOR TESTING
reg TICK;
reg [31:0] VECTORCOUNT, ERRORS;
reg YEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (gate)
and2_gate UUT_and2_gate (
... | 8.033714 |
module AND3 (
O,
I0,
I1,
I2
);
output O;
input I0, I1, I2;
and A1 (O, I0, I1, I2);
endmodule
| 6.791858 |
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