code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module implements a and gate
that takes an array and AND them together
*/
module and_arr #(parameter Width = 5)
(input [Width - 1:0] in,
output out);
wire [Width - 1:0] temp;
assign temp[0] = in[0];
genvar i;
generate
for (i = 1; i < Width; i = i + 1) begin: g... | 6.904081 |
module AND_Array (
A,
B,
C
);
input [3:0] A, B;
output [3:0] C;
assign C[0] = A[0] & B[0];
assign C[1] = A[1] & B[1];
assign C[2] = A[2] & B[2];
assign C[3] = A[3] & B[3];
endmodule
| 7.206052 |
module and_block_assign (
input wire a,
b,
c,
output reg y
);
always @* begin
y = a;
y = y & b;
y = y & c;
end
endmodule
| 8.332254 |
module and_comb (
A,
B,
Y
);
input A, B;
output Y;
assign Y = A & B;
endmodule
| 7.542933 |
module and_combinational_logic_model (
c,
a,
b
);
output c;
input a, b;
assign c = (a && b);
endmodule
| 6.883187 |
module and_comb_tb;
reg SA, SB;
wire SY;
and_comb and_comb (
.A(SA),
.B(SB),
.Y(SY)
);
initial begin
SA = 0;
SB = 0;
#100 SA = 1;
SB = 0;
#100 SA = 0;
SB = 1;
#100 SA = 1;
SB = 1;
#100 $finish;
end
endmodule
| 6.648485 |
module my_and (
out,
a,
b
);
output out;
input a, b;
and and1 (out, a, b);
endmodule
| 8.69728 |
module And_DFF_Or (
in1,
in2,
in3,
CK,
out1
);
input in1, in2, in3, CK;
output out1;
wire w1, w2;
and AND1 (w1, in1, in2);
dff DFF1 (
CK,
w2,
w1
);
or OR1 (out1, w2, in3);
endmodule
| 6.879799 |
module and_dfm (
output Y,
input A,
B
);
assign Y = A & B;
endmodule
| 6.555762 |
module and_fact #(
parameter WIDTH = 32
) (
input [WIDTH - 1:0] a,
b,
output wire c
);
assign c = a & b;
endmodule
| 8.124136 |
module AND_G2 (
A,
B,
F
);
input A, B; // 输入端口定义
output F; // 输出端口定义
assign F = A & B; //如果F等于1 LED灯会亮，
//如果F等于0 LED灯不会亮，
endmodule
| 7.797063 |
module And_gate (
INPUT1,
INPUT2,
OUTPUT
);
input INPUT1;
input INPUT2;
output OUTPUT;
assign OUTPUT = INPUT1 & INPUT2;
endmodule
| 8.40007 |
module and_gate (
input A_i,
input B_i,
output F_o
);
assign F_o = A_i & B_i;
endmodule
| 8.887051 |
module counter input
CLR: module counter input
out_num: output port for the counter module
OV: overflow flag
------------------------------------------------------
History:
12-14-2015: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simula... | 7.206611 |
module AND_GATE_10_INPUTS (
Input_1,
Input_10,
Input_2,
Input_3,
Input_4,
Input_5,
Input_6,
Input_7,
Input_8,
Input_9,
Result
);
/***************************************************************************
** Here all module parameters are defined with a dummy value ... | 7.872232 |
module and_gate_16 (
c,
b,
a
);
output [15:0] c;
input [15:0] a;
input [15:0] b;
and_gate and_gate_call[15:0] (
c,
b,
a
);
endmodule
| 6.846078 |
module and_gate_2001_comma (
input a,
b,
output reg result
);
//Definition for Variables in the module
//Logical
always @(a, b) begin
result <= a & b;
end
endmodule
| 6.97362 |
module and_gate_2001_star (
input a,
b,
output reg result
);
//Definition for Variables in the module
//Logical
always @(*) begin
result <= a & b;
end
endmodule
| 6.97362 |
module and_gate_2inputs (
out,
in1,
in2
);
output out;
input in1, in2;
C1 c1_module (
2'b00,
in1,
2'b10,
in1,
{in2, in2},
out
);
endmodule
| 7.820078 |
module and_gate_32 (
x,
y,
z
);
input [31:0] x;
input [31:0] y;
output [31:0] z;
assign z = (x & y);
endmodule
| 9.819195 |
module and_gate_3inputs (
out,
in1,
in2,
in3
);
output out;
input in1, in2, in3;
wire and1_2_out;
and_gate_2inputs and1 (
and1_2_out,
in1,
in2
);
and_gate_2inputs and2 (
out,
and1_2_out,
in3
);
endmodule
| 8.671195 |
module AND_GATE_3_INPUTS (
Input_1,
Input_2,
Input_3,
Result
);
/***************************************************************************
** Here all module parameters are defined with a dummy value **
***************************************************************************/... | 7.771588 |
module and_gate_4inputs (
out,
in1,
in2,
in3,
in4
);
output out;
input in1, in2, in3, in4;
wire and1_2_3_out;
and_gate_3inputs and1 (
and1_2_3_out,
in1,
in2,
in3
);
and_gate_2inputs and2 (
out,
and1_2_3_out,
in4
);
endmodule
| 8.274462 |
module AND_GATE_4_INPUTS (
Input_1,
Input_2,
Input_3,
Input_4,
Result
);
/***************************************************************************
** Here all module parameters are defined with a dummy value **
***************************************************************... | 8.375909 |
module AND_GATE_5_INPUTS (
Input_1,
Input_2,
Input_3,
Input_4,
Input_5,
Result
);
/***************************************************************************
** Here all module parameters are defined with a dummy value **
**************************************************... | 8.568057 |
module AND_GATE_6_INPUTS (
Input_1,
Input_2,
Input_3,
Input_4,
Input_5,
Input_6,
Result
);
/***************************************************************************
** Here all module parameters are defined with a dummy value **
*************************************... | 8.453516 |
module AND_GATE_7_INPUTS (
Input_1,
Input_2,
Input_3,
Input_4,
Input_5,
Input_6,
Input_7,
Result
);
/***************************************************************************
** Here all module parameters are defined with a dummy value **
************************... | 8.544883 |
module AND_GATE_8_INPUTS (
Input_1,
Input_2,
Input_3,
Input_4,
Input_5,
Input_6,
Input_7,
Input_8,
Result
);
/***************************************************************************
** Here all module parameters are defined with a dummy value **
***********... | 8.761747 |
module and_gate_95 (
input a,
b,
output reg result
);
//Definition for Variables in the module
//Logical
always @(a or b) begin
result <= a & b;
end
endmodule
| 7.240829 |
module and_gate_behavioral (
A,
B,
X
);
input A, B;
output X;
reg X;
always @(A, B) begin
if (A == 1 && B == 1) X = 1;
else X = 0;
end
endmodule
| 6.617893 |
module and_gate_bitwise (
A,
B,
X
);
input A, B;
output X;
assign X = A & B;
endmodule
| 8.301988 |
module AND_GATE_BUS (
input1,
input2,
result
);
/*******************************************************************************
** Here all module parameters are defined with a dummy value **
*******************************************************************************/
parame... | 8.621443 |
module and_gate_gate_primitive (
A,
B,
X
);
input A, B;
output X;
and U0 (X, A, B);
endmodule
| 6.704694 |
module and_gate_level (
c,
a,
b
);
output c;
input a, b;
and G1 (c, a, b);
endmodule
| 8.154772 |
module and_gate_n (
x,
y,
z
);
// synopsys template
parameter n = 32;
input [n-1:0] x;
input [n-1:0] y;
output [n-1:0] z;
assign z = (x & y);
endmodule
| 8.441283 |
module And_Gate_Project (
input i_Switch_1,
input i_Switch_2,
output o_LED_1
);
assign o_LED_1 = i_Switch_1 & i_Switch_2;
endmodule
| 7.399305 |
module and_gate (
a,
b,
o
);
input a;
input b;
output o;
wire GND;
wire VCC;
wire a;
wire b;
wire o;
VCC VCC_cZ (.V(VCC));
GND GND_cZ (.G(GND));
GSR GSR (.GSRI(VCC));
LUT2 o_d_s (
.I0(a),
.I1(b),
.F (o)
);
defparam o_d_s.INIT = 4'h8;
endmodule
| 8.887051 |
module and_gate_tb;
`define AND_TEST(ID, A, B, OUT) \
a = A; \
b = B; \
#5; \
if(out == OUT) \
$display("Case %d passed!", ID); \
else begin \
$display("Case %d failed!", ID); \
$finish; \
end \
#5;
reg a;
reg b;
wire out;
and_gate x_and_gate (
.... | 7.961841 |
module and_gate_test ();
reg [31:0] A;
reg [31:0] B;
wire [31:0] C;
and_gate uut (
A,
B,
C
);
initial begin
A = 32'd1234;
B = 32'd0;
#250;
A = 32'd1234;
B = 32'd1234;
#250;
A = 32'd0;
B = 32'd9999;
#250;
A = 32'd99999;
B = 32'd9999;
#250;... | 6.561794 |
module and_glm (
output Y,
input A,
B
);
and (Y, A, B);
endmodule
| 6.917206 |
module and_HPC1 #(
parameter security_order = 2,
parameter pipeline = 1
) (
ina,
inb,
rnd,
clk,
outt
);
parameter integer d = security_order + 1;
`include "MSKand_HPC1.vh"
input [d-1:0] ina;
input [d-1:0] inb;
output [d-1:0] outt;
input clk;
input [and_pini_nrnd-1:0] rnd;
... | 7.594307 |
module AND_inciso3 (
//output out_7,
//output out_8,
output S_OR3,
input X,
input Y,
input Z,
input K,
input M
);
assign noX = !X;
assign noY = !Y;
assign noZ = !Z;
assign noK = !K;
assign noM = !M;
assign out_1 = noX & noY & noM; //implicante 3
assign out_2 ... | 6.564864 |
module AND_jalr (
input [31:0] lhs,
rhs,
output [31:0] res
);
assign res = lhs & rhs;
endmodule
| 7.117047 |
module and_latch (
clock,
a_in,
b_in,
out
);
// SIGNAL DECLARATIONS
input clock;
input a_in;
input b_in;
output out;
// ASSIGN STATEMENTS
always @(posedge clock) begin
out <= a_in & b_in;
end
endmodule
| 6.721103 |
module And_Gate (
input i_Switch_1,
input i_Switch_2,
output o_LED_1
);
assign o_LED_1 = i_Switch_1 & i_Switch_2;
endmodule
| 7.496103 |
module andnand_gate (
a,
b,
clk,
andout,
nandout
);
input [15:0] a, b;
output [15:0] andout, nandout;
always @(posedge clk) assign andout = a & b;
assign nandout = ~(a & b);
endmodule
| 7.931277 |
module
//=============================================
module nand_gate (a, b, nandout);
//---------------------------------------------
//Inputs/Outputs/regs
//---------------------------------------------
input [15:0] a, b;
output [15:0] nandout;
reg [15:0] reg_nandout;
always... | 7.574158 |
module AND_n_bit (
AND_out,
R2,
R3
);
parameter word_size = 32; // the default size
input [word_size-1:0] R2, R3;
output [word_size-1:0] AND_out;
and AND1[word_size-1:0] (AND_out, R2, R3);
endmodule
| 9.148956 |
module for ALU
//
//
//////////////////////////////////////////////////////////////////////////////////
module and_operator(X,Y,Z);
//port definitions - customize for different bit widths
input wire [31:0] X;
input wire [31:0] Y;
output wire [31:0] Z;
assign Z = X & Y;
endmodule
| 11.503445 |
module and_or (
input wire zero,
input wire pc_write_cond,
input wire pc_write,
output wire Pc_w
);
assign Pc_w = (pc_write_cond & zero) | pc_write;
endmodule
| 7.256084 |
module
module And_Or_Xor(in_numA, in_numB, out_And, out_Or, out_Xor);
parameter DATA_WIDTH = 64;
input [DATA_WIDTH - 1:0] in_numA, in_numB;
output [DATA_WIDTH - 1:0] out_And, out_Or, out_Xor;
assign out_And = in_numA & in_numB;
assign out_Or = in_numA | in_numB;
assign out_Xor = in_numA ^ i... | 7.641337 |
module and_power (
input i1,
i2,
i3,
i4,
clk,
output out
);
assign out = i1 & i2 & i3 & i4;
endmodule
| 7.562243 |
module and_q_k_URAM #(
parameter INDEX_WIDTH = 12
) (
input k,
input [INDEX_WIDTH-1:0] q,
output [INDEX_WIDTH-1:0] out_and
);
wire [INDEX_WIDTH-1:0] k_12;
assign k_12 = {INDEX_WIDTH{k}};
assign out_and = q & k_12;
endmodule
| 7.695597 |
module and_r #(
parameter WIDTH = 8
) (
input clk,
input [WIDTH-1:0] din,
output dout
);
genvar i;
generate
if (WIDTH <= 6) begin
reg dout_r = 1'b0;
always @(posedge clk) dout_r <= &din;
assign dout = dout_r;
end else if ((WIDTH % 6) == 0) begin
localparam NUM_HEXES ... | 7.634818 |
module and_r1_2ph ( /*AUTOARG*/
// Outputs
a1,
a2,
r,
// Inputs
r1,
r2,
a,
rstn
);
// Input pandts
input r1;
output a1;
input r2;
output a2;
// output pandt
output r;
input a;
input rstn;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTANDEG*/
/*AUTOWIRE*/
wire ... | 7.236833 |
module Compression (
port_u_0_0,
port_u_0_1,
port_u_1_0,
port_u_1_1,
port_c_0,
port_c_1
);
input [1:0] port_u_0_0;
input [1:0] port_u_0_1;
input [1:0] port_u_1_0;
input [1:0] port_u_1_1;
output [1:0] port_c_0;
output [1:0] port_c_1;
XOR2_X1 U1 (
.A(port_u_0_0[0]),
.B(... | 6.665518 |
module Compression (
port_u_0_0,
port_u_0_1,
port_u_1_0,
port_u_1_1,
port_c_0,
port_c_1
);
input [2:0] port_u_0_0;
input [2:0] port_u_0_1;
input [2:0] port_u_1_0;
input [2:0] port_u_1_1;
output [2:0] port_c_0;
output [2:0] port_c_1;
XOR2_X1 U1 (
.A(port_u_0_0[0]),
.B(... | 6.665518 |
module Compression (
port_u_0_0,
port_u_0_1,
port_u_0_2,
port_u_1_0,
port_u_1_1,
port_u_1_2,
port_u_2_0,
port_u_2_1,
port_u_2_2,
port_c_0,
port_c_1,
port_c_2
);
input [1:0] port_u_0_0;
input [1:0] port_u_0_1;
input [1:0] port_u_0_2;
input [1:0] port_u_1_0;
input... | 6.665518 |
module Compression (
port_u_0_0,
port_u_0_1,
port_u_0_2,
port_u_1_0,
port_u_1_1,
port_u_1_2,
port_u_2_0,
port_u_2_1,
port_u_2_2,
port_c_0,
port_c_1,
port_c_2
);
input [2:0] port_u_0_0;
input [2:0] port_u_0_1;
input [2:0] port_u_0_2;
input [2:0] port_u_1_0;
input... | 6.665518 |
module and_tp (
output z,
input x,
input y
);
assign #1 z = x & y;
endmodule
| 6.590066 |
module
module and_tree(N1, N2, N3, N4, N5, N6, N7, N8, N9);
input N1, N2, N3, N4, N5, N6, N7, N8;
output N9;
wire N10, N11, N12, N13, N14, N15;
and ginst1 (N10, N1, N2);
and ginst2 (N11, N3, N4);
and ginst3 (N12, N5, N6);
and ginst4 (N13, N7, N8);
and ginst5 (N14, N10, N11);
and ginst6 (N15, N12, N1... | 6.764226 |
module for the two input AND gate
module and_two_input_gate(
// inputs
input in1_and_gate,
input in2_and_gate,
//outputs
output out_and_gate
);
// Using verilog's definition for a gate or
and #4.3 and_gate(out_and_gate, in1_and_gate, in2_and_gate);
endmodule
| 8.5587 |
module andgate_u_mux (
i0,
i1,
y
);
input i0, i1;
output y;
mux21 m1 (
0,
i1,
i0,
y
);
endmodule
| 6.683966 |
module Angelia_AD4 (
clock,
SCLK,
nCS,
MISO,
MOSI,
AIN1,
AIN2
);
input wire clock;
output reg SCLK;
output reg nCS;
input wire MISO;
output reg MOSI;
output reg [11:0] AIN1; //
output reg [11:0] AIN2; //
reg [5:0] ADC_state = 1'd0;
reg [3:0] bit_cnt;
reg [12:0] tem... | 7.281839 |
module Angelia_ADC (
clock,
SCLK,
nCS,
MISO,
MOSI,
AIN1,
AIN2
);
input wire clock;
output reg SCLK;
output reg nCS;
input wire MISO;
output reg MOSI;
output reg [11:0] AIN1; //
output reg [11:0] AIN2; //
reg [5:0] ADC_state = 1'd0;
reg [3:0] bit_cnt;
reg [12:0] tem... | 7.24306 |
module Angelia_clk_lrclk_gen (
reset,
CLK_IN,
BCLK,
Brise,
Bfall,
LRCLK,
LRrise,
LRfall
);
localparam BCLK_DIV = (CLK_FREQ / 48000 / 64);
localparam BCLK_00 = 32;
parameter CLK_FREQ = 122880000; // frequency of incoming clock
input wire reset; // reset
input wire CLK_IN;
... | 7.541522 |
module angle_to_step #(
parameter SIZE = 64,
// MICROSTEPS / (STEPANGLE / GEARING)
// (in Q(SIZE >> 1).(SIZE>>1))
parameter [SIZE - 1 : 0] SCALE = {32'd4000, {(SIZE >> 1) {1'b0}}},
parameter SYSCLK = 25000000,
parameter [SIZE - 1 : 0] VRISE = 20000,
parameter [SIZE - 1 : 0] TRISE = 10000,
... | 7.132166 |
module SpeedController (
input AE_CLK, // Clock for angular encoder
input PWM_CLK, // Clock for PWM
input [7:0] Duty_In,
input AngularEncoder, // AE Wire
output PWM_Out,
output [7:0] Rate
);
reg [7:0] Counter; //, SetCounted;
reg [9:0] Wait_Count;
reg [8:0] Duty_Offset;
reg [9:0] Co... | 6.980638 |
module: SpeedController
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module AngularEncoderTest;
// Inputs
reg AE_CLK;
reg PWM_CLK;
reg [7:0] Duty_In;
reg AngularEncoder;
integer... | 6.595108 |
module animate_egg (
go,
lose,
resetn,
vga_x,
vga_y,
in_x,
in_y,
out_y,
colour,
plyr_x,
done,
clock,
speed
);
input go;
input resetn;
input clock;
input [7:0] plyr_x;
input [2:0] speed;
output reg lose;
reg writeEn;
reg go_increment;
reg go_increment... | 7.162971 |
module animate_plyr (
go,
resetn,
vga_x,
vga_y,
in_x,
out_x,
colour,
done,
clock,
left,
right
);
input go;
input resetn;
input clock;
input left;
input right;
reg writeEn;
reg go_increment;
reg go_decrement;
reg go_increment_init;
parameter [2:0] WAIT = 3... | 7.316989 |
module animation (
SW,
CLOCK_50, // On Board 50 MHz
KEY, // Push Button[3:0]
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK, // VGA BLANK
VGA_SYNC, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B // VGA Blue[9:0]
);
... | 8.192052 |
module coordinate_selector (
clk,
draw_,
erase_,
xPrev,
yPrev,
xNow,
yNow,
xPassIn,
yPassIn
);
input [7:0] xPrev, xNow;
input [6:0] yPrev, yNow;
input draw_, erase_, clk;
output reg [7:0] xPassIn;
output reg [6:0] yPassIn;
always @(posedge clk) begin
if (draw_) begin... | 7.539435 |
module sate_machine (
compute_enable,
clk_50,
draw_,
erase_,
plot
);
parameter IDLE = 2'b00;
parameter DRAW = 2'b01;
parameter ERASE = 2'b10;
input compute_enable, clk_50;
output draw_, erase_, plot;
reg [2:0] present_state, next_state;
assign plot = (present_state != IDLE);
assi... | 7.028833 |
module colour_select (
clk,
draw_,
xPrev,
yPrev,
xCounter,
yCounter,
colour
);
input [7:0] xPrev, xCounter;
input [6:0] yPrev, yCounter;
output reg [2:0] colour;
input clk, draw_;
always @(posedge clk) begin
if (draw_) colour <= 3'b111; // DRAW
else colour <= 3'b000;
end... | 7.125161 |
module animation_17 (
input clk,
input rst,
output reg [63:0] out_start,
output reg [63:0] out_win
);
reg [263:0] start;
reg [231:0] win;
localparam FLIP = 5'h18;
wire [5-1:0] M_counter_start_value;
counter_26 counter_start (
.clk (clk),
.rst (rst),
.value(M_counter_s... | 6.838054 |
module animator #(
parameter c_ledboards = 30,
parameter c_bpc = 12,
parameter c_max_time = 1024,
parameter c_max_type = 64,
parameter c_channels = c_ledboards * 32,
parameter c_addr_w = $clog2(c_channels),
parameter c_time_w = $clog2(c_max_time),
parameter c_type_w = $clog2(c_max_type)
... | 6.744441 |
module LUTRAM_GPR (
wclk,
we,
waddr,
d_i,
raddr,
d_o
);
/****************************************************************/
parameter DATA_WIDTH_W = 64;
parameter ADDR_WIDTH_W = 05;
parameter DATA_DEPTH_W = 32;
parameter DATA_WIDTH_R = 64;
parameter ADDR_WIDTH_R = 05;
parameter DA... | 8.02552 |
module ANN #(
parameter DW = 8,
parameter O_VEC = 21,
parameter N = 10
) (
input wire [DW*N-1:0] value,
weight,
input wire [DW-1:0] bias,
input wire clk,
rst,
start,
hidden,
output wire [DW-1:0] result,
output wire ready
);
wire [5:0] offset;
wire ld, clr, mult_done;... | 8.26444 |
module since it conveys intent,
// and avoids an RTL schematic cluttered with a bunch of AND gates.
// We do this using logic instead of a register synchronous clear
// since it might not be as portable, nor synthesize as well.
// See http://www.altera.com/literature/hb/qts/qts_qii51007.pdf (page 14-49):
// // Creat... | 7.695391 |
module aggregator (
clk,
rst_n,
sender_data,
sender_empty_n,
sender_deq,
receiver_data,
receiver_full_n,
receiver_enq,
change_fetch_width,
input_fetch_width
);
parameter DATA_WIDTH = 16;
parameter FETCH_WIDTH = 40;
input clk;
input rst_n;
input [DATA_WIDTH - 1:0] sender... | 7.870736 |
module CW_ff (
CLK,
D,
Q
);
parameter wD = 1;
input CLK;
input [wD - 1:0] D;
output reg [wD - 1:0] Q;
wire [wD - 1:0] D2 = D;
always @(posedge CLK) Q <= D2;
endmodule
| 7.001566 |
module kBestArrays (
clk,
csb0,
web0,
addr0,
wdata0,
rdata0,
csb1,
addr1,
rdata1
);
parameter DATA_WIDTH = 32;
parameter IDX_WIDTH = 9;
parameter K = 4;
parameter NUM_LEAVES = 64;
parameter LEAF_ADDRW = $clog2(NUM_LEAVES);
input clk;
input wire csb0;
input wire web0;
... | 7.912533 |
module LeavesMem (
clk,
csb0,
web0,
addr0,
wleaf0,
rleaf0,
rpatch_data0,
rpatch_idx0,
csb1,
addr1,
rpatch_data1,
rpatch_idx1
);
parameter DATA_WIDTH = 11;
parameter IDX_WIDTH = 9;
parameter LEAF_SIZE = 8;
parameter PATCH_SIZE = 5;
parameter NUM_LEAVES = 64;
pa... | 6.772541 |
module ResetMux (
select,
rst0,
rst1,
out_rst
);
input select;
input rst0;
input rst1;
output wire out_rst;
assign out_rst = (select ? rst1 : rst0);
endmodule
| 6.767128 |
module sky130_sram_1kbyte_1rw1r_32x256_8 (
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
parameter DELAY = 3;
paramete... | 7.095527 |
module SyncBit (
sCLK,
sRST,
dCLK,
sEN,
sD_IN,
dD_OUT
);
parameter init = 1'b0;
input sCLK;
input sRST;
input sEN;
input sD_IN;
input dCLK;
output wire dD_OUT;
reg sSyncReg;
reg dSyncReg1;
reg dSyncReg2;
assign dD_OUT = dSyncReg2;
always @(posedge sCLK or negedge sRST)
... | 6.836602 |
module ann_mux_3to1 (
//Input
input [ 1:0] iSel,
input [31:0] iFeature,
input [31:0] iOutput_Logsig,
//Output
output [31:0] oData_out
);
assign oData_out = (iSel == 2'b0) ? 32'b1 : (iSel == 2'b1) ? iFeature : iOutput_Logsig;
endmodule
| 7.884962 |
module ann_threshold (
//Input
input iClk,
input iReset_n,
input iInput_ready,
input [31:0] iOutput_Logsig,
//Output
output reg oFlag,
output reg oOutput_ready,
output reg [31:0] oData_out
);
parameter THRESHOLD = 32'h800000;
... | 6.993755 |
module anode_sel (
input CLK100MHZ,
input [2:0] rr,
output reg [7:0] AN
);
//Assign which digit to refresh with what segment mapping needed
always @(posedge CLK100MHZ) begin
case (rr)
//0 shows what 7-seg disp is beign affected
3'b000: AN = 8'b01111111;
3'b001: AN = 8'b10111111;
... | 8.78009 |
module top_module (
input in1,
input in2,
output out
);
assign out = in1 & (~in2);
endmodule
| 7.203305 |
module top_module (
input in1,
input in2,
output out
);
assign out = ~in2 & in1;
endmodule
| 7.203305 |
module ano_test_shift_register_32 ();
//测试移位功能
wire [31:0] data_bus_out;
wire [31:0] data_bus;
reg [31:0] data_bus_in = 32'b10110010111000101111000010111110;
reg en = 1, clear = 0, io = 1, clk = 0, is_left = 1'bx;
wire carry_bit;
shift_register_32 sr32 (
data_bus,
en,
clear,
io,
... | 6.927664 |
module ansiport_example ();
reg read, write = 0;
reg [7:0] data_in = 0;
reg [3:0] addr = 0;
wire [7:0] data_v95, data_notype, data_ansi;
initial begin
$monitor("%g rd=%b wr=%b addr=%b data_in=%h data_v95=%h data_notype=%h data_ansi=%h", $time,
read, write, addr, data_in, data_v95, data_noty... | 6.764758 |
module memory_v95 (
read,
write,
data_in,
addr,
data_out
);
input read;
input write;
input [7:0] data_in;
input [3:0] addr;
output [7:0] data_out;
reg [7:0] data_out;
reg [7:0] mem[0:15];
always @(*) begin
if (write) mem[addr] = data_in;
end
always @(read, addr) begin
... | 6.804368 |
module memory_ansi_notype (
input read,
input write,
input [7:0] data_in,
input [3:0] addr,
output [7:0] data_out
);
reg [7:0] mem[0:15];
always @(*) begin
if (write) mem[addr] = data_in;
end
assign data_out = (read) ? mem[addr] : 0;
endmodule
| 7.509735 |
module Top (
input [4:0] a,
input [4:0] b,
input [4:0] c,
output [8:0] addition
);
wire [8:0] sum;
wire [7:0] cout;
carrysave_3is2stage instantiated (
a[4:0],
b[4:0],
c[4:0],
sum[8:0],
cout[7:0]
);
assign addition[8:0] = sum[8:0] + ({cout[7:0], 1'b0});
endmodul... | 6.64497 |
module carrysave_3is2stage (
input [4:0] inp1,
input [4:0] inp2,
input [4:0] inp3,
output [8:0] sump,
output [7:0] coutp
);
wire [8:0] inp1_9bit;
wire [8:0] inp2_9bit;
wire [8:0] inp3_9bit;
assign inp1_9bit[8:0] = {inp1[4], inp1[4], inp1[4], inp1[4], inp1[4:0]};
assign inp2_9bit[8:0] = ... | 6.500131 |
module FullAdder (
input in1,
input in2,
input cin,
output sum,
output cout
);
assign sum = (in1 ^ in2) ^ cin;
assign cout = (in1 & in2) | (cin & (in1 ^ in2));
endmodule
| 7.610141 |
module Top_tb;
reg [4:0] a;
reg [4:0] b;
reg [4:0] c;
wire [8:0] addition;
Top testbench_adddition (
a[4:0],
b[4:0],
c[4:0],
addition[8:0]
);
initial begin
$monitor($time, "a = %b \t b = %b \t c = %b \t addition = %b \n", a[4:0], b[4:0], c[4:0],
addition[8:0])... | 6.693003 |
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