code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module implements a and gate
that takes an array and AND them together
*/
module and_arr #(parameter Width = 5)
(input [Width - 1:0] in,
output out);
wire [Width - 1:0] temp;
assign temp[0] = in[0];
genvar i;
generate
for (i = 1; i < Width; i = i + 1) begin: gen_and
and u_and(temp[i], in[i], temp[i-1]);
end
endgenerate
assign out = temp[Width - 1];
endmodule
| 6.904081 |
module AND_Array (
A,
B,
C
);
input [3:0] A, B;
output [3:0] C;
assign C[0] = A[0] & B[0];
assign C[1] = A[1] & B[1];
assign C[2] = A[2] & B[2];
assign C[3] = A[3] & B[3];
endmodule
| 7.206052 |
module and_block_assign (
input wire a,
b,
c,
output reg y
);
always @* begin
y = a;
y = y & b;
y = y & c;
end
endmodule
| 8.332254 |
module and_comb (
A,
B,
Y
);
input A, B;
output Y;
assign Y = A & B;
endmodule
| 7.542933 |
module and_combinational_logic_model (
c,
a,
b
);
output c;
input a, b;
assign c = (a && b);
endmodule
| 6.883187 |
module and_comb_tb;
reg SA, SB;
wire SY;
and_comb and_comb (
.A(SA),
.B(SB),
.Y(SY)
);
initial begin
SA = 0;
SB = 0;
#100 SA = 1;
SB = 0;
#100 SA = 0;
SB = 1;
#100 SA = 1;
SB = 1;
#100 $finish;
end
endmodule
| 6.648485 |
module my_and (
out,
a,
b
);
output out;
input a, b;
and and1 (out, a, b);
endmodule
| 8.69728 |
module And_DFF_Or (
in1,
in2,
in3,
CK,
out1
);
input in1, in2, in3, CK;
output out1;
wire w1, w2;
and AND1 (w1, in1, in2);
dff DFF1 (
CK,
w2,
w1
);
or OR1 (out1, w2, in3);
endmodule
| 6.879799 |
module and_dfm (
output Y,
input A,
B
);
assign Y = A & B;
endmodule
| 6.555762 |
module and_fact #(
parameter WIDTH = 32
) (
input [WIDTH - 1:0] a,
b,
output wire c
);
assign c = a & b;
endmodule
| 8.124136 |
module AND_G2 (
A,
B,
F
);
input A, B; // 输入端口定义
output F; // 输出端口定义
assign F = A & B; //如果F等于1 LED灯会亮，
//如果F等于0 LED灯不会亮，
endmodule
| 7.797063 |
module And_gate (
INPUT1,
INPUT2,
OUTPUT
);
input INPUT1;
input INPUT2;
output OUTPUT;
assign OUTPUT = INPUT1 & INPUT2;
endmodule
| 8.40007 |
module and_gate (
input A_i,
input B_i,
output F_o
);
assign F_o = A_i & B_i;
endmodule
| 8.887051 |
module counter input
CLR: module counter input
out_num: output port for the counter module
OV: overflow flag
------------------------------------------------------
History:
12-14-2015: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simulation time assignment
//Insert the modules
module And_Gates_test;
//defination for Variables
reg clk;
reg reset;
reg[1:0] cntr;
wire EN;
wire CLR;
wire[1:0] out_num;
wire OV;
wire[2:0] result;
//Connection to the modules
counter_2bits C1(.clk(clk), .Reset(reset), .EN(EN),
.CLR(CLR), .counter(out_num), .OV(OV));
and_gate_95 A1( .a(out_num[0]), .b(out_num[1]), .result(result[0]) );
and_gate_2001_comma A2( .a(out_num[0]), .b(out_num[1]), .result(result[1]) );
and_gate_2001_star A3( .a(out_num[0]), .b(out_num[1]), .result(result[2]) );
begin
assign EN = 1'b1;
assign CLR = 1'b0;
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#10 clk = !clk;
//Reverse the clock in each 10ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
//Couner as input
always @(posedge clk or reset)
begin
if ( !reset)
//reset statement: counter keeps at 0
begin
cntr <= 2'h0;
end
else
//Wroking, counter increasing
begin
cntr <= cntr + 2'h1;
end
end
end
endmodule
| 7.206611 |
module AND_GATE_10_INPUTS (
Input_1,
Input_10,
Input_2,
Input_3,
Input_4,
Input_5,
Input_6,
Input_7,
Input_8,
Input_9,
Result
);
/***************************************************************************
** Here all module parameters are defined with a dummy value **
***************************************************************************/
parameter BubblesMask = 1;
/***************************************************************************
** Here the inputs are defined **
***************************************************************************/
input Input_1;
input Input_10;
input Input_2;
input Input_3;
input Input_4;
input Input_5;
input Input_6;
input Input_7;
input Input_8;
input Input_9;
/***************************************************************************
** Here the outputs are defined **
***************************************************************************/
output Result;
/***************************************************************************
** Here the internal wires are defined **
***************************************************************************/
wire s_real_input_1;
wire s_real_input_10;
wire s_real_input_2;
wire s_real_input_3;
wire s_real_input_4;
wire s_real_input_5;
wire s_real_input_6;
wire s_real_input_7;
wire s_real_input_8;
wire s_real_input_9;
wire [9:0] s_signal_invert_mask;
/***************************************************************************
** Here the bubbles are processed **
***************************************************************************/
assign s_signal_invert_mask = BubblesMask;
assign s_real_input_1 = (s_signal_invert_mask[0]) ? ~Input_1 : Input_1;
assign s_real_input_2 = (s_signal_invert_mask[1]) ? ~Input_2 : Input_2;
assign s_real_input_3 = (s_signal_invert_mask[2]) ? ~Input_3 : Input_3;
assign s_real_input_4 = (s_signal_invert_mask[3]) ? ~Input_4 : Input_4;
assign s_real_input_5 = (s_signal_invert_mask[4]) ? ~Input_5 : Input_5;
assign s_real_input_6 = (s_signal_invert_mask[5]) ? ~Input_6 : Input_6;
assign s_real_input_7 = (s_signal_invert_mask[6]) ? ~Input_7 : Input_7;
assign s_real_input_8 = (s_signal_invert_mask[7]) ? ~Input_8 : Input_8;
assign s_real_input_9 = (s_signal_invert_mask[8]) ? ~Input_9 : Input_9;
assign s_real_input_10 = (s_signal_invert_mask[9]) ? ~Input_10 : Input_10;
/***************************************************************************
** Here the functionality is defined **
***************************************************************************/
assign Result = s_real_input_1 &
s_real_input_2 &
s_real_input_3 &
s_real_input_4 &
s_real_input_5 &
s_real_input_6 &
s_real_input_7 &
s_real_input_8 &
s_real_input_9 &
s_real_input_10;
endmodule
| 7.872232 |
module and_gate_16 (
c,
b,
a
);
output [15:0] c;
input [15:0] a;
input [15:0] b;
and_gate and_gate_call[15:0] (
c,
b,
a
);
endmodule
| 6.846078 |
module and_gate_2001_comma (
input a,
b,
output reg result
);
//Definition for Variables in the module
//Logical
always @(a, b) begin
result <= a & b;
end
endmodule
| 6.97362 |
module and_gate_2001_star (
input a,
b,
output reg result
);
//Definition for Variables in the module
//Logical
always @(*) begin
result <= a & b;
end
endmodule
| 6.97362 |
module and_gate_2inputs (
out,
in1,
in2
);
output out;
input in1, in2;
C1 c1_module (
2'b00,
in1,
2'b10,
in1,
{in2, in2},
out
);
endmodule
| 7.820078 |
module and_gate_32 (
x,
y,
z
);
input [31:0] x;
input [31:0] y;
output [31:0] z;
assign z = (x & y);
endmodule
| 9.819195 |
module and_gate_3inputs (
out,
in1,
in2,
in3
);
output out;
input in1, in2, in3;
wire and1_2_out;
and_gate_2inputs and1 (
and1_2_out,
in1,
in2
);
and_gate_2inputs and2 (
out,
and1_2_out,
in3
);
endmodule
| 8.671195 |
module AND_GATE_3_INPUTS (
Input_1,
Input_2,
Input_3,
Result
);
/***************************************************************************
** Here all module parameters are defined with a dummy value **
***************************************************************************/
parameter BubblesMask = 1;
/***************************************************************************
** Here the inputs are defined **
***************************************************************************/
input Input_1;
input Input_2;
input Input_3;
/***************************************************************************
** Here the outputs are defined **
***************************************************************************/
output Result;
/***************************************************************************
** Here the internal wires are defined **
***************************************************************************/
wire s_real_input_1;
wire s_real_input_2;
wire s_real_input_3;
wire [2:0] s_signal_invert_mask;
/***************************************************************************
** Here the bubbles are processed **
***************************************************************************/
assign s_signal_invert_mask = BubblesMask;
assign s_real_input_1 = (s_signal_invert_mask[0]) ? ~Input_1 : Input_1;
assign s_real_input_2 = (s_signal_invert_mask[1]) ? ~Input_2 : Input_2;
assign s_real_input_3 = (s_signal_invert_mask[2]) ? ~Input_3 : Input_3;
/***************************************************************************
** Here the functionality is defined **
***************************************************************************/
assign Result = s_real_input_1 & s_real_input_2 & s_real_input_3;
endmodule
| 7.771588 |
module and_gate_4inputs (
out,
in1,
in2,
in3,
in4
);
output out;
input in1, in2, in3, in4;
wire and1_2_3_out;
and_gate_3inputs and1 (
and1_2_3_out,
in1,
in2,
in3
);
and_gate_2inputs and2 (
out,
and1_2_3_out,
in4
);
endmodule
| 8.274462 |
module AND_GATE_4_INPUTS (
Input_1,
Input_2,
Input_3,
Input_4,
Result
);
/***************************************************************************
** Here all module parameters are defined with a dummy value **
***************************************************************************/
parameter BubblesMask = 1;
/***************************************************************************
** Here the inputs are defined **
***************************************************************************/
input Input_1;
input Input_2;
input Input_3;
input Input_4;
/***************************************************************************
** Here the outputs are defined **
***************************************************************************/
output Result;
/***************************************************************************
** Here the internal wires are defined **
***************************************************************************/
wire s_real_input_1;
wire s_real_input_2;
wire s_real_input_3;
wire s_real_input_4;
wire [3:0] s_signal_invert_mask;
/***************************************************************************
** Here the bubbles are processed **
***************************************************************************/
assign s_signal_invert_mask = BubblesMask;
assign s_real_input_1 = (s_signal_invert_mask[0]) ? ~Input_1 : Input_1;
assign s_real_input_2 = (s_signal_invert_mask[1]) ? ~Input_2 : Input_2;
assign s_real_input_3 = (s_signal_invert_mask[2]) ? ~Input_3 : Input_3;
assign s_real_input_4 = (s_signal_invert_mask[3]) ? ~Input_4 : Input_4;
/***************************************************************************
** Here the functionality is defined **
***************************************************************************/
assign Result = s_real_input_1 & s_real_input_2 & s_real_input_3 & s_real_input_4;
endmodule
| 8.375909 |
module AND_GATE_5_INPUTS (
Input_1,
Input_2,
Input_3,
Input_4,
Input_5,
Result
);
/***************************************************************************
** Here all module parameters are defined with a dummy value **
***************************************************************************/
parameter BubblesMask = 1;
/***************************************************************************
** Here the inputs are defined **
***************************************************************************/
input Input_1;
input Input_2;
input Input_3;
input Input_4;
input Input_5;
/***************************************************************************
** Here the outputs are defined **
***************************************************************************/
output Result;
/***************************************************************************
** Here the internal wires are defined **
***************************************************************************/
wire s_real_input_1;
wire s_real_input_2;
wire s_real_input_3;
wire s_real_input_4;
wire s_real_input_5;
wire [4:0] s_signal_invert_mask;
/***************************************************************************
** Here the bubbles are processed **
***************************************************************************/
assign s_signal_invert_mask = BubblesMask;
assign s_real_input_1 = (s_signal_invert_mask[0]) ? ~Input_1 : Input_1;
assign s_real_input_2 = (s_signal_invert_mask[1]) ? ~Input_2 : Input_2;
assign s_real_input_3 = (s_signal_invert_mask[2]) ? ~Input_3 : Input_3;
assign s_real_input_4 = (s_signal_invert_mask[3]) ? ~Input_4 : Input_4;
assign s_real_input_5 = (s_signal_invert_mask[4]) ? ~Input_5 : Input_5;
/***************************************************************************
** Here the functionality is defined **
***************************************************************************/
assign Result = s_real_input_1 &
s_real_input_2 &
s_real_input_3 &
s_real_input_4 &
s_real_input_5;
endmodule
| 8.568057 |
module AND_GATE_6_INPUTS (
Input_1,
Input_2,
Input_3,
Input_4,
Input_5,
Input_6,
Result
);
/***************************************************************************
** Here all module parameters are defined with a dummy value **
***************************************************************************/
parameter BubblesMask = 1;
/***************************************************************************
** Here the inputs are defined **
***************************************************************************/
input Input_1;
input Input_2;
input Input_3;
input Input_4;
input Input_5;
input Input_6;
/***************************************************************************
** Here the outputs are defined **
***************************************************************************/
output Result;
/***************************************************************************
** Here the internal wires are defined **
***************************************************************************/
wire s_real_input_1;
wire s_real_input_2;
wire s_real_input_3;
wire s_real_input_4;
wire s_real_input_5;
wire s_real_input_6;
wire [5:0] s_signal_invert_mask;
/***************************************************************************
** Here the bubbles are processed **
***************************************************************************/
assign s_signal_invert_mask = BubblesMask;
assign s_real_input_1 = (s_signal_invert_mask[0]) ? ~Input_1 : Input_1;
assign s_real_input_2 = (s_signal_invert_mask[1]) ? ~Input_2 : Input_2;
assign s_real_input_3 = (s_signal_invert_mask[2]) ? ~Input_3 : Input_3;
assign s_real_input_4 = (s_signal_invert_mask[3]) ? ~Input_4 : Input_4;
assign s_real_input_5 = (s_signal_invert_mask[4]) ? ~Input_5 : Input_5;
assign s_real_input_6 = (s_signal_invert_mask[5]) ? ~Input_6 : Input_6;
/***************************************************************************
** Here the functionality is defined **
***************************************************************************/
assign Result = s_real_input_1 &
s_real_input_2 &
s_real_input_3 &
s_real_input_4 &
s_real_input_5 &
s_real_input_6;
endmodule
| 8.453516 |
module AND_GATE_7_INPUTS (
Input_1,
Input_2,
Input_3,
Input_4,
Input_5,
Input_6,
Input_7,
Result
);
/***************************************************************************
** Here all module parameters are defined with a dummy value **
***************************************************************************/
parameter BubblesMask = 1;
/***************************************************************************
** Here the inputs are defined **
***************************************************************************/
input Input_1;
input Input_2;
input Input_3;
input Input_4;
input Input_5;
input Input_6;
input Input_7;
/***************************************************************************
** Here the outputs are defined **
***************************************************************************/
output Result;
/***************************************************************************
** Here the internal wires are defined **
***************************************************************************/
wire s_real_input_1;
wire s_real_input_2;
wire s_real_input_3;
wire s_real_input_4;
wire s_real_input_5;
wire s_real_input_6;
wire s_real_input_7;
wire [6:0] s_signal_invert_mask;
/***************************************************************************
** Here the bubbles are processed **
***************************************************************************/
assign s_signal_invert_mask = BubblesMask;
assign s_real_input_1 = (s_signal_invert_mask[0]) ? ~Input_1 : Input_1;
assign s_real_input_2 = (s_signal_invert_mask[1]) ? ~Input_2 : Input_2;
assign s_real_input_3 = (s_signal_invert_mask[2]) ? ~Input_3 : Input_3;
assign s_real_input_4 = (s_signal_invert_mask[3]) ? ~Input_4 : Input_4;
assign s_real_input_5 = (s_signal_invert_mask[4]) ? ~Input_5 : Input_5;
assign s_real_input_6 = (s_signal_invert_mask[5]) ? ~Input_6 : Input_6;
assign s_real_input_7 = (s_signal_invert_mask[6]) ? ~Input_7 : Input_7;
/***************************************************************************
** Here the functionality is defined **
***************************************************************************/
assign Result = s_real_input_1 &
s_real_input_2 &
s_real_input_3 &
s_real_input_4 &
s_real_input_5 &
s_real_input_6 &
s_real_input_7;
endmodule
| 8.544883 |
module AND_GATE_8_INPUTS (
Input_1,
Input_2,
Input_3,
Input_4,
Input_5,
Input_6,
Input_7,
Input_8,
Result
);
/***************************************************************************
** Here all module parameters are defined with a dummy value **
***************************************************************************/
parameter BubblesMask = 1;
/***************************************************************************
** Here the inputs are defined **
***************************************************************************/
input Input_1;
input Input_2;
input Input_3;
input Input_4;
input Input_5;
input Input_6;
input Input_7;
input Input_8;
/***************************************************************************
** Here the outputs are defined **
***************************************************************************/
output Result;
/***************************************************************************
** Here the internal wires are defined **
***************************************************************************/
wire s_real_input_1;
wire s_real_input_2;
wire s_real_input_3;
wire s_real_input_4;
wire s_real_input_5;
wire s_real_input_6;
wire s_real_input_7;
wire s_real_input_8;
wire [7:0] s_signal_invert_mask;
/***************************************************************************
** Here the bubbles are processed **
***************************************************************************/
assign s_signal_invert_mask = BubblesMask;
assign s_real_input_1 = (s_signal_invert_mask[0]) ? ~Input_1 : Input_1;
assign s_real_input_2 = (s_signal_invert_mask[1]) ? ~Input_2 : Input_2;
assign s_real_input_3 = (s_signal_invert_mask[2]) ? ~Input_3 : Input_3;
assign s_real_input_4 = (s_signal_invert_mask[3]) ? ~Input_4 : Input_4;
assign s_real_input_5 = (s_signal_invert_mask[4]) ? ~Input_5 : Input_5;
assign s_real_input_6 = (s_signal_invert_mask[5]) ? ~Input_6 : Input_6;
assign s_real_input_7 = (s_signal_invert_mask[6]) ? ~Input_7 : Input_7;
assign s_real_input_8 = (s_signal_invert_mask[7]) ? ~Input_8 : Input_8;
/***************************************************************************
** Here the functionality is defined **
***************************************************************************/
assign Result = s_real_input_1 &
s_real_input_2 &
s_real_input_3 &
s_real_input_4 &
s_real_input_5 &
s_real_input_6 &
s_real_input_7 &
s_real_input_8;
endmodule
| 8.761747 |
module and_gate_95 (
input a,
b,
output reg result
);
//Definition for Variables in the module
//Logical
always @(a or b) begin
result <= a & b;
end
endmodule
| 7.240829 |
module and_gate_behavioral (
A,
B,
X
);
input A, B;
output X;
reg X;
always @(A, B) begin
if (A == 1 && B == 1) X = 1;
else X = 0;
end
endmodule
| 6.617893 |
module and_gate_bitwise (
A,
B,
X
);
input A, B;
output X;
assign X = A & B;
endmodule
| 8.301988 |
module AND_GATE_BUS (
input1,
input2,
result
);
/*******************************************************************************
** Here all module parameters are defined with a dummy value **
*******************************************************************************/
parameter NrOfBits = 1;
parameter [64:0] BubblesMask = 1;
/*******************************************************************************
** The inputs are defined here **
*******************************************************************************/
input [NrOfBits-1:0] input1;
input [NrOfBits-1:0] input2;
/*******************************************************************************
** The outputs are defined here **
*******************************************************************************/
output [NrOfBits-1:0] result;
/*******************************************************************************
** The wires are defined here **
*******************************************************************************/
wire [NrOfBits-1:0] s_realInput1;
wire [NrOfBits-1:0] s_realInput2;
/*******************************************************************************
** The module functionality is described here **
*******************************************************************************/
/*******************************************************************************
** Here the bubbles are processed **
*******************************************************************************/
assign s_realInput1 = (BubblesMask[0] == 1'b0) ? input1 : ~input1;
assign s_realInput2 = (BubblesMask[1] == 1'b0) ? input2 : ~input2;
/*******************************************************************************
** Here the functionality is defined **
*******************************************************************************/
assign result = s_realInput1 & s_realInput2;
endmodule
| 8.621443 |
module and_gate_gate_primitive (
A,
B,
X
);
input A, B;
output X;
and U0 (X, A, B);
endmodule
| 6.704694 |
module and_gate_level (
c,
a,
b
);
output c;
input a, b;
and G1 (c, a, b);
endmodule
| 8.154772 |
module and_gate_n (
x,
y,
z
);
// synopsys template
parameter n = 32;
input [n-1:0] x;
input [n-1:0] y;
output [n-1:0] z;
assign z = (x & y);
endmodule
| 8.441283 |
module And_Gate_Project (
input i_Switch_1,
input i_Switch_2,
output o_LED_1
);
assign o_LED_1 = i_Switch_1 & i_Switch_2;
endmodule
| 7.399305 |
module and_gate (
a,
b,
o
);
input a;
input b;
output o;
wire GND;
wire VCC;
wire a;
wire b;
wire o;
VCC VCC_cZ (.V(VCC));
GND GND_cZ (.G(GND));
GSR GSR (.GSRI(VCC));
LUT2 o_d_s (
.I0(a),
.I1(b),
.F (o)
);
defparam o_d_s.INIT = 4'h8;
endmodule
| 8.887051 |
module and_gate_tb;
`define AND_TEST(ID, A, B, OUT) \
a = A; \
b = B; \
#5; \
if(out == OUT) \
$display("Case %d passed!", ID); \
else begin \
$display("Case %d failed!", ID); \
$finish; \
end \
#5;
reg a;
reg b;
wire out;
and_gate x_and_gate (
.a (a),
.b (b),
.out(out)
);
initial begin
`AND_TEST(8'd1, 1'b0, 1'b0, 1'b0);
`AND_TEST(8'd2, 1'b0, 1'b1, 1'b0);
`AND_TEST(8'd3, 1'b1, 1'b0, 1'b0);
`AND_TEST(8'd4, 1'b1, 1'b1, 1'b1);
$display("Success!");
$finish;
end
endmodule
| 7.961841 |
module and_gate_test ();
reg [31:0] A;
reg [31:0] B;
wire [31:0] C;
and_gate uut (
A,
B,
C
);
initial begin
A = 32'd1234;
B = 32'd0;
#250;
A = 32'd1234;
B = 32'd1234;
#250;
A = 32'd0;
B = 32'd9999;
#250;
A = 32'd99999;
B = 32'd9999;
#250;
end
endmodule
| 6.561794 |
module and_glm (
output Y,
input A,
B
);
and (Y, A, B);
endmodule
| 6.917206 |
module and_HPC1 #(
parameter security_order = 2,
parameter pipeline = 1
) (
ina,
inb,
rnd,
clk,
outt
);
parameter integer d = security_order + 1;
`include "MSKand_HPC1.vh"
input [d-1:0] ina;
input [d-1:0] inb;
output [d-1:0] outt;
input clk;
input [and_pini_nrnd-1:0] rnd;
wire [d-1:0] inb_ref;
reg [d-1:0] ina_delay;
wire [ref_n_rnd-1:0] rnd_ref;
assign rnd_ref = rnd[ref_n_rnd-1:0];
wire [and_pini_mul_nrnd-1:0] rnd_mul;
assign rnd_mul = rnd[and_pini_nrnd-1:ref_n_rnd];
if (pipeline != 0) begin
always @(posedge clk) ina_delay <= ina;
end else begin
always @(*) ina_delay <= ina;
end
MSKref #(
.d(d)
) rfrsh (
.in (inb),
.clk(clk),
.out(inb_ref),
.rnd(rnd_ref)
);
MSKand_DOM #(
.d(d)
) mul (
.ina(ina_delay),
.inb(inb_ref),
.clk(clk),
.rnd(rnd_mul),
.out(outt)
);
endmodule
| 7.594307 |
module AND_inciso3 (
//output out_7,
//output out_8,
output S_OR3,
input X,
input Y,
input Z,
input K,
input M
);
assign noX = !X;
assign noY = !Y;
assign noZ = !Z;
assign noK = !K;
assign noM = !M;
assign out_1 = noX & noY & noM; //implicante 3
assign out_2 = noX & Y & K & M; //implicante 8
assign out_3 = noY & noZ & K; //implicante 4
assign out_4 = X & noY & M; //implicante 10
assign out_5 = X & noZ & M; //implicante 9
assign out_6 = noX & noZ & noM; //implicante 1
assign S_OR3 = (out_1) | (out_2) | (out_3) | (out_4) | (out_5) | (out_6);
endmodule
| 6.564864 |
module AND_jalr (
input [31:0] lhs,
rhs,
output [31:0] res
);
assign res = lhs & rhs;
endmodule
| 7.117047 |
module and_latch (
clock,
a_in,
b_in,
out
);
// SIGNAL DECLARATIONS
input clock;
input a_in;
input b_in;
output out;
// ASSIGN STATEMENTS
always @(posedge clock) begin
out <= a_in & b_in;
end
endmodule
| 6.721103 |
module And_Gate (
input i_Switch_1,
input i_Switch_2,
output o_LED_1
);
assign o_LED_1 = i_Switch_1 & i_Switch_2;
endmodule
| 7.496103 |
module andnand_gate (
a,
b,
clk,
andout,
nandout
);
input [15:0] a, b;
output [15:0] andout, nandout;
always @(posedge clk) assign andout = a & b;
assign nandout = ~(a & b);
endmodule
| 7.931277 |
module
//=============================================
module nand_gate (a, b, nandout);
//---------------------------------------------
//Inputs/Outputs/regs
//---------------------------------------------
input [15:0] a, b;
output [15:0] nandout;
reg [15:0] reg_nandout;
always @(*) begin
reg_nandout = ~(a & b);
end
assign nandout = reg_nandout;
endmodule
| 7.574158 |
module AND_n_bit (
AND_out,
R2,
R3
);
parameter word_size = 32; // the default size
input [word_size-1:0] R2, R3;
output [word_size-1:0] AND_out;
and AND1[word_size-1:0] (AND_out, R2, R3);
endmodule
| 9.148956 |
module for ALU
//
//
//////////////////////////////////////////////////////////////////////////////////
module and_operator(X,Y,Z);
//port definitions - customize for different bit widths
input wire [31:0] X;
input wire [31:0] Y;
output wire [31:0] Z;
assign Z = X & Y;
endmodule
| 11.503445 |
module and_or (
input wire zero,
input wire pc_write_cond,
input wire pc_write,
output wire Pc_w
);
assign Pc_w = (pc_write_cond & zero) | pc_write;
endmodule
| 7.256084 |
module
module And_Or_Xor(in_numA, in_numB, out_And, out_Or, out_Xor);
parameter DATA_WIDTH = 64;
input [DATA_WIDTH - 1:0] in_numA, in_numB;
output [DATA_WIDTH - 1:0] out_And, out_Or, out_Xor;
assign out_And = in_numA & in_numB;
assign out_Or = in_numA | in_numB;
assign out_Xor = in_numA ^ in_numB;
endmodule
| 7.641337 |
module and_power (
input i1,
i2,
i3,
i4,
clk,
output out
);
assign out = i1 & i2 & i3 & i4;
endmodule
| 7.562243 |
module and_q_k_URAM #(
parameter INDEX_WIDTH = 12
) (
input k,
input [INDEX_WIDTH-1:0] q,
output [INDEX_WIDTH-1:0] out_and
);
wire [INDEX_WIDTH-1:0] k_12;
assign k_12 = {INDEX_WIDTH{k}};
assign out_and = q & k_12;
endmodule
| 7.695597 |
module and_r #(
parameter WIDTH = 8
) (
input clk,
input [WIDTH-1:0] din,
output dout
);
genvar i;
generate
if (WIDTH <= 6) begin
reg dout_r = 1'b0;
always @(posedge clk) dout_r <= &din;
assign dout = dout_r;
end else if ((WIDTH % 6) == 0) begin
localparam NUM_HEXES = WIDTH / 6;
wire [NUM_HEXES-1:0] tmp;
for (i = 0; i < NUM_HEXES; i = i + 1) begin : lp
and_r a (
.clk (clk),
.din (din[(i+1)*6-1:i*6]),
.dout(tmp[i])
);
defparam a.WIDTH = 6;
end
and_r h (
.clk (clk),
.din (tmp),
.dout(dout)
);
defparam h.WIDTH = NUM_HEXES;
end else if ((WIDTH % 5) == 0) begin
localparam NUM_QUINTS = WIDTH / 5;
wire [NUM_QUINTS-1:0] tmp;
for (i = 0; i < NUM_QUINTS; i = i + 1) begin : lp
and_r a (
.clk (clk),
.din (din[(i+1)*5-1:i*5]),
.dout(tmp[i])
);
defparam a.WIDTH = 5;
end
and_r h (
.clk (clk),
.din (tmp),
.dout(dout)
);
defparam h.WIDTH = NUM_QUINTS;
end else if ((WIDTH % 4) == 0) begin
localparam NUM_QUADS = WIDTH / 4;
wire [NUM_QUADS-1:0] tmp;
for (i = 0; i < NUM_QUADS; i = i + 1) begin : lp
and_r a (
.clk (clk),
.din (din[(i+1)*4-1:i*4]),
.dout(tmp[i])
);
defparam a.WIDTH = 4;
end
and_r h (
.clk (clk),
.din (tmp),
.dout(dout)
);
defparam h.WIDTH = NUM_QUADS;
end else begin
initial begin
$display("Oops - no pipelined gate pattern available for width %d", WIDTH);
$display("Please add");
$stop();
end
end
endgenerate
endmodule
| 7.634818 |
module and_r1_2ph ( /*AUTOARG*/
// Outputs
a1,
a2,
r,
// Inputs
r1,
r2,
a,
rstn
);
// Input pandts
input r1;
output a1;
input r2;
output a2;
// output pandt
output r;
input a;
input rstn;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTANDEG*/
/*AUTOWIRE*/
wire r;
wire r1, r2;
wire a1, a2;
wire g1, g2;
wire d1, d2;
arbitrer_r1_2ph U_ARBITRER (
// Input pandts
.r1(r1),
.a1(a1),
.r2(r2),
.a2(a2),
// Output pandts
.g1(g1),
.g2(g2),
.d1 (d1),
.d2 (d2),
.rstn(rstn)
);
// Structure is similar to the call block
// replacing the xor by an and
// and also inside the decision-wait element
// UPDATE : this does not work
// The following code seems to work way better
// If port #2 is zero, then the output r
// is already zero and not ready (a==1)
// else we have to wait for a
mux2 U_MUX2_1 (
.z (d1pre),
.s (d2),
.a0(g1),
.a1(a)
);
mux2 U_MUX2_2 (
.z (d2pre),
.s (d1),
.a0(g2),
.a1(a)
);
// and2 U_AND2_1(.z(d1pre), .a(a), .b(d2));
// and2 U_AND2_2(.z(d2pre), .a(d1), .b(a));
// We need some memory to keep the feedback when state change
// on the other port
muller2 U_MULLER_ACK1 (
.a(g1),
.b(d1pre),
.rstn(rstn),
.z(d1)
);
muller2 U_MULLER_ACK2 (
.a(g2),
.b(d2pre),
.rstn(rstn),
.z(d2)
);
and2 U_AND2_OUT (
.z(r),
.a(g1),
.b(g2)
);
endmodule
| 7.236833 |
module Compression (
port_u_0_0,
port_u_0_1,
port_u_1_0,
port_u_1_1,
port_c_0,
port_c_1
);
input [1:0] port_u_0_0;
input [1:0] port_u_0_1;
input [1:0] port_u_1_0;
input [1:0] port_u_1_1;
output [1:0] port_c_0;
output [1:0] port_c_1;
XOR2_X1 U1 (
.A(port_u_0_0[0]),
.B(port_u_0_1[0]),
.Z(port_c_0[0])
);
XOR2_X1 U2 (
.A(port_u_0_0[1]),
.B(port_u_0_1[1]),
.Z(port_c_0[1])
);
XOR2_X1 U3 (
.A(port_u_1_0[0]),
.B(port_u_1_1[0]),
.Z(port_c_1[0])
);
XOR2_X1 U4 (
.A(port_u_1_0[1]),
.B(port_u_1_1[1]),
.Z(port_c_1[1])
);
endmodule
| 6.665518 |
module Compression (
port_u_0_0,
port_u_0_1,
port_u_1_0,
port_u_1_1,
port_c_0,
port_c_1
);
input [2:0] port_u_0_0;
input [2:0] port_u_0_1;
input [2:0] port_u_1_0;
input [2:0] port_u_1_1;
output [2:0] port_c_0;
output [2:0] port_c_1;
XOR2_X1 U1 (
.A(port_u_0_0[0]),
.B(port_u_0_1[0]),
.Z(port_c_0[0])
);
XOR2_X1 U2 (
.A(port_u_0_0[1]),
.B(port_u_0_1[1]),
.Z(port_c_0[1])
);
XOR2_X1 U3 (
.A(port_u_0_0[2]),
.B(port_u_0_1[2]),
.Z(port_c_0[2])
);
XOR2_X1 U4 (
.A(port_u_1_0[0]),
.B(port_u_1_1[0]),
.Z(port_c_1[0])
);
XOR2_X1 U5 (
.A(port_u_1_0[1]),
.B(port_u_1_1[1]),
.Z(port_c_1[1])
);
XOR2_X1 U6 (
.A(port_u_1_0[2]),
.B(port_u_1_1[2]),
.Z(port_c_1[2])
);
endmodule
| 6.665518 |
module Compression (
port_u_0_0,
port_u_0_1,
port_u_0_2,
port_u_1_0,
port_u_1_1,
port_u_1_2,
port_u_2_0,
port_u_2_1,
port_u_2_2,
port_c_0,
port_c_1,
port_c_2
);
input [1:0] port_u_0_0;
input [1:0] port_u_0_1;
input [1:0] port_u_0_2;
input [1:0] port_u_1_0;
input [1:0] port_u_1_1;
input [1:0] port_u_1_2;
input [1:0] port_u_2_0;
input [1:0] port_u_2_1;
input [1:0] port_u_2_2;
output [1:0] port_c_0;
output [1:0] port_c_1;
output [1:0] port_c_2;
wire n1, n2, n3, n4, n5, n6;
XNOR2_X1 U1 (
.A (port_u_0_0[0]),
.B (port_u_0_1[0]),
.ZN(n1)
);
XNOR2_X1 U2 (
.A (n1),
.B (port_u_0_2[0]),
.ZN(port_c_0[0])
);
XNOR2_X1 U3 (
.A (port_u_0_0[1]),
.B (port_u_0_1[1]),
.ZN(n2)
);
XNOR2_X1 U4 (
.A (n2),
.B (port_u_0_2[1]),
.ZN(port_c_0[1])
);
XNOR2_X1 U5 (
.A (port_u_1_0[0]),
.B (port_u_1_1[0]),
.ZN(n3)
);
XNOR2_X1 U6 (
.A (n3),
.B (port_u_1_2[0]),
.ZN(port_c_1[0])
);
XNOR2_X1 U7 (
.A (port_u_1_0[1]),
.B (port_u_1_1[1]),
.ZN(n4)
);
XNOR2_X1 U8 (
.A (n4),
.B (port_u_1_2[1]),
.ZN(port_c_1[1])
);
XNOR2_X1 U9 (
.A (port_u_2_0[0]),
.B (port_u_2_1[0]),
.ZN(n5)
);
XNOR2_X1 U10 (
.A (n5),
.B (port_u_2_2[0]),
.ZN(port_c_2[0])
);
XNOR2_X1 U11 (
.A (port_u_2_0[1]),
.B (port_u_2_1[1]),
.ZN(n6)
);
XNOR2_X1 U12 (
.A (n6),
.B (port_u_2_2[1]),
.ZN(port_c_2[1])
);
endmodule
| 6.665518 |
module Compression (
port_u_0_0,
port_u_0_1,
port_u_0_2,
port_u_1_0,
port_u_1_1,
port_u_1_2,
port_u_2_0,
port_u_2_1,
port_u_2_2,
port_c_0,
port_c_1,
port_c_2
);
input [2:0] port_u_0_0;
input [2:0] port_u_0_1;
input [2:0] port_u_0_2;
input [2:0] port_u_1_0;
input [2:0] port_u_1_1;
input [2:0] port_u_1_2;
input [2:0] port_u_2_0;
input [2:0] port_u_2_1;
input [2:0] port_u_2_2;
output [2:0] port_c_0;
output [2:0] port_c_1;
output [2:0] port_c_2;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9;
XNOR2_X1 U1 (
.A (port_u_0_0[0]),
.B (port_u_0_1[0]),
.ZN(n1)
);
XNOR2_X1 U2 (
.A (n1),
.B (port_u_0_2[0]),
.ZN(port_c_0[0])
);
XNOR2_X1 U3 (
.A (port_u_0_0[1]),
.B (port_u_0_1[1]),
.ZN(n2)
);
XNOR2_X1 U4 (
.A (n2),
.B (port_u_0_2[1]),
.ZN(port_c_0[1])
);
XNOR2_X1 U5 (
.A (port_u_0_0[2]),
.B (port_u_0_1[2]),
.ZN(n3)
);
XNOR2_X1 U6 (
.A (n3),
.B (port_u_0_2[2]),
.ZN(port_c_0[2])
);
XNOR2_X1 U7 (
.A (port_u_1_0[0]),
.B (port_u_1_1[0]),
.ZN(n4)
);
XNOR2_X1 U8 (
.A (n4),
.B (port_u_1_2[0]),
.ZN(port_c_1[0])
);
XNOR2_X1 U9 (
.A (port_u_1_0[1]),
.B (port_u_1_1[1]),
.ZN(n5)
);
XNOR2_X1 U10 (
.A (n5),
.B (port_u_1_2[1]),
.ZN(port_c_1[1])
);
XNOR2_X1 U11 (
.A (port_u_1_0[2]),
.B (port_u_1_1[2]),
.ZN(n6)
);
XNOR2_X1 U12 (
.A (n6),
.B (port_u_1_2[2]),
.ZN(port_c_1[2])
);
XNOR2_X1 U13 (
.A (port_u_2_0[0]),
.B (port_u_2_1[0]),
.ZN(n7)
);
XNOR2_X1 U14 (
.A (n7),
.B (port_u_2_2[0]),
.ZN(port_c_2[0])
);
XNOR2_X1 U15 (
.A (port_u_2_0[1]),
.B (port_u_2_1[1]),
.ZN(n8)
);
XNOR2_X1 U16 (
.A (n8),
.B (port_u_2_2[1]),
.ZN(port_c_2[1])
);
XNOR2_X1 U17 (
.A (port_u_2_0[2]),
.B (port_u_2_1[2]),
.ZN(n9)
);
XNOR2_X1 U18 (
.A (n9),
.B (port_u_2_2[2]),
.ZN(port_c_2[2])
);
endmodule
| 6.665518 |
module and_tp (
output z,
input x,
input y
);
assign #1 z = x & y;
endmodule
| 6.590066 |
module
module and_tree(N1, N2, N3, N4, N5, N6, N7, N8, N9);
input N1, N2, N3, N4, N5, N6, N7, N8;
output N9;
wire N10, N11, N12, N13, N14, N15;
and ginst1 (N10, N1, N2);
and ginst2 (N11, N3, N4);
and ginst3 (N12, N5, N6);
and ginst4 (N13, N7, N8);
and ginst5 (N14, N10, N11);
and ginst6 (N15, N12, N13);
and ginst7 (N9, N14, N15);
endmodule
| 6.764226 |
module for the two input AND gate
module and_two_input_gate(
// inputs
input in1_and_gate,
input in2_and_gate,
//outputs
output out_and_gate
);
// Using verilog's definition for a gate or
and #4.3 and_gate(out_and_gate, in1_and_gate, in2_and_gate);
endmodule
| 8.5587 |
module andgate_u_mux (
i0,
i1,
y
);
input i0, i1;
output y;
mux21 m1 (
0,
i1,
i0,
y
);
endmodule
| 6.683966 |
module Angelia_AD4 (
clock,
SCLK,
nCS,
MISO,
MOSI,
AIN1,
AIN2
);
input wire clock;
output reg SCLK;
output reg nCS;
input wire MISO;
output reg MOSI;
output reg [11:0] AIN1; //
output reg [11:0] AIN2; //
reg [5:0] ADC_state = 1'd0;
reg [3:0] bit_cnt;
reg [12:0] temp_1;
reg [12:0] temp_2;
reg CH = 0;
// NOTE: this code generates the SCLK clock for the ADC
always @(posedge clock) begin
case (ADC_state)
0: begin
nCS <= 1; // set nCS high
bit_cnt <= 4'd12; // set bit counter
CH <= ~CH;
ADC_state <= ADC_state + 1'd1;
end
1: begin
nCS <= 0; // select ADC
SCLK <= 0;
MOSI <= 1; // START bit
ADC_state <= ADC_state + 1'd1;
end
2: begin
SCLK <= 1; // SCLK high
ADC_state <= ADC_state + 1'd1;
end
3: begin
SCLK <= 0; // SCLK low
MOSI <= 1; // SGL/DIFF bit
ADC_state <= ADC_state + 1'd1;
end
4: begin
SCLK <= 1; // SCLK high
ADC_state <= ADC_state + 1'd1;
end
5: begin
SCLK <= 0; // SCLK low
MOSI <= 1; // D2 bit
ADC_state <= ADC_state + 1'd1;
end
6: begin
SCLK <= 1; // SCLK high
ADC_state <= ADC_state + 1'd1;
end
7: begin
SCLK <= 0; // SCLK low
MOSI <= 1; // D1 bit
ADC_state <= ADC_state + 1'd1;
end
8: begin
SCLK <= 1; // SCLK high
ADC_state <= ADC_state + 1'd1;
end
9: begin
SCLK <= 0; // SCLK low
MOSI <= CH; // Channel select
ADC_state <= ADC_state + 1'd1;
end
10: begin
SCLK <= 1; // SCLK high
ADC_state <= ADC_state + 1'd1;
end
11: begin
SCLK <= 0; // SCLK low
ADC_state <= ADC_state + 1'd1;
end
12: begin
SCLK <= 1; // SCLK high
ADC_state <= ADC_state + 1'd1;
end
13: begin
SCLK <= 0; // SCLK low
ADC_state <= ADC_state + 1'd1;
end
14: begin
SCLK <= 1; // SCLK high
ADC_state <= ADC_state + 1'd1;
end
15: begin
SCLK <= 0; // SCLK low
ADC_state <= ADC_state + 1'd1;
end
16: begin
SCLK <= 1; // SCLK high
ADC_state <= ADC_state + 1'd1;
end
17: begin
if (CH) temp_1[bit_cnt] <= MISO;
else temp_2[bit_cnt] <= MISO;
SCLK <= 0; // SCLK low
ADC_state <= ADC_state + 1'd1;
end
18:
if (bit_cnt == 0) begin
if (CH) AIN1 <= temp_1[11:0];
else AIN2 <= temp_2[11:0];
ADC_state <= 1'd0;
end else begin
bit_cnt <= bit_cnt - 1'd1;
ADC_state <= 6'd16;
end
default: ADC_state <= 0;
endcase
end
endmodule
| 7.281839 |
module Angelia_ADC (
clock,
SCLK,
nCS,
MISO,
MOSI,
AIN1,
AIN2
);
input wire clock;
output reg SCLK;
output reg nCS;
input wire MISO;
output reg MOSI;
output reg [11:0] AIN1; //
output reg [11:0] AIN2; //
reg [5:0] ADC_state = 1'd0;
reg [3:0] bit_cnt;
reg [12:0] temp_1;
reg [12:0] temp_2;
reg CH = 0;
// NOTE: this code generates the SCLK clock for the ADC
always @(posedge clock) begin
case (ADC_state)
0: begin
nCS <= 1; // set nCS high
bit_cnt <= 4'd12; // set bit counter
CH <= ~CH;
ADC_state <= ADC_state + 1'd1;
end
1: begin
nCS <= 0; // select ADC
SCLK <= 0;
MOSI <= 1; // START bit
ADC_state <= ADC_state + 1'd1;
end
2: begin
SCLK <= 1; // SCLK high
ADC_state <= ADC_state + 1'd1;
end
3: begin
SCLK <= 0; // SCLK low
MOSI <= 1; // SGL/DIFF bit
ADC_state <= ADC_state + 1'd1;
end
4: begin
SCLK <= 1; // SCLK high
ADC_state <= ADC_state + 1'd1;
end
5: begin
SCLK <= 0; // SCLK low
MOSI <= CH; // Channel select
ADC_state <= ADC_state + 1'd1;
end
6: begin
SCLK <= 1; // SCLK high
ADC_state <= ADC_state + 1'd1;
end
7: begin
SCLK <= 0; // SCLK low
MOSI <= 1; // MSBF bit
ADC_state <= ADC_state + 1'd1;
end
8: begin
SCLK <= 1; // SCLK high
ADC_state <= ADC_state + 1'd1;
end
9: begin
SCLK <= 0; // SCLK low
ADC_state <= ADC_state + 1'd1;
end
10: begin
SCLK <= 1; // SCLK high
ADC_state <= ADC_state + 1'd1;
end
11: begin
if (CH) temp_1[bit_cnt] <= MISO;
else temp_2[bit_cnt] <= MISO;
SCLK <= 0; // SCLK low
ADC_state <= ADC_state + 1'd1;
end
12:
if (bit_cnt == 0) begin
if (CH) AIN1 <= temp_1[11:0];
else AIN2 <= temp_2[11:0];
ADC_state <= 1'd0;
end else begin
bit_cnt <= bit_cnt - 1'd1;
ADC_state <= 6'd10;
end
default: ADC_state <= 0;
endcase
end
endmodule
| 7.24306 |
module Angelia_clk_lrclk_gen (
reset,
CLK_IN,
BCLK,
Brise,
Bfall,
LRCLK,
LRrise,
LRfall
);
localparam BCLK_DIV = (CLK_FREQ / 48000 / 64);
localparam BCLK_00 = 32;
parameter CLK_FREQ = 122880000; // frequency of incoming clock
input wire reset; // reset
input wire CLK_IN;
output reg BCLK;
output reg Brise;
output reg Bfall;
output reg LRCLK;
output reg LRrise;
output reg LRfall;
localparam LS = clogb2(32 - 1); // 0 to (BCLK_10-1)
// internal signals
reg [ 15:0] BCLK_cnt;
//reg [15:0] BCLK_DIV;
reg [LS-1:0] LRCLK_cnt;
localparam TPD = 1;
// CLK_IN gets divided down to create BCLK
always @(posedge CLK_IN) begin
if (reset) BCLK_cnt <= #TPD 0;
else if (BCLK_cnt == (BCLK_DIV - 1)) BCLK_cnt <= #TPD 0;
else BCLK_cnt <= #TPD BCLK_cnt + 1'b1; // 0, 1, ...(BCLK_DIV-1), 0, ...
if (reset) Brise <= 1'b0;
else Brise <= (BCLK_cnt == (BCLK_DIV / 2));
if (reset) Bfall <= 1'b0;
else Bfall <= (BCLK_cnt == 1'b0); // may not be a 50/50 duty cycle
if (Brise) BCLK <= #TPD 1'b1;
else if (Bfall) BCLK <= #TPD 1'b0;
if (reset) LRCLK_cnt <= #TPD 0;
else begin
if ((LRCLK_cnt == 0) && Bfall) begin
LRCLK_cnt <= #TPD BCLK_00 - 1;
end else if (Bfall) LRCLK_cnt <= #TPD LRCLK_cnt - 1'b1;
end
if (reset) LRCLK <= #TPD 1'b1;
else if ((LRCLK_cnt == 0) && Bfall) LRCLK <= #TPD ~LRCLK;
if (reset) LRrise <= 1'b0;
else LRrise <= (LRCLK_cnt == 0) && Bfall && !LRCLK;
if (reset) LRfall <= 1'b0;
else LRfall <= (LRCLK_cnt == 0) && Bfall && LRCLK; // may not be a 50/50 duty cycle
end
function integer clogb2;
input [31:0] depth;
begin
for (clogb2 = 0; depth > 0; clogb2 = clogb2 + 1) depth = depth >> 1;
end
endfunction
endmodule
| 7.541522 |
module angle_to_step #(
parameter SIZE = 64,
// MICROSTEPS / (STEPANGLE / GEARING)
// (in Q(SIZE >> 1).(SIZE>>1))
parameter [SIZE - 1 : 0] SCALE = {32'd4000, {(SIZE >> 1) {1'b0}}},
parameter SYSCLK = 25000000,
parameter [SIZE - 1 : 0] VRISE = 20000,
parameter [SIZE - 1 : 0] TRISE = 10000,
parameter [SIZE - 1 : 0] OUTPUT_DIV_MIN = 50
) (
input clk_i,
input enable_i,
output reg done_o = 1'b1,
input [SIZE - 1:0] relative_angle_i,
output step_o
);
parameter SF = SIZE >> 1;
parameter INC = {1'b1, {SF{1'b0}}};
wire int_clk;
wire output_clk;
// Used as the actual frequency divider (inverse)
reg [SIZE - 1:0] r_t = INC;
wire [SIZE - 1:0] speedup;
wire [SIZE - 1:0] div;
wire [SIZE - 1:0] negated_div;
wire [SIZE - 1:0] invers_div;
wire [SIZE - 1:0] switched_invers_div;
reg r_output_clk_prev = 1'b0;
reg r_enable_prev = 1'b0;
reg r_run = 1'b0;
reg [SIZE - 1:0] steps_done = 0;
wire [SIZE - 1:0] steps_needed;
assign step_o = (r_t > INC) ? output_clk : 1'b0;
always @(posedge clk_i) begin
// Reset on negative edge
if (!enable_i && r_enable_prev) begin
r_run <= 1'b0;
done_o <= 1'b0;
$display("%m>\tDisabled");
end
if ((steps_done >> SF) >= (steps_needed >> SF)) begin
r_run <= 1'b0;
done_o <= 1'b1;
end
// Enable output
if (enable_i && !r_enable_prev) begin
r_run <= 1'b1;
done_o <= 1'b0;
$display("%m>\tEnabled");
end
r_enable_prev <= enable_i;
end
// Counter to keep track of how far the algorithm has already stepped.
// It is used to find out when the algorithm needs to be reversed for the falloff.
always @(posedge clk_i) begin
// Count the steps done up until it reaches steps_done
if (r_run) begin
if (output_clk && !r_output_clk_prev) begin
steps_done <= steps_done + INC;
end
end else begin
steps_done <= 0;
end
r_output_clk_prev <= output_clk;
end
// Increment time if the output is enabled
always @(posedge int_clk) begin
if (r_run) begin
if ((steps_needed >> 1) <= steps_done) begin
r_t <= r_t - INC;
end else begin
r_t <= r_t + INC;
end
end else begin
r_t <= INC;
end
end
/* speedup = VRISE / TRISE */
fx_div #(
.Q(SF),
.N(SIZE)
) calc_speedup (
.dividend_i(VRISE << SF),
.divisor_i (TRISE << SF),
.quotient_o(speedup),
.start_i(1'b1),
.clk_i (clk_i),
.complete_o(),
.overflow_o()
);
/* div = r_t * speedup */
fx_mult #(
.Q(SF),
.N(SIZE)
) calc_clk_divider (
.multiplicand_i(speedup),
.multiplier_i(r_t),
.r_result_o(div),
.overflow_r_o()
);
/* negated_div = -div */
assign negated_div[SIZE-2:0] = div[SIZE-2:0];
assign negated_div[SIZE-1] = ~div[SIZE-1];
/* invers_div = VRISE + negated_div */
fx_add #(
.Q(SF),
.N(SIZE)
) calc_invert_div (
.summand_a_i((VRISE + OUTPUT_DIV_MIN) << SF),
.summand_b_i(negated_div),
.sum_i(invers_div)
);
assign switched_invers_div = (r_t > 0 && r_t < (TRISE << SF)) ? invers_div : OUTPUT_DIV_MIN << SF;
/* steps_needed = relative_angle_i * SCALE; */
fx_mult #(
.Q(SF),
.N(SIZE)
) steps_needed_mult (
.multiplicand_i(relative_angle_i),
.multiplier_i(SCALE),
.r_result_o(steps_needed),
.overflow_r_o()
);
// Internal clk (used for timekeeping)
clk_divider #(
.SIZE(32)
) internal_clk_gen (
.clk_in (clk_i),
// Every 1 us
.max_in ((SYSCLK / 1000000) >> 1),
.clk_out(int_clk)
);
// Step pulse generator clk divider
clk_divider #(
.SIZE(SIZE)
) step_pulse_gen (
.clk_in (clk_i),
.max_in ((switched_invers_div >> SF) >> 1),
.clk_out(output_clk)
);
endmodule
| 7.132166 |
module SpeedController (
input AE_CLK, // Clock for angular encoder
input PWM_CLK, // Clock for PWM
input [7:0] Duty_In,
input AngularEncoder, // AE Wire
output PWM_Out,
output [7:0] Rate
);
reg [7:0] Counter; //, SetCounted;
reg [9:0] Wait_Count;
reg [8:0] Duty_Offset;
reg [9:0] Count60Hz;
integer Rate_;
reg First;
wire [7:0] SetCounted;
assign Rate = Rate_;
reg Average_CLK;
initial begin
First = 1;
Counter = 0;
Rate_ = 0;
Wait_Count = 0;
Count60Hz = 0;
//SetCounted=100;
end
// Measured frequencies:
// 0 to 200 Hz
always @(posedge AE_CLK) begin
//Average_CLK <= 0;
if (First) begin // first check on posedge
if (AngularEncoder) begin
Wait_Count <= 0;
Counter <= Counter + 1; // increment counter
end else begin
First <= 0; // end of pulse
//Average_CLK <= 1;
//Counter <= 0; // reset counter
//SetCounted <= Counter;
//Rate_ <= ((Duty_In*2)-Counter == 0 && Duty_In > 0) ?
// Duty_In :
// (Duty_In*2)-Counter; // take difference
end
end else if (AngularEncoder) begin
First <= 1; // Allow for next pulse
Counter <= 1; // Count this pulse
end else if (Wait_Count > 1000) begin
// nothing is happening... speed stuck at 0!
Wait_Count <= 0;
Rate_ <= Duty_In;
end else begin
Wait_Count <= Wait_Count + 1;
Counter <= 0; // reset counter
end
// take offset between the two signals.
//Duty_Offset <= (Duty_In*2)-SetCounted; // Accounts for real-time offset
Duty_Offset <= 2 * Duty_In - (Duty_In + SetCounted) / 2;
//Duty_Offset <= (Duty_In-SetCounted)*2;
Rate_ <= ((Rate_ <= 10 && Duty_In > 10) || SetCounted == 0) ?
Duty_In :
(Duty_Offset > 255) ? 255 : Duty_Offset;
end
always @(negedge AE_CLK) begin
// 51.2k / 60Hz =
Count60Hz <= Count60Hz + 1;
Average_CLK <= 0;
if (Count60Hz > 1707) begin // set
Count60Hz <= 0;
Average_CLK <= 1;
end
end
PWM pwm1 (
.CLK(PWM_CLK),
.DUTY_CYCLE(Rate_),
.PWM_OUT(PWM_Out)
);
Average8 averager ( // provides concise averaging over time
.CLK(Average_CLK),
.SampleIN(Counter),
.AverageOUT(SetCounted)
);
endmodule
| 6.980638 |
module: SpeedController
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module AngularEncoderTest;
// Inputs
reg AE_CLK;
reg PWM_CLK;
reg [7:0] Duty_In;
reg AngularEncoder;
integer CC,CC2, CC3, TRate;
// Outputs
wire PWM_Out;
wire [7:0] Rate;
// Instantiate the Unit Under Test (UUT)
SpeedController uut (
.AE_CLK(AE_CLK),
.PWM_CLK(PWM_CLK),
.Duty_In(Duty_In),
.AngularEncoder(AngularEncoder),
.PWM_Out(PWM_Out),
.Rate(Rate)
);
initial begin
// Initialize Inputs
AE_CLK = 0;
PWM_CLK = 0;
Duty_In = 0;
AngularEncoder = 0;
CC=0;
CC2=0;
CC3=0;
TRate = 130;
// Wait 100 ns for global reset to finish
#100;
Duty_In = 100;
// Add stimulus here
while(1) begin
AE_CLK = ~AE_CLK; // run clock
#9766; // 5.12 kHz in nanoseconds
if(CC2 == (10)) begin // 5120 Hz
PWM_CLK = ~PWM_CLK;
CC2 = 0;
end
if(CC3 >= 2560) begin //2560 is normal, set different for unstable
CC3 = 0;
//TRate = (TRate >= 130) ? 20 : TRate+1;
end
// wait for first 400Hz signal timeout
if(CC >= (TRate*2)) begin
CC=0;
AngularEncoder = ~AngularEncoder; // set opposite
end
CC = CC+1;
CC2 = CC2+1;
CC3 = CC3+1;
end
end
endmodule
| 6.595108 |
module animate_egg (
go,
lose,
resetn,
vga_x,
vga_y,
in_x,
in_y,
out_y,
colour,
plyr_x,
done,
clock,
speed
);
input go;
input resetn;
input clock;
input [7:0] plyr_x;
input [2:0] speed;
output reg lose;
reg writeEn;
reg go_increment;
reg go_increment_init;
parameter [2:0] WAIT = 3'b000, SHIFT = 3'b010, CHECK = 3'b100, PRINT = 3'b110;
parameter [6:0] HEIGHT_SCREEN = 7'b1111000;
parameter [3:0] HEIGHT_EGG = 4'b0001, WIDTH_EGG = 4'b0001;
parameter [4:0] HEIGHT_PLYR = 5'b10100, WIDTH_PLYR = 5'b10100;
wire [6:0] w_out_y;
wire done_print; //done signal to know when finished printing
input [7:0] in_x; //original start x
wire [7:0] w_in_x;
assign w_in_x = in_x;
input [6:0] in_y; //original start y
reg [6:0] w_in_y;
wire [7:0] w_vga_x;
wire [6:0] w_vga_y;
output [7:0] vga_x; //all pixels to be printed x
output [6:0] vga_y; //all pixels to be printed y
output [6:0] out_y; //new shifted start y
output [2:0] colour;
output reg done = 0;
reg [2:0] PresentState, NextState;
reg [3:0] count;
always @(*) begin : StateTable
case (PresentState)
WAIT: begin
done = 0;
if (go == 0) begin
NextState = WAIT;
lose = 0;
end else begin
NextState = SHIFT;
lose = 0;
end
end
SHIFT: begin
NextState = CHECK;
done = 0;
lose = 0;
end
CHECK: begin
if (((w_out_y >= (HEIGHT_SCREEN)) && ((w_in_x < plyr_x) || (w_in_x > (plyr_x + WIDTH_PLYR)))))
begin
NextState = WAIT;
lose = 1;
done = 0;
end else begin
NextState = PRINT;
done = 0;
lose = 0;
end
end
PRINT: begin
if (done_print == 1) begin
NextState = WAIT;
done = 1;
lose = 0;
end else begin
NextState = PRINT;
done = 0;
lose = 0;
end
end
default: begin
NextState = WAIT;
done = 0;
lose = 0;
end
endcase
end
always @(posedge clock) begin
if (go_increment_init) begin
w_in_y = in_y;
end
if (go_increment) begin
w_in_y = w_in_y + speed;
end
end
always @(*) begin : output_logic
case (PresentState)
WAIT: begin
go_increment_init = 1;
go_increment = 0;
writeEn = 0;
end
SHIFT: begin
go_increment_init = 0;
go_increment = 1;
writeEn = 0;
end
CHECK: begin
go_increment_init = 0;
go_increment = 0;
writeEn = 0;
end
PRINT: begin
go_increment_init = 0;
go_increment = 0;
writeEn = 1;
end
default: begin
go_increment_init = 0;
go_increment = 0;
writeEn = 0;
end
endcase
end
always @(posedge clock) begin : state_FFs
if (resetn == 1'b0) PresentState <= WAIT;
else PresentState <= NextState;
end
assign out_y = w_in_y;
assign w_out_y = w_in_y;
assign vga_x = w_vga_x;
assign vga_y = w_vga_y;
draw_egg egg1 (
.reset(resetn),
.writeEn(writeEn),
.x(w_vga_x),
.y(w_vga_y),
.startx(w_in_x),
.starty(w_out_y),
.clock(clock),
.color(colour),
.done_print(done_print)
);
endmodule
| 7.162971 |
module animate_plyr (
go,
resetn,
vga_x,
vga_y,
in_x,
out_x,
colour,
done,
clock,
left,
right
);
input go;
input resetn;
input clock;
input left;
input right;
reg writeEn;
reg go_increment;
reg go_decrement;
reg go_increment_init;
parameter [2:0] WAIT = 3'b000, SHIFT = 3'b010, PRINT = 3'b110;
parameter [6:0] HEIGHT_SCREEN = 7'b1111000;
parameter [3:0] HEIGHT_EGG = 4'b1010, WIDTH_EGG = 4'b1010;
parameter [4:0] HEIGHT_PLYR = 5'b10100, WIDTH_PLYR = 5'b10100;
wire [7:0] w_out_x;
wire [6:0] w_out_y;
assign w_out_y = HEIGHT_SCREEN - HEIGHT_PLYR;
wire done_print; //done signal to know when finished printing
input [7:0] in_x; //original start x
reg [7:0] w_in_x;
wire [7:0] w_vga_x;
wire [6:0] w_vga_y;
output [7:0] vga_x; //all pixels to be printed x
output [6:0] vga_y; //all pixels to be printed y
output [7:0] out_x; //new shifted start x
output [2:0] colour;
output reg done = 0;
reg [2:0] PresentState, NextState;
reg [3:0] count;
always @(*) begin : StateTable
case (PresentState)
WAIT: begin
done = 0;
if (go == 0) NextState = WAIT;
else begin
NextState = SHIFT;
end
end
SHIFT: begin
NextState = PRINT;
done = 0;
end
PRINT: begin
if (done_print == 1) begin
NextState = WAIT;
done = 1;
end else begin
NextState = PRINT;
done = 0;
end
end
default: begin
NextState = WAIT;
done = 0;
end
endcase
end
always @(posedge clock) begin
if (go_increment_init) begin
w_in_x = in_x;
end else if (go_increment) w_in_x = w_in_x + 3'b111;
else if (go_decrement) w_in_x = w_in_x - 3'b111;
end
always @(*) begin : output_logic
case (PresentState)
WAIT: begin
go_increment_init = 1;
go_increment = 0;
go_decrement = 0;
writeEn = 0;
end
SHIFT: begin
go_increment_init = 0;
if (left == 0) begin
go_decrement = 1;
go_increment = 0;
end else if (right == 0) begin
go_increment = 1;
go_decrement = 0;
end else begin
go_increment = 0;
go_decrement = 0;
end
writeEn = 0;
end
PRINT: begin
writeEn = 1;
go_increment_init = 0;
go_increment = 0;
go_decrement = 0;
end
default: begin
writeEn = 0;
go_increment_init = 0;
go_increment = 0;
go_decrement = 0;
end
endcase
end
always @(posedge clock) begin : state_FFs
if (resetn == 1'b0) PresentState <= WAIT;
else PresentState <= NextState;
end
assign out_x = w_in_x;
assign w_out_x = w_in_x;
assign vga_x = w_vga_x;
assign vga_y = w_vga_y;
draw_plyr plyr1 (
.reset(resetn),
.writeEn(writeEn),
.x(w_vga_x),
.y(w_vga_y),
.startx(w_out_x),
.starty(w_out_y),
.clock(clock),
.color(colour),
.done_print(done_print)
);
endmodule
| 7.316989 |
module animation (
SW,
CLOCK_50, // On Board 50 MHz
KEY, // Push Button[3:0]
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK, // VGA BLANK
VGA_SYNC, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B // VGA Blue[9:0]
);
input CLOCK_50; // 50 MHz
input [0:0] KEY; // Button[3:0]
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK; // VGA BLANK
output VGA_SYNC; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
input [17:0] SW;
wire resetn;
assign resetn = KEY[0];
// Create the color, x, y and writeEn wires that are inputs to the controller.
wire [2:0] colour;
wire [7:0] xCounter;
wire [6:0] yCounter;
wire writeEn;
// assign color = 3'b111;
reg [28:0] counter;
reg [7:0] xPos;
reg [6:0] yPos;
reg [7:0] xPrev;
reg [6:0] yPrev;
wire [7:0] xPassIn;
wire [6:0] yPassIn;
parameter MOVEx = 8'd1;
parameter MOVEy = 7'd1;
wire compute_enable;
wire do_draw;
assign compute_enable = counter[22] & counter[23];
always @(posedge CLOCK_50) begin
if (counter > 28'd12582912) begin
counter <= 28'd0; // computational refresh rate ~= 12.5 MHz
// nooo :(
end else counter <= counter + 1;
if (compute_enable) begin
xPrev <= xPos;
yPrev <= yPos;
xPos <= xPos + MOVEx;
yPos <= yPos + MOVEy;
end
// if (do_draw)
// colour <= 3'b111;
// else // erase
// colour <= 3'b000;
end
wire draw_, erase_, plot;
assign writeEn = SW[2] & plot;
sate_machine FSM (
compute_enable,
CLOCK_50,
draw_,
erase_,
plot
);
coordinate_selector CS (
CLOCK_50,
draw_,
erase_,
xPrev,
yPrev,
xPos,
yPos,
xPassIn,
yPassIn
);
colour_select colour_mux (
CLOCK_50,
draw_,
xPrev,
yPrev,
xCounter,
yCounter,
colour
);
// Create an Instance of a VGA controller - there can be only one!
// Define the number of colours as well as the initial background
// image file (.MIF) for the controller.
vga_adapter VGA (
.resetn(resetn),
.clock(CLOCK_50),
.colour(colour),
.x(xPassIn),
.y(yPassIn),
.plot(writeEn),
/* Signals for the DAC to drive the monitor. */
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK),
.VGA_SYNC(VGA_SYNC),
.VGA_CLK(VGA_CLK)
);
defparam VGA.RESOLUTION = "160x120"; defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1; defparam VGA.BACKGROUND_IMAGE = "display.mif";
// Put your code here. Your code should produce signals x,y,color and writeEn
// for the VGA controller, in addition to any other functionality your design may require.
endmodule
| 8.192052 |
module coordinate_selector (
clk,
draw_,
erase_,
xPrev,
yPrev,
xNow,
yNow,
xPassIn,
yPassIn
);
input [7:0] xPrev, xNow;
input [6:0] yPrev, yNow;
input draw_, erase_, clk;
output reg [7:0] xPassIn;
output reg [6:0] yPassIn;
always @(posedge clk) begin
if (draw_) begin
xPassIn <= xNow;
yPassIn <= yNow;
end else if (erase_) begin
xPassIn <= xPrev;
yPassIn <= yPrev;
end
end
endmodule
| 7.539435 |
module sate_machine (
compute_enable,
clk_50,
draw_,
erase_,
plot
);
parameter IDLE = 2'b00;
parameter DRAW = 2'b01;
parameter ERASE = 2'b10;
input compute_enable, clk_50;
output draw_, erase_, plot;
reg [2:0] present_state, next_state;
assign plot = (present_state != IDLE);
assign draw_ = (present_state == DRAW);
assign erase_ = (present_state == ERASE);
always @(posedge clk_50) begin
case (present_state)
IDLE: begin
if (compute_enable) next_state <= ERASE;
else next_state <= IDLE;
end
DRAW: next_state <= IDLE;
ERASE: next_state <= DRAW;
default: next_state <= IDLE;
endcase
present_state <= next_state;
end
endmodule
| 7.028833 |
module colour_select (
clk,
draw_,
xPrev,
yPrev,
xCounter,
yCounter,
colour
);
input [7:0] xPrev, xCounter;
input [6:0] yPrev, yCounter;
output reg [2:0] colour;
input clk, draw_;
always @(posedge clk) begin
if (draw_) colour <= 3'b111; // DRAW
else colour <= 3'b000;
end
endmodule
| 7.125161 |
module animation_17 (
input clk,
input rst,
output reg [63:0] out_start,
output reg [63:0] out_win
);
reg [263:0] start;
reg [231:0] win;
localparam FLIP = 5'h18;
wire [5-1:0] M_counter_start_value;
counter_26 counter_start (
.clk (clk),
.rst (rst),
.value(M_counter_start_value)
);
wire [5-1:0] M_counter_win_value;
counter_27 counter_win (
.clk (clk),
.rst (rst),
.value(M_counter_win_value)
);
integer i;
always @* begin
start = 264'h00000000086888878414444202063e2181071110208485080842428404f8e08f9c;
win = 232'h18070381e224121f811089febe5f2ff402017fa020119902010000e070;
for (i = 1'h0; i < 4'h8; i = i + 1) begin
out_start[(i)*8+7-:8] = start[(i)*33+32-:33] >> M_counter_start_value | start[(i)*33+32-:33] << (6'h21 - M_counter_start_value);
out_win[(i)*8+7-:8] = win[(i)*29+28-:29] >> M_counter_win_value | win[(i)*29+28-:29] << (5'h1d - M_counter_win_value);
end
end
endmodule
| 6.838054 |
module animator #(
parameter c_ledboards = 30,
parameter c_bpc = 12,
parameter c_max_time = 1024,
parameter c_max_type = 64,
parameter c_channels = c_ledboards * 32,
parameter c_addr_w = $clog2(c_channels),
parameter c_time_w = $clog2(c_max_time),
parameter c_type_w = $clog2(c_max_type)
) (
input i_clk,
i_drq,
input [c_bpc-1:0] i_target_data,
i_current_data,
input [c_type_w-1:0] i_type,
input [c_time_w-1:0] i_target_time,
i_start_time,
output o_wen,
output [c_addr_w-1:0] o_addr,
output [c_bpc-1:0] o_data,
output o_drq
);
localparam c_channels_1 = c_channels - 1;
localparam c_max_time_1 = c_max_time - 1;
reg [c_addr_w-1:0] r_addr = 0;
reg [c_bpc-1:0] r_data = 0;
reg r_wen = 0;
reg r_drq = 0;
reg [c_time_w-1:0] r_count = 0;
localparam s_wait = 3'd0;
localparam s_read = 3'd1;
localparam s_anim = 3'd2;
localparam s_write = 3'd3;
localparam s_end = 3'd4;
reg [2:0] r_state = s_wait;
localparam c_anim_linear = 1'd1;
/* verilator lint_off WIDTH */
task calculate;
input [c_type_w-1:0] i_anim_type;
input [c_bpc-1:0] i_current_data;
input [c_bpc-1:0] i_target_data;
input [c_time_w-1:0] i_start_time;
input [c_time_w-1:0] i_current_time;
input [c_time_w-1:0] i_target_time;
output [c_bpc-1:0] o_data;
begin
case (i_anim_type)
// TODO BUG division by zero possible
c_anim_linear: begin
if (i_target_time < i_current_time) begin
o_data = i_current_data + (i_target_data - i_current_data) /
(c_max_time - i_current_time + i_target_time);
end else begin
o_data = i_current_data + (i_target_data - i_current_data) /
(i_target_time - i_current_time);
end
end
default: begin
end
endcase
end
endtask
/* verilator lint_on WIDTH */
always @(posedge i_clk) begin
case (r_state)
s_wait: begin
if (i_drq == 1'b1) begin
if (r_count == c_max_time_1[c_time_w-1:0]) begin
r_count <= 0;
end else begin
r_count <= r_count + 1;
end
r_addr <= 0;
r_state <= s_read;
end
r_drq <= 0;
end
s_read: begin
r_state <= s_anim;
end
s_anim: begin
calculate(i_type, i_current_data, i_target_data, i_start_time, r_count, i_target_time,
r_data);
r_wen <= 1;
r_state <= s_write;
end
s_write: begin
r_wen <= 0;
if (r_addr == c_channels_1[c_addr_w-1:0]) begin
r_state <= s_end;
end else begin
r_addr <= r_addr + 1;
r_state <= s_read;
end
end
s_end: begin
if (r_count == i_target_time) begin
r_drq <= 1'b1;
end
r_state <= s_wait;
end
default: begin
end
endcase
end
assign o_addr = r_addr;
assign o_data = r_data;
assign o_wen = r_wen;
assign o_drq = r_drq;
endmodule
| 6.744441 |
module LUTRAM_GPR (
wclk,
we,
waddr,
d_i,
raddr,
d_o
);
/****************************************************************/
parameter DATA_WIDTH_W = 64;
parameter ADDR_WIDTH_W = 05;
parameter DATA_DEPTH_W = 32;
parameter DATA_WIDTH_R = 64;
parameter ADDR_WIDTH_R = 05;
parameter DATA_DEPTH_R = 32;
/****************************************************************/
input wclk;
input we;
/****************************************************************/
wire wclk;
wire we;
/****************************************************************/
/*Input*/
input d_i;
input waddr;
input raddr;
/*Output*/
output d_o;
/****************************************************************/
wire [DATA_WIDTH_W-1:0] d_i;
wire [ADDR_WIDTH_W-1:0] waddr;
wire [ADDR_WIDTH_R-1:0] raddr;
wire [DATA_WIDTH_R-1:0] d_o;
EG_LOGIC_DRAM #(
.INIT_FILE ("Anlogic_GPR_Sample_64bit_INIT.mif"),
.DATA_WIDTH_W(DATA_WIDTH_W),
.ADDR_WIDTH_W(ADDR_WIDTH_W),
.DATA_DEPTH_W(DATA_DEPTH_W),
.DATA_WIDTH_R(DATA_WIDTH_R),
.ADDR_WIDTH_R(ADDR_WIDTH_R),
.DATA_DEPTH_R(DATA_DEPTH_R)
) DRAM_inst (
.di (d_i),
.waddr(waddr),
.wclk (wclk),
.we (we),
.do (d_o),
.raddr(raddr)
);
/****************************************************************/
endmodule
| 8.02552 |
module ANN #(
parameter DW = 8,
parameter O_VEC = 21,
parameter N = 10
) (
input wire [DW*N-1:0] value,
weight,
input wire [DW-1:0] bias,
input wire clk,
rst,
start,
hidden,
output wire [DW-1:0] result,
output wire ready
);
wire [5:0] offset;
wire ld, clr, mult_done;
Neuron_DataPath #(
.DW(DW),
.N(N),
.O_VEC(O_VEC)
) data_path (
value,
weight,
bias,
offset,
clk,
rst,
ld,
clr,
ready,
mult_done,
hidden,
result
);
Neuron_Controller #(
.N(N)
) controller (
clk,
rst,
start,
offset,
ld,
clr,
ready,
mult_done
);
endmodule
| 8.26444 |
module since it conveys intent,
// and avoids an RTL schematic cluttered with a bunch of AND gates.
// We do this using logic instead of a register synchronous clear
// since it might not be as portable, nor synthesize as well.
// See http://www.altera.com/literature/hb/qts/qts_qii51007.pdf (page 14-49):
// // Creating many registers with different sload and sclr signals can make
// // packing the registers into LABs difficult for the Quartus II Fitter
// // because the sclr and sload signals are LAB-wide signals. In addition,
// // using the LAB-wide sload signal prevents the Fitter from packing
// // registers using the quick feedback path in the device architecture,
// // which means that some registers cannot be packed with other logic.
// // Synthesis tools typically restrict use of sload and sclr signals to
// // cases in which there are enough registers with common signals to allow
// // good LAB packing. Using the look-up table (LUT) to implement the signals
// // is always more flexible if it is available. Because different device
// // families offer different numbers of control signals, inference of these
// // signals is also device-specific. For example, because Stratix II devices
// // have more flexibility than Stratix devices with respect to secondary
// // control signals, synthesis tools might infer more sload and sclr signals
// // for Stratix II devices.
`default_nettype none
module Annuller
#(
parameter WORD_WIDTH = 0
)
(
input wire annul,
input wire [WORD_WIDTH-1:0] in,
output reg [WORD_WIDTH-1:0] out
);
initial begin
out = 0;
end
always @(*) begin
out <= (annul == 1'b1) ? {WORD_WIDTH{1'b0}} : in;
end
endmodule
| 7.695391 |
module aggregator (
clk,
rst_n,
sender_data,
sender_empty_n,
sender_deq,
receiver_data,
receiver_full_n,
receiver_enq,
change_fetch_width,
input_fetch_width
);
parameter DATA_WIDTH = 16;
parameter FETCH_WIDTH = 40;
input clk;
input rst_n;
input [DATA_WIDTH - 1:0] sender_data;
input sender_empty_n;
output wire sender_deq;
output wire [(FETCH_WIDTH * DATA_WIDTH) - 1:0] receiver_data;
input receiver_full_n;
output reg receiver_enq;
input change_fetch_width;
input [2:0] input_fetch_width;
localparam COUNTER_WIDTH = $clog2(FETCH_WIDTH);
reg [COUNTER_WIDTH - 1:0] count_r;
reg [DATA_WIDTH - 1:0] receiver_data_unpacked[FETCH_WIDTH - 1:0];
wire sender_deq_w;
assign sender_deq_w = (rst_n && sender_empty_n) && receiver_full_n;
assign sender_deq = sender_deq_w;
genvar i;
generate
for (i = 0; i < FETCH_WIDTH; i = i + 1) begin : unpack
assign receiver_data[((i+1)*DATA_WIDTH)-1:i*DATA_WIDTH] = receiver_data_unpacked[i];
end
endgenerate
reg [5:0] LOCAL_FETCH_WIDTH;
always @(posedge clk)
if (!rst_n) LOCAL_FETCH_WIDTH <= FETCH_WIDTH;
else if (change_fetch_width) LOCAL_FETCH_WIDTH <= {3'b000, input_fetch_width};
else LOCAL_FETCH_WIDTH <= LOCAL_FETCH_WIDTH;
always @(posedge clk)
if (rst_n) begin
if (sender_deq_w) begin
receiver_data_unpacked[count_r] <= sender_data;
count_r <= (count_r == LOCAL_FETCH_WIDTH ? 0 : count_r + 1);
receiver_enq <= count_r == LOCAL_FETCH_WIDTH;
end else receiver_enq <= 0;
end else begin
receiver_enq <= 0;
count_r <= 0;
end
endmodule
| 7.870736 |
module CW_ff (
CLK,
D,
Q
);
parameter wD = 1;
input CLK;
input [wD - 1:0] D;
output reg [wD - 1:0] Q;
wire [wD - 1:0] D2 = D;
always @(posedge CLK) Q <= D2;
endmodule
| 7.001566 |
module kBestArrays (
clk,
csb0,
web0,
addr0,
wdata0,
rdata0,
csb1,
addr1,
rdata1
);
parameter DATA_WIDTH = 32;
parameter IDX_WIDTH = 9;
parameter K = 4;
parameter NUM_LEAVES = 64;
parameter LEAF_ADDRW = $clog2(NUM_LEAVES);
input clk;
input wire csb0;
input wire web0;
input wire [7:0] addr0;
input wire [(K * DATA_WIDTH) - 1:0] wdata0;
output wire [(K * DATA_WIDTH) - 1:0] rdata0;
input wire [K - 1:0] csb1;
input wire [7:0] addr1;
output wire [(K * DATA_WIDTH) - 1:0] rdata1;
wire [DATA_WIDTH - 1:0] dout0[K - 1:0];
wire [DATA_WIDTH - 1:0] dout1[K - 1:0];
genvar i;
generate
for (i = 0; i < K; i = i + 1) begin : loop_best_array_gen
sram_1kbyte_1rw1r #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(8),
.RAM_DEPTH (256)
) best_dist_array_inst (
.clk0 (clk),
.csb0 (csb0),
.web0 (web0),
.addr0(addr0),
.din0 (wdata0[i*DATA_WIDTH+:DATA_WIDTH]),
.dout0(dout0[i]),
.clk1 (clk),
.csb1 (csb1[i]),
.addr1(addr1),
.dout1(dout1[i])
);
assign rdata0[i*DATA_WIDTH+:DATA_WIDTH] = dout0[i];
assign rdata1[i*DATA_WIDTH+:DATA_WIDTH] = dout1[i];
end
endgenerate
endmodule
| 7.912533 |
module LeavesMem (
clk,
csb0,
web0,
addr0,
wleaf0,
rleaf0,
rpatch_data0,
rpatch_idx0,
csb1,
addr1,
rpatch_data1,
rpatch_idx1
);
parameter DATA_WIDTH = 11;
parameter IDX_WIDTH = 9;
parameter LEAF_SIZE = 8;
parameter PATCH_SIZE = 5;
parameter NUM_LEAVES = 64;
parameter LEAF_ADDRW = $clog2(NUM_LEAVES);
input wire clk;
input wire [LEAF_SIZE - 1:0] csb0;
input wire [LEAF_SIZE - 1:0] web0;
input wire [LEAF_ADDRW - 1:0] addr0;
input wire [((PATCH_SIZE * DATA_WIDTH) + IDX_WIDTH) - 1:0] wleaf0;
output wire [(LEAF_SIZE * 64) - 1:0] rleaf0;
output wire [((LEAF_SIZE * PATCH_SIZE) * DATA_WIDTH) - 1:0] rpatch_data0;
output wire [(LEAF_SIZE * IDX_WIDTH) - 1:0] rpatch_idx0;
input wire csb1;
input wire [LEAF_ADDRW - 1:0] addr1;
output wire [((LEAF_SIZE * PATCH_SIZE) * DATA_WIDTH) - 1:0] rpatch_data1;
output wire [(LEAF_SIZE * IDX_WIDTH) - 1:0] rpatch_idx1;
wire [7:0] ram_addr0;
wire [7:0] ram_addr1;
wire [63:0] rdata0[LEAF_SIZE - 1:0];
wire [63:0] rdata1[LEAF_SIZE - 1:0];
assign ram_addr0 = {1'sb0, addr0};
assign ram_addr1 = {1'sb0, addr1};
genvar i;
generate
for (i = 0; i < LEAF_SIZE; i = i + 1) begin : loop_ram_patch_gen
sram_1kbyte_1rw1r #(
.DATA_WIDTH(64),
.ADDR_WIDTH(8),
.RAM_DEPTH (256)
) ram_patch_inst (
.clk0 (clk),
.csb0 (csb0[i]),
.web0 (web0[i]),
.addr0(ram_addr0),
.din0 (wleaf0),
.dout0(rdata0[i]),
.clk1 (clk),
.csb1 (csb1),
.addr1(ram_addr1),
.dout1(rdata1[i])
);
assign rpatch_data0[DATA_WIDTH * (i * PATCH_SIZE)+:DATA_WIDTH * PATCH_SIZE] = rdata0[i][(PATCH_SIZE * DATA_WIDTH) - 1:0];
assign rpatch_idx0[i*IDX_WIDTH+:IDX_WIDTH] = rdata0[i][63:PATCH_SIZE*DATA_WIDTH];
assign rpatch_data1[DATA_WIDTH * (i * PATCH_SIZE)+:DATA_WIDTH * PATCH_SIZE] = rdata1[i][(PATCH_SIZE * DATA_WIDTH) - 1:0];
assign rpatch_idx1[i*IDX_WIDTH+:IDX_WIDTH] = rdata1[i][63:PATCH_SIZE*DATA_WIDTH];
assign rleaf0[i*64+:64] = rdata0[i];
end
endgenerate
endmodule
| 6.772541 |
module ResetMux (
select,
rst0,
rst1,
out_rst
);
input select;
input rst0;
input rst1;
output wire out_rst;
assign out_rst = (select ? rst1 : rst0);
endmodule
| 6.767128 |
module sky130_sram_1kbyte_1rw1r_32x256_8 (
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
parameter DELAY = 3;
parameter VERBOSE = 0;
parameter T_HOLD = 1;
input clk0;
input csb0;
input web0;
input [NUM_WMASKS - 1:0] wmask0;
input [ADDR_WIDTH - 1:0] addr0;
input [DATA_WIDTH - 1:0] din0;
output reg [DATA_WIDTH - 1:0] dout0;
input clk1;
input csb1;
input [ADDR_WIDTH - 1:0] addr1;
output reg [DATA_WIDTH - 1:0] dout1;
reg csb0_reg;
reg web0_reg;
reg [NUM_WMASKS - 1:0] wmask0_reg;
reg [ADDR_WIDTH - 1:0] addr0_reg;
reg [DATA_WIDTH - 1:0] din0_reg;
reg [DATA_WIDTH - 1:0] mem[0:RAM_DEPTH - 1];
always @(posedge clk0) begin
csb0_reg = csb0;
web0_reg = web0;
wmask0_reg = wmask0;
addr0_reg = addr0;
din0_reg = din0;
#(T_HOLD) dout0 = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if ((!csb0_reg && web0_reg) && VERBOSE)
$display($time, " Reading %m addr0=%b dout0=%b", addr0_reg, mem[addr0_reg]);
if ((!csb0_reg && !web0_reg) && VERBOSE)
$display($time, " Writing %m addr0=%b din0=%b wmask0=%b", addr0_reg, din0_reg, wmask0_reg);
end
reg csb1_reg;
reg [ADDR_WIDTH - 1:0] addr1_reg;
always @(posedge clk1) begin
csb1_reg = csb1;
addr1_reg = addr1;
if (((!csb0 && !web0) && !csb1) && (addr0 == addr1))
$display(
$time, " WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!", addr0, addr1
);
#(T_HOLD) dout1 = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if (!csb1_reg && VERBOSE)
$display($time, " Reading %m addr1=%b dout1=%b", addr1_reg, mem[addr1_reg]);
end
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg && !web0_reg) begin
if (wmask0_reg[0]) mem[addr0_reg][7:0] = din0_reg[7:0];
if (wmask0_reg[1]) mem[addr0_reg][15:8] = din0_reg[15:8];
if (wmask0_reg[2]) mem[addr0_reg][23:16] = din0_reg[23:16];
if (wmask0_reg[3]) mem[addr0_reg][31:24] = din0_reg[31:24];
end
end
always @(negedge clk0) begin : MEM_READ0
if (!csb0_reg && web0_reg) dout0 <= #(DELAY) mem[addr0_reg];
end
always @(negedge clk1) begin : MEM_READ1
if (!csb1_reg) dout1 <= #(DELAY) mem[addr1_reg];
end
endmodule
| 7.095527 |
module SyncBit (
sCLK,
sRST,
dCLK,
sEN,
sD_IN,
dD_OUT
);
parameter init = 1'b0;
input sCLK;
input sRST;
input sEN;
input sD_IN;
input dCLK;
output wire dD_OUT;
reg sSyncReg;
reg dSyncReg1;
reg dSyncReg2;
assign dD_OUT = dSyncReg2;
always @(posedge sCLK or negedge sRST)
if (sRST == 1'b0) sSyncReg <= init;
else if (sEN) sSyncReg <= (sD_IN == 1'b1 ? 1'b1 : 1'b0);
always @(posedge dCLK or negedge sRST)
if (sRST == 1'b0) begin
dSyncReg1 <= init;
dSyncReg2 <= init;
end else begin
dSyncReg1 <= sSyncReg;
dSyncReg2 <= dSyncReg1;
end
initial begin
sSyncReg = init;
dSyncReg1 = init;
dSyncReg2 = init;
end
endmodule
| 6.836602 |
module ann_mux_3to1 (
//Input
input [ 1:0] iSel,
input [31:0] iFeature,
input [31:0] iOutput_Logsig,
//Output
output [31:0] oData_out
);
assign oData_out = (iSel == 2'b0) ? 32'b1 : (iSel == 2'b1) ? iFeature : iOutput_Logsig;
endmodule
| 7.884962 |
module ann_threshold (
//Input
input iClk,
input iReset_n,
input iInput_ready,
input [31:0] iOutput_Logsig,
//Output
output reg oFlag,
output reg oOutput_ready,
output reg [31:0] oData_out
);
parameter THRESHOLD = 32'h800000;
//=================================REGISTERS=====================================
reg [31:0] data_in_reg;
reg input_ready_reg;
//===================================WIRES=======================================
wire flag;
wire [31:0] data_out;
//===============================================================================
assign flag = data_in_reg >= THRESHOLD;
assign data_out = (flag) ? data_in_reg : 32'h11EB85;
//===============================================================================
always @(posedge iClk)
if (~iReset_n) begin
oFlag <= 1'b0;
oOutput_ready <= 1'b0;
oData_out <= 32'b0;
data_in_reg <= 32'b0;
input_ready_reg <= 1'b0;
end else begin
input_ready_reg <= iInput_ready;
if (iInput_ready) data_in_reg <= iOutput_Logsig;
else if (input_ready_reg) begin
oFlag <= ~flag;
oData_out <= data_out;
oOutput_ready <= 1'b1;
end else begin
oOutput_ready <= 1'b0;
data_in_reg <= 32'b0;
end
end
endmodule
| 6.993755 |
module anode_sel (
input CLK100MHZ,
input [2:0] rr,
output reg [7:0] AN
);
//Assign which digit to refresh with what segment mapping needed
always @(posedge CLK100MHZ) begin
case (rr)
//0 shows what 7-seg disp is beign affected
3'b000: AN = 8'b01111111;
3'b001: AN = 8'b10111111;
3'b010: AN = 8'b11011111;
3'b011: AN = 8'b11101111;
3'b100: AN = 8'b11110111;
3'b101: AN = 8'b11111011;
3'b110: AN = 8'b11111101;
3'b111: AN = 8'b11111110;
endcase
end
endmodule
| 8.78009 |
module top_module (
input in1,
input in2,
output out
);
assign out = in1 & (~in2);
endmodule
| 7.203305 |
module top_module (
input in1,
input in2,
output out
);
assign out = ~in2 & in1;
endmodule
| 7.203305 |
module ano_test_shift_register_32 ();
//测试移位功能
wire [31:0] data_bus_out;
wire [31:0] data_bus;
reg [31:0] data_bus_in = 32'b10110010111000101111000010111110;
reg en = 1, clear = 0, io = 1, clk = 0, is_left = 1'bx;
wire carry_bit;
shift_register_32 sr32 (
data_bus,
en,
clear,
io,
clk,
is_left,
carry_bit
);
assign data_bus = (io) ? data_bus_in : 32'bz;
assign data_bus_out = !(io) ? data_bus : 32'bz;
initial
fork
#10 io = 0;
#10 is_left = 1;
#330 is_left = 0;
forever #5 clk = ~clk;
join
endmodule
| 6.927664 |
module ansiport_example ();
reg read, write = 0;
reg [7:0] data_in = 0;
reg [3:0] addr = 0;
wire [7:0] data_v95, data_notype, data_ansi;
initial begin
$monitor("%g rd=%b wr=%b addr=%b data_in=%h data_v95=%h data_notype=%h data_ansi=%h", $time,
read, write, addr, data_in, data_v95, data_notype, data_ansi);
#1 read = 0; // why only for read ?
#3
repeat (16) begin
data_in = $random;
write = 1;
#1 addr = addr + 1;
end
write = 0;
addr = 0;
#3
repeat (16) begin
read = 1;
#1 addr = addr + 1;
end
read = 0;
#1 $finish;
end
memory_v95 U (
read,
write,
data_in,
addr,
data_v95
);
memory_ansi_notype W (
read,
write,
data_in,
addr,
data_notype
);
memory_ansi V (
read,
write,
data_in,
addr,
data_ansi
);
endmodule
| 6.764758 |
module memory_v95 (
read,
write,
data_in,
addr,
data_out
);
input read;
input write;
input [7:0] data_in;
input [3:0] addr;
output [7:0] data_out;
reg [7:0] data_out;
reg [7:0] mem[0:15];
always @(*) begin
if (write) mem[addr] = data_in;
end
always @(read, addr) begin
if (read) data_out = mem[addr];
end
endmodule
| 6.804368 |
module memory_ansi_notype (
input read,
input write,
input [7:0] data_in,
input [3:0] addr,
output [7:0] data_out
);
reg [7:0] mem[0:15];
always @(*) begin
if (write) mem[addr] = data_in;
end
assign data_out = (read) ? mem[addr] : 0;
endmodule
| 7.509735 |
module Top (
input [4:0] a,
input [4:0] b,
input [4:0] c,
output [8:0] addition
);
wire [8:0] sum;
wire [7:0] cout;
carrysave_3is2stage instantiated (
a[4:0],
b[4:0],
c[4:0],
sum[8:0],
cout[7:0]
);
assign addition[8:0] = sum[8:0] + ({cout[7:0], 1'b0});
endmodule
| 6.64497 |
module carrysave_3is2stage (
input [4:0] inp1,
input [4:0] inp2,
input [4:0] inp3,
output [8:0] sump,
output [7:0] coutp
);
wire [8:0] inp1_9bit;
wire [8:0] inp2_9bit;
wire [8:0] inp3_9bit;
assign inp1_9bit[8:0] = {inp1[4], inp1[4], inp1[4], inp1[4], inp1[4:0]};
assign inp2_9bit[8:0] = {inp2[4], inp2[4], inp2[4:0], 1'b0, 1'b0};
assign inp3_9bit[8:0] = {1'b0, inp3[4:0], 1'b0, 1'b0, 1'b0};
FullAdder FA0 (
inp1_9bit[0],
inp2_9bit[0],
inp3_9bit[0],
sump[0],
coutp[0]
);
FullAdder FA1 (
inp1_9bit[1],
inp2_9bit[1],
inp3_9bit[1],
sump[1],
coutp[1]
);
FullAdder FA2 (
inp1_9bit[2],
inp2_9bit[2],
inp3_9bit[2],
sump[2],
coutp[2]
);
FullAdder FA3 (
inp1_9bit[3],
inp2_9bit[3],
inp3_9bit[3],
sump[3],
coutp[3]
);
FullAdder FA4 (
inp1_9bit[4],
inp2_9bit[4],
inp3_9bit[4],
sump[4],
coutp[4]
);
FullAdder FA5 (
inp1_9bit[5],
inp2_9bit[5],
inp3_9bit[5],
sump[5],
coutp[5]
);
FullAdder FA6 (
inp1_9bit[6],
inp2_9bit[6],
inp3_9bit[6],
sump[6],
coutp[6]
);
FullAdder FA7 (
inp1_9bit[7],
inp2_9bit[7],
inp3_9bit[7],
sump[7],
coutp[7]
);
FullAdder FA8 (
inp1_9bit[8],
inp2_9bit[8],
inp3_9bit[8],
sump[8],
);
endmodule
| 6.500131 |
module FullAdder (
input in1,
input in2,
input cin,
output sum,
output cout
);
assign sum = (in1 ^ in2) ^ cin;
assign cout = (in1 & in2) | (cin & (in1 ^ in2));
endmodule
| 7.610141 |
module Top_tb;
reg [4:0] a;
reg [4:0] b;
reg [4:0] c;
wire [8:0] addition;
Top testbench_adddition (
a[4:0],
b[4:0],
c[4:0],
addition[8:0]
);
initial begin
$monitor($time, "a = %b \t b = %b \t c = %b \t addition = %b \n", a[4:0], b[4:0], c[4:0],
addition[8:0]);
#10 a[4:0] = 10000;
b[4:0] = 10000;
c[4:0] = 01111;
#50;
a[4:0] = 10010;
b[4:0] = 10100;
c[4:0] = 11111;
#50;
a[4:0] = 10101;
b[4:0] = 10001;
c[4:0] = 01011;
#50;
a[4:0] = 10110;
b[4:0] = 11100;
c[4:0] = 11011;
#50;
a[4:0] = 00000;
b[4:0] = 00000;
c[4:0] = 00000;
#50;
a[4:0] = 11111;
b[4:0] = 11111;
c[4:0] = 11111;
#50;
a[4:0] = 10000;
b[4:0] = 1000;
c[4:0] = 10011;
#50;
a[4:0] = 00111;
b[4:0] = 11100;
c[4:0] = 11111;
#50;
a[4:0] = 01100;
b[4:0] = 01100;
c[4:0] = 01111;
#50;
a[4:0] = 00111;
b[4:0] = 00101;
c[4:0] = 01001;
#50;
a[4:0] = 10101;
b[4:0] = 10101;
c[4:0] = 11010;
#50;
a[4:0] = 00001;
b[4:0] = 00001;
c[4:0] = 00001;
#50;
a[4:0] = 00100;
b[4:0] = 00100;
c[4:0] = 01100;
#50;
a[4:0] = 11011;
b[4:0] = 11011;
c[4:0] = 11011;
#50;
a[4:0] = 01110;
b[4:0] = 00001;
c[4:0] = 00101;
#50;
a[4:0] = 00111;
b[4:0] = 10100;
c[4:0] = 01011;
#50;
end
endmodule
| 6.693003 |
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