code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module apb2per #(
parameter PER_ADDR_WIDTH = 32,
parameter APB_ADDR_WIDTH = 32
) (
clk_i,
rst_ni,
PADDR,
PWDATA,
PWRITE,
PSEL,
PENABLE,
PRDATA,
PREADY,
PSLVERR,
per_master_req_o,
per_master_add_o,
per_master_we_o,
per_master_wdata_o,
per_master_be_o,
... | 7.923519 |
module apb2reg (
input clk,
input reset_n,
// APB Master
input psel,
input [15:2] paddr,
input pwrite,
input [31:0] pwdata,
input penable,
output [31:0] prdata,
output pready,
// reg... | 7.214433 |
module APB_SLAVE (
// APB SLAVE PORT INTERFACE
input PCLK,
input PRESETn,
input [`APB_ADDR_WIDTH-1:0] PADDR,
input PWRITE,
input PSEL,
input PENABLE,
... | 8.643298 |
module APB_SPI_top (
// APB SLAVE PORT INTERFACE
input PCLK,
input PRESETn,
input [`APB_ADDR_WIDTH-1:0] PADDR,
input PWRITE,
input PSEL,
input PENABLE,
input [`APB_DATA_W... | 8.5891 |
module to test apb2 slaves
//
// This takes standard APB signals and allows
// communication to a slave via the tasks
// write and read.
module apb2_master_tester #(
parameter ADDR_BITS = 4,
parameter DATA_BITS = 8
)
(
input wire PCLK,
input wire [ADDR_BITS - 1:0] PADDR,
... | 7.372718 |
module to test apb2 slaves
//
// This takes standard APB signals and allows
// communication to a slave via the tasks
// write and read.
module apb2_slave_tester #(
parameter ADDR_BITS = 4,
parameter DATA_BITS = 8
)
(
input wire PCLK,
output reg [ADDR_BITS - 1:0] PADDR,
... | 7.372718 |
module APBSlave_AD7609 (
// APB Slave Interface
input [31:0] PADDR,
input PSEL,
input PENABLE,
input PWRITE,
output [31:0] PRDATA,
input [31:0] PWDATA,
output PREADY,
// output PSLVERRS,
//
input [15:0] value1,
input [15:0] value2,
input [15:0] val... | 6.737949 |
module apb3_slave #(
// user parameter starts here
//
parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 31,
parameter NUM_REG = 4
) (
// user logic starts here
output [1:0] apb3LED,
output apb3Interrupt,
//
input clk,
input resetn,
input [ADDR_WIDTH-1:0] PADDR... | 7.546385 |
module APBGPIO (
//APB Inputs
input wire PCLK,
input wire PRESETn,
input wire PWRITE,
input wire [31:0] PWDATA,
input wire [31:0] PADDR,
input wire PENABLE,
input PSEL,
//APB Outputs
output wire PREADY,
output wire [31:0] PRDATA,
// GPIO Ports
input wire [15:0] GP... | 7.16019 |
module to I2C Core
////
////
////
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbi2c/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// apbi2c_spec IP core specification document.
////
////
////
//// To Do: Things are right here ... | 8.069831 |
module fifo #(
parameter integer DWIDTH = 32,
parameter integer AWIDTH = 4
) (
input clock,
reset,
wr_en,
rd_en,
input [DWIDTH-1:0] data_in,
output f_full,
f_empty,
output [DWIDTH-1:0] data_out
);
reg [DWIDTH-1:0] mem[0:2**AWIDTH-1];
//parameter integer DEPTH = 1 << AWIDTH;... | 8.01468 |
module i2c (
//APB PORTS
input PCLK,
input PRESETn,
input [31:0] PADDR,
input [31:0] PWDATA,
input PWRITE,
input PSELx,
input PENABLE,
output PREADY,
output PSLVERR,
output INT_RX,
output INT_TX,
output [31:0] PRDATA,
//I2C OUTPUT
output SDA_ENABLE,
output... | 6.662695 |
module QueueModuleled ( // @[:@53.2]
input clock, // @[:@54.4]
input reset, // @[:@55.4]
output io_i_ready, // @[:@56.4]
input io_i_valid, // @[:@56.4]
input [23:0] io_i_bits, // @[:@56.4]
input io_o_ready, // @[:@56.4]
output ... | 7.583162 |
module apbmaster (
input pclk,
input presetn,
input [1:0]add,//00-x,01-read,10-x,11-write
output reg psel,
output reg penable,
output [7:0] paddr,
output pwrite,
output [7:0]pwdata,
input [7:0]prdata,
input pready
);
reg [7:0] cur_pwrite, nex_pwrite, cur_prda... | 7.946033 |
module APBSlaveLED (
// APB Slave Interface
input [31:0] PADDR,
input PSEL,
input PENABLE,
input PWRITE,
output [31:0] PRDATA,
input [31:0] PWDATA,
output PREADY,
// output PSLVERRS,
//
input clk_i,
input rst_n_i,
input key_i,
output reg led0_o,
output re... | 6.576075 |
module aes_core (
//OUTPUTS
output [31:0] col_out,
output [31:0] key_out,
output [31:0] iv_out,
output end_aes,
//INPUTS
input [31:0] bus_in,
input [3:0] iv_en,
input [3:0] iv_sel_rd,
input [3:0] key_en,
input [1:0] key_sel_rd,
input [1:0] data_type,
input [1:0] addr,... | 7.695875 |
module data_swap #(
parameter WIDTH = 32
) (
//OUTPUTS
output [WIDTH - 1:0] data_swap,
//INPUTS
input [WIDTH - 1:0] data_in,
input [1:0] swap_type
);
//=====================================================================================
// Swap Types
//===================================... | 6.690797 |
module key_expander (
// OUTPUTS
output [127:0] key_out,
output [31:0] g_in,
// INPUTS
input [31:0] g_out,
input [127:0] key_in,
input [3:0] round,
input add_w_out,
input enc_dec
);
localparam integer KEY_WIDTH = 32;
localparam integer KEY_NUM = 4;
localparam integer WORD = 8;... | 8.294333 |
module sBox #(
parameter SBOX_NUM = 4
) (
//OUTPUTS
output [8*SBOX_NUM - 1:0] sbox_out_enc,
output [8*SBOX_NUM - 1:0] sbox_out_dec,
//INPUTS
input [8*SBOX_NUM - 1:0] sbox_in,
input enc_dec,
input clk
);
sBox_8 SBOX[SBOX_NUM - 1:0] (
.sbox_out_enc(sbox_out_enc),
.sbox_out_de... | 6.582372 |
module shift_rows (
//OUTPUTS
output [127 : 0] data_out_enc, // Result after Shift Rows operation - enc
output [127 : 0] data_out_dec, // Result after Shift Rows operation - dec
//INPUTS
input [127 : 0] data_in // Input Bus
);
localparam integer BUS_WIDTH = 128; // Bus Width
localpar... | 6.667518 |
module QueueModule_uart ( // @[:@53.2]
input clock, // @[:@54.4]
input reset, // @[:@55.4]
output io_i_ready, // @[:@56.4]
input io_i_valid, // @[:@56.4]
input [11:0] io_i_bits, // @[:@56.4]
input io_o_ready, // @[:@56.4]
output ... | 6.970289 |
module apb_burst_regs (
input wire clk,
input wire rst_n,
// APB Port
input wire apbs_psel,
input wire apbs_penable,
input wire apbs_pwrite,
input wire [15:0] apbs_paddr,
input wire [31:0] apbs_pwdata,
output wire [31:0] apbs_prdata,
output wire apbs_pready,
output wire apbs... | 8.774598 |
module apb_decode #(
parameter PORTS = 3, // Output ports
BOTREGION = 1024, // Address first port
REGION = 3072, // address locations/port
TOP_DEFAULT = 0 // All unadressed accesses go to top p_sel bus
) (
// APB input (slave) ... | 8.571854 |
module apb_edgeirq (
// system
input reset_n,
input enable, // clock gating
// APB
input pclk,
input [ 2:0] paddr, // ls 2 bits are unused
input pwrite,
input psel,
input penable,
input [31:0] pwdata,
output re... | 7.482032 |
module apb_edgeirq_test;
`define ENBL_REG 16'h0
`define STAT_REG 16'h4
localparam CLK_PERIOD = 100;
// system
reg reset_n;
reg enable; // clock gating
// APB
wire pclk;
wire [15:0] paddr; // ls 2 bits are unused
wire pwrite;
wire pse... | 6.704237 |
module apb_event_unit #(
parameter APB_ADDR_WIDTH = 12 //APB slaves are 4KB by default
) (
clk_i,
HCLK,
HRESETn,
PADDR,
PWDATA,
PWRITE,
PSEL,
PENABLE,
PRDATA,
PREADY,
PSLVERR,
irq_i,
event_i,
irq_o,
fetch_enable_i,
fetch_enable_o,
clk_gate_core_o,... | 8.483797 |
module apb_fastdecode #(
parameter PORTS = 2, // Output ports
MS_SLVADR = 9, // Sets size of region
// 9=1K, 10=2K etc.
TOP_DEFAULT = 0 // Highest bus is default (no errors)
) (
// APB input (slave)
input [31:0] s_paddr, ... | 8.826312 |
module apb_fc (
// CPU Interface Input (APB bus interface)
input wire PCLK, // APB clock
input wire PRESETB, // APB asynchronous reset (0: reset, 1: normal)
input wire [31:0] PADDR, // APB address
input wire PSEL, // APB select
input wire ... | 7.688624 |
module apb_fifo (
// system
input reset_n,
input enable, // clock gating
// APB
input pclk,
input [ 3:0] paddr, // ls 2 bits are unused
input pwrite,
input psel,
input penable,
input [31:0] pwdata,
output reg [... | 7.166059 |
module apb_fifo_test;
`define DATA_REG 16'h0
`define STAT_REG 16'h4
`define SR_EMPTY 32'h00000001
`define SR_FULL 32'h00000002
localparam CLK_PERIOD = 100;
// system
reg reset_n;
reg enable; // clock gating
// APB
wire pclk;
wire [15:0] paddr; // ls 2 bit... | 7.372279 |
module APB_FSM_CONT (
HCLK,
HRESETn,
VALID,
TSELx,
TPADDR1,
TPADDR2,
TPWDATA1,
TPWDATA2,
HWRITEreg,
PRDATA,
HWRITE,
PENABLE,
PSELx,
PADDR,
PWDATA,
HRDATA,
PWRITE,
HRESP,
HREADY_OUT
);
input HCLK, //reference signal HCLK
HRESETn, //res... | 6.689181 |
module apb_i2c #(
parameter APB_ADDR_WIDTH = 12 //APB slaves are 4KB by default
) (
HCLK,
HRESETn,
PADDR,
PWDATA,
PWRITE,
PSEL,
PENABLE,
PRDATA,
PREADY,
PSLVERR,
interrupt_o,
scl_pad_i,
scl_pad_o,
scl_padoen_o,
sda_pad_i,
sda_pad_o,
sda_padoen_o
)... | 8.863317 |
module apb_i2c_ic ( ////top module
input wire PCLK,
input wire PRESETn,
input wire PSEL,
input wire PENABLE,
input wire PWrite,
input wire [31:0] PADDR,
input wire [31:0] PWDATA,
output [31:0] PRDATA,
output PREADY,
output PSLVERR,
inout i2c_scl,
inout i2c_sda
);
... | 8.060032 |
module APB_I2C_SLAVE (
// APB SLAVE PORT INTERFACE
input PCLK,
input PRESETn,
input [`APB_ADDR_WIDTH-1:0] PADDR,
input PWRITE,
input PSEL,
input ... | 9.352512 |
module addr_dec #(
parameter BUS_WIDTH = 16,
parameter SLAVE_PORTS = 10
) (
input [ BUS_WIDTH-1:0] addr,
output [ SLAVE_PORTS-1:0] sel,
output reg [`clog2(SLAVE_PORTS)-1:0] seli
);
// binary bit output
// GPIO0
assign sel[`APB_PSELX_GPIO0] = ((addr >= `DEF_MMU_GPIO0_... | 7.175933 |
module apb_interface (
pwrite,
penable,
psel,
paddr,
pwdata,
pwrite_out,
penable_out,
psel_out,
paddr_out,
pwdata_out,
prdata
);
input pwrite, penable;
input [2:0] psel;
input [31:0] paddr, pwdata;
output pwrite_out, penable_out;
output [2:0] psel_out;
output [31... | 6.87051 |
module APB_INTERFACE (
input PCLK,
input [31:0] PADDR,
input [31:0] PWDATA,
input PRESETn,
input PWRITE,
input [1:0] PSEL,
input [2:0] PPROT,
output reg [31:0] PRDATA,
output reg PREADY,
output reg PSLVERR,
output [1:0] REGSEL,
input [7:0] BUSRDATA,
output clk,
ou... | 8.75567 |
module APB_Keyboard (
input wire clk,
rst_n,
input wire [3:0] col_in,
output wire [3:0] row,
output wire [31:0] PRDATA,
output wire KeyboardINT
);
wire [15:0] keyn;
wire [15:0] key;
wire [3:0] col_out;
wire [1:0] hi;
wire row_rdy;
reg [15:0] KeyINT;
KeyToCol KeyToCol (
.clk ... | 8.155701 |
module apb_levirq (
// system
input reset_n,
input enable, // clock gating
// APB
input pclk,
input [ 2:0] paddr, // ls 2 bits are unused
input pwrite,
input psel,
input penable,
input [31:0] pwdata,
output reg... | 7.842738 |
module apb_levirq_test;
`define ENBL_REG 16'h0
`define STAT_REG 16'h4
localparam CLK_PERIOD = 100;
// system
reg reset_n;
reg enable; // clock gating
// APB
wire pclk;
wire [15:0] paddr; // ls 2 bits are unused
wire pwrite;
wire psel... | 7.032568 |
module APB_MasterModule_Tb ();
reg clk = 1;
reg rstN = 1;
reg [31:0] apb_addr;
reg apb_write;
reg apb_sel;
reg apb_en;
reg [31:0] apb_wdata;
wire apb_ready;
wire pwm_out;
APB_PWM APB_PWM_Test (
.PCLK(clk),
.PRESETn(rstN),
... | 7.230037 |
module APB_MFGPIO (
// --------------------------
// Input pins: AHB signals //
// --------------------------
// Select
input PSEL,
// Address and control
input [31:0] PADDR,
input PWRITE,
// Data in
input [31:0] PWDATA,
// Reset and clock
input HRESETn,
input HCLK,
... | 6.869115 |
module apb_mock_uart #(
parameter APB_ADDR_WIDTH = 12 //APB slaves are 4KB by default
) (
CLK,
RSTN,
PADDR,
PWDATA,
PWRITE,
PSEL,
PENABLE,
PRDATA,
PREADY,
PSLVERR,
INT,
OUT1N,
OUT2N,
RTSN,
DTRN,
CTSN,
DSRN,
DCDN,
RIN,
SIN,
SOUT
);
... | 8.288888 |
module apb_mux (
// -------------
// Input pins //
// -------------
// Clock and reset
input HCLK,
input HRESETn,
// Slave datas
input [31:0] PRDATAx0,
input [31:0] PRDATAx1,
input [31:0] PRDATAx2,
input [31:0] PRDATAx3,
input [31:0] PRDATAx4,
input [31:0] PRDATAx5,
... | 7.22852 |
module apb_mux2 (
clk,
rst_n,
apb_ack_cpu,
apb_rw_cpu,
apb_psel_cpu,
apb_enab_cpu,
apb_addr_cpu,
apb_datai_cpu,
apb_datao_cpu,
apb_high_24b_rd,
apb_high_24b_wr,
apb_word_trans_cpu,
apb_ready_dma,
apb_rw_dma,
apb_psel_dma,
apb_enab_dma,
apb_addr_dma,
... | 6.690016 |
module arb_2_1 (
clk,
rst_n,
valid0,
valid1,
dma_grant
);
input clk;
input rst_n;
input valid0;
input valid1;
output dma_grant;
reg dma_grant;
always @(posedge clk)
if (~rst_n) dma_grant <= 1'b0;
else if (valid0 && ~valid1) dma_grant <= 1'b0;
else if (valid1 && ~valid0) dm... | 7.253966 |
module apb_node #(
parameter NB_MASTER = 8,
parameter APB_DATA_WIDTH = 32,
parameter APB_ADDR_WIDTH = 32
) (
penable_i,
pwrite_i,
paddr_i,
pwdata_i,
prdata_o,
pready_o,
pslverr_o,
penable_o,
pwrite_o,
paddr_o,
psel_o,
pwdata_o,
prdata_i,
pready_i,
... | 7.415225 |
module apb_node_wrap (
clk_i,
rst_ni,
apb_slave,
apb_masters,
start_addr_i,
end_addr_i
);
parameter NB_MASTER = 8;
parameter APB_DATA_WIDTH = 32;
parameter APB_ADDR_WIDTH = 32;
input wire clk_i;
input wire rst_ni;
input apb_slave;
input [NB_MASTER - 1:0] apb_masters;
input wire [... | 7.357296 |
module apb_pool (
// CPU Interface Input (APB bus interface)
input wire PCLK, // APB clock
input wire PRESETB, // APB asynchronous reset (0: reset, 1: normal)
input wire [31:0] PADDR, // APB address
input wire PSEL, // APB select
input w... | 7.009961 |
module APB_Protcol (
input pclk,
penable,
pwrite,
transfer,
Reset,
input [4:0] write_paddr,
apb_read_paddr,
input [31:0] write_data,
// 1 gpio 2 uart 0 idle
input [1:0] Psel,
output [31:0] apb_read_data_out,
input rx,
output PSLVERR,
// Know The Type of Error
... | 7.093577 |
module APB_PSMCREG (
input PCLK,
input PSEL,
input PENABLE,
input PWRITE,
input [7:0] PADDR,
input [31:0] PWDATA,
output [31:0] PRDATA,
output reg PREADY,
output reg PSLVERR,
input RESETN,
output MOSI,
input MISO,
output MCS,
output MCLKO,
output reg [31:0] p... | 6.775748 |
module apb_pulse (
// system
input reset_n,
input enable, // clock gating
// APB
input pclk,
input [ 3:0] paddr, // ls 2 bits are unused
input pwrite,
input psel,
input penable,
input [31:0] pwdata,
output [31:0] prdata,
output ... | 8.422322 |
module apb_pulse_test;
localparam CLK_PERIOD = 100;
// system
reg reset_n;
reg enable; // clock gating
// APB
wire pclk;
wire [15:0] paddr; // ls 2 bits are unused
wire pwrite;
wire psel;
wire penable;
wire [31:0] pwdata;... | 7.310459 |
module APB_PWM (
// Peripheral Signals
input PCLK,
input PRESETn,
// APB Bridge Signals
input [31:0] PADDR,
input PWRITE,
input PSEL,
input PENABLE,
input [31:0] PWDATA,
// APB Slave Signals
output reg PREADY,
output reg PWM_OUT
);
// State Mech... | 7.595131 |
module APB_PWM32 (
// APB Interface
// clock and reset
input wire PCLK,
//input wire PCLKG, // Gated clock
input wire PRESETn, // Reset
// input ports
input wire PSEL, // Select
input wire [19:2] PADDR, // Address
input wire PENABLE, // Transfer cont... | 6.577182 |
module apb_regs (
// system
input reset_n,
input enable, // clock gating
// APB
input pclk,
input [ 4:0] paddr, // ls 2 bits are unused
input pwrite,
input psel,
input penable,
input [31:0] pwdata,
output reg [... | 7.935939 |
module apb_regs1 (
// system
input reset_n,
input enable, // clock gating
// APB
input pclk,
input [ 3:0] paddr, // ls 2 bits are unused
input pwrite,
input psel,
input penable,
input [31:0] pwdata,
output reg ... | 7.605514 |
module apb_regs1_test;
localparam CLK_PERIOD = 100;
// system
reg reset_n;
reg enable; // clock gating
// APB
wire pclk;
wire [15:0] paddr; // ls 2 bits are unused
wire pwrite;
wire psel;
wire penable;
wire [31:0] pwdata;
wire [31:0] prdata;
... | 7.046327 |
module apb_regs_test;
localparam CLK_PERIOD = 100;
// system
reg reset_n;
reg enable; // clock gating
// APB
wire pclk;
wire [15:0] paddr; // ls 2 bits are unused
wire pwrite;
wire psel;
wire penable;
wire [31:0] pwdata;
wire [31:0] prdata;
... | 7.223267 |
module apb_regs_top #(
parameter APB_ADDR_WIDTH = 12, //APB slaves are 4KB by default
parameter APB_DATA_WIDTH = 32,
parameter N_REGION_MAX = 4,
parameter N_MASTER_PORT = 16,
parameter N_SLAVE_PORT = 16
) (
HCLK,
HRESETn,
PADDR_i,
PWDATA_i,
PWRITE_i,
PSEL_i,
PENABLE... | 8.72867 |
module !!!
----------------------------------------
Receive 8/10 bit (depending on mode)
Receive bit-by-bit according to baudrate
Receive & store
Control Path:
Data Path:
*/
module apb_rx
(
// Inputs:
input wire clk,
input wire rstn,
input wire sel,
input wire rx_en,
input wire mode,
input... | 7.687749 |
module !!!
----------------------------------------
Append received data bit into correct bit in rx_data
*/
module apb_rx_cp
(
// Inputs:
input wire rstn,
input wire sel,
input wire rx_en,
input wire mode,
input wire baud_clk,
input wire [9:0] bit_cnto,
// Outputs:
output reg [9:0] bit_cnt... | 7.687749 |
module !!!
----------------------------------------
Receive data bits
*/
module apb_rx_dp
(
// Inputs:
input wire rstn,
input wire sel,
input wire rx_en,
input wire rx_in,
input wire start_bit,
input wire end_bit,
input wire [9:0] bit_cnto,
input wire [9:0] data_bit,
// Outputs:
outp... | 7.687749 |
module apb_rx_tb ();
/* -------------------
Essential variables
------------------- */
localparam period = 5;
localparam cycle = period * 2;
reg clk;
reg rstn;
reg sel;
reg mode;
reg [19:0] baud;
/* ---------------
apb RX variables
--------------- */
// Inputs:
reg rx_en; // set DUTY & P... | 7.836132 |
module APB_SLAVE (
// APB SLAVE PORT INTERFACE
input PCLK,
input PRESETn,
input [`APB_ADDR_WIDTH-1:0] PADDR,
input PWRITE,
input PSEL,
input PENABLE,
... | 8.643298 |
module apb_slaveinterface (
input Pwrite,
input Penable,
input [ 2:0] Pselx,
input [31:0] Paddr,
input [31:0] Pwdata,
inout [31:0] Pdata, //Tristate Buffer for read and write bus
output [31:0] Paddr_out,
output [31:0] Pwdata_out,... | 7.528235 |
module PREFIX_mem (
PORTS
);
parameter MEM_WORDS = EXPR((2 ^ ADDR_BITS) / (DATA_BITS / 8));
parameter ADDR_LSB = LOG2(EXPR(DATA_BITS / 8));
input clk;
input reset;
revport GROUP_STUB_MEM;
reg [ DATA_BITS-1:0] Mem [MEM_WORDS-1:0... | 6.889752 |
module apb_slave_top #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input PCLK,
input PRESETn,
input [ ADDR_WIDTH-1:0] PADDR,
input PSEL,
input PENABLE,
input PWRITE,
input [ DATA_WIDTH-1:0] PWDATA,
inpu... | 7.870532 |
module apb_slave_wrapper #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8,
parameter SLV_ADDR_WIDTH = 8,
parameter SLV_CNT = 1
) (
input PCLK,
input PRESETn,
input [ ADDR_WIDTH-1:0] PADDR,
input [ SLV_CNT-1:0] PSELx,
input [ DATA_WIDTH-1:0] PWDATA,
input [DATA... | 7.588113 |
module apb_slv_iface (
// APB Interface signals
input wire pclk,
input wire preset_n,
input wire [31:0] paddr,
input wire psel,
input wire penable,
input wire pwrite,
input wire [31:0] pwdata,
output wire pready,
output wire [31:0]... | 8.651964 |
module APB_SPI (
input wire PCLK,
input wire PRESETn,
input wire PWRITE,
input wire [31:0] PWDATA,
input wire [31:0] PADDR,
input wire PENABLE,
input PSEL,
output wire PREADY,
output wire [31:0] PRDATA,
input wire MSI,
output wire MSO,
output wire SSn,
output wir... | 6.55338 |
module apb_spi_top #(
parameter ADDRWIDTH = 2'd3,
parameter DATAWIDTH = 4'd8
) (
pclk, // APB Clock
spi_clk, // SPI Clock
preset_n, // Active Low Reset
paddr, // Address
psel, // APB Select
penable, // APB Enable
pwrite, // Read Write signal 1-> Write 0->Read
pwdata, //... | 8.069158 |
module APB_SPI_WRAP (
// APB SLAVE PORT INTERFACE
input PCLK,
input PRESETn,
input [`APB_ADDR_WIDTH-1:0] PADDR,
input PWRITE,
input PSEL,
input P... | 7.180925 |
module apb_splitter #(
parameter W_ADDR = 16,
parameter W_DATA = 32,
parameter N_SLAVES = 2,
parameter ADDR_MAP = 32'h0000_4000,
parameter ADDR_MASK = 32'hc000_c000
) (
input wire [W_ADDR-1:0] apbs_paddr,
input wire apbs_psel,
input wire apbs_penable,
inp... | 6.948851 |
module apb_sram_inf (
clk,
rstn,
psel,
penable,
paddr,
pwrite,
pwdata,
pready,
prdata
);
parameter mem_depth = 1024;
parameter mem_width = 32;
parameter mem_bitw = 10;
parameter IDEL = 0;
parameter SETUP = 1;
parameter ENABLE = 2;
input wire clk;
input wire rstn;
... | 7.819726 |
module apb_timer #(
parameter APB_ADDR_WIDTH = 12, //APB slaves are 4KB by default
parameter TIMER_CNT = 2 // how many timers should be instantiated
) (
HCLK,
HRESETn,
PADDR,
PWDATA,
PWRITE,
PSEL,
PENABLE,
PRDATA,
PREADY,
PSLVERR,
irq_o
);
//parameter APB_ADDR_WID... | 8.234696 |
module APB_top (
input PCLK,
input PRESETn,
input Transfer,
input Wr_Rd,
input [4:0] Address,
input [31:0] write_data,
output [31:0] read_data
);
wire [4:0] PADDR;
wire [31:0] PWDATA, PRDATA;
wire PSELx, PENABLE, PWRITE, PREADY, PSLVERR;
APB_master Design_master (
Transfer,
... | 7.879159 |
module !!!
----------------------------------------
Transmit 8/10 bit (depending on mode)
Transmit bit-by-bit according to baudrate
Control Path:
Data Path:
*/
module apb_tx
(
// Input:
input wire clk,
input wire rstn, // active LOW to reset
input wire sel, // activate apb_tx module
input wire ... | 7.687749 |
module !!!
----------------------------------------
Determine data bit for transmission
*/
module apb_tx_cp
(
// Inputs:
input wire rstn, // active LOW to reset
input wire sel, // activate apb_tx module
input wire set, // set DUTY & PERIOD. enable PWM
input wire baud_clk, // signal to transmit... | 7.687749 |
module !!!
----------------------------------------
Transmit data bits
*/
module apb_tx_dp
(
// Inputs:
input wire rstn, // active LOW to reset
input wire tx_en, // signal to transmit data
input wire [9:0] bit_cnto, // # bit transmitted
input wire start_bit, // signal HIGH for tx start bit
inp... | 7.687749 |
module apb_uart_tx #(
parameter BUS_WIDTH = 16,
parameter CELL_DEPTH = 8,
parameter DATA_WIDTH = 8,
parameter ADDR_EXP = 5
) (
input clk,
input reset,
// APB Slave to master interface
input [ 1:0] S_PADDR,
// S_PADDR[0] = write port,
// S_PADDR[1] = read port
... | 8.367163 |
module start_bit_det (
clk,
n_rst,
serial_in,
start_bit_detected,
new_package_detected
);
input clk, n_rst, serial_in;
output start_bit_detected, new_package_detected;
wire start_bit_detected, old_sample, new_sample, sync_phase, n4;
assign new_package_detected = start_bit_detected;
DFFSR ... | 6.610416 |
module second_flex_counter (
clk,
n_rst,
clear,
shift_strobe,
rollover_val,
packet_done
);
input [3:0] rollover_val;
input clk, n_rst, clear, shift_strobe;
output packet_done;
flex_counter CORE (
.clk(clk),
.n_rst(n_rst),
.clear(clear),
.count_enable(shift_strob... | 7.910599 |
module sr_9bit (
clk,
n_rst,
serial_in,
shift_strobe,
packet_data
);
output [8:0] packet_data;
input clk, n_rst, serial_in, shift_strobe;
flex_stp_sr_NUM_BITS9_SHIFT_MSB0 CORE (
.clk(clk),
.n_rst(n_rst),
.shift_enable(shift_strobe),
.serial_in(serial_in),
.paral... | 7.17007 |
module apb_uart_rx (
clk,
n_rst,
serial_in,
psel,
paddr,
penable,
pwrite,
pwdata,
prdata,
pslverr
);
input [2:0] paddr;
input [7:0] pwdata;
output [7:0] prdata;
input clk, n_rst, serial_in, psel, penable, pwrite;
output pslverr;
wire data_ready, overrun_error, framing... | 7.619214 |
module APB_WDT32 (
// APB Interface
// clock and reset
input wire PCLK,
//input wire PCLKG, // Gated clock
input wire PRESETn, // Reset
// input ports
input wire PSEL, // Select
input wire [19:2] PADDR, // Address
input wire PENABLE, // Transfer cont... | 6.541544 |
module apb_wrtsetclr (
// system
input reset_n,
input enable, // clock gating
// APB
input pclk,
input [ 2:0] paddr, // ls 2 bits are unused
input pwrite,
input psel,
input penable,
input [31:0] pwdata,
output ... | 7.45127 |
module apb_wrtsetclr_test;
localparam CLK_PERIOD = 100;
// system
reg reset_n;
reg enable; // clock gating
// APB
wire pclk;
wire [15:0] paddr; // ls 2 bits are unused
wire pwrite;
wire psel;
wire penable;
wire [31:0] pwdata;
wire [31:0] prdat... | 7.45127 |
module apb_xactor #(
parameter ADDR_WIDTH = 32,
DATA_WIDTH = 32
) ( /*AUTOARG*/
// Outputs
psel,
penable,
paddr,
pwdata,
pwrite,
// Inputs
clk,
reset_n,
prdata,
pready,
pslverr
);
input clk;
input reset_n;
output reg psel;
output reg penable;
output re... | 8.215047 |
module apdtimer_all (
clk,
strobe_in,
delta_in,
reg_clk,
reg_addr,
reg_data,
reg_wr,
record_rdy,
record
);
input clk;
input [3:0] strobe_in;
input [3:0] delta_in;
input reg_clk;
input [15:0] reg_addr;
inout [31:0] reg_data;
input reg_wr;
output record_rdy;
output... | 6.930687 |
module APE_encode150_tabbFp_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 10;
parameter AWIDTH = 6;
parameter MEM_SIZE = 33;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH... | 6.529176 |
module APE_encode150_tabbFp (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd10;
parameter AddressRange = 32'd33;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input... | 6.529176 |
module apll_0002 (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multi... | 6.705623 |
module appcontrol (
input clk,
input rst,
input [9:0] mouse_x,
input [9:0] mouse_y,
input yes,
output reg machine_en,
output reg machine_reset,
input sound,
input sound_en
);
parameter stop = 4'd0;
parameter start = 4'd1;
parameter reset = 4'd2;
reg [3:0] state;
always @(po... | 6.753611 |
module for Terasic DE0 board
//
// Author.....: Niels A. Moseley
// Date.......: 26-1-2018
//
module apple1_de0_top #(
parameter BASIC_FILENAME = "../../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../../../roms/ram.he... | 8.4806 |
module apple1_top #(
parameter BASIC_FILENAME = "../../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../../../roms/ram.hex",
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENA... | 7.949466 |
module for Digilent Spartan 3E
// starter kit board
//
// Author.....: Niels A. Moseley
// Date.......: 11-2-2018
//
module apple1_s3e_starterkit_top #(
parameter BASIC_FILENAME = "../../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
parame... | 9.524504 |
module apple1_tb #(
parameter BASIC_FILENAME = "../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../roms/ram.hex",
parameter VRAM_FILENAME = "../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../roms/wozmon.hex"... | 7.544506 |
module apple1_top #(
parameter BASIC_FILENAME = "../../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../../../roms/ram.hex",
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENA... | 7.949466 |
module applei_verilator #(
parameter BASIC_FILENAME = "../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../../roms/ram.hex",
parameter VRAM_FILENAME = "../../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "... | 8.204769 |
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