code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module apb2per #(
parameter PER_ADDR_WIDTH = 32,
parameter APB_ADDR_WIDTH = 32
) (
clk_i,
rst_ni,
PADDR,
PWDATA,
PWRITE,
PSEL,
PENABLE,
PRDATA,
PREADY,
PSLVERR,
per_master_req_o,
per_master_add_o,
per_master_we_o,
per_master_wdata_o,
per_master_be_o,
per_master_gnt_i,
per_master_r_valid_i,
per_master_r_opc_i,
per_master_r_rdata_i
);
//parameter PER_ADDR_WIDTH = 32;
//parameter APB_ADDR_WIDTH = 32;
input wire clk_i;
input wire rst_ni;
input wire [APB_ADDR_WIDTH - 1:0] PADDR;
input wire [31:0] PWDATA;
input wire PWRITE;
input wire PSEL;
input wire PENABLE;
output wire [31:0] PRDATA;
output reg PREADY;
output wire PSLVERR;
output reg per_master_req_o;
output wire [PER_ADDR_WIDTH - 1:0] per_master_add_o;
output reg per_master_we_o;
output wire [31:0] per_master_wdata_o;
output wire [3:0] per_master_be_o;
input wire per_master_gnt_i;
input wire per_master_r_valid_i;
input wire per_master_r_opc_i;
input wire [31:0] per_master_r_rdata_i;
reg CS;
reg NS;
always @(posedge clk_i or negedge rst_ni)
if (rst_ni == 1'b0) CS <= 1'd0;
else CS <= NS;
always @(*) begin
per_master_we_o = 0;
per_master_req_o = 0;
PREADY = 0;
case (CS)
1'd0:
if ((PSEL == 1) && (PENABLE == 1)) begin
per_master_req_o = 1;
if (PWRITE == 1) per_master_we_o = 1'b1;
else per_master_we_o = 1'b0;
if (per_master_gnt_i == 1) begin
if (PWRITE == 1) begin
PREADY = 1;
NS = 1'd0;
end else begin
PREADY = 0;
NS = 1'd1;
end
end else begin
PREADY = 0;
NS = 1'd0;
end
end else begin
NS = 1'd0;
PREADY = 0;
end
1'd1:
if (per_master_r_valid_i == 1) begin
PREADY = 1;
NS = 1'd0;
end else begin
PREADY = 0;
NS = 1'd1;
end
default: NS = 1'd0;
endcase
end
assign PRDATA = per_master_r_rdata_i;
assign PSLVERR = 1'sb0;
assign per_master_add_o = PADDR;
assign per_master_wdata_o = PWDATA;
assign per_master_be_o = 1'sb1;
endmodule
| 7.923519 |
module apb2reg (
input clk,
input reset_n,
// APB Master
input psel,
input [15:2] paddr,
input pwrite,
input [31:0] pwdata,
input penable,
output [31:0] prdata,
output pready,
// reg_ctrl
output wire [31:0] reg_write_data,
output wire [15:0] reg_addr,
input wire [31:0] reg_read_data,
output wire reg_write,
output reg_read,
output reg_idle
);
reg reg_wr_en;
reg reg_re_en;
reg reg_wr_en_dly;
reg reg_re_en_dly;
reg reg_idle_reg;
reg [31:0] reg_read_data_dly;
reg [31:0] reg_write_data_dly;
reg [15:0] reg_addr_dly;
always @(posedge clk) begin : proc_reg_write_data_dly
if (~reset_n) begin
reg_write_data_dly <= 0;
end else if (psel) begin
reg_write_data_dly <= pwdata;
end
end
always @(posedge clk) begin : proc_reg_addr_dly
if (~reset_n) begin
reg_addr_dly <= 0;
end else if (psel) begin
reg_addr_dly <= {paddr, 2'b0};
end
end
always @(posedge clk) begin : proc_reg_wr_en
if (~reset_n) begin
reg_wr_en <= 0;
end else if (reg_wr_en) begin
reg_wr_en <= 1'b0;
end else if (psel & pwrite & ~penable) begin
reg_wr_en <= 1'b1;
end
end
always @(posedge clk) begin : proc_reg_re_en
if (~reset_n) begin
reg_re_en <= 0;
end else if (reg_re_en) begin
reg_re_en <= 1'b0;
end else if (psel & ~pwrite & ~penable) begin
reg_re_en <= 1'b1;
end
end
always @(posedge clk) begin : proc_reg_re_en_dly
if (~reset_n) begin
reg_re_en_dly <= 0;
end else begin
reg_re_en_dly <= reg_re_en;
end
end
always @(posedge clk) begin : proc_reg_wr_en_dly
if (~reset_n) begin
reg_wr_en_dly <= 0;
end else begin
reg_wr_en_dly <= reg_wr_en;
end
end
always @(posedge clk) begin : proc_reg_read_data_dly
if (~reset_n) begin
reg_read_data_dly <= 0;
end else begin
reg_read_data_dly <= reg_read_data;
end
end
always @(posedge clk) begin : proc_reg_idle_reg
if (~reset_n) begin
reg_idle_reg <= 1'b1;
end else begin
reg_idle_reg <= pready;
end
end
assign reg_write = reg_wr_en;
assign reg_read = reg_re_en;
assign reg_addr = reg_addr_dly;
assign reg_write_data = reg_write_data_dly;
assign reg_idle = reg_idle_reg;
assign prdata = reg_read_data_dly;
assign pready = ~penable | (~reg_re_en & ~reg_re_en_dly) | (~reg_wr_en & reg_wr_en_dly);
endmodule
| 7.214433 |
module APB_SLAVE (
// APB SLAVE PORT INTERFACE
input PCLK,
input PRESETn,
input [`APB_ADDR_WIDTH-1:0] PADDR,
input PWRITE,
input PSEL,
input PENABLE,
input [`APB_DATA_WIDTH-1:0] PWDATA,
output reg [`APB_DATA_WIDTH-1:0] PRDATA,
output reg PREADY,
input TrFr,
// SPI INTERFACE
output reg [ `SPI_REG_WIDTH-1:0] SPI_CR_1,
output reg [ `SPI_REG_WIDTH-1:0] SPI_CR_2,
output reg [ `SPI_REG_WIDTH-1:0] SPI_BR_R,
output reg [ `SPI_REG_WIDTH-1:0] SPI_ST_R,
output reg [ `SPI_REG_WIDTH-1:0] SPI_DATA_Reg_1,
output reg [ `SPI_REG_WIDTH-1:0] SPI_DATA_Reg_2,
output reg [ `SPI_REG_WIDTH-1:0] SPI_DATA_Reg_3,
output reg [ `SPI_REG_WIDTH-1:0] SPI_DATA_Reg_4
);
/////////////////////////////////////////////
// Signal Description ////
/////////////////////////////////////////////
localparam IDLE = 2'b00;
localparam SETUP = 2'b01;
localparam ENABLE = 2'b10;
reg [1:0] STATE;
always @(posedge PCLK or negedge PRESETn) begin
if (!PRESETn) begin
STATE <= IDLE;
PREADY <= 0;
end else begin
PREADY <= 0;
case (STATE)
IDLE: begin
PREADY <= 1;
//if(PSEL && !PENABLE)
if (TrFr) STATE <= SETUP;
else STATE <= IDLE;
end
SETUP: begin
if (PENABLE) STATE <= ENABLE;
else STATE <= IDLE;
end
ENABLE: begin
if (PENABLE) STATE <= SETUP;
else STATE <= IDLE;
end
endcase
end
end
assign write_en = PWRITE && (STATE == ENABLE);
assign read_en = !PWRITE && (STATE == SETUP);
//always@(PADDR,PWDATA,write_en)
always @(posedge PCLK or negedge PRESETn) begin
if (!PRESETn) begin
PRDATA <= 8'd0;
SPI_CR_1 <= 8'd0;
SPI_CR_2 <= 8'd0;
SPI_BR_R <= 8'd0;
SPI_ST_R <= 8'd0;
SPI_DATA_Reg_1 <= 8'd0;
SPI_DATA_Reg_2 <= 8'd0;
SPI_DATA_Reg_3 <= 8'd0;
SPI_DATA_Reg_4 <= 8'd0;
end else begin
if (write_en) begin
case (PADDR)
3'b000: SPI_CR_1 <= PWDATA;
3'b001: SPI_CR_2 <= PWDATA;
3'b010: SPI_BR_R <= PWDATA;
3'b011: SPI_ST_R <= PWDATA;
3'b100: SPI_DATA_Reg_1 <= PWDATA;
3'b101: SPI_DATA_Reg_2 <= PWDATA;
3'b110: SPI_DATA_Reg_3 <= PWDATA;
3'b111: SPI_DATA_Reg_4 <= PWDATA;
default: SPI_CR_1 <= PWDATA;
endcase
end else if (read_en && PENABLE) begin
case (PADDR)
3'b000: PRDATA <= SPI_CR_1;
3'b001: PRDATA <= SPI_CR_2;
3'b010: PRDATA <= SPI_BR_R;
3'b011: PRDATA <= SPI_ST_R;
3'b100: PRDATA <= SPI_DATA_Reg_1;
3'b101: PRDATA <= SPI_DATA_Reg_2;
3'b110: PRDATA <= SPI_DATA_Reg_3;
3'b111: PRDATA <= SPI_DATA_Reg_4;
default: PRDATA <= SPI_CR_1;
endcase
end else begin
SPI_CR_1 <= SPI_CR_1;
SPI_CR_2 <= SPI_CR_2;
SPI_BR_R <= SPI_BR_R;
SPI_ST_R <= SPI_ST_R;
SPI_DATA_Reg_1 <= SPI_DATA_Reg_1;
SPI_DATA_Reg_2 <= SPI_DATA_Reg_2;
SPI_DATA_Reg_3 <= SPI_DATA_Reg_3;
SPI_DATA_Reg_4 <= SPI_DATA_Reg_4;
end
end
end
endmodule
| 8.643298 |
module APB_SPI_top (
// APB SLAVE PORT INTERFACE
input PCLK,
input PRESETn,
input [`APB_ADDR_WIDTH-1:0] PADDR,
input PWRITE,
input PSEL,
input PENABLE,
input [`APB_DATA_WIDTH-1:0] PWDATA,
output [`APB_DATA_WIDTH-1:0] PRDATA,
output PREADY,
input TrFr,
// SPI INTERFACE
////if Master/Slave Mode
//inout SCLK,
//inout MISO,
//inout MOSI,
//output SS,
//if only Master Mode
output SCLK,
input MISO,
output MOSI,
output SS
////if only Slave Mode
//input SCLK,
//output MISO,
//input MOSI,
//input SS
);
//APB Slave Interface Module
APB_SLAVE APB_SL (
.PCLK (PCLK),
.PRESETn(PRESETn),
.PADDR (PADDR),
.PWRITE (PWRITE),
.PSEL (PSEL),
.PENABLE(PENABLE),
.PWDATA (PWDATA),
.PRDATA (PRDATA),
.PREADY (PREADY),
.TrFr (TrFr),
.SPI_CR_1 (),
.SPI_CR_2 (),
.SPI_BR_R (),
.SPI_ST_R (),
.SPI_DATA_Reg_1(),
.SPI_DATA_Reg_2(),
.SPI_DATA_Reg_3(),
.SPI_DATA_Reg_4()
);
`ifdef ENABLED
// SPI Master Definition
SPI_Master SPI_M ();
// SPI Slave Definition
SPI_Slave SPI_S ();
// Contains the register definiation of the
Register_Def Reg_Def ();
// Baud Rate Generator for the SPI Speed of operation
Clock_Gen CLK_Gen ();
// Selection of the IO PAD type for the MISO and MOSI based on the Configuration of Registers
IO_PAD_Instance IO_Pad ();
`endif
endmodule
| 8.5891 |
module to test apb2 slaves
//
// This takes standard APB signals and allows
// communication to a slave via the tasks
// write and read.
module apb2_master_tester #(
parameter ADDR_BITS = 4,
parameter DATA_BITS = 8
)
(
input wire PCLK,
input wire [ADDR_BITS - 1:0] PADDR,
input wire PSEL,
input wire PENABLE,
input wire PWRITE,
input wire [DATA_BITS - 1:0] PWDATA,
output wire [DATA_BITS - 1:0] PRDATA
);
localparam integer MEM_SIZE = 1 << ADDR_BITS;
reg [ADDR_BITS - 1:0] PADDR_prev;
reg [DATA_BITS - 1:0] PRDATA_reg;
reg [DATA_BITS - 1:0] mem[0:MEM_SIZE - 1];
integer i;
// Public variables for assertions
integer write_count;
integer read_count;
reg last_transfer_write;
reg [ADDR_BITS - 1:0] last_addr;
reg [DATA_BITS - 1:0] last_write;
initial begin
PADDR_prev = 'hx;
PRDATA_reg = 'hx;
for (i = 0; i < MEM_SIZE; i = i + 1) begin
mem[i] = 'hx;
end
write_count = 0;
read_count = 0;
last_transfer_write = 'hx;
end
task mem_set;
input reg [ADDR_BITS - 1:0] addr;
input reg [DATA_BITS - 1:0] data;
begin
mem[addr] = data;
end
endtask
task mem_get;
input reg [ADDR_BITS - 1:0] addr;
output reg [DATA_BITS - 1:0] data;
begin
data = mem[addr];
end
endtask
task mem_reset;
begin
for (i = 0; i < MEM_SIZE; i = i + 1) begin
mem[i] = 'hx;
end
end
endtask
// Only output valid data if all the conditions are met
assign PRDATA = (PADDR === PADDR_prev) && PSEL && PENABLE && !PWRITE ? PRDATA_reg : 'hx;
always @(posedge PCLK) begin
if (PSEL) begin
PADDR_prev <= PADDR;
PRDATA_reg <= PWRITE ? 'hx : mem[PADDR];
if (PWRITE) begin
if (PENABLE) begin
mem[PADDR] <= PWDATA;
write_count <= write_count + 1;
last_addr <= PADDR;
last_write <= PWDATA;
last_transfer_write <= 1;
end
end else begin
if (PENABLE) begin
read_count <= read_count + 1;
last_addr <= PADDR;
last_transfer_write <= 0;
end
end
end else begin
PADDR_prev <= 'hx;
PRDATA_reg <= 'hx;
end
end
endmodule
| 7.372718 |
module to test apb2 slaves
//
// This takes standard APB signals and allows
// communication to a slave via the tasks
// write and read.
module apb2_slave_tester #(
parameter ADDR_BITS = 4,
parameter DATA_BITS = 8
)
(
input wire PCLK,
output reg [ADDR_BITS - 1:0] PADDR,
output reg PSEL,
output reg PENABLE,
output reg PWRITE,
output reg [DATA_BITS - 1:0] PWDATA,
input wire [DATA_BITS - 1:0] PRDATA
);
initial begin
PADDR = 'hx;
PSEL = 0;
PENABLE = 'hx;
PWRITE = 'hx;
PWDATA = 'hx;
end
task write;
input reg [ADDR_BITS - 1:0] addr;
input reg [DATA_BITS - 1:0] data;
begin
// Setup phase
@(negedge PCLK);
PADDR = addr;
PSEL = 1;
PWRITE = 1;
PENABLE = 0;
PWDATA = data;
// Access phase
@(negedge PCLK);
PENABLE = 1;
// Idle
@(negedge PCLK);
PADDR = 'hx;
PSEL = 0;
PWRITE = 'hx;
PENABLE = 'hx;
PWDATA = 'hx;
end
endtask
task write2le;
input reg [ADDR_BITS - 1:0] addr;
input reg [DATA_BITS * 2 - 1:0] data;
begin
write(addr + 0, data[DATA_BITS * 0+:DATA_BITS]);
write(addr + 1, data[DATA_BITS * 1+:DATA_BITS]);
end
endtask
task write4le;
input reg [ADDR_BITS - 1:0] addr;
input reg [DATA_BITS * 4 - 1:0] data;
begin
write(addr + 0, data[DATA_BITS * 0+:DATA_BITS]);
write(addr + 1, data[DATA_BITS * 1+:DATA_BITS]);
write(addr + 2, data[DATA_BITS * 2+:DATA_BITS]);
write(addr + 3, data[DATA_BITS * 3+:DATA_BITS]);
end
endtask
task read;
input reg [ADDR_BITS - 1:0] addr;
output reg [DATA_BITS - 1:0] data;
begin
// Setup phase
@(negedge PCLK);
PADDR = addr;
PSEL = 1;
PWRITE = 0;
PENABLE = 0;
// Access phase
@(negedge PCLK);
PENABLE = 1;
data = PRDATA;
// Idle
@(negedge PCLK);
PADDR = 'hx;
PSEL = 0;
PWRITE = 'hx;
PENABLE = 'hx;
end
endtask
task read2le;
input reg [ADDR_BITS - 1:0] addr;
output reg [DATA_BITS * 2 - 1:0] data;
begin
read(addr + 0, data[DATA_BITS * 0+:DATA_BITS]);
read(addr + 1, data[DATA_BITS * 1+:DATA_BITS]);
end
endtask
task read4le;
input reg [ADDR_BITS - 1:0] addr;
output reg [DATA_BITS * 4 - 1:0] data;
begin
read(addr + 0, data[DATA_BITS * 0+:DATA_BITS]);
read(addr + 1, data[DATA_BITS * 1+:DATA_BITS]);
read(addr + 2, data[DATA_BITS * 2+:DATA_BITS]);
read(addr + 3, data[DATA_BITS * 3+:DATA_BITS]);
end
endtask
endmodule
| 7.372718 |
module APBSlave_AD7609 (
// APB Slave Interface
input [31:0] PADDR,
input PSEL,
input PENABLE,
input PWRITE,
output [31:0] PRDATA,
input [31:0] PWDATA,
output PREADY,
// output PSLVERRS,
//
input [15:0] value1,
input [15:0] value2,
input [15:0] value3,
input [15:0] value4,
input [15:0] value5,
input [15:0] value6,
input [15:0] value7,
input [15:0] value8,
input clk_i,
input rst_n_i,
output reg Start
);
assign PREADY = 1'b1;
//??MSS????
reg [31:0] DataFromMSS_r;
reg [31:0] AddrFromMSS_r;
always @(posedge clk_i or negedge rst_n_i) begin
if (!rst_n_i) begin
DataFromMSS_r <= 32'd0;
end else if (PWRITE & PSEL & PENABLE) begin // ???
AddrFromMSS_r <= PADDR;
DataFromMSS_r <= PWDATA;
end
end
//raed data from mss
always @(posedge clk_i or negedge rst_n_i) begin
if (!rst_n_i) begin
Start <= 0;
end else begin
case (AddrFromMSS_r)
32'h3000_0100: Start <= DataFromMSS_r[0];
default: begin
Start <= Start;
end
endcase
end
end
//write data to msss
reg [31:0] DataFromFabricToMSS_r;
always @(posedge clk_i or negedge rst_n_i) begin
if (!rst_n_i) begin
DataFromFabricToMSS_r <= 32'd0;
end else if (!PWRITE & PSEL) begin
case (PADDR)
32'h3000_0000: DataFromFabricToMSS_r <=value1 ;
32'h3000_0004: DataFromFabricToMSS_r <=value2 ;
32'h3000_0008: DataFromFabricToMSS_r <=value3 ;
32'h3000_000c: DataFromFabricToMSS_r <=value4 ;
32'h3000_0010: DataFromFabricToMSS_r <=value5 ;
32'h3000_0014: DataFromFabricToMSS_r <=value6 ;
32'h3000_0018: DataFromFabricToMSS_r <=value7 ;
32'h3000_001c: DataFromFabricToMSS_r <=value8 ;
default: DataFromFabricToMSS_r <= DataFromFabricToMSS_r;
endcase
end else DataFromFabricToMSS_r <= DataFromFabricToMSS_r;
end
assign PRDATA = DataFromFabricToMSS_r;
endmodule
| 6.737949 |
module apb3_slave #(
// user parameter starts here
//
parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 31,
parameter NUM_REG = 4
) (
// user logic starts here
output [1:0] apb3LED,
output apb3Interrupt,
//
input clk,
input resetn,
input [ADDR_WIDTH-1:0] PADDR,
input PSEL,
input PENABLE,
output PREADY,
input PWRITE,
input [DATA_WIDTH-1:0] PWDATA,
output [DATA_WIDTH-1:0] PRDATA,
output PSLVERROR
);
///////////////////////////////////////////////////////////////////////////////
localparam [1:0] IDLE = 2'b00, SETUP = 2'b01, ACCESS = 2'b10;
reg [1:0] busState, busNext;
reg [DATA_WIDTH-1:0] slaveReg[0:NUM_REG-1];
reg [DATA_WIDTH-1:0] slaveRegOut;
reg slaveReady;
wire actWrite, actRead;
integer byteIndex;
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk or negedge resetn) begin
if (!resetn) busState <= IDLE;
else busState <= busNext;
end
always @(*) begin
busNext = busState;
case (busState)
IDLE: begin
if (PSEL && !PENABLE) busNext = SETUP;
else busNext = IDLE;
end
SETUP: begin
if (PENABLE) busNext = ACCESS;
else busNext = IDLE;
end
ACCESS: begin
if (PENABLE) busNext = ACCESS;
else busNext = IDLE;
end
default: begin
busNext = IDLE;
end
endcase
end
assign actWrite = PWRITE & (busNext == ACCESS);
assign actRead = !PWRITE & (busNext == SETUP);
assign PSLVERROR = 1'b0; //FIXME
assign PRDATA = slaveRegOut;
assign PREADY = slaveReady;
always @(posedge clk) begin
slaveReady <= (busState == IDLE);
end
always @(posedge clk or negedge resetn) begin
if (!resetn)
for (byteIndex = 0; byteIndex < NUM_REG; byteIndex = byteIndex + 1)
slaveReg[byteIndex] <= {{DATA_WIDTH} {1'b0}};
else begin
for (byteIndex = 0; byteIndex < NUM_REG; byteIndex = byteIndex + 1)
if (actWrite && PADDR[3:0] == (byteIndex * 4)) slaveReg[byteIndex] <= PWDATA;
else slaveReg[byteIndex] <= slaveReg[byteIndex];
end
end
always @(posedge clk or negedge resetn) begin
if (!resetn) slaveRegOut <= {{DATA_WIDTH} {1'b0}};
else begin
if (actRead) slaveRegOut <= slaveReg[PADDR[7:2]];
else slaveRegOut <= slaveRegOut;
end
end
//custom logic starts here
assign apb3LED = slaveReg[0][1:0];
assign apb3Interrupt = slaveReg[0][2];
//
endmodule
| 7.546385 |
module APBGPIO (
//APB Inputs
input wire PCLK,
input wire PRESETn,
input wire PWRITE,
input wire [31:0] PWDATA,
input wire [31:0] PADDR,
input wire PENABLE,
input PSEL,
//APB Outputs
output wire PREADY,
output wire [31:0] PRDATA,
// GPIO Ports
input wire [15:0] GPIOIN,
output wire [15:0] GPIOOUT,
output wire [15:0] GPIOPU,
output wire [15:0] GPIOPD,
output wire [15:0] GPIOEN
);
reg [15:0] gpio_data, gpio_data_next; // Address 0: Port Data
reg [15:0] gpio_dir; // Address 4: Port direction; 1:i/p, 0:o/p
reg [15:0]
gpio_pu,
gpio_pd; // PU (Address: 8) & PD (Address: 16) enable registers @ 8 and 16 respectively
assign GPIOEN = gpio_dir;
assign GPIOPU = gpio_pu;
assign GPIOPD = gpio_pd;
assign GPIOOUT = gpio_data;
assign PREADY = 1'b1; //always ready
// The GPIO Direction Register (0: o/p, 1: i/p)
always @(posedge PCLK, negedge PRESETn) begin
if (!PRESETn) begin
gpio_dir <= 16'b0;
end else if (PENABLE & PWRITE & PREADY & PSEL & PADDR[2]) //
gpio_dir <= PWDATA[15:0];
end
// The GPIO PU Register
always @(posedge PCLK, negedge PRESETn) begin
if (!PRESETn) begin
gpio_pu <= 16'b0;
end else if (PENABLE & PWRITE & PREADY & PSEL & PADDR[3]) //
gpio_pu <= PWDATA[15:0];
end
// The GPIO PD Register
always @(posedge PCLK, negedge PRESETn) begin
if (!PRESETn) begin
gpio_pd <= 16'b0;
end else if (PENABLE & PWRITE & PREADY & PSEL & PADDR[4]) //
gpio_pd <= PWDATA[15:0];
end
// The GPIO Data
always @(posedge PCLK, negedge PRESETn) begin
if (!PRESETn) begin
gpio_data <= 16'b0;
end else gpio_data <= gpio_data_next;
end
integer i;
always @* begin
for (i = 0; i < 16; i = i + 1) begin
if (gpio_dir[i] == 1'b1) gpio_data_next[i] = GPIOIN[i];
else if (PENABLE & PWRITE & PREADY & PSEL & ~PADDR[2]) gpio_data_next[i] = PWDATA[i];
else gpio_data_next[i] = gpio_data[i];
end
end
assign PRDATA[31:0] = (~PADDR[2]) ? {16'h0, gpio_data} : {16'h0, gpio_dir};
endmodule
| 7.16019 |
module to I2C Core
////
////
////
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbi2c/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// apbi2c_spec IP core specification document.
////
////
////
//// To Do: Things are right here but always all block can suffer changes
////
////
////
////
////
//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
//// Ronal Dario Celaya
////
/////////////////////////////////////////////////////////////////
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
`timescale 1ns/1ps //timescale
module apb(
//standard ARM
input PCLK,
input PRESETn,
input PSELx,
input PWRITE,
input PENABLE,
input [31:0] PADDR,
input [31:0] PWDATA,
//internal pin
input [31:0] READ_DATA_ON_RX,
input ERROR,
input TX_EMPTY,
input RX_EMPTY,
//external pin
output [31:0] PRDATA,
//internal pin
output reg [13:0] INTERNAL_I2C_REGISTER_CONFIG,
output reg [13:0] INTERNAL_I2C_REGISTER_TIMEOUT,
output [31:0] WRITE_DATA_ON_TX,
output WR_ENA,
output RD_ENA,
//outside port
output PREADY,
output PSLVERR,
//interruption
output INT_RX,
output INT_TX
);
//ENABLE WRITE ON TX FIFO
assign WR_ENA = (PWRITE == 1'b1 & PENABLE == 1'b1 & PADDR == 32'd0 & PSELx == 1'b1)? 1'b1:1'b0;
//ENABLE READ ON RX FIFO
assign RD_ENA = (PWRITE == 1'b0 & PENABLE == 1'b1 & PADDR == 32'd4 & PSELx == 1'b1)? 1'b1:1'b0;
//WRITE ON I2C MODULE
assign PREADY = ((WR_ENA == 1'b1 | RD_ENA == 1'b1 | PADDR == 32'd8 | PADDR == 32'd12) & (PENABLE == 1'b1 & PSELx == 1'b1))? 1'b1:1'b0;
//INPUT TO WRITE ON TX FIFO
assign WRITE_DATA_ON_TX = (PADDR == 32'd0)? PWDATA:PWDATA;
//OUTPUT DATA FROM RX TO PRDATA
assign PRDATA = (PADDR == 32'd4)? READ_DATA_ON_RX:READ_DATA_ON_RX;
//ERROR FROM I2C CORE
assign PSLVERR = ERROR;
//INTERRUPTION FROM I2C
assign INT_TX = TX_EMPTY;
//INTERRUPTION FROM I2C
assign INT_RX = RX_EMPTY;
//This is sequential logic used only to register configuration
always@(posedge PCLK)
begin
if(!PRESETn)
begin
INTERNAL_I2C_REGISTER_CONFIG <= 14'd0;
INTERNAL_I2C_REGISTER_TIMEOUT <= 14'd0;
end
else
begin
// Set configuration to i2c
if(PADDR == 32'd8 && PSELx == 1'b1 && PWRITE == 1'b1 && PREADY == 1'b1)
begin
INTERNAL_I2C_REGISTER_CONFIG <= PWDATA[13:0];
end
else if(PADDR == 32'd12 && PSELx == 1'b1 && PWRITE == 1'b1 && PREADY == 1'b1)
begin
INTERNAL_I2C_REGISTER_TIMEOUT <= PWDATA[13:0];
end
else
begin
INTERNAL_I2C_REGISTER_CONFIG <= INTERNAL_I2C_REGISTER_CONFIG;
end
end
end
endmodule
| 8.069831 |
module fifo #(
parameter integer DWIDTH = 32,
parameter integer AWIDTH = 4
) (
input clock,
reset,
wr_en,
rd_en,
input [DWIDTH-1:0] data_in,
output f_full,
f_empty,
output [DWIDTH-1:0] data_out
);
reg [DWIDTH-1:0] mem[0:2**AWIDTH-1];
//parameter integer DEPTH = 1 << AWIDTH;
//wire [DWIDTH-1:0] data_ram_out;
//wire wr_en_ram;
//wire rd_en_ram;
reg [AWIDTH-1:0] wr_ptr;
reg [AWIDTH-1:0] rd_ptr;
reg [AWIDTH-1:0] counter;
wire [AWIDTH-1:0] wr;
wire [AWIDTH-1:0] rd;
wire [AWIDTH-1:0] w_counter;
//Write pointer
always @(posedge clock) begin
if (reset) begin
wr_ptr <= {(AWIDTH) {1'b0}};
end else if (wr_en && !f_full) begin
mem[wr_ptr] <= data_in;
wr_ptr <= wr;
end
end
//Read pointer
always @(posedge clock) begin
if (reset) begin
rd_ptr <= {(AWIDTH) {1'b0}};
end else if (rd_en && !f_empty) begin
rd_ptr <= rd;
end
end
//Counter
always @(posedge clock) begin
if (reset) begin
counter <= {(AWIDTH) {1'b0}};
end else begin
if (rd_en && !f_empty && !wr_en) begin
counter <= w_counter;
end else if (wr_en && !f_full && !rd_en) begin
counter <= w_counter;
end
end
end
assign f_full = (counter == 4'd15) ? 1'b1 : 1'b0; //DEPTH- 1) ;
assign f_empty = (counter == 4'd0) ? 1'b1 : 1'b0; //{AWIDTH{1'b0}});
assign wr = (wr_en && !f_full) ? wr_ptr + 4'd1 : wr_ptr + 4'd0;
assign rd = (rd_en && !f_empty) ? rd_ptr + 4'd1 : rd_ptr + 4'd0;
assign w_counter = (rd_en && !f_empty && !wr_en)? counter - 4'd1:
(wr_en && !f_full && !rd_en)? counter + 4'd1:
w_counter + 4'd0;
//assign wr_en_ram = wr_en;
//assign rd_en_ram = rd_en;
assign data_out = mem[rd_ptr]; //data_ram_out;
/*
dp_ram #(DWIDTH, AWIDTH)
RAM_1 (
.clock(clock),
.reset(reset),
.wr_en(wr_en_ram),
.rd_en(rd_en_ram),
.data_in(data_in),
.wr_addr(wr_ptr),
.data_out(data_ram_out),
.rd_addr(rd_ptr)
);
*/
endmodule
| 8.01468 |
module i2c (
//APB PORTS
input PCLK,
input PRESETn,
input [31:0] PADDR,
input [31:0] PWDATA,
input PWRITE,
input PSELx,
input PENABLE,
output PREADY,
output PSLVERR,
output INT_RX,
output INT_TX,
output [31:0] PRDATA,
//I2C OUTPUT
output SDA_ENABLE,
output SCL_ENABLE,
inout SDA,
inout SCL
);
wire RESET_N;
//THIS IS USED TO RESET FIFO
assign RESET_N = (PRESETn == 0) ? 1'b1 : 1'b0;
//WIRES USED TO CONECT BLOCK WITH EACH OTHER
wire TX_RD_EN;
wire TX_F_EMPTY;
wire TX_F_FULL;
wire [31:0] TX_DATA_IN;
wire [31:0] TX_DATA_OUT;
wire TX_WRITE_ENA;
wire RX_RD_EN;
wire RX_F_EMPTY;
wire RX_F_FULL;
wire [31:0] RX_DATA_IN;
wire [31:0] RX_DATA_OUT;
wire RX_WRITE_ENA;
wire [13:0] REGISTER_CONFIG;
wire [13:0] TIMEOUT_CONFIG;
wire error;
wire tx_empty;
wire rx_empty;
//wire w_pwrite;
wire w_full;
//wire w_full_tx;
//assign w_pwrite = (PWRITE == 1'b0)?1'b1:1'b0;
//CONECTIONS WITH FIFO TX
fifo DUT_FIFO_TX (
.clock(PCLK),
.reset(RESET_N),
.wr_en(TX_WRITE_ENA),
.rd_en(TX_RD_EN),
.data_in(TX_DATA_IN),
.f_full(w_full),
.f_empty(TX_F_EMPTY),
.data_out(TX_DATA_OUT)
);
//and(w_full_tx,w_pwrite,w_full);
assign TX_F_FULL = w_full;
//CONECTIONS WITH FIFO RX
fifo DUT_FIFO_RX (
.clock(PCLK),
.reset(RESET_N),
.wr_en(RX_WRITE_ENA),
.rd_en(RX_RD_EN),
.data_in(RX_DATA_IN),
.f_full(RX_F_FULL),
.f_empty(RX_F_EMPTY),
.data_out(RX_DATA_OUT)
);
//CONECTIONS WITH APB AND ALL BLOCKS WHERE IS TWO FIFOS AND I2C CORE
apb DUT_APB (
.PCLK(PCLK),
.PRESETn(PRESETn),
.PADDR(PADDR),
.PRDATA(PRDATA),
.PWDATA(PWDATA),
.PWRITE(PWRITE),
.PSELx(PSELx),
.PENABLE(PENABLE),
.PREADY(PREADY),
.PSLVERR(PSLVERR),
.READ_DATA_ON_RX(RX_DATA_OUT),
.INTERNAL_I2C_REGISTER_CONFIG(REGISTER_CONFIG),
.INTERNAL_I2C_REGISTER_TIMEOUT(TIMEOUT_CONFIG),
.INT_RX(INT_RX),
.WR_ENA(TX_WRITE_ENA),
.WRITE_DATA_ON_TX(TX_DATA_IN),
.RD_ENA(RX_RD_EN),
.INT_TX(INT_TX),
.TX_EMPTY(tx_empty),
.RX_EMPTY(rx_empty),
.ERROR(error)
);
//I2C CORE BLOCK WITH ALL ANOTHER BLOCKS
module_i2c DUT_I2C_INTERNAL_RX_TX (
.PCLK(PCLK),
.PRESETn(PRESETn),
.fifo_rx_wr_en(RX_WRITE_ENA),
.fifo_rx_f_empty(RX_F_EMPTY),
.fifo_rx_data_in(RX_DATA_IN),
.fifo_rx_f_full(RX_F_FULL),
.fifo_tx_f_full(TX_F_FULL),
.fifo_tx_f_empty(TX_F_EMPTY),
.fifo_tx_rd_en(TX_RD_EN),
.fifo_tx_data_out(TX_DATA_OUT),
.DATA_CONFIG_REG(REGISTER_CONFIG),
.TIMEOUT_TX(TIMEOUT_CONFIG),
.RX_EMPTY(rx_empty),
.TX_EMPTY(tx_empty),
.ERROR(error),
.ENABLE_SDA(SDA_ENABLE),
.ENABLE_SCL(SCL_ENABLE),
.SDA(SDA),
.SCL(SCL)
);
endmodule
| 6.662695 |
module QueueModuleled ( // @[:@53.2]
input clock, // @[:@54.4]
input reset, // @[:@55.4]
output io_i_ready, // @[:@56.4]
input io_i_valid, // @[:@56.4]
input [23:0] io_i_bits, // @[:@56.4]
input io_o_ready, // @[:@56.4]
output io_o_valid, // @[:@56.4]
output [23:0] io_o_bits // @[:@56.4]
);
wire qa_clock; // @[Decoupled.scala 293:21:@58.4]
wire qa_reset; // @[Decoupled.scala 293:21:@58.4]
wire qa_io_enq_ready; // @[Decoupled.scala 293:21:@58.4]
wire qa_io_enq_valid; // @[Decoupled.scala 293:21:@58.4]
wire [23:0] qa_io_enq_bits; // @[Decoupled.scala 293:21:@58.4]
wire qa_io_deq_ready; // @[Decoupled.scala 293:21:@58.4]
wire qa_io_deq_valid; // @[Decoupled.scala 293:21:@58.4]
wire [23:0] qa_io_deq_bits; // @[Decoupled.scala 293:21:@58.4]
Queue_led qa ( // @[Decoupled.scala 293:21:@58.4]
.clock(qa_clock),
.reset(qa_reset),
.io_enq_ready(qa_io_enq_ready),
.io_enq_valid(qa_io_enq_valid),
.io_enq_bits(qa_io_enq_bits),
.io_deq_ready(qa_io_deq_ready),
.io_deq_valid(qa_io_deq_valid),
.io_deq_bits(qa_io_deq_bits)
);
assign io_i_ready = qa_io_enq_ready; // @[Decoupled.scala 296:17:@63.4]
assign io_o_valid = qa_io_deq_valid; // @[queue.scala 17:15:@64.4]
assign io_o_bits = qa_io_deq_bits; // @[queue.scala 18:15:@65.4]
assign qa_clock = clock; // @[:@59.4]
assign qa_reset = reset; // @[:@60.4]
assign qa_io_enq_valid = io_i_valid; // @[Decoupled.scala 294:22:@61.4]
assign qa_io_enq_bits = io_i_bits; // @[Decoupled.scala 295:21:@62.4]
assign qa_io_deq_ready = io_o_ready; // @[queue.scala 19:15:@66.4]
endmodule
| 7.583162 |
module apbmaster (
input pclk,
input presetn,
input [1:0]add,//00-x,01-read,10-x,11-write
output reg psel,
output reg penable,
output [7:0] paddr,
output pwrite,
output [7:0]pwdata,
input [7:0]prdata,
input pready
);
reg [7:0] cur_pwrite, nex_pwrite, cur_prdata, nex_prdata;
reg [1:0] cur_s, nex_s;
parameter idle = 2'b00, setup = 2'b01, access = 2'b10;
always @(posedge pclk) begin
if (~presetn) begin
cur_s <= idle;
cur_pwrite <= 7'b0;
cur_prdata <= 7'b0;
end else begin
cur_s <= nex_s;
cur_pwrite <= nex_pwrite;
cur_prdata <= nex_prdata;
end
end
always @(cur_s or add) begin
case (cur_s)
idle: begin
if (add[0]) begin
nex_s = setup;
nex_pwrite = add[1];
end else nex_s = idle;
end
setup: begin
psel = 1;
penable = 0;
nex_s = access;
end
access: begin
psel = 1;
penable = 1;
if (pready) begin
if (~cur_pwrite) begin
nex_prdata = prdata;
nex_s = idle;
end
end else nex_s = access;
end
default: begin
psel = 0;
penable = 0;
nex_s = idle;
nex_prdata = cur_prdata;
nex_pwrite = cur_pwrite;
end
endcase
end
assign paddr = (cur_s == access) ? 8'h32 : 8'h0000;
assign pwrite = cur_pwrite;
assign pwdata = (cur_s == access) ? cur_prdata : 7'b0;
endmodule
| 7.946033 |
module APBSlaveLED (
// APB Slave Interface
input [31:0] PADDR,
input PSEL,
input PENABLE,
input PWRITE,
output [31:0] PRDATA,
input [31:0] PWDATA,
output PREADY,
// output PSLVERRS,
//
input clk_i,
input rst_n_i,
input key_i,
output reg led0_o,
output reg led1_o
);
assign PREADY = 1'b1;
//??MSS????
reg [31:0] DataFromMSS_r;
reg [31:0] AddrFromMSS_r;
always @(posedge clk_i or negedge rst_n_i) begin
if (!rst_n_i) begin
DataFromMSS_r <= 32'd0;
end else if (PWRITE & PSEL & PENABLE) begin // ???
AddrFromMSS_r <= PADDR;
DataFromMSS_r <= PWDATA;
end
end
//?MSS????????LED????
always @(posedge clk_i or negedge rst_n_i) begin
if (!rst_n_i) begin
led0_o <= 0;
led1_o <= 0;
end else begin
case (AddrFromMSS_r)
32'h3000_0000: led0_o <= DataFromMSS_r[0];
32'h3000_0004: led1_o <= DataFromMSS_r[0];
default: begin
led0_o <= led0_o;
led1_o <= led1_o;
end
endcase
end
end
//??MSS???? ?KEY??????MSS
reg [31:0] DataFromFabricToMSS_r;
always @(posedge clk_i or negedge rst_n_i) begin
if (!rst_n_i) begin
DataFromFabricToMSS_r <= 32'd0;
end else if (!PWRITE & PSEL) begin
case (PADDR)
32'h3000_0008: DataFromFabricToMSS_r <= {31'd0, key_i}; // ??????????0
default: DataFromFabricToMSS_r <= DataFromFabricToMSS_r;
endcase
end else DataFromFabricToMSS_r <= DataFromFabricToMSS_r;
end
assign PRDATA = DataFromFabricToMSS_r;
endmodule
| 6.576075 |
module aes_core (
//OUTPUTS
output [31:0] col_out,
output [31:0] key_out,
output [31:0] iv_out,
output end_aes,
//INPUTS
input [31:0] bus_in,
input [3:0] iv_en,
input [3:0] iv_sel_rd,
input [3:0] key_en,
input [1:0] key_sel_rd,
input [1:0] data_type,
input [1:0] addr,
input [1:0] op_mode,
input [1:0] aes_mode,
input start,
input disable_core,
input write_en,
input read_en,
input first_block,
input rst_n,
input clk
);
wire [1:0] rk_sel;
wire [1:0] key_out_sel;
wire [3:0] round;
wire [2:0] sbox_sel;
wire [3:0] col_en_host;
wire [3:0] iv_en_host;
wire [3:0] col_en_cnt_unit;
wire [3:0] key_en_host;
wire [3:0] key_en_cnt_unit;
wire [1:0] col_sel;
wire key_sel;
wire bypass_rk;
wire bypass_key_en;
wire last_round;
wire iv_cnt_en;
wire iv_cnt_sel;
wire mode_ctr;
wire mode_cbc;
wire key_init;
wire key_gen;
wire [1:0] col_addr_host;
assign col_en_host = (4'b0001 << addr) & {4{write_en}};
assign col_addr_host = addr & {2{read_en}};
assign iv_en_host = iv_en;
assign key_en_host = key_en;
datapath AES_CORE_DATAPATH (
.col_bus (col_out),
.key_bus (key_out),
.iv_bus (iv_out),
.bus_in (bus_in),
.end_aes (end_aes),
.data_type (data_type),
.rk_sel (rk_sel),
.key_out_sel (key_out_sel),
.round (round),
.sbox_sel (sbox_sel),
.iv_en (iv_en_host),
.iv_sel_rd (iv_sel_rd),
.col_en_host (col_en_host),
.col_en_cnt_unit (col_en_cnt_unit),
.key_host_en (key_en_host),
.key_en (key_en_cnt_unit),
.key_sel_rd (key_sel_rd),
.col_sel_host (col_addr_host),
.col_sel (col_sel),
.key_sel (key_sel),
.bypass_rk (bypass_rk),
.bypass_key_en (bypass_key_en),
.first_block (first_block),
.last_round (last_round),
.iv_cnt_en (iv_cnt_en),
.iv_cnt_sel (iv_cnt_sel),
.enc_dec (enc_dec),
.mode_ctr (mode_ctr),
.mode_cbc (mode_cbc),
.key_init (key_init),
.key_gen (key_gen),
.key_derivation_en(key_derivation_en),
.end_comp (end_comp),
.rst_n (rst_n),
.clk (clk)
);
control_unit AES_CORE_CONTROL_UNIT (
.end_comp (end_comp),
.sbox_sel (sbox_sel),
.rk_sel (rk_sel),
.key_out_sel (key_out_sel),
.col_sel (col_sel),
.key_en (key_en_cnt_unit),
.col_en (col_en_cnt_unit),
.round (round),
.bypass_rk (bypass_rk),
.bypass_key_en (bypass_key_en),
.key_sel (key_sel),
.last_round (last_round),
.iv_cnt_en (iv_cnt_en),
.iv_cnt_sel (iv_cnt_sel),
.mode_ctr (mode_ctr),
.mode_cbc (mode_cbc),
.key_init (key_init),
.encrypt_decrypt (enc_dec),
.key_gen (key_gen),
.operation_mode (op_mode),
.aes_mode (aes_mode),
.start (start),
.key_derivation_en(key_derivation_en),
.disable_core (disable_core),
.clk (clk),
.rst_n (rst_n)
);
endmodule
| 7.695875 |
module data_swap #(
parameter WIDTH = 32
) (
//OUTPUTS
output [WIDTH - 1:0] data_swap,
//INPUTS
input [WIDTH - 1:0] data_in,
input [1:0] swap_type
);
//=====================================================================================
// Swap Types
//=====================================================================================
localparam NO_SWAP = 2'b00;
localparam HALF_WORD_SWAP = 2'b01;
localparam BYTE_SWAP = 2'b10;
localparam BIT_SWAP = 2'b11;
localparam TYPES = 4;
wire [WIDTH - 1 : 0] words[0 : TYPES - 1];
generate
genvar i, j;
for (i = 0; i < TYPES; i = i + 1) begin : BLOCK
for (j = 0; j < WIDTH; j = j + 1) begin : SUB_BLOCK
if (i != 3)
assign words[i][j] = data_in[(WIDTH-(WIDTH/2**i))-2*(WIDTH/2**i)*(j/(WIDTH/2**i))+j];
else assign words[i][j] = data_in[WIDTH-1-j];
end
end
endgenerate
assign data_swap = words[swap_type];
endmodule
| 6.690797 |
module key_expander (
// OUTPUTS
output [127:0] key_out,
output [31:0] g_in,
// INPUTS
input [31:0] g_out,
input [127:0] key_in,
input [3:0] round,
input add_w_out,
input enc_dec
);
localparam integer KEY_WIDTH = 32;
localparam integer KEY_NUM = 4;
localparam integer WORD = 8;
localparam integer ROUNDS = 10;
wire [KEY_WIDTH - 1 : 0] key [0 : KEY_NUM - 1];
wire [ WORD - 1 : 0] rot_in [0 : KEY_NUM - 1];
wire [KEY_WIDTH - 1 : 0] g_func;
reg [WORD - 1 : 0] rc_dir, rc_inv;
wire [WORD - 1 : 0] rc;
//=====================================================================================
// Key Generation
//=====================================================================================
generate
genvar i;
for (i = 0; i < KEY_NUM; i = i + 1) begin : KG
assign key[KEY_NUM-1-i] = key_in[KEY_WIDTH*(i+1)-1 : KEY_WIDTH*i];
end
endgenerate
//=====================================================================================
// Key Out Generation
//=====================================================================================
generate
genvar j;
for (j = 0; j < KEY_NUM; j = j + 1) begin : KGO
if (j == 0)
assign key_out[KEY_WIDTH*(KEY_NUM-j)-1 : KEY_WIDTH*(KEY_NUM-j-1)] = key[j] ^ g_func;
else if (j == 1)
assign key_out[KEY_WIDTH*(KEY_NUM - j) - 1 : KEY_WIDTH*(KEY_NUM - j - 1)] = (add_w_out) ? key[j] ^ key[j - 1] ^ g_func : key[j] ^ key[j - 1];
else assign key_out[KEY_WIDTH*(KEY_NUM-j)-1 : KEY_WIDTH*(KEY_NUM-j-1)] = key[j] ^ key[j-1];
end
endgenerate
//=====================================================================================
// G Function Input Generation
//=====================================================================================
generate
genvar k;
for (k = 0; k < KEY_NUM; k = k + 1) begin : GFIG
assign rot_in[k] = (enc_dec) ? key[KEY_NUM - 1][WORD*(k + 1) - 1 : WORD*k] : key[KEY_NUM - 1][WORD*(k + 1) - 1 : WORD*k] ^ key[KEY_NUM - 2][WORD*(k + 1) - 1 : WORD*k];
end
endgenerate
generate
genvar l;
for (l = 0; l < KEY_NUM; l = l + 1) begin : GFIG1
assign g_in[WORD*(l+1)-1 : WORD*l] = rot_in[(KEY_NUM+l-1)%KEY_NUM];
end
endgenerate
//=====================================================================================
// G Functin Output Processsing
//=====================================================================================
assign g_func = {g_out[KEY_WIDTH-1 : KEY_WIDTH-WORD] ^ rc, g_out[KEY_WIDTH-WORD-1 : 0]};
assign rc = (enc_dec) ? rc_dir : rc_inv;
always @(*) begin : RC_DIR
integer i;
for (i = 0; i < ROUNDS; i = i + 1)
if (round == 8) rc_dir = 8'h1b;
else if (round == 9) rc_dir = 8'h36;
else rc_dir = 8'h01 << round;
end
always @(*) begin : RC_INV
integer i;
for (i = 0; i < ROUNDS; i = i + 1)
if (round == 1) rc_inv = 8'h1b;
else if (round == 0) rc_inv = 8'h36;
else rc_inv = 8'h80 >> (round - 2);
end
endmodule
| 8.294333 |
module sBox #(
parameter SBOX_NUM = 4
) (
//OUTPUTS
output [8*SBOX_NUM - 1:0] sbox_out_enc,
output [8*SBOX_NUM - 1:0] sbox_out_dec,
//INPUTS
input [8*SBOX_NUM - 1:0] sbox_in,
input enc_dec,
input clk
);
sBox_8 SBOX[SBOX_NUM - 1:0] (
.sbox_out_enc(sbox_out_enc),
.sbox_out_dec(sbox_out_dec),
.sbox_in (sbox_in),
.enc_dec (enc_dec),
.clk (clk)
);
endmodule
| 6.582372 |
module shift_rows (
//OUTPUTS
output [127 : 0] data_out_enc, // Result after Shift Rows operation - enc
output [127 : 0] data_out_dec, // Result after Shift Rows operation - dec
//INPUTS
input [127 : 0] data_in // Input Bus
);
localparam integer BUS_WIDTH = 128; // Bus Width
localparam integer ST_WORD = 8; // Data Size of word in State MAtrix
localparam integer ST_LINE = 4; // Number of Lines of State Matrix
localparam integer ST_COL = 4; // Number of Columns of State Matrix
wire [ST_WORD - 1 : 0] state[0 : ST_LINE - 1][0 : ST_COL - 1];
wire [ST_WORD - 1 : 0] state_sft_l[0 : ST_LINE - 1][0 : ST_COL - 1];
wire [ST_WORD - 1 : 0] state_sft_r[0 : ST_LINE - 1][0 : ST_COL - 1];
//=====================================================================================
// State Matrix generation
//=====================================================================================
generate
genvar l, c;
for (l = 0; l < ST_LINE; l = l + 1) begin : SMG
for (c = 0; c < ST_COL; c = c + 1) begin : BLOCK
assign state[l][c] = data_in[ST_WORD*((ST_COL - c)*ST_LINE - l) - 1 : ST_WORD*((ST_COL - c)*ST_LINE - l - 1)];
end
end
endgenerate
//=====================================================================================
// Shift Row operation
//=====================================================================================
generate
genvar l1, c1;
for (l1 = 0; l1 < ST_LINE; l1 = l1 + 1) begin : SRO
for (c1 = 0; c1 < ST_COL; c1 = c1 + 1) begin : BLOCK
assign state_sft_l[l1][c1] = state[l1][(c1+l1)%ST_COL];
assign state_sft_r[l1][c1] = state[l1][(c1+(ST_COL-l1))%ST_COL];
end
end
endgenerate
//=====================================================================================
// State Matrix to Bus Output Transformation
//=====================================================================================
generate
genvar l2, c2;
for (l2 = 0; l2 < ST_LINE; l2 = l2 + 1) begin : SMBOT
for (c2 = 0; c2 < ST_COL; c2 = c2 + 1) begin : BLOCK
assign data_out_enc[ST_WORD*((ST_COL - c2)*ST_LINE - l2) - 1 : ST_WORD*((ST_COL - c2)*ST_LINE - l2 - 1)] = state_sft_l[l2][c2];
assign data_out_dec[ST_WORD*((ST_COL - c2)*ST_LINE - l2) - 1 : ST_WORD*((ST_COL - c2)*ST_LINE - l2 - 1)] = state_sft_r[l2][c2];
end
end
endgenerate
endmodule
| 6.667518 |
module QueueModule_uart ( // @[:@53.2]
input clock, // @[:@54.4]
input reset, // @[:@55.4]
output io_i_ready, // @[:@56.4]
input io_i_valid, // @[:@56.4]
input [11:0] io_i_bits, // @[:@56.4]
input io_o_ready, // @[:@56.4]
output io_o_valid, // @[:@56.4]
output [11:0] io_o_bits // @[:@56.4]
);
wire qa_clock; // @[Decoupled.scala 293:21:@58.4]
wire qa_reset; // @[Decoupled.scala 293:21:@58.4]
wire qa_io_enq_ready; // @[Decoupled.scala 293:21:@58.4]
wire qa_io_enq_valid; // @[Decoupled.scala 293:21:@58.4]
wire [11:0] qa_io_enq_bits; // @[Decoupled.scala 293:21:@58.4]
wire qa_io_deq_ready; // @[Decoupled.scala 293:21:@58.4]
wire qa_io_deq_valid; // @[Decoupled.scala 293:21:@58.4]
wire [11:0] qa_io_deq_bits; // @[Decoupled.scala 293:21:@58.4]
Queue_uart qa ( // @[Decoupled.scala 293:21:@58.4]
.clock(qa_clock),
.reset(qa_reset),
.io_enq_ready(qa_io_enq_ready),
.io_enq_valid(qa_io_enq_valid),
.io_enq_bits(qa_io_enq_bits),
.io_deq_ready(qa_io_deq_ready),
.io_deq_valid(qa_io_deq_valid),
.io_deq_bits(qa_io_deq_bits)
);
assign io_i_ready = qa_io_enq_ready; // @[Decoupled.scala 296:17:@63.4]
assign io_o_valid = qa_io_deq_valid; // @[queue.scala 17:15:@64.4]
assign io_o_bits = qa_io_deq_bits; // @[queue.scala 18:15:@65.4]
assign qa_clock = clock; // @[:@59.4]
assign qa_reset = reset; // @[:@60.4]
assign qa_io_enq_valid = io_i_valid; // @[Decoupled.scala 294:22:@61.4]
assign qa_io_enq_bits = io_i_bits; // @[Decoupled.scala 295:21:@62.4]
assign qa_io_deq_ready = io_o_ready; // @[queue.scala 19:15:@66.4]
endmodule
| 6.970289 |
module apb_burst_regs (
input wire clk,
input wire rst_n,
// APB Port
input wire apbs_psel,
input wire apbs_penable,
input wire apbs_pwrite,
input wire [15:0] apbs_paddr,
input wire [31:0] apbs_pwdata,
output wire [31:0] apbs_prdata,
output wire apbs_pready,
output wire apbs_pslverr,
// Register interfaces
input wire csr_ready_i,
output reg csr_read_o,
output reg csr_write_o,
output reg [31:0] addr_o,
input wire [31:0] data0_i,
output reg [31:0] data0_o,
output reg data0_wen,
output reg data0_ren,
input wire [31:0] data1_i,
output reg [31:0] data1_o,
output reg data1_wen,
output reg data1_ren,
input wire [31:0] data2_i,
output reg [31:0] data2_o,
output reg data2_wen,
output reg data2_ren,
input wire [31:0] data3_i,
output reg [31:0] data3_o,
output reg data3_wen,
output reg data3_ren
);
// APB adapter
wire [31:0] wdata = apbs_pwdata;
reg [31:0] rdata;
wire wen = apbs_psel && apbs_penable && apbs_pwrite;
wire ren = apbs_psel && apbs_penable && !apbs_pwrite;
wire [15:0] addr = apbs_paddr & 16'h1c;
assign apbs_prdata = rdata;
assign apbs_pready = 1'b1;
assign apbs_pslverr = 1'b0;
localparam ADDR_CSR = 0;
localparam ADDR_ADDR = 4;
localparam ADDR_DATA0 = 8;
localparam ADDR_DATA1 = 12;
localparam ADDR_DATA2 = 16;
localparam ADDR_DATA3 = 20;
wire __csr_wen = wen && addr == ADDR_CSR;
wire __csr_ren = ren && addr == ADDR_CSR;
wire __addr_wen = wen && addr == ADDR_ADDR;
wire __addr_ren = ren && addr == ADDR_ADDR;
wire __data0_wen = wen && addr == ADDR_DATA0;
wire __data0_ren = ren && addr == ADDR_DATA0;
wire __data1_wen = wen && addr == ADDR_DATA1;
wire __data1_ren = ren && addr == ADDR_DATA1;
wire __data2_wen = wen && addr == ADDR_DATA2;
wire __data2_ren = ren && addr == ADDR_DATA2;
wire __data3_wen = wen && addr == ADDR_DATA3;
wire __data3_ren = ren && addr == ADDR_DATA3;
wire csr_ready_wdata = wdata[0];
wire csr_ready_rdata;
wire csr_read_wdata = wdata[1];
wire csr_read_rdata;
wire csr_write_wdata = wdata[2];
wire csr_write_rdata;
wire [31:0] __csr_rdata = {29'h0, csr_write_rdata, csr_read_rdata, csr_ready_rdata};
assign csr_ready_rdata = csr_ready_i;
assign csr_read_rdata = 1'h0;
assign csr_write_rdata = 1'h0;
wire [31:0] addr_wdata = wdata[31:0];
wire [31:0] addr_rdata;
wire [31:0] __addr_rdata = {addr_rdata};
assign addr_rdata = addr_o;
wire [31:0] data0_wdata = wdata[31:0];
wire [31:0] data0_rdata;
wire [31:0] __data0_rdata = {data0_rdata};
assign data0_rdata = data0_i;
wire [31:0] data1_wdata = wdata[31:0];
wire [31:0] data1_rdata;
wire [31:0] __data1_rdata = {data1_rdata};
assign data1_rdata = data1_i;
wire [31:0] data2_wdata = wdata[31:0];
wire [31:0] data2_rdata;
wire [31:0] __data2_rdata = {data2_rdata};
assign data2_rdata = data2_i;
wire [31:0] data3_wdata = wdata[31:0];
wire [31:0] data3_rdata;
wire [31:0] __data3_rdata = {data3_rdata};
assign data3_rdata = data3_i;
always @(*) begin
case (addr)
ADDR_CSR: rdata = __csr_rdata;
ADDR_ADDR: rdata = __addr_rdata;
ADDR_DATA0: rdata = __data0_rdata;
ADDR_DATA1: rdata = __data1_rdata;
ADDR_DATA2: rdata = __data2_rdata;
ADDR_DATA3: rdata = __data3_rdata;
default: rdata = 32'h0;
endcase
csr_read_o = csr_read_wdata & {1{__csr_wen}};
csr_write_o = csr_write_wdata & {1{__csr_wen}};
data0_wen = __data0_wen;
data0_o = data0_wdata;
data0_ren = __data0_ren;
data1_wen = __data1_wen;
data1_o = data1_wdata;
data1_ren = __data1_ren;
data2_wen = __data2_wen;
data2_o = data2_wdata;
data2_ren = __data2_ren;
data3_wen = __data3_wen;
data3_o = data3_wdata;
data3_ren = __data3_ren;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
addr_o <= 32'h0;
end else begin
if (__addr_wen) addr_o <= addr_wdata;
end
end
endmodule
| 8.774598 |
module apb_decode #(
parameter PORTS = 3, // Output ports
BOTREGION = 1024, // Address first port
REGION = 3072, // address locations/port
TOP_DEFAULT = 0 // All unadressed accesses go to top p_sel bus
) (
// APB input (slave)
input [31:0] s_paddr, // ls 2 bits are unused
input s_pwrite,
input s_psel,
input s_penable,
input [31:0] s_pwdata,
output [31:0] s_prdata,
output s_pready,
output s_pslverr,
// APB output (master)
output [ 31:0] m_paddr, // ls 2 bits always 0
output m_pwrite,
output reg [ PORTS-1:0] m_psel,
output m_penable,
output [ 31:0] m_pwdata,
input [PORTS*32-1:0] m_prdata,
input [ PORTS-1:0] m_pready,
input [ PORTS-1:0] m_pslverr
);
localparam BOT = BOTREGION, // inclusive
TOP = BOTREGION + REGION * PORTS; // exclusive
// How many address bits do we need?
localparam SELBITS = PORTS<=2 ? 1 :
PORTS<=4 ? 2 :
PORTS<=8 ? 3 :
PORTS<=16 ? 4 :
PORTS<=32 ? 5 :
PORTS<=64 ? 6 :
0 ; // this should hopefully raise an error in synthesis
wire select_error;
reg [SELBITS-1:0] select_bits; // Index bits
// A lot of signals pass-through
assign m_paddr = s_paddr;
assign m_pwrite = s_pwrite;
assign m_penable = s_penable;
assign m_pwdata = s_pwdata;
// Address map split up
always @(*) begin : dec
integer adrs_loop;
select_bits = 0;
for (adrs_loop = BOT + REGION; adrs_loop < TOP; adrs_loop = adrs_loop + REGION) begin
// #1; // Used only to debug loop
if (s_paddr >= adrs_loop) select_bits = select_bits + 1;
end
end
assign select_error = !(s_paddr >= BOT && s_paddr < TOP);
always @(*) begin
if (select_error) begin
if (TOP_DEFAULT) m_psel = s_psel << (PORTS - 1);
else m_psel = {PORTS{1'b0}};
end else m_psel = s_psel << select_bits;
end
//
// return signals
//
// return data
assign s_prdata = m_prdata[select_bits*32+:32];
// return error from port or local error
assign s_pslverr = (m_pslverr[select_bits] | (select_error & ~TOP_DEFAULT));
// return ready from port or on local error
assign s_pready = (m_pready[select_bits] | (select_error & ~TOP_DEFAULT));
/*
// Alternative is to make all return signals zero if this
// module is not selected. That way you can OR all busses
// together at a higher level
// But that works only if all modules stick to that rule!!
wire for_me = p_sel & p_enable;
assign s_prdata = for_me ? m_prdata[select_bits*32 +: 32] : 32'h0;
assign s_pslverr = for_me & (m_pslverr[select_bits] | (select_error & ~TOP_DEFAULT));
assign s_pready = for_me & (m_pready[select_bits] | (select_error & ~TOP_DEFAULT));
*/
endmodule
| 8.571854 |
module apb_edgeirq (
// system
input reset_n,
input enable, // clock gating
// APB
input pclk,
input [ 2:0] paddr, // ls 2 bits are unused
input pwrite,
input psel,
input penable,
input [31:0] pwdata,
output reg [31:0] prdata,
output pready,
output pslverr,
output irq,
// Interface
input [3:0] irq_posedge
);
reg [3:0] edge_detect; // Needed to detect rising edge
reg [3:0] irq_control; // enable bit per IRQ input
reg [3:0] irq_edgeseen; // Set if rising edge was seen
wire [3:0] irq_pending; // IRQs currently active (set & enabled)
wire apb_write = psel & penable & pwrite;
wire apb_read = psel & ~pwrite;
assign pready = 1'b1;
assign pslverr = 1'b0;
assign irq_pending = irq_edgeseen & irq_control;
assign irq = |irq_pending;
always @(posedge pclk or negedge reset_n) begin : rr
integer b;
if (!reset_n) begin
edge_detect <= 4'h0;
irq_edgeseen <= 4'h0;
irq_control <= 4'h0;
prdata <= 32'h0;
end // reset
else if (enable)
begin
edge_detect <= irq_posedge;
for (b = 0; b < 4; b = b + 1) begin
// on an arrving rising edge always set detected
if (~edge_detect[b] & irq_posedge[b]) irq_edgeseen[b] <= 1'b1;
else begin
// If user wrises status register, clear when write bit is set
if (apb_write && (paddr == 3'h4) && pwdata[b]) irq_edgeseen[b] <= 1'b0;
end
end
if (apb_write) begin
case (paddr)
3'h0: irq_control <= pwdata[3:0];
// 3'h4 : Done above
endcase
end // write
// irq_posedge can be one pulse so is not worth reading back
// return irq_edgeseen status instead
if (apb_read) begin
case (paddr)
3'h0: prdata <= {28'h0, irq_control};
3'h4: prdata <= {24'h0, irq_pending, irq_edgeseen};
endcase
end // read
else prdata <= 32'h0; // so we can OR all busses
end // clocked
end // always
endmodule
| 7.482032 |
module apb_edgeirq_test;
`define ENBL_REG 16'h0
`define STAT_REG 16'h4
localparam CLK_PERIOD = 100;
// system
reg reset_n;
reg enable; // clock gating
// APB
wire pclk;
wire [15:0] paddr; // ls 2 bits are unused
wire pwrite;
wire psel;
wire penable;
wire [31:0] pwdata;
wire [31:0] prdata;
wire pready;
wire pslverr;
wire irq;
// Interface
reg [ 3:0] irq_posedge;
integer i;
initial begin
// system
reset_n = 1'b0;
enable = 1'b1;
// Interface
irq_posedge = 4'h0;
@(posedge pclk) #(CLK_PERIOD * 5);
reset_n = 1'b1;
#(CLK_PERIOD * 5);
// Check each input individually
for (i = 0; i < 4; i = i + 1) begin
// Must be clear
apb_bus0.read(`STAT_REG, 32'h00);
apb_bus0.delay(1);
if (irq !== 0) begin
$display("%m@%0t: IRQ high (A) error", $time);
#1 $stop;
end
// Pulse irq high
@(posedge pclk) irq_posedge = 1 << i;
@(posedge pclk) irq_posedge = 0;
// Edge detect needs cycle
@(posedge pclk);
// Status must be set
apb_bus0.read(`STAT_REG, 1 << i);
// But IRQ must still be low
if (irq !== 1'b0) begin
$display("%m@%0t: IRQ high (B) error", $time);
#1 $stop;
end
// enable IRQ
apb_bus0.write(`ENBL_REG, 1 << i);
apb_bus0.delay(2); // wait for write to complete
// IRQ must now be high
if (irq !== 1'b1) begin
$display("%m@%0t: IRQ low (A) error", $time);
#1 $stop;
end
// Pending bit and irq bit must be set
apb_bus0.read(`STAT_REG, 32'h11 << i);
apb_bus0.delay(2); // wait for read to complete
// Clear by writing clear bit
apb_bus0.write(`STAT_REG, 1 << i);
apb_bus0.delay(2); // wait for write to complete
// Check IRQ must again be low
if (irq !== 1'b0) begin
$display("%m@%0t: IRQ high (C) error", $time);
#1 $stop;
end
// Status reg. must be clear
apb_bus0.read(`STAT_REG, 32'h00);
// Back to initial state
apb_bus0.write(`ENBL_REG, 0);
end
// Quick check for all patterns
apb_bus0.write(`ENBL_REG, 32'hF);
for (i = 0; i < 16; i = i + 1) begin
// Pulse interrupts high
@(posedge pclk) irq_posedge = i;
@(posedge pclk) irq_posedge = 0;
// Edge detect needs cycle
@(posedge pclk);
apb_bus0.read(`STAT_REG, {24'h0, i[3:0], i[3:0]});
apb_bus0.write(`STAT_REG, i); // clear again
apb_bus0.delay(2);
end
apb_bus0.delay(3);
if (apb_bus0.errors == 0) $display("apb_edgeirq test passed");
else $display("apb_edgeirq test FAILED!");
#500 $stop;
end
apb_edgeirq apb_edgeirq_0 (
// system
.reset_n(reset_n),
.enable (enable), // clock gating
// APB
.pclk (pclk),
.paddr (paddr[2:0]), // ls 2 bits are unused
.pwrite (pwrite),
.psel (psel),
.penable(penable),
.pwdata (pwdata),
.prdata (prdata),
.pready (pready),
.pslverr(pslverr),
.irq(irq),
// Interface
.irq_posedge(irq_posedge)
);
apb_bus #(
.CLKPER(CLK_PERIOD)
) apb_bus0 (
// APB
.pclk (pclk),
.paddr (paddr), // ls 2 bits are unused
.pwrite (pwrite),
.psel (psel),
.penable(penable),
.pwdata (pwdata),
.prdata (prdata),
.pready (pready),
.pslverr(pslverr)
);
endmodule
| 6.704237 |
module apb_event_unit #(
parameter APB_ADDR_WIDTH = 12 //APB slaves are 4KB by default
) (
clk_i,
HCLK,
HRESETn,
PADDR,
PWDATA,
PWRITE,
PSEL,
PENABLE,
PRDATA,
PREADY,
PSLVERR,
irq_i,
event_i,
irq_o,
fetch_enable_i,
fetch_enable_o,
clk_gate_core_o,
core_busy_i
);
//parameter APB_ADDR_WIDTH = 12;
input wire clk_i;
input wire HCLK;
input wire HRESETn;
input wire [APB_ADDR_WIDTH - 1:0] PADDR;
input wire [31:0] PWDATA;
input wire PWRITE;
input wire PSEL;
input wire PENABLE;
output reg [31:0] PRDATA;
output reg PREADY;
output reg PSLVERR;
input wire [31:0] irq_i;
input wire [31:0] event_i;
output wire [31:0] irq_o;
input wire fetch_enable_i;
output wire fetch_enable_o;
output wire clk_gate_core_o;
input wire core_busy_i;
wire [31:0] events;
reg [2:0] psel_int;
wire [2:0] pready;
wire [2:0] pslverr;
wire [1:0] slave_address_int;
wire [95:0] prdata;
reg fetch_enable_ff1;
reg fetch_enable_ff2;
wire fetch_enable_int;
assign fetch_enable_o = fetch_enable_ff2 & fetch_enable_int;
assign slave_address_int = PADDR[5:4];
always @(*) begin
psel_int = 3'b000;
psel_int[slave_address_int] = PSEL;
end
always @(*)
if (psel_int != 2'b00) begin
PRDATA = prdata[slave_address_int*32+:32];
PREADY = pready[slave_address_int];
PSLVERR = pslverr[slave_address_int];
end else begin
PRDATA = 1'sb0;
PREADY = 1'b1;
PSLVERR = 1'b0;
end
generic_service_unit #(
.APB_ADDR_WIDTH(APB_ADDR_WIDTH)
) i_interrupt_unit (
.HCLK(HCLK),
.HRESETn(HRESETn),
.PADDR(PADDR),
.PWDATA(PWDATA),
.PWRITE(PWRITE),
.PSEL(psel_int[0]),
.PENABLE(PENABLE),
.PRDATA(prdata[0+:32]),
.PREADY(pready[0]),
.PSLVERR(pslverr[0]),
.signal_i(irq_i),
.irq_o(irq_o)
);
generic_service_unit #(
.APB_ADDR_WIDTH(APB_ADDR_WIDTH)
) i_event_unit (
.HCLK(HCLK),
.HRESETn(HRESETn),
.PADDR(PADDR),
.PWDATA(PWDATA),
.PWRITE(PWRITE),
.PSEL(psel_int[1]),
.PENABLE(PENABLE),
.PRDATA(prdata[32+:32]),
.PREADY(pready[1]),
.PSLVERR(pslverr[1]),
.signal_i(event_i),
.irq_o(events)
);
sleep_unit #(
.APB_ADDR_WIDTH(APB_ADDR_WIDTH)
) i_sleep_unit (
.HCLK(HCLK),
.HRESETn(HRESETn),
.PADDR(PADDR),
.PWDATA(PWDATA),
.PWRITE(PWRITE),
.PSEL(psel_int[2]),
.PENABLE(PENABLE),
.PRDATA(prdata[64+:32]),
.PREADY(pready[2]),
.PSLVERR(pslverr[2]),
.irq_i(|irq_o),
.event_i(|events),
.core_busy_i(core_busy_i),
.fetch_en_o(fetch_enable_int),
.clk_gate_core_o(clk_gate_core_o)
);
always @(posedge clk_i or negedge HRESETn)
if (~HRESETn) begin
fetch_enable_ff1 <= 1'b0;
fetch_enable_ff2 <= 1'b0;
end else begin
fetch_enable_ff1 <= fetch_enable_i;
fetch_enable_ff2 <= fetch_enable_ff1;
end
endmodule
| 8.483797 |
module apb_fastdecode #(
parameter PORTS = 2, // Output ports
MS_SLVADR = 9, // Sets size of region
// 9=1K, 10=2K etc.
TOP_DEFAULT = 0 // Highest bus is default (no errors)
) (
// APB input (slave)
input [31:0] s_paddr, // ls 2 bits are unused
input s_pwrite,
input s_psel,
input s_penable,
input [31:0] s_pwdata,
output [31:0] s_prdata,
output s_pready,
output s_pslverr,
// APB output (master)
output [ MS_SLVADR:0] m_paddr,
output m_pwrite,
output [ PORTS-1:0] m_psel,
output m_penable,
output [ 31:0] m_pwdata,
input [PORTS*32-1:0] m_prdata,
input [ PORTS-1:0] m_pready,
input [ PORTS-1:0] m_pslverr
);
// How many address bits do we need?
localparam SELBITS = PORTS<=2 ? 1 :
PORTS<=4 ? 2 :
PORTS<=8 ? 3 :
PORTS<=16 ? 4 :
PORTS<=32 ? 5 :
PORTS<=64 ? 6 :
PORTS<=128 ? 7 :
0 ; // this should hopefully raise an error in synthesis
wire select_error;
wire [SELBITS-1:0] pre_select_bits, select_bits;
// A lot of signals pass-through
assign m_paddr = s_paddr[MS_SLVADR:0];
assign m_pwrite = s_pwrite;
assign m_penable = s_penable;
assign m_pwdata = s_pwdata;
// These bits define the port
assign pre_select_bits = s_paddr[MS_SLVADR+1 +: SELBITS];
// If too big we have an error
assign select_error = pre_select_bits>=PORTS;
// The final port bits: the original ones
// or on error and top-port-is-default, map on top port
assign select_bits = TOP_DEFAULT & select_error ? PORTS-1 : pre_select_bits;
// The sel bit of the right port is set
// None is set if error and NOT top_is_default
assign m_psel = ~TOP_DEFAULT & select_error ? {PORTS{1'b0}} : s_psel<<select_bits;
assign s_prdata = m_prdata[select_bits*32 +: 32];
// Return ready from port or ready on error
assign s_pready = m_pready[select_bits] | (~TOP_DEFAULT & select_error);
assign s_pslverr = m_pslverr[select_bits] | (~TOP_DEFAULT & select_error);
endmodule
| 8.826312 |
module apb_fc (
// CPU Interface Input (APB bus interface)
input wire PCLK, // APB clock
input wire PRESETB, // APB asynchronous reset (0: reset, 1: normal)
input wire [31:0] PADDR, // APB address
input wire PSEL, // APB select
input wire PENABLE, // APB enable
input wire PWRITE, // APB write enable
input wire [31:0] PWDATA, // APB write data
input wire [31:0] clk_counter,
input wire [31:0] max_index,
input wire [ 0:0] fc_done,
output reg [20:0] receive_size,
output reg [ 2:0] receiveCommand,
input wire feature_receive_done,
input wire bias_receive_done,
input wire weight_receive_done,
// CPU Interface Output (APB bus interface)
output wire [31:0] PRDATA
);
wire state_enable;
wire state_enable_pre;
reg [31:0] prdata_reg;
assign state_enable = PSEL & PENABLE;
assign state_enable_pre = PSEL & ~PENABLE;
// READ OUTPUT
always @(posedge PCLK, negedge PRESETB) begin
if (PRESETB == 1'b0) begin
prdata_reg <= 32'h00000000;
end else begin
if (~PWRITE & state_enable_pre) begin
case ({
PADDR[31:2], 2'h0
})
/*READOUT*/
32'h00000000: prdata_reg <= receiveCommand;
32'h00000004: prdata_reg <= receive_size;
32'h00000008: prdata_reg <= weight_receive_done;
32'h0000000c: prdata_reg <= fc_done;
32'h00000010: prdata_reg <= feature_receive_done;
32'h00000014: prdata_reg <= bias_receive_done;
32'h0000001c: prdata_reg <= clk_counter;
32'h00000020: prdata_reg <= max_index;
default: prdata_reg <= 32'h0;
endcase
end else begin
prdata_reg <= 32'h0;
end
end
end
assign PRDATA = (~PWRITE & state_enable) ? prdata_reg : 32'h00000000;
// WRITE ACCESS
always @(posedge PCLK, negedge PRESETB) begin
if (PRESETB == 1'b0) begin
/*WRITERES*/
receiveCommand <= 0;
receive_size <= 0;
end else begin
if (PWRITE & state_enable) begin
case ({
PADDR[31:2], 2'h0
})
/*WRITEIN*/
32'h00000000: begin
receiveCommand <= PWDATA[2:0];
end
32'h00000004: begin
receive_size <= PWDATA[20:0];
end
default: ;
endcase
end
end
end
endmodule
| 7.688624 |
module apb_fifo (
// system
input reset_n,
input enable, // clock gating
// APB
input pclk,
input [ 3:0] paddr, // ls 2 bits are unused
input pwrite,
input psel,
input penable,
input [31:0] pwdata,
output reg [31:0] prdata,
output pready,
output pslverr,
// Interface
output ff_write,
output ff_read,
output reg ff_clear,
input [7:0] ff_rdata,
input ff_full,
input ff_empty,
input [8:0] ff_level
);
wire apb_write = psel & penable & pwrite;
wire apb_read = psel & ~pwrite;
assign pready = 1'b1;
assign pslverr = 1'b0;
// Fifo write pulse must come whilst apb_wdata is present
// (Thus not after cycle has finished)
assign ff_write = psel & penable & pwrite & (paddr == 4'h0);
// Fifo read pulse must come on last cycle
// That makes FIFO finishes at the same time as the read cycle
// and thus the status read on the next APB read is correct
assign ff_read = psel & penable & ~pwrite & (paddr == 4'h0);
always @(posedge pclk or negedge reset_n) begin
if (!reset_n) begin
ff_clear <= 1'b0;
prdata <= 32'h0;
end // reset
else if (enable)
begin
ff_clear <= 1'b0;
if (apb_write) begin
case (paddr)
// 4'h0 : Write to FIFO, not registers
4'h4: ff_clear <= pwdata[0];
endcase
end // write
if (apb_read) begin
case (paddr)
4'h0: prdata <= {24'h0, ff_rdata};
4'h4: prdata <= {15'h0, ff_level, 6'h0, ff_full, ff_empty};
endcase
end // read
else prdata <= 32'h0;
end // clocked
end // always
endmodule
| 7.166059 |
module apb_fifo_test;
`define DATA_REG 16'h0
`define STAT_REG 16'h4
`define SR_EMPTY 32'h00000001
`define SR_FULL 32'h00000002
localparam CLK_PERIOD = 100;
// system
reg reset_n;
reg enable; // clock gating
// APB
wire pclk;
wire [15:0] paddr; // ls 2 bits are unused
wire pwrite;
wire psel;
wire penable;
wire [31:0] pwdata;
wire [31:0] prdata;
wire pready;
wire pslverr;
// Interface
wire ff_write;
wire ff_read;
wire ff_clear;
wire [ 7:0] ff_rdata;
wire ff_full;
wire ff_empty;
wire [ 8:0] ff_level;
// testbench
integer i;
initial begin
// system
reset_n = 1'b0;
enable = 1'b1;
@(posedge pclk) #(CLK_PERIOD * 5);
reset_n = 1'b1;
#(CLK_PERIOD * 5);
// After reset check status reg is correct: only empty bit set
apb_bus0.read(`STAT_REG, `SR_EMPTY);
apb_bus0.write(`DATA_REG, 32'h00000044); // write byte
apb_bus0.read(`STAT_REG, 32'h00000100); // level = 1, not empty, Not full
apb_bus0.read(`DATA_REG, 32'h00000044); // read byte
apb_bus0.read(`STAT_REG, `SR_EMPTY);
#(CLK_PERIOD * 25);
// Check filling up
for (i = 0; i < 255; i = i + 1) begin
apb_bus0.write(`DATA_REG, i); // write byte
apb_bus0.read(`STAT_REG, (i + 1) << 8); // level, not empty, Not full
end
apb_bus0.write(`DATA_REG, 0); // write byte
apb_bus0.read(`STAT_REG, (256 << 8) | `SR_FULL); // level=256, Full
// Check if clear works
apb_bus0.write(`STAT_REG, 0); // should fail
apb_bus0.read(`STAT_REG, (256 << 8) | `SR_FULL); // level=256, Full
apb_bus0.write(`STAT_REG, 0); // should work
apb_bus0.read(`STAT_REG, `SR_EMPTY); // level=256, Full
if (apb_bus0.errors == 0) $display("apb_fifo test passed");
else $display("apb_fifo test FAILED!");
#500 $stop;
end
apb_fifo apb_fifo_0 (
// system
.reset_n(reset_n),
.enable (enable), // clock gating
// APB
.pclk (pclk),
.paddr (paddr[3:0]), // ls 2 bits are unused
.pwrite (pwrite),
.psel (psel),
.penable(penable),
.pwdata (pwdata),
.prdata (prdata),
.pready (pready),
.pslverr(pslverr),
// Interface
.ff_write(ff_write),
.ff_read (ff_read),
.ff_clear(ff_clear),
.ff_rdata(ff_rdata),
.ff_full (ff_full),
.ff_empty(ff_empty),
.ff_level(ff_level)
);
sync_fifo #(
.WI (8),
.L2D (8),
.REGFLAGS(0)
) // parameters
sync_fifo_256x8 (
.clk (pclk),
.reset_n(reset_n),
.enable (enable),
.clear (ff_clear),
.wdata(pwdata[7:0]), // APB bus direct to FIFO
.write(ff_write),
.rdata(ff_rdata),
.read (ff_read),
.full (ff_full),
.empty(ff_empty),
.level(ff_level)
);
apb_bus #(
.CLKPER(CLK_PERIOD)
) apb_bus0 (
// APB
.pclk (pclk),
.paddr (paddr), // ls 2 bits are unused
.pwrite (pwrite),
.psel (psel),
.penable(penable),
.pwdata (pwdata),
.prdata (prdata),
.pready (pready),
.pslverr(pslverr)
);
endmodule
| 7.372279 |
module APB_FSM_CONT (
HCLK,
HRESETn,
VALID,
TSELx,
TPADDR1,
TPADDR2,
TPWDATA1,
TPWDATA2,
HWRITEreg,
PRDATA,
HWRITE,
PENABLE,
PSELx,
PADDR,
PWDATA,
HRDATA,
PWRITE,
HRESP,
HREADY_OUT
);
input HCLK, //reference signal HCLK
HRESETn, //reset signal HRESETn
VALID, //handshaking signal VALID
HWRITEreg, HWRITE;
input [31:0] TPADDR1, TPADDR2, //Transmition addresses signals
TPWDATA1, TPWDATA2, //Transmission data signals
PRDATA;
input [2:0] TSELx;
output reg PENABLE, //control signals
PWRITE, HREADY_OUT;
output reg [2:0] PSELx;
output reg [31:0] PADDR, //slave address signal
PWDATA; //Transmission data signal
output [31:0] HRDATA;
output [1:0] HRESP;
reg PENABLE_TEMP, HREADY_OUT_TEMP, PWRITE_TEMP;
reg [2:0] PSELx_TEMP;
reg [31:0] PADDR_TEMP, PWDATA_TEMP;
reg [2:0] CURR_STATE, NEXT_STATE;
reg [31:0] ADDR;
//define state
parameter S_IDLE = 3'b000; //IDLE
parameter S_READ = 3'b001; //READ SETUP
parameter S_REN = 3'b010; //READ ENABLE
parameter S_WWAIT = 3'b011; //WAITING FOR HWDATA
parameter S_WRITE = 3'b100; //WRITE SETUP(no need for a pending)
parameter S_WRITEP = 3'b101; //WRITE SETUP(need a pending cycle)
parameter S_WENP = 3'b110; //WRITE ENABLE(insert a pedning cycle)
parameter S_WEN = 3'b111; //WRITE ENBALE(no need for a pending)
always @(posedge HCLK) begin
if (HRESETn) CURR_STATE <= S_IDLE;
else CURR_STATE <= NEXT_STATE;
end
always @(*) begin
NEXT_STATE = S_IDLE;
case (CURR_STATE)
S_IDLE:
if (VALID && HWRITE) NEXT_STATE = S_WWAIT;
else if (VALID && (~HWRITE)) NEXT_STATE = S_READ;
else NEXT_STATE = S_IDLE;
S_WWAIT:
if (!VALID) NEXT_STATE = S_WRITE;
else NEXT_STATE = S_WRITEP;
S_WRITEP: NEXT_STATE = S_WENP;
S_WENP:
if ((!VALID) && HWRITEreg) NEXT_STATE = S_WRITE;
else if (~HWRITEreg) NEXT_STATE = S_READ;
S_WEN:
if (!VALID) NEXT_STATE = S_IDLE;
else if (VALID && HWRITE) NEXT_STATE = S_WWAIT;
else if (VALID && (!HWRITE)) NEXT_STATE = S_READ;
S_REN:
if (!VALID) NEXT_STATE = S_IDLE;
else if (VALID && HWRITE) NEXT_STATE = S_WWAIT;
else if (VALID && (!HWRITE)) NEXT_STATE = S_READ;
S_READ: NEXT_STATE = S_REN;
S_WRITE:
if (!VALID) NEXT_STATE = S_WEN;
else NEXT_STATE = S_WENP;
endcase
end
always @(posedge HCLK or posedge HRESETn) begin
PENABLE_TEMP = 0;
PSELx_TEMP = 0;
PADDR_TEMP = 0;
PWDATA_TEMP = 0;
HREADY_OUT_TEMP = 0;
PWRITE_TEMP = 0;
case (CURR_STATE)
S_IDLE: begin
HREADY_OUT_TEMP = 1;
end
S_WWAIT: begin
HREADY_OUT_TEMP = 1;
end
S_WRITEP: begin
PWDATA_TEMP = TPWDATA1;
PWRITE_TEMP = 1;
PSELx_TEMP = TSELx;
PADDR_TEMP = TPADDR2;
ADDR = PADDR_TEMP;
end
S_WENP: begin
PWRITE_TEMP = 1;
PENABLE_TEMP = 1;
PSELx_TEMP = TSELx;
PADDR_TEMP = ADDR;
PWDATA_TEMP = TPWDATA2;
HREADY_OUT_TEMP = 1;
end
S_WEN: begin
PWDATA_TEMP = TPWDATA1;
PADDR_TEMP = TPADDR1;
PENABLE_TEMP = 1;
PSELx_TEMP = TSELx;
HREADY_OUT_TEMP = 1;
PWRITE_TEMP = 1;
end
S_REN: begin
PENABLE_TEMP = 1;
HREADY_OUT_TEMP = 1;
PADDR_TEMP = TPADDR2;
PSELx_TEMP = TSELx;
end
S_READ: begin
PADDR_TEMP = TPADDR1;
PSELx_TEMP = TSELx;
HREADY_OUT_TEMP = 0;
end
S_WRITE: begin
PWDATA_TEMP = TPWDATA1;
PADDR_TEMP = TPADDR1;
PWRITE_TEMP = 1;
PSELx_TEMP = TSELx;
PENABLE_TEMP = 0;
HREADY_OUT_TEMP = 1;
end
endcase
end
always @(posedge HCLK or posedge HRESETn) begin
if (HRESETn) begin
PENABLE <= 0;
PSELx <= 0;
PADDR <= 0;
PWDATA <= 0;
HREADY_OUT <= 0;
PWRITE <= 0;
end else begin
PENABLE <= PENABLE_TEMP;
PSELx <= PSELx_TEMP;
PADDR <= PADDR_TEMP;
PWDATA <= PWDATA_TEMP;
HREADY_OUT <= HREADY_OUT_TEMP;
PWRITE <= PWRITE_TEMP;
end
end
assign HRDATA = PRDATA;
assign HRESP = 0;
endmodule
| 6.689181 |
module apb_i2c #(
parameter APB_ADDR_WIDTH = 12 //APB slaves are 4KB by default
) (
HCLK,
HRESETn,
PADDR,
PWDATA,
PWRITE,
PSEL,
PENABLE,
PRDATA,
PREADY,
PSLVERR,
interrupt_o,
scl_pad_i,
scl_pad_o,
scl_padoen_o,
sda_pad_i,
sda_pad_o,
sda_padoen_o
);
//parameter APB_ADDR_WIDTH = 12;
input wire HCLK;
input wire HRESETn;
input wire [APB_ADDR_WIDTH - 1:0] PADDR;
input wire [31:0] PWDATA;
input wire PWRITE;
input wire PSEL;
input wire PENABLE;
output reg [31:0] PRDATA;
output wire PREADY;
output wire PSLVERR;
output reg interrupt_o;
input wire scl_pad_i;
output wire scl_pad_o;
output wire scl_padoen_o;
input wire sda_pad_i;
output wire sda_pad_o;
output wire sda_padoen_o;
wire [3:0] s_apb_addr;
reg [15:0] r_pre;
reg [7:0] r_ctrl;
reg [7:0] r_tx;
wire [7:0] s_rx;
reg [7:0] r_cmd;
wire [7:0] s_status;
wire s_done;
wire s_core_en;
wire s_ien;
wire s_irxack;
reg rxack;
reg tip;
reg irq_flag;
wire i2c_busy;
wire i2c_al;
reg al;
assign s_apb_addr = PADDR[5:2];
always @(posedge HCLK or negedge HRESETn)
if (~HRESETn) begin
r_pre <= 'h0;
r_ctrl <= 'h0;
r_tx <= 'h0;
r_cmd <= 'h0;
end else if ((PSEL && PENABLE) && PWRITE) begin
if (s_done | i2c_al) r_cmd[7:4] <= 4'h0;
r_cmd[2:1] <= 2'b00;
r_cmd[0] <= 1'b0;
case (s_apb_addr)
3'b000: r_pre <= PWDATA[15:0];
3'b001: r_ctrl <= PWDATA[7:0];
3'b100: r_tx <= PWDATA[7:0];
3'b101: if (s_core_en) r_cmd <= PWDATA[7:0];
endcase
end else begin
if (s_done | i2c_al) r_cmd[7:4] <= 4'h0;
r_cmd[2:1] <= 2'b00;
r_cmd[0] <= 1'b0;
end
always @(*)
case (s_apb_addr)
3'b000: PRDATA = {16'h0000, r_pre};
3'b001: PRDATA = {24'h000000, r_ctrl};
3'b010: PRDATA = {24'h000000, s_rx};
3'b011: PRDATA = {24'h000000, s_status};
3'b100: PRDATA = {24'h000000, r_tx};
3'b101: PRDATA = {24'h000000, r_cmd};
default: PRDATA = 'h0;
endcase
wire sta = r_cmd[7];
wire sto = r_cmd[6];
wire rd = r_cmd[5];
wire wr = r_cmd[4];
wire ack = r_cmd[3];
wire iack = r_cmd[0];
assign s_core_en = r_ctrl[7];
assign s_ien = r_ctrl[6];
i2c_master_byte_ctrl byte_controller (
.clk(HCLK),
.nReset(HRESETn),
.ena(s_core_en),
.clk_cnt(r_pre),
.start(sta),
.stop(sto),
.read(rd),
.write(wr),
.ack_in(ack),
.din(r_tx),
.cmd_ack(s_done),
.ack_out(s_irxack),
.dout(s_rx),
.i2c_busy(i2c_busy),
.i2c_al(i2c_al),
.scl_i(scl_pad_i),
.scl_o(scl_pad_o),
.scl_oen(scl_padoen_o),
.sda_i(sda_pad_i),
.sda_o(sda_pad_o),
.sda_oen(sda_padoen_o)
);
always @(posedge HCLK or negedge HRESETn)
if (!HRESETn) begin
al <= 1'b0;
rxack <= 1'b0;
tip <= 1'b0;
irq_flag <= 1'b0;
end else begin
al <= i2c_al | (al & ~sta);
rxack <= s_irxack;
tip <= rd | wr;
irq_flag <= ((s_done | i2c_al) | irq_flag) & ~iack;
end
always @(posedge HCLK or negedge HRESETn)
if (!HRESETn) interrupt_o <= 1'b0;
else interrupt_o <= irq_flag && s_ien;
assign s_status[7] = rxack;
assign s_status[6] = i2c_busy;
assign s_status[5] = al;
assign s_status[4:2] = 3'h0;
assign s_status[1] = tip;
assign s_status[0] = irq_flag;
assign PREADY = 1'b1;
assign PSLVERR = 1'b0;
endmodule
| 8.863317 |
module apb_i2c_ic ( ////top module
input wire PCLK,
input wire PRESETn,
input wire PSEL,
input wire PENABLE,
input wire PWrite,
input wire [31:0] PADDR,
input wire [31:0] PWDATA,
output [31:0] PRDATA,
output PREADY,
output PSLVERR,
inout i2c_scl,
inout i2c_sda
);
wire [ 7:0] i2c_con1;
wire [ 7:0] i2c_con2;
wire [ 7:0] i2c_stat;
wire [31:0] Din;
wire [31:0] Dout;
apb_slave apb (
.PCLK(PCLK),
.PRESETn(PRESETn),
.PSEL(PSEL),
.PENABLE(PENABLE),
.PWrite(PWrite),
.PADDR(PADDR),
.PWDATA(PWDATA),
.Dout(Dout),
.ready(ready),
.i2c_stat(i2c_stat),
.i2c_con1(i2c_con1),
.i2c_con2(i2c_con2),
.PRDATA(PRDATA),
.Din(Din),
.PREADY(PREADY),
.PSLVERR(PSLVERR)
);
i2c_bridge bridge (
.PCLK(PCLK),
.i2c_con1(i2c_con1),
.i2c_con2(i2c_con2),
.Din(Din), // from apb
.Dout(Dout), // to apb
.i2c_stat(i2c_stat),
.i2c_scl(i2c_scl),
.ready(ready),
.i2c_sda(i2c_sda)
);
endmodule
| 8.060032 |
module APB_I2C_SLAVE (
// APB SLAVE PORT INTERFACE
input PCLK,
input PRESETn,
input [`APB_ADDR_WIDTH-1:0] PADDR,
input PWRITE,
input PSEL,
input PENABLE,
input [`APB_DATA_WIDTH-1:0] PWDATA,
output [`APB_DATA_WIDTH-1:0] PRDATA,
output PREADY,
//Interrupt
output wire I2C_INT,
// I2C signals
// i2c clock line
input wire scl_pad_i, // SCL-line input
output wire scl_pad_o, // SCL-line output (always 1'b0)
output wire scl_padoen_o, // SCL-line output enable (active low)
// i2c data line
input wire sda_pad_i, // SDA-line input
output wire sda_pad_o, // SDA-line output (always 1'b0)
output wire sda_padoen_o // SDA-line output enable (active low)
);
i2c_master_top i2c_master_top (
.wb_clk_i(PCLK),
.wb_rst_i(!PRESETn),
.arst_i(), //NO ASYNC
.wb_adr_i(PADDR[7:3]),
.wb_dat_i(PWDATA),
.wb_dat_o(PRDATA),
.wb_we_i(PWRITE),
.wb_stb_i(PENABLE), //因为ENABLE信号比PSEL信号延后一个周期，故连接STB
.wb_cyc_i (PSEL), //因为PSEL信号在ENABLE信号前一周期出现，所以PSEL信号连接CYC
.wb_ack_o(PREADY),
.wb_inta_o(I2C_INT),
//I2C INTERFACE
.scl_pad_i(scl_pad_i),
.scl_pad_o(scl_pad_o),
.scl_padoen_o(scl_padoen_o),
.sda_pad_i(sda_pad_i),
.sda_pad_o(sda_pad_o),
.sda_padoen_o(sda_padoen_o)
);
endmodule
| 9.352512 |
module addr_dec #(
parameter BUS_WIDTH = 16,
parameter SLAVE_PORTS = 10
) (
input [ BUS_WIDTH-1:0] addr,
output [ SLAVE_PORTS-1:0] sel,
output reg [`clog2(SLAVE_PORTS)-1:0] seli
);
// binary bit output
// GPIO0
assign sel[`APB_PSELX_GPIO0] = ((addr >= `DEF_MMU_GPIO0_S) && (addr <= `DEF_MMU_GPIO0_E));
// GPIO1
assign sel[`APB_PSELX_GPIO1] = ((addr >= `DEF_MMU_GPIO1_S) && (addr <= `DEF_MMU_GPIO1_E));
// GPIO2
assign sel[`APB_PSELX_GPIO2] = ((addr >= `DEF_MMU_GPIO2_S) && (addr <= `DEF_MMU_GPIO2_E));
// UART0
assign sel[`APB_PSELX_UART0] = ((addr >= `DEF_MMU_UART0_S) && (addr <= `DEF_MMU_UART0_E));
// REGS0
assign sel[`APB_PSELX_REGS0] = ((addr >= `DEF_MMU_REGS0_S) && (addr <= `DEF_MMU_REGS0_E));
// BRAM0
assign sel[`APB_PSELX_BRAM0] = ((addr >= `DEF_MMU_BRAM0_S) && (addr <= `DEF_MMU_BRAM0_E));
// TIMR0
assign sel[`APB_PSELX_TIMR0] = ((addr >= `DEF_MMU_TIMR0_S) && (addr <= `DEF_MMU_TIMR0_E));
// WDOG0
assign sel[`APB_PSELX_WDOG0] = ((addr >= `DEF_MMU_WDOG0_S) && (addr <= `DEF_MMU_WDOG0_E));
// PERR0
// Bus error recovery for bad PADDR mmu addresses.
assign sel[`APB_PSELX_PERR0] = ~(|sel[`APB_PSELX_WDOG0:`APB_PSELX_GPIO0]);
// binary number output
always @(*)
if ((addr >= `DEF_MMU_GPIO0_S) && (addr <= `DEF_MMU_GPIO0_E)) seli = `APB_PSELX_GPIO0;
else if ((addr >= `DEF_MMU_GPIO1_S) && (addr <= `DEF_MMU_GPIO1_E)) seli = `APB_PSELX_GPIO1;
else if ((addr >= `DEF_MMU_GPIO2_S) && (addr <= `DEF_MMU_GPIO2_E)) seli = `APB_PSELX_GPIO2;
else if ((addr >= `DEF_MMU_UART0_S) && (addr <= `DEF_MMU_UART0_E)) seli = `APB_PSELX_UART0;
else if ((addr >= `DEF_MMU_REGS0_S) && (addr <= `DEF_MMU_REGS0_E)) seli = `APB_PSELX_REGS0;
else if ((addr >= `DEF_MMU_BRAM0_S) && (addr <= `DEF_MMU_BRAM0_E)) seli = `APB_PSELX_BRAM0;
else if ((addr >= `DEF_MMU_TIMR0_S) && (addr <= `DEF_MMU_TIMR0_E)) seli = `APB_PSELX_TIMR0;
else if ((addr >= `DEF_MMU_WDOG0_S) && (addr <= `DEF_MMU_WDOG0_E)) seli = `APB_PSELX_WDOG0;
else if (sel[`APB_PSELX_PERR0]) seli = `APB_PSELX_PERR0;
else seli = 0;
endmodule
| 7.175933 |
module apb_interface (
pwrite,
penable,
psel,
paddr,
pwdata,
pwrite_out,
penable_out,
psel_out,
paddr_out,
pwdata_out,
prdata
);
input pwrite, penable;
input [2:0] psel;
input [31:0] paddr, pwdata;
output pwrite_out, penable_out;
output [2:0] psel_out;
output [31:0] paddr_out, pwdata_out, prdata;
assign pwrite_out = pwrite;
assign penable_out = penable;
assign psel_out = psel;
assign paddr_out = paddr;
assign pwdata_out = pwdata;
assign prdata = (!pwrite && penable) ? {$random} : 32'hzz;
endmodule
| 6.87051 |
module APB_INTERFACE (
input PCLK,
input [31:0] PADDR,
input [31:0] PWDATA,
input PRESETn,
input PWRITE,
input [1:0] PSEL,
input [2:0] PPROT,
output reg [31:0] PRDATA,
output reg PREADY,
output reg PSLVERR,
output [1:0] REGSEL,
input [7:0] BUSRDATA,
output clk,
output rst_n,
output BUSW,
output reg [7:0] BUSWDATA
);
parameter [1:0] SELECT = 3'b00, READY = 3'b10, ERROR = 3'b11;
reg [1:0] state, next_state;
assign clk = PCLK;
assign rst_n = PRESETn;
assign BUSW = PWRITE;
assign REGSEL = PADDR[1:0];
always @(posedge PCLK, negedge PRESETn) begin
if (!PRESETn) state <= SELECT;
else begin
state <= next_state;
end
end
always @(PSEL, state) begin
case (state)
SELECT: begin
if (PSEL == 2'b01) begin
PREADY <= 0;
PSLVERR <= 0;
next_state <= READY;
if (PWRITE) BUSWDATA <= PWDATA[7:0];
else PRDATA[7:0] <= BUSRDATA;
end else next_state <= SELECT;
end
READY: begin
PREADY <= 1;
next_state <= SELECT;
end
ERROR: begin
PSLVERR <= 1;
next_state <= SELECT;
end
default: next_state <= SELECT;
endcase
end
endmodule
| 8.75567 |
module APB_Keyboard (
input wire clk,
rst_n,
input wire [3:0] col_in,
output wire [3:0] row,
output wire [31:0] PRDATA,
output wire KeyboardINT
);
wire [15:0] keyn;
wire [15:0] key;
wire [3:0] col_out;
wire [1:0] hi;
wire row_rdy;
reg [15:0] KeyINT;
KeyToCol KeyToCol (
.clk (clk),
.rst_n (rst_n),
.col_in (col_in),
.row (row),
.col_out(col_out),
.hi (hi),
.row_rdy(row_rdy),
.row_old(keyn)
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
KeyINT <= 16'b0;
end else if (KeyboardINT) begin
case (hi)
2'b00: KeyINT[3:0] <= col_out;
2'b01: KeyINT[7:4] <= col_out;
2'b10: KeyINT[11:8] <= col_out;
2'b11: KeyINT[15:12] <= col_out;
endcase
end
end
assign KeyboardINT = row_rdy & (|(~col_out));
assign PRDATA = {KeyINT, key};
assign key = ~keyn;
endmodule
| 8.155701 |
module apb_levirq (
// system
input reset_n,
input enable, // clock gating
// APB
input pclk,
input [ 2:0] paddr, // ls 2 bits are unused
input pwrite,
input psel,
input penable,
input [31:0] pwdata,
output reg [31:0] prdata,
output pready,
output pslverr,
output irq,
// Interface
input [3:0] irq_request
);
reg [3:0] irq_control; // enable bit per IRQ input
wire [3:0] irq_pending; //
wire apb_write = psel & penable & pwrite;
wire apb_read = psel & ~pwrite;
assign pready = 1'b1;
assign pslverr = 1'b0;
assign irq_pending = irq_request & irq_control;
assign irq = |irq_pending;
always @(posedge pclk or negedge reset_n) begin
if (!reset_n) begin
irq_control <= 4'h0;
prdata <= 32'h0;
end // reset
else if (enable)
begin
if (apb_write) begin
case (paddr)
3'h0: irq_control <= pwdata[3:0];
//3'h4 : status : read only
endcase
end // write
if (apb_read) begin
case (paddr)
3'h0: prdata <= {28'h0, irq_control};
3'h4: prdata <= {24'h0, irq_pending, irq_request};
endcase
end // read
else prdata <= 32'h0; // so we can OR all busses
end // clocked
end // always
endmodule
| 7.842738 |
module apb_levirq_test;
`define ENBL_REG 16'h0
`define STAT_REG 16'h4
localparam CLK_PERIOD = 100;
// system
reg reset_n;
reg enable; // clock gating
// APB
wire pclk;
wire [15:0] paddr; // ls 2 bits are unused
wire pwrite;
wire psel;
wire penable;
wire [31:0] pwdata;
wire [31:0] prdata;
wire pready;
wire pslverr;
wire irq;
// Interface
reg [ 3:0] irq_request;
integer i;
initial begin
// system
reset_n = 1'b0;
enable = 1'b1;
// Interface
irq_request = 4'h0;
@(posedge pclk) #(CLK_PERIOD * 5);
reset_n = 1'b1;
#(CLK_PERIOD * 5);
// Check each input individually
for (i = 0; i < 4; i = i + 1) begin
// Must be clear
apb_bus0.read(`STAT_REG, 32'h00);
apb_bus0.delay(1);
if (irq !== 0) begin
$display("%m@%0t: IRQ high (A) error", $time);
#1 $stop;
end
// Set irq high
irq_request = 1 << i;
// Status must be set
apb_bus0.read(`STAT_REG, 1 << i);
// But IRQ must still be low
if (irq !== 1'b0) begin
$display("%m@%0t: IRQ high (B) error", $time);
#1 $stop;
end
// enable IRQ
apb_bus0.write(`ENBL_REG, 1 << i);
apb_bus0.delay(2); // wait for write to complete
// IRQ must now be high
if (irq !== 1'b1) begin
$display("%m@%0t: IRQ low (A) error", $time);
#1 $stop;
end
// Pending bit and irq bit must be set
apb_bus0.read(`STAT_REG, 32'h11 << i);
apb_bus0.delay(1); // wait for read to complete
irq_request = 0;
#1;
// Check IRQ must again be low
if (irq !== 1'b0) begin
$display("%m@%0t: IRQ high (C) error", $time);
#1 $stop;
end
// Back to initial state
apb_bus0.write(`ENBL_REG, 0);
end
// Quick check for all patterns
apb_bus0.write(`ENBL_REG, 32'hF);
for (i = 0; i < 16; i = i + 1) begin
irq_request = i;
apb_bus0.read(`STAT_REG, {24'h0, i[3:0], i[3:0]});
apb_bus0.delay(2); // wait for read to complete
end
apb_bus0.delay(3);
if (apb_bus0.errors == 0) $display("apb_levirq test passed");
else $display("apb_levirq test FAILED!");
#500 $stop;
end
apb_levirq apb_levirq_0 (
// system
.reset_n(reset_n),
.enable (enable), // clock gating
// APB
.pclk (pclk),
.paddr (paddr[2:0]), // ls 2 bits are unused
.pwrite (pwrite),
.psel (psel),
.penable(penable),
.pwdata (pwdata),
.prdata (prdata),
.pready (pready),
.pslverr(pslverr),
.irq(irq),
// Interface
.irq_request(irq_request)
);
apb_bus #(
.CLKPER(CLK_PERIOD)
) apb_bus0 (
// APB
.pclk (pclk),
.paddr (paddr), // ls 2 bits are unused
.pwrite (pwrite),
.psel (psel),
.penable(penable),
.pwdata (pwdata),
.prdata (prdata),
.pready (pready),
.pslverr(pslverr)
);
endmodule
| 7.032568 |
module APB_MasterModule_Tb ();
reg clk = 1;
reg rstN = 1;
reg [31:0] apb_addr;
reg apb_write;
reg apb_sel;
reg apb_en;
reg [31:0] apb_wdata;
wire apb_ready;
wire pwm_out;
APB_PWM APB_PWM_Test (
.PCLK(clk),
.PRESETn(rstN),
.PADDR(apb_addr),
.PWRITE(apb_write),
.PSEL(apb_sel),
.PENABLE(apb_en),
.PWDATA(apb_wdata),
.PREADY(apb_ready),
.PWM_OUT(pwm_out)
);
// 10 ns Clock Signal
always begin
clk = !clk;
#5;
end
initial begin
// Initial values
clk = 1;
rstN = 1;
apb_sel = 0;
apb_en = 0;
apb_addr = 0;
apb_wdata = 0;
apb_write = 0;
// First Write
@(posedge clk);
apb_sel = 1;
apb_write = 1;
apb_addr = 1;
apb_wdata = 120;
@(posedge clk);
apb_en = 1;
@(posedge clk);
if (apb_ready) begin
apb_en = 0;
apb_addr = 2;
apb_wdata = 5;
end else begin
$display("Timeout");
end
// Second Write
@(posedge clk);
apb_en = 1;
@(posedge clk);
if (apb_ready) begin
apb_en = 0;
apb_sel = 1;
apb_addr = 0;
apb_wdata = 1;
end
@(posedge clk);
apb_en = 1;
@(posedge clk);
if (apb_ready) begin
apb_en = 0;
apb_sel = 0;
apb_addr = 0;
apb_wdata = 0;
$display("Success");
end else begin
$display("Failed TimeOut");
end
@(posedge clk);
apb_en = 0;
apb_sel = 0;
$finish;
end
endmodule
| 7.230037 |
module APB_MFGPIO (
// --------------------------
// Input pins: AHB signals //
// --------------------------
// Select
input PSEL,
// Address and control
input [31:0] PADDR,
input PWRITE,
// Data in
input [31:0] PWDATA,
// Reset and clock
input HRESETn,
input HCLK,
// --------------
// Output pins //
// --------------
// Transfer responses
output HREADY,
// Data out
output [31:0] PRDATA,
input [31:0] GPIO1_DI, //Data Input Port
output reg [31:0] GPIO1_DO, //Data Output port
output reg [31:0] GPIO1_AFC, //Function Select
output reg [31:0] GPIO1_DIR, //GPIO Direction 0=HiZ input 1=Output mode
output reg [63:0] GPIO1_PM, //GPIO Port Mode, 00=Push Pull/HiZ 01=Pull up 02=Pull down
output reg [63:0] GPIO1_PS //GPIO Pull Strengh Select,00=disable out/OD
);
reg [31:0] GPIO1_DIS; //Data Input,Sampled
genvar i;
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
GPIO1_AFC <= 32'h00000000;
GPIO1_DIR <= 32'h00000000;
GPIO1_PM <= 64'h00000000;
GPIO1_PS <= 64'h00000000;
end
//else
end
assign HREADY = 1;
generate
for (i = 0; i <= 31; i = i + 1) begin : gpio_dirgen
always @(posedge HCLK or negedge HRESETn)
if (!HRESETn) GPIO1_DIS[i] <= 1'b0;
else GPIO1_DIS[i] <= (~(GPIO1_AFC[i] | GPIO1_DIR[i])) ? (GPIO1_DI[i]) : 1'b0;
end
endgenerate
endmodule
| 6.869115 |
module apb_mock_uart #(
parameter APB_ADDR_WIDTH = 12 //APB slaves are 4KB by default
) (
CLK,
RSTN,
PADDR,
PWDATA,
PWRITE,
PSEL,
PENABLE,
PRDATA,
PREADY,
PSLVERR,
INT,
OUT1N,
OUT2N,
RTSN,
DTRN,
CTSN,
DSRN,
DCDN,
RIN,
SIN,
SOUT
);
//parameter APB_ADDR_WIDTH = 12;
input wire CLK;
input wire RSTN;
input wire [APB_ADDR_WIDTH - 1:0] PADDR;
input wire [31:0] PWDATA;
input wire PWRITE;
input wire PSEL;
input wire PENABLE;
output reg [31:0] PRDATA;
output wire PREADY;
output wire PSLVERR;
output wire INT;
output wire OUT1N;
output wire OUT2N;
output wire RTSN;
output wire DTRN;
input wire CTSN;
input wire DSRN;
input wire DCDN;
input wire RIN;
input wire SIN;
output wire SOUT;
wire [ 3:0] register_adr;
reg [63:0] regs_q;
reg [63:0] regs_n;
assign register_adr = PADDR[2:0];
always @(*) begin
regs_n = regs_q;
if ((PSEL && PENABLE) && PWRITE) regs_n[$unsigned(register_adr)*8+:8] = PWDATA[7:0];
regs_n[40+:8] = 32'h00000060;
end
always @(*) begin
PRDATA = 'b0;
if ((PSEL && PENABLE) && !PWRITE)
PRDATA = {24'b000000000000000000000000, regs_q[$unsigned(register_adr)*8+:8]};
end
always @(posedge CLK or negedge RSTN)
if (~RSTN) regs_q <= {8{8'b00000000}};
else begin
regs_q <= regs_n;
if ((PSEL && PENABLE) && PWRITE) if ($unsigned(register_adr) == 0) $write("%C", PWDATA[7:0]);
end
assign PREADY = 1'b1;
assign PSLVERR = 1'b0;
endmodule
| 8.288888 |
module apb_mux (
// -------------
// Input pins //
// -------------
// Clock and reset
input HCLK,
input HRESETn,
// Slave datas
input [31:0] PRDATAx0,
input [31:0] PRDATAx1,
input [31:0] PRDATAx2,
input [31:0] PRDATAx3,
input [31:0] PRDATAx4,
input [31:0] PRDATAx5,
input [31:0] PRDATAx6,
input [31:0] PRDATAx7,
input [31:0] PRDATAx8,
// Control signals
input PSELx0,
input PSELx1,
input PSELx2,
input PSELx3,
input PSELx4,
input PSELx5,
input PSELx6,
input PSELx7,
input PSELx8,
// Slave responses
input PREADYx0,
input PREADYx1,
input PREADYx2,
input PREADYx3,
input PREADYx4,
input PREADYx5,
input PREADYx6,
input PREADYx7,
input PREADYx8,
input PRESPx0,
input PRESPx1,
input PRESPx2,
input PRESPx3,
input PRESPx4,
input PRESPx5,
input PRESPx6,
input PRESPx7,
input PRESPx8,
// --------------
// Output pins //
// --------------
output reg PREADY,
output reg PRESP,
output reg [31:0] PRDATA
);
// Slave select register
reg [3:0] slave_select;
// Slave select register update
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
slave_select <= 4'b0;
end else begin
// If PREADY is high, update slave_select
if (PREADY) begin
case ({
PSELx8, PSELx7, PSELx6, PSELx5, PSELx4, PSELx3, PSELx2, PSELx1, PSELx0
})
9'h001: slave_select <= 4'h0;
9'h002: slave_select <= 4'h1;
9'h004: slave_select <= 4'h2;
9'h008: slave_select <= 4'h3;
9'h010: slave_select <= 4'h4;
9'h020: slave_select <= 4'h5;
9'h040: slave_select <= 4'h6;
9'h080: slave_select <= 4'h7;
9'h100: slave_select <= 4'h8;
// Default is for default slave
default: slave_select <= 4'hx;
endcase
end
end
end
// Read data multiplexor
always @(*) begin
case (slave_select)
4'h0: PRDATA = PRDATAx0;
4'h1: PRDATA = PRDATAx1;
4'h2: PRDATA = PRDATAx2;
4'h3: PRDATA = PRDATAx3;
4'h4: PRDATA = PRDATAx4;
4'h5: PRDATA = PRDATAx5;
4'h6: PRDATA = PRDATAx6;
4'h7: PRDATA = PRDATAx7;
default: PRDATA = 64'hx;
endcase
end
// Response multiplexor
always @(*) begin
case (slave_select)
4'h0: begin
PRESP = PRESPx0;
PREADY = PREADYx0;
end
4'h1: begin
PRESP = PRESPx1;
PREADY = PREADYx1;
end
4'h2: begin
PRESP = PRESPx2;
PREADY = PREADYx2;
end
4'h3: begin
PRESP = PRESPx3;
PREADY = PREADYx3;
end
4'h4: begin
PRESP = PRESPx4;
PREADY = PREADYx4;
end
4'h5: begin
PRESP = PRESPx5;
PREADY = PREADYx5;
end
4'h6: begin
PRESP = PRESPx6;
PREADY = PREADYx6;
end
4'h7: begin
PRESP = PRESPx7;
PREADY = PREADYx7;
end
default: begin
PRESP = 1'bx;
PREADY = 1'bx;
end
endcase
end
endmodule
| 7.22852 |
module apb_mux2 (
clk,
rst_n,
apb_ack_cpu,
apb_rw_cpu,
apb_psel_cpu,
apb_enab_cpu,
apb_addr_cpu,
apb_datai_cpu,
apb_datao_cpu,
apb_high_24b_rd,
apb_high_24b_wr,
apb_word_trans_cpu,
apb_ready_dma,
apb_rw_dma,
apb_psel_dma,
apb_enab_dma,
apb_addr_dma,
apb_wdata_dma,
apb_rdata_dma,
apb_valid_dma,
apb_valid_cpu,
dma_grant,
apb0_req,
apb0_ack,
apb0_rw,
apb0_psel,
apb0_enab,
apb0_addr,
apb0_datai,
apb0_datao,
apb1_req,
apb1_ack,
apb1_rw,
apb1_psel,
apb1_enab,
apb1_addr,
apb1_datai,
apb1_datao
);
parameter ADDR_APB = 20, DATA_APB = 8, DATA_APB_32 = 32;
input clk, rst_n;
output apb_ready_dma;
input apb_rw_dma;
input apb_psel_dma;
input apb_enab_dma;
input [ADDR_APB-1:0] apb_addr_dma;
input [31:0] apb_wdata_dma;
output [31:0] apb_rdata_dma;
output dma_grant;
input apb_valid_dma;
input apb_valid_cpu;
output apb_ack_cpu;
input apb_rw_cpu;
input apb_psel_cpu;
input apb_enab_cpu;
input [ADDR_APB-1:0] apb_addr_cpu;
input [DATA_APB-1:0] apb_datai_cpu;
output [DATA_APB-1:0] apb_datao_cpu;
output [23:0] apb_high_24b_rd;
input [23:0] apb_high_24b_wr;
output apb_word_trans_cpu;
output apb0_req;
input apb0_ack;
output apb0_rw;
output apb0_psel;
output apb0_enab;
output [ADDR_APB-1:0] apb0_addr;
output [DATA_APB-1:0] apb0_datai;
input [DATA_APB-1:0] apb0_datao;
output apb1_req;
input apb1_ack;
output apb1_rw;
output apb1_psel;
output apb1_enab;
output [ADDR_APB-1:0] apb1_addr;
output [31:0] apb1_datai;
input [31:0] apb1_datao;
wire apb_ack;
wire apb_rw;
wire apb_psel;
wire apb_enab;
wire [ADDR_APB-1:0] apb_addr;
wire [DATA_APB-1:0] apb_datai;
wire [ 23:0] high_24b_wr;
wire [ 23:0] high_24b_rd;
wire [ 7:0] apb_datao;
wire dma_grant;
arb_2_1 arb_2_1 (
.clk(clk),
.rst_n(rst_n),
.valid0(apb_valid_cpu),
.valid1(apb_valid_dma),
.dma_grant(dma_grant)
);
assign apb_addr = dma_grant ? apb_addr_dma : apb_addr_cpu;
assign apb_rw = dma_grant ? apb_rw_dma : apb_rw_cpu;
assign apb_psel = dma_grant ? apb_psel_dma : apb_psel_cpu;
assign apb_enab = dma_grant ? apb_enab_dma : apb_enab_cpu;
assign apb_datai = dma_grant ? apb_wdata_dma[7:0] : apb_datai_cpu;
assign high_24b_wr = dma_grant ? apb_wdata_dma[31:8] : apb_high_24b_wr;
assign high_24b_rd = apb1_req ? apb1_datao[31:8] : 24'h0;
assign apb_word_trans_cpu = dma_grant ? 1'h0 : apb1_req;
assign apb_high_24b_rd = dma_grant ? 24'h0 : high_24b_rd;
assign apb_datao_cpu = dma_grant ? 8'h0 : apb_datao;
assign apb_rdata_dma = dma_grant ? {high_24b_rd, apb_datao} : 32'h0;
assign apb_ack_cpu = ~dma_grant & apb_ack;
assign apb_ready_dma = dma_grant & apb_ack;
assign apb0_req = (apb_addr[ADDR_APB-1:14] == `APB_DEV0);
assign apb1_req = (apb_addr[ADDR_APB-1:14] == `APB_DEV1);
assign apb0_psel = apb_psel && apb0_req;
assign apb1_psel = apb_psel && apb1_req;
assign apb0_enab = apb_enab && apb0_req;
assign apb1_enab = apb_enab && apb1_req;
assign apb_ack = apb0_req ? apb0_ack : apb1_req ? apb1_ack : 1'b0;
assign apb_datao = apb0_req ? apb0_datao : apb1_req ? apb1_datao[7:0] : 8'b0;
assign apb0_addr = apb_addr;
assign apb0_datai = apb_datai;
assign apb0_rw = apb_rw;
assign apb1_addr = apb_addr;
assign apb1_datai = {high_24b_wr, apb_datai};
assign apb1_rw = apb_rw;
endmodule
| 6.690016 |
module arb_2_1 (
clk,
rst_n,
valid0,
valid1,
dma_grant
);
input clk;
input rst_n;
input valid0;
input valid1;
output dma_grant;
reg dma_grant;
always @(posedge clk)
if (~rst_n) dma_grant <= 1'b0;
else if (valid0 && ~valid1) dma_grant <= 1'b0;
else if (valid1 && ~valid0) dma_grant <= 1'b1;
else if (valid0 && valid1 && ~dma_grant) dma_grant <= 1'b0;
else if (valid0 && valid1 && dma_grant) dma_grant <= 1'b1;
else dma_grant <= 1'b0;
endmodule
| 7.253966 |
module apb_node #(
parameter NB_MASTER = 8,
parameter APB_DATA_WIDTH = 32,
parameter APB_ADDR_WIDTH = 32
) (
penable_i,
pwrite_i,
paddr_i,
pwdata_i,
prdata_o,
pready_o,
pslverr_o,
penable_o,
pwrite_o,
paddr_o,
psel_o,
pwdata_o,
prdata_i,
pready_i,
pslverr_i,
START_ADDR_i,
END_ADDR_i
);
//parameter NB_MASTER = 8;
//parameter APB_DATA_WIDTH = 32;
//parameter APB_ADDR_WIDTH = 32;
input wire penable_i;
input wire pwrite_i;
input wire [31:0] paddr_i;
input wire [31:0] pwdata_i;
output reg [31:0] prdata_o;
output reg pready_o;
output reg pslverr_o;
output reg [NB_MASTER - 1:0] penable_o;
output reg [NB_MASTER - 1:0] pwrite_o;
output reg [(NB_MASTER * 32) - 1:0] paddr_o;
output wire [NB_MASTER - 1:0] psel_o;
output reg [(NB_MASTER * 32) - 1:0] pwdata_o;
input wire [(NB_MASTER * 32) - 1:0] prdata_i;
input wire [NB_MASTER - 1:0] pready_i;
input wire [NB_MASTER - 1:0] pslverr_i;
input wire [(NB_MASTER * APB_ADDR_WIDTH) - 1:0] START_ADDR_i;
input wire [(NB_MASTER * APB_ADDR_WIDTH) - 1:0] END_ADDR_i;
genvar i;
integer s_loop1;
integer s_loop2;
integer s_loop3;
integer s_loop4;
integer s_loop5;
integer s_loop6;
integer s_loop7;
generate
for (i = 0; i < NB_MASTER; i = i + 1) begin : genblk1
assign psel_o[i] = (paddr_i >= START_ADDR_i[i * APB_ADDR_WIDTH+:APB_ADDR_WIDTH]) && (paddr_i <= END_ADDR_i[i * APB_ADDR_WIDTH+:APB_ADDR_WIDTH]);
end
endgenerate
always @(*)
for (s_loop1 = 0; s_loop1 < NB_MASTER; s_loop1 = s_loop1 + 1)
if (psel_o[s_loop1] == 1'b1) penable_o[s_loop1] = penable_i;
else penable_o[s_loop1] = 1'sb0;
always @(*)
for (s_loop2 = 0; s_loop2 < NB_MASTER; s_loop2 = s_loop2 + 1)
if (psel_o[s_loop2] == 1'b1) pwrite_o[s_loop2] = pwrite_i;
else pwrite_o[s_loop2] = 1'sb0;
always @(*)
for (s_loop3 = 0; s_loop3 < NB_MASTER; s_loop3 = s_loop3 + 1)
if (psel_o[s_loop3] == 1'b1) paddr_o[s_loop3*32+:32] = paddr_i;
else paddr_o[s_loop3*32+:32] = 1'sb0;
always @(*)
for (s_loop4 = 0; s_loop4 < NB_MASTER; s_loop4 = s_loop4 + 1)
if (psel_o[s_loop4] == 1'b1) pwdata_o[s_loop4*32+:32] = pwdata_i;
else pwdata_o[s_loop4*32+:32] = 1'sb0;
always @(*) begin
prdata_o = 1'sb0;
for (s_loop5 = 0; s_loop5 < NB_MASTER; s_loop5 = s_loop5 + 1)
if (psel_o[s_loop5] == 1'b1) prdata_o = prdata_i[s_loop5*32+:32];
end
always @(*) begin
pready_o = 1'sb0;
for (s_loop6 = 0; s_loop6 < NB_MASTER; s_loop6 = s_loop6 + 1)
if (psel_o[s_loop6] == 1'b1) pready_o = pready_i[s_loop6];
end
always @(*) begin
pslverr_o = 1'sb0;
for (s_loop7 = 0; s_loop7 < NB_MASTER; s_loop7 = s_loop7 + 1)
if (psel_o[s_loop7] == 1'b1) pslverr_o = pslverr_i[s_loop7];
end
endmodule
| 7.415225 |
module apb_node_wrap (
clk_i,
rst_ni,
apb_slave,
apb_masters,
start_addr_i,
end_addr_i
);
parameter NB_MASTER = 8;
parameter APB_DATA_WIDTH = 32;
parameter APB_ADDR_WIDTH = 32;
input wire clk_i;
input wire rst_ni;
input apb_slave;
input [NB_MASTER - 1:0] apb_masters;
input wire [(NB_MASTER * APB_ADDR_WIDTH) - 1:0] start_addr_i;
input wire [(NB_MASTER * APB_ADDR_WIDTH) - 1:0] end_addr_i;
genvar i;
wire [NB_MASTER - 1:0] penable;
wire [NB_MASTER - 1:0] pwrite;
wire [(NB_MASTER * 32) - 1:0] paddr;
wire [NB_MASTER - 1:0] psel;
wire [(NB_MASTER * 32) - 1:0] pwdata;
wire [(NB_MASTER * 32) - 1:0] prdata;
wire [NB_MASTER - 1:0] pready;
wire [NB_MASTER - 1:0] pslverr;
initial begin
for (i = 0; i < NB_MASTER; i = i + 1) begin
assign apb_masters[i].penable = penable[i];
assign apb_masters[i].pwrite = pwrite[i];
assign apb_masters[i].paddr = paddr[i*32+:32];
assign apb_masters[i].psel = psel[i];
assign apb_masters[i].pwdata = pwdata[i*32+:32];
assign prdata[i*32+:32] = apb_masters[i].prdata;
assign pready[i] = apb_masters[i].pready;
assign pslverr[i] = apb_masters[i].pslverr;
end
end
apb_node #(
.NB_MASTER(NB_MASTER),
.APB_DATA_WIDTH(APB_DATA_WIDTH),
.APB_ADDR_WIDTH(APB_ADDR_WIDTH)
) apb_node_i (
.penable_i(apb_slave.penable),
.pwrite_i(apb_slave.pwrite),
.paddr_i(apb_slave.paddr),
.pwdata_i(apb_slave.pwdata),
.prdata_o(apb_slave.prdata),
.pready_o(apb_slave.pready),
.pslverr_o(apb_slave.pslverr),
.penable_o(penable),
.pwrite_o(pwrite),
.paddr_o(paddr),
.psel_o(psel),
.pwdata_o(pwdata),
.prdata_i(prdata),
.pready_i(pready),
.pslverr_i(pslverr),
.START_ADDR_i(start_addr_i),
.END_ADDR_i(end_addr_i)
);
endmodule
| 7.357296 |
module apb_pool (
// CPU Interface Input (APB bus interface)
input wire PCLK, // APB clock
input wire PRESETB, // APB asynchronous reset (0: reset, 1: normal)
input wire [31:0] PADDR, // APB address
input wire PSEL, // APB select
input wire PENABLE, // APB enable
input wire PWRITE, // APB write enable
input wire [31:0] PWDATA, // APB write data
input wire [31:0] clk_counter,
input wire [ 0:0] pool_done,
output reg [ 0:0] pool_start,
output reg [ 5:0] flen,
output reg [ 8:0] in_channel,
// CPU Interface Output (APB bus interface)
output wire [31:0] PRDATA
);
wire state_enable;
wire state_enable_pre;
reg [31:0] prdata_reg;
assign state_enable = PSEL & PENABLE;
assign state_enable_pre = PSEL & ~PENABLE;
// READ OUTPUT
always @(posedge PCLK, negedge PRESETB) begin
if (PRESETB == 1'b0) begin
prdata_reg <= 32'h00000000;
end else begin
if (~PWRITE & state_enable_pre) begin
case ({
PADDR[31:2], 2'h0
})
/*READOUT*/
32'h00000000: prdata_reg <= {31'h0, pool_start};
32'h00000004: prdata_reg <= flen;
32'h00000008: prdata_reg <= {31'd0, pool_done};
32'h0000000C: prdata_reg <= in_channel;
32'h00000010: prdata_reg <= {clk_counter};
default: prdata_reg <= 32'h0;
endcase
end else begin
prdata_reg <= 32'h0;
end
end
end
assign PRDATA = (~PWRITE & state_enable) ? prdata_reg : 32'h00000000;
// WRITE ACCESS
always @(posedge PCLK, negedge PRESETB) begin
if (PRESETB == 1'b0) begin
/*WRITERES*/
pool_start <= 1'b0;
flen <= 0;
in_channel <= 0;
end else begin
if (PWRITE & state_enable) begin
case ({
PADDR[31:2], 2'h0
})
/*WRITEIN*/
32'h00000000: begin
pool_start <= PWDATA[0];
end
32'h00000004: begin
flen <= PWDATA[5:0];
end
32'h0000000C: begin
in_channel <= PWDATA[8:0];
end
default: ;
endcase
end
end
end
endmodule
| 7.009961 |
module APB_Protcol (
input pclk,
penable,
pwrite,
transfer,
Reset,
input [4:0] write_paddr,
apb_read_paddr,
input [31:0] write_data,
// 1 gpio 2 uart 0 idle
input [1:0] Psel,
output [31:0] apb_read_data_out,
input rx,
output PSLVERR,
// Know The Type of Error
output [2:0] Error_Identify
);
// coming from Slave
reg pready;
reg [31:0] prdata;
wire [31:0] pwdata;
wire [4:0] paddr;
wire PSEL1, PSEL2;
wire [31:0] prdata1, prdata2;
wire pready1, pready2;
wire pwrite_slave, penable_slave;
always @(Psel or pready1 or prdata1 or pready2 or prdata2) begin
case (Psel)
1: begin
pready <= pready1;
prdata <= prdata1;
end
2: begin
pready <= pready2;
prdata <= prdata2;
end
default: begin
pready <= 0;
prdata <= 0;
end
endcase
end
APB_Bridge dut_mas (
pclk,
penable,
pwrite,
transfer,
Reset,
Psel,
write_paddr,
apb_read_paddr,
write_data, // From Tb
pready,
prdata,
pwrite_slave,
penable_slave, //From Slaves
pwdata,
paddr,
PSEL1,
PSEL2 // Out To Slave
, apb_read_data_out // Out To Test bench
, PSLVERR,
Error_Identify
);
GPIO g1 (
pclk,
penable_slave,
pwrite_slave,
PSEL1,
Reset,
pwdata,
paddr,
pready1,
prdata1
);
// Inistantiate UART
UART_APB uart (
.PCLK(pclk),
.PADDR(write_paddr),
.PWDATA(write_data),
.PRDATA(apb_read_data_out),
.PSELx(PSEL2),
.PENABLE(penable),
.PWRITE(pwrite),
.PRESETn(Reset),
.PREADY(pready2),
.rx(rx)
);
// slave2 dut2( PCLK,PRESETn, PSEL2,PENABLE,PWRITE, PADDR[7:0],PWDATA, PRDATA2, PREADY2 );
endmodule
| 7.093577 |
module APB_PSMCREG (
input PCLK,
input PSEL,
input PENABLE,
input PWRITE,
input [7:0] PADDR,
input [31:0] PWDATA,
output [31:0] PRDATA,
output reg PREADY,
output reg PSLVERR,
input RESETN,
output MOSI,
input MISO,
output MCS,
output MCLKO,
output reg [31:0] psramc_ctrlreg, //PSRAMEN[31] SPISendDone[8] SPITx[7:0]
output reg [31:0] psramc_cycPU, //tPU Cycles (150us)
output reg [31:0] psramc_cycCEM //tCEM Cycles (8us)
);
wire [31:0] spi_o;
assign PRDATA=(
({32{PADDR[3:0]==4'h0}}&psramc_ctrlreg)|
({32{PADDR[3:0]==4'h0}}&psramc_cycPU)|
({32{PADDR[3:0]==4'h0}}&psramc_cycCEM)|
({32{PADDR[3]}}&spi_o)
);
always @(posedge PCLK) begin
if (!RESETN) begin
psramc_ctrlreg <= 32'b0;
end else begin
if (PSEL & PENABLE & PWRITE) begin
case (PADDR[3:0])
4'h0: psramc_ctrlreg <= PWDATA;
4'h1: psramc_cycPU <= PWDATA;
4'h2: psramc_cycCEM <= PWDATA;
endcase
end
end
end
tiny_spi spi_PSRAMC (
// system
.rst_i(!RESETN),
.clk_i(PCLK),
// memory mapped
.stb_i(PENABLE & PADDR[3]),
.we_i(PSEL & PENABLE & PWRITE),
.dat_o(spi_o),
.dat_i(PWDATA),
// .int_o,
.adr_i(PADDR[2:0]),
.cyc_i(PSEL), // comment out for avalon
//.ack_o, // comment out for avalon
// spi
.MOSI(MOSI),
.SCLK(MCLKO),
.MISO(MISO)
);
endmodule
| 6.775748 |
module apb_pulse (
// system
input reset_n,
input enable, // clock gating
// APB
input pclk,
input [ 3:0] paddr, // ls 2 bits are unused
input pwrite,
input psel,
input penable,
input [31:0] pwdata,
output [31:0] prdata,
output pready,
output pslverr,
// Interface
output reg pulse_write,
output reg pulse_writebit,
output reg pulse_read
);
wire apb_write = psel & penable & pwrite;
wire apb_read = psel & ~pwrite;
assign pready = 1'b1;
assign pslverr = 1'b0;
assign prdata = 32'h0; // no actual data read implemented
always @(posedge pclk or negedge reset_n) begin
if (!reset_n) begin
pulse_write <= 1'b0;
pulse_writebit <= 1'b0;
pulse_read <= 1'b0;
end // reset
else if (enable)
begin
pulse_write <= 1'b0;
pulse_writebit <= 1'b0;
pulse_read <= 1'b0;
if (apb_write) begin
case (paddr)
4'h00: pulse_write <= 1'b1;
4'h04: pulse_writebit <= pwdata[0];
endcase
end // write
if (apb_read) begin
// Beware: apb_read id high for TWO cycles
// Thus can't use it in the same way as apb_write
case (paddr)
//4'h00 : pulse_write <= 1'b1;
//4'h04 : pulse_writebit <= pwdata[0];
4'h08: pulse_read <= penable;
endcase
end // read
end // clocked
end // always
endmodule
| 8.422322 |
module apb_pulse_test;
localparam CLK_PERIOD = 100;
// system
reg reset_n;
reg enable; // clock gating
// APB
wire pclk;
wire [15:0] paddr; // ls 2 bits are unused
wire pwrite;
wire psel;
wire penable;
wire [31:0] pwdata;
wire [31:0] prdata;
wire pready;
wire pslverr;
// Interface
wire pulse_write;
wire pulse_writebit;
wire pulse_read;
// testbench
reg fail;
integer i;
initial begin
// system
reset_n = 1'b0;
enable = 1'b1;
fail = 0;
@(posedge pclk) #(CLK_PERIOD * 5);
reset_n = 1'b1;
#(CLK_PERIOD * 5);
// write set
apb_bus0.write(16'h0, 32'h0);
// Write comes in 3 cycles, pulse at 4
for (i = 0; i < 3; i = i + 1) @(posedge pclk);
@(posedge pclk) if (pulse_write !== 1'b1) fail = 1;
@(posedge pclk) if (pulse_write !== 1'b0) fail = 1;
apb_bus0.write(16'h4, 32'h1);
// Write comes in 3 cycles, pulse at 4
for (i = 0; i < 3; i = i + 1) @(posedge pclk);
@(posedge pclk) if (pulse_writebit !== 1'b1) fail = 1;
@(posedge pclk) if (pulse_writebit !== 1'b0) fail = 1;
apb_bus0.write(16'h4, 32'h0);
for (i = 0; i < 3; i = i + 1) @(posedge pclk);
@(posedge pclk) if (pulse_writebit !== 1'b0) fail = 1;
apb_bus0.read(16'h8, 32'hx);
// Read comes in 3 cycles, pulse at 4
for (i = 0; i < 3; i = i + 1) @(posedge pclk);
@(posedge pclk) if (pulse_read !== 1'b1) fail = 1;
@(posedge pclk) if (pulse_read !== 1'b0) fail = 1;
if (fail == 0) $display("apb_pulse test passed");
else $display("apb_pulse test FAILED!");
#500 $stop;
end
apb_pulse apb_pulse_0 (
// system
.reset_n(reset_n),
.enable (enable), // clock gating
// APB
.pclk (pclk),
.paddr (paddr[3:0]), // ls 2 bits are unused
.pwrite (pwrite),
.psel (psel),
.penable(penable),
.pwdata (pwdata),
.prdata (prdata),
.pready (pready),
.pslverr(pslverr),
// Interface
.pulse_write (pulse_write),
.pulse_writebit(pulse_writebit),
.pulse_read (pulse_read)
);
apb_bus #(
.CLKPER(CLK_PERIOD)
) apb_bus0 (
// APB
.pclk (pclk),
.paddr (paddr), // ls 2 bits are unused
.pwrite (pwrite),
.psel (psel),
.penable(penable),
.pwdata (pwdata),
.prdata (prdata),
.pready (pready),
.pslverr(pslverr)
);
endmodule
| 7.310459 |
module APB_PWM (
// Peripheral Signals
input PCLK,
input PRESETn,
// APB Bridge Signals
input [31:0] PADDR,
input PWRITE,
input PSEL,
input PENABLE,
input [31:0] PWDATA,
// APB Slave Signals
output reg PREADY,
output reg PWM_OUT
);
// State Mechine Parameters and State declaration
localparam IDLE = 2'b00;
localparam WRITE = 2'b01;
localparam READ = 2'b10;
reg [1:0] State = 2'b00;
// PWM Module Registers
// 32 Bit Data Width
// 2 Bit Depth
// RAM[0] : PWM Enable 0x1 Register
// RAM[1] : PWM Duty Cycle (Width) Register
// RAM[2] : PWM Frequency Register
reg [31:0] RAM[0:2];
initial RAM[2] = 1;
always @(posedge PCLK, negedge PRESETn) begin
if (~PRESETn) begin
// Initial Values For The APB Slave
State <= IDLE;
PREADY <= 0;
PWM_OUT <= 0;
end else begin
case (State)
IDLE: begin
PREADY <= 0;
if (PSEL) begin
if (PWRITE) begin
State <= WRITE;
end else begin
State <= READ;
end
end
end
WRITE: begin
if (PSEL && PENABLE && PWRITE) begin
RAM[PADDR] <= PWDATA;
PREADY <= 1'b1;
end
State <= IDLE;
end
default: begin
State <= IDLE;
end
endcase
end
end
reg div_clk = 0;
reg [31:0] clk_counter = 0;
always @(posedge PCLK) begin
clk_counter <= clk_counter + 1;
if (clk_counter == RAM[2]) begin
div_clk = ~div_clk;
clk_counter <= 1;
end
end
reg [8:0] counter = 0;
always @(posedge div_clk) begin
if (RAM[0]) begin
if (RAM[1] > counter) begin
PWM_OUT <= 1;
end else begin
PWM_OUT <= 0;
end
counter <= counter + 1;
end
end
endmodule
| 7.595131 |
module APB_PWM32 (
// APB Interface
// clock and reset
input wire PCLK,
//input wire PCLKG, // Gated clock
input wire PRESETn, // Reset
// input ports
input wire PSEL, // Select
input wire [19:2] PADDR, // Address
input wire PENABLE, // Transfer control
input wire PWRITE, // Write control
input wire [31:0] PWDATA, // Write data
// output ports
output wire [31:0] PRDATA, // Read data
output wire PREADY,
// Device ready
// IP Interface
// PRE register/fields
output [31:0] PRE,
// TMRCMP1 register/fields
output [31:0] TMRCMP1,
// TMRCMP2 register/fields
output [31:0] TMRCMP2,
// TMREN register/fields
output [0:0] TMREN
);
wire rd_enable;
wire wr_enable;
assign rd_enable = PSEL & (~PWRITE);
assign wr_enable = PSEL & PWRITE & (PENABLE);
assign PREADY = 1'b1;
reg [31:0] PRE;
reg [31:0] TMRCMP1;
reg [31:0] TMRCMP2;
reg [0:0] TMREN;
// Register: PRE
wire PRE_select = wr_enable & (PADDR[19:2] == 18'h4);
always @(posedge PCLK or negedge PRESETn) begin
if (~PRESETn) PRE <= 32'h0;
else if (PRE_select) PRE <= PWDATA;
end
// Register: TMRCMP1
wire TMRCMP1_select = wr_enable & (PADDR[19:2] == 18'h1);
always @(posedge PCLK or negedge PRESETn) begin
if (~PRESETn) TMRCMP1 <= 32'h0;
else if (TMRCMP1_select) TMRCMP1 <= PWDATA;
end
// Register: TMRCMP2
wire TMRCMP2_select = wr_enable & (PADDR[19:2] == 18'h2);
always @(posedge PCLK or negedge PRESETn) begin
if (~PRESETn) TMRCMP2 <= 32'h0;
else if (TMRCMP2_select) TMRCMP2 <= PWDATA;
end
// Register: TMREN
wire TMREN_select = wr_enable & (PADDR[19:2] == 18'h8);
always @(posedge PCLK or negedge PRESETn) begin
if (~PRESETn) TMREN <= 1'h0;
else if (TMREN_select) TMREN <= PWDATA;
end
assign PRDATA =
(PADDR[19:2] == 18'h4) ? PRE :
(PADDR[19:2] == 18'h1) ? TMRCMP1 :
(PADDR[19:2] == 18'h2) ? TMRCMP2 :
(PADDR[19:2] == 18'h8) ? {31'd0,TMREN} :
32'hDEADBEEF;
endmodule
| 6.577182 |
module apb_regs (
// system
input reset_n,
input enable, // clock gating
// APB
input pclk,
input [ 4:0] paddr, // ls 2 bits are unused
input pwrite,
input psel,
input penable,
input [31:0] pwdata,
output reg [31:0] prdata,
output pready,
output pslverr,
// Interface
input [31:0] status32,
input [15:0] status16,
input [ 7:0] status8,
output reg [31:0] control32,
output reg [15:0] control16,
output reg [ 7:0] control8
);
wire apb_write = psel & penable & pwrite;
wire apb_read = psel & ~pwrite;
assign pready = 1'b1;
assign pslverr = 1'b0;
always @(posedge pclk or negedge reset_n) begin
if (!reset_n) begin
control32 <= 32'h0;
control16 <= 16'h1234; // reset/initial value
control8 <= 8'h0;
prdata <= 32'h0;
end // reset
else if (enable)
begin
if (apb_write) begin
case (paddr)
//5'h00 : status32 read only
//5'h04 : status16 read only
//5'h08 : status8 read only
//5'h0C : Unused (gap)
5'h10: control32 <= pwdata;
5'h14: control16 <= pwdata[15:0];
5'h18: control8 <= pwdata[7:0];
//5'h1C : Identify read only
endcase
end // write
if (apb_read) begin
case (paddr)
5'h00: prdata <= status32;
5'h04: prdata <= {16'h0, status16};
5'h08: prdata <= {24'h0, status8};
//5'h0C : unused (GAP)
5'h10: prdata <= control32;
5'h14: prdata <= {16'h0, control16};
5'h18: prdata <= {24'h0, control8};
5'h1C: prdata <= 32'h00216948; // "Hi!"
endcase
end // read
else prdata <= 32'h0; // so we can OR all busses
end // clocked
end // always
endmodule
| 7.935939 |
module apb_regs1 (
// system
input reset_n,
input enable, // clock gating
// APB
input pclk,
input [ 3:0] paddr, // ls 2 bits are unused
input pwrite,
input psel,
input penable,
input [31:0] pwdata,
output reg [31:0] prdata,
output pready,
output pslverr,
// Interface
input [31:0] status32,
input [15:0] status16,
input [ 7:0] status8,
output reg [31:0] control32,
output reg [15:0] control16,
output reg [ 7:0] control8
);
wire apb_write = psel & penable & pwrite;
wire apb_read = psel & ~pwrite;
assign pready = 1'b1;
assign pslverr = 1'b0;
always @(posedge pclk or negedge reset_n) begin
if (!reset_n) begin
control32 <= 32'h0;
control16 <= 16'h1234; // reset/initial value
control8 <= 8'h0;
prdata <= 32'h0;
end // reset
else if (enable)
begin
if (apb_write) begin
case (paddr)
//4'h0 : status32 read only
4'h4: control32 <= pwdata;
4'h8: control16 <= pwdata[15:0];
4'hC: control8 <= pwdata[7:0];
endcase
end // write
if (apb_read) begin
case (paddr)
4'h0: prdata <= status32;
4'h4: prdata <= control32;
4'h8: prdata <= {status16, control16};
4'hC: prdata <= {8'h0, status8, 8'h0, control8};
endcase
end // read
else prdata <= 32'h0; // so we can OR all busses
end // clocked
end // always
endmodule
| 7.605514 |
module apb_regs1_test;
localparam CLK_PERIOD = 100;
// system
reg reset_n;
reg enable; // clock gating
// APB
wire pclk;
wire [15:0] paddr; // ls 2 bits are unused
wire pwrite;
wire psel;
wire penable;
wire [31:0] pwdata;
wire [31:0] prdata;
wire pready;
wire pslverr;
// Interface
reg [31:0] status32;
reg [15:0] status16;
reg [ 7:0] status8;
wire [31:0] control32;
wire [15:0] control16;
wire [ 7:0] control8;
reg flag;
initial begin
// system
reset_n = 1'b0;
enable = 1'b1;
flag = 1'b0;
// Interface
status32 = 32'h9c4e9a31;
status16 = 16'h7832;
status8 = 16'h2a;
@(posedge pclk) #(CLK_PERIOD * 5);
reset_n = 1'b1;
#(CLK_PERIOD * 5);
apb_bus0.read(16'h00, 32'h9c4e9a31);
apb_bus0.write(16'h04, 32'h11223344);
apb_bus0.write(16'h08, 32'hAABB);
apb_bus0.write(16'h0C, 32'hDD);
apb_bus0.read(16'h04, 32'h11223344);
apb_bus0.read(16'h08, 32'h7832AABB);
apb_bus0.read(16'h0C, 32'h002a00DD);
apb_bus0.delay(3);
if (apb_bus0.errors == 0) $display("apb_regs1 test passed");
else $display("apb_regs1 test FAILED!");
#500 $stop;
end
apb_regs1 apb_regs1_0 (
// system
.reset_n(reset_n),
.enable (enable), // clock gating
// APB
.pclk (pclk),
.paddr (paddr[3:0]), // ls 2 bits are unused
.pwrite (pwrite),
.psel (psel),
.penable(penable),
.pwdata (pwdata),
.prdata (prdata),
.pready (pready),
.pslverr(pslverr),
// Interface
.status32 (status32),
.status16 (status16),
.status8 (status8),
.control32(control32),
.control16(control16),
.control8 (control8)
);
apb_bus #(
.CLKPER(CLK_PERIOD)
) apb_bus0 (
// APB
.pclk (pclk),
.paddr (paddr), // ls 2 bits are unused
.pwrite (pwrite),
.psel (psel),
.penable(penable),
.pwdata (pwdata),
.prdata (prdata),
.pready (pready),
.pslverr(pslverr)
);
endmodule
| 7.046327 |
module apb_regs_test;
localparam CLK_PERIOD = 100;
// system
reg reset_n;
reg enable; // clock gating
// APB
wire pclk;
wire [15:0] paddr; // ls 2 bits are unused
wire pwrite;
wire psel;
wire penable;
wire [31:0] pwdata;
wire [31:0] prdata;
wire pready;
wire pslverr;
// Interface
reg [31:0] status32;
reg [15:0] status16;
reg [ 7:0] status8;
wire [31:0] control32;
wire [15:0] control16;
wire [ 7:0] control8;
initial begin
// system
reset_n = 1'b0;
enable = 1'b1;
// Interface
status32 = 32'h9c4e9a31;
status16 = 16'h7832;
status8 = 16'h2a;
@(posedge pclk) #(CLK_PERIOD * 5);
reset_n = 1'b1;
#(CLK_PERIOD * 5);
apb_bus0.read(16'h00, 32'h9c4e9a31);
apb_bus0.read(16'h04, 32'h7832);
apb_bus0.read(16'h08, 32'h2a);
apb_bus0.read(16'h14, 32'h1234); // reset value
apb_bus0.write(16'h10, 32'h11223344);
apb_bus0.write(16'h14, 32'hAABB);
apb_bus0.write(16'h18, 32'hDD);
apb_bus0.read(16'h10, 32'h11223344);
apb_bus0.read(16'h14, 32'hxxxxAABB);
apb_bus0.read(16'h18, 32'hxxxxxxDD);
apb_bus0.read(16'h1C, 32'h00216948); // Expect "Hi!" (Reverse endian)
apb_bus0.delay(3);
if (apb_bus0.errors == 0) $display("apb_regs test passed");
else $display("apb_regs test FAILED!");
#500 $stop;
end
apb_regs apb_regs_0 (
// system
.reset_n(reset_n),
.enable (enable), // clock gating
// APB
.pclk (pclk),
.paddr (paddr[4:0]), // ls 2 bits are unused
.pwrite (pwrite),
.psel (psel),
.penable(penable),
.pwdata (pwdata),
.prdata (prdata),
.pready (pready),
.pslverr(pslverr),
// Interface
.status32 (status32),
.status16 (status16),
.status8 (status8),
.control32(control32),
.control16(control16),
.control8 (control8)
);
apb_bus #(
.CLKPER(CLK_PERIOD)
) apb_bus0 (
// APB
.pclk (pclk),
.paddr (paddr), // ls 2 bits are unused
.pwrite (pwrite),
.psel (psel),
.penable(penable),
.pwdata (pwdata),
.prdata (prdata),
.pready (pready),
.pslverr(pslverr)
);
endmodule
| 7.223267 |
module apb_regs_top #(
parameter APB_ADDR_WIDTH = 12, //APB slaves are 4KB by default
parameter APB_DATA_WIDTH = 32,
parameter N_REGION_MAX = 4,
parameter N_MASTER_PORT = 16,
parameter N_SLAVE_PORT = 16
) (
HCLK,
HRESETn,
PADDR_i,
PWDATA_i,
PWRITE_i,
PSEL_i,
PENABLE_i,
PRDATA_o,
PREADY_o,
PSLVERR_o,
init_START_ADDR_i,
init_END_ADDR_i,
init_valid_rule_i,
init_connectivity_map_i,
START_ADDR_o,
END_ADDR_o,
valid_rule_o,
connectivity_map_o
);
//parameter APB_ADDR_WIDTH = 12;
//parameter APB_DATA_WIDTH = 32;
//parameter N_REGION_MAX = 4;
//parameter N_MASTER_PORT = 16;
//parameter N_SLAVE_PORT = 16;
input wire HCLK;
input wire HRESETn;
input wire [APB_ADDR_WIDTH - 1:0] PADDR_i;
input wire [APB_DATA_WIDTH - 1:0] PWDATA_i;
input wire PWRITE_i;
input wire PSEL_i;
input wire PENABLE_i;
output reg [APB_DATA_WIDTH - 1:0] PRDATA_o;
output wire PREADY_o;
output wire PSLVERR_o;
input wire [((N_REGION_MAX * N_MASTER_PORT) * 32) - 1:0] init_START_ADDR_i;
input wire [((N_REGION_MAX * N_MASTER_PORT) * 32) - 1:0] init_END_ADDR_i;
input wire [(N_REGION_MAX * N_MASTER_PORT) - 1:0] init_valid_rule_i;
input wire [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] init_connectivity_map_i;
output wire [((N_REGION_MAX * N_MASTER_PORT) * 32) - 1:0] START_ADDR_o;
output wire [((N_REGION_MAX * N_MASTER_PORT) * 32) - 1:0] END_ADDR_o;
output wire [(N_REGION_MAX * N_MASTER_PORT) - 1:0] valid_rule_o;
output wire [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] connectivity_map_o;
reg [((N_REGION_MAX * N_MASTER_PORT) * 32) - 1:0] cfg_req_START_ADDR;
reg [((N_REGION_MAX * N_MASTER_PORT) * 32) - 1:0] cfg_req_END_ADDR;
reg [(N_REGION_MAX * N_MASTER_PORT) - 1:0] cfg_req_valid_rule;
reg [(N_SLAVE_PORT * N_MASTER_PORT) - 1:0] cfg_req_connectivity_map;
always @(posedge HCLK)
if (~HRESETn) begin
cfg_req_START_ADDR <= init_START_ADDR_i;
cfg_req_END_ADDR <= init_END_ADDR_i;
cfg_req_valid_rule <= init_valid_rule_i;
cfg_req_connectivity_map <= init_connectivity_map_i;
end else if ((PSEL_i && PENABLE_i) && PWRITE_i)
case (PADDR_i[9:8])
2'b00: cfg_req_START_ADDR[PADDR_i[7:2]*32+:32] <= PWDATA_i[31:0];
2'b01: cfg_req_END_ADDR[PADDR_i[7:2]*32+:32] <= PWDATA_i[31:0];
2'b10:
cfg_req_valid_rule[PADDR_i[7:2] * N_MASTER_PORT+:N_MASTER_PORT] <= PWDATA_i[N_MASTER_PORT - 1:0];
2'b11: cfg_req_END_ADDR[PADDR_i[7:2]*32+:32] <= PWDATA_i[N_MASTER_PORT-1:0];
endcase
always @(*)
if ((PSEL_i && PENABLE_i) && ~PWRITE_i)
case (PADDR_i[9:8])
2'b00: PRDATA_o[31:0] = cfg_req_START_ADDR[PADDR_i[7:2]*32+:32];
2'b01: PRDATA_o[31:0] = cfg_req_END_ADDR[PADDR_i[7:2]*32+:32];
2'b10: PRDATA_o[31:0] = cfg_req_valid_rule[PADDR_i[7:2]*N_MASTER_PORT+:N_MASTER_PORT];
2'b11: PRDATA_o[31:0] = cfg_req_END_ADDR[PADDR_i[7:2]*32+:32];
endcase
else PRDATA_o = 1'sb0;
assign PREADY_o = 1'b1;
assign PSLVERR_o = 1'b0;
endmodule
| 8.72867 |
module !!!
----------------------------------------
Receive 8/10 bit (depending on mode)
Receive bit-by-bit according to baudrate
Receive & store
Control Path:
Data Path:
*/
module apb_rx
(
// Inputs:
input wire clk,
input wire rstn,
input wire sel,
input wire rx_en,
input wire mode,
input wire [19:0] baud,
input wire rx_in,
// Outputs:
output wire [31:0] rx_data
);
/* -------------------
internal wires/regs
------------------- */
wire rst;
wire [9:0] bit_cnto;
wire [9:0] bit_cntn;
wire start_bit;
wire end_bit;
wire [9:0] data_bit;
wire [19:0] baud_cnto;
wire [19:0] baud_cntn;
wire baud_clk;
/* ---------------------------
connect CONTROl & DATA path
--------------------------- */
apb_rx_cp rx_cp
(
// Inputs:
.rstn (rstn),
.sel (sel),
.rx_en (rx_en),
.mode (mode),
.baud_clk (baud_clk),
.bit_cnto (bit_cnto),
// Outputs:
.bit_cntn (bit_cntn),
.start_bit (start_bit),
.end_bit (end_bit),
.data_bit (data_bit)
);
apb_rx_dp rx_dp
(
// Inputs:
.rstn (rstn),
.sel (sel),
.rx_en (rx_en),
.rx_in (rx_in),
.start_bit (start_bit),
.end_bit (end_bit),
.bit_cnto (bit_cnto),
.data_bit (data_bit),
// Outputs:
.rx_data (rx_data)
);
baud_counter baud_counter
(
// Inputs:
.rstn (rstn),
.en (rx_en),
.baud (baud),
.baud_cnto (baud_cnto),
// Outputs:
.baud_cntn (baud_cntn),
.baud_clk (baud_clk)
);
/* ----------------
connecting wires
---------------- */
assign rst = ~rstn;
PipeReg #(10) bit_cnt
(
.CLK (clk),
.RST (rst),
.EN (1'b1),
.D (bit_cntn),
.Q (bit_cnto)
);
PipeReg #(20) baud_cnt
(
.CLK (clk),
.RST (rst),
.EN (1'b1),
.D (baud_cntn),
.Q (baud_cnto)
);
endmodule
| 7.687749 |
module !!!
----------------------------------------
Append received data bit into correct bit in rx_data
*/
module apb_rx_cp
(
// Inputs:
input wire rstn,
input wire sel,
input wire rx_en,
input wire mode,
input wire baud_clk,
input wire [9:0] bit_cnto,
// Outputs:
output reg [9:0] bit_cntn,
output wire start_bit,
output wire end_bit,
output reg [9:0] data_bit
);
/* -------------------
internal wires/regs
------------------- */
localparam eight_bit = 9;
localparam ten_bit = 11;
wire [9:0] upper_cnt;
/* ----------------
conditions check
---------------- */
assign upper_cnt = (mode == 1'b1) ? ten_bit : eight_bit;
assign start_bit = (bit_cnto == 10'b0) ? 1'b1 : 1'b0;
assign end_bit = (bit_cnto == upper_cnt) ? 1'b1 : 1'b0;
/* -------------
CONTROL Logic
------------- */
always @ *
begin
casex ({rstn, sel, rx_en, start_bit, end_bit, baud_clk})
// reset
{1'b0, 1'bx, 1'bx, 1'bx , 1'bx, 1'bx}: begin
bit_cntn = 10'b0;
data_bit = 10'bx;
end
// Data bit. Current bit
{1'b0, 1'b1, 1'b1, 1'b0 , 1'b0, 1'b0}: begin
bit_cntn = bit_cnto;
data_bit = bit_cnto - 10'b1;
end
// Data bit. Next bit
{1'b0, 1'b1, 1'b1, 1'b0 , 1'b0, 1'b1}: begin
bit_cntn = bit_cnto + 10'b1;
data_bit = bit_cnto - 10'b1;
end
// Start bit. Current bit
{1'b0, 1'b1, 1'b1, 1'b1 , 1'b0, 1'b0}: begin
bit_cntn = bit_cnto;
data_bit = 10'bx;
end
// Start bit. Next bit.
{1'b0, 1'b1, 1'b1, 1'b1 , 1'b0, 1'b1}: begin
bit_cntn = bit_cnto + 10'b1;
data_bit = 10'bx;
end
// End bit. Current bit
{1'b0, 1'b1, 1'b1, 1'b0 , 1'b1, 1'b0}: begin
bit_cntn = bit_cnto;
data_bit = 10'bx;
end
// End bit. Next bit
{1'b0, 1'b1, 1'b1, 1'b0 , 1'b1, 1'b1}: begin
bit_cntn = bit_cnto;
data_bit = 10'bx;
end
default: begin
bit_cntn = 10'b0;
data_bit = 10'bx;
end
endcase
end
endmodule
| 7.687749 |
module !!!
----------------------------------------
Receive data bits
*/
module apb_rx_dp
(
// Inputs:
input wire rstn,
input wire sel,
input wire rx_en,
input wire rx_in,
input wire start_bit,
input wire end_bit,
input wire [9:0] bit_cnto,
input wire [9:0] data_bit,
// Outputs:
output reg [31:0] rx_data
);
/* -----------------------
Internal Data variables
----------------------- */
/* ---------
Data Path
---------- */
always @ *
begin
casex ({rstn, sel, rx_en, start_bit, end_bit, data_bit})
{1'b0, 1'bx, 1'bx, 1'bx, 1'bx, 10'bx}: rx_data <= 32'bx; // Reset
{1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 10'd0}: rx_data[0] <= rx_in; // RX data bit 0
{1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 10'd1}: rx_data[0] <= rx_in; // RX data bit 1
{1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 10'd2}: rx_data[0] <= rx_in; // RX data bit 2
{1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 10'd3}: rx_data[0] <= rx_in; // RX data bit 3
{1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 10'd4}: rx_data[0] <= rx_in; // RX data bit 4
{1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 10'd5}: rx_data[0] <= rx_in; // RX data bit 5
{1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 10'd6}: rx_data[0] <= rx_in; // RX data bit 6
{1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 10'd7}: rx_data[0] <= rx_in; // RX data bit 7
{1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 10'd8}: rx_data[0] <= rx_in; // RX data bit 8
{1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 10'd9}: rx_data[0] <= rx_in; // RX data bit 9
{1'b1, 1'b1, 1'b1, 1'b1, 1'b0, 10'bx}: rx_data <= 32'b0; // Start bit
{1'b1, 1'b1, 1'b1, 1'b0, 1'b1, 10'bx}: rx_data <= rx_data; // End bit
default: rx_data = rx_data;
endcase
end
endmodule
| 7.687749 |
module apb_rx_tb ();
/* -------------------
Essential variables
------------------- */
localparam period = 5;
localparam cycle = period * 2;
reg clk;
reg rstn;
reg sel;
reg mode;
reg [19:0] baud;
/* ---------------
apb RX variables
--------------- */
// Inputs:
reg rx_en; // set DUTY & PERIOD. enable PWM
reg rx_in; // input data for transmission
// Outputs:
wire [31:0] rx_data;
/* ---------------------
test module instances
--------------------- */
apb_rx rx (
// Inputs:
.clk (clk),
.rstn (rstn),
.sel (sel),
.rx_en(rx_en),
.mode (mode),
.baud (baud),
.rx_in(rx_in),
// Outputs:
.rx_data(rx_data)
);
/* ----------------
Clock Generation
---------------- */
initial clk <= 1'b1;
always #(period) clk <= ~clk;
/* -------------
Reset Control
------------- */
initial begin
rstn <= 1'b0;
sel <= 1'b0;
rx_en <= 1'b0;
mode <= 1'b0;
#(cycle * 2) rstn <= 1'b1;
end
/* ----------
Simulation
---------- */
initial begin
#(cycle * 2)
/* --- Cycle 1 ---
Bauddiv = 16
Mode = 8 bit
Din = 10'b00_0011_0101
*/
sel <= 1'b1;
mode <= 1'b0;
baud <= 20'd16;
din <= 10'b00_0011_0101;
#(cycle) sel <= 1'b0;
#(cycle)
// Start TX & RX
sel <= 1'b1;
set <= 1'b1;
rx_en <= 1'b1;
#(cycle * 160)
// Stop TX & RX
sel <= 1'b0;
set <= 1'b0;
rx_en <= 1'b0;
din <= 10'bx;
baud <= 20'bx;
/* --- End of Cycle 1 --- */
#(cycle * 10)
/* --- Cycle 2 ---
Bauddiv = 20
Mode = 10 bit
Din = 10'b11000_01010
*/
sel <= 1'b1;
mode <= 1'b1;
baud <= 20'd20;
din <= 10'b11000_01010;
#(cycle) sel <= 1'b0;
#(cycle)
// Start Tx & RX
sel <= 1'b1;
set <= 1'b1;
rx_en <= 1'b1;
#(cycle * 240)
// Stop TX & RX
sel <= 1'b0;
set <= 1'b0;
din <= 10'bx;
baud <= 20'bx;
/* --- End of Cycle 2 --- */
#(cycle * 10) $finish();
end
endmodule
| 7.836132 |
module APB_SLAVE (
// APB SLAVE PORT INTERFACE
input PCLK,
input PRESETn,
input [`APB_ADDR_WIDTH-1:0] PADDR,
input PWRITE,
input PSEL,
input PENABLE,
input [`APB_DATA_WIDTH-1:0] PWDATA,
output reg [`APB_DATA_WIDTH-1:0] PRDATA,
output reg PREADY,
input TrFr,
// SPI INTERFACE
output reg [ `SPI_REG_WIDTH-1:0] SPI_CR_1,
output reg [ `SPI_REG_WIDTH-1:0] SPI_CR_2,
output reg [ `SPI_REG_WIDTH-1:0] SPI_BR_R,
output reg [ `SPI_REG_WIDTH-1:0] SPI_ST_R,
output reg [ `SPI_REG_WIDTH-1:0] SPI_DATA_Reg_1,
output reg [ `SPI_REG_WIDTH-1:0] SPI_DATA_Reg_2,
output reg [ `SPI_REG_WIDTH-1:0] SPI_DATA_Reg_3,
output reg [ `SPI_REG_WIDTH-1:0] SPI_DATA_Reg_4
);
/////////////////////////////////////////////
// Signal Description ////
/////////////////////////////////////////////
localparam IDLE = 2'b00;
localparam SETUP = 2'b01;
localparam ENABLE = 2'b10;
reg [1:0] STATE;
always @(posedge PCLK or negedge PRESETn) begin
if (!PRESETn) begin
STATE <= IDLE;
PREADY <= 0;
end else begin
PREADY <= 0;
case (STATE)
IDLE: begin
PREADY <= 1;
//if(PSEL && !PENABLE)
if (TrFr) STATE <= SETUP;
else STATE <= IDLE;
end
SETUP: begin
if (PENABLE) STATE <= ENABLE;
else STATE <= IDLE;
end
ENABLE: begin
if (PENABLE) STATE <= SETUP;
else STATE <= IDLE;
end
endcase
end
end
assign write_en = PWRITE && (STATE == ENABLE);
assign read_en = !PWRITE && (STATE == SETUP);
//always@(PADDR,PWDATA,write_en)
always @(posedge PCLK or negedge PRESETn) begin
if (!PRESETn) begin
PRDATA <= 8'd0;
SPI_CR_1 <= 8'd0;
SPI_CR_2 <= 8'd0;
SPI_BR_R <= 8'd0;
SPI_ST_R <= 8'd0;
SPI_DATA_Reg_1 <= 8'd0;
SPI_DATA_Reg_2 <= 8'd0;
SPI_DATA_Reg_3 <= 8'd0;
SPI_DATA_Reg_4 <= 8'd0;
end else begin
if (write_en) begin
case (PADDR)
3'b000: SPI_CR_1 <= PWDATA;
3'b001: SPI_CR_2 <= PWDATA;
3'b010: SPI_BR_R <= PWDATA;
3'b011: SPI_ST_R <= PWDATA;
3'b100: SPI_DATA_Reg_1 <= PWDATA;
3'b101: SPI_DATA_Reg_2 <= PWDATA;
3'b110: SPI_DATA_Reg_3 <= PWDATA;
3'b111: SPI_DATA_Reg_4 <= PWDATA;
default: SPI_CR_1 <= PWDATA;
endcase
end else if (read_en && PENABLE) begin
case (PADDR)
3'b000: PRDATA <= SPI_CR_1;
3'b001: PRDATA <= SPI_CR_2;
3'b010: PRDATA <= SPI_BR_R;
3'b011: PRDATA <= SPI_ST_R;
3'b100: PRDATA <= SPI_DATA_Reg_1;
3'b101: PRDATA <= SPI_DATA_Reg_2;
3'b110: PRDATA <= SPI_DATA_Reg_3;
3'b111: PRDATA <= SPI_DATA_Reg_4;
default: PRDATA <= SPI_CR_1;
endcase
end else begin
SPI_CR_1 <= SPI_CR_1;
SPI_CR_2 <= SPI_CR_2;
SPI_BR_R <= SPI_BR_R;
SPI_ST_R <= SPI_ST_R;
SPI_DATA_Reg_1 <= SPI_DATA_Reg_1;
SPI_DATA_Reg_2 <= SPI_DATA_Reg_2;
SPI_DATA_Reg_3 <= SPI_DATA_Reg_3;
SPI_DATA_Reg_4 <= SPI_DATA_Reg_4;
end
end
end
endmodule
| 8.643298 |
module apb_slaveinterface (
input Pwrite,
input Penable,
input [ 2:0] Pselx,
input [31:0] Paddr,
input [31:0] Pwdata,
inout [31:0] Pdata, //Tristate Buffer for read and write bus
output [31:0] Paddr_out,
output [31:0] Pwdata_out,
output Pwrite_out,
output Penable_out,
output [ 2:0] Pselx_out,
output reg [31:0] Prdata
);
assign Pwrite_out = Pwrite;
assign Penable_out = Penable;
assign Paddr_out = Paddr;
assign Pwdata_out = Pwdata;
assign Pselx_out = Pselx;
always @(*)
if (Penable && !Pwrite) Prdata = $random;
else Prdata = 32'bx;
assign Pdata = (Pwrite) ? Pwdata : Prdata;
endmodule
| 7.528235 |
module PREFIX_mem (
PORTS
);
parameter MEM_WORDS = EXPR((2 ^ ADDR_BITS) / (DATA_BITS / 8));
parameter ADDR_LSB = LOG2(EXPR(DATA_BITS / 8));
input clk;
input reset;
revport GROUP_STUB_MEM;
reg [ DATA_BITS-1:0] Mem [MEM_WORDS-1:0];
reg [ DATA_BITS-1:0] DOUT;
wire [ DATA_BITS-1:0] BitSEL;
wire [ADDR_BITS-1:ADDR_LSB] ADDR_WR_word = ADDR_WR[ADDR_BITS-1:ADDR_LSB];
wire [ADDR_BITS-1:ADDR_LSB] ADDR_RD_word = ADDR_RD[ADDR_BITS-1:ADDR_LSB];
assign BitSEL = {CONCAT({8{BSEL[BX]}},)};
always @(posedge clk)
if (WR)
Mem[ADDR_WR_word] <= #FFD(Mem[ADDR_WR_word] & ~BitSEL) | (DIN & BitSEL);
always @(posedge clk or posedge reset)
if (reset) DOUT <= #FFD{DATA_BITS{1'b0}};
else if (RD) DOUT <= #FFD Mem[ADDR_RD_word];
endmodule
| 6.889752 |
module apb_slave_top #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input PCLK,
input PRESETn,
input [ ADDR_WIDTH-1:0] PADDR,
input PSEL,
input PENABLE,
input PWRITE,
input [ DATA_WIDTH-1:0] PWDATA,
input [DATA_WIDTH/8-1:0] PSTRB,
output PREADY,
output [ DATA_WIDTH-1:0] PRDATA,
output SLVERROR
);
wire wr, rd;
wire wdone, rvalid;
wire [ ADDR_WIDTH-1:0] addr;
wire [ DATA_WIDTH-1:0] wdata;
wire [DATA_WIDTH/8-1:0] byte_en;
wire [ DATA_WIDTH-1:0] rdata;
apb_slave #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH)
) U_APB_SLAVE (
.PCLK (PCLK),
.PRESETn (PRESETn),
.PADDR (PADDR),
.PSEL (PSEL),
.PENABLE (PENABLE),
.PWRITE (PWRITE),
.PWDATA (PWDATA),
.PSTRB (PSTRB),
.PREADY (PREADY),
.PRDATA (PRDATA),
.SLVERROR(SLVERROR),
.wr (wr),
.rd (rd),
.addr (addr),
.wdata (wdata),
.byte_en (byte_en),
.wdone (wdone),
.rvalid (rvalid),
.rdata (rdata)
);
SRAM #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH)
) U_SRAM (
.clk (PCLK),
.rstn (PRESETn),
.wr (wr),
.rd (rd),
.addr (addr),
.wdata (wdata),
.byte_en(byte_en),
.wdone (wdone),
.rvalid (rvalid),
.rdata (rdata)
);
endmodule
| 7.870532 |
module apb_slave_wrapper #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8,
parameter SLV_ADDR_WIDTH = 8,
parameter SLV_CNT = 1
) (
input PCLK,
input PRESETn,
input [ ADDR_WIDTH-1:0] PADDR,
input [ SLV_CNT-1:0] PSELx,
input [ DATA_WIDTH-1:0] PWDATA,
input [DATA_WIDTH/8-1:0] PSTRB,
input PENABLE,
input PWRITE,
output PREADY,
output [ DATA_WIDTH-1:0] PRDATA,
output PSLVERROR
);
wire [ SLV_CNT-1:0] READY;
wire [ SLV_CNT-1:0] SLVERROR;
wire [SLV_CNT*DATA_WIDTH-1:0] RDATA;
genvar i;
generate
for (i = 0; i < SLV_CNT; i = i + 1'b1) begin : SLAVE_TOP
apb_slave_top #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(SLV_ADDR_WIDTH)
) U_APB_SLAVE_TOP (
.PCLK (PCLK),
.PRESETn (PRESETn),
.PADDR ({SLV_ADDR_WIDTH{PSELx[i]}} & PADDR[SLV_ADDR_WIDTH-1:0]),
.PSEL (PSELx[i]),
.PENABLE (PSELx[i] & PENABLE),
.PWRITE (PSELx[i] & PWRITE),
.PWDATA ({DATA_WIDTH{PSELx[i]}} & PWDATA),
.PSTRB ({DATA_WIDTH / 8{PSELx[i]}} & PSTRB),
.PREADY (READY[i]),
.PRDATA (RDATA[i*DATA_WIDTH+:DATA_WIDTH]),
.SLVERROR(SLVERROR[i])
);
end
endgenerate
reg DEC_ERROR;
wire DEC_ERROR_i;
assign PREADY = |READY | DEC_ERROR;
assign PSLVERROR = |SLVERROR | DEC_ERROR;
always @(posedge PCLK)
if (!PRESETn | DEC_ERROR) DEC_ERROR <= 1'b0;
else DEC_ERROR <= DEC_ERROR_i;
//MAX 4 SLAVES supported
//DECODE ERROR generation for out-of range
generate
if (SLV_CNT == 1) begin
assign PRDATA = READY[0] ? RDATA[0*DATA_WIDTH+:DATA_WIDTH] : {DATA_WIDTH{1'b0}};
assign DEC_ERROR_i = PADDR > {SLV_ADDR_WIDTH{1'b1}};
end else if (SLV_CNT == 2) begin
assign PRDATA = READY[0]? RDATA[0*DATA_WIDTH +: DATA_WIDTH] :
READY[1]? RDATA[1*DATA_WIDTH +: DATA_WIDTH] : {DATA_WIDTH{1'b0}};
assign DEC_ERROR_i = PADDR > {SLV_ADDR_WIDTH + 1{1'b1}};
end else if (SLV_CNT == 3) begin
assign PRDATA = READY[0]? RDATA[0*DATA_WIDTH +: DATA_WIDTH] :
READY[1]? RDATA[1*DATA_WIDTH +: DATA_WIDTH] :
READY[2]? RDATA[2*DATA_WIDTH +: DATA_WIDTH] : {DATA_WIDTH{1'b0}};
assign DEC_ERROR_i = PADDR > {SLV_ADDR_WIDTH + 2{1'b1}};
end else if (SLV_CNT == 4) begin
assign PRDATA = READY[0]? RDATA[0*DATA_WIDTH +: DATA_WIDTH] :
READY[1]? RDATA[1*DATA_WIDTH +: DATA_WIDTH] :
READY[2]? RDATA[2*DATA_WIDTH +: DATA_WIDTH] :
READY[3]? RDATA[3*DATA_WIDTH +: DATA_WIDTH] : {DATA_WIDTH{1'b0}};
assign DEC_ERROR_i = PADDR > {SLV_ADDR_WIDTH + 3{1'b1}};
end
endgenerate
endmodule
| 7.588113 |
module apb_slv_iface (
// APB Interface signals
input wire pclk,
input wire preset_n,
input wire [31:0] paddr,
input wire psel,
input wire penable,
input wire pwrite,
input wire [31:0] pwdata,
output wire pready,
output wire [31:0] prdata,
output wire pslverr,
// Local bus registe control signals
output wire lb_wrout, // 1- write / 0 - read
output wire [31:0] lb_aout,
output wire [31:0] lb_dout,
output wire lb_cs,
input wire lb_rdyh,
input wire [31:0] lb_din
);
// Internal signal declaration
reg lb_wrout_reg;
reg [31:0] lb_aout_reg;
reg [31:0] lb_dout_reg;
reg lb_cs_reg;
// No error as this used only for the register access
assign pslverr = 1'b0;
//==========================================================================//
// Chip select is generated once the slave is selected
//==========================================================================//
always @(posedge pclk or negedge preset_n) begin
if (preset_n == 1'b0) lb_cs_reg <= 1'b0;
else lb_cs_reg <= psel;
end
assign lb_cs = lb_wrout_reg ? 1'b1 : 1'b0;
//==========================================================================//
// This code include both setup adn access phase of APB
//==========================================================================//
always @(posedge pclk or negedge preset_n) begin
if (preset_n == 1'b0) lb_wrout_reg <= 1'b0;
else if (pwrite == 1'b1 && psel == 1'b1 && penable == 1'b1 && lb_wrout_reg == 1'b0)
lb_wrout_reg <= 1'b1;
else lb_wrout_reg <= 1'b0;
end
assign lb_wrout = lb_wrout_reg;
//==========================================================================//
// Latch the address if the slave is selected
//==========================================================================//
always @(posedge pclk or negedge preset_n) begin
if (preset_n == 1'b0) lb_aout_reg <= 32'b0;
else if (psel == 1'b1) lb_aout_reg <= paddr;
end
assign lb_dout = lb_dout_reg;
assign lb_aout = lb_wrout_reg ? lb_aout_reg : paddr;
//==========================================================================//
// Latch the write data when the slave is selcted and enabled
//==========================================================================//
always @(posedge pclk or negedge preset_n) begin
if (preset_n == 1'b0) lb_dout_reg <= 32'b0;
else if (pwrite == 1'b1 && psel == 1'b1 && penable == 1'b1) lb_dout_reg <= pwdata;
end
assign prdata = lb_rdyh ? lb_din : 32'b0;
// Since the Peripheral has a TWO clock fixed delay PREADY is tied high for
// if peripheral has more than two clock delay this logic needs to be modified
// accordingly
assign pready = 1'b1;
endmodule
| 8.651964 |
module APB_SPI (
input wire PCLK,
input wire PRESETn,
input wire PWRITE,
input wire [31:0] PWDATA,
input wire [31:0] PADDR,
input wire PENABLE,
input PSEL,
output wire PREADY,
output wire [31:0] PRDATA,
input wire MSI,
output wire MSO,
output wire SSn,
output wire SCLK,
output IRQ
);
reg [7:0] SPI_DATAi_REG;
wire [7:0] SPI_DATAo_REG;
reg [1:0] SPI_CTRL_REG;
wire SPI_STATUS_REG;
reg [9:0] SPI_CFG_REG;
reg [0:0] SPI_IM_REG;
wire go, cpol, cpha, done, busy, csb;
wire [7:0] datai, datao, clkdiv;
// The Control Register -- Size: 2 -- offset: 4
always @(posedge PCLK, negedge PRESETn) begin
if (!PRESETn) begin
SPI_CTRL_REG <= 2'b0;
end else if (PENABLE & PWRITE & PREADY & PSEL & PADDR[2] & ~PADDR[3] & ~PADDR[4])
SPI_CTRL_REG <= PWDATA[1:0];
end
// Configuration Register -- Size; 10 -- Offset: 8
always @(posedge PCLK, negedge PRESETn) begin
if (!PRESETn) begin
SPI_CFG_REG <= 10'b0;
end else if (PENABLE & PWRITE & PREADY & PSEL & PADDR[3] & ~PADDR[2] & ~PADDR[4])
SPI_CFG_REG <= PWDATA[9:0];
end
// Data Register -- Size: 8 -- Offset: 0
always @(posedge PCLK, negedge PRESETn) begin
if (!PRESETn) begin
SPI_DATAi_REG <= 8'b0;
end else if (PENABLE & PWRITE & PREADY & PSEL & ~PADDR[2] & ~PADDR[3] & ~PADDR[4])
SPI_DATAi_REG <= PWDATA[7:0];
end
// IM Register -- Size: 1 -- Offset: 0x14
always @(posedge PCLK, negedge PRESETn) begin
if (!PRESETn) begin
SPI_IM_REG <= 1'b0;
end else if (PENABLE & PWRITE & PREADY & PSEL & PADDR[2] & ~PADDR[3] & PADDR[4])
SPI_IM_REG <= PWDATA[0:0];
end
assign datai = SPI_DATAi_REG[7:0];
assign go = SPI_CTRL_REG[0];
assign SSn = ~SPI_CTRL_REG[1];
assign cpol = SPI_CFG_REG[0];
assign cpha = SPI_CFG_REG[1];
assign clkdiv = SPI_CFG_REG[9:2];
assign SPI_STATUS_REG = DONE;
assign SPI_DATAo_REG = datao;
reg DONE;
always @(posedge PCLK, negedge PRESETn) begin
if (!PRESETn) begin
DONE <= 1'b0;
end else if (done) DONE <= 1'b1;
else if (go) DONE <= 1'b0;
end
spi_master #(
.DATA_WIDTH(8),
.CLK_DIVIDER_WIDTH(8)
) SPI_CTRL (
.clk(PCLK),
.resetb(PRESETn),
.CPOL(cpol),
.CPHA(cpha),
.clk_divider(clkdiv),
.go(go),
.datai(datai),
.datao(datao),
//.busy(busy),
.done(done),
.dout(MSI),
.din (MSO),
//.csb(ss),
.sclk(SCLK)
);
assign PRDATA[31:0] = (PADDR[2] & PADDR[4]) ? {31'd0, SPI_IM_REG} :
(PADDR[2]) ? {30'd0,SPI_CTRL_REG} :
(PADDR[3]) ? {{22'd0,SPI_CFG_REG}} :
(PADDR[4]) ? {31'd0,SPI_STATUS_REG} :
{24'd0,SPI_DATAo_REG};
assign PREADY = 1'b1;
assign IRQ = SPI_IM_REG[0] & DONE;
endmodule
| 6.55338 |
module apb_spi_top #(
parameter ADDRWIDTH = 2'd3,
parameter DATAWIDTH = 4'd8
) (
pclk, // APB Clock
spi_clk, // SPI Clock
preset_n, // Active Low Reset
paddr, // Address
psel, // APB Select
penable, // APB Enable
pwrite, // Read Write signal 1-> Write 0->Read
pwdata, // Write DATA
pready, // Ready from Slave
prdata, // Read Data from slave
pslverr // Transfer Failure signal
);
input pclk;
input spi_clk;
input preset_n;
input [ADDRWIDTH-1:0] paddr;
input psel;
input penable;
input pwrite;
input [DATAWIDTH-1:0] pwdata;
output pready;
output [DATAWIDTH-1:0] prdata;
output pslverr;
wire [DATAWIDTH-1 : 0] w_spi_data_out;
wire [DATAWIDTH-1 : 0] w_spi_data_in;
wire w_spi_enable;
wire w_spi_clk;
wire [ 2:0] w_CS;
wire w_MISO;
wire w_MOSI;
apb_slave #(
.ADDRWIDTH(ADDRWIDTH),
.DATAWIDTH(DATAWIDTH)
) i_apb_slave (
.pclk (pclk),
.preset_n(preset_n),
.paddr (paddr),
.pwrite (pwrite),
.psel (psel),
.penable (penable),
.pwdata (pwdata),
.prdata (prdata),
.pready (pready),
.pslverr (pslverr),
.data_rx (w_spi_data_out),
.data_tx (w_spi_data_in)
);
handshake_syn i_handshake_syn (
.pclk (pclk),
.spi_clk (spi_clk),
.preset_n (preset_n),
.penable (penable),
.pready (w_rw_ack),
.spi_enable(w_spi_enable),
.spi_ready (pready)
);
spi_master #(
.ADDRWIDTH(ADDRWIDTH),
.DATAWIDTH(DATAWIDTH)
) i_spi_master (
.clk (spi_clk),
.reset_n (preset_n),
.data_in (w_spi_data_in),
.address (paddr),
.enable (w_spi_enable),
.rw_en (pwrite),
.data_out(w_spi_data_out),
.rw_ack (w_rw_ack),
.spi_clk (w_spi_clk),
.CS (w_CS),
.MISO (w_MISO),
.MOSI (w_MOSI)
);
spi_slave i_spi_slave (
.spi_clk(w_spi_clk),
.CS (w_CS),
.MISO (w_MISO),
.MOSI (w_MOSI)
);
endmodule
| 8.069158 |
module APB_SPI_WRAP (
// APB SLAVE PORT INTERFACE
input PCLK,
input PRESETn,
input [`APB_ADDR_WIDTH-1:0] PADDR,
input PWRITE,
input PSEL,
input PENABLE,
input [`APB_DATA_WIDTH-1:0] PWDATA,
output [`APB_DATA_WIDTH-1:0] PRDATA,
output PREADY,
//Interrupt
output wire SPI_INT,
// SPI signals
output scs_o,
output sck_o,
input miso_i,
output mosi_o,
output [ 2:0] devs
);
simple_spi_top spi_master_top (
.clk_i (PCLK), // clock
.rst_i (PRESETn), // reset (asynchronous active low)
.cyc_i (PSEL), // cycle
.stb_i (PENABLE), // strobe
.adr_i (PADDR[7:3]), // address
.we_i (PWRITE), // write enable
.dat_i (PWDATA), // data input
.dat_o (PRDATA), // data output
.ack_o (PREADY), // normal bus termination
.inta_o(SPI_INT), // interrupt output
//SPI INTERFACE
.sck_o (sck_o), // serial clock output
.mosi_o(mosi_o), // MasterOut SlaveIN
.miso_i(miso_i), // MasterIn SlaveOut
.scs_o (scs_o),
.devs_o(devs)
);
endmodule
| 7.180925 |
module apb_splitter #(
parameter W_ADDR = 16,
parameter W_DATA = 32,
parameter N_SLAVES = 2,
parameter ADDR_MAP = 32'h0000_4000,
parameter ADDR_MASK = 32'hc000_c000
) (
input wire [W_ADDR-1:0] apbs_paddr,
input wire apbs_psel,
input wire apbs_penable,
input wire apbs_pwrite,
input wire [W_DATA-1:0] apbs_pwdata,
output wire apbs_pready,
output wire [W_DATA-1:0] apbs_prdata,
output wire apbs_pslverr,
output wire [N_SLAVES*W_ADDR-1:0] apbm_paddr,
output wire [ N_SLAVES-1:0] apbm_psel,
output wire [ N_SLAVES-1:0] apbm_penable,
output wire [ N_SLAVES-1:0] apbm_pwrite,
output wire [N_SLAVES*W_DATA-1:0] apbm_pwdata,
input wire [ N_SLAVES-1:0] apbm_pready,
input wire [N_SLAVES*W_DATA-1:0] apbm_prdata,
input wire [ N_SLAVES-1:0] apbm_pslverr
);
integer i;
reg [N_SLAVES-1:0] slave_mask;
always @(*) begin
for (i = 0; i < N_SLAVES; i = i + 1) begin
slave_mask[i] = (apbs_paddr & ADDR_MASK[i*W_ADDR+:W_ADDR]) == ADDR_MAP[i*W_ADDR+:W_ADDR];
end
end
assign apbs_pready = !slave_mask || slave_mask & apbm_pready;
assign apbs_pslverr = !slave_mask || slave_mask & apbm_pslverr;
assign apbm_paddr = {N_SLAVES{apbs_paddr}};
assign apbm_psel = slave_mask & {N_SLAVES{apbs_psel}};
assign apbm_penable = slave_mask & {N_SLAVES{apbs_penable}};
assign apbm_pwrite = slave_mask & {N_SLAVES{apbs_pwrite}};
assign apbm_pwdata = {N_SLAVES{apbs_pwdata}};
onehot_mux #(
.N_INPUTS(N_SLAVES),
.W_INPUT (W_DATA)
) prdata_mux (
.in (apbm_prdata),
.sel(slave_mask),
.out(apbs_prdata)
);
endmodule
| 6.948851 |
module apb_sram_inf (
clk,
rstn,
psel,
penable,
paddr,
pwrite,
pwdata,
pready,
prdata
);
parameter mem_depth = 1024;
parameter mem_width = 32;
parameter mem_bitw = 10;
parameter IDEL = 0;
parameter SETUP = 1;
parameter ENABLE = 2;
input wire clk;
input wire rstn;
input wire psel;
input wire penable;
input wire [mem_bitw+1:0] paddr; //byte address;
input wire pwrite;
input wire [31:0] pwdata;
output wire pready;
output reg [31:0] prdata;
reg [1:0] sta;
reg [1:0] nsta;
reg apb_write;
reg apb_read;
reg pready_pre;
reg [mem_bitw-1:0] apb_addr;
reg [31:0] apb_wdata;
wire mem_cs;
wire mem_we;
wire [mem_width-1:0] mem_dout;
//fsm;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
sta = 2'd0;
end else begin
sta = nsta;
end
end
//state transition;
always @(*) begin
nsta = sta;
case (sta)
IDEL: begin
if ((psel == 1'b1) && (penable == 1'b0)) begin
nsta = SETUP;
end else begin
nsta = IDEL;
end
end
SETUP: begin
if ((psel == 1'b1) && (penable == 1'b1)) begin
nsta = ENABLE;
end else begin
nsta = IDEL;
end
end
ENABLE: begin
if ((psel == 1'b1) && (penable == 1'b1)) begin
nsta = ENABLE;
end else begin
nsta = IDEL;
end
end
default: begin
nsta <= IDEL;
end
endcase
end
//fsm output;
always @(*) begin
if (sta == IDEL) begin
apb_write = 1'b0;
apb_read = 1'b0;
pready_pre = 1'b0;
end else if (sta == SETUP) begin
apb_addr = paddr[mem_bitw+1:2];
if (pwrite) begin
apb_write = 1'b1;
apb_read = 1'b0;
apb_wdata = pwdata;
pready_pre = 1'b0;
end else if (!pwrite) begin
apb_write = 1'b0;
apb_read = 1'b1;
pready_pre = 1'b0;
end
end else if (sta == ENABLE) begin
if (pwrite) begin
pready_pre = 1'b1;
end else if (!pwrite) begin
prdata = mem_dout;
pready_pre = 1'b1;
end
end
end
assign pready = pready_pre; //apb trans done;
assign mem_cs = (apb_write | apb_read); //sram cs;
assign mem_we = apb_write; //sram we;
spsram u_spsram (
.clk (clk),
.cs (mem_cs),
.we (mem_we),
.addr(apb_addr),
.din (apb_wdata),
.dout(mem_dout)
);
endmodule
| 7.819726 |
module apb_timer #(
parameter APB_ADDR_WIDTH = 12, //APB slaves are 4KB by default
parameter TIMER_CNT = 2 // how many timers should be instantiated
) (
HCLK,
HRESETn,
PADDR,
PWDATA,
PWRITE,
PSEL,
PENABLE,
PRDATA,
PREADY,
PSLVERR,
irq_o
);
//parameter APB_ADDR_WIDTH = 12;
//parameter TIMER_CNT = 2;
input wire HCLK;
input wire HRESETn;
input wire [APB_ADDR_WIDTH - 1:0] PADDR;
input wire [31:0] PWDATA;
input wire PWRITE;
input wire PSEL;
input wire PENABLE;
output reg [31:0] PRDATA;
output reg PREADY;
output reg PSLVERR;
output wire [(TIMER_CNT * 2) - 1:0] irq_o;
reg [TIMER_CNT - 1:0] psel_int;
wire [TIMER_CNT - 1:0] pready;
wire [TIMER_CNT - 1:0] pslverr;
wire [$clog2(TIMER_CNT) - 1:0] slave_address_int;
wire [(TIMER_CNT * 32) - 1:0] prdata;
assign slave_address_int = PADDR[$clog2(TIMER_CNT)+(2'd2+1):2'd2+2];
always @(*) begin
psel_int = 1'sb0;
psel_int[slave_address_int] = PSEL;
end
always @(*)
if (psel_int != {TIMER_CNT{1'sb0}}) begin
PRDATA = prdata[slave_address_int*32+:32];
PREADY = pready[slave_address_int];
PSLVERR = pslverr[slave_address_int];
end else begin
PRDATA = 1'sb0;
PREADY = 1'b1;
PSLVERR = 1'b0;
end
genvar k;
generate
for (k = 0; k < TIMER_CNT; k = k + 1) begin : TIMER_GEN
timer timer_i (
.HCLK(HCLK),
.HRESETn(HRESETn),
.PADDR(PADDR),
.PWDATA(PWDATA),
.PWRITE(PWRITE),
.PSEL(psel_int[k]),
.PENABLE(PENABLE),
.PRDATA(prdata[k*32+:32]),
.PREADY(pready[k]),
.PSLVERR(pslverr[k]),
.irq_o(irq_o[(2*k)+1:2*k])
);
end
endgenerate
endmodule
| 8.234696 |
module APB_top (
input PCLK,
input PRESETn,
input Transfer,
input Wr_Rd,
input [4:0] Address,
input [31:0] write_data,
output [31:0] read_data
);
wire [4:0] PADDR;
wire [31:0] PWDATA, PRDATA;
wire PSELx, PENABLE, PWRITE, PREADY, PSLVERR;
APB_master Design_master (
Transfer,
Wr_Rd,
Address,
write_data,
read_data,
PCLK,
PRESETn,
PREADY,
PRDATA,
PSLVERR,
PADDR,
PSELx,
PENABLE,
PWRITE,
PWDATA
);
APB_slave Design_slave (
PCLK,
PRESETn,
PADDR,
PSELx,
PENABLE,
PWRITE,
PWDATA,
PREADY,
PRDATA,
PSLVERR
);
endmodule
| 7.879159 |
module !!!
----------------------------------------
Transmit 8/10 bit (depending on mode)
Transmit bit-by-bit according to baudrate
Control Path:
Data Path:
*/
module apb_tx
(
// Input:
input wire clk,
input wire rstn, // active LOW to reset
input wire sel, // activate apb_tx module
input wire set, // set DUTY & PERIOD. enable PWM
input wire mode, // switch between 8 bit & 10 bit tx
input wire [9:0] din, // input data for transmission
input wire [19:0] baud, // bauddiv
// Output:
output wire tx_en, // enable transmission
output wire tx_out // transmitted data
);
/* -------------------
internal wires/regs
------------------- */
wire rst;
wire [9:0] bit_cnto;
wire [9:0] bit_cntn;
wire start_bit;
wire end_bit;
wire [9:0] data_bit;
wire [19:0] baud_cnto;
wire [19:0] baud_cntn;
wire baud_clk;
/* ---------------------------
connect CONTROl & DATA path
--------------------------- */
apb_tx_cp tx_cp
(
// Inputs:
.rstn (rstn), // active LOW to reset
.sel (sel), // activate apb_tx module
.set (set), // set DUTY & PERIOD. enable PWM
.baud_clk (baud_clk), // signal to transmit next bit
.bit_cnto (bit_cnto), // # bit transmitted
.mode (mode), // switch between 8 bit & 10 bit tx
// Outputs:
.bit_cntn (bit_cntn), // index of bit transmitting now
.tx_en (tx_en), // signal HIGH to tx data
.start_bit (start_bit), // signal HIGH for tx start bit
.end_bit (end_bit), // signal HIGH for tx end bit
.data_bit (data_bit) // which data bit to tx
);
apb_tx_dp tx_dp
(
// Inputs:
.rstn (rstn), // active LOW to reset
.tx_en (tx_en), // signal to transmit data
.bit_cnto (bit_cnto), // # bit transmitted
.start_bit (start_bit), // signal HIGH for tx start bit
.end_bit (end_bit), // signal HIGH for tx end bit
.data_bit (data_bit), // which data bit to tx
.din (din),
// Outputs:
.tx_out (tx_out)
);
baud_counter baud_counter
(
// Inputs:
.rstn (rstn),
.en (tx_en),
.baud (baud),
.baud_cnto (baud_cnto),
// Outputs:
.baud_cntn (baud_cntn),
.baud_clk (baud_clk)
);
/* ----------------
connecting wires
---------------- */
assign rst = ~rstn;
PipeReg #(10) bit_cnt
(
.CLK (clk),
.RST (rst),
.EN (1'b1),
.D (bit_cntn),
.Q (bit_cnto)
);
PipeReg #(20) baud_cnt
(
.CLK (clk),
.RST (rst),
.EN (1'b1),
.D (baud_cntn),
.Q (baud_cnto)
);
endmodule
| 7.687749 |
module !!!
----------------------------------------
Determine data bit for transmission
*/
module apb_tx_cp
(
// Inputs:
input wire rstn, // active LOW to reset
input wire sel, // activate apb_tx module
input wire set, // set DUTY & PERIOD. enable PWM
input wire baud_clk, // signal to transmit next bit
input wire [9:0] bit_cnto, // # bit transmitted
input wire mode, // switch between 8 bit & 10 bit tx
// Outputs:
output reg [9:0] bit_cntn, // index of bit transmitting now
output reg tx_en, // signal HIGH to tx data
output wire start_bit, // signal HIGH for tx start bit
output wire end_bit, // signal HIGH for tx end bit
output reg [9:0] data_bit // which data bit to tx
);
/* -------------------
internal wires/regs
------------------- */
localparam eight_bit = 9;
localparam ten_bit = 11;
wire [9:0] upper_cnt;
/* ----------------
conditions check
---------------- */
assign upper_cnt = (mode == 1'b1) ? ten_bit : eight_bit;
assign start_bit = (bit_cnto == 10'b0) ? 1'b1 : 1'b0;
assign end_bit = (bit_cnto == upper_cnt) ? 1'b1 : 1'b0;
/* -------------
CONTROL Logic
------------- */
always @ *
begin
casex ({rstn, sel, set, start_bit, end_bit, baud_clk})
// reset
{1'b0, 1'bx, 1'bx, 1'bx , 1'bx, 1'bx}: begin
tx_en = 1'b0;
bit_cntn = 10'b0;
data_bit = 10'bx;
end
// Data bit. Current bit
{1'b1, 1'b1, 1'b1, 1'b0 , 1'b0, 1'b0}: begin
tx_en = 1'b1;
bit_cntn = bit_cnto;
data_bit = bit_cnto - 10'b1;
end
// Data bit. Prep next bit
{1'b1, 1'b1, 1'b1, 1'b0 , 1'b0, 1'b1}: begin
tx_en = 1'b1;
bit_cntn = bit_cnto + 10'b1;
data_bit = bit_cnto - 10'b1;
end
// Start bit. Current bit
{1'b1, 1'b1, 1'b1, 1'b1 , 1'b0, 1'b0}: begin
tx_en = 1'b1;
bit_cntn = bit_cnto;
data_bit = 10'bx;
end
// Start bit. Prep next bit
{1'b1, 1'b1, 1'b1, 1'b1 , 1'b0, 1'b1}: begin
tx_en = 1'b1;
bit_cntn = bit_cnto + 10'b1;
data_bit = 10'bx;
end
// End bit. Current bit
{1'b1, 1'b1, 1'b1, 1'b0 , 1'b1, 1'b0}: begin
tx_en = 1'b1;
bit_cntn = bit_cnto;
data_bit = 10'bx;
end
// End bit. Prep next bit
{1'b1, 1'b1, 1'b1, 1'b0 , 1'b1, 1'b1}: begin
tx_en = 1'b1;
bit_cntn = bit_cnto;
data_bit = 10'bx;
end
default: begin
tx_en = 1'b0;
bit_cntn = 10'b0;
data_bit = 10'bx;
end
endcase
end
endmodule
| 7.687749 |
module !!!
----------------------------------------
Transmit data bits
*/
module apb_tx_dp
(
// Inputs:
input wire rstn, // active LOW to reset
input wire tx_en, // signal to transmit data
input wire [9:0] bit_cnto, // # bit transmitted
input wire start_bit, // signal HIGH for tx start bit
input wire end_bit, // signal HIGH for tx end bit
input wire [9:0] data_bit, // which data bit to tx
input wire [9:0] din,
// Outputs:
output reg tx_out
);
/* ---------
Data Path
---------- */
always @ *
begin
casex ({rstn, tx_en, start_bit, end_bit, data_bit})
{1'b0, 1'bx, 1'bx, 1'bx, 10'bx}: tx_out = 1'b1; // Reset
{1'b1, 1'b1, 1'b0, 1'b0, 10'd0}: tx_out = din[0]; // Data bit 0
{1'b1, 1'b1, 1'b0, 1'b0, 10'd1}: tx_out = din[1]; // Data bit 1
{1'b1, 1'b1, 1'b0, 1'b0, 10'd2}: tx_out = din[2]; // Data bit 2
{1'b1, 1'b1, 1'b0, 1'b0, 10'd3}: tx_out = din[3]; // Data bit 3
{1'b1, 1'b1, 1'b0, 1'b0, 10'd4}: tx_out = din[4]; // Data bit 4
{1'b1, 1'b1, 1'b0, 1'b0, 10'd5}: tx_out = din[5]; // Data bit 5
{1'b1, 1'b1, 1'b0, 1'b0, 10'd6}: tx_out = din[6]; // Data bit 6
{1'b1, 1'b1, 1'b0, 1'b0, 10'd7}: tx_out = din[7]; // Data bit 7
{1'b1, 1'b1, 1'b0, 1'b0, 10'd8}: tx_out = din[8]; // Data bit 8
{1'b1, 1'b1, 1'b0, 1'b0, 10'd9}: tx_out = din[9]; // Data bit 9
{1'b1, 1'b1, 1'b1, 1'b0, 10'dx}: tx_out = 1'b0; // Start bit
{1'b1, 1'b1, 1'b0, 1'b1, 10'dx}: tx_out = 1'b1; // End bit
default: tx_out = 1'b1;
endcase
end
endmodule
| 7.687749 |
module apb_uart_tx #(
parameter BUS_WIDTH = 16,
parameter CELL_DEPTH = 8,
parameter DATA_WIDTH = 8,
parameter ADDR_EXP = 5
) (
input clk,
input reset,
// APB Slave to master interface
input [ 1:0] S_PADDR,
// S_PADDR[0] = write port,
// S_PADDR[1] = read port
input S_PWRITE,
input S_PSELx,
input S_PENABLE,
input [BUS_WIDTH-1:0] S_PWDATA,
output [BUS_WIDTH-1:0] S_PRDATA,
output reg S_PREADY,
output tx_wire,
input rx_wire
);
localparam APB_ADDR_WRITE = 0;
localparam APB_ADDR_READ = 1;
wire apb_we = S_PSELx & S_PENABLE & S_PWRITE;
wire apb_sel = S_PSELx & S_PENABLE;
wire uart_tx_is_transmitting;
wire uart_tx_busy;
wire uart_rx_rdy = 1;
wire [7:0] uart_rx_dout;
wire uart_tx_fifo_full;
reg uart_rx_rdy_clear;
assign S_PRDATA = (apb_sel) ? 16'hAAAA : 16'h0000;
always @(*)
if (S_PADDR == APB_ADDR_WRITE) S_PREADY = (apb_sel) ? (!uart_tx_fifo_full) : 1'b0;
else S_PREADY = (apb_sel) ? uart_rx_rdy : 1'b0;
always @(posedge clk)
if (S_PADDR == APB_ADDR_READ)
if (apb_sel) uart_rx_rdy_clear <= 1;
else uart_rx_rdy_clear <= 0;
always @(posedge clk) if (apb_we) $display($time, "\t\tUART0 <= %h", S_PWDATA[7:0]);
wire uart_tx_transmit_en = apb_we && (!uart_tx_fifo_full);
uart_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_EXP (ADDR_EXP)
) uart_fifo (
.clk(clk),
.rst(reset),
// reciever
//.rx (uart_rx),
//.rx_fifo_pop (uart_rx_fifo_pop)
//.rx_fifo_empty (uart_rx_fifo_empty),
//.rx_byte (uart_rx_byte[7:0]),
//.irq (uart_irq),
// transmitter
.tx (tx_wire),
.busy (uart_tx_busy),
.tx_fifo_full(uart_tx_fifo_full),
.tx_byte (S_PWDATA[7:0]),
.transmit (uart_tx_transmit_en)
);
endmodule
| 8.367163 |
module start_bit_det (
clk,
n_rst,
serial_in,
start_bit_detected,
new_package_detected
);
input clk, n_rst, serial_in;
output start_bit_detected, new_package_detected;
wire start_bit_detected, old_sample, new_sample, sync_phase, n4;
assign new_package_detected = start_bit_detected;
DFFSR sync_phase_reg (
.D (serial_in),
.CLK(clk),
.R (1'b1),
.S (n_rst),
.Q (sync_phase)
);
DFFSR new_sample_reg (
.D (sync_phase),
.CLK(clk),
.R (1'b1),
.S (n_rst),
.Q (new_sample)
);
DFFSR old_sample_reg (
.D (new_sample),
.CLK(clk),
.R (1'b1),
.S (n_rst),
.Q (old_sample)
);
NOR2X1 U6 (
.A(new_sample),
.B(n4),
.Y(start_bit_detected)
);
INVX1 U7 (
.A(old_sample),
.Y(n4)
);
endmodule
| 6.610416 |
module second_flex_counter (
clk,
n_rst,
clear,
shift_strobe,
rollover_val,
packet_done
);
input [3:0] rollover_val;
input clk, n_rst, clear, shift_strobe;
output packet_done;
flex_counter CORE (
.clk(clk),
.n_rst(n_rst),
.clear(clear),
.count_enable(shift_strobe),
.rollover_val(rollover_val),
.rollover_flag(packet_done)
);
endmodule
| 7.910599 |
module sr_9bit (
clk,
n_rst,
serial_in,
shift_strobe,
packet_data
);
output [8:0] packet_data;
input clk, n_rst, serial_in, shift_strobe;
flex_stp_sr_NUM_BITS9_SHIFT_MSB0 CORE (
.clk(clk),
.n_rst(n_rst),
.shift_enable(shift_strobe),
.serial_in(serial_in),
.parallel_out(packet_data)
);
endmodule
| 7.17007 |
module apb_uart_rx (
clk,
n_rst,
serial_in,
psel,
paddr,
penable,
pwrite,
pwdata,
prdata,
pslverr
);
input [2:0] paddr;
input [7:0] pwdata;
output [7:0] prdata;
input clk, n_rst, serial_in, psel, penable, pwrite;
output pslverr;
wire data_ready, overrun_error, framing_error, data_read;
wire [ 7:0] rx_data;
wire [ 3:0] data_size;
wire [13:0] bit_period;
apb_slave A1 (
.clk(clk),
.n_rst(n_rst),
.rx_data(rx_data),
.data_ready(data_ready),
.overrun_error(overrun_error),
.framing_error(framing_error),
.psel(psel),
.paddr(paddr),
.penable(penable),
.pwrite(pwrite),
.pwdata(pwdata),
.data_read(data_read),
.prdata(prdata),
.pslverr(pslverr),
.data_size(data_size),
.bit_period(bit_period)
);
rcv_block A2 (
.clk(clk),
.n_rst(n_rst),
.data_size(data_size),
.bit_period(bit_period),
.serial_in(serial_in),
.data_read(data_read),
.rx_data(rx_data),
.data_ready(data_ready),
.overrun_error(overrun_error),
.framing_error(framing_error)
);
endmodule
| 7.619214 |
module APB_WDT32 (
// APB Interface
// clock and reset
input wire PCLK,
//input wire PCLKG, // Gated clock
input wire PRESETn, // Reset
// input ports
input wire PSEL, // Select
input wire [19:2] PADDR, // Address
input wire PENABLE, // Transfer control
input wire PWRITE, // Write control
input wire [31:0] PWDATA, // Write data
// output ports
output wire [31:0] PRDATA, // Read data
output wire PREADY,
// Device ready
// IP Interface
output IRQ,
// WDTMR register/fields
input [31:0] WDTMR,
// WDLOAD register/fields
output [31:0] WDLOAD,
// WDOV register/fields
input [0:0] WDOV,
// WDOVCLR register/fields
output [0:0] WDOVCLR,
// WDEN register/fields
output [0:0] WDEN
);
wire rd_enable;
wire wr_enable;
assign rd_enable = PSEL & (~PWRITE);
assign wr_enable = PSEL & PWRITE & (PENABLE);
assign PREADY = 1'b1;
reg [31:0] WDLOAD;
reg [0:0] WDOVCLR;
reg [0:0] WDEN;
wire [31:0] WDTMR;
wire [0:0] WDOV;
// Register: WDLOAD
wire WDLOAD_select = wr_enable & (PADDR[19:2] == 18'h1);
always @(posedge PCLK or negedge PRESETn) begin
if (~PRESETn) WDLOAD <= 32'h0;
else if (WDLOAD_select) WDLOAD <= PWDATA;
end
// Register: WDOVCLR
wire WDOVCLR_select = wr_enable & (PADDR[19:2] == 18'h4);
always @(posedge PCLK or negedge PRESETn) begin
if (~PRESETn) WDOVCLR <= 1'h0;
else if (WDOVCLR_select) WDOVCLR <= PWDATA;
end
// Register: WDEN
wire WDEN_select = wr_enable & (PADDR[19:2] == 18'h5);
always @(posedge PCLK or negedge PRESETn) begin
if (~PRESETn) WDEN <= 1'h0;
else if (WDEN_select) WDEN <= PWDATA;
end
// IRQ Enable Register @ offset 0x100
reg [0:0] IRQEN;
wire IRQEN_select = wr_enable & (PADDR[19:2] == 18'h40);
always @(posedge PCLK or negedge PRESETn) begin
if (~PRESETn) IRQEN <= 1'h0;
else if (IRQEN_select) IRQEN <= PWDATA;
end
assign IRQ = (WDOV & IRQEN[0]);
assign PRDATA =
(PADDR[19:2] == 18'h0) ? WDTMR :
(PADDR[19:2] == 18'h1) ? WDLOAD :
(PADDR[19:2] == 18'h3) ? {31'd0,WDOV} :
(PADDR[19:2] == 18'h4) ? {31'd0,WDOVCLR} :
(PADDR[19:2] == 18'h5) ? {31'd0,WDEN} :
(PADDR[19:2] == 18'h40) ? {31'd0,IRQEN} :
32'hDEADBEEF;
endmodule
| 6.541544 |
module apb_wrtsetclr (
// system
input reset_n,
input enable, // clock gating
// APB
input pclk,
input [ 2:0] paddr, // ls 2 bits are unused
input pwrite,
input psel,
input penable,
input [31:0] pwdata,
output reg [31:0] prdata,
output pready,
output pslverr,
// Interface
output reg [31:0] control32
);
wire apb_write = psel & penable & pwrite;
wire apb_read = psel & ~pwrite;
assign pready = 1'b1;
assign pslverr = 1'b0;
always @(posedge pclk or negedge reset_n) begin
if (!reset_n) begin
control32 <= 32'h0;
prdata <= 32'h0;
end // reset
else if (enable)
begin
if (apb_write) begin
case (paddr)
3'h0: control32 <= control32 | pwdata;
3'h4: control32 <= control32 & ~pwdata;
endcase
end // write
if (apb_read) begin
case (paddr)
3'h0: prdata <= control32;
3'h4: prdata <= control32;
endcase
end // read
else prdata <= 32'h0; // so we can OR all busses
end // clocked
end // always
endmodule
| 7.45127 |
module apb_wrtsetclr_test;
localparam CLK_PERIOD = 100;
// system
reg reset_n;
reg enable; // clock gating
// APB
wire pclk;
wire [15:0] paddr; // ls 2 bits are unused
wire pwrite;
wire psel;
wire penable;
wire [31:0] pwdata;
wire [31:0] prdata;
wire pready;
wire pslverr;
// Interface
wire [31:0] control32;
reg flag;
initial begin
// system
reset_n = 1'b0;
enable = 1'b1;
flag = 1'b0;
@(posedge pclk) #(CLK_PERIOD * 5);
reset_n = 1'b1;
#(CLK_PERIOD * 5);
// write set
apb_bus0.write(16'h0, 32'hAAAA5555);
apb_bus0.read(16'h0, 32'hAAAA5555);
apb_bus0.read(16'h4, 32'hAAAA5555);
// write Set some more
apb_bus0.write(16'h0, 32'h55550000);
apb_bus0.read(16'h0, 32'hFFFF5555);
apb_bus0.read(16'h4, 32'hFFFF5555);
// write clear
apb_bus0.write(16'h4, 32'h00005500);
apb_bus0.read(16'h0, 32'hFFFF0055);
apb_bus0.read(16'h4, 32'hFFFF0055);
apb_bus0.delay(3);
if (apb_bus0.errors == 0) $display("apb_wrtsetclr test passed");
else $display("apb_wrtsetclr test FAILED!");
#500 $stop;
end
apb_wrtsetclr apb_wrtsetclr_0 (
// system
.reset_n(reset_n),
.enable (enable), // clock gating
// APB
.pclk (pclk),
.paddr (paddr[2:0]), // ls 2 bits are unused
.pwrite (pwrite),
.psel (psel),
.penable(penable),
.pwdata (pwdata),
.prdata (prdata),
.pready (pready),
.pslverr(pslverr),
// Interface
.control32(control32)
);
apb_bus #(
.CLKPER(CLK_PERIOD)
) apb_bus0 (
// APB
.pclk (pclk),
.paddr (paddr), // ls 2 bits are unused
.pwrite (pwrite),
.psel (psel),
.penable(penable),
.pwdata (pwdata),
.prdata (prdata),
.pready (pready),
.pslverr(pslverr)
);
endmodule
| 7.45127 |
module apb_xactor #(
parameter ADDR_WIDTH = 32,
DATA_WIDTH = 32
) ( /*AUTOARG*/
// Outputs
psel,
penable,
paddr,
pwdata,
pwrite,
// Inputs
clk,
reset_n,
prdata,
pready,
pslverr
);
input clk;
input reset_n;
output reg psel;
output reg penable;
output reg [ADDR_WIDTH-1:0] paddr;
output reg [DATA_WIDTH-1:0] pwdata;
output reg pwrite;
input [DATA_WIDTH-1:0] prdata;
input pready;
input pslverr;
reg [7:0] bus_timer;
parameter BUS_TIMER_EXPIRATION = 100;
always @(posedge clk) begin
if (!reset_n) begin
bus_timer <= 0;
psel <= 0;
penable <= 0;
paddr <= 0;
pwdata <= 0;
pwrite <= 0;
end
end
task write;
input [63:0] addr;
input [31:0] data;
output reg response;
begin
psel <= 1;
penable <= 0;
pwrite <= 1;
paddr <= addr[31:0];
pwdata <= data[31:0];
@(posedge clk);
penable <= 1;
while ((!pready) && (bus_timer < BUS_TIMER_EXPIRATION)) begin
bus_timer <= bus_timer + 1;
@(posedge clk);
end
bus_timer <= 0;
psel <= 0;
penable <= 0;
pwrite <= 0;
paddr <= 0;
pwdata <= 0;
response <= (pslverr) | (bus_timer == BUS_TIMER_EXPIRATION);
@(posedge clk);
end
endtask // write
task read;
input [63:0] addr;
output reg [31:0] data;
output reg response;
begin
psel <= 1;
penable <= 0;
pwrite <= 0;
paddr <= addr[31:0];
@(posedge clk);
penable <= 1;
while ((!pready) && (bus_timer < BUS_TIMER_EXPIRATION)) begin
bus_timer <= bus_timer + 1;
@(posedge clk);
end
bus_timer <= 0;
psel <= 0;
penable <= 0;
pwrite <= 0;
paddr <= 0;
data <= prdata;
response <= (pslverr) | (bus_timer == BUS_TIMER_EXPIRATION);
@(posedge clk);
end
endtask
endmodule
| 8.215047 |
module apdtimer_all (
clk,
strobe_in,
delta_in,
reg_clk,
reg_addr,
reg_data,
reg_wr,
record_rdy,
record
);
input clk;
input [3:0] strobe_in;
input [3:0] delta_in;
input reg_clk;
input [15:0] reg_addr;
inout [31:0] reg_data;
input reg_wr;
output record_rdy;
output [46:0] record;
wire [ 3:0] strobe_chans;
wire [31:0] timer_reg;
register #(
.ADDR(8'h03)
) apdtimer_reg (
.reg_clk(reg_clk),
.reg_addr(reg_addr),
.reg_data(reg_data),
.reg_wr(reg_wr),
.clk(clk),
.value(timer_reg)
);
wire capture_operate = timer_reg[0];
wire counter_operate = timer_reg[1];
wire reset_counter = timer_reg[2];
wire [31:0] strobe_operate;
register #(
.ADDR(8'h04)
) strobe_operate_reg (
.reg_clk(reg_clk),
.reg_addr(reg_addr),
.reg_data(reg_data),
.reg_wr(reg_wr),
.clk(clk),
.value(strobe_operate)
);
wire [31:0] delta_operate;
register #(
.ADDR(8'h05)
) delta_operate_reg (
.reg_clk(reg_clk),
.reg_addr(reg_addr),
.reg_data(reg_data),
.reg_wr(reg_wr),
.clk(clk),
.value(delta_operate)
);
event_tagger tagger (
.clk(clk),
.reset_counter(reset_counter),
.capture_operate(capture_operate),
.counter_operate(counter_operate),
.strobe_channels(strobe_chans & strobe_operate[3:0]),
.delta_channels(delta_in & delta_operate[3:0]),
.ready(record_rdy),
.data(record)
);
strobe_latch latch0 (
.clk(clk),
.in (strobe_in[0]),
.out(strobe_chans[0])
);
strobe_latch latch1 (
.clk(clk),
.in (strobe_in[1]),
.out(strobe_chans[1])
);
strobe_latch latch2 (
.clk(clk),
.in (strobe_in[2]),
.out(strobe_chans[2])
);
strobe_latch latch3 (
.clk(clk),
.in (strobe_in[3]),
.out(strobe_chans[3])
);
endmodule
| 6.930687 |
module APE_encode150_tabbFp_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 10;
parameter AWIDTH = 6;
parameter MEM_SIZE = 33;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 6.529176 |
module APE_encode150_tabbFp (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd10;
parameter AddressRange = 32'd33;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
APE_encode150_tabbFp_ram APE_encode150_tabbFp_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.q1(q1)
);
endmodule
| 6.529176 |
module apll_0002 (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("1.791044 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0.895522 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst(rst),
.outclk({outclk_1, outclk_0}),
.locked(locked),
.fboutclk(),
.fbclk(1'b0),
.refclk(refclk)
);
endmodule
| 6.705623 |
module appcontrol (
input clk,
input rst,
input [9:0] mouse_x,
input [9:0] mouse_y,
input yes,
output reg machine_en,
output reg machine_reset,
input sound,
input sound_en
);
parameter stop = 4'd0;
parameter start = 4'd1;
parameter reset = 4'd2;
reg [3:0] state;
always @(posedge clk or posedge rst) begin
if (rst) begin
state <= reset;
end else begin
case (state)
reset: begin
machine_reset <= 1;
machine_en <= 0;
state <= stop;
end
stop: begin
machine_reset <= 0;
machine_en <= 0;
if (yes && mouse_y >= 160 && mouse_y <= 200 && mouse_x >= 550 && mouse_x <= 590)
state <= reset;
else if (yes && mouse_y >= 160 && mouse_y <= 200 && mouse_x >= 505 && mouse_x <= 545)
state <= start;
else state <= stop;
end
start: begin
machine_en <= 1;
if (yes && mouse_y >= 160 && mouse_y <= 200 && mouse_x >= 550 && mouse_x <= 590)
state <= reset;
else if((yes&&mouse_y>=160&&mouse_y<=200&&mouse_x>=595&&mouse_x<=635)||(sound_en&&~sound))
state <= stop;
else state <= start;
end
endcase
end
end
endmodule
| 6.753611 |
module for Terasic DE0 board
//
// Author.....: Niels A. Moseley
// Date.......: 26-1-2018
//
module apple1_de0_top #(
parameter BASIC_FILENAME = "../../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../../../roms/ram.hex",
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
) (
input CLOCK_50, // the 50 MHz DE0 master clock
// UART I/O signals
output UART_TXD, // UART transmit pin on DE0 board
input UART_RXD, // UART receive pin on DE0 board
output UART_CTS, // UART clear-to-send pin on DE0 board
output [7:0] LEDG, // monitoring for lower 8 address bits
input [2:0] BUTTON, // BUTTON[0] for reset
output [6:0] HEX0_D,
output [6:0] HEX1_D,
output [6:0] HEX2_D,
output [6:0] HEX3_D,
input PS2_KBCLK,
input PS2_KBDAT,
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B,
output VGA_HS,
output VGA_VS
);
//////////////////////////////////////////////////////////////////////////
// Registers and Wires
reg clk25;
wire [15:0] pc_monitor;
// generate 25MHz clock from 50MHz master clock
always @(posedge CLOCK_50)
begin
clk25 <= ~clk25;
end
wire r_bit, g_bit, b_bit;
//////////////////////////////////////////////////////////////////////////
// Core of system
apple1 #(
.BASIC_FILENAME (BASIC_FILENAME),
.FONT_ROM_FILENAME (FONT_ROM_FILENAME),
.RAM_FILENAME (RAM_FILENAME),
.VRAM_FILENAME (VRAM_FILENAME),
.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
) apple1_top(
.clk25(clk25),
.rst_n(BUTTON[0]), // we don't have any reset pulse..
.uart_rx(UART_RXD),
.uart_tx(UART_TXD),
.uart_cts(UART_CTS),
.ps2_clk(PS2_KBCLK),
.ps2_din(PS2_KBDAT),
.ps2_select(1'b1),
.vga_h_sync(VGA_HS),
.vga_v_sync(VGA_VS),
.vga_red(r_bit),
.vga_grn(g_bit),
.vga_blu(b_bit),
.pc_monitor(pc_monitor)
);
// set the monochrome base colour here..
assign VGA_R[3:0] = {4{r_bit}};
assign VGA_G[3:0] = {4{g_bit}};
assign VGA_B[3:0] = {4{b_bit}};
//////////////////////////////////////////////////////////////////////////
// Display 6502 address on 7-segment displays
segmentdisplay seg1(
.clk(clk25),
.latch(1'b1),
.hexdigit_in(pc_monitor[3:0]),
.display_out(HEX0_D)
);
segmentdisplay seg2(
.clk(clk25),
.latch(1'b1),
.hexdigit_in(pc_monitor[7:4]),
.display_out(HEX1_D)
);
segmentdisplay seg3(
.clk(clk25),
.latch(1'b1),
.hexdigit_in(pc_monitor[11:8]),
.display_out(HEX2_D)
);
segmentdisplay seg4(
.clk(clk25),
.latch(1'b1),
.hexdigit_in(pc_monitor[15:12]),
.display_out(HEX3_D)
);
assign LEDG = 0;
endmodule
| 8.4806 |
module apple1_top #(
parameter BASIC_FILENAME = "../../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../../../roms/ram.hex",
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
) (
input pin3_clk_16mhz, // 16 MHz board clock
// Outputs to VGA display
output pin4, // hozizontal VGA sync pulse
output pin5, // vertical VGA sync pulse
input pin6, // PS/2 data input
input pin7, // PS/2 clock
// I/O interface to computer
input pin11, // asynchronous serial data input from computer
output pin12, // asynchronous serial data output to computer
output pin13, // clear to send flag to computer
output reg pin24, // red VGA signal
output reg pin23, // red VGA signal
output reg pin22, // green VGA signal
output reg pin21, // green VGA signal
output reg pin20, // blue VGA signal
output reg pin19 // blue VGA signal
);
wire clk25;
// 16MHz up to 25MHz
clock_pll clock_pll_inst (
.REFERENCECLK(pin3_clk_16mhz),
.PLLOUTGLOBAL(clk25),
.RESET(1'b1)
);
wire [15:0] pc_monitor;
reg [1:0] button = 2'b01;
wire vga_red;
wire vga_grn;
wire vga_blu;
// apple one main system
apple1 #(
.BASIC_FILENAME(BASIC_FILENAME),
.FONT_ROM_FILENAME(FONT_ROM_FILENAME),
.RAM_FILENAME(RAM_FILENAME),
.VRAM_FILENAME(VRAM_FILENAME),
.WOZMON_ROM_FILENAME(WOZMON_ROM_FILENAME)
) my_apple1 (
.clk25(clk25),
.rst_n(button[0]),
.ps2_clk(pin7), // PS/2 not working with my keyboard
.ps2_din(pin6),
.ps2_select(1'b0), // change to 1 in order to test with keyboard
.uart_rx(pin11),
.uart_tx(pin12),
.uart_cts(pin13),
.vga_h_sync(pin4),
.vga_v_sync(pin5),
.vga_red(vga_red),
.vga_grn(vga_grn),
.vga_blu(vga_blu),
.pc_monitor(pc_monitor)
);
assign pin19 = vga_blu;
assign pin20 = vga_blu;
assign pin21 = vga_grn;
assign pin22 = vga_grn;
assign pin23 = vga_red;
assign pin24 = vga_red;
endmodule
| 7.949466 |
module for Digilent Spartan 3E
// starter kit board
//
// Author.....: Niels A. Moseley
// Date.......: 11-2-2018
//
module apple1_s3e_starterkit_top #(
parameter BASIC_FILENAME = "../../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../../../roms/ram.hex",
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
) (
input CLK_50MHZ, // the 50 MHz master clock
// UART I/O signals
output UART_TXD, // UART transmit pin on board
input UART_RXD, // UART receive pin on board
input PS2_KBCLK,
input PS2_KBDAT,
input BUTTON, // Button for RESET
input SWITCH, // Switch between PS/2 input and UART
output VGA_R,
output VGA_G,
output VGA_B,
output VGA_HS,
output VGA_VS
);
//////////////////////////////////////////////////////////////////////////
// Registers and Wires
reg clk25;
wire [15:0] pc_monitor;
wire rst_n;
assign rst_n = ~BUTTON;
// generate 25MHz clock from 50MHz master clock
always @(posedge CLK_50MHZ)
begin
clk25 <= ~clk25;
end
//////////////////////////////////////////////////////////////////////////
// Core of system
apple1 #(
.BASIC_FILENAME (BASIC_FILENAME),
.FONT_ROM_FILENAME (FONT_ROM_FILENAME),
.RAM_FILENAME (RAM_FILENAME),
.VRAM_FILENAME (VRAM_FILENAME),
.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
) apple1_top(
.clk25(clk25),
.rst_n(rst_n), // we don't have any reset pulse..
.uart_rx(UART_RXD),
.uart_tx(UART_TXD),
//.uart_cts(UART_CTS), // there is no CTS on the board :(
.ps2_clk(PS2_KBCLK),
.ps2_din(PS2_KBDAT),
.ps2_select(SWITCH),
.vga_h_sync(VGA_HS),
.vga_v_sync(VGA_VS),
.vga_red(VGA_R),
.vga_grn(VGA_G),
.vga_blu(VGA_B),
.vga_cls(~rst_n),
.pc_monitor(pc_monitor)
);
endmodule
| 9.524504 |
module apple1_tb #(
parameter BASIC_FILENAME = "../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../roms/ram.hex",
parameter VRAM_FILENAME = "../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../roms/wozmon.hex"
);
reg clk25, uart_rx, rst_n;
wire uart_tx, uart_cts;
//////////////////////////////////////////////////////////////////////////
// Setup dumping of data for inspection
initial begin
clk25 = 1'b0;
uart_rx = 1'b1;
rst_n = 1'b0;
#40 rst_n = 1'b1;
$display("Starting...");
$dumpfile("apple1_top_tb.vcd");
$dumpvars;
#180000 uart_rx = 1'b0;
#400 uart_rx = 1'b1;
#400 uart_rx = 1'b0;
#400 uart_rx = 1'b1;
#800 uart_rx = 1'b0;
#1600 uart_rx = 1'b1;
#1000000 $display("Stopping...");
$finish;
end
//////////////////////////////////////////////////////////////////////////
// Clock
always #20 clk25 = !clk25;
//////////////////////////////////////////////////////////////////////////
// Core of system
apple1 #(
.BASIC_FILENAME(BASIC_FILENAME),
.FONT_ROM_FILENAME(FONT_ROM_FILENAME),
.RAM_FILENAME(RAM_FILENAME),
.VRAM_FILENAME(VRAM_FILENAME),
.WOZMON_ROM_FILENAME(WOZMON_ROM_FILENAME)
) core_top (
.clk25(clk25),
.rst_n(rst_n),
.uart_rx(uart_rx),
.uart_tx(uart_tx),
.uart_cts(uart_cts)
);
endmodule
| 7.544506 |
module apple1_top #(
parameter BASIC_FILENAME = "../../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../../../roms/ram.hex",
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
) (
// I/O interface to computer
input uart_rx, // asynchronous serial data input from computer
output uart_tx, // asynchronous serial data output to computer
output uart_cts, // clear to send flag to computer
// Outputs to VGA display
output vga_h_sync, // hozizontal VGA sync pulse
output vga_v_sync, // vertical VGA sync pulse
output reg vga_red, // red VGA signal
output reg vga_grn, // green VGA signal
output reg vga_blu, // blue VGA signal
// Tricolor LED on the UPDuino
output red_led,
output green_led,
output blue_led
);
wire [15:0] leds;
assign red_led = ~leds[9];
assign green_led = ~leds[8];
assign blue_led = ~leds[7];
wire clk25;
wire clk;
SB_HFOSC inthosc (
.CLKHFPU(1'b1),
.CLKHFEN(1'b1),
.CLKHF (clk)
);
pll pll (
.clock_in (clk),
.clock_out(clk25),
);
// apple one main system
apple1 #(
.BASIC_FILENAME(BASIC_FILENAME),
.FONT_ROM_FILENAME(FONT_ROM_FILENAME),
.RAM_FILENAME(RAM_FILENAME),
.VRAM_FILENAME(VRAM_FILENAME),
.WOZMON_ROM_FILENAME(WOZMON_ROM_FILENAME)
) my_apple1 (
.clk25(clk25),
.rst_n(1'b1),
.uart_rx(uart_rx),
.uart_tx(uart_tx),
.uart_cts(uart_cts),
.vga_h_sync(vga_h_sync),
.vga_v_sync(vga_v_sync),
.vga_red(vga_red),
.vga_grn(vga_grn),
.vga_blu(vga_blu),
.pc_monitor(leds),
.ps2_select(1'b0), // no ps2 keyboard right now
);
endmodule
| 7.949466 |
module applei_verilator #(
parameter BASIC_FILENAME = "../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../../roms/ram.hex",
parameter VRAM_FILENAME = "../../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../../roms/wozmon.hex"
);
reg clk /*verilator public_flat*/;
reg reset /*verilator public_flat*/;
reg ioctl_wait /*verilator public_flat*/;
reg ioctl_download /*verilator public_flat*/;
reg [7:0] ioctl_data /*verilator public_flat*/;
reg [15:0] ioctl_addr /*verilator public_flat*/;
wire [8:0] rgb;
wire csync, hsync, vsync, hblank, vblank;
wire [7:0] audio;
wire [3:0] led /*verilator public_flat*/;
reg [7:0] trakball /*verilator public_flat*/;
reg [7:0] joystick /*verilator public_flat*/;
reg [7:0] sw1 /*verilator public_flat*/;
reg [7:0] sw2 /*verilator public_flat*/;
reg [9:0] playerinput /*verilator public_flat*/;
wire r, g, b;
wire ps2_clk;
Clock_divider #(1000) cdiv (
clk,
ps2_clk
);
apple1 #(
.BASIC_FILENAME(BASIC_FILENAME),
.FONT_ROM_FILENAME(FONT_ROM_FILENAME),
.RAM_FILENAME(RAM_FILENAME),
.VRAM_FILENAME(VRAM_FILENAME),
.WOZMON_ROM_FILENAME(WOZMON_ROM_FILENAME)
) apple1 (
.clk25(clk),
.rst_n(~reset),
.uart_rx(),
.uart_tx(),
.uart_cts(),
.ps2_clk(ps2_clk),
.ps2_din(),
.ps2_select(1'b1),
.vga_h_sync(hsync),
.vga_v_sync(vsync),
.vga_red(r),
.vga_grn(g),
.vga_blu(b),
.vga_de(),
.vga_cls(),
.ioctl_download(ioctl_download),
.textinput_dout(ioctl_data),
.textinput_addr(ioctl_addr),
.pc_monitor()
);
`ifdef SDL_DISPLAY
import "DPI-C" function void dpi_vga_init(
input integer h,
input integer v
);
import "DPI-C" function void dpi_vga_display(
input integer vsync_,
input integer hsync_,
input integer pixel_
);
initial begin
dpi_vga_init(640, 480);
end
wire [31:0] pxd;
wire [31:0] hs;
wire [31:0] vs;
wire [ 2:0] vgaBlue;
wire [ 2:0] vgaGreen;
wire [ 2:0] vgaRed;
assign vgaBlue = rgb[8:6];
assign vgaGreen = rgb[5:3];
assign vgaRed = rgb[2:0];
//assign pxd = (hblank | vblank) ? 32'b0 : { 24'b0, vgaBlue, vgaGreen[2:1], vgaRed };
//assign pxd = (hblank | vblank) ? 32'b0 : { vgaRed,5'b0,vgaGreen,5'b0,vgaBlue,5'b0,8'b11111111 };
assign pxd = (hblank | vblank) ? 32'b0 : { 8'b11111111,{r,r,r},5'b0,{g,g,g},5'b0,{b,b,b},5'b0 };
//ARGB8888
assign vs = {31'b0, vsync};
assign hs = {31'b0, hsync};
always @(posedge clk) dpi_vga_display(vs, hs, pxd);
`endif
endmodule
| 8.204769 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.