code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module TopLevel (
ain[4:0],
bin[4:0],
cin[4:0],
extendeda[7:0],
extendedb[7:0],
extendedcin[7:0],
sumf[8:0],
coutf[8:0],
carrysaveoutput[8:0]
);
input [4:0] ain;
input [4:0] bin;
input [4:0] cin;
output [8:0] carrysaveoutput;
output [7:0] extendeda;
output [7:0] extendedb;
output [7:0] extendedcin;
output [8:0] sumf;
output [8:0] coutf;
/*reg [7:0] shifteda;
reg [7:0] shiftedb;
reg [7:0] shiftedcin;*/
assign extendeda[7:0] = {{3{ain[4]}}, ain[4:0]};
assign extendedb[7:0] = {{{3{bin[4]}}, bin[4:0]} << 2};
assign extendedcin[7:0] = {{{3{cin[4]}}, cin[4:0]} << 3};
carrysave_8 instantiate (
extendeda[7:0],
extendedb[7:0],
extendedcin[7:0],
sumf[8:0],
coutf[8:0],
carrysaveoutput[8:0]
);
endmodule
| 8.03714 |
module carrysave_8 (
a[7:0],
b[7:0],
c[7:0],
sum[8:0],
cout[8:0],
addition[8:0]
);
input [7:0] a;
input [7:0] b;
input [7:0] c;
output [8:0] sum;
output [8:0] cout;
output [8:0] addition;
FA FA0 (
a[0],
b[0],
c[0],
sum[0],
cout[0]
);
FA FA1 (
a[1],
b[1],
c[1],
sum[1],
cout[1]
);
FA FA2 (
a[2],
b[2],
c[2],
sum[2],
cout[2]
);
FA FA3 (
a[3],
b[3],
c[3],
sum[3],
cout[3]
);
FA FA4 (
a[4],
b[4],
c[4],
sum[4],
cout[4]
);
FA FA5 (
a[5],
b[5],
c[5],
sum[5],
cout[5]
);
FA FA6 (
a[6],
b[6],
c[6],
sum[6],
cout[6]
);
FA FA7 (
a[7],
b[7],
c[7],
sum[7],
cout[7]
);
assign sum[8] = 1'b0;
assign cout[8] = 1'b0;
assign addition[8:0] = sum[8:0] + {cout[8:0] << 1};
endmodule
| 7.576805 |
module HA (
in1,
in2,
sum,
carry
);
input in1, in2;
output sum, carry;
assign sum = in1 ^ in2;
assign carry = in1 & in2;
endmodule
| 8.480391 |
module TopLevel_testbench;
reg [4:0] ina;
reg [4:0] inb;
reg [4:0] inc;
wire [7:0] aextended;
wire [7:0] bextended;
wire [7:0] cinextended;
wire [8:0] fsum;
wire [8:0] fcout;
wire [8:0] outaddition;
TopLevel stage1 (
ina[4:0],
inb[4:0],
inc[4:0],
aextended[7:0],
bextended[7:0],
cinextended[7:0],
fsum[8:0],
fcout[8:0],
outaddition[8:0]
);
initial begin
$monitor($time, "ina = %b \t inb = %b \t inc = %b \t outsum = %b \n", ina[4:0], inb[4:0],
inc[4:0], outaddition[8:0]);
ina[4:0] = 11001;
#10;
inb[4:0] = 00001;
#10;
inc[4:0] = 10010;
/*#100;
ina[4:0] = 11001;
inb[4:0] = 00001;
inc[4:0] = 01010;
# 100;
ina[4:0] = 11111;
inb[4:0] = 11010;
inc[4:0] = 10000;
# 100;*/
end
endmodule
| 6.875707 |
module carrysave_4is2 (
input [4:0] in,
output c0,
output c1,
output sum
);
wire connection;
FullAdder FA0 (
in[0],
in[1],
in[2],
connection,
c0
);
FullAdder FA1 (
connection,
in[4],
in[3],
sum,
c1
);
endmodule
| 6.660827 |
module FullAdder (
input in1,
input in2,
input cin,
output sum,
output cout
);
assign sum = (in1 ^ in2) ^ cin;
assign cout = (in1 & in2) | (cin & (in1 ^ in2));
endmodule
| 7.610141 |
module carrysave_4is2_tb;
reg [4:0] in;
wire c0, c1, sum;
carrysave_4is2 carrysave_tb (
in[4:0],
c0,
c1,
sum
);
initial begin
$monitor($time, "input is %b \t c0 is %b \t c1 is %b \t sum is %b \n", in[4:0], c0, c1, sum);
#50;
in[4:0] = 10110;
#50 in[4:0] = 00000;
#50;
in[4:0] = 10001;
#50;
in[4:0] = 00101;
end
endmodule
| 6.660827 |
module stage1_3is2 (
input [5:0] in1,
input [5:0] in2,
input [5:0] in3,
output [5:0] cout_stage1,
output [5:0] sum_stage1
);
FullAdder FA2 (
in1[0],
in2[0],
in3[0],
sum_stage1[0],
cout_stage1[0]
);
FullAdder FA3 (
in1[1],
in2[1],
in3[1],
sum_stage1[1],
cout_stage1[1]
);
FullAdder FA4 (
in1[2],
in2[2],
in3[2],
sum_stage1[2],
cout_stage1[2]
);
FullAdder FA5 (
in1[3],
in2[3],
in3[3],
sum_stage1[3],
cout_stage1[3]
);
FullAdder FA12 (
in1[4],
in2[4],
in3[4],
sum_stage1[4],
cout_stage1[4]
);
FullAdder FA13 (
in1[5],
in2[5],
in3[5],
sum_stage1[5],
cout_stage1[5]
);
endmodule
| 7.405017 |
module stage2_3is2 (
input [5:0] in4,
input [5:0] in5,
input [5:0] in6,
output [5:0] cout_stage2,
output [5:0] sum_stage2
);
FullAdder FA6 (
in4[0],
in5[0],
in6[0],
sum_stage2[0],
cout_stage2[0]
);
FullAdder FA7 (
in4[1],
in5[1],
in6[1],
sum_stage2[1],
cout_stage2[1]
);
FullAdder FA8 (
in4[2],
in5[2],
in6[2],
sum_stage2[2],
cout_stage2[2]
);
FullAdder FA9 (
in4[3],
in5[3],
in6[3],
sum_stage2[3],
cout_stage2[3]
);
FullAdder FA22 (
in4[4],
in5[4],
in6[4],
sum_stage2[4],
cout_stage2[4]
);
FullAdder FA23 (
in4[5],
in5[5],
in6[5],
sum_stage2[5],
cout_stage2[5]
);
endmodule
| 6.971046 |
module stage3_4is2 (
input [5:0] subin1,
input [5:0] subin2,
input [5:0] subin3,
input [5:0] subin4,
output [5:0] sum_stage3,
output [5:0] cout_stage3
//output carry
);
wire connection1, connection2, connection3, connection4, connection5;
carrysave_4is2 CS1 (
({1'b0, 1'b0, subin3[0], 1'b0, subin1[0]}),
connection1,
cout_stage3[0],
sum_stage3[0]
);
carrysave_4is2 CS2 (
({connection1, subin4[0], subin3[1], subin2[0], subin1[1]}),
connection2,
cout_stage3[1],
sum_stage3[1]
);
carrysave_4is2 CS3 (
({connection2, subin4[1], subin3[2], subin2[1], subin1[2]}),
connection3,
cout_stage3[2],
sum_stage3[2]
);
carrysave_4is2 CS4 (
({connection3, subin4[2], subin3[3], subin2[2], subin1[3]}),
connection4,
cout_stage3[3],
sum_stage3[3]
);
carrysave_4is2 CS5 (
({connection4, subin4[3], subin3[4], subin2[3], subin1[4]}),
connection5,
cout_stage3[4],
sum_stage3[4]
);
carrysave_4is2 CS6 (
({connection5, subin4[4], subin3[5], subin2[4], subin1[5]})
,,,
sum_stage3[5]
);
endmodule
| 7.405799 |
module Top (
input [3:0] i1,
input [3:0] i2,
input [3:0] i3,
input [3:0] i4,
input [3:0] i5,
input [3:0] i6,
output [5:0] answer
);
wire [5:0] cout_S1;
wire [5:0] sum_S1;
wire [5:0] cout_S2;
wire [5:0] sum_S2;
wire [5:0] sum_S3;
wire [5:0] cout_S3;
//wire carry_S3;
stage1_3is2 S1 (
{i1[3], i1[3], i1[3:0]},
{i2[3], i2[3], i2[3:0]},
{i3[3], i3[3], i3[3:0]},
cout_S1[5:0],
sum_S1[5:0]
);
stage2_3is2 S2 (
{i4[3], i4[3], i4[3:0]},
{i5[3], i5[3], i5[3:0]},
{i6[3], i6[3], i6[3:0]},
cout_S2[5:0],
sum_S2[5:0]
);
stage3_4is2 S3 (
sum_S1[5:0],
({cout_S1[4:0], 1'b0}),
sum_S2[5:0],
({cout_S2[4:0], 1'b0}),
sum_S3[5:0],
cout_S3[5:0] /*,carry_S3*/
);
assign answer[5:0] = (sum_S3[5:0]) + ({cout_S3[4:0], 1'b0});
endmodule
| 6.64497 |
module carrysave_4is2 (
input [4:0] in,
output c0,
output c1,
output sum
);
wire connection;
FullAdder FA0 (
in[0],
in[1],
in[2],
connection,
c0
);
FullAdder FA1 (
connection,
in[4],
in[3],
sum,
c1
);
endmodule
| 6.660827 |
module FullAdder (
input in1,
input in2,
input cin,
output sum,
output cout
);
assign sum = (in1 ^ in2) ^ cin;
assign cout = (in1 & in2) | (cin & (in1 ^ in2));
endmodule
| 7.610141 |
module carrysave_4is2 (
input [4:0] in,
output c0,
output c1,
output sum
);
wire connection;
FullAdder FA0 (
in[0],
in[1],
in[2],
connection,
c0
);
FullAdder FA1 (
connection,
in[4],
in[3],
sum,
c1
);
endmodule
| 6.660827 |
module FullAdder (
input in1,
input in2,
input cin,
output sum,
output cout
);
assign sum = (in1 ^ in2) ^ cin;
assign cout = (in1 & in2) | (cin & (in1 ^ in2));
endmodule
| 7.610141 |
module TOP_testbench;
reg [10:0] inps;
wire [ 4:0] add;
Top instance1 (
inps[10:0],
add[4:0]
);
initial begin
$monitor($time, "inps = %b \t output = %b \n", inps[10:0], add[4:0]);
#10;
inps[10:0] = 11'b00000011111;
#50;
inps[10:0] = 11'b11000011111;
#50;
inps[10:0] = 11'b00110011011;
#50;
end
endmodule
| 6.517038 |
module abro (
input clk,
input reset,
input a,
input b,
output z
);
parameter IDLE = 0, SA = 1, SB = 2, SAB = 3;
reg [1:0] cur_state, next_state;
assign z = cur_state == SAB ? 1 : 0;
always @(posedge clk) begin
if (reset) cur_state <= IDLE;
else cur_state <= next_state;
end
always @(cur_state or a or b) begin
case (cur_state)
IDLE: begin
if (a && !b) next_state = SA;
else if (!a && b) next_state = SB;
else if (a && b) next_state = SAB;
else next_state = IDLE;
end
SA: begin
if (b) next_state = SAB;
else next_state = SA;
end
SB: begin
if (a) next_state = SAB;
else next_state = SB;
end
SAB: begin
next_state = IDLE;
end
endcase
end
endmodule
| 7.130853 |
module advshift (
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q
);
always @(posedge clk) begin
if (load) begin
q <= data;
end else if (ena) begin
case (amount)
0: q <= {q[62:0], 1'b0};
1: q <= {q[55:0], 8'b0};
2: q <= {1'b0, q[63:1]};
3: q <= {8'b0, q[63:8]};
endcase
end
end
endmodule
| 7.037838 |
module that implements an AND gate
module and_gate(
input a,
input b,
output out );
assign out = a && b;
endmodule
| 8.896332 |
module half_adder (
input a,
b,
output cout,
sum
);
assign sum = a ^ b;
assign cout = a & b;
endmodule
| 6.966406 |
module lfsr (
input clk,
input reset,
output [4:0] q
);
reg [4:0] r_reg;
wire [4:0] r_next;
wire feedback_value;
always @(posedge clk, posedge reset) begin
if (reset) begin
// set initial value to 1
r_reg <= 1;
end else if (clk == 1'b1) r_reg <= r_next;
end
assign feedback_value = r_reg[4] ^ r_reg[2] ^ r_reg[0];
assign r_next = {feedback_value, r_reg[4:1]};
assign q = r_reg;
endmodule
| 6.570207 |
module MODULENAME (
parameter WIDTH = 5
)(
input clk,
input rst_n,
input butten,
input trigger,
input [WIDTH-1 : 0] others,
output red,
output yellow,
output green,
output out_butten
)
always @(posedge clk or negedge rst_n) begin
if(rst_n) cnt <= 10'd0;
else if(rst_cnt)
cnt <= 10'd0;
else if(cnt == 10'd1000)
cnt <= cnt;
else if(trigger)
cnt <= cnt + 1'b1;
end
localparam IDLE = 3'd0;
localparam s_yellow = 3'd1;
localparam s_green = 3'd2;
localparam s_red = 3'd3;
localparam s_0 = 3'd4;
reg [2:0] cur_state;
reg [2:0] nxt_state;
always @(posedge clk or negedge rst_n) begin
if(rst_n) cur_state <= IDLE;
else cur_state <= nxt_state;
end
always @(*) begin
case(cur_state)
IDLE: nxt_state = s0;
s0: begin
if((cnt<10'd1000) && butten && (~|others))
nxt_state = s_green;
else if((cnt<10'd1000) && butten && (|others))
nxt_state = s_yellow;
else if(cnt==10'd1000)
nxt_state = s_red;
end
s_green : nxt_state = s_green;
s_red: nxt_state = s_red;
s_yellow: nxt_state = IDLE;
default: nxt_state = IDLE;
endcase
end
assign trigger = cur_state == s0;
assign rst_cnt = cur_state == s_yellow;
assign green = cur_state == s_green;
assign red = cur_state == s_red;
assign yellow = cur_state == s_yellow;
assign out_butten = butten && (cur_state != s_red);
endmodule
| 7.350224 |
module that implements an AND gate
module mux(
input [4:0] a, b,
input sel,
output [4:0] out );
assign out = sel?b:a;
endmodule
| 8.896332 |
module priority_encoder (
input [2:0] in,
output reg [1:0] pos
);
always @(*) begin
if (in[0] == 1'b1) pos = 0;
else if (in[1] == 1'b1) pos = 1;
else if (in[2] == 1'b1) pos = 2;
else pos = 0;
end
endmodule
| 7.114361 |
module
module ram #( parameter ADDR_WIDTH=6, parameter DATA_WIDTH=8)
(input [DATA_WIDTH-1:0] data, input [ADDR_WIDTH-1:0] addr, input we, clk, output [DATA_WIDTH-1:0] q);
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
// when we is high, write data to ram at address addr
// assign the ram value at address addr to q
always @ (posedge clk)
begin
if (we)
ram[addr] <= data;
end
assign q = ram[addr];
endmodule
| 7.233831 |
module left_rotate (
input clk,
input reset,
input [2:0] amount,
input [7:0] data,
input load,
output reg [7:0] out
);
// when load is high, load data to out
// shift left and rotate the register out by amount bits
always @(posedge clk) begin
if (load) out <= data;
else begin
case (amount)
0: out <= out;
1: out <= {out[6:0], out[7]};
2: out <= {out[5:0], out[7:6]};
3: out <= {out[4:0], out[7:5]};
4: out <= {out[3:0], out[7:4]};
5: out <= {out[2:0], out[7:3]};
6: out <= {out[1:0], out[7:2]};
7: out <= {out[0], out[7:1]};
endcase
end
end
endmodule
| 6.527094 |
module simple_fsm (
input clk,
input reset,
input in,
output out
);
reg present_state, next_state;
// In state 0, if in=1, stay in state 0. In state 0, if in=0, go to state 1
// In state 1, if in=1, stay in state 1. In state 1, if in=0, go to state 0
// out=1 in state 0 and out=0 in state 1
always @(posedge clk) begin
if (reset) begin
present_state <= 0;
end else begin
// State flip-flops
present_state <= next_state;
end
end
always @(present_state, in) begin
case (present_state)
// next state logic
0: begin
if (in) next_state <= 0;
else next_state <= 1;
end
1: begin
if (in) next_state <= 1;
else next_state <= 0;
end
endcase
end
// output logic
assign out = present_state ? 0 : 1;
endmodule
| 8.56957 |
module with one input and one output that behaves like a wire
module wire_assign( input in, output out );
// assign out to in
assign out = in;
endmodule
| 7.695416 |
module ANS_FIFO (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input aclr;
input [135:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [135:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [135:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [135:0] q = sub_wire0[135:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.aclr(aclr),
.data(data),
.rdclk(rdclk),
.rdreq(rdreq),
.wrclk(wrclk),
.wrreq(wrreq),
.q(sub_wire0),
.rdempty(sub_wire1),
.wrfull(sub_wire2),
.eccstatus(),
.rdfull(),
.rdusedw(),
.wrempty(),
.wrusedw()
);
defparam dcfifo_component.intended_device_family = "Cyclone 10 LP",
dcfifo_component.lpm_numwords = 256, dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 136,
dcfifo_component.lpm_widthu = 8, dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 3, dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF", dcfifo_component.wrsync_delaypipe = 3;
endmodule
| 6.630796 |
module ANS_MEM #(
parameter ID_WIDTH = 4,
ADDR_WIDTH = 32,
DATA_WIDTH = 16
);
parameter DRAM_p_r = "../00_TESTBED/DRAM/data_file.dat";
reg [7:0] DRAM_r[0:8*1024-1];
initial $readmemh(DRAM_p_r, DRAM_r);
endmodule
| 8.214137 |
module anti_bounce_reset (
input clk,
input button,
output reg stabilized_button
);
//CAREFULL
reg [19:0] clk_count=1'b0; //(Depending on the FPGA system used.) For 50mhz clock (period=2e-8) and for a 20ms delay, 20bits give the required 2^20cycles.
wire check; //ClockDividing using AND: When clk_hits 2^20 clock periods CHECK will give me a posedge////
reg reset_initialize = 1'b1;
reg saved_button_state;
reg [1:0] current_state;
always @(posedge clk) begin
clk_count <= clk_count + 1'b1;
end
assign check = &clk_count;
//ClockDividing using AND: When clk_hits 1048576 Cycles=(20b'1111111111111111111111) clock periods CHECK will give me a posedge
//if the clock of the FPGA is 10mhz then 1048576 cycles equal a worst case of a 4*0.1048576seconds delay,
//making it necessary to be pressing the button for that much time to make an effect
always @(posedge check, posedge reset_initialize) begin
if (reset_initialize) begin
current_state <= 2'b00;
saved_button_state <= 1'b0;
stabilized_button <= 1'b0;
reset_initialize <= 1'b0;
end else begin
case (current_state)
2'b00: //INITIAL STATE: CHECKING FOR CHANGE IN THE STATE OF THE BUTTON
if (button == ~saved_button_state) begin
current_state <= 2'b01; //progress_state
saved_button_state <= button;
end
2'b01:
if (button == ~saved_button_state) current_state <= 2'b00;
else begin
current_state <= 2'b10; //progress_state
saved_button_state <= button;
end
2'b10:
if (button == ~saved_button_state) current_state <= 2'b00;
else begin
current_state <= 2'b11; //progress_state
saved_button_state <= button;
end
2'b11:
if (button == ~saved_button_state) current_state <= 2'b00;
else begin
current_state <= 2'b00; //Reinitialize FSM
stabilized_button <= button; //PROGRESS THE RESULT IN THE OUTPUT
end
endcase
end
end
endmodule
| 6.519225 |
module antares_add (
input [31:0] a,
input [31:0] b,
output [31:0] c
);
assign c = a + b;
endmodule
| 7.424336 |
module antares_branch_unit (
input [ 5:0] opcode, // Instruction opcode
input [31:0] id_pc_add4, // Instruction address + 4
input [31:0] id_data_rs, // Data from R0
input [31:0] id_data_rt, // Data from R1
input [25:0] op_imm26, // imm21/Imm16
output reg [31:0] pc_branch_address, // Destination address
output reg id_take_branch // Valid branch
);
//--------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
wire beq;
wire bne;
wire bgez;
wire bgtz;
wire blez;
wire bltz;
wire [31:0] long_jump;
wire [31:0] short_jump;
wire [ 5:0] inst_function;
wire [ 4:0] op_rt;
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign beq = id_data_rs == id_data_rt;
assign bne = ~beq;
assign bgez = ~bltz;
assign bgtz = ~blez;
assign blez = bltz | ~(|id_data_rs);
assign bltz = id_data_rs[31];
assign long_jump = {id_pc_add4[31:28], op_imm26, 2'b00};
assign short_jump = $signed(
id_pc_add4
) + $signed(
{{14{op_imm26[15]}}, op_imm26[`ANTARES_INSTR_IMM16], 2'b00}
);
assign inst_function = op_imm26[`ANTARES_INSTR_FUNCT];
assign op_rt = op_imm26[`ANTARES_INSTR_RT];
//--------------------------------------------------------------------------
// Get branch address
//--------------------------------------------------------------------------
always @(*) begin
case (opcode)
`OP_BEQ: begin
pc_branch_address = short_jump;
id_take_branch = beq;
end
`OP_BGTZ: begin
pc_branch_address = short_jump;
id_take_branch = bgtz;
end
`OP_BLEZ: begin
pc_branch_address = short_jump;
id_take_branch = blez;
end
`OP_BNE: begin
pc_branch_address = short_jump;
id_take_branch = bne;
end
`OP_J: begin
pc_branch_address = long_jump;
id_take_branch = 1'b1;
end
`OP_JAL: begin
pc_branch_address = long_jump;
id_take_branch = 1'b1;
end
`OP_TYPE_REGIMM: begin
case (op_rt)
`RT_OP_BGEZ: begin
pc_branch_address = short_jump;
id_take_branch = bgez;
end
`RT_OP_BGEZAL: begin
pc_branch_address = short_jump;
id_take_branch = bgez;
end
`RT_OP_BLTZ: begin
pc_branch_address = short_jump;
id_take_branch = bltz;
end
`RT_OP_BLTZAL: begin
pc_branch_address = short_jump;
id_take_branch = bltz;
end
default: begin
pc_branch_address = 32'bx;
id_take_branch = 1'b0;
end
endcase // case (op_rt)
end
`OP_TYPE_R: begin
case (inst_function)
`FUNCTION_OP_JALR: begin
pc_branch_address = id_data_rs;
id_take_branch = 1'b1;
end
`FUNCTION_OP_JR: begin
pc_branch_address = id_data_rs;
id_take_branch = 1'b1;
end
default: begin
pc_branch_address = 32'bx;
id_take_branch = 1'b0;
end
endcase // case (inst_function)
end
default: begin
pc_branch_address = 32'bx;
id_take_branch = 1'b0;
end
endcase // case (opcode)
end // always @ (*)
endmodule
| 7.549423 |
module antares_divider (
input clk,
input rst,
input op_divs,
input op_divu,
input [31:0] dividend,
input [31:0] divisor,
output [31:0] quotient,
output [31:0] remainder,
output div_stall
);
//--------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg active; // 1 while running
reg neg_result; // 1 if the result must be negative
reg neg_remainder; // 1 if the remainder must be negative
reg [ 4:0] cycle; // number of cycles needed.
reg [31:0] result; // Store the result.
reg [31:0] denominator; // divisor
reg [31:0] residual; // current remainder
//--------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
wire [32:0] partial_sub; // temp
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign quotient = !neg_result ? result : -result;
assign remainder = !neg_remainder ? residual : -residual;
assign div_stall = active;
assign partial_sub = {residual[30:0], result[31]} - denominator; // calculate partial result
//--------------------------------------------------------------------------
// State Machine. This needs 32 cycles to calculate the result.
// The result is loaded after 34 cycles
// The first cycle is setup.
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
active <= 1'h0;
cycle <= 5'h0;
denominator <= 32'h0;
neg_result <= 1'h0;
neg_remainder <= 1'h0;
residual <= 32'h0;
result <= 32'h0;
// End of automatics
end else begin
if (op_divs) begin
// Signed division.
cycle <= 5'd31;
result <= (dividend[31] == 1'b0) ? dividend : -dividend;
denominator <= (divisor[31] == 1'b0) ? divisor : -divisor;
residual <= 32'b0;
neg_result <= dividend[31] ^ divisor[31];
neg_remainder <= dividend[31];
active <= 1'b1;
end else if (op_divu) begin
// Unsigned division.
cycle <= 5'd31;
result <= dividend;
denominator <= divisor;
residual <= 32'b0;
neg_result <= 1'b0;
neg_remainder <= 1'h0;
active <= 1'b1;
end else if (active) begin
// run a iteration
if (partial_sub[32] == 1'b0) begin
residual <= partial_sub[31:0];
result <= {result[30:0], 1'b1};
end else begin
residual <= {residual[30:0], result[31]};
result <= {result[30:0], 1'b0};
end
if (cycle == 5'b0) begin
active <= 1'b0;
end
cycle <= cycle - 5'd1;
end
end
end
endmodule
| 6.657417 |
module antares_memwb_register (
input clk, // main clock
input rst, // main reset
input [31:0] mem_read_data, // data from Memory
input [31:0] mem_alu_data, // data from ALU
input [ 4:0] mem_gpr_wa, // GPR write enable
input mem_mem_to_gpr_select, // select MEM/ALU to GPR
input mem_gpr_we, // GPR write enable
input mem_flush,
input mem_stall, // stall MEM stage
input wb_stall, // stall WB stage
output reg [31:0] wb_read_data, // data from Memory
output reg [31:0] wb_alu_data, // data from ALU
output reg [ 4:0] wb_gpr_wa, // GPR write address
output reg wb_mem_to_gpr_select, // select MEM/ALU to GPR
output reg wb_gpr_we // GPR write enable
);
//--------------------------------------------------------------------------
// Propagate signals
//--------------------------------------------------------------------------
always @(posedge clk) begin
wb_read_data <= (rst) ? 32'b0 : ((wb_stall) ? wb_read_data : mem_read_data);
wb_alu_data <= (rst) ? 32'b0 : ((wb_stall) ? wb_alu_data : mem_alu_data);
wb_gpr_wa <= (rst) ? 5'b0 : ((wb_stall) ? wb_gpr_wa : mem_gpr_wa);
wb_mem_to_gpr_select <= (rst) ? 1'b0 : ((wb_stall) ? wb_mem_to_gpr_select : mem_mem_to_gpr_select);
wb_gpr_we <= (rst) ? 1'b0 : ((wb_stall) ? wb_gpr_we : ((mem_stall | mem_flush) ? 1'b0 : mem_gpr_we));
end
endmodule
| 7.414291 |
module antares_mux_2_1 #(
parameter WIDTH = 32
) (
input [WIDTH-1:0] in0,
input [WIDTH-1:0] in1,
input select,
output reg [WIDTH-1:0] out
);
always @( /*AUTOSENSE*/ in0 or in1 or select) begin
case (select)
1'b0: out = in0;
1'b1: out = in1;
endcase // case (select)
end // always @ (...
endmodule
| 7.671781 |
module antares_mux_4_1 #(
parameter WIDTH = 32
) (
input [ 1:0] select,
input [WIDTH-1:0] in0,
input [WIDTH-1:0] in1,
input [WIDTH-1:0] in2,
input [WIDTH-1:0] in3,
output reg [WIDTH-1:0] out
);
always @( /*AUTOSENSE*/ in0 or in1 or in2 or in3 or select) begin
case (select)
2'b00: out = in0;
2'b01: out = in1;
2'b10: out = in2;
2'b11: out = in3;
endcase // case (select)
end // always @ (...
endmodule
| 7.530474 |
module antares_pc_register (
input clk,
input rst,
input [31:0] if_new_pc,
input if_stall,
output reg [31:0] if_pc
);
always @(posedge clk) begin
if_pc <= (rst) ? `ANTARES_VECTOR_BASE_RESET : ((if_stall) ? if_pc : if_new_pc);
end
endmodule
| 6.544672 |
module antares_reg_file (
input clk,
input [ 4:0] gpr_ra_a,
input [ 4:0] gpr_ra_b,
input [ 4:0] gpr_wa,
input [31:0] gpr_wd,
input gpr_we,
output [31:0] gpr_rd_a,
output [31:0] gpr_rd_b
);
// Register file of 32 32-bit registers. Register 0 is always 0
reg [31:0] registers[1:31];
// Clocked write
always @(posedge clk) begin
if (gpr_wa != 5'b0) registers[gpr_wa] <= (gpr_we) ? gpr_wd : registers[gpr_wa];
end
// Combinatorial read (no delay). Register 0 is read as 0 always.
assign gpr_rd_a = (gpr_ra_a == 5'b0) ? 32'b0 : registers[gpr_ra_a];
assign gpr_rd_b = (gpr_ra_b == 5'b0) ? 32'b0 : registers[gpr_ra_b];
endmodule
| 7.638787 |
module anti_bounce (
input clk,
input reset,
input button,
output reg stabilized_button
);
//carefull
reg [19:0] clk_count=1'b0; //(Depending on the FPGA system used.) For 50mhz clock (period=2e-8) and for a 20ms delay, 20bits give the required 2^20cycles.
wire check; ////ClockDividing using AND: When clk_hits 2^20 clock periods CHECK will give me a posedge
reg saved_button_state;
reg [1:0] current_state;
always @(posedge clk) begin
clk_count <= clk_count + 1'b1;
end
assign check = &clk_count;
//ClockDividing using AND: When clk_hits 1048576 Cycles=(20b'1111111111111111111111) clock periods CHECK will give me a posedge
//if the clock of the FPGA is 10mhz then 1048576 cycles equal a worst case of a 4*0.1048576seconds delay,
//making it necessary to be pressing the button for that much time to make an effect//////
always @(posedge check, posedge reset) begin
if (reset) begin
current_state <= 2'b00;
saved_button_state <= button;
stabilized_button<=1'b0; //A different module is utilized for Buttons than the Reset button
//itself in order for the system to regain partial functionality in the a case of a shortcircuited o
//r stuck button, the anti_bounce module will effectively nulify the malfunctioning button's effect when the reset button is pressed.
end else begin
case (current_state)
2'b00: //INITIAL STATE: CHECKING FOR CHANGE IN THE STATE OF THE BUTTON
if (button == ~saved_button_state) begin
current_state <= 2'b01; //progress_state
saved_button_state <= button;
end
2'b01:
if (button == ~saved_button_state) current_state <= 2'b00;
else begin
current_state <= 2'b10; //progress_state
saved_button_state <= button;
end
2'b10:
if (button == ~saved_button_state) current_state <= 2'b00;
else begin
current_state <= 2'b11; //progress_state
saved_button_state <= button;
end
2'b11:
if (button == ~saved_button_state) current_state <= 2'b00;
else begin
current_state <= 2'b00; //Reinitialize FSM
stabilized_button <= button; //PROGRESS THE RESULT IN THE OUTPUT
end
endcase
end
end
endmodule
| 6.764266 |
module adder_block #(
parameter block_width = 4
) (
input wire [block_width-1 : 0] a,
b,
wire cin,
output wire [block_width-1 : 0] sum,
wire cout
);
wire [block_width : 0] c;
wire [block_width-1 : 0] p, g, g_all;
wire p_all;
assign c[0] = cin;
assign p = a ^ b;
assign g = a & b;
assign p_all = &p;
assign g_all[0] = g[0];
assign g_all[block_width-1 : 1] = (p[block_width-1 : 1] & g_all[block_width-2 : 0]) | g[block_width-1 : 1];
assign cout = (cin & p_all) | g_all[block_width-1];
genvar i;
generate
for (i = 0; i < block_width; i = i + 1) begin : full_adders
full_adder fa (
.a(a[i]),
.b(b[i]),
.cin(c[i]),
.sum(sum[i]),
.cout(c[i+1])
);
end
endgenerate
endmodule
| 9.11153 |
module anticipated_carry_adder #(
parameter block_width = 4,
parameter width = 32
) (
input wire [width-1 : 0] a,
b,
wire cin,
output wire [width-1 : 0] sum,
wire cout
);
localparam block_num = width / block_width;
wire [block_num : 0] c;
assign c[0] = cin;
assign cout = c[block_num];
genvar i;
generate
for (i = 0; i < block_num; i = i + 1) begin : adder_blocks
adder_block #(
.block_width(block_width)
) ab (
.a(a[(i+1)*block_width-1 : i*block_width]),
.b(b[(i+1)*block_width-1 : i*block_width]),
.cin(c[i]),
.sum(sum[(i+1)*block_width-1 : i*block_width]),
.cout(c[i+1])
);
end
endgenerate
endmodule
| 8.775118 |
module AntiJitter #(
parameter WIDTH = 20,
parameter INIT = 1'b0
) (
input clk,
input I,
output reg O = INIT
);
reg [WIDTH-1:0] cnt = {WIDTH{INIT}};
always @(posedge clk) begin
if (I) begin
if (&cnt) O <= 1'b1;
else cnt <= cnt + 1'b1;
end else begin
if (|cnt) cnt <= cnt - 1'b1;
else O <= 1'b0;
end
end
endmodule
| 7.202376 |
module AntiLog2
/*
A fast base-2 anti-logarithm function, 10 bits in, 24 bits out.
Designed and coded by: Michael Dunn, http://www.cantares.on.ca/
Executes every cycle, with a latency of 2.
The input and output have binary points: In: xxxx.yyyy_yy; Out: xxxx_xxxx_xxxx_xxxx.yyyy_yyyy
License: Free to use & modify, but please keep this header intact.
August 8, 2010, Kitchener, Ontario, Canada
*/
(
input [9:0] DIN,
input clk,
output reg [23:0] DOUT
);
// Comprises 2 main blocks: barrel shifter & LUT
reg [ 3:0] barrelshfcnt;
reg [22:0] LUTout;
wire [38:0] tmp1 = ({1'b1, LUTout} << barrelshfcnt);
always @(posedge clk) begin
barrelshfcnt <= DIN[9:6];
DOUT <= tmp1[38:15];
end
//LUT for one octave of antilog lookup
// The equation is: output = (2^(input/64)-1) * 2^23
// For larger tables, better to generate a separate data file using a program!
always @(posedge clk)
case (DIN[5:0])
0: LUTout <= 0;
1: LUTout <= 91346;
2: LUTout <= 183687;
3: LUTout <= 277033;
4: LUTout <= 371395;
5: LUTout <= 466786;
6: LUTout <= 563215;
7: LUTout <= 660693;
8: LUTout <= 759234;
9: LUTout <= 858847;
10: LUTout <= 959546;
11: LUTout <= 1061340;
12: LUTout <= 1164243;
13: LUTout <= 1268267;
14: LUTout <= 1373424;
15: LUTout <= 1479725;
16: LUTout <= 1587184;
17: LUTout <= 1695814;
18: LUTout <= 1805626;
19: LUTout <= 1916634;
20: LUTout <= 2028850;
21: LUTout <= 2142289;
22: LUTout <= 2256963;
23: LUTout <= 2372886;
24: LUTout <= 2490071;
25: LUTout <= 2608532;
26: LUTout <= 2728283;
27: LUTout <= 2849338;
28: LUTout <= 2971711;
29: LUTout <= 3095417;
30: LUTout <= 3220470;
31: LUTout <= 3346884;
32: LUTout <= 3474675;
33: LUTout <= 3603858;
34: LUTout <= 3734447;
35: LUTout <= 3866459;
36: LUTout <= 3999908;
37: LUTout <= 4134810;
38: LUTout <= 4271181;
39: LUTout <= 4409037;
40: LUTout <= 4548394;
41: LUTout <= 4689269;
42: LUTout <= 4831678;
43: LUTout <= 4975637;
44: LUTout <= 5121164;
45: LUTout <= 5268276;
46: LUTout <= 5416990;
47: LUTout <= 5567323;
48: LUTout <= 5719293;
49: LUTout <= 5872918;
50: LUTout <= 6028216;
51: LUTout <= 6185205;
52: LUTout <= 6343903;
53: LUTout <= 6504329;
54: LUTout <= 6666503;
55: LUTout <= 6830442;
56: LUTout <= 6996167;
57: LUTout <= 7163696;
58: LUTout <= 7333050;
59: LUTout <= 7504247;
60: LUTout <= 7677309;
61: LUTout <= 7852255;
62: LUTout <= 8029107;
63: LUTout <= 8207884;
endcase
endmodule
| 6.558796 |
module: AntiTheftModule
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module AntiTheftTest;
// Inputs
reg clock;
reg reset;
reg ignition;
reg driver_door;
reg passenger_door;
reg reprogram;
reg timer_expired;
// Outputs
wire [1:0] timer_interval;
wire siren_on;
wire status_indicator;
wire start_timer;
// Instantiate the Unit Under Test (UUT)
AntiTheftModule uut (
.clock(clock),
.reset(reset),
.ignition(ignition),
.driver_door(driver_door),
.passenger_door(passenger_door),
.reprogram(reprogram),
.timer_expired(timer_expired),
.timer_interval(timer_interval),
.siren_on(siren_on),
.status_indicator(status_indicator),
.start_timer(start_timer)
);
always #5 clock = !clock;
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
ignition = 0;
driver_door = 0;
passenger_door = 0;
reprogram = 0;
timer_expired = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 1;
#10
reset = 0;
#10
//test that state machine goes into armed state
ignition = 0;
driver_door = 0;
passenger_door = 0;
#30
//test that state machine goes into disarmed state
ignition = 1;
#30
//turn off car
ignition = 0;
#20
///should go to second disarmed state, wait for door to open
driver_door = 1;
#20
//should go to third disarmed state, wait T_ARM_DELAY
driver_door = 0;
#50
//goes back to armed state
timer_expired = 1;
#30
//go to triggered state
timer_expired = 0;
driver_door = 1;
#30
//timer expires ---> go to sounding state
timer_expired = 1;
#30
timer_expired = 0;
driver_door = 0;
passenger_door = 0;
#30
timer_expired = 1;
#30
timer_expired = 0;
passenger_door =1;
#30
timer_expired = 1;
#30
timer_expired = 0;
driver_door = 0;
passenger_door = 0;
#30
$stop();
end
endmodule
| 7.121774 |
module anti_jitter (
input wire clk, // main clock
input wire rst, // synchronous reset
input wire sig_i, // input signal with jitter noises
output reg sig_o = INIT_VALUE // output signal without jitter noises
);
`include "function.vh"
parameter CLK_FREQ = 100, // main clock frequency in MHz
JITTER_MAX = 10000; // longest time for jitter noises in us
parameter INIT_VALUE = 0; // initialized output value
localparam CLK_COUNT = CLK_FREQ * JITTER_MAX, // CLK_FREQ * 1000000 / (1000000 / JITTER_MAX)
CLK_COUNT_WIDTH = GET_WIDTH(
CLK_COUNT - 1
);
reg [CLK_COUNT_WIDTH-1:0] clk_count = 0;
always @(posedge clk) begin
if (rst) begin
clk_count <= 0;
sig_o <= INIT_VALUE;
end else if (sig_i == sig_o) begin
clk_count <= 0;
end else if (clk_count == CLK_COUNT - 1) begin
clk_count <= 0;
sig_o <= sig_i;
end else begin
clk_count <= clk_count + 1'h1;
end
end
endmodule
| 7.883053 |
module anti_jitter_combined (
input clk,
input [15:0] sw,
input [3:0] btn_y,
output [15:0] switch_buf,
output [3:0] btn_y_buf
);
localparam
CLK_FREQ_SYS = 50,
CLK_FREQ_BUS = 25,
CLK_FREQ_CPU = 50,
CLK_FREQ_MEM = 50,
CLK_FREQ_DEV = 50;
`ifndef SIMULATING
anti_jitter #(
.CLK_FREQ (CLK_FREQ_DEV),
.JITTER_MAX(1000),
.INIT_VALUE(0)
)
AJ0 (
.clk (clk_out),
.rst (1'b0),
.sig_i(sw[0]),
.sig_o(switch_buf[0])
),
AJ1 (
.clk (clk_out),
.rst (1'b0),
.sig_i(sw[1]),
.sig_o(switch_buf[1])
),
AJ2 (
.clk (clk_out),
.rst (1'b0),
.sig_i(sw[2]),
.sig_o(switch_buf[2])
),
AJ3 (
.clk (clk_out),
.rst (1'b0),
.sig_i(sw[3]),
.sig_o(switch_buf[3])
),
AJ4 (
.clk (clk_out),
.rst (1'b0),
.sig_i(sw[4]),
.sig_o(switch_buf[4])
),
AJ5 (
.clk (clk_out),
.rst (1'b0),
.sig_i(sw[5]),
.sig_o(switch_buf[5])
),
AJ6 (
.clk (clk_out),
.rst (1'b0),
.sig_i(sw[6]),
.sig_o(switch_buf[6])
),
AJ7 (
.clk (clk_out),
.rst (1'b0),
.sig_i(sw[7]),
.sig_o(switch_buf[7])
),
AJ8 (
.clk (clk_out),
.rst (1'b0),
.sig_i(sw[8]),
.sig_o(switch_buf[8])
),
AJ9 (
.clk (clk_out),
.rst (1'b0),
.sig_i(sw[9]),
.sig_o(switch_buf[9])
),
AJ10 (
.clk (clk_out),
.rst (1'b0),
.sig_i(sw[10]),
.sig_o(switch_buf[10])
),
AJ11 (
.clk (clk_out),
.rst (1'b0),
.sig_i(sw[11]),
.sig_o(switch_buf[11])
),
AJ12 (
.clk (clk_out),
.rst (1'b0),
.sig_i(sw[12]),
.sig_o(switch_buf[12])
),
AJ13 (
.clk (clk_out),
.rst (1'b0),
.sig_i(sw[13]),
.sig_o(switch_buf[13])
),
AJ14 (
.clk (clk_out),
.rst (1'b0),
.sig_i(sw[14]),
.sig_o(switch_buf[14])
),
AJ15 (
.clk (clk_out),
.rst (1'b0),
.sig_i(sw[15]),
.sig_o(switch_buf[15])
),
AJY0 (
.clk (clk_out),
.rst (1'b0),
.sig_i(btn_y[0]),
.sig_o(btn_y_buf[0])
),
AJY1 (
.clk (clk_out),
.rst (1'b0),
.sig_i(btn_y[1]),
.sig_o(btn_y_buf[1])
),
AJY2 (
.clk (clk_out),
.rst (1'b0),
.sig_i(btn_y[2]),
.sig_o(btn_y_buf[2])
),
AJY3 (
.clk (clk_out),
.rst (1'b0),
.sig_i(btn_y[3]),
.sig_o(btn_y_buf[3])
);
`else
assign switch_buf = sw;
assign btn_y_buf = btn_y;
`endif
// assign switch_buf = sw;
// assign btn_y_buf = btn_y;
endmodule
| 7.000978 |
module AsyncResetRegVec_w1_i0 (
input clock,
input reset,
input io_d,
output io_q
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
AsyncResetReg reg_0 (
.rst(reg_0_rst),
.clk(reg_0_clk),
.en (reg_0_en),
.q (reg_0_q),
.d (reg_0_d)
);
assign io_q = reg_0_q;
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = 1'h1;
assign reg_0_d = io_d;
endmodule
| 6.68936 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0 (
input clock,
input reset,
input io_d,
output io_q
);
wire sync_0_clock;
wire sync_0_reset;
wire sync_0_io_d;
wire sync_0_io_q;
wire sync_1_clock;
wire sync_1_reset;
wire sync_1_io_d;
wire sync_1_io_q;
wire sync_2_clock;
wire sync_2_reset;
wire sync_2_io_d;
wire sync_2_io_q;
AsyncResetRegVec_w1_i0 sync_0 (
.clock(sync_0_clock),
.reset(sync_0_reset),
.io_d (sync_0_io_d),
.io_q (sync_0_io_q)
);
AsyncResetRegVec_w1_i0 sync_1 (
.clock(sync_1_clock),
.reset(sync_1_reset),
.io_d (sync_1_io_d),
.io_q (sync_1_io_q)
);
AsyncResetRegVec_w1_i0 sync_2 (
.clock(sync_2_clock),
.reset(sync_2_reset),
.io_d (sync_2_io_d),
.io_q (sync_2_io_q)
);
assign io_q = sync_0_io_q;
assign sync_0_io_d = sync_1_io_q;
assign sync_0_clock = clock;
assign sync_0_reset = reset;
assign sync_1_io_d = sync_2_io_q;
assign sync_1_clock = clock;
assign sync_1_reset = reset;
assign sync_2_io_d = io_d;
assign sync_2_clock = clock;
assign sync_2_reset = reset;
endmodule
| 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d4_i0 (
input clock,
input reset,
output io_q
);
wire sync_0_clock;
wire sync_0_reset;
wire sync_0_io_d;
wire sync_0_io_q;
wire sync_1_clock;
wire sync_1_reset;
wire sync_1_io_d;
wire sync_1_io_q;
wire sync_2_clock;
wire sync_2_reset;
wire sync_2_io_d;
wire sync_2_io_q;
wire sync_3_clock;
wire sync_3_reset;
wire sync_3_io_d;
wire sync_3_io_q;
AsyncResetRegVec_w1_i0 sync_0 (
.clock(sync_0_clock),
.reset(sync_0_reset),
.io_d (sync_0_io_d),
.io_q (sync_0_io_q)
);
AsyncResetRegVec_w1_i0 sync_1 (
.clock(sync_1_clock),
.reset(sync_1_reset),
.io_d (sync_1_io_d),
.io_q (sync_1_io_q)
);
AsyncResetRegVec_w1_i0 sync_2 (
.clock(sync_2_clock),
.reset(sync_2_reset),
.io_d (sync_2_io_d),
.io_q (sync_2_io_q)
);
AsyncResetRegVec_w1_i0 sync_3 (
.clock(sync_3_clock),
.reset(sync_3_reset),
.io_d (sync_3_io_d),
.io_q (sync_3_io_q)
);
assign io_q = sync_0_io_q;
assign sync_0_io_d = sync_1_io_q;
assign sync_0_clock = clock;
assign sync_0_reset = reset;
assign sync_1_io_d = sync_2_io_q;
assign sync_1_clock = clock;
assign sync_1_reset = reset;
assign sync_2_io_d = sync_3_io_q;
assign sync_2_clock = clock;
assign sync_2_reset = reset;
assign sync_3_io_d = 1'h1;
assign sync_3_clock = clock;
assign sync_3_reset = reset;
endmodule
| 6.605499 |
module AsyncValidSync (
input clock,
input reset,
output io_out
);
wire source_valid_clock;
wire source_valid_reset;
wire source_valid_io_q;
wire _T_5;
AsyncResetSynchronizerShiftReg_w1_d4_i0 source_valid (
.clock(source_valid_clock),
.reset(source_valid_reset),
.io_q (source_valid_io_q)
);
assign io_out = _T_5;
assign source_valid_clock = clock;
assign source_valid_reset = reset;
assign _T_5 = source_valid_io_q;
endmodule
| 6.70336 |
module AsyncResetSynchronizerShiftReg_w1_d1_i0 (
input clock,
input reset,
input io_d,
output io_q
);
wire sync_0_clock;
wire sync_0_reset;
wire sync_0_io_d;
wire sync_0_io_q;
AsyncResetRegVec_w1_i0 sync_0 (
.clock(sync_0_clock),
.reset(sync_0_reset),
.io_d (sync_0_io_d),
.io_q (sync_0_io_q)
);
assign io_q = sync_0_io_q;
assign sync_0_io_d = io_d;
assign sync_0_clock = clock;
assign sync_0_reset = reset;
endmodule
| 6.605499 |
module AsyncValidSync_1 (
input clock,
input reset,
input io_in,
output io_out
);
wire sink_extend_clock;
wire sink_extend_reset;
wire sink_extend_io_d;
wire sink_extend_io_q;
wire _T_5;
AsyncResetSynchronizerShiftReg_w1_d1_i0 sink_extend (
.clock(sink_extend_clock),
.reset(sink_extend_reset),
.io_d (sink_extend_io_d),
.io_q (sink_extend_io_q)
);
assign io_out = _T_5;
assign sink_extend_io_d = io_in;
assign sink_extend_clock = clock;
assign sink_extend_reset = reset;
assign _T_5 = sink_extend_io_q;
endmodule
| 6.70336 |
module AsyncValidSync_2 (
input clock,
input reset,
input io_in,
output io_out
);
wire sink_valid_clock;
wire sink_valid_reset;
wire sink_valid_io_d;
wire sink_valid_io_q;
wire _T_5;
AsyncResetSynchronizerShiftReg_w1_d3_i0 sink_valid (
.clock(sink_valid_clock),
.reset(sink_valid_reset),
.io_d (sink_valid_io_d),
.io_q (sink_valid_io_q)
);
assign io_out = _T_5;
assign sink_valid_io_d = io_in;
assign sink_valid_clock = clock;
assign sink_valid_reset = reset;
assign _T_5 = sink_valid_io_q;
endmodule
| 6.70336 |
module SynchronizerShiftReg_w42_d1 (
input clock,
input [41:0] io_d,
output [41:0] io_q
);
reg [41:0] sync_0;
reg [63:0] _RAND_0;
assign io_q = sync_0;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {2{$random}};
sync_0 = _RAND_0[41:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
sync_0 <= io_d;
end
endmodule
| 6.820992 |
module AsyncValidSync_3 (
input clock,
input reset,
output io_out
);
wire sink_valid_clock;
wire sink_valid_reset;
wire sink_valid_io_q;
wire _T_5;
AsyncResetSynchronizerShiftReg_w1_d4_i0 sink_valid (
.clock(sink_valid_clock),
.reset(sink_valid_reset),
.io_q (sink_valid_io_q)
);
assign io_out = _T_5;
assign sink_valid_clock = clock;
assign sink_valid_reset = reset;
assign _T_5 = sink_valid_io_q;
endmodule
| 6.70336 |
module AsyncValidSync_4 (
input clock,
input reset,
input io_in,
output io_out
);
wire source_extend_clock;
wire source_extend_reset;
wire source_extend_io_d;
wire source_extend_io_q;
wire _T_5;
AsyncResetSynchronizerShiftReg_w1_d1_i0 source_extend (
.clock(source_extend_clock),
.reset(source_extend_reset),
.io_d (source_extend_io_d),
.io_q (source_extend_io_q)
);
assign io_out = _T_5;
assign source_extend_io_d = io_in;
assign source_extend_clock = clock;
assign source_extend_reset = reset;
assign _T_5 = source_extend_io_q;
endmodule
| 6.70336 |
module AsyncValidSync_5 (
input clock,
input reset,
input io_in,
output io_out
);
wire source_valid_clock;
wire source_valid_reset;
wire source_valid_io_d;
wire source_valid_io_q;
wire _T_5;
AsyncResetSynchronizerShiftReg_w1_d3_i0 source_valid (
.clock(source_valid_clock),
.reset(source_valid_reset),
.io_d (source_valid_io_d),
.io_q (source_valid_io_q)
);
assign io_out = _T_5;
assign source_valid_io_d = io_in;
assign source_valid_clock = clock;
assign source_valid_reset = reset;
assign _T_5 = source_valid_io_q;
endmodule
| 6.70336 |
module SynchronizerShiftReg_w54_d1 (
input clock,
input [53:0] io_d,
output [53:0] io_q
);
reg [53:0] sync_0;
reg [63:0] _RAND_0;
assign io_q = sync_0;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {2{$random}};
sync_0 = _RAND_0[53:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
sync_0 <= io_d;
end
endmodule
| 6.820992 |
module SynchronizerShiftReg_w11_d1 (
input clock,
input [10:0] io_d,
output [10:0] io_q
);
reg [10:0] sync_0;
reg [31:0] _RAND_0;
assign io_q = sync_0;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{$random}};
sync_0 = _RAND_0[10:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
sync_0 <= io_d;
end
endmodule
| 6.820992 |
module AMOALU (
input [ 3:0] io_mask,
input [ 4:0] io_cmd,
input [31:0] io_lhs,
input [31:0] io_rhs,
output [31:0] io_out
);
wire _T_8;
wire _T_10;
wire max;
wire _T_12;
wire _T_14;
wire min;
wire add;
wire _T_17;
wire _T_19;
wire logic_and;
wire _T_21;
wire logic_xor;
wire [32:0] _T_24;
wire [31:0] adder_out;
wire [4:0] _T_28;
wire _T_31;
wire _T_32;
wire _T_33;
wire _T_34;
wire _T_35;
wire _T_38;
wire less;
wire _T_39;
wire [31:0] minmax;
wire [31:0] _T_40;
wire [31:0] _T_42;
wire [31:0] _T_43;
wire [31:0] _T_45;
wire [31:0] logic$;
wire _T_46;
wire [31:0] _T_47;
wire [31:0] out;
wire _T_48;
wire _T_49;
wire _T_50;
wire _T_51;
wire [7:0] _T_55;
wire [7:0] _T_59;
wire [7:0] _T_63;
wire [7:0] _T_67;
wire [15:0] _T_68;
wire [15:0] _T_69;
wire [31:0] wmask;
wire [31:0] _T_70;
wire [31:0] _T_71;
wire [31:0] _T_72;
wire [31:0] _T_73;
assign _T_8 = io_cmd == 5'hd;
assign _T_10 = io_cmd == 5'hf;
assign max = _T_8 | _T_10;
assign _T_12 = io_cmd == 5'hc;
assign _T_14 = io_cmd == 5'he;
assign min = _T_12 | _T_14;
assign add = io_cmd == 5'h8;
assign _T_17 = io_cmd == 5'ha;
assign _T_19 = io_cmd == 5'hb;
assign logic_and = _T_17 | _T_19;
assign _T_21 = io_cmd == 5'h9;
assign logic_xor = _T_21 | _T_17;
assign _T_24 = io_lhs + io_rhs;
assign adder_out = _T_24[31:0];
assign _T_28 = io_cmd & 5'h2;
assign _T_31 = _T_28 == 5'h0;
assign _T_32 = io_lhs[31];
assign _T_33 = io_rhs[31];
assign _T_34 = _T_32 == _T_33;
assign _T_35 = io_lhs < io_rhs;
assign _T_38 = _T_31 ? _T_32 : _T_33;
assign less = _T_34 ? _T_35 : _T_38;
assign _T_39 = less ? min : max;
assign minmax = _T_39 ? io_lhs : io_rhs;
assign _T_40 = io_lhs & io_rhs;
assign _T_42 = logic_and ? _T_40 : 32'h0;
assign _T_43 = io_lhs ^ io_rhs;
assign _T_45 = logic_xor ? _T_43 : 32'h0;
assign logic$ = _T_42 | _T_45;
assign _T_46 = logic_and | logic_xor;
assign _T_47 = _T_46 ? logic$ : minmax;
assign out = add ? adder_out : _T_47;
assign _T_48 = io_mask[0];
assign _T_49 = io_mask[1];
assign _T_50 = io_mask[2];
assign _T_51 = io_mask[3];
assign _T_55 = _T_48 ? 8'hff : 8'h0;
assign _T_59 = _T_49 ? 8'hff : 8'h0;
assign _T_63 = _T_50 ? 8'hff : 8'h0;
assign _T_67 = _T_51 ? 8'hff : 8'h0;
assign _T_68 = {_T_59, _T_55};
assign _T_69 = {_T_67, _T_63};
assign wmask = {_T_69, _T_68};
assign _T_70 = wmask & out;
assign _T_71 = ~wmask;
assign _T_72 = _T_71 & io_lhs;
assign _T_73 = _T_70 | _T_72;
assign io_out = _T_73;
endmodule
| 8.467919 |
module BreakpointUnit (
input io_status_debug,
input io_bp_0_control_action,
input [ 1:0] io_bp_0_control_tmatch,
input io_bp_0_control_x,
input io_bp_0_control_w,
input io_bp_0_control_r,
input [31:0] io_bp_0_address,
input [31:0] io_pc,
input [31:0] io_ea,
output io_xcpt_if,
output io_xcpt_ld,
output io_xcpt_st,
output io_debug_if,
output io_debug_ld,
output io_debug_st
);
wire _T_27;
wire [3:0] _T_31;
wire _T_32;
wire _T_33;
wire _T_35;
wire _T_36;
wire _T_37;
wire _T_38;
wire _T_39;
wire [31:0] _T_40;
wire _T_42;
wire _T_43;
wire _T_44;
wire _T_45;
wire _T_46;
wire _T_47;
wire [1:0] _T_48;
wire [1:0] _T_49;
wire [3:0] _T_50;
wire [31:0] _GEN_6;
wire [31:0] _T_51;
wire [31:0] _T_52;
wire [31:0] _T_63;
wire _T_64;
wire _T_65;
wire _T_66;
wire _T_68;
wire _T_99;
wire _T_101;
wire _T_103;
wire _T_105;
wire [31:0] _T_106;
wire [31:0] _T_117;
wire _T_130;
wire _T_131;
wire _T_132;
wire _T_137;
wire _GEN_0;
wire _GEN_1;
wire _GEN_2;
wire _GEN_3;
wire _GEN_4;
wire _GEN_5;
assign _T_27 = io_status_debug == 1'h0;
assign _T_31 = 4'h8 >> 2'h3;
assign _T_32 = _T_31[0];
assign _T_33 = _T_27 & _T_32;
assign _T_35 = _T_33 & io_bp_0_control_r;
assign _T_36 = io_bp_0_control_tmatch[1];
assign _T_37 = io_ea >= io_bp_0_address;
assign _T_38 = io_bp_0_control_tmatch[0];
assign _T_39 = _T_37 ^ _T_38;
assign _T_40 = ~io_ea;
assign _T_42 = io_bp_0_address[0];
assign _T_43 = _T_38 & _T_42;
assign _T_44 = io_bp_0_address[1];
assign _T_45 = _T_43 & _T_44;
assign _T_46 = io_bp_0_address[2];
assign _T_47 = _T_45 & _T_46;
assign _T_48 = {_T_43, _T_38};
assign _T_49 = {_T_47, _T_45};
assign _T_50 = {_T_49, _T_48};
assign _GEN_6 = {{28'd0}, _T_50};
assign _T_51 = _T_40 | _GEN_6;
assign _T_52 = ~io_bp_0_address;
assign _T_63 = _T_52 | _GEN_6;
assign _T_64 = _T_51 == _T_63;
assign _T_65 = _T_36 ? _T_39 : _T_64;
assign _T_66 = _T_35 & _T_65;
assign _T_68 = _T_33 & io_bp_0_control_w;
assign _T_99 = _T_68 & _T_65;
assign _T_101 = _T_33 & io_bp_0_control_x;
assign _T_103 = io_pc >= io_bp_0_address;
assign _T_105 = _T_103 ^ _T_38;
assign _T_106 = ~io_pc;
assign _T_117 = _T_106 | _GEN_6;
assign _T_130 = _T_117 == _T_63;
assign _T_131 = _T_36 ? _T_105 : _T_130;
assign _T_132 = _T_101 & _T_131;
assign _T_137 = io_bp_0_control_action == 1'h0;
assign _GEN_0 = _T_66 ? _T_137 : 1'h0;
assign _GEN_1 = _T_66 ? io_bp_0_control_action : 1'h0;
assign _GEN_2 = _T_99 ? _T_137 : 1'h0;
assign _GEN_3 = _T_99 ? io_bp_0_control_action : 1'h0;
assign _GEN_4 = _T_132 ? _T_137 : 1'h0;
assign _GEN_5 = _T_132 ? io_bp_0_control_action : 1'h0;
assign io_xcpt_if = _GEN_4;
assign io_xcpt_ld = _GEN_0;
assign io_xcpt_st = _GEN_2;
assign io_debug_if = _GEN_5;
assign io_debug_ld = _GEN_1;
assign io_debug_st = _GEN_3;
endmodule
| 8.021329 |
module SynchronizerShiftReg_w1_d3 (
input clock,
input io_d,
output io_q
);
reg sync_0;
reg [31:0] _RAND_0;
reg sync_1;
reg [31:0] _RAND_1;
reg sync_2;
reg [31:0] _RAND_2;
assign io_q = sync_0;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{$random}};
sync_0 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{$random}};
sync_1 = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{$random}};
sync_2 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
sync_0 <= sync_1;
sync_1 <= sync_2;
sync_2 <= io_d;
end
endmodule
| 6.820992 |
module IntXbar_2 (
input auto_int_in_0_0,
input auto_int_in_0_1,
output auto_int_out_0,
output auto_int_out_1
);
wire _T_5_0;
wire _T_5_1;
wire _T_20_0;
wire _T_20_1;
assign auto_int_out_0 = _T_20_0;
assign auto_int_out_1 = _T_20_1;
assign _T_5_0 = auto_int_in_0_0;
assign _T_5_1 = auto_int_in_0_1;
assign _T_20_0 = _T_5_0;
assign _T_20_1 = _T_5_1;
endmodule
| 7.94893 |
module AsyncResetRegVec_w4_i15 (
input clock,
input reset,
input [3:0] io_d,
output [3:0] io_q
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
wire reg_1_rst;
wire reg_1_clk;
wire reg_1_en;
wire reg_1_q;
wire reg_1_d;
wire reg_2_rst;
wire reg_2_clk;
wire reg_2_en;
wire reg_2_q;
wire reg_2_d;
wire reg_3_rst;
wire reg_3_clk;
wire reg_3_en;
wire reg_3_q;
wire reg_3_d;
wire _T_5;
wire _T_7;
wire q_0;
wire _T_9;
wire _T_11;
wire q_1;
wire _T_13;
wire _T_15;
wire q_2;
wire _T_17;
wire _T_19;
wire q_3;
wire [1:0] _T_21;
wire [1:0] _T_22;
wire [3:0] _T_23;
AsyncResetReg reg_0 (
.rst(reg_0_rst),
.clk(reg_0_clk),
.en (reg_0_en),
.q (reg_0_q),
.d (reg_0_d)
);
AsyncResetReg reg_1 (
.rst(reg_1_rst),
.clk(reg_1_clk),
.en (reg_1_en),
.q (reg_1_q),
.d (reg_1_d)
);
AsyncResetReg reg_2 (
.rst(reg_2_rst),
.clk(reg_2_clk),
.en (reg_2_en),
.q (reg_2_q),
.d (reg_2_d)
);
AsyncResetReg reg_3 (
.rst(reg_3_rst),
.clk(reg_3_clk),
.en (reg_3_en),
.q (reg_3_q),
.d (reg_3_d)
);
assign _T_5 = io_d[0];
assign _T_7 = _T_5 == 1'h0;
assign q_0 = reg_0_q == 1'h0;
assign _T_9 = io_d[1];
assign _T_11 = _T_9 == 1'h0;
assign q_1 = reg_1_q == 1'h0;
assign _T_13 = io_d[2];
assign _T_15 = _T_13 == 1'h0;
assign q_2 = reg_2_q == 1'h0;
assign _T_17 = io_d[3];
assign _T_19 = _T_17 == 1'h0;
assign q_3 = reg_3_q == 1'h0;
assign _T_21 = {q_1, q_0};
assign _T_22 = {q_3, q_2};
assign _T_23 = {_T_22, _T_21};
assign io_q = _T_23;
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = 1'h1;
assign reg_0_d = _T_7;
assign reg_1_rst = reset;
assign reg_1_clk = clock;
assign reg_1_en = 1'h1;
assign reg_1_d = _T_11;
assign reg_2_rst = reset;
assign reg_2_clk = clock;
assign reg_2_en = 1'h1;
assign reg_2_d = _T_15;
assign reg_3_rst = reset;
assign reg_3_clk = clock;
assign reg_3_en = 1'h1;
assign reg_3_d = _T_19;
endmodule
| 6.68936 |
module anton_neopixel_apb_top #(
// number of bytes counting from zero, so the size is BUFFER_END+1, maximum
// 8192 bytes (8192 pixels in 8bit mode and 2048 pixels in 32bit mode), which should have ~4Hz refresh
parameter BUFFER_END = `BUFFER_END_DEFAULT, // read anton_common.vh
parameter VIRTUAL_END = `BUFFER_END_DEFAULT, // read anton_common.vh
// How long the reset delay will be happening, minimum spec is so
// 50us => 50000ns/(1/6.4) = 320 000 ticks. But some arrays need bit more:
// 81us => 81000ns/(1/6.4) = 518 400 ticks
parameter RESET_DELAY = `RESET_DELAY_DEFAULT
) (
input clk6_4mhz,
input syncStart,
output neoData,
output neoState,
input apbPenable,
input [19:0] apbPaddr, // control registers/deltas/virtual region/raw region 19:18 + LED raw data 14:2 (or 17:2 for virtual writes) + ignored 1:0
input [7:0] apbPwData,
input apbPclk,
input apbPselx,
input apbPresern,
input apbPwrite,
output [7:0] apbPrData,
output apbPready,
output apbPslverr
);
wire wrEnable;
wire rdEnable;
wire [17:0] address; // correct address packed down from 32bit aligned access to 8bit access, will be limited to 8192 pixels (but for the virtual deltas 2 writes per pixel and 2 bits for write modes)
assign apbPslverr = 1'd0; // never report errors
assign wrEnable = (apbPenable && apbPwrite && apbPselx);
assign rdEnable = (!apbPwrite && apbPselx);
assign address = apbPaddr[19:2]; // 4 bytes (word) aligned to 1 byte aligned, 20bit addr but only 18bits are used
reg [2:0] testUnit; // TODO: disable when not in simulation/debug
anton_neopixel_module #(
.BUFFER_END (`SANITIZE_BUFFER_END(BUFFER_END)),
.VIRTUAL_END(`SANITIZE_BUFFER_END(VIRTUAL_END)),
.RESET_DELAY(RESET_DELAY)
) neopixel (
.clk6_4mhz(clk6_4mhz),
.syncStart(syncStart),
.neoData(neoData),
.neoState(neoState),
.busAddr(address),
.busDataIn(apbPwData),
.busClk(apbPclk),
.busWrite(wrEnable),
.busRead(rdEnable),
.busDataOut(apbPrData),
.busReady(apbPready)
);
endmodule
| 7.450523 |
module anton_neopixel_module #(
parameter BUFFER_END = `BUFFER_END_DEFAULT, // read anton_common.vh
parameter VIRTUAL_END = `BUFFER_END_DEFAULT, // read anton_common.vh
parameter RESET_DELAY = `RESET_DELAY_DEFAULT
) (
input clk6_4mhz,
input syncStart,
output neoData,
output neoState,
input [17:0] busAddr,
input [ 7:0] busDataIn,
input busClk,
input busWrite,
input busRead,
output [ 7:0] busDataOut,
output busReady
);
// minimum required amount of bits to store the BUFFER_END
localparam BUFFER_BITS = `CLOG2(BUFFER_END + 1);
wire [ 12:0] regMax;
wire regCtrlInit;
wire regCtrlLimit;
wire regCtrlRun;
wire regCtrlLoop;
wire regCtrl32bit;
wire initSlow;
wire initSlowDone;
wire streamSyncOf;
wire [BUFFER_BITS-1:0] pixelIxComb;
wire [ 7:0] pixelByte;
anton_neopixel_registers #(
.BUFFER_END (`SANITIZE_BUFFER_END(BUFFER_END)),
.VIRTUAL_END(`SANITIZE_BUFFER_END(VIRTUAL_END))
) registers (
.busClk(busClk),
.busAddr(busAddr),
.busDataIn(busDataIn),
.busWrite(busWrite),
.busRead(busRead),
.busDataOut(busDataOut),
.busReady(busReady),
.pixelIxComb(pixelIxComb),
.pixelByte (pixelByte),
.streamSyncOf(streamSyncOf),
.syncStart(syncStart),
.state(neoState),
.regMax(regMax),
.regCtrlInit(regCtrlInit),
.regCtrlLimit(regCtrlLimit),
.regCtrlRun(regCtrlRun),
.regCtrlLoop(regCtrlLoop),
.regCtrl32bit(regCtrl32bit),
.initSlow(initSlow),
.initSlowDone(initSlowDone)
);
wire [ 2:0] bitPatternIx; // 8 patterns in a bit
wire [ 2:0] pixelBitIx; // 8 bits in channel
wire [ 1:0] channelIx; // 3 channels in pixel
wire [BUFFER_BITS-1:0] pixelIxMax;
wire streamOutput;
wire streamReset;
wire streamBitOf;
wire streamChannelOf;
wire streamPixelOf;
anton_neopixel_stream_logic #(
.BUFFER_END (`SANITIZE_BUFFER_END(BUFFER_END)),
.RESET_DELAY(RESET_DELAY)
) stream_logic (
.clk6_4mhz(clk6_4mhz),
.regCtrlInit(regCtrlInit),
.regCtrlRun(regCtrlRun),
.regCtrlLoop(regCtrlLoop),
.regCtrlLimit(regCtrlLimit),
.regCtrl32bit(regCtrl32bit),
.regMax(regMax),
.initSlow(initSlow),
.initSlowDone(initSlowDone),
.bitPatternIx(bitPatternIx),
.pixelBitIx(pixelBitIx),
.channelIx(channelIx),
.pixelIxMax(pixelIxMax),
.pixelIxComb(pixelIxComb),
.state(neoState),
.streamOutput(streamOutput),
.streamReset(streamReset),
.streamBitOf(streamBitOf),
.streamChannelOf(streamChannelOf),
.streamPixelOf(streamPixelOf),
.streamSyncOf(streamSyncOf)
);
anton_neopixel_stream #(
.BUFFER_END(`SANITIZE_BUFFER_END(BUFFER_END))
) stream (
.pixelByte(pixelByte),
.state(neoState),
.channelIx(channelIx),
.pixelBitIx(pixelBitIx),
.bitPatternIx(bitPatternIx),
.regCtrl32bit(regCtrl32bit),
.regCtrlRun(regCtrlRun),
.neoData(neoData)
);
endmodule
| 7.450523 |
module anton_neopixel_stream #(
parameter BUFFER_END = `BUFFER_END_DEFAULT, // read anton_common.vh
localparam BUFFER_BITS =
`CLOG2(BUFFER_END + 1) // minimum required amount of bits to store the BUFFER_END
) (
input [7:0] pixelByte,
input state,
input [2:0] pixelBitIx, // 0 - 7 to count whole 8bits of a one channel (RGB) inside a pixel
input [1:0] channelIx,
input [2:0] bitPatternIx,
input regCtrl32bit,
input regCtrlRun,
output neoData
);
reg [7:0] neoPatternLookup = 'd0; // move to wire
reg neoDataB = 'b0;
reg [7:0] pixelColourValue = 'd0; // One of the channels Blue Red Green, order is from right to left and the MSB are sent first
// as combinational logic should be enough
// https://electronics.stackexchange.com/questions/29553/how-are-verilog-always-statements-implemented-in-hardware
always @(*) begin
// depending on the current bit decide what pattern to push
// patterns are ordered from right to left
if (pixelColourValue[pixelBitIx]) begin
neoPatternLookup = 8'b00011111;
end else begin
neoPatternLookup = 8'b00000011;
end
end
always @(*) begin
if (regCtrl32bit) begin
// In 32bit mode use 3 bytes to concatenate RGB values and reordered
// them to make it convenient (4th byte is dropped)
pixelColourValue = {
pixelByte[0],
pixelByte[1],
pixelByte[2],
pixelByte[3],
pixelByte[4],
pixelByte[5],
pixelByte[6],
pixelByte[7] // RGB depending on the channelIx
};
end else begin
// 8bit mode
// 2B, 3G, 3R = 8bit source format => [7:5]Red, [4:2]Green, [1:0]Blue
// 8B, 8R, 8G = 32bit destination format => xxxxBxxB xxRxRxxR xxGxGxGx high bits are sent first (so reorder them to the right)
case (channelIx)
default:
pixelColourValue = {
2'b00, pixelByte[2], 1'b0, pixelByte[3], 1'b0, pixelByte[4], 1'b0
}; // 3bits Green, the 'd0 and default are the same
'd1:
pixelColourValue = {
2'b00, pixelByte[5], 1'b0, pixelByte[6], 2'b00, pixelByte[7]
}; // 3bits Red
'd2: pixelColourValue = {4'b0000, pixelByte[0], 2'b00, pixelByte[1]}; // 2bits Blues
endcase
end
end
always @(*) begin
if (state == `ENUM_STATE_TRANSMIT && regCtrlRun) begin
// push pattern of a single bit inside a pixel
neoDataB = neoPatternLookup[bitPatternIx[2:0]];
end else begin
// reset state, stay LOW
neoDataB = 'd0;
end
end
assign neoData = neoDataB;
endmodule
| 7.450523 |
module anton_ram_2port_asymmetric #(
parameter BUFFER_END = `BUFFER_END_DEFAULT, // read anton_common.vh
parameter BUFFER_WIDTH_READ = 16,
parameter BUFFER_WIDTH_WRITE = 8,
localparam BUFFER_BITS =
`CLOG2(BUFFER_END + 1) // minimum required amount of bits to store the BUFFER_END
) (
input clk,
input [BUFFER_BITS-1:0] rAddr,
output [BUFFER_WIDTH-READ-1:0] dOut,
input wr,
input [ BUFFER_BITS-1:0] wAddr,
input [BUFFER_WIDTH_WRITE-1:0] dIn
);
reg [BUFFER_BITS-1:0] raddr_reg;
reg [BUFFER_WIDTH_READ-1:0] mem[0:BUFFER_END-1];
reg [BUFFER_WIDTH_READ-1:0] dOutB1;
reg [BUFFER_WIDTH_READ-1:0] dOutB2;
always @(posedge clk) begin
raddr_reg <= rAddr;
dOutB2 <= mem[raddr_reg];
if (wr) mem[wAddr] <= dIn;
end
always @(posedge clk) begin
dOutB1 <= dOutB2;
end
assign dOutB = dOutB1;
endmodule
| 7.228175 |
module anton_ram_2port_symmetric #(
parameter BUFFER_END = `BUFFER_END_DEFAULT, // read anton_common.vh
parameter BUFFER_WIDTH = 8,
localparam BUFFER_BITS =
`CLOG2(BUFFER_END + 1) // minimum required amount of bits to store the BUFFER_END
) (
input clk,
input [ BUFFER_BITS-1:0] rAddr,
output [BUFFER_WIDTH-1:0] dOut,
input wr,
input [ BUFFER_BITS-1:0] wAddr,
input [BUFFER_WIDTH-1:0] dIn
);
reg [BUFFER_BITS-1:0] raddr_reg;
reg [BUFFER_WIDTH-1:0] mem[0:BUFFER_END-1];
reg [BUFFER_WIDTH-1:0] dOutB1;
reg [BUFFER_WIDTH-1:0] dOutB2;
always @(posedge clk) begin
raddr_reg <= rAddr;
dOutB2 <= mem[raddr_reg];
if (wr) mem[wAddr] <= dIn;
end
always @(posedge clk) begin
dOutB1 <= dOutB2;
end
assign dOut = dOutB1;
endmodule
| 7.228175 |
module ant #(
parameter N = 16,
M = 64,
WIDTH = 16
) (
input clk,
input reset,
input [N*M-1:0] adjacency,
input [N*WIDTH-1:0] weights,
input [1:0] id,
input [5:0] query,
input [WIDTH+5:0] response, //{data,page_id},get response from noc
output reg [5:0] request, //send request to noc
output reg [WIDTH-1:0] reply, //send reply to noc
output reg [WIDTH-1:0] node0Val, //only for test
output wire [WIDTH*N-1:0] vals
);
//We will use a 16 bit fixed point representation throughout.
//All values are in the range [0,(2^16-1)/2^16].
// For example, the 16 bit value 2'h11 corresponds to (2^16-1)/2^16.
localparam base = 17'h10000; //2^17
localparam d = 16'h2666; //d = 0.15, 9830 0.15=15/100=3/20
localparam dn = d / N; // d/N : NOTE --- please update based on N
localparam db = base - d; //1-d: NOTE: --- please update based on d
localparam n_1 = base / N; // 1/n
reg [WIDTH-1:0] nodeVal_next[N-1:0]; //next state node value
reg [WIDTH-1:0] nodeVal[N-1:0]; //value of each node
reg [WIDTH-1:0] nodeWeight[N-1:0]; //weight of each node
reg [M-1:0] adj[N-1:0]; //adjacency matrix
reg [N-1:0] i, j, k, p, q, r, x, s, z;
reg [N-1:0] count;
reg [3*WIDTH-1:0] temp; //16bit*16bit*16bit
//output all the page vals
generate
genvar y;
for (y = 0; y < N; y = y + 1) assign vals[y*WIDTH+:WIDTH] = nodeVal[y];
endgenerate
//Convert adj from 1D to 2D array
always @(*) begin
count = 0;
for (p = 0; p < N; p = p + 1) begin
for (q = 0; q < M; q = q + 1) begin
adj[p][q] = adjacency[count];
count = count + 1;
end
end
end
//Convert nodeWeights from 1D to 2D array
always @(*) begin
for (r = 0; r < N; r = r + 1) begin
nodeWeight[r] = weights[r*WIDTH+:WIDTH];
end
end
always @(*) begin
node0Val = nodeVal[0];
end
reg [5:0] page;
reg [6:0] ref_page;
reg block;
always @(posedge clk or posedge reset) begin
if (reset) begin
ref_page <= 0;
page <= 0;
end else if (!block) begin
if (ref_page == M - 1) begin
ref_page <= 0;
if (page == N - 1) page <= 0;
else page = page + 1;
end else ref_page = ref_page + 1;
end
end
always @(ref_page, page) begin
if (adj[page][ref_page]) begin
if (ref_page < (id + 1) * N && ref_page >= id * N) begin
//inner
end else begin
//outer
block = 1'b1;
request = ref_page;
end
end
end
//----------------------------I/O----------------------------
//reply to noc
reg [5:0] index;
reg [3*WIDTH-1:0] buffer2;
always @(query) begin
index = query - id * N; //6 bits-id 2 bits* WIDTH 4 bits
buffer2 = db * nodeVal[index] * nodeWeight[index];
reply = buffer2[3*WIDTH-1:2*WIDTH];
end
reg [5:0] response_page;
reg [WIDTH-1:0] response_val;
//update with incomming response
always @(response) begin
response_page = response[5:0];
response_val = response[WIDTH+5:6];
nodeVal[page] = nodeVal[page] + response_val;
block = 1'b0; //cancel block, process resume
end
endmodule
| 7.11283 |
module pageRank #(
parameter M = 64,
WIDTH = 16
) (
input clk,
input reset,
input [M*M-1:0] adj,
input [M*WIDTH-1:0] nodeWeight,
output [10*WIDTH-1:0] top10Vals,
output [10*6-1:0] top10IDs,
output wire [WIDTH-1:0] nodeVal0,
output wire [WIDTH-1:0] nodeVal16,
output wire [WIDTH-1:0] nodeVal32,
output wire [WIDTH-1:0] nodeVal48
);
parameter N = 16, RESP_W = WIDTH + 6 + 3, REQ_W = 12, DEPTH = 16, MAX_UPDATE_TIME = 4000;
wire [5:0] query[3:0];
wire [WIDTH+5:0] response[3:0];
wire [5:0] request[3:0];
wire [WIDTH-1:0] reply[3:0];
wire [WIDTH-1:0] node0Val[3:0];
wire [WIDTH*N-1:0] array[3:0];
reg done;
reg syc_in = 1'b1; //input to ants
wire syc_out[3:0]; //output from ants
assign nodeVal0 = node0Val[0];
assign nodeVal16 = node0Val[1];
assign nodeVal32 = node0Val[2];
assign nodeVal48 = node0Val[3];
integer k;
always @(*) begin
//k=16;
//$display($time,"----pageRank64-----k=%d %p",k+1,array_in[k*WIDTH+:WIDTH]);
$display($time, "--------------------");
for (k = 0; k < N; k = k + 1) begin
$display("k=%d ,%d", k, array[0][k*WIDTH+:WIDTH]);
end
end
// always @(*)begin
// $display($time,"array=%p",array[0]);
// end
//----------------update time count--------
reg [12:0] update_time;
always @(posedge clk or posedge reset) begin
if (reset) begin
update_time <= 0;
done <= 0;
end else if (~done) begin
update_time <= update_time + 1;
if (update_time == MAX_UPDATE_TIME) done <= 1;
end
end
//---------------cpu------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
syc_in = 1;
end else begin
syc_in = syc_out[0] && syc_out[1] && syc_out[2] && syc_out[3];
end
end
// always @(*)begin
// $display($time,"syc_in=%d",syc_in);
// end
generate
genvar i;
for (i = 0; i < 4; i = i + 1) begin
ant #(N, M, WIDTH) ant (
clk,
reset,
adj[i*N*M+:N*M],
nodeWeight[i*N*WIDTH+:N*WIDTH],
i[1:0],
query[i],
response[i],
syc_in,
request[i],
reply[i],
node0Val[i],
array[i],
syc_out[i]
);
end
endgenerate
//-----------------noc(ReqRouter+RespRouter+requester+responser)---------------
noc #(N, WIDTH, RESP_W, REQ_W, DEPTH) noc (
clk,
reset,
request[0],
request[1],
request[2],
request[3], //-->request_id,request page id,16~64
reply[0],
reply[1],
reply[2],
reply[3], //--->reply from ants
query[0],
query[1],
query[2],
query[3], //--->query_id, page value that requestd
response[0],
response[1],
response[2],
response[3]
); //resonsder out-->response to ants
//---------------sortvals------------
wire enable_sort;
wire [M*WIDTH-1:0] array_in;
wire [10*WIDTH-1:0] array_out;
//merge
generate
genvar j;
for (j = 0; j < 4; j = j + 1) begin
assign array_in[j*N*WIDTH+:N*WIDTH] = array[j];
end
endgenerate
top10 #(WIDTH, M) sortvals (
clk,
reset,
done,
array_in,
top10Vals,
top10IDs
);
endmodule
| 7.537287 |
module Anubis_SBox (
input [7:0] idat,
output [7:0] odat
);
wire [7:0] a, b, c, d;
// layer 1
Anubis_PBox pbox1 (
.idat(idat[7:4]),
.odat(a[7:4])
);
Anubis_QBox qbox1 (
.idat(idat[3:0]),
.odat(a[3:0])
);
// 2-bit shuffle
assign b[3:0] = {a[5:4], a[1:0]};
assign b[7:4] = {a[7:6], a[3:2]};
// layer 2
Anubis_QBox qbox2 (
.idat(b[7:4]),
.odat(c[7:4])
);
Anubis_PBox pbox2 (
.idat(b[3:0]),
.odat(c[3:0])
);
// 2-bit shuffle
assign d[3:0] = {c[5:4], c[1:0]};
assign d[7:4] = {c[7:6], c[3:2]};
// layer 3
Anubis_PBox pbox3 (
.idat(d[7:4]),
.odat(odat[7:4])
);
Anubis_QBox qbox3 (
.idat(d[3:0]),
.odat(odat[7:4])
);
endmodule
| 6.518908 |
module the implementation
// Uses modules: transmit_top.v, receive_top.v, anubis.v
// Board: BASYS3 By Digilent
//------------------------------------------------------------------
module anubis_wrapper(
input wire clk_w5, // onboard 100 Mhz clock (W5 pin)
input wire reset_b, // onboard reset (push button U18)
input wire RxD, // data recieved through communication protocol (PMOD)
input wire r_sync, // request for synchronization from a remote device (PMOD)
input wire r_acknowledge, // remote device acknowledgment in the communication protocol
output wire TxD, // data which being sent through communication protocol (PMOD)
output wire basys3_acknowledge, // Basys3 Acknowledgement in the communication protocol
output wire basys3_sync// Basys3 is ready to Synchronization
);
reg rxd_en; //LED on board
reg txd_en ; //LED on board
wire rxd_done; //LED on board
wire txd_done; //LED on board
wire [4:0] clk;
reg [127:0] plain_text_128;
wire [127:0] data_in,key_in;
reg [127:0] key_128;
wire [127:0] cipher_text_128;
reg [127:0] data_out;
wire encrypt_mode;
reg encrypt;
wire core_done;
reg basys_ack;
reg basys3_s;
wire clock_div;
assign clk=clock_div;
assign basys3_acknowledge=basys_ack;
assign basys3_sync=basys3_s;
//if (rxd_en&&~txd_en)
// assign basys3_acknowledge = basys_ack_r;
//assign
// Encryption/Decryption with the anubis algorithm (plaintext[127:0] and key[127:0] )
anubis CORE(
.clk(clk_w5),
.reset(reset_b),
.encrypt(encrypt), //encrypt or decrypt ?
.plain_text(plain_text_128),
.key(key_128),
.cipher_text(cipher_text_128),
.end_flag(core_done)
);
// 4 Mhz Clock to synchronization with CmodA7
clk_4 CLOCK(
.clk_w5(clk_w5),
.reset_b(reset_b),
.clk(clock_div)
);
//recieve data from CMOD-A7
recieve_top COM_RxD(
.clk(clk), //4Mhz
.reset_b(reset_b),
.RxD(RxD),
.r_sync(r_sync),
.r_acknowledge(r_acknowledge),
.basys3_sync(basys3_sync),
.basys3_acknowledge(basys3_ack_r),
.enable(rxd_en),
.data_in(data_in),
.key_in(key_in),
.encrypt(encrypt_mode),
.ready(rxd_done)
);
//transmit data to CMOD-A7
transmit_top COM_TxD(
.clk(clk),
.reset_b(reset_b),
.TxD(TxD),
.r_sync(r_sync),
.r_acknowledge(r_acknowledge),
.basys3_sync(basys_s),
.basys3_acknowledge(basys3_acknowledge_t),
.enable(txd_en),
.data_out(data_out),
.encrypt(encrypt_mode),
.ready(txd_done)
);
// recieved data from Communication to basys3 registers
always @(posedge clk_w5 or posedge reset_b)
begin
if (reset_b) //reset high - initialization
begin
plain_text_128<= 128'b0;
key_128<= 128'b0;
data_out<= 128'b0;
data_out<=128'b0;
encrypt<=1'b0;
rxd_en <=1'b1; // after reset idle state= waiting for data to be recieved
txd_en <=1'b0; //
basys3_s <= 1'b0;
end
else //reset is low
if (rxd_en && rxd_done && basys3_acknowledge)
if(encrypt_mode)
begin //encryption of received data
plain_text_128 <= data_in;
key_128 <= key_in;
encrypt <=1'b1;
rxd_en <= 1'b0; // disable recieving and changes in internal register
end
else
begin //decryption of received data
plain_text_128 <= data_in;
key_128 <= key_in;
encrypt <=1'b0;
rxd_en <= 1'b0; // disable recieving and changes in internal register
end
end
// Returning the ciphertext or plaintext(depends on requested core operation) to the remote device
always @ (posedge clk_w5)
begin
if (core_done)
begin
data_out<= cipher_text_128;
rxd_en<=1'b1;
basys3_s<=1'b1; //waiting for communication
basys_ack<=1'b0;
end
if (basys3_sync && r_acknowledge)
begin
basys_ack<=1'b1;
txd_en<=1'b1;
end
if (basys3_acknowledge && txd_done)
begin
basys3_s<=1'b0;
basys_ack<=1'b0;
txd_en<=1'b0;
end
end
endmodule
| 7.086096 |
module anyToRecodedFloat32 (
output [ 4:0] exceptionFlags,
input [63:0] in,
output [32:0] out,
input [ 1:0] typeOp,
input [ 1:0] roundingMode
);
wire [ 0:0] T2;
wire [31:0] T3;
wire [63:0] T4;
wire [ 0:0] T5;
wire [ 0:0] T6;
wire [ 0:0] T7;
wire [ 0:0] T8;
wire [ 0:0] T9;
wire [ 0:0] T10;
wire [ 0:0] T11;
wire [ 0:0] T12;
wire [ 0:0] T13;
wire [ 0:0] T14;
wire [ 0:0] sign;
wire [31:0] T15;
wire [31:0] T16;
wire [31:0] T17;
wire [31:0] T18;
wire [63:0] T19;
wire [ 0:0] T20;
wire [ 0:0] T21;
wire [63:0] T22;
wire [63:0] T23;
wire [63:0] T24;
wire [63:0] T25;
wire [63:0] T26;
wire [63:0] norm_in;
wire [63:0] out_0;
wire [ 1:0] T27;
wire [38:0] T28;
wire [ 0:0] T29;
wire [ 2:0] roundBits;
wire [ 1:0] T30;
wire [ 0:0] roundInexact;
wire [ 4:0] T31;
wire [ 0:0] T32;
wire [ 0:0] T33;
wire [ 5:0] dist_1;
wire [ 0:0] T34;
wire [ 0:0] T35;
wire [ 5:0] T36;
wire [ 8:0] T37;
wire [23:0] T38;
wire [24:0] T39;
wire [ 0:0] T40;
wire [ 1:0] T41;
wire [ 0:0] T42;
wire [ 1:0] T43;
wire [ 0:0] T44;
wire [ 0:0] roundEvenOffset;
wire [ 0:0] T45;
wire [ 0:0] T46;
wire [ 0:0] T47;
wire [ 0:0] T48;
wire [ 0:0] T49;
wire [ 0:0] T50;
wire [ 0:0] T51;
wire [ 0:0] T52;
wire [ 0:0] T53;
wire [ 0:0] T54;
wire [ 0:0] T55;
wire [ 0:0] roundOffset;
wire [24:0] norm_round;
wire [ 0:0] T56;
wire [ 8:0] exponent_offset;
wire [ 8:0] exponent;
wire [ 9:0] T57;
wire [22:0] T58;
wire [32:0] T59;
assign T2 = typeOp == 2'h0;
assign T3 = in[5'h1f:1'h0];
assign T4 = {32'h0, T3};
assign T5 = typeOp == 2'h1;
assign T6 = typeOp == 2'h0;
assign T7 = typeOp == 2'h1;
assign T8 = in[5'h1f];
assign T9 = typeOp == 2'h2;
assign T10 = typeOp == 2'h3;
assign T11 = in[6'h3f];
assign T12 = T10 ? T11 : 1'h0;
assign T13 = T9 ? 1'h0 : T12;
assign T14 = T7 ? T8 : T13;
assign sign = T6 ? 1'h0 : T14;
assign T15 = in[5'h1f:1'h0];
assign T16 = -T15;
assign T17 = in[5'h1f:1'h0];
assign T18 = sign ? T16 : T17;
assign T19 = {32'h0, T18};
assign T20 = typeOp == 2'h2;
assign T21 = typeOp == 2'h3;
assign T22 = -in;
assign T23 = sign ? T22 : in;
assign T24 = T21 ? T23 : 64'h0;
assign T25 = T20 ? in : T24;
assign T26 = T5 ? T19 : T25;
assign norm_in = T2 ? T4 : T26;
assign T27 = out_0[6'h28:6'h27];
assign T28 = out_0[6'h26:1'h0];
assign T29 = T28 != 39'h0;
assign roundBits = {T27, T29};
assign T30 = roundBits[1'h1:1'h0];
assign roundInexact = T30 != 2'h0;
assign T31 = {4'h0, roundInexact};
assign exceptionFlags = T31;
assign T32 = out_0[6'h3f];
assign T33 = T32 == 1'h0;
assign T34 = dist_1 == 6'h3f;
assign T35 = T33 && T34;
assign T36 = ~dist_1;
assign T37 = {3'b100, T36};
assign T38 = out_0[6'h3f:6'h28];
assign T39 = {1'h0, T38};
assign T40 = roundingMode == 2'h0;
assign T41 = roundBits[1'h1:1'h0];
assign T42 = T41 == 2'b11;
assign T43 = roundBits[2'h2:1'h1];
assign T44 = T43 == 2'b11;
assign roundEvenOffset = T42 || T44;
assign T45 = roundingMode == 2'h1;
assign T46 = roundingMode == 2'h2;
assign T47 = roundInexact ? 1'h1 : 1'h0;
assign T48 = sign & T47;
assign T49 = roundingMode == 2'h3;
assign T50 = ~sign;
assign T51 = roundInexact ? 1'h1 : 1'h0;
assign T52 = T50 & T51;
assign T53 = T49 ? T52 : 1'h0;
assign T54 = T46 ? T48 : T53;
assign T55 = T45 ? 1'h0 : T54;
assign roundOffset = T40 ? roundEvenOffset : T55;
assign norm_round = T39 + roundOffset;
assign T56 = norm_round[5'h18];
assign exponent_offset = T37 + T56;
assign exponent = T35 ? 9'h0 : exponent_offset;
assign T57 = {sign, exponent};
assign T58 = norm_round[5'h16:1'h0];
assign T59 = {T57, T58};
assign out = T59;
normalize64_0 normalize64_0 (
.in(norm_in),
.out(out_0),
.distance(dist_1)
);
endmodule
| 7.073609 |
module recodedFloat32ToFloat32 (
input [32:0] in,
output [31:0] out
);
wire [ 0:0] sign;
wire [ 8:0] expIn;
wire [ 1:0] T0;
wire [ 0:0] T1;
wire [ 6:0] T2;
wire [ 0:0] exp01_isHighSubnormalIn;
wire [ 0:0] T3;
wire [ 0:0] T4;
wire [ 1:0] T5;
wire [ 0:0] T6;
wire [ 0:0] isNormal;
wire [ 8:0] normal_expOut;
wire [ 8:0] T7;
wire [ 1:0] T8;
wire [ 0:0] isSpecial;
wire [ 7:0] T9;
wire [ 8:0] expOut;
wire [ 7:0] T10;
wire [ 8:0] T11;
wire [ 2:0] T12;
wire [ 0:0] T13;
wire [ 1:0] T14;
wire [ 0:0] T15;
wire [ 0:0] T16;
wire [ 0:0] isSubnormal;
wire [22:0] fractIn;
wire [23:0] T17;
wire [ 4:0] T18;
wire [ 4:0] denormShiftDist;
wire [ 4:0] T19;
wire [23:0] subnormal_fractOut;
wire [23:0] T20;
wire [ 0:0] T21;
wire [ 0:0] isNaN;
wire [ 0:0] T22;
wire [22:0] T23;
wire [23:0] fractOut;
wire [22:0] T24;
wire [31:0] T25;
assign sign = in[6'h20];
assign expIn = in[5'h1f:5'h17];
assign T0 = expIn[4'h8:3'h7];
assign T1 = T0 == 2'b01;
assign T2 = expIn[3'h6:1'h0];
assign exp01_isHighSubnormalIn = T2 < 7'h2;
assign T3 = ~exp01_isHighSubnormalIn;
assign T4 = T1 & T3;
assign T5 = expIn[4'h8:3'h7];
assign T6 = T5 == 2'b10;
assign isNormal = T4 | T6;
assign normal_expOut = expIn - 9'b010000001;
assign T7 = isNormal ? normal_expOut : 8'h0;
assign T8 = expIn[4'h8:3'h7];
assign isSpecial = T8 == 2'b11;
assign T9 = isSpecial ? 8'b11111111 : 8'h0;
assign expOut = T7 | T9;
assign T10 = expOut[3'h7:1'h0];
assign T11 = {sign, T10};
assign T12 = expIn[4'h8:3'h6];
assign T13 = T12 == 3'b001;
assign T14 = expIn[4'h8:3'h7];
assign T15 = T14 == 2'b01;
assign T16 = T15 & exp01_isHighSubnormalIn;
assign isSubnormal = T13 | T16;
assign fractIn = in[5'h16:1'h0];
assign T17 = {1'h1, fractIn};
assign T18 = expIn[3'h4:1'h0];
assign denormShiftDist = 5'h2 - T18;
assign T19 = denormShiftDist[3'h4:1'h0];
assign subnormal_fractOut = T17 >> T19;
assign T20 = isSubnormal ? subnormal_fractOut : 23'h0;
assign T21 = expIn[3'h6];
assign isNaN = isSpecial & T21;
assign T22 = isNormal | isNaN;
assign T23 = T22 ? fractIn : 23'h0;
assign fractOut = T20 | T23;
assign T24 = fractOut[5'h16:1'h0];
assign T25 = {T11, T24};
assign out = T25;
endmodule
| 7.17714 |
module anyToFloat32 (
output [ 4:0] exceptionFlags,
input [63:0] in,
output [31:0] out,
input [ 1:0] typeOp,
input [ 1:0] roundingMode
);
wire [ 4:0] exceptionFlags_0;
wire [32:0] out_1;
wire [31:0] out_2;
assign exceptionFlags = exceptionFlags_0;
assign out = out_2;
anyToRecodedFloat32 anyToRecodedFloat32 (
.exceptionFlags(exceptionFlags_0),
.in(in),
.out(out_1),
.typeOp(typeOp),
.roundingMode(roundingMode)
);
recodedFloat32ToFloat32 recodedFloat32ToFloat32 (
.in (out_1),
.out(out_2)
);
endmodule
| 6.826584 |
module anyToRecodedFloat32 (
in,
roundingMode,
typeOp,
out,
exceptionFlags
);
parameter INT_WIDTH = 64;
parameter SHIFT_WIDTH = INT_WIDTH + 1; // Save one fraction bit.
parameter STAGES = `ceilLog2(SHIFT_WIDTH);
parameter SIG_WIDTH = 23;
parameter EXP_WIDTH = 9; // Recoded float has one more exponent bit.
parameter EXP_OFFSET = 9'h100; // Recoded offset=2048 (IEEE offset=1023)
parameter FLOAT_WIDTH = SIG_WIDTH + EXP_WIDTH + 1;
input [INT_WIDTH-1:0] in;
input [1:0] roundingMode;
input [1:0] typeOp;
output [FLOAT_WIDTH-1:0] out;
output [4:0] exceptionFlags;
wire sign;
wire [INT_WIDTH-1:0] norm_in;
wire [ 5:0] norm_count;
wire [INT_WIDTH-1:0] norm_out;
wire [ 2:0] roundBits;
wire roundInexact;
wire roundEvenOffset;
wire roundOffset;
wire [ 24:0] norm_round;
wire [EXP_WIDTH-1:0] exponent_offset;
wire [EXP_WIDTH-1:0] exponent;
// Generate the absolute value of the input.
assign sign =
(typeOp == `type_uint32) ? 1'b0 :
(typeOp == `type_int32) ? in[31] :
(typeOp == `type_uint64) ? 1'b0 :
(typeOp == `type_int64) ? in[63] :
1'bx;
assign norm_in =
(typeOp == `type_uint32) ? {32'b0, in[31:0]} :
(typeOp == `type_int32) ? {32'b0, (sign ? -in[31:0] : in[31:0])}:
(typeOp == `type_uint64) ? in :
(typeOp == `type_int64) ? (sign ? -in : in) :
64'bx;
// Normalize to generate the fractional part.
normalize64 normalizeFract (
norm_in,
norm_count,
norm_out
);
// Rounding depends on:
// norm_out[40]: The LSB of the significand
// norm_out[39]: The MSB of the extra bits to be rounded
// norm_out[38:0]: Remaining Extra bits
assign roundBits = {norm_out[40:39], (norm_out[38:0] != 39'b0)};
// Check if rounding is necessary.
assign roundInexact = (roundBits[1:0] != 2'b0);
// Determine the rounding increment, based on the rounding mode.
assign roundEvenOffset = (roundBits[1:0] == 2'b11 || roundBits[2:1] == 2'b11);
assign roundOffset =
roundingMode == `round_nearest_even ? roundEvenOffset :
roundingMode == `round_minMag ? 1'b0 :
roundingMode == `round_min ? sign & roundInexact ? 1'b1 : 1'b0 :
roundingMode == `round_max ? ~sign & roundInexact ? 1'b1 : 1'b0 :
1'bx;
// The rounded normalized significand includes the carry-out, implicit unit
// digit, and 23-bits of final significand (25 bits total).
assign norm_round = ({1'b0, norm_out[63:40]} + roundOffset);
// For the Recoded Float32:
// norm_count Exponent Recoded Exponent IEEE Exponent
// 63, msb=0 2^0 9'b000------ 8'b00000000
// 63, msb=1 2^0 9'b100000000 8'b01111111
// 62 2^1 9'b100000001 8'b10000000
// 61 2^2 9'b100000010 8'b10000001
// ...
// 1 2^62 9'b100111110 8'b10111101
// 0 2^63 9'b100111111 8'b10111110
//
// Construct the exponent from the norm_count, and increment the exponent if
// the rounding overflows (the significand will still be all zeros in this case).
assign exponent_offset = {3'b100, ~norm_count} + norm_round[24];
assign exponent = (norm_out[63] == 1'b0 && norm_count == 6'd63) ? 9'b0 : exponent_offset;
assign out = {sign, exponent, norm_round[22:0]};
assign exceptionFlags = {1'b0, 1'b0, 1'b0, 1'b0, roundInexact};
endmodule
| 7.073609 |
module anyToRecodedFloat64 (
in,
roundingMode,
typeOp,
out,
exceptionFlags
);
parameter INT_WIDTH = 64;
parameter SHIFT_WIDTH = INT_WIDTH + 1; // Save one fraction bit.
parameter STAGES = `ceilLog2(SHIFT_WIDTH);
parameter SIG_WIDTH = 52;
parameter EXP_WIDTH = 12; // Recoded float has one more exponent bit.
parameter EXP_OFFSET = 12'h800; // Recoded offset=2048 (IEEE offset=1023)
parameter FLOAT_WIDTH = SIG_WIDTH + EXP_WIDTH + 1;
input [INT_WIDTH-1:0] in;
input [1:0] roundingMode;
input [1:0] typeOp;
output [FLOAT_WIDTH-1:0] out;
output [4:0] exceptionFlags;
wire sign;
wire [INT_WIDTH-1:0] norm_in;
wire [ 5:0] norm_count;
wire [INT_WIDTH-1:0] norm_out;
wire [ 2:0] roundBits;
wire roundInexact;
wire roundEvenOffset;
wire roundOffset;
wire [ 53:0] norm_round;
wire [EXP_WIDTH-1:0] exponent_offset;
wire [EXP_WIDTH-1:0] exponent;
// Generate the absolute value of the input.
assign sign =
(typeOp == `type_uint32) ? 1'b0 :
(typeOp == `type_int32) ? in[31] :
(typeOp == `type_uint64) ? 1'b0 :
(typeOp == `type_int64) ? in[63] :
1'bx;
assign norm_in =
(typeOp == `type_uint32) ? {32'b0, in[31:0]} :
(typeOp == `type_int32) ? {32'b0, (sign ? -in[31:0] : in[31:0])}:
(typeOp == `type_uint64) ? in :
(typeOp == `type_int64) ? (sign ? -in : in) :
64'bx;
// Normalize to generate the fractional part.
normalize64 normalizeFract (
norm_in,
norm_count,
norm_out
);
// Rounding depends on:
// norm_out[11]: The LSB of the significand
// norm_out[10]: The MSB of the extra bits to be rounded
// norm_out[9:0]: Remaining Extra bits
assign roundBits = {norm_out[11:10], (norm_out[9:0] != 10'b0)};
// Check if rounding is necessary.
assign roundInexact =
(typeOp == `type_uint32) ? 1'b0 :
(typeOp == `type_int32) ? 1'b0 :
(typeOp == `type_uint64) ? roundBits[1:0] != 2'b0 :
(typeOp == `type_int64) ? roundBits[1:0] != 2'b0 :
1'bx;
// Determine the rounding increment, based on the rounding mode.
assign roundEvenOffset = (roundBits[1:0] == 2'b11 || roundBits[2:1] == 2'b11);
assign roundOffset =
roundingMode == `round_nearest_even ? roundEvenOffset :
roundingMode == `round_minMag ? 1'b0 :
roundingMode == `round_min ? sign & roundInexact ? 1'b1 : 1'b0 :
roundingMode == `round_max ? ~sign & roundInexact ? 1'b1 : 1'b0 :
1'bx;
// The rounded normalized significand includes the carry-out, implicit unit
// digit, and 52-bits of final significand (54 bits total).
assign norm_round = ({1'b0, norm_out[63:11]} + roundOffset);
// For the Recoded Float64:
// norm_count Exponent Recoded Exponent IEEE Exponent
// 63, msb=0 2^0 12'b000--------- 11'b00000000000
// 63, msb=1 2^0 12'b100000000000 11'b01111111111
// 62 2^1 12'b100000000001 11'b10000000000
// 61 2^2 12'b100000000010 11'b10000000001
// ...
// 1 2^62 12'b100000111110 11'b10000111101
// 0 2^63 12'b100000111111 11'b10000111110
//
// Construct the exponent from the norm_count, and increment the exponent if
// the rounding overflows (the significand will still be all zeros in this case).
assign exponent_offset = {6'b100000, ~norm_count} + norm_round[53];
assign exponent = (norm_out[63] == 1'b0 && norm_count == 6'd63) ? 12'b0 : exponent_offset;
assign out = {sign, exponent, norm_round[51:0]};
assign exceptionFlags = {1'b0, 1'b0, 1'b0, 1'b0, roundInexact};
endmodule
| 7.073609 |
module AO2 (
input a,
b,
c,
output w
);
wire i, j;
not #(5, 7) G2 (j, c);
nand #(10, 8) G1 (i, a, b);
nand #(10, 8) G3 (w, i, j);
endmodule
| 7.624179 |
module ao486_rst_controller (
input wire clk_sys,
input wire rst,
output reg ao486_rst,
input wire [ 1:0] address,
input wire write,
input wire [31:0] writedata
);
always @(posedge clk_sys) begin
if (rst) begin
ao486_rst <= 1;
end else begin
if (write && writedata[0] == 1'b0 && address == 4'b0000) ao486_rst <= 0;
else if (write && writedata[0] == 1'b1 && address == 4'b0000) ao486_rst <= 1;
end
end
endmodule
| 7.881611 |
module AOBUFX2 (
INP,
Z
);
input INP;
output Z;
buf U0 (Z, INP);
specify
specparam tdelay_INP_Z_01_0 = 0.01, tdelay_INP_Z_10_0 = 0.01;
(INP + => Z) = (tdelay_INP_Z_01_0, tdelay_INP_Z_10_0);
endspecify
endmodule
| 6.629566 |
module AOI (
input a,
input b,
input c,
input d,
output e,
output f,
output g
);
assign e = a && b;
assign f = c && d;
assign g = ~(e || f);
endmodule
| 6.51183 |
module AOI22 (
Y,
A0,
A1,
B0,
B1,
VDD,
VSS
);
input A0, A1, B0, B1;
output Y;
inout VDD, VSS;
assign Y = ~((A0 && A1) || (B0 && B1));
endmodule
| 7.559635 |
module AOI23 (
Y,
A0,
A1,
B0,
B1,
C0,
C1,
VDD,
VSS
);
input A0, A1, B0, B1, C0, C1;
output Y;
inout VDD, VSS;
assign Y = ~((A0 && A1) || (B0 && B1) || (C0 || C1));
endmodule
| 6.777044 |
module AOI24 (
Y,
A0,
A1,
B0,
B1,
C0,
C1,
D0,
D1,
VDD,
VSS
);
input A0, A1, B0, B1, C0, C1, D0, D1;
output Y;
inout VDD, VSS;
assign Y = ~((A0 && A1) || (B0 && B1) || (C0 && C1) || (D0 && D1));
endmodule
| 7.300116 |
module AOI32 (
Y,
A0,
A1,
A2,
B0,
B1,
B2,
VDD,
VSS
);
input A0, A1, A2, B0, B1, B2;
output Y;
inout VDD, VSS;
assign Y = ~((A0 && A1 && A2) || (B0 && B1 && B2));
endmodule
| 7.450454 |
module AOI33 (
Y,
A0,
A1,
A2,
B0,
B1,
B2,
C0,
C1,
C2,
VDD,
VSS
);
input A0, A1, A2, B0, B1, B2, C0, C1, C2;
output Y;
inout VDD, VSS;
assign Y = ~((A0 && A1 && A2) || (B0 && B1 && B2) || (C0 && C1 && C2));
endmodule
| 6.600732 |
module AOI42 (
Y,
A0,
A1,
A2,
A3,
B0,
B1,
B2,
B3,
VDD,
VSS
);
input A0, A1, A2, A3, B0, B1, B2, B3;
output Y;
inout VDD, VSS;
assign Y = ~((A0 && A1 && A2 && A3) || (B0 && B1 && B2 && B3));
endmodule
| 7.019812 |
module AOI43 (
Y,
A0,
A1,
A2,
A3,
B0,
B1,
B2,
B3,
C0,
C1,
C2,
C3,
VDD,
VSS
);
input A0, A1, A2, A3, B0, B1, B2, B3, C0, C1, C2, C3;
output Y;
inout VDD, VSS;
assign Y = ~((A0 && A1 && A2 && A3) || (B0 && B1 && B2 && B3) || (C0 && C1 && C2 && C3));
endmodule
| 6.85537 |
module AOI44 (
Y,
A0,
A1,
A2,
A3,
B0,
B1,
B2,
B3,
C0,
C1,
C2,
C3,
D0,
D1,
D2,
D3,
VDD,
VSS
);
input A0, A1, A2, A3, B0, B1, B2, B3, C0, C1, C2, C3, D0, D1, D2, D3;
output Y;
inout VDD, VSS;
assign Y=~((A0 && A1 && A2 && A3) || (B0 && B1 && B2 && B3) || (C0 && C1 && C2 && C3) || (D0 && D1 && D2 && D3));
endmodule
| 6.680585 |
module AOINVX1 (
INP,
ZN
);
input INP;
output ZN;
not U0 (ZN, INP);
specify
specparam tdelay_INP_ZN_01_0 = 0.01, tdelay_INP_ZN_10_0 = 0.01;
(INP - => ZN) = (tdelay_INP_ZN_01_0, tdelay_INP_ZN_10_0);
endspecify
endmodule
| 7.137007 |
module AOINVX2 (
INP,
ZN
);
input INP;
output ZN;
not U0 (ZN, INP);
specify
specparam tdelay_INP_ZN_01_0 = 0.01, tdelay_INP_ZN_10_0 = 0.01;
(INP - => ZN) = (tdelay_INP_ZN_01_0, tdelay_INP_ZN_10_0);
endspecify
endmodule
| 7.814333 |
module AOINVX4 (
INP,
ZN
);
input INP;
output ZN;
not U0 (ZN, INP);
specify
specparam tdelay_INP_ZN_01_0 = 0.01, tdelay_INP_ZN_10_0 = 0.01;
(INP - => ZN) = (tdelay_INP_ZN_01_0, tdelay_INP_ZN_10_0);
endspecify
endmodule
| 6.928771 |
module AOI_logic (
and1,
or1,
not1,
in
);
input [1:0] in;
output and1;
output or1;
output not1;
wire a;
wire o;
wire i;
and gate1 (a, in[0], in[1]);
or gate2 (o, in[0], in[1]);
not gate3 (i, in[0]);
endmodule
| 7.597809 |
module AOI_logic_tb;
reg [1:0] in;
wire and1, or1, not1;
AOI_logic uut (
and1,
or1,
not1,
in
);
initial begin
$dumpfile("AOI_logic_tb.vcd");
$dumpvars(0, AOI_logic_tb);
in[0] = 0;
in[1] = 0;
#10;
in[0] = 0;
in[1] = 1;
#10;
in[0] = 1;
in[1] = 0;
#10;
in[0] = 1;
in[1] = 1;
#10;
$display("Completed");
end
endmodule
| 6.594818 |
module aoOCS_tb ();
// inputs
reg clk;
reg rst_n;
wire sram_clk;
wire [18:0] sram_address;
wire sram_oe_n;
wire sram_writeen_n;
wire [3:0] sram_byteen_n;
wire [31:0] sram_data_o;
inout [35:0] sram_data;
assign sram_data = (sram_oe_n == 1'b0) ? {4'b0, sram_data_o} : 36'bZ;
wire sram_advance_n;
wire sram_adsc_n;
wire sd_clk;
wire sd_cmd;
wire sd_dat;
reg [2:0] ext_int;
aoOCS aoOCS_inst (
.clk_50(clk),
.reset_ext_n(rst_n),
// ssram interface
.ssram_address(sram_address), //[18:0]
.ssram_oe_n(sram_oe_n),
.ssram_writeen_n(sram_writeen_n),
.ssram_byteen_n(sram_byteen_n), //[3:0]
.ssram_data(sram_data), //[35:0] inout
.ssram_clk(sram_clk),
.ssram_globalw_n(),
.ssram_advance_n(sram_advance_n),
.ssram_adsp_n(),
.ssram_adsc_n(sram_adsc_n),
.ssram_ce1_n(),
.ssram_ce2(),
.ssram_ce3_n(),
// sd interface
.sd_clk_o (sd_clk),
.sd_cmd_io(sd_cmd), //inout
.sd_dat_io(sd_dat), //inout
// serial interface
.uart_rxd(1'b0),
.uart_rts(1'b0),
.uart_txd(),
.uart_cts(),
// vga output
.vga_r(), //[9:0]
.vga_g(), //[9:0]
.vga_b(), //[9:0]
.vga_blank_n(),
.vga_sync_n(),
.vga_clock(),
.vga_hsync(),
.vga_vsync(),
// hex output
.hex0(),
.hex1(),
.hex2(),
.hex3(),
.hex4(),
.hex5(),
.hex6(),
.hex7(),
.hex_switch(1'b0),
// debug
.sd_debug(),
.pc_debug(),
.sd_error(),
.halt_switch(1'b0),
.key0(1'b1),
.blitter_switch(1'b0),
.floppy_debug()
);
/*
model_sd model_sd_inst(
.reset_n(rst_n),
.sd_clk(sd_clk),
.sd_cmd_io(sd_cmd),
.sd_dat_io(sd_dat)
);
*/
initial begin
clk = 1'b0;
forever #2 clk = ~clk;
end
reg [31:0] rom[0:65535];
reg [31:0] ram[0:458751];
integer f;
integer r;
wire [18:0] sram_address_final;
assign sram_address_final = {sram_address[18:2], sram_address[1:0] ^ sram_burst[1:0]};
wire [15:0] rom_index;
assign rom_index = (sram_address_final - 458752);
assign sram_data_o = (sram_address_final < 458752) ? ram[sram_address_final] : rom[rom_index];
reg [1:0] sram_burst;
always @(posedge sram_clk) begin
if (sram_adsc_n == 1'b0) sram_burst = 2'd0;
else if (sram_advance_n == 1'b0) sram_burst = sram_burst + 2'd1;
end
always @(posedge sram_clk) begin
if (sram_writeen_n == 1'b0 && {sram_address, 2'b00} < 1835008 && sram_byteen_n[0] == 1'b0)
ram[sram_address_final][7:0] = sram_data[7:0];
if (sram_writeen_n == 1'b0 && {sram_address, 2'b00} < 1835008 && sram_byteen_n[1] == 1'b0)
ram[sram_address_final][15:8] = sram_data[15:8];
if (sram_writeen_n == 1'b0 && {sram_address, 2'b00} < 1835008 && sram_byteen_n[2] == 1'b0)
ram[sram_address_final][23:16] = sram_data[23:16];
if (sram_writeen_n == 1'b0 && {sram_address, 2'b00} < 1835008 && sram_byteen_n[3] == 1'b0)
ram[sram_address_final][31:24] = sram_data[31:24];
if (sram_writeen_n == 1'b0 && {sram_address, 2'b00} < 1835008 && sram_byteen_n[3:0] != 4'b1111)
$display("Written: %x <- %x, sel: %x", sram_address_final, sram_data, sram_byteen_n);
end
initial begin
f = $fopen("/home/alek/temp/e-uae-0.8.29-WIP4/build/bin/kick12_a.rom", "rb");
r = $fread(rom, f);
$display(r);
$fclose(f);
for (f = 0; f < 458752; f = f + 1) ram[f] = 32'd0;
$display("%x", rom[54]);
$display("%x", rom[55]);
rom[54] = 32'h203c0000; //was 203c0002
rom[55] = 32'h00045380; //was 00005380
end
//initial begin
// forever begin
// #2 aoOCS_inst.control_inst.pc_switch = 32'd0;
// aoOCS_inst.control_inst.management_mode = 1'd0;
// end
//end
initial begin
$dumpfile("aoOCS_tb.vcd");
$dumpvars(0);
$dumpon();
ext_int = 3'd0;
rst_n = 1'b0;
#10 rst_n = 1'b1;
#580 ext_int = 3'd3;
#100000 $dumpoff();
$finish();
end
endmodule
| 6.936619 |
module aopac01_3v3 ( OUT, EN, IB, INN, INP, VDDA, VSSA );
input IB;
input EN;
input VSSA;
input VDDA;
input INN;
input INP;
output OUT;
wire real IB, VSSA, VDDA, INN, INP;
reg real OUT;
wire real outval, nextout;
real NaN;
initial begin
NaN = 0.0 / 0.0;
OUT <= 0.0;
end
// Gain and poles are more or less randomly assigned here.
// Updates are restricted to exact (1ns) intervals so that
// equations remain valid for the same parameters.
assign outval = 100.0 * (INP - INN);
assign nextout = 0.999 * OUT + 0.001 * outval;
always @(INN or INP or EN) begin
if (EN == 1'b1) begin
#1 OUT <= 0.99 * OUT + 0.01 * outval;
if (nextout > VDDA) begin
#1 OUT <= VDDA;
end else if (nextout < VSSA) begin
#1 OUT <= VSSA;
end else begin
#1 OUT <= nextout;
end
end else if (EN == 1'b0) begin
OUT <= 0.0;
end else begin
OUT <= NaN;
end
end
endmodule
| 7.064295 |
module APB_I2C (
//APB Inputs
input wire PCLK,
input wire PRESETn,
input wire PWRITE,
input wire [31:0] PWDATA,
input wire [31:0] PADDR,
input wire PENABLE,
input PSEL,
//APB Outputs
output wire PREADY,
output wire [31:0] PRDATA,
// i2c Ports
input wire scl_i, // SCL-line input
output wire scl_o, // SCL-line output (always 1'b0)
output wire scl_oen_o, // SCL-line output enable (active low)
input wire sda_i, // SDA-line input
output wire sda_o, // SDA-line output (always 1'b0)
output wire sda_oen_o // SDA-line output enable (active low)
);
assign PREADY = 1'b1; //always ready
wire [7:0] io_do;
wire io_we = PENABLE & PWRITE & PREADY & PSEL;
wire io_re = PENABLE & ~PWRITE & PREADY & PSEL;
wire i2c_irq;
i2c_master i2c (
.sys_clk(PCLK),
.sys_rst(~PRESETn),
//
.io_a(PADDR[7:2]),
.io_di(PWDATA[7:0]),
.io_do(io_do),
.io_re(io_re),
.io_we(io_we),
//
.i2c_irq(i2c_irq),
//
.scl_i(scl_i), // SCL-line input
.scl_o(scl_o), // SCL-line output (always 1'b0)
.scl_oen_o(scl_oen_o), // SCL-line output enable (active low)
.sda_i(sda_i), // SDA-line input
.sda_o(sda_o), // SDA-line output (always 1'b0)
.sda_oen_o(sda_oen_o) // SDA-line output enable (active low)
);
assign PRDATA[31:0] = io_do; //I2C_DATA_REG;
endmodule
| 7.853387 |
module apb2iob #(
parameter APB_ADDR_W = 21, // APB address bus width in bits
parameter APB_DATA_W = 21, // APB data bus width in bits
parameter ADDR_W = APB_ADDR_W, // IOb address bus width in bits
parameter DATA_W = APB_DATA_W // IOb data bus width in bits
) (
// Global signals
`include "clk_en_rst_s_port.vs"
// APB slave interface
`include "apb_s_port.vs"
// IOb master interface
`include "iob_m_port.vs"
);
wire apb_ready_nxt;
iob_reg #(
.DATA_W (1),
.RST_VAL(1'b0)
) apb_ready_reg_inst (
`include "clk_en_rst_s_s_portmap.vs"
.data_i(apb_ready_nxt),
.data_o(apb_ready_o)
);
assign apb_ready_nxt = ~apb_ready_o & iob_ready_i & apb_sel_i & apb_enable_i;
assign apb_rdata_o = iob_rdata_i;
assign iob_avalid_o = apb_sel_i & apb_enable_i & ~apb_ready_o;
assign iob_addr_o = apb_addr_i;
assign iob_wdata_o = apb_wdata_i;
assign iob_wstrb_o = apb_wstrb_i;
endmodule
| 7.210421 |
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