code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module TopLevel (
ain[4:0],
bin[4:0],
cin[4:0],
extendeda[7:0],
extendedb[7:0],
extendedcin[7:0],
sumf[8:0],
coutf[8:0],
carrysaveoutput[8:0]
);
input [4:0] ain;
input [4:0] bin;
input [4:0] cin;
output [8:0] carrysaveoutput;
output [7:0] extendeda;
output [7:0] extendedb... | 8.03714 |
module carrysave_8 (
a[7:0],
b[7:0],
c[7:0],
sum[8:0],
cout[8:0],
addition[8:0]
);
input [7:0] a;
input [7:0] b;
input [7:0] c;
output [8:0] sum;
output [8:0] cout;
output [8:0] addition;
FA FA0 (
a[0],
b[0],
c[0],
sum[0],
cout[0]
);
FA FA1 (
... | 7.576805 |
module HA (
in1,
in2,
sum,
carry
);
input in1, in2;
output sum, carry;
assign sum = in1 ^ in2;
assign carry = in1 & in2;
endmodule
| 8.480391 |
module TopLevel_testbench;
reg [4:0] ina;
reg [4:0] inb;
reg [4:0] inc;
wire [7:0] aextended;
wire [7:0] bextended;
wire [7:0] cinextended;
wire [8:0] fsum;
wire [8:0] fcout;
wire [8:0] outaddition;
TopLevel stage1 (
ina[4:0],
inb[4:0],
inc[4:0],
aextended[7:0],
bext... | 6.875707 |
module carrysave_4is2 (
input [4:0] in,
output c0,
output c1,
output sum
);
wire connection;
FullAdder FA0 (
in[0],
in[1],
in[2],
connection,
c0
);
FullAdder FA1 (
connection,
in[4],
in[3],
sum,
c1
);
endmodule
| 6.660827 |
module FullAdder (
input in1,
input in2,
input cin,
output sum,
output cout
);
assign sum = (in1 ^ in2) ^ cin;
assign cout = (in1 & in2) | (cin & (in1 ^ in2));
endmodule
| 7.610141 |
module carrysave_4is2_tb;
reg [4:0] in;
wire c0, c1, sum;
carrysave_4is2 carrysave_tb (
in[4:0],
c0,
c1,
sum
);
initial begin
$monitor($time, "input is %b \t c0 is %b \t c1 is %b \t sum is %b \n", in[4:0], c0, c1, sum);
#50;
in[4:0] = 10110;
#50 in[4:0] = 00000;
#50... | 6.660827 |
module stage1_3is2 (
input [5:0] in1,
input [5:0] in2,
input [5:0] in3,
output [5:0] cout_stage1,
output [5:0] sum_stage1
);
FullAdder FA2 (
in1[0],
in2[0],
in3[0],
sum_stage1[0],
cout_stage1[0]
);
FullAdder FA3 (
in1[1],
in2[1],
in3[1],
... | 7.405017 |
module stage2_3is2 (
input [5:0] in4,
input [5:0] in5,
input [5:0] in6,
output [5:0] cout_stage2,
output [5:0] sum_stage2
);
FullAdder FA6 (
in4[0],
in5[0],
in6[0],
sum_stage2[0],
cout_stage2[0]
);
FullAdder FA7 (
in4[1],
in5[1],
in6[1],
... | 6.971046 |
module stage3_4is2 (
input [5:0] subin1,
input [5:0] subin2,
input [5:0] subin3,
input [5:0] subin4,
output [5:0] sum_stage3,
output [5:0] cout_stage3
//output carry
);
wire connection1, connection2, connection3, connection4, connection5;
carrysave_4is2 CS1 (
({1'b0, 1'b0, subi... | 7.405799 |
module Top (
input [3:0] i1,
input [3:0] i2,
input [3:0] i3,
input [3:0] i4,
input [3:0] i5,
input [3:0] i6,
output [5:0] answer
);
wire [5:0] cout_S1;
wire [5:0] sum_S1;
wire [5:0] cout_S2;
wire [5:0] sum_S2;
wire [5:0] sum_S3;
wire [5:0] cout_S3;
//wire carry_S3;
stag... | 6.64497 |
module carrysave_4is2 (
input [4:0] in,
output c0,
output c1,
output sum
);
wire connection;
FullAdder FA0 (
in[0],
in[1],
in[2],
connection,
c0
);
FullAdder FA1 (
connection,
in[4],
in[3],
sum,
c1
);
endmodule
| 6.660827 |
module FullAdder (
input in1,
input in2,
input cin,
output sum,
output cout
);
assign sum = (in1 ^ in2) ^ cin;
assign cout = (in1 & in2) | (cin & (in1 ^ in2));
endmodule
| 7.610141 |
module carrysave_4is2 (
input [4:0] in,
output c0,
output c1,
output sum
);
wire connection;
FullAdder FA0 (
in[0],
in[1],
in[2],
connection,
c0
);
FullAdder FA1 (
connection,
in[4],
in[3],
sum,
c1
);
endmodule
| 6.660827 |
module FullAdder (
input in1,
input in2,
input cin,
output sum,
output cout
);
assign sum = (in1 ^ in2) ^ cin;
assign cout = (in1 & in2) | (cin & (in1 ^ in2));
endmodule
| 7.610141 |
module TOP_testbench;
reg [10:0] inps;
wire [ 4:0] add;
Top instance1 (
inps[10:0],
add[4:0]
);
initial begin
$monitor($time, "inps = %b \t output = %b \n", inps[10:0], add[4:0]);
#10;
inps[10:0] = 11'b00000011111;
#50;
inps[10:0] = 11'b11000011111;
#50;
inps[10:0] = ... | 6.517038 |
module abro (
input clk,
input reset,
input a,
input b,
output z
);
parameter IDLE = 0, SA = 1, SB = 2, SAB = 3;
reg [1:0] cur_state, next_state;
assign z = cur_state == SAB ? 1 : 0;
always @(posedge clk) begin
if (reset) cur_state <= IDLE;
else cur_state <= next_state;
end... | 7.130853 |
module advshift (
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q
);
always @(posedge clk) begin
if (load) begin
q <= data;
end else if (ena) begin
case (amount)
0: q <= {q[62:0], 1'b0};
1: q <= {q[55:0], 8'b0};... | 7.037838 |
module that implements an AND gate
module and_gate(
input a,
input b,
output out );
assign out = a && b;
endmodule
| 8.896332 |
module half_adder (
input a,
b,
output cout,
sum
);
assign sum = a ^ b;
assign cout = a & b;
endmodule
| 6.966406 |
module lfsr (
input clk,
input reset,
output [4:0] q
);
reg [4:0] r_reg;
wire [4:0] r_next;
wire feedback_value;
always @(posedge clk, posedge reset) begin
if (reset) begin
// set initial value to 1
r_reg <= 1;
end else if (clk == 1'b1) r_reg <= r_next;
end
assign feedback... | 6.570207 |
module MODULENAME (
parameter WIDTH = 5
)(
input clk,
input rst_n,
input butten,
input trigger,
input [WIDTH-1 : 0] others,
output red,
output yellow,
output green,
output out_butten
)
always @(posedge clk or negedge rst_n) begin
if(rst_n) cnt <= 10'd0;
else if(rst_cnt)
... | 7.350224 |
module that implements an AND gate
module mux(
input [4:0] a, b,
input sel,
output [4:0] out );
assign out = sel?b:a;
endmodule
| 8.896332 |
module priority_encoder (
input [2:0] in,
output reg [1:0] pos
);
always @(*) begin
if (in[0] == 1'b1) pos = 0;
else if (in[1] == 1'b1) pos = 1;
else if (in[2] == 1'b1) pos = 2;
else pos = 0;
end
endmodule
| 7.114361 |
module
module ram #( parameter ADDR_WIDTH=6, parameter DATA_WIDTH=8)
(input [DATA_WIDTH-1:0] data, input [ADDR_WIDTH-1:0] addr, input we, clk, output [DATA_WIDTH-1:0] q);
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
// when we is high, write data to ram at address addr
// assign the ram value at address addr to q
alw... | 7.233831 |
module left_rotate (
input clk,
input reset,
input [2:0] amount,
input [7:0] data,
input load,
output reg [7:0] out
);
// when load is high, load data to out
// shift left and rotate the register out by amount bits
always @(posedge clk) begin
if (load) out <= data;
else begin
... | 6.527094 |
module simple_fsm (
input clk,
input reset,
input in,
output out
);
reg present_state, next_state;
// In state 0, if in=1, stay in state 0. In state 0, if in=0, go to state 1
// In state 1, if in=1, stay in state 1. In state 1, if in=0, go to state 0
// out=1 in state 0 and out=0 in state 1
... | 8.56957 |
module with one input and one output that behaves like a wire
module wire_assign( input in, output out );
// assign out to in
assign out = in;
endmodule
| 7.695416 |
module ANS_FIFO (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input aclr;
input [135:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [135:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_... | 6.630796 |
module ANS_MEM #(
parameter ID_WIDTH = 4,
ADDR_WIDTH = 32,
DATA_WIDTH = 16
);
parameter DRAM_p_r = "../00_TESTBED/DRAM/data_file.dat";
reg [7:0] DRAM_r[0:8*1024-1];
initial $readmemh(DRAM_p_r, DRAM_r);
endmodule
| 8.214137 |
module anti_bounce_reset (
input clk,
input button,
output reg stabilized_button
);
//CAREFULL
reg [19:0] clk_count=1'b0; //(Depending on the FPGA system used.) For 50mhz clock (period=2e-8) and for a 20ms delay, 20bits give the required 2^20cycles.
wire check; //ClockDividing using AND: When clk_hits... | 6.519225 |
module antares_add (
input [31:0] a,
input [31:0] b,
output [31:0] c
);
assign c = a + b;
endmodule
| 7.424336 |
module antares_branch_unit (
input [ 5:0] opcode, // Instruction opcode
input [31:0] id_pc_add4, // Instruction address + 4
input [31:0] id_data_rs, // Data from R0
input [31:0] id_data_rt, // Data from R1
input [25:0] op_imm26, ... | 7.549423 |
module antares_divider (
input clk,
input rst,
input op_divs,
input op_divu,
input [31:0] dividend,
input [31:0] divisor,
output [31:0] quotient,
output [31:0] remainder,
output div_stall
);
//-----------------------------------------------... | 6.657417 |
module antares_memwb_register (
input clk, // main clock
input rst, // main reset
input [31:0] mem_read_data, // data from Memory
input [31:0] mem_alu_data, // data from ALU
input [ 4:0] mem_gpr_wa, ... | 7.414291 |
module antares_mux_2_1 #(
parameter WIDTH = 32
) (
input [WIDTH-1:0] in0,
input [WIDTH-1:0] in1,
input select,
output reg [WIDTH-1:0] out
);
always @( /*AUTOSENSE*/ in0 or in1 or select) begin
case (select)
1'b0: out = in0;
1'b1: out = in1;
endcase ... | 7.671781 |
module antares_mux_4_1 #(
parameter WIDTH = 32
) (
input [ 1:0] select,
input [WIDTH-1:0] in0,
input [WIDTH-1:0] in1,
input [WIDTH-1:0] in2,
input [WIDTH-1:0] in3,
output reg [WIDTH-1:0] out
);
always @( /*AUTOSENSE*/ in0 or in1 or in2 or in3 or select) begi... | 7.530474 |
module antares_pc_register (
input clk,
input rst,
input [31:0] if_new_pc,
input if_stall,
output reg [31:0] if_pc
);
always @(posedge clk) begin
if_pc <= (rst) ? `ANTARES_VECTOR_BASE_RESET : ((if_stall) ? if_pc : if_new_pc);
end
endmodule
| 6.544672 |
module antares_reg_file (
input clk,
input [ 4:0] gpr_ra_a,
input [ 4:0] gpr_ra_b,
input [ 4:0] gpr_wa,
input [31:0] gpr_wd,
input gpr_we,
output [31:0] gpr_rd_a,
output [31:0] gpr_rd_b
);
// Register file of 32 32-bit registers. Register 0 is always 0
reg [31:0]... | 7.638787 |
module anti_bounce (
input clk,
input reset,
input button,
output reg stabilized_button
);
//carefull
reg [19:0] clk_count=1'b0; //(Depending on the FPGA system used.) For 50mhz clock (period=2e-8) and for a 20ms delay, 20bits give the required 2^20cycles.
wire check; ////ClockDividing using AND:... | 6.764266 |
module adder_block #(
parameter block_width = 4
) (
input wire [block_width-1 : 0] a,
b,
wire cin,
output wire [block_width-1 : 0] sum,
wire cout
);
wire [block_width : 0] c;
wire [block_width-1 : 0] p, g, g_all;
wire p_all;
assign... | 9.11153 |
module anticipated_carry_adder #(
parameter block_width = 4,
parameter width = 32
) (
input wire [width-1 : 0] a,
b,
wire cin,
output wire [width-1 : 0] sum,
wire cout
);
localparam block_num = width / block_width;
wire [block_num : 0] c;
ass... | 8.775118 |
module AntiJitter #(
parameter WIDTH = 20,
parameter INIT = 1'b0
) (
input clk,
input I,
output reg O = INIT
);
reg [WIDTH-1:0] cnt = {WIDTH{INIT}};
always @(posedge clk) begin
if (I) begin
if (&cnt) O <= 1'b1;
else cnt <= cnt + 1'b1;
end else begin
if (|cnt) cnt <= c... | 7.202376 |
module AntiLog2
/*
A fast base-2 anti-logarithm function, 10 bits in, 24 bits out.
Designed and coded by: Michael Dunn, http://www.cantares.on.ca/
Executes every cycle, with a latency of 2.
The input and output have binary points: In: xxxx.yyyy_yy; Out: xxxx_xxxx_xxxx_xxxx.yyyy_yyyy
License: Free to use & modify, b... | 6.558796 |
module: AntiTheftModule
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module AntiTheftTest;
// Inputs
reg clock;
reg reset;
reg ignition;
reg driver_door;
reg passenger_door;
reg ... | 7.121774 |
module anti_jitter (
input wire clk, // main clock
input wire rst, // synchronous reset
input wire sig_i, // input signal with jitter noises
output reg sig_o = INIT_VALUE // output signal without jitter noises
);
`include "function.vh"
parameter CLK_FREQ = 100, // main clock frequency in MHz
... | 7.883053 |
module anti_jitter_combined (
input clk,
input [15:0] sw,
input [3:0] btn_y,
output [15:0] switch_buf,
output [3:0] btn_y_buf
);
localparam
CLK_FREQ_SYS = 50,
CLK_FREQ_BUS = 25,
CLK_FREQ_CPU = 50,
CLK_FREQ_MEM = 50,
CLK_FREQ_DEV = 50;
`ifndef SIMULATING
anti_jitter #(
.CLK_FREQ... | 7.000978 |
module AsyncResetRegVec_w1_i0 (
input clock,
input reset,
input io_d,
output io_q
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
AsyncResetReg reg_0 (
.rst(reg_0_rst),
.clk(reg_0_clk),
.en (reg_0_en),
.q (reg_0_q),
.d (reg_0_d... | 6.68936 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0 (
input clock,
input reset,
input io_d,
output io_q
);
wire sync_0_clock;
wire sync_0_reset;
wire sync_0_io_d;
wire sync_0_io_q;
wire sync_1_clock;
wire sync_1_reset;
wire sync_1_io_d;
wire sync_1_io_q;
wire sync_2_clock;
wire sync_2_... | 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d4_i0 (
input clock,
input reset,
output io_q
);
wire sync_0_clock;
wire sync_0_reset;
wire sync_0_io_d;
wire sync_0_io_q;
wire sync_1_clock;
wire sync_1_reset;
wire sync_1_io_d;
wire sync_1_io_q;
wire sync_2_clock;
wire sync_2_reset;
wire syn... | 6.605499 |
module AsyncValidSync (
input clock,
input reset,
output io_out
);
wire source_valid_clock;
wire source_valid_reset;
wire source_valid_io_q;
wire _T_5;
AsyncResetSynchronizerShiftReg_w1_d4_i0 source_valid (
.clock(source_valid_clock),
.reset(source_valid_reset),
.io_q (source_v... | 6.70336 |
module AsyncResetSynchronizerShiftReg_w1_d1_i0 (
input clock,
input reset,
input io_d,
output io_q
);
wire sync_0_clock;
wire sync_0_reset;
wire sync_0_io_d;
wire sync_0_io_q;
AsyncResetRegVec_w1_i0 sync_0 (
.clock(sync_0_clock),
.reset(sync_0_reset),
.io_d (sync_0_io_d),
... | 6.605499 |
module AsyncValidSync_1 (
input clock,
input reset,
input io_in,
output io_out
);
wire sink_extend_clock;
wire sink_extend_reset;
wire sink_extend_io_d;
wire sink_extend_io_q;
wire _T_5;
AsyncResetSynchronizerShiftReg_w1_d1_i0 sink_extend (
.clock(sink_extend_clock),
.reset(si... | 6.70336 |
module AsyncValidSync_2 (
input clock,
input reset,
input io_in,
output io_out
);
wire sink_valid_clock;
wire sink_valid_reset;
wire sink_valid_io_d;
wire sink_valid_io_q;
wire _T_5;
AsyncResetSynchronizerShiftReg_w1_d3_i0 sink_valid (
.clock(sink_valid_clock),
.reset(sink_val... | 6.70336 |
module SynchronizerShiftReg_w42_d1 (
input clock,
input [41:0] io_d,
output [41:0] io_q
);
reg [41:0] sync_0;
reg [63:0] _RAND_0;
assign io_q = sync_0;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 =... | 6.820992 |
module AsyncValidSync_3 (
input clock,
input reset,
output io_out
);
wire sink_valid_clock;
wire sink_valid_reset;
wire sink_valid_io_q;
wire _T_5;
AsyncResetSynchronizerShiftReg_w1_d4_i0 sink_valid (
.clock(sink_valid_clock),
.reset(sink_valid_reset),
.io_q (sink_valid_io_q)
... | 6.70336 |
module AsyncValidSync_4 (
input clock,
input reset,
input io_in,
output io_out
);
wire source_extend_clock;
wire source_extend_reset;
wire source_extend_io_d;
wire source_extend_io_q;
wire _T_5;
AsyncResetSynchronizerShiftReg_w1_d1_i0 source_extend (
.clock(source_extend_clock),
... | 6.70336 |
module AsyncValidSync_5 (
input clock,
input reset,
input io_in,
output io_out
);
wire source_valid_clock;
wire source_valid_reset;
wire source_valid_io_d;
wire source_valid_io_q;
wire _T_5;
AsyncResetSynchronizerShiftReg_w1_d3_i0 source_valid (
.clock(source_valid_clock),
.re... | 6.70336 |
module SynchronizerShiftReg_w54_d1 (
input clock,
input [53:0] io_d,
output [53:0] io_q
);
reg [53:0] sync_0;
reg [63:0] _RAND_0;
assign io_q = sync_0;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 =... | 6.820992 |
module SynchronizerShiftReg_w11_d1 (
input clock,
input [10:0] io_d,
output [10:0] io_q
);
reg [10:0] sync_0;
reg [31:0] _RAND_0;
assign io_q = sync_0;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 =... | 6.820992 |
module AMOALU (
input [ 3:0] io_mask,
input [ 4:0] io_cmd,
input [31:0] io_lhs,
input [31:0] io_rhs,
output [31:0] io_out
);
wire _T_8;
wire _T_10;
wire max;
wire _T_12;
wire _T_14;
wire min;
wire add;
wire _T_17;
wire _T_19;
wire logic_and;
wire _T_21;
wire logic_xor;
... | 8.467919 |
module BreakpointUnit (
input io_status_debug,
input io_bp_0_control_action,
input [ 1:0] io_bp_0_control_tmatch,
input io_bp_0_control_x,
input io_bp_0_control_w,
input io_bp_0_control_r,
input [31:0] io_bp_0_address,
input [31:0] io_pc,
in... | 8.021329 |
module SynchronizerShiftReg_w1_d3 (
input clock,
input io_d,
output io_q
);
reg sync_0;
reg [31:0] _RAND_0;
reg sync_1;
reg [31:0] _RAND_1;
reg sync_2;
reg [31:0] _RAND_2;
assign io_q = sync_0;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`en... | 6.820992 |
module IntXbar_2 (
input auto_int_in_0_0,
input auto_int_in_0_1,
output auto_int_out_0,
output auto_int_out_1
);
wire _T_5_0;
wire _T_5_1;
wire _T_20_0;
wire _T_20_1;
assign auto_int_out_0 = _T_20_0;
assign auto_int_out_1 = _T_20_1;
assign _T_5_0 = auto_int_in_0_0;
assign _T_5_1 = auto... | 7.94893 |
module AsyncResetRegVec_w4_i15 (
input clock,
input reset,
input [3:0] io_d,
output [3:0] io_q
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
wire reg_1_rst;
wire reg_1_clk;
wire reg_1_en;
wire reg_1_q;
wire reg_1_d;
wire reg_2_rst;
w... | 6.68936 |
module anton_neopixel_apb_top #(
// number of bytes counting from zero, so the size is BUFFER_END+1, maximum
// 8192 bytes (8192 pixels in 8bit mode and 2048 pixels in 32bit mode), which should have ~4Hz refresh
parameter BUFFER_END = `BUFFER_END_DEFAULT, // read anton_common.vh
parameter VIRTUAL_END... | 7.450523 |
module anton_neopixel_module #(
parameter BUFFER_END = `BUFFER_END_DEFAULT, // read anton_common.vh
parameter VIRTUAL_END = `BUFFER_END_DEFAULT, // read anton_common.vh
parameter RESET_DELAY = `RESET_DELAY_DEFAULT
) (
input clk6_4mhz,
input syncStart,
output neoData,
output neoState,
... | 7.450523 |
module anton_neopixel_stream #(
parameter BUFFER_END = `BUFFER_END_DEFAULT, // read anton_common.vh
localparam BUFFER_BITS =
`CLOG2(BUFFER_END + 1) // minimum required amount of bits to store the BUFFER_END
) (
input [7:0] pixelByte,
input state,
input [2:0] pixelBitIx, // 0 - 7 to co... | 7.450523 |
module anton_ram_2port_asymmetric #(
parameter BUFFER_END = `BUFFER_END_DEFAULT, // read anton_common.vh
parameter BUFFER_WIDTH_READ = 16,
parameter BUFFER_WIDTH_WRITE = 8,
localparam BUFFER_BITS =
`CLOG2(BUFFER_END + 1) // minimum required amount of bits to store the BUFFER_END
) (
input clk,... | 7.228175 |
module anton_ram_2port_symmetric #(
parameter BUFFER_END = `BUFFER_END_DEFAULT, // read anton_common.vh
parameter BUFFER_WIDTH = 8,
localparam BUFFER_BITS =
`CLOG2(BUFFER_END + 1) // minimum required amount of bits to store the BUFFER_END
) (
input clk,
input [ BUFFER_BITS-1:0] rAddr,
ou... | 7.228175 |
module ant #(
parameter N = 16,
M = 64,
WIDTH = 16
) (
input clk,
input reset,
input [N*M-1:0] adjacency,
input [N*WIDTH-1:0] weights,
input [1:0] id,
input [5:0] query,
input [WIDTH+5:0] response, //{data,page_id},get response from noc
output reg [5:0] request, //send req... | 7.11283 |
module pageRank #(
parameter M = 64,
WIDTH = 16
) (
input clk,
input reset,
input [M*M-1:0] adj,
input [M*WIDTH-1:0] nodeWeight,
output [10*WIDTH-1:0] top10Vals,
output [10*6-1:0] top10IDs,
output wire [WIDTH-1:0] nodeVal0,
output wire [WIDTH-1:0] nodeVal16,
output wire [WIDT... | 7.537287 |
module Anubis_SBox (
input [7:0] idat,
output [7:0] odat
);
wire [7:0] a, b, c, d;
// layer 1
Anubis_PBox pbox1 (
.idat(idat[7:4]),
.odat(a[7:4])
);
Anubis_QBox qbox1 (
.idat(idat[3:0]),
.odat(a[3:0])
);
// 2-bit shuffle
assign b[3:0] = {a[5:4], a[1:0]};
assign b[7:... | 6.518908 |
module the implementation
// Uses modules: transmit_top.v, receive_top.v, anubis.v
// Board: BASYS3 By Digilent
//------------------------------------------------------------------
module anubis_wrapper(
input wire clk_w5, // onboard 100 Mhz clock (W5 pin)
input wire reset_b, // onboard reset (push button U18... | 7.086096 |
module anyToRecodedFloat32 (
output [ 4:0] exceptionFlags,
input [63:0] in,
output [32:0] out,
input [ 1:0] typeOp,
input [ 1:0] roundingMode
);
wire [ 0:0] T2;
wire [31:0] T3;
wire [63:0] T4;
wire [ 0:0] T5;
wire [ 0:0] T6;
wire [ 0:0] T7;
wire [ 0:0] T8;
wire [ 0:0] T9;
wire ... | 7.073609 |
module recodedFloat32ToFloat32 (
input [32:0] in,
output [31:0] out
);
wire [ 0:0] sign;
wire [ 8:0] expIn;
wire [ 1:0] T0;
wire [ 0:0] T1;
wire [ 6:0] T2;
wire [ 0:0] exp01_isHighSubnormalIn;
wire [ 0:0] T3;
wire [ 0:0] T4;
wire [ 1:0] T5;
wire [ 0:0] T6;
wire [ 0:0] isNormal;
wire [ ... | 7.17714 |
module anyToFloat32 (
output [ 4:0] exceptionFlags,
input [63:0] in,
output [31:0] out,
input [ 1:0] typeOp,
input [ 1:0] roundingMode
);
wire [ 4:0] exceptionFlags_0;
wire [32:0] out_1;
wire [31:0] out_2;
assign exceptionFlags = exceptionFlags_0;
assign out = out_2;
anyToRecodedFlo... | 6.826584 |
module anyToRecodedFloat32 (
in,
roundingMode,
typeOp,
out,
exceptionFlags
);
parameter INT_WIDTH = 64;
parameter SHIFT_WIDTH = INT_WIDTH + 1; // Save one fraction bit.
parameter STAGES = `ceilLog2(SHIFT_WIDTH);
parameter SIG_WIDTH = 23;
parameter EXP_WIDTH = 9; // Recoded float has one ... | 7.073609 |
module anyToRecodedFloat64 (
in,
roundingMode,
typeOp,
out,
exceptionFlags
);
parameter INT_WIDTH = 64;
parameter SHIFT_WIDTH = INT_WIDTH + 1; // Save one fraction bit.
parameter STAGES = `ceilLog2(SHIFT_WIDTH);
parameter SIG_WIDTH = 52;
parameter EXP_WIDTH = 12; // Recoded float has one... | 7.073609 |
module AO2 (
input a,
b,
c,
output w
);
wire i, j;
not #(5, 7) G2 (j, c);
nand #(10, 8) G1 (i, a, b);
nand #(10, 8) G3 (w, i, j);
endmodule
| 7.624179 |
module ao486_rst_controller (
input wire clk_sys,
input wire rst,
output reg ao486_rst,
input wire [ 1:0] address,
input wire write,
input wire [31:0] writedata
);
always @(posedge clk_sys) begin
if (rst) begin
ao486_rst <= 1;
end else begin
if (write && writeda... | 7.881611 |
module AOBUFX2 (
INP,
Z
);
input INP;
output Z;
buf U0 (Z, INP);
specify
specparam tdelay_INP_Z_01_0 = 0.01, tdelay_INP_Z_10_0 = 0.01;
(INP + => Z) = (tdelay_INP_Z_01_0, tdelay_INP_Z_10_0);
endspecify
endmodule
| 6.629566 |
module AOI (
input a,
input b,
input c,
input d,
output e,
output f,
output g
);
assign e = a && b;
assign f = c && d;
assign g = ~(e || f);
endmodule
| 6.51183 |
module AOI22 (
Y,
A0,
A1,
B0,
B1,
VDD,
VSS
);
input A0, A1, B0, B1;
output Y;
inout VDD, VSS;
assign Y = ~((A0 && A1) || (B0 && B1));
endmodule
| 7.559635 |
module AOI23 (
Y,
A0,
A1,
B0,
B1,
C0,
C1,
VDD,
VSS
);
input A0, A1, B0, B1, C0, C1;
output Y;
inout VDD, VSS;
assign Y = ~((A0 && A1) || (B0 && B1) || (C0 || C1));
endmodule
| 6.777044 |
module AOI24 (
Y,
A0,
A1,
B0,
B1,
C0,
C1,
D0,
D1,
VDD,
VSS
);
input A0, A1, B0, B1, C0, C1, D0, D1;
output Y;
inout VDD, VSS;
assign Y = ~((A0 && A1) || (B0 && B1) || (C0 && C1) || (D0 && D1));
endmodule
| 7.300116 |
module AOI32 (
Y,
A0,
A1,
A2,
B0,
B1,
B2,
VDD,
VSS
);
input A0, A1, A2, B0, B1, B2;
output Y;
inout VDD, VSS;
assign Y = ~((A0 && A1 && A2) || (B0 && B1 && B2));
endmodule
| 7.450454 |
module AOI33 (
Y,
A0,
A1,
A2,
B0,
B1,
B2,
C0,
C1,
C2,
VDD,
VSS
);
input A0, A1, A2, B0, B1, B2, C0, C1, C2;
output Y;
inout VDD, VSS;
assign Y = ~((A0 && A1 && A2) || (B0 && B1 && B2) || (C0 && C1 && C2));
endmodule
| 6.600732 |
module AOI42 (
Y,
A0,
A1,
A2,
A3,
B0,
B1,
B2,
B3,
VDD,
VSS
);
input A0, A1, A2, A3, B0, B1, B2, B3;
output Y;
inout VDD, VSS;
assign Y = ~((A0 && A1 && A2 && A3) || (B0 && B1 && B2 && B3));
endmodule
| 7.019812 |
module AOI43 (
Y,
A0,
A1,
A2,
A3,
B0,
B1,
B2,
B3,
C0,
C1,
C2,
C3,
VDD,
VSS
);
input A0, A1, A2, A3, B0, B1, B2, B3, C0, C1, C2, C3;
output Y;
inout VDD, VSS;
assign Y = ~((A0 && A1 && A2 && A3) || (B0 && B1 && B2 && B3) || (C0 && C1 && C2 && C3));
end... | 6.85537 |
module AOI44 (
Y,
A0,
A1,
A2,
A3,
B0,
B1,
B2,
B3,
C0,
C1,
C2,
C3,
D0,
D1,
D2,
D3,
VDD,
VSS
);
input A0, A1, A2, A3, B0, B1, B2, B3, C0, C1, C2, C3, D0, D1, D2, D3;
output Y;
inout VDD, VSS;
assign Y=~((A0 && A1 && A2 && A3) || (B0 && B... | 6.680585 |
module AOINVX1 (
INP,
ZN
);
input INP;
output ZN;
not U0 (ZN, INP);
specify
specparam tdelay_INP_ZN_01_0 = 0.01, tdelay_INP_ZN_10_0 = 0.01;
(INP - => ZN) = (tdelay_INP_ZN_01_0, tdelay_INP_ZN_10_0);
endspecify
endmodule
| 7.137007 |
module AOINVX2 (
INP,
ZN
);
input INP;
output ZN;
not U0 (ZN, INP);
specify
specparam tdelay_INP_ZN_01_0 = 0.01, tdelay_INP_ZN_10_0 = 0.01;
(INP - => ZN) = (tdelay_INP_ZN_01_0, tdelay_INP_ZN_10_0);
endspecify
endmodule
| 7.814333 |
module AOINVX4 (
INP,
ZN
);
input INP;
output ZN;
not U0 (ZN, INP);
specify
specparam tdelay_INP_ZN_01_0 = 0.01, tdelay_INP_ZN_10_0 = 0.01;
(INP - => ZN) = (tdelay_INP_ZN_01_0, tdelay_INP_ZN_10_0);
endspecify
endmodule
| 6.928771 |
module AOI_logic (
and1,
or1,
not1,
in
);
input [1:0] in;
output and1;
output or1;
output not1;
wire a;
wire o;
wire i;
and gate1 (a, in[0], in[1]);
or gate2 (o, in[0], in[1]);
not gate3 (i, in[0]);
endmodule
| 7.597809 |
module AOI_logic_tb;
reg [1:0] in;
wire and1, or1, not1;
AOI_logic uut (
and1,
or1,
not1,
in
);
initial begin
$dumpfile("AOI_logic_tb.vcd");
$dumpvars(0, AOI_logic_tb);
in[0] = 0;
in[1] = 0;
#10;
in[0] = 0;
in[1] = 1;
#10;
in[0] = 1;
in[1] = 0;
... | 6.594818 |
module aoOCS_tb ();
// inputs
reg clk;
reg rst_n;
wire sram_clk;
wire [18:0] sram_address;
wire sram_oe_n;
wire sram_writeen_n;
wire [3:0] sram_byteen_n;
wire [31:0] sram_data_o;
inout [35:0] sram_data;
assign sram_data = (sram_oe_n == 1'b0) ? {4'b0, sram_data_o} : 36'bZ;
wire sram_advance_n;
... | 6.936619 |
module aopac01_3v3 ( OUT, EN, IB, INN, INP, VDDA, VSSA );
input IB;
input EN;
input VSSA;
input VDDA;
input INN;
input INP;
output OUT;
wire real IB, VSSA, VDDA, INN, INP;
reg real OUT;
wire real outval, nextout;
real NaN;
initial begin
NaN = 0.0 / 0.0;
OUT <= 0.0;
end
// Gain... | 7.064295 |
module APB_I2C (
//APB Inputs
input wire PCLK,
input wire PRESETn,
input wire PWRITE,
input wire [31:0] PWDATA,
input wire [31:0] PADDR,
input wire PENABLE,
input PSEL,
//APB Outputs
output wire PREADY,
output wire [31:0] PRDATA,
// i2c Ports
input wire scl_i, ... | 7.853387 |
module apb2iob #(
parameter APB_ADDR_W = 21, // APB address bus width in bits
parameter APB_DATA_W = 21, // APB data bus width in bits
parameter ADDR_W = APB_ADDR_W, // IOb address bus width in bits
parameter DATA_W = APB_DATA_W // IOb data bus width in bits
) (
// Globa... | 7.210421 |
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