code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module AppleIIePAL (
input clk_14M,
output reg clk_7M,
output clk_3_58M,
output reg clk_q3,
output clk_phi_0,
// RAM address strobes
input clk_phi_1,
input ramen_n,
output reg pcas_n,
output reg pras_n,
input vid7,
input gr,
input eighty_vid_n,
input entmg,
output h0,
output segb,
output ldps_n,
output vid7m
);
always @(posedge clk_14M) clk_7M <= ~clk_7M;
ClockDivideByN #(
.N(14)
) phi_0_divider (
.clk_in (clk_14M),
.reset (1'b0),
.clk_out(clk_phi_0)
);
// Q3's asymmetric waveform edges are always aligned with positive edges
// of 14M. Counting those edges is sufficient to generate both periods of
// Q3. RAS pulses high for 2 14M periods centered on Q3's rising edge.
reg [3:0] q3_counter;
always @(posedge clk_14M) begin
if (q3_counter < 4'd4) clk_q3 <= 1'b1;
else clk_q3 <= 1'b0;
if (q3_counter >= 4'd6) q3_counter <= 0;
else q3_counter <= q3_counter + 1;
end
// RAS# goes high 2 14M cycles after Q3 goes low and remains high for
// 2 14M cycles.
reg pras_counter;
always @(posedge clk_14M) begin
if (~pras_n && ~clk_q3) begin
if (~pras_counter) pras_counter <= 1'b1;
else begin
pras_counter <= 1'b0;
pras_n <= 1'b1;
end
end else if (pras_n) begin
if (~pras_counter) pras_counter <= 1'b1;
else begin
pras_counter <= 1'b0;
pras_n <= 1'b0;
end
end
end
// If RAMEN# is low, CAS# goes high on the rising edge of 14M when RAS# is
// also high. It remains high for 3 14M periods. If RAMEN# is high, CAS#
// is held high to prevent the RAMs from enabling their outputs.
reg [1:0] pcas_counter;
always @(posedge clk_14M) begin
if (ramen_n) pcas_n <= 1'b1;
else begin
if (pras_n) begin
pcas_counter <= 2'b0;
pcas_n <= 1'b1;
end else if (pcas_n) begin
if (pcas_counter < 2'd2) pcas_counter <= pcas_counter + 1;
else pcas_n <= 1'b0;
end
end
end
endmodule
| 7.748564 |
module apple_rom (
addr,
rd_data,
clk,
rst
);
localparam ADDR_WIDTH = 11; // @IPC int 9,20
localparam DATA_WIDTH = 8; // @IPC int 1,1152
localparam OUTPUT_REG = 0; // @IPC bool
localparam RD_OCE_EN = 0; // @IPC bool
localparam CLK_OR_POL_INV = 0; // @IPC bool
localparam RESET_TYPE = "ASYNC"; // @IPC enum ASYNC,SYNC,Sync_Internally
localparam POWER_OPT = 0; // @IPC bool
localparam INIT_FILE = "E:/PDS/PGL22G/CD_20210223/CD_20210223/demo/zhenjiuzhe_ddr3_ov5640_hdmi - 5 - 2/source/ISP/red_apple.dat" ; // @IPC string
localparam INIT_FORMAT = "HEX"; // @IPC enum BIN,HEX
localparam CLK_EN = 0; // @IPC bool
localparam ADDR_STROBE_EN = 0; // @IPC bool
localparam INIT_EN = 1; // @IPC bool
localparam RESET_TYPE_SEL = (RESET_TYPE == "ASYNC") ? "ASYNC_RESET" :
(RESET_TYPE == "SYNC") ? "SYNC_RESET" : "ASYNC_RESET_SYNC_RELEASE";
localparam DEVICE_NAME = "PGL22G";
localparam DATA_WIDTH_WRAP = ((DEVICE_NAME == "PGT30G") && (DATA_WIDTH <= 9)) ? 10 : DATA_WIDTH;
localparam SIM_DEVICE = ((DEVICE_NAME == "PGL22G") || (DEVICE_NAME == "PGL22GS")) ? "PGL22G" : "LOGOS";
input [ADDR_WIDTH-1 : 0] addr;
output [DATA_WIDTH-1 : 0] rd_data;
input clk;
input rst;
wire [ ADDR_WIDTH-1 : 0] addr;
wire [ DATA_WIDTH-1 : 0] rd_data;
wire clk;
wire clk_en;
wire addr_strobe;
wire rst;
wire rd_oce;
wire rd_oce_mux;
wire clk_en_mux;
wire addr_strobe_mux;
wire [DATA_WIDTH_WRAP-1 : 0] rd_data_wrap;
assign rd_oce_mux = (RD_OCE_EN == 1) ? rd_oce : (OUTPUT_REG == 1) ? 1'b1 : 1'b0;
assign clk_en_mux = (CLK_EN == 1) ? clk_en : 1'b1;
assign addr_strobe_mux = (ADDR_STROBE_EN == 1) ? addr_strobe : 1'b0;
assign rd_data = ((DEVICE_NAME == "PGT30G") && (DATA_WIDTH <= 9)) ? rd_data_wrap[DATA_WIDTH-1 : 0] : rd_data_wrap;
//ipml_rom IP instance
ipml_rom_v1_4_apple_rom #(
.c_SIM_DEVICE(SIM_DEVICE),
.c_ADDR_WIDTH(ADDR_WIDTH), //write address width legal value:1~20
.c_DATA_WIDTH(DATA_WIDTH_WRAP), //write data width legal value:8~1152
.c_OUTPUT_REG(OUTPUT_REG), //output register legal value:1~20
.c_RD_OCE_EN(RD_OCE_EN),
.c_CLK_EN(CLK_EN),
.c_ADDR_STROBE_EN(ADDR_STROBE_EN),
.c_RESET_TYPE ( RESET_TYPE_SEL ), //ASYNC_RESET_SYNC_RELEASE SYNC_RESET legal valve "ASYNC_RESET_SYNC_RELEASE" "SYNC_RESET" "ASYNC_RESET"
.c_POWER_OPT(POWER_OPT), //0 :normal mode 1:low power mode legal value:0 or 1
.c_CLK_OR_POL_INV ( CLK_OR_POL_INV ), //clk polarity invert for output register legal value 1 or 0
.c_INIT_FILE("NONE"), //legal value:"NONE" or "initial file name"
.c_INIT_FORMAT(INIT_FORMAT) //initial data format legal valve: "bin" or "hex"
) U_ipml_rom_apple_rom (
.addr (addr),
.rd_data (rd_data_wrap),
.clk (clk),
.clk_en (clk_en_mux),
.addr_strobe(addr_strobe_mux),
.rst (rst),
.rd_oce (rd_oce_mux)
);
endmodule
| 6.977502 |
module font_apple (
input wire clk,
input wire video_on,
input wire [9:0] pixel_x,
pixel_y,
output reg [2:0] rgb_apple
);
// signal declaration
wire [10:0] rom_addr;
reg [ 6:0] char_addr;
reg [6:0] char_addr_a, char_addr_p, char_addr_p2, char_addr_l, char_addr_e;
reg [3:0] row_addr;
wire [3:0] row_addr_a, row_addr_p, row_addr_p2, row_addr_l, row_addr_e;
reg [2:0] bit_addr;
wire [2:0] bit_addr_a, bit_addr_p, bit_addr_p2, bit_addr_l, bit_addr_e;
wire [7:0] font_word;
wire font_bit, apple_a_on, apple_p_on, apple_p2_on, apple_l_on, apple_e_on;
// body
// instantiate font ROM
font_rom font_unit (
.clk (clk),
.addr(rom_addr),
.data(font_word)
);
assign apple_a_on = (pixel_y[9:5] == 1) && (pixel_x[9:6] == 4);
assign row_addr_a = pixel_y[5:2];
assign bit_addr_a = pixel_x[4:2];
always @*
case (pixel_x[7:4])
default: char_addr_a = 7'h61; //a
endcase
assign apple_p_on = (pixel_y[9:5] == 1) && (pixel_x[9:6] == 5);
assign row_addr_p = pixel_y[4:1];
assign bit_addr_p = pixel_x[3:1];
always @*
case (pixel_x[7:4])
default: char_addr_p = 7'h70; //p
endcase
assign apple_p2_on = (pixel_y[9:5] == 1) && (pixel_x[9:6] == 6);
assign row_addr_p2 = pixel_y[4:1];
assign bit_addr_p2 = pixel_x[3:1];
always @*
case (pixel_x[7:4])
default: char_addr_p2 = 7'h70; //p
endcase
assign apple_l_on = (pixel_y[9:5] == 1) && (pixel_x[9:6] == 7);
assign row_addr_l = pixel_y[4:1];
assign bit_addr_l = pixel_x[3:1];
always @*
case (pixel_x[7:4])
default: char_addr_l = 7'h6c; //l
endcase
assign apple_e_on = (pixel_y[9:5] == 1) && (pixel_x[9:6] == 8);
assign row_addr_e = pixel_y[4:1];
assign bit_addr_e = pixel_x[3:1];
always @*
case (pixel_x[7:4])
default: char_addr_e = 7'h65; //e
endcase
assign rom_addr = {char_addr, row_addr};
assign font_bit = font_word[~bit_addr];
// rgb multiplexing circuit
always @*
if (~video_on) rgb_apple = 3'b000; // blank
else if (apple_a_on) begin
bit_addr = bit_addr_a;
char_addr = char_addr_a;
row_addr = row_addr_a;
if (font_bit) rgb_apple = 3'b111; // white
end else if (apple_p_on) begin
bit_addr = bit_addr_p;
char_addr = char_addr_p;
row_addr = row_addr_p;
if (font_bit) rgb_apple = 3'b111; // white
end else if (apple_p2_on) begin
bit_addr = bit_addr_p2;
char_addr = char_addr_p2;
row_addr = row_addr_p2;
if (font_bit) rgb_apple = 3'b111; // white
end else if (apple_l_on) begin
bit_addr = bit_addr_l;
char_addr = char_addr_l;
row_addr = row_addr_l;
if (font_bit) rgb_apple = 3'b111; // white
end else if (apple_e_on) begin
bit_addr = bit_addr_e;
char_addr = char_addr_e;
row_addr = row_addr_e;
if (font_bit) rgb_apple = 3'b111; // white
end
endmodule
| 7.721663 |
module ApplySimpleCases(
// Input
input wire `TYPE_DEF typeIn,
input wire `INDEX_DEF f,
input wire `INDEX_DEF g,
input wire `VAR_DEF top,
input wire `VAR_DEF cubeLastVar,
// Abstract transform result
output reg `TYPE_DEF outType,
output reg `INDEX_DEF outF,
output reg `INDEX_DEF outG,
// Simple cases
output reg hit,
output reg `INDEX_DEF result
);
wire topBigger,equal_f_one,equal_f_g,equal_g_one;
assign topBigger = (top > cubeLastVar);
assign equal_f_one = (f == `BDD_ONE);
assign equal_f_g = (f == g);
assign equal_g_one = (g == `BDD_ONE);
wire typeEqualAbstract,transformAnd,transformExistG,transformExistF;
assign typeEqualAbstract = (typeIn == `BDD_ABSTRACT);
assign transformAnd = topBigger;
assign transformExistG = (equal_f_one | equal_f_g);
assign transformExistF = equal_g_one;
reg checkExistGSimpleCase;
// Perform transformation
always @*
begin
checkExistGSimpleCase = 0;
casez({typeEqualAbstract,transformAnd,transformExistG,transformExistF})
4'b11??: begin
outF = f;
outG = g;
outType = `BDD_AND;
end
4'b101?: begin
checkExistGSimpleCase = 1;
outF = g;
outG = `BDD_ZERO; // This isn't needed, but nice for hashing purposes
outType = `BDD_EXIST;
end
4'b1001:begin
outF = f;
outG = `BDD_ZERO; // This isn't needed, but nice for hashing purposes
outType = `BDD_EXIST;
end
default:begin
outF = f;
outG = g;
outType = typeIn;
end
endcase
end
wire andHit;
wire `INDEX_DEF andResult;
AndTerminalCase terminalAnd(
.f(f),
.g(g),
.hit(andHit),
.result(andResult));
wire existHit;
wire `INDEX_DEF existResult;
ExistTerminalCase terminalExist(
.f(f),
.top(top),
.cubeLastVar(cubeLastVar),
.hit(existHit),
.result(existResult));
wire transformedExistHit;
wire `INDEX_DEF transformedExistResult;
ExistTerminalCase transformedTerminalExist( // Calculates the terminal case if we do have a exist transformation (its the only case that needs a separate calculation)
.f(g),
.top(top),
.cubeLastVar(cubeLastVar),
.hit(transformedExistHit),
.result(transformedExistResult));
wire abstractHit;
wire `INDEX_DEF abstractResult;
AbstractTerminalCase terminalAbstract(
.f(f),
.g(g),
.hit(abstractHit),
.result(abstractResult));
wire existFinalHit;
wire `INDEX_DEF existFinalResult;
assign existFinalHit = (checkExistGSimpleCase ? transformedExistHit : existHit);
assign existFinalResult = (checkExistGSimpleCase ? transformedExistResult : existResult);
always @*
begin
case(typeIn)
`BDD_AND:begin
hit = andHit;
result = andResult;
end
`BDD_EXIST:begin
hit = existFinalHit;
result = existFinalResult;
end
`BDD_ABSTRACT:begin
hit = abstractHit;
result = abstractResult;
end
`BDD_PERMUTE:begin
hit = (f == `BDD_ZERO | f == `BDD_ONE);
result = f;
end
default:begin
hit = 1'b0;
result = 30'h00000000; // Can be xxxxxxxx
end
endcase
end
endmodule
| 6.839091 |
module ApplySimpleCasesNoVar(
// Input
input wire `TYPE_DEF typeIn,
input wire `INDEX_DEF f,
input wire `INDEX_DEF g,
output reg `TYPE_DEF outType,
output reg `INDEX_DEF outF,
output reg `INDEX_DEF outG,
// Simple cases
output reg hit,
output reg `INDEX_DEF result
);
wire equal_f_one,equal_f_g,equal_g_one;
assign equal_f_one = (f == `BDD_ONE);
assign equal_f_g = (f == g);
assign equal_g_one = (g == `BDD_ONE);
wire typeEqualAbstract,transformExistG,transformExistF;
assign typeEqualAbstract = (typeIn == `BDD_ABSTRACT);
assign transformExistG = (equal_f_one | equal_f_g);
assign transformExistF = equal_g_one;
reg checkExistGSimpleCase;
// Perform transformation
always @*
begin
checkExistGSimpleCase = 0;
casez({typeEqualAbstract,transformExistG,transformExistF})
4'b11?: begin
checkExistGSimpleCase = 1;
outF = g;
outG = `BDD_ZERO; // This isn't needed, but nice for hashing purposes
outType = `BDD_EXIST;
end
4'b101:begin
outF = f;
outG = `BDD_ZERO; // This isn't needed, but nice for hashing purposes
outType = `BDD_EXIST;
end
default:begin
outF = f;
outG = g;
outType = typeIn;
end
endcase
end
wire andHit;
wire `INDEX_DEF andResult;
AndTerminalCase terminalAnd(
.f(f),
.g(g),
.hit(andHit),
.result(andResult));
wire existHit;
wire `INDEX_DEF existResult;
ExistTerminalCaseNoVar terminalExist(
.f(f),
.hit(existHit),
.result(existResult));
wire transformedExistHit;
wire `INDEX_DEF transformedExistResult;
ExistTerminalCaseNoVar transformedTerminalExist( // Calculates the terminal case if we do have a exist transformation (its the only case that needs a separate calculation)
.f(g),
.hit(transformedExistHit),
.result(transformedExistResult));
wire abstractHit;
wire `INDEX_DEF abstractResult;
AbstractTerminalCase terminalAbstract(
.f(f),
.g(g),
.hit(abstractHit),
.result(abstractResult));
wire existFinalHit;
wire `INDEX_DEF existFinalResult;
assign existFinalHit = (checkExistGSimpleCase ? transformedExistHit : existHit);
assign existFinalResult = (checkExistGSimpleCase ? transformedExistResult : existResult);
always @*
begin
case(typeIn)
`BDD_AND:begin
hit = andHit;
result = andResult;
end
`BDD_EXIST:begin
hit = existFinalHit;
result = existFinalResult;
end
`BDD_ABSTRACT:begin
hit = abstractHit;
result = abstractResult;
end
`BDD_PERMUTE:begin
hit = (f == `BDD_ZERO | f == `BDD_ONE);
result = f;
end
default:begin
hit = 1'b0;
result = 30'h00000000; // Can be xxxxxxxx
end
endcase
end
endmodule
| 6.839091 |
module ApplyStage #(
parameter MEMORY_HALFADDRESS_BITS = 10,
parameter INSTRUCTION_HALFADDRESS_BITS = 32
) (
input wire CLK,
input wire RST_X,
output wire MemoryStallRequest,
input wire MemOp, //Whether to access memory
input wire MemRw, //Whether to read (0) or write (1) memory
input wire [31:0] AluRes, //Alu result
input wire [31:0] RegRdataC, //Readed data of Register C operand
input wire [3:0] RegNoC, //Destination register number specified by instruction
input wire ValidAS,
//Memory interface
output wire MemEn,
output wire [MEMORY_HALFADDRESS_BITS-2:0] MemAddr,
input wire [31:0] MemRdata,
output wire MemWen,
output wire [31:0] MemWdata,
//Register write to CS
output wire RegWen,
output wire [31:0] RegWdata,
output wire [3:0] RegWno
);
//Pipeline stage will stall by all memory read / write instructions
reg memReaded = 1'b0;
always @(posedge CLK) begin
if (ValidAS && MemOp && !memReaded && RST_X) memReaded <= 1'b1;
else memReaded <= 1'b0;
end
assign MemoryStallRequest = ValidAS && !memReaded && MemOp;
//Perfom memory access
assign MemEn = !memReaded;
assign MemAddr = {2'b0, AluRes[31:2]}; //AluRes[1]: half address
assign MemWen = !memReaded & MemRw;
assign MemWdata = RegRdataC;
//Perfom register writing when not-memory access or memory reading
assign RegWen = ValidAS && (!MemOp || (!MemRw && !memReaded));
assign RegWdata = MemOp ? MemRdata : AluRes;
assign RegWno = RegNoC;
endmodule
| 9.353955 |
module clock_approximator #(
parameter actual_frequency = 50e6,
parameter desired_frequency = 16e6
) (
input clock_original,
output reg clock_generated
);
// Skip every other HF clock period to achieve the LF clock
localparam skip_clocks = desired_frequency / actual_frequency;
reg [$clog2(skip_clocks):0] skip_counter = 0;
// Counts the number of elapsed HF clock periods
reg [$clog2(actual_frequency):0] high_frequency_period_counter = 0;
// Counts the number of elapsed LF clock periods
reg [$clog2(desired_frequency):0] low_frequency_period_counter = 0;
always @(posedge clock_original) begin
skip_counter <= skip_counter + 1;
if (skip_counter == skip_clocks - 1) skip_counter <= 0;
// TODO...
end
endmodule
| 7.150452 |
module approx_8x8 (
input [7:0] A,
input [7:0] B,
output [15:0] P
);
wire [15:0] P_1;
mult_8x8_1111 M (
.A(A),
.B(B),
.R(P)
); //change this module name
endmodule
| 6.860685 |
module approx_fp_div (
a,
b,
q,
clk
);
input [31:0] a, b;
input clk;
output [31:0] q;
reg a_sign, b_sign, q_sign;
reg [7:0] a_exp, b_exp, q_exp;
reg [22:0] a_frac, q_frac;
reg [5:0] b_frac /*synthesis keep*/;
//input, output interface
always @(posedge clk) begin
a_sign <= a[31];
a_exp <= a[30:23];
a_frac <= a[22:0];
b_sign <= b[31];
b_exp <= b[30:23];
b_frac <= b[22:17];
end
//stage 1
//sign bit and exp
reg q_sign_reg1;
reg [7:0] q_exp_reg1;
always @(posedge clk) begin
q_sign_reg1 <= a_sign ^ b_sign;
q_exp_reg1 <= {1'b0, a_exp} + 9'h7e - {1'b0, b_exp};
end
//frac bits
wire [23:0] a0_tmp;
assign a0_tmp = {1'b1, a_frac};
//Get estimation e0
reg [ 6:0] e0_reg1;
wire [ 6:0] e0 /*synthesis keep*/;
reg [23:0] a0_reg1;
always @(posedge clk) begin
e0_reg1 <= e0;
a0_reg1 <= a0_tmp;
end
approx_fp_div_lut tbl1 (
.in (b_frac),
.out(e0)
);
//Stage 2
//Product
wire [31:0] product;
reg q_sign_reg2, q_sign_reg3, q_sign_reg4;
reg [7:0] q_exp_reg2, q_exp_reg3, q_exp_reg4, q_exp_plus;
always @(posedge clk) begin
q_sign_reg2 <= q_sign_reg1;
q_sign_reg3 <= q_sign_reg2;
q_sign_reg4 <= q_sign_reg3;
q_exp_reg2 <= q_exp_reg1;
q_exp_reg3 <= q_exp_reg2;
q_exp_reg4 <= q_exp_reg3;
q_exp_plus <= q_exp_reg3 + 1'b1;
end
mult_3tick mult1 (
.clk(clk),
.a_in({12'b0, a0_reg1}),
.b_in({29'b1, e0_reg1}),
.o(product)
);
//Stage3
wire [22:0] q_frac_tmp;
assign q_frac_tmp = (product[31]) ? product[30:8] : product[29:7];
always @(posedge clk) begin
q_sign <= q_sign_reg4;
q_exp <= (product[31]) ? q_exp_plus : q_exp_reg4;
q_frac <= q_frac_tmp;
end
assign q = {q_sign, q_exp, q_frac};
endmodule
| 7.014474 |
module approx_fp_div_lut (
in,
out
);
input [5:0] in;
output [6:0] out;
reg [6:0] out;
always @(in) begin
case (in)
6'h0: out <= 7'h7c;
6'h1: out <= 7'h78;
6'h2: out <= 7'h74;
6'h3: out <= 7'h70;
6'h4: out <= 7'h6d;
6'h5: out <= 7'h6a;
6'h6: out <= 7'h66;
6'h7: out <= 7'h63;
6'h8: out <= 7'h60;
6'h9: out <= 7'h5d;
6'ha: out <= 7'h5a;
6'hb: out <= 7'h57;
6'hc: out <= 7'h54;
6'hd: out <= 7'h52;
6'he: out <= 7'h4f;
6'hf: out <= 7'h4c;
6'h10: out <= 7'h4a;
6'h11: out <= 7'h47;
6'h12: out <= 7'h45;
6'h13: out <= 7'h43;
6'h14: out <= 7'h40;
6'h15: out <= 7'h3e;
6'h16: out <= 7'h3c;
6'h17: out <= 7'h3a;
6'h18: out <= 7'h38;
6'h19: out <= 7'h36;
6'h1a: out <= 7'h34;
6'h1b: out <= 7'h32;
6'h1c: out <= 7'h30;
6'h1d: out <= 7'h2e;
6'h1e: out <= 7'h2c;
6'h1f: out <= 7'h2a;
6'h20: out <= 7'h28;
6'h21: out <= 7'h27;
6'h22: out <= 7'h25;
6'h23: out <= 7'h23;
6'h24: out <= 7'h22;
6'h25: out <= 7'h20;
6'h26: out <= 7'h1f;
6'h27: out <= 7'h1d;
6'h28: out <= 7'h1c;
6'h29: out <= 7'h1a;
6'h2a: out <= 7'h19;
6'h2b: out <= 7'h17;
6'h2c: out <= 7'h16;
6'h2d: out <= 7'h14;
6'h2e: out <= 7'h13;
6'h2f: out <= 7'h12;
6'h30: out <= 7'h10;
6'h31: out <= 7'hf;
6'h32: out <= 7'he;
6'h33: out <= 7'hd;
6'h34: out <= 7'hc;
6'h35: out <= 7'ha;
6'h36: out <= 7'h9;
6'h37: out <= 7'h8;
6'h38: out <= 7'h7;
6'h39: out <= 7'h6;
6'h3a: out <= 7'h5;
6'h3b: out <= 7'h4;
6'h3c: out <= 7'h3;
6'h3d: out <= 7'h2;
6'h3e: out <= 7'h1;
6'h3f: out <= 7'h0;
endcase
end
endmodule
| 7.014474 |
module approx_fp_div_tb ();
////////////////////////
// define the latency here
////////////////////////
parameter LATENCY = 5;
wire [31:0] q;
reg clk = 0;
reg [31:0] nf, df;
reg [31:0] qf[LATENCY:0];
////////////////////////
// test unit
////////////////////////
approx_fp_div dut (
.a (nf),
.b (df),
.q (q),
.clk(clk)
);
////////////////////////
// C based model
////////////////////////
always @(posedge clk) begin
qf[0] <= $float_div(nf, df);
end
genvar i;
generate
for (i = 1; i <= LATENCY; i = i + 1) begin : output_latency
always @(posedge clk) begin
qf[i] <= qf[i-1];
end
end
endgenerate
////////////////////////
// stimulus
////////////////////////
initial begin
nf = $rand_float;
df = $rand_float;
end
always @(negedge clk) begin
nf = $rand_float;
df = $rand_float;
end
always begin
#10 clk = ~clk;
end
////////////////////////
// check
////////////////////////
integer err_bar;
reg fail = 0;
always @(posedge clk) begin
#5 err_bar = $float_err_bar(q, qf[LATENCY]);
if (err_bar > 200) begin
$display("Mismatch - Error greater than 2.00 pct at time %d", $time);
fail = 1'b1;
end
end
initial begin
#2000000 if (!fail) $display("PASS");
$stop();
end
endmodule
| 7.014474 |
module approx_fp_invsqrt (
clk,
in,
out
);
parameter CORRECTION_ROUND = 1'b1;
input clk;
input [31:0] in;
output [31:0] out;
wire [31:0] out;
// Magic courtesy of Quake 3 / Well known Internet trick
// first order approximation of 1 / sqrt(in)
//
reg [31:0] app;
always @(posedge clk) begin
app <= 32'h5F3759DF - {1'b0, in[31:1]};
end
generate
if (!CORRECTION_ROUND) begin
// output the approx directly
assign out = app;
end else begin
// add a Newton improvement round
reg [31:0] in_r;
always @(posedge clk) begin
in_r <= in;
end
wire [22:0] in_mant = in_r[22:0];
wire [ 7:0] in_exp = in_r[30:23];
wire [22:0] app_mant = app[22:0];
wire [ 7:0] app_exp = app[30:23];
reg [35:0] app_sqr_m, app_hlf_m;
reg [8:0] app_sqr_e, app_hlf_e;
reg [24:0] op5_m;
reg [ 8:0] op5_e;
// pipe layer 1
always @(posedge clk) begin
// app * app
app_sqr_m <= {1'b1, app_mant[22:6]} * {1'b1, app_mant[22:6]};
app_sqr_e <= {app_exp, 1'b0} - 8'h7f;
// app * in/2
app_hlf_m <= {1'b1, app_mant[22:6]} * {1'b1, in_mant[22:6]};
app_hlf_e <= in_exp + app_exp - 8'h7f - 8'h1;
// 1.5 * app
op5_m <= {1'b1, app_mant} + {1'b0, 1'b1, app_mant[22:1]};
op5_e <= app_exp;
end
reg [35:0] chunk_m;
reg [ 8:0] chunk_e;
reg [24:0] op5_m_r;
reg [ 8:0] op5_e_r;
// pipe layer 2
always @(posedge clk) begin
// app^3 * in/2
chunk_m <= app_sqr_m[35:18] * app_hlf_m[35:18];
chunk_e <= app_sqr_e[7:0] + app_hlf_e[7:0] - 8'h7f;
op5_m_r <= op5_m;
op5_e_r <= op5_e;
end
// work on op5 - chunk
// ironically much harder to subtract than multiply FP's
//
wire [ 3:0] exp_delta = op5_e_r[7:0] - chunk_e[7:0];
wire [24:0] scaled_chunk = (chunk_m[35:13] >> exp_delta) << 4;
reg [24:0] rough_m;
reg [ 7:0] rough_e;
// pipe layer 3
always @(posedge clk) begin
rough_m <= op5_m_r - scaled_chunk;
rough_e <= op5_e_r;
end
wire [31:0] scaled_m;
wire [ 4:0] distance;
scale_up sc (
.in({rough_m[24:0], 7'b0}),
.out(scaled_m),
.distance(distance)
);
defparam sc.WIDTH = 32; defparam sc.WIDTH_DIST = 5;
reg [22:0] scaled_m_r;
reg [ 7:0] distance_r;
reg [ 7:0] rough_e_r;
// pipe_layer 4
always @(posedge clk) begin
scaled_m_r <= scaled_m[30:8];
distance_r <= distance;
rough_e_r <= rough_e;
end
reg [22:0] out_m;
reg [ 7:0] out_e;
// pipe layer 5
always @(posedge clk) begin
out_m <= scaled_m_r;
out_e <= rough_e_r - distance_r + 1;
end
assign out = {1'b0, out_e, out_m};
end
endgenerate
endmodule
| 7.178777 |
module approx_fp_invsqrt_tb ();
// number of stimuli in table
parameter NUM_STIM = 50000;
// 1st order approximation only v.s. additional Newton refinement round
parameter CORRECTION_ROUND = 1'b1;
// the correction round increases the pipeline latency
parameter LAG = CORRECTION_ROUND ? 6 : 1;
reg [32*NUM_STIM*7-1:0] test_stim =
{
`include "inv_sqrt.tbl"
};
reg clk = 0;
//////////////////////////
// handle the stimulus and
// expected result latency
//////////////////////////
wire [31:0] in, invsqrt_in, min_err2, max_err2,
min_err5, max_err5,min_err10, max_err10;
wire [6*32-1:0] err_bars;
assign {in,err_bars} = test_stim [7*32-1:0];
reg [32*6*LAG-1:0] history;
always @(posedge clk) begin
history <= (history << 6*32) | err_bars;
end
assign {min_err2,max_err2,min_err5,max_err5,min_err10,max_err10} =
history [LAG*6*32-1:(LAG-1)*6*32];
//////////////////////////
// DUT
//////////////////////////
approx_fp_invsqrt ais (.clk(clk),.in(in),.out(invsqrt_in));
defparam ais .CORRECTION_ROUND = CORRECTION_ROUND;
integer n;
integer fail10 = 0, fail5 = 0, fail2 = 0;
initial begin
for (n=0; n<LAG; n=n+1)
begin : flush
@(posedge clk);
end
for (n=0; n<NUM_STIM-1; n=n+1)
begin : tst
@(posedge clk);
#5 if (invsqrt_in < min_err10 ||
invsqrt_in > max_err10)
begin
$display ("10pct error bar failed");
fail10 = fail10 + 1'b1;
end
else if (invsqrt_in < min_err5 ||
invsqrt_in > max_err5)
begin
$display ("5pct error bar failed");
fail5 = fail5 + 1'b1;
end
else if (invsqrt_in < min_err2 ||
invsqrt_in > max_err2)
begin
$display ("2pct error bar failed");
fail2 = fail2 + 1'b1;
end
end
$display ("Total trials %d",NUM_STIM);
$display (" 2 to 5 pct err %d",fail2);
$display (" 5 to 10 pct err %d",fail5);
$display (" over 10 pct err %d",fail10);
if (fail10 == 0) $display ("PASS");
$stop();
end
always @(posedge clk) begin
test_stim <= test_stim >> (7*32);
end
always begin
#100 clk = ~clk;
end
endmodule
| 7.178777 |
module appro_42 (
input a,
b,
c,
d,
output carry,
sum
);
assign carry = (a & b) | (c & d);
assign sum = (a ^ b) | (c ^ d) | (a & b & c & d);
endmodule
| 7.731284 |
module appro_fulladder (
input a,
b,
c,
output carry,
sum
);
assign carry = (a & c) | (b & c);
assign sum = (a | b) ^ c;
endmodule
| 6.890692 |
module appr_cordic #(
parameter width_in = 18, //data width_in
parameter width_out = 16 //data width_out
) (
input signed [ width_in-1:0] x_in,
input signed [ width_in-1:0] y_in,
input start,
input clk,
input rst_n,
output [width_out-1:0] x_out,
output [width_out-1:0] y_out,
output [width_out-1:0] phi_right
);
reg [width_out-1:0]
buffer_x1,
buffer_x2,
buffer_y1,
buffer_y2,
buffer_phi1,
buffer_phi2; //Dem du lieu de dam bao chac chan khong bi mat sau 16 chu ki
reg [width_out-1:0] x_temp, y_temp, phi_temp;
assign x_out = buffer_x2;
assign y_out = buffer_y2;
assign phi_right = buffer_phi2;
always @(x_in) begin // lam tron x_in
if ((x_in < -18'd8192) && (x_in[width_in-1])) begin //<-2 va x_in am
x_temp = -16'd12288; //=-3
end else if ((x_in >= -18'd8192) && (x_in[width_in-1])) begin //-2<=x_in && x_in la so am
x_temp = -16'd4096; //=-1
end
else if((x_in>=18'd0) && (x_in<18'd8192) && (~x_in[width_in-1]))begin//0<=x_in<2 va x_in duong
x_temp = 16'd4096; //=1
end else begin
x_temp = 16'd12288; //=3
end
end
always @(y_in) begin // lam tron y_in
if ((y_in < -18'd8192) && (y_in[width_in-1])) begin //<-2 va y_in am
y_temp = -16'd12288; //=-3
end else if ((y_in >= -18'd8192) && (y_in[width_in-1])) begin //-2<=y_in va y_in am
y_temp = -16'd4096; //=-1
end
else if((y_in>=18'd0) && (y_in<18'd8192) && (~y_in[width_in-1]))begin//0<=y_in<2 va y_in duong
y_temp = 16'd4096; //=1
end else begin
y_temp = 16'd12288; //=3
end
end
always @(x_temp or y_temp) begin
if(((x_temp==16'd4096)&&(y_temp==16'd4096)) || ((x_temp==16'd12288)&&(y_temp==16'd12288)))begin
phi_temp = 16'd3217;
end
else if(((x_temp==-16'd4096)&&(y_temp==-16'd4096)) || ((x_temp==-16'd12288)&&(y_temp==-16'd12288)))begin
phi_temp = 16'd16085;
end
else if(((x_temp==-16'd4096)&&(y_temp==16'd4096)) || ((x_temp==-16'd12288)&&(y_temp==16'd12288)))begin
phi_temp = 16'd9651;
end
else if(((x_temp==16'd4096)&&(y_temp==-16'd4096)) || ((x_temp==16'd12288)&&(y_temp==-16'd12288)))begin
phi_temp = 16'd22519;
end else if ((x_temp == 16'd12288) && (y_temp == 16'd4096)) begin
phi_temp = 16'd1318;
end else if ((x_temp == -16'd12288) && (y_temp == -16'd4096)) begin
phi_temp = 16'd14186;
end else if ((x_temp == 16'd4096) && (y_temp == 16'd12288)) begin
phi_temp = 16'd5116;
end else if ((x_temp == -16'd4096) && (y_temp == -16'd12288)) begin
phi_temp = 16'd17984;
end else if ((x_temp == -16'd4096) && (y_temp == 16'd12288)) begin
phi_temp = 16'd7752;
end else if ((x_temp == 16'd4096) && (y_temp == -16'd12288)) begin
phi_temp = 16'd20619;
end else if ((x_temp == -16'd12288) && (y_temp == 16'd4096)) begin
phi_temp = 16'd11550;
end else begin
phi_temp = 16'd24418;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
buffer_x1 <= 0;
buffer_x2 <= 0;
buffer_y1 <= 0;
buffer_y2 <= 0;
buffer_phi1 <= 0;
buffer_phi2 <= 0;
end else if (start) begin
buffer_x1 <= x_temp;
buffer_x2 <= buffer_x1;
buffer_y1 <= y_temp;
buffer_y2 <= buffer_y1;
buffer_phi1 <= phi_temp;
buffer_phi2 <= buffer_phi1;
end
end
endmodule
| 7.036113 |
module Appr_Mag #(
parameter WIDTH = 16
) (
input clk,
rst,
ena,
input [WIDTH-1:0] real_in,
imag_in,
output [ WIDTH:0] mag,
output val
);
reg [WIDTH-1:0] real_abs, imag_abs;
reg ena_abs;
always @(posedge clk) begin
if (rst) begin
ena_abs <= 1'b0;
real_abs <= 0;
imag_abs <= 0;
end else if (ena) begin
ena_abs <= 1'b1;
real_abs <= (real_in[WIDTH-1]) ? (~real_in + 1'b1) : real_in;
imag_abs <= (imag_in[WIDTH-1]) ? (~imag_in + 1'b1) : imag_in;
end else ena_abs <= 1'b0;
end
assign mag = (real_abs > imag_abs) ? (real_abs + (imag_abs >> 1)) : (imag_abs + (real_abs >> 1));
assign val = ena_abs;
endmodule
| 7.85363 |
module app_aes_end_s_table_0_0_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 6.994657 |
module app_aes_end_s_table_0_0_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
app_aes_end_s_table_0_0_V_ram app_aes_end_s_table_0_0_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 6.994657 |
module app_aes_process_0_mux_42_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
input [7 : 0] din1,
input [7 : 0] din2,
input [7 : 0] din3,
input [1 : 0] din4,
output [7 : 0] dout
);
// puts internal signals
wire [1 : 0] sel;
// level 1 signals
wire [7 : 0] mux_1_0;
wire [7 : 0] mux_1_1;
// level 2 signals
wire [7 : 0] mux_2_0;
assign sel = din4;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
| 8.416717 |
module app_aes_process_0_s_table_0_0_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 8.416717 |
module app_aes_process_0_s_table_0_0_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
app_aes_process_0_s_table_0_0_V_ram app_aes_process_0_s_table_0_0_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 8.416717 |
module app_aes_process_1_mux_42_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
input [7 : 0] din1,
input [7 : 0] din2,
input [7 : 0] din3,
input [1 : 0] din4,
output [7 : 0] dout
);
// puts internal signals
wire [1 : 0] sel;
// level 1 signals
wire [7 : 0] mux_1_0;
wire [7 : 0] mux_1_1;
// level 2 signals
wire [7 : 0] mux_2_0;
assign sel = din4;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
| 8.416717 |
module app_aes_process_1_s_table_0_0_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 8.416717 |
module app_aes_process_1_s_table_0_0_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
app_aes_process_1_s_table_0_0_V_ram app_aes_process_1_s_table_0_0_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 8.416717 |
module app_aes_process_2_mux_42_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
input [7 : 0] din1,
input [7 : 0] din2,
input [7 : 0] din3,
input [1 : 0] din4,
output [7 : 0] dout
);
// puts internal signals
wire [1 : 0] sel;
// level 1 signals
wire [7 : 0] mux_1_0;
wire [7 : 0] mux_1_1;
// level 2 signals
wire [7 : 0] mux_2_0;
assign sel = din4;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
| 8.416717 |
module app_aes_process_2_s_table_0_0_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 8.416717 |
module app_aes_process_2_s_table_0_0_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
app_aes_process_2_s_table_0_0_V_ram app_aes_process_2_s_table_0_0_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 8.416717 |
module app_aes_process_3_mux_42_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
input [7 : 0] din1,
input [7 : 0] din2,
input [7 : 0] din3,
input [1 : 0] din4,
output [7 : 0] dout
);
// puts internal signals
wire [1 : 0] sel;
// level 1 signals
wire [7 : 0] mux_1_0;
wire [7 : 0] mux_1_1;
// level 2 signals
wire [7 : 0] mux_2_0;
assign sel = din4;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
| 8.416717 |
module app_aes_process_3_s_table_0_0_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 8.416717 |
module app_aes_process_3_s_table_0_0_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
app_aes_process_3_s_table_0_0_V_ram app_aes_process_3_s_table_0_0_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 8.416717 |
module app_aes_process_4_mux_42_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
input [7 : 0] din1,
input [7 : 0] din2,
input [7 : 0] din3,
input [1 : 0] din4,
output [7 : 0] dout
);
// puts internal signals
wire [1 : 0] sel;
// level 1 signals
wire [7 : 0] mux_1_0;
wire [7 : 0] mux_1_1;
// level 2 signals
wire [7 : 0] mux_2_0;
assign sel = din4;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
| 8.416717 |
module app_aes_process_4_s_table_0_0_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 8.416717 |
module app_aes_process_4_s_table_0_0_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
app_aes_process_4_s_table_0_0_V_ram app_aes_process_4_s_table_0_0_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 8.416717 |
module app_aes_process_5_mux_42_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
input [7 : 0] din1,
input [7 : 0] din2,
input [7 : 0] din3,
input [1 : 0] din4,
output [7 : 0] dout
);
// puts internal signals
wire [1 : 0] sel;
// level 1 signals
wire [7 : 0] mux_1_0;
wire [7 : 0] mux_1_1;
// level 2 signals
wire [7 : 0] mux_2_0;
assign sel = din4;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
| 8.416717 |
module app_aes_process_5_s_table_0_0_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 8.416717 |
module app_aes_process_5_s_table_0_0_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
app_aes_process_5_s_table_0_0_V_ram app_aes_process_5_s_table_0_0_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 8.416717 |
module app_aes_process_6_mux_42_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
input [7 : 0] din1,
input [7 : 0] din2,
input [7 : 0] din3,
input [1 : 0] din4,
output [7 : 0] dout
);
// puts internal signals
wire [1 : 0] sel;
// level 1 signals
wire [7 : 0] mux_1_0;
wire [7 : 0] mux_1_1;
// level 2 signals
wire [7 : 0] mux_2_0;
assign sel = din4;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
| 8.416717 |
module app_aes_process_6_s_table_0_0_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 8.416717 |
module app_aes_process_6_s_table_0_0_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
app_aes_process_6_s_table_0_0_V_ram app_aes_process_6_s_table_0_0_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 8.416717 |
module app_aes_process_7_mux_42_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
input [7 : 0] din1,
input [7 : 0] din2,
input [7 : 0] din3,
input [1 : 0] din4,
output [7 : 0] dout
);
// puts internal signals
wire [1 : 0] sel;
// level 1 signals
wire [7 : 0] mux_1_0;
wire [7 : 0] mux_1_1;
// level 2 signals
wire [7 : 0] mux_2_0;
assign sel = din4;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
| 8.416717 |
module app_aes_process_7_s_table_0_0_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 8.416717 |
module app_aes_process_7_s_table_0_0_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
app_aes_process_7_s_table_0_0_V_ram app_aes_process_7_s_table_0_0_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 8.416717 |
module app_aes_process_8_mux_42_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
input [7 : 0] din1,
input [7 : 0] din2,
input [7 : 0] din3,
input [1 : 0] din4,
output [7 : 0] dout
);
// puts internal signals
wire [1 : 0] sel;
// level 1 signals
wire [7 : 0] mux_1_0;
wire [7 : 0] mux_1_1;
// level 2 signals
wire [7 : 0] mux_2_0;
assign sel = din4;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
| 8.416717 |
module app_aes_process_8_s_table_0_0_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 8.416717 |
module app_aes_process_8_s_table_0_0_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
app_aes_process_8_s_table_0_0_V_ram app_aes_process_8_s_table_0_0_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 8.416717 |
module App_DataControl (
input in_rst,
input in_clk,
input in_clk_200M,
input in_clk_10M,
input in_clk_1k,
input in_trigger_n,
input [9:0] in_addata,
input in_request_n,
input [1:0] in_sample_rate_select,
//uart接口
output out_uart_txd,
output out_adc_clk,
output out_measure_hold_sig
);
//in_sample_rate_select[1] 1:1K实时采样 0:等效采样
//in_sample_rate_select[0] 1:10M等效采样 0:200M等效采样 in_sample_rate_select[1]为0时有效
wire measure_sig;
sample_control u_sample_control (
.in_rst(in_rst),
.in_clk(in_clk),
.in_clk_200M(in_clk_200M),
.in_clk_10M(in_clk_10M),
.in_clk_1k(in_clk_1k),
.in_trigger_n(in_trigger_n),
.in_request_n(in_request_n),
.in_sample_rate_select(in_sample_rate_select),
.out_adc_clk(out_adc_clk),
.out_measure_hold_sig(out_measure_hold_sig),
.out_measure_sig(measure_sig)
);
wire out_uart_send_sig;
wire uart_send_start;
wire [7:0] fifo_data2uart;
wire uart_start_sig;
fifo_control u_fifo_control (
.in_rst(in_rst),
.in_clk(in_clk),
.fifo_enable(~in_sample_rate_select[1]),
.measure_sig(measure_sig),
.measure_adc_clk(out_adc_clk),
.in_uart_send_sig(out_uart_send_sig),
.in_uart_send_start(uart_send_start),
.in_addata(in_addata[9:2]),
.out_fifo_data(fifo_data2uart),
.out_fifo_end_sig(uart_start_sig)
);
wire uart_force_send;
assign uart_force_send = in_sample_rate_select[1] ? in_clk_1k : 1'b0;
wire [7:0] uart_data;
assign uart_data = in_sample_rate_select[1] ? in_addata[9:2] : fifo_data2uart;
uart_send_control u_uart_send_control (
.in_rst(in_rst),
.in_clk(in_clk),
.in_uart_data(uart_data),
.in_uart_start_sig(uart_start_sig),
.uart_force_send(uart_force_send),
.out_uart_txd(out_uart_txd),
.out_uart_send_sig(out_uart_send_sig),
.out_uart_send_start(uart_send_start)
);
endmodule
| 7.188806 |
module App_FSK (
input in_clr
, input in_clk
, input [9:0] in_ADFIFO
, input in_rdFIFOempty
, input [4:0] DS18B20_Input
, output reg out_rdFIFOclk
, output reg out_rdFIFOreq
, output reg fsk_data
, output out_FSK
);
/* 寄存器配置 -------------------------*/
reg fsk_signal; //fsk_signal
reg [6:0] fsk_wave_cnt;
reg [3:0] fsk_switch_cnt;
reg [9:0] output_data;
reg [9:0] old_output_data;
reg [7:0] output_data_cnt;
reg [8:0] send_data_cnt;
/* 连接输出 ---------------------------*/
assign out_FSK = fsk_signal;
//assign fsk_data = output_data[0];
/* 运行线程 ---------------------------*/
always @(posedge in_clk or negedge in_clr)// or posedge sig_20msclk or posedge ack_20msclk
begin
if (in_clr == 0) begin
fsk_signal = 0;
output_data = 10'b1010101010; //01001010 10110101 01001010
output_data_cnt <= 0;
out_rdFIFOreq <= 0;
end else begin
//out_rdFIFOreq <= 1;
if(fsk_data==1) //1发送500k,高电平
begin
fsk_wave_cnt <= (fsk_wave_cnt + 1) % 100; //25 500k 1us切换一次电平 2us一个周期
end else begin
fsk_wave_cnt <= (fsk_wave_cnt + 1)%125; //20 400k 1.25us切换一次电平 2.5us一个周期
end
if(fsk_wave_cnt == 0) //计数半次波形结束，需要切换电平
begin
fsk_switch_cnt = fsk_switch_cnt + 1;
fsk_signal = ~fsk_signal;
if((fsk_data==0 && fsk_switch_cnt==8) || (fsk_data==1 && fsk_switch_cnt==10)) //一个位的数据发送结束，需要切换下一位数据
begin //10us 4/5次完整周期 100k
fsk_switch_cnt = 0;
output_data_cnt <= (output_data_cnt + 1) % 10;
//fsk_data = 1;
//fsk_data <= !fsk_data;
fsk_data <= output_data[0];
output_data <= (output_data >> 1);
if(output_data_cnt == 0) //一串数据发送结束,100us 10bit 10k 100us 0.1ms*160=16ms
begin
send_data_cnt <= (send_data_cnt + 1) % 100; //100 10ms/cycle
if(send_data_cnt < 1)//5
begin
output_data <= 10'b0111111111; //10'b0000000000;
out_rdFIFOreq <= 0;
end
else if(send_data_cnt < 2)//5
begin
output_data <= (DS18B20_Input<<5)|5'b10101;// 10101 10'b0101010101;//10'b0000000000;
out_rdFIFOreq <= 0;
end
else if(send_data_cnt < 82)//161 80
begin
if (in_rdFIFOempty) begin
output_data <= old_output_data;
out_rdFIFOreq <= 0;
end else begin
out_rdFIFOreq <= 1;
out_rdFIFOclk <= 1;
output_data <= in_ADFIFO; //10'b1110100001;//
old_output_data <= in_ADFIFO; //10'b1110100001;//
end
end else begin
output_data <= 10'b1111111111;
out_rdFIFOreq <= 0;
end
//out_rdFIFOreq <= 1;
//output_data = in_ADFIFO;
end
end
end
end
end
endmodule
| 6.654899 |
module app_gzip_mux_83_32_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
din7_WIDTH = 32,
din8_WIDTH = 32,
dout_WIDTH = 32
) (
input [31 : 0] din0,
input [31 : 0] din1,
input [31 : 0] din2,
input [31 : 0] din3,
input [31 : 0] din4,
input [31 : 0] din5,
input [31 : 0] din6,
input [31 : 0] din7,
input [ 2 : 0] din8,
output [31 : 0] dout
);
// puts internal signals
wire [ 2 : 0] sel;
// level 1 signals
wire [31 : 0] mux_1_0;
wire [31 : 0] mux_1_1;
wire [31 : 0] mux_1_2;
wire [31 : 0] mux_1_3;
// level 2 signals
wire [31 : 0] mux_2_0;
wire [31 : 0] mux_2_1;
// level 3 signals
wire [31 : 0] mux_3_0;
assign sel = din8;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
assign mux_1_2 = (sel[0] == 0) ? din4 : din5;
assign mux_1_3 = (sel[0] == 0) ? din6 : din7;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
assign mux_2_1 = (sel[1] == 0) ? mux_1_2 : mux_1_3;
// Generate level 3 logic
assign mux_3_0 = (sel[2] == 0) ? mux_2_0 : mux_2_1;
// output logic
assign dout = mux_3_0;
endmodule
| 6.755936 |
module app_stencil_mux_164_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
din7_WIDTH = 32,
din8_WIDTH = 32,
din9_WIDTH = 32,
din10_WIDTH = 32,
din11_WIDTH = 32,
din12_WIDTH = 32,
din13_WIDTH = 32,
din14_WIDTH = 32,
din15_WIDTH = 32,
din16_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
input [7 : 0] din1,
input [7 : 0] din2,
input [7 : 0] din3,
input [7 : 0] din4,
input [7 : 0] din5,
input [7 : 0] din6,
input [7 : 0] din7,
input [7 : 0] din8,
input [7 : 0] din9,
input [7 : 0] din10,
input [7 : 0] din11,
input [7 : 0] din12,
input [7 : 0] din13,
input [7 : 0] din14,
input [7 : 0] din15,
input [3 : 0] din16,
output [7 : 0] dout
);
// puts internal signals
wire [3 : 0] sel;
// level 1 signals
wire [7 : 0] mux_1_0;
wire [7 : 0] mux_1_1;
wire [7 : 0] mux_1_2;
wire [7 : 0] mux_1_3;
wire [7 : 0] mux_1_4;
wire [7 : 0] mux_1_5;
wire [7 : 0] mux_1_6;
wire [7 : 0] mux_1_7;
// level 2 signals
wire [7 : 0] mux_2_0;
wire [7 : 0] mux_2_1;
wire [7 : 0] mux_2_2;
wire [7 : 0] mux_2_3;
// level 3 signals
wire [7 : 0] mux_3_0;
wire [7 : 0] mux_3_1;
// level 4 signals
wire [7 : 0] mux_4_0;
assign sel = din16;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
assign mux_1_2 = (sel[0] == 0) ? din4 : din5;
assign mux_1_3 = (sel[0] == 0) ? din6 : din7;
assign mux_1_4 = (sel[0] == 0) ? din8 : din9;
assign mux_1_5 = (sel[0] == 0) ? din10 : din11;
assign mux_1_6 = (sel[0] == 0) ? din12 : din13;
assign mux_1_7 = (sel[0] == 0) ? din14 : din15;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
assign mux_2_1 = (sel[1] == 0) ? mux_1_2 : mux_1_3;
assign mux_2_2 = (sel[1] == 0) ? mux_1_4 : mux_1_5;
assign mux_2_3 = (sel[1] == 0) ? mux_1_6 : mux_1_7;
// Generate level 3 logic
assign mux_3_0 = (sel[2] == 0) ? mux_2_0 : mux_2_1;
assign mux_3_1 = (sel[2] == 0) ? mux_2_2 : mux_2_3;
// Generate level 4 logic
assign mux_4_0 = (sel[3] == 0) ? mux_3_0 : mux_3_1;
// output logic
assign dout = mux_4_0;
endmodule
| 7.001465 |
module app_stencil_mux_32_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
input [7 : 0] din1,
input [7 : 0] din2,
input [1 : 0] din3,
output [7 : 0] dout
);
// puts internal signals
wire [1 : 0] sel;
// level 1 signals
wire [7 : 0] mux_1_0;
wire [7 : 0] mux_1_1;
// level 2 signals
wire [7 : 0] mux_2_0;
assign sel = din3;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = din2;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
| 7.001465 |
module app_stencil_rows_buffer_0_0_red_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) begin
ram[addr1] <= d1;
end
end
end
endmodule
| 6.805174 |
module app_stencil_rows_buffer_0_0_red (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
app_stencil_rows_buffer_0_0_red_ram app_stencil_rows_buffer_0_0_red_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.d1(d1),
.we1(we1)
);
endmodule
| 6.805174 |
module app_sw_mux_32_16_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
dout_WIDTH = 32
) (
input [15 : 0] din0,
input [15 : 0] din1,
input [15 : 0] din2,
input [ 1 : 0] din3,
output [15 : 0] dout
);
// puts internal signals
wire [ 1 : 0] sel;
// level 1 signals
wire [15 : 0] mux_1_0;
wire [15 : 0] mux_1_1;
// level 2 signals
wire [15 : 0] mux_2_0;
assign sel = din3;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = din2;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
| 6.584762 |
module app_tb;
// 156.25 MHz clock for Ethernet PHY
reg clk_156;
initial begin
clk_156 = 0;
end
always #8 clk_156 = ~clk_156;
// reset
reg sys_rst;
initial begin
sys_rst = 1;
#100 sys_rst = 0;
end
// top
wire [63:0] xgmii_txd;
wire [ 7:0] xgmii_txc;
reg [ 3:0] dipsw;
wire [ 7:0] led;
app app_inst (
.sys_rst(sys_rst),
.xgmii_clk(clk_156),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.xgmii_rxd(xgmii_txd),
.xgmii_rxc(xgmii_txc),
.dipsw(dipsw),
.led(led)
);
initial begin
$dumpfile("./app_tb.vcd");
$dumpvars(0, app_tb);
#10 dipsw = 4'h0;
#300 #10 dipsw = 4'h1;
#10 dipsw = 4'h2;
#10 dipsw = 4'h3;
#10 dipsw = 4'h4;
#10 dipsw = 4'h5;
#10 dipsw = 4'h6;
#10 dipsw = 4'h7;
#10 dipsw = 4'h8;
#10 dipsw = 4'h9;
#10 dipsw = 4'ha;
#10 dipsw = 4'hb;
#10 dipsw = 4'hc;
#10 dipsw = 4'hd;
#10 dipsw = 4'he;
#10 dipsw = 4'hf;
#10 dipsw = 4'h0;
#1000 $finish;
end
endmodule
| 6.553104 |
module mux #(
parameter WIDTH = 8,
CHANNELS = 4,
SEL_WIDTH = 3
) // arg! this should be $clog2(CHANNELS) but Quartus does not accept that in a port declaration;
(
// input [$clog2(CHANNELS)-1:0] sel,
input [SEL_WIDTH-1:0] sel,
input [(CHANNELS*WIDTH)-1:0] in_bus,
output [WIDTH-1:0] out
);
genvar ig;
wire [WIDTH-1:0] input_array[0:CHANNELS-1];
assign out = input_array[sel];
generate
for (ig = 0; ig < CHANNELS; ig = ig + 1) begin : array_assignments
assign input_array[ig] = in_bus[(ig*WIDTH)+:WIDTH];
end
endgenerate
endmodule
| 8.575874 |
module debug (
input wire clk_in, // main tick
input wire clk_tx_in, // uart transmitter tick
input new_cycle_in, // assrted when we have to send the info
input wire [95:0] debug_data_in,
output wire uart_tx_o
);
reg [95:0] data;
reg [ 8:0] state;
reg [ 7:0] uart_data;
reg transmit, transmission_started, transmission_done, old_transmission_done;
wire uart_en;
assign uart_en = (state[3:0] == 4'h2) & (state [ 8:4] > 7'd1) & (state [ 8:4] <= 7'd31); // transmission
wire [7:0] hex = (data[95:92] > 4'h9) ? 8'd55 + data[95:92] : {4'h3, data[95:92]};
uart_tx tx (
.clk_in(clk_tx_in),
.data_in(uart_data),
.en_in(uart_en),
.tx_o(uart_tx_o)
);
/*
always @(posedge clk_in)
begin
if (new_cycle_in)
transmit <= 1'b1;
old_transmission_done <= transmission_done
if ((!old_transmission_done) & transmission_done) // on the rising edge
transmit <= 1'b0;
end
*/
always @(posedge clk_tx_in) // we do the work on the slow clock
begin
state <= state + 9'd1;
case (state[8:4])
5'd1: begin
uart_data <= 8'd10;
data <= debug_data_in;
end
5'd2: begin
uart_data <= hex;
data <= data << 4;
end
5'd3: uart_data <= 8'd32;
5'd4: begin
uart_data <= hex;
data <= data << 4;
end // PC
5'd5: begin
uart_data <= hex;
data <= data << 4;
end
5'd6: begin
uart_data <= hex;
data <= data << 4;
end
5'd7: uart_data <= 8'd32;
5'd9: begin
uart_data <= hex;
data <= data << 4;
end // OPCODE
5'd10: begin
uart_data <= hex;
data <= data << 4;
end // OPCODE
5'd11: begin
uart_data <= hex;
data <= data << 4;
end // OPCODE
5'd12: begin
uart_data <= hex;
data <= data << 4;
end // OPCODE
5'd13: begin
uart_data <= hex;
data <= data << 4;
end // OPCODE
5'd14: begin
uart_data <= hex;
data <= data << 4;
end // OPCODE
5'd15: begin
uart_data <= hex;
data <= data << 4;
end // OPCODE
5'd16: begin
uart_data <= hex;
data <= data << 4;
end // OPCODE
5'd17: uart_data <= 8'd32;
5'd19: begin
uart_data <= hex;
data <= data << 4;
end // HUB ADDR
5'd20: begin
uart_data <= hex;
data <= data << 4;
end // HUB ADDR
5'd21: begin
uart_data <= hex;
data <= data << 4;
end // HUB ADDR
5'd22: begin
uart_data <= hex;
data <= data << 4;
end // HUB ADDR
5'd23: uart_data <= 8'd32;
5'd24: begin
uart_data <= hex;
data <= data << 4;
end // HUB DATA
5'd25: begin
uart_data <= hex;
data <= data << 4;
end
5'd26: begin
uart_data <= hex;
data <= data << 4;
end
5'd27: begin
uart_data <= hex;
data <= data << 4;
end
5'd28: begin
uart_data <= hex;
data <= data << 4;
end
5'd29: begin
uart_data <= hex;
data <= data << 4;
end
5'd30: begin
uart_data <= hex;
data <= data << 4;
end
5'd31: begin
uart_data <= hex;
data <= data << 4;
end
endcase
end
initial state = 0;
endmodule
| 6.504557 |
module uart_tx (
input wire clk_in,
input wire [7:0] data_in,
input wire en_in,
output wire tx_o
);
reg [3:0] state;
reg [7:0] data;
assign tx_o = (state == 1) ? 1'b1 : state[3] ? data[0] : 1'b0;
always @(posedge clk_in) begin
case (state)
0: if (en_in) state <= 4'h1;
1: begin
data <= data_in;
state <= 4'h8;
end
8, 9, 10, 11, 12, 13, 14, 15: begin
state <= state + 4'h1;
data <= data >> 1;
end
endcase
end
initial state = 0;
endmodule
| 6.884683 |
module apb_tx_tb ();
/* ---------------
INPUT of apb_tx
--------------- */
reg clk;
reg rstn; // active LOW to reset
reg sel; // activate apb_tx module
reg set; // set DUTY & PERIOD. enable PWM
reg mode; // switch between 8 bit & 10 bit tx
reg [9:0] din; // input data for transmission
reg [19:0] baud; // bauddiv
/* ----------------
OUTPUT of apb_tx
---------------- */
wire tx_en;
wire tx_out;
/* ------------------
testbench variable
------------------ */
localparam period = 5;
localparam cycle = period * 2;
/* ---------------------
test module instances
--------------------- */
apb_tx tx (
// Inputs:
.clk (clk),
.rstn(rstn),
.sel (sel),
.set (set),
.mode(mode),
.din (din),
.baud(baud),
// Outputs:
.tx_en (tx_en),
.tx_out(tx_out)
);
/* ----------------
Clock Generation
---------------- */
initial clk <= 1'b1;
always #(period) clk <= ~clk;
/* -------------
Reset Control
------------- */
initial begin
rstn <= 1'b0;
sel <= 1'b0;
set <= 1'b0;
mode <= 1'b0;
#(cycle * 2) rstn <= 1'b1;
end
/* ----------
Simulation
---------- */
initial begin
#(cycle * 2) sel <= 1'b1;
mode <= 1'b0;
baud <= 20'd16;
din <= 10'b00_0011_0101;
#(cycle) sel <= 1'b0;
#(cycle) sel <= 1'b1;
set <= 1'b1;
#(cycle * 200) sel <= 1'b0;
set <= 1'b0;
din <= 10'bx;
baud <= 20'bx;
#(cycle) sel <= 1'b1;
mode <= 1'b1;
baud <= 20'd20;
din <= 10'b11000_01010;
#(cycle) sel <= 1'b0;
#(cycle) sel <= 1'b1;
set <= 1'b1;
#(cycle * 300) sel <= 1'b0;
set <= 1'b0;
din <= 10'bx;
baud <= 20'bx;
#(cycle * 10) $finish();
end
endmodule
| 9.311727 |
module TriangleChan (
input clk,
input ce,
input reset,
input [1:0] Addr,
input [7:0] DIN,
input MW,
input LenCtr_Clock,
input LinCtr_Clock,
input Enabled,
input [7:0] LenCtr_In,
output [3:0] Sample,
output IsNonZero
);
//
reg [10:0] Period, TimerCtr;
reg [4:0] SeqPos;
//
// Linear counter state
reg [6:0] LinCtrPeriod, LinCtr;
reg LinCtrl, LinHalt;
wire LinCtrZero = (LinCtr == 0);
//
// Length counter state
reg [7:0] LenCtr;
wire LenCtrHalt = LinCtrl; // Aliased bit
wire LenCtrZero = (LenCtr == 0);
assign IsNonZero = !LenCtrZero;
//
always @(posedge clk)
if (reset) begin
Period <= 0;
TimerCtr <= 0;
SeqPos <= 0;
LinCtrPeriod <= 0;
LinCtr <= 0;
LinCtrl <= 0;
LinHalt <= 0;
LenCtr <= 0;
end else if (ce) begin
// Check if writing to the regs of this channel
if (MW) begin
case (Addr)
0: begin
LinCtrl <= DIN[7];
LinCtrPeriod <= DIN[6:0];
end
2: begin
Period[7:0] <= DIN;
end
3: begin
Period[10:8] <= DIN[2:0];
LenCtr <= LenCtr_In;
LinHalt <= 1;
end
endcase
end
// Count down the period timer...
if (TimerCtr == 0) begin
TimerCtr <= Period;
end else begin
TimerCtr <= TimerCtr - 1;
end
//
// Clock the length counter?
if (LenCtr_Clock && !LenCtrZero && !LenCtrHalt) begin
LenCtr <= LenCtr - 1;
end
//
// Clock the linear counter?
if (LinCtr_Clock) begin
if (LinHalt) LinCtr <= LinCtrPeriod;
else if (!LinCtrZero) LinCtr <= LinCtr - 1;
if (!LinCtrl) LinHalt <= 0;
end
//
// Length counter forced to zero if disabled.
if (!Enabled) LenCtr <= 0;
//
// Clock the sequencer position
if (TimerCtr == 0 && !LenCtrZero && !LinCtrZero) SeqPos <= SeqPos + 1;
end
// Generate the output
assign Sample = SeqPos[3:0] ^ {4{~SeqPos[4]}};
//
endmodule
| 7.276593 |
module NoiseChan (
input clk,
input ce,
input reset,
input [1:0] Addr,
input [7:0] DIN,
input MW,
input LenCtr_Clock,
input Env_Clock,
input Enabled,
input [7:0] LenCtr_In,
output [3:0] Sample,
output IsNonZero
);
//
// Envelope volume
reg EnvLoop, EnvDisable, EnvDoReset;
reg [3:0] Volume, Envelope, EnvDivider;
// Length counter
wire LenCtrHalt = EnvLoop; // Aliased bit
reg [7:0] LenCtr;
//
reg ShortMode;
reg [14:0] Shift = 1;
assign IsNonZero = (LenCtr != 0);
//
// Period stuff
reg [3:0] Period;
reg [11:0] NoisePeriod, TimerCtr;
always @* begin
case (Period)
0: NoisePeriod = 12'h004;
1: NoisePeriod = 12'h008;
2: NoisePeriod = 12'h010;
3: NoisePeriod = 12'h020;
4: NoisePeriod = 12'h040;
5: NoisePeriod = 12'h060;
6: NoisePeriod = 12'h080;
7: NoisePeriod = 12'h0A0;
8: NoisePeriod = 12'h0CA;
9: NoisePeriod = 12'h0FE;
10: NoisePeriod = 12'h17C;
11: NoisePeriod = 12'h1FC;
12: NoisePeriod = 12'h2FA;
13: NoisePeriod = 12'h3F8;
14: NoisePeriod = 12'h7F2;
15: NoisePeriod = 12'hFE4;
endcase
end
//
always @(posedge clk)
if (reset) begin
EnvLoop <= 0;
EnvDisable <= 0;
EnvDoReset <= 0;
Volume <= 0;
Envelope <= 0;
EnvDivider <= 0;
LenCtr <= 0;
ShortMode <= 0;
Shift <= 1;
Period <= 0;
TimerCtr <= 0;
end else if (ce) begin
// Check if writing to the regs of this channel
if (MW) begin
case (Addr)
0: begin
EnvLoop <= DIN[5];
EnvDisable <= DIN[4];
Volume <= DIN[3:0];
end
2: begin
ShortMode <= DIN[7];
Period <= DIN[3:0];
end
3: begin
LenCtr <= LenCtr_In;
EnvDoReset <= 1;
end
endcase
end
// Count down the period timer...
if (TimerCtr == 0) begin
TimerCtr <= NoisePeriod;
// Clock the shift register. Use either
// bit 1 or 6 as the tap.
Shift <= {Shift[0] ^ (ShortMode ? Shift[6] : Shift[1]), Shift[14:1]};
end else begin
TimerCtr <= TimerCtr - 1;
end
// Clock the length counter?
if (LenCtr_Clock && LenCtr != 0 && !LenCtrHalt) begin
LenCtr <= LenCtr - 1;
end
// Clock the envelope generator?
if (Env_Clock) begin
if (EnvDoReset) begin
EnvDivider <= Volume;
Envelope <= 15;
EnvDoReset <= 0;
end else if (EnvDivider == 0) begin
EnvDivider <= Volume;
if (Envelope != 0) Envelope <= Envelope - 1;
else if (EnvLoop) Envelope <= 15;
end else EnvDivider <= EnvDivider - 1;
end
if (!Enabled) LenCtr <= 0;
end
// Produce the output signal
assign Sample = (LenCtr == 0 || Shift[0]) ? 0 : (EnvDisable ? Volume : Envelope);
endmodule
| 6.570767 |
module apu_div #(
parameter PERIOD_BITS = 16
) (
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire pulse_in, // input pulse
input wire reload_in, // reset counter to period_in (no pulse_out generated)
input wire [PERIOD_BITS-1:0] period_in, // new period value
output wire pulse_out // divided output pulse
);
reg [PERIOD_BITS-1:0] q_cnt;
wire [PERIOD_BITS-1:0] d_cnt;
always @(posedge clk_in) begin
if (rst_in) q_cnt <= 0;
else q_cnt <= d_cnt;
end
assign d_cnt = (reload_in || (pulse_in && (q_cnt == 0))) ? period_in :
(pulse_in) ? q_cnt - 1'h1 : q_cnt;
assign pulse_out = pulse_in && (q_cnt == 0);
endmodule
| 7.631895 |
module apu_envelope_generator (
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire eg_pulse_in, // 1 clk pulse for every env gen update
input wire [5:0] env_in, // envelope value (e.g., via $4000)
input wire env_wr_in, // envelope value write
input wire env_restart, // envelope restart
output wire [3:0] env_out // output volume
);
reg [5:0] q_reg;
wire [5:0] d_reg;
reg [3:0] q_cnt, d_cnt;
reg q_start_flag, d_start_flag;
always @(posedge clk_in) begin
if (rst_in) begin
q_reg <= 6'h00;
q_cnt <= 4'h0;
q_start_flag <= 1'b0;
end else begin
q_reg <= d_reg;
q_cnt <= d_cnt;
q_start_flag <= d_start_flag;
end
end
reg divider_pulse_in;
reg divider_reload;
wire divider_pulse_out;
apu_div #(
.PERIOD_BITS(4)
) divider (
.clk_in(clk_in),
.rst_in(rst_in),
.pulse_in(divider_pulse_in),
.reload_in(divider_reload),
.period_in(q_reg[3:0]),
.pulse_out(divider_pulse_out)
);
always @* begin
d_cnt = q_cnt;
d_start_flag = q_start_flag;
divider_pulse_in = 1'b0;
divider_reload = 1'b0;
// When the divider outputs a clock, one of two actions occurs: If the counter is non-zero, it
// is decremented, otherwise if the loop flag is set, the counter is loaded with 15.
if (divider_pulse_out) begin
divider_reload = 1'b1;
if (q_cnt != 4'h0) d_cnt = q_cnt - 4'h1;
else if (q_reg[5]) d_cnt = 4'hF;
end
// When clocked by the frame counter, one of two actions occurs: if the start flag is clear,
// the divider is clocked, otherwise the start flag is cleared, the counter is loaded with 15,
// and the divider's period is immediately reloaded.
if (eg_pulse_in) begin
if (q_start_flag == 1'b0) begin
divider_pulse_in = 1'b1;
end else begin
d_start_flag = 1'b0;
d_cnt = 4'hF;
end
end
if (env_restart) d_start_flag = 1'b1;
end
assign d_reg = (env_wr_in) ? env_in : q_reg;
// The envelope unit's volume output depends on the constant volume flag: if set, the envelope
// parameter directly sets the volume, otherwise the counter's value is the current volume.
assign env_out = (q_reg[4]) ? q_reg[3:0] : q_cnt;
endmodule
| 7.106507 |
module NES_WRAM (
M2,
RnW,
n_RES,
Addr,
Data
);
input M2;
input RnW;
input n_RES;
input [15:0] Addr;
inout [7:0] Data;
wire wram_sel;
assign wram_sel = ~|Addr[15:11];
assign Data = (wram_sel & RnW) ? 8'b0 : 8'bz;
endmodule
| 6.556247 |
module apu_triangle (
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire en_in, // enable (via $4015)
input wire cpu_cycle_pulse_in, // 1 clk pulse on every cpu cycle
input wire lc_pulse_in, // 1 clk pulse for every length counter decrement
input wire eg_pulse_in, // 1 clk pulse for every env gen update
input wire [1:0] a_in, // control register addr (i.e. $400C - $400F)
input wire [7:0] d_in, // control register write value
input wire wr_in, // enable control register write
output wire [3:0] triangle_out, // triangle channel output
output wire active_out // triangle channel active (length counter > 0)
);
//
// Timer
//
reg [10:0] q_timer_period;
wire [10:0] d_timer_period;
wire timer_pulse;
always @(posedge clk_in) begin
if (rst_in) q_timer_period <= 11'h000;
else q_timer_period <= d_timer_period;
end
apu_div #(
.PERIOD_BITS(11)
) timer (
.clk_in(clk_in),
.rst_in(rst_in),
.pulse_in(cpu_cycle_pulse_in),
.reload_in(1'b0),
.period_in(q_timer_period),
.pulse_out(timer_pulse)
);
assign d_timer_period = (wr_in && (a_in == 2'b10)) ? { q_timer_period[10:8], d_in[7:0] } :
(wr_in && (a_in == 2'b11)) ? { d_in[2:0], q_timer_period[7:0] } :
q_timer_period;
//
// Linear Counter
//
reg q_linear_counter_halt;
wire d_linear_counter_halt;
reg [7:0] q_linear_counter_cntl;
wire [7:0] d_linear_counter_cntl;
reg [6:0] q_linear_counter_val;
wire [6:0] d_linear_counter_val;
wire linear_counter_en;
always @(posedge clk_in) begin
if (rst_in) begin
q_linear_counter_halt <= 1'b0;
q_linear_counter_cntl <= 8'h00;
q_linear_counter_val <= 7'h00;
end else begin
q_linear_counter_halt <= d_linear_counter_halt;
q_linear_counter_cntl <= d_linear_counter_cntl;
q_linear_counter_val <= d_linear_counter_val;
end
end
assign d_linear_counter_cntl = (wr_in && (a_in == 2'b00)) ? d_in : q_linear_counter_cntl;
assign d_linear_counter_val =
(eg_pulse_in && q_linear_counter_halt) ? q_linear_counter_cntl[6:0] :
(eg_pulse_in && (q_linear_counter_val != 7'h00)) ? q_linear_counter_val - 7'h01 :
q_linear_counter_val;
assign d_linear_counter_halt =
(wr_in && (a_in == 2'b11)) ? 1'b1 :
(eg_pulse_in && !q_linear_counter_cntl[7]) ? 1'b0 :
q_linear_counter_halt;
assign linear_counter_en = |q_linear_counter_val;
//
// Length Counter
//
reg q_length_counter_halt;
wire d_length_counter_halt;
wire length_counter_wr;
wire length_counter_en;
always @(posedge clk_in) begin
if (rst_in) q_length_counter_halt <= 1'b0;
else q_length_counter_halt <= d_length_counter_halt;
end
apu_length_counter length_counter (
.clk_in(clk_in),
.rst_in(rst_in),
.en_in(en_in),
.halt_in(q_length_counter_halt),
.length_pulse_in(lc_pulse_in),
.length_in(d_in[7:3]),
.length_wr_in(length_counter_wr),
.en_out(length_counter_en)
);
assign d_length_counter_halt = (wr_in && (a_in == 2'b00)) ? d_in[7] : q_length_counter_halt;
assign length_counter_wr = wr_in && (a_in == 2'b11);
//
// Sequencer
//
reg [4:0] q_seq;
wire [4:0] d_seq;
wire [3:0] seq_out;
always @(posedge clk_in) begin
if (rst_in) q_seq <= 5'h0;
else q_seq <= d_seq;
end
assign d_seq = (active_out && timer_pulse) ? q_seq + 5'h01 : q_seq;
assign seq_out = (q_seq[4]) ? q_seq[3:0] : ~q_seq[3:0];
assign active_out = linear_counter_en && length_counter_en;
assign triangle_out = seq_out;
endmodule
| 6.831666 |
module ApvDataFifo_1024x12 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw
);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
output rdfull;
output [9:0] rdusedw;
output wrempty;
output wrfull;
output [9:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire sub_wire1;
wire [9:0] sub_wire2;
wire sub_wire3;
wire sub_wire4;
wire [11:0] sub_wire5;
wire [9:0] sub_wire6;
wire rdfull = sub_wire0;
wire rdempty = sub_wire1;
wire [9:0] wrusedw = sub_wire2[9:0];
wire wrfull = sub_wire3;
wire wrempty = sub_wire4;
wire [11:0] q = sub_wire5[11:0];
wire [9:0] rdusedw = sub_wire6[9:0];
dcfifo dcfifo_component (
.wrclk(wrclk),
.rdreq(rdreq),
.aclr(aclr),
.rdclk(rdclk),
.wrreq(wrreq),
.data(data),
.rdfull(sub_wire0),
.rdempty(sub_wire1),
.wrusedw(sub_wire2),
.wrfull(sub_wire3),
.wrempty(sub_wire4),
.q(sub_wire5),
.rdusedw(sub_wire6)
);
defparam dcfifo_component.intended_device_family = "Arria GX", dcfifo_component.lpm_numwords =
1024, dcfifo_component.lpm_showahead = "ON", dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 12, dcfifo_component.lpm_widthu = 10,
dcfifo_component.overflow_checking = "ON", dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF", dcfifo_component.wrsync_delaypipe = 4;
endmodule
| 7.338939 |
module ApvDataFifo_1024x12 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw
);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
output rdfull;
output [9:0] rdusedw;
output wrempty;
output wrfull;
output [9:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 7.338939 |
module ApvDataFifo_1024x13 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw
);
input aclr;
input [12:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [12:0] q;
output rdempty;
output rdfull;
output [9:0] rdusedw;
output wrempty;
output wrfull;
output [9:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire sub_wire1;
wire [9:0] sub_wire2;
wire sub_wire3;
wire sub_wire4;
wire [12:0] sub_wire5;
wire [9:0] sub_wire6;
wire rdfull = sub_wire0;
wire rdempty = sub_wire1;
wire [9:0] wrusedw = sub_wire2[9:0];
wire wrfull = sub_wire3;
wire wrempty = sub_wire4;
wire [12:0] q = sub_wire5[12:0];
wire [9:0] rdusedw = sub_wire6[9:0];
dcfifo dcfifo_component (
.wrclk(wrclk),
.rdreq(rdreq),
.aclr(aclr),
.rdclk(rdclk),
.wrreq(wrreq),
.data(data),
.rdfull(sub_wire0),
.rdempty(sub_wire1),
.wrusedw(sub_wire2),
.wrfull(sub_wire3),
.wrempty(sub_wire4),
.q(sub_wire5),
.rdusedw(sub_wire6)
);
defparam dcfifo_component.intended_device_family = "Arria GX", dcfifo_component.lpm_numwords =
1024, dcfifo_component.lpm_showahead = "ON", dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 13, dcfifo_component.lpm_widthu = 10,
dcfifo_component.overflow_checking = "ON", dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF", dcfifo_component.wrsync_delaypipe = 4;
endmodule
| 7.338939 |
module ApvDataFifo_1024x13 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw
);
input aclr;
input [12:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [12:0] q;
output rdempty;
output rdfull;
output [9:0] rdusedw;
output wrempty;
output wrfull;
output [9:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 7.338939 |
module ApvDataFifo_2048x12 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw
);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
output rdfull;
output [10:0] rdusedw;
output wrempty;
output wrfull;
output [10:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire sub_wire1;
wire [10:0] sub_wire2;
wire sub_wire3;
wire sub_wire4;
wire [11:0] sub_wire5;
wire [10:0] sub_wire6;
wire rdfull = sub_wire0;
wire rdempty = sub_wire1;
wire [10:0] wrusedw = sub_wire2[10:0];
wire wrfull = sub_wire3;
wire wrempty = sub_wire4;
wire [11:0] q = sub_wire5[11:0];
wire [10:0] rdusedw = sub_wire6[10:0];
dcfifo dcfifo_component (
.wrclk(wrclk),
.rdreq(rdreq),
.aclr(aclr),
.rdclk(rdclk),
.wrreq(wrreq),
.data(data),
.rdfull(sub_wire0),
.rdempty(sub_wire1),
.wrusedw(sub_wire2),
.wrfull(sub_wire3),
.wrempty(sub_wire4),
.q(sub_wire5),
.rdusedw(sub_wire6)
);
defparam dcfifo_component.intended_device_family = "Arria GX", dcfifo_component.lpm_numwords =
2048, dcfifo_component.lpm_showahead = "ON", dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 12, dcfifo_component.lpm_widthu = 11,
dcfifo_component.overflow_checking = "ON", dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF", dcfifo_component.wrsync_delaypipe = 4;
endmodule
| 6.903746 |
module ApvDataFifo_2048x12 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw
);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
output rdfull;
output [10:0] rdusedw;
output wrempty;
output wrfull;
output [10:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.903746 |
module ap_adder (
input [15:0] y,
output [31:0] s
);
wire [3:0] cout;
assign s[0] = y[0];
genvar i;
generate
for (i = 1; i < 5; i = i + 1) begin
if (i == 1)
ap_adder_u ap_adder_unit (
.y2 (y[i*2]),
.y1 (y[i*2-1]),
.y0 (y[i*2-2]),
.cin (1'b0),
.s1 (s[i*2-1]),
.s2 (s[i*2]),
.cout(cout[i-1])
);
else
ap_adder_u ap_adder_unit (
.y2 (y[i*2]),
.y1 (y[i*2-1]),
.y0 (y[i*2-2]),
.cin (cout[i-2]),
.s1 (s[i*2-1]),
.s2 (s[i*2]),
.cout(cout[i-1])
);
end
endgenerate
rca #(
.width(7)
) u_rca (
.op1 (y[14:8]),
.op2 (y[15:9]),
.cin (cout[3]),
.sum (s[15:9]),
.cout(s[16])
);
assign s[31:17] = {15{y[15]}};
endmodule
| 7.087331 |
module ap_adder_u (
input y2,
input y1,
input y0,
input cin,
output s1,
output s2,
output cout
);
assign cout = y1;
assign s2 = y2;
assign s1 = cin ^ y1 ^ y0;
endmodule
| 8.009772 |
module ap_comp (
input wire x1,
x2,
x3,
x4,
output wire s,
c
);
assign c = (x1 & x2) || (x1 & x3) || (x1 & x4) || (x2 & x3) || (x2 & x4);
assign s = (x1 ^ x2) ^ (x3 || x4);
endmodule
| 6.890932 |
module aq_axi4ls (
input RST_N,
input CLK,
// AXI4 Lite Interface
input ARESETN,
input ACLK,
// Write Address Channel
input [31:0] AWADDR,
input [3:0] AWCACHE, // 4'b0011
input [2:0] AWPROT, // 3'b000
input AWVALID,
output AWREADY,
// Write Data Channel
input [31:0] WDATA,
input [3:0] WSTRB,
input WVALID,
output WREADY,
// Write Response Channel
output BVALID,
input BREADY,
output [1:0] BRESP,
// Read Address Channel
input [31:0] ARADDR,
input [3:0] ARCACHE, // 4'b0011
input [2:0] ARPROT, // 3'b000
input ARVALID,
output ARREADY,
// Read Data Channel
output [31:0] RDATA,
output [1:0] RRESP,
output RVALID,
input RREADY,
// Local Interface
output LOCAL_CS,
output LOCAL_RNW,
input LOCAL_ACK,
output [31:0] LOCAL_ADDR,
output [3:0] LOCAL_BE,
output [31:0] LOCAL_WDATA,
input [31:0] LOCAL_RDATA
);
/*
CACHE[3:0]
WA RA C B
0 0 0 0 Noncacheable and nonbufferable
0 0 0 1 Bufferable only
0 0 1 0 Cacheable, but do not allocate
0 0 1 1 Cacheable and Bufferable, but do not allocate
0 1 1 0 Cacheable write-through, allocate on reads only
0 1 1 1 Cacheable write-back, allocate on reads only
1 0 1 0 Cacheable write-through, allocate on write only
1 0 1 1 Cacheable write-back, allocate on writes only
1 1 1 0 Cacheable write-through, allocate on both reads and writes
1 1 1 1 Cacheable write-back, allocate on both reads and writes
PROR
[2]:0:Data Access
1:Instruction Access
[1]:0:Secure Access
1:NoSecure Access
[0]:0:Privileged Access
1:Normal Access
RESP
00: OK
01: EXOK
10: SLVERR
11: DECERR
*/
parameter S_IDLE = 2'd0;
parameter S_WRITE = 2'd1;
parameter S_WRITE2 = 2'd2;
parameter S_READ = 2'd3;
reg [1:0] state;
reg reg_rnw;
reg [31:0] reg_adrs, reg_wdata;
reg [3:0] reg_be;
always @(posedge ACLK or negedge ARESETN) begin
if (!ARESETN) begin
state <= S_IDLE;
reg_rnw <= 1'b0;
reg_adrs <= 32'd0;
reg_wdata <= 32'd0;
reg_be <= 4'd0;
end else begin
case (state)
S_IDLE: begin
if (AWVALID) begin
reg_rnw <= 1'b0;
reg_adrs <= AWADDR;
state <= S_WRITE;
end else if (ARVALID) begin
reg_rnw <= 1'b1;
reg_adrs <= ARADDR;
end
end
S_WRITE: begin
if (WVALID) begin
state <= S_WRITE2;
reg_wdata <= WDATA;
reg_be <= WSTRB;
end
end
S_WRITE2: begin
if (LOCAL_ACK & BREADY) begin
state <= S_IDLE;
end
end
S_READ: begin
if (LOCAL_ACK & RREADY) begin
state <= S_IDLE;
end
end
default: begin
state <= S_IDLE;
end
endcase
end
end
// Local Interface
assign LOCAL_CS = ((state == S_WRITE2) ? 1'b1 : 1'b0) | ((state == S_READ) ? 1'b1 : 1'b0) | 1'b0;
assign LOCAL_RNW = reg_rnw;
assign LOCAL_ADRS = reg_adrs;
assign LOCAL_BE = reg_be;
assign LOCAL_WDATA = reg_wdata;
// Write Channel
assign AWREADY = (state == S_WRITE) ? AWVALID : 1'b0;
assign WREADY = (state == S_WRITE) ? WVALID : 1'b0;
assign BVALID = (state == S_WRITE2) ? LOCAL_ACK : 1'b0;
assign BRESP = 2'b00;
// Read Channel
assign ARREADY = (state == S_READ) ? ARVALID : 1'b0;
assign RVALID = (state == S_READ) ? LOCAL_ACK : 1'b0;
assign RRESP = 2'b00;
assign RDATA = (state == S_READ) ? LOCAL_RDATA : 32'd0;
endmodule
| 8.442275 |
module aq_axis_djpeg (
// --------------------------------------------------
// AXI4 Lite Interface
// --------------------------------------------------
input ARESETN,
input ACLK,
// Write Address Channel
input [31:0] S_AXI_AWADDR,
input [ 3:0] S_AXI_AWCACHE,
input [ 2:0] S_AXI_AWPROT,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
// Write Data Channel
input [31:0] S_AXI_WDATA,
input [ 3:0] S_AXI_WSTRB,
input S_AXI_WVALID,
output S_AXI_WREADY,
// Write Response Channel
output S_AXI_BVALID,
input S_AXI_BREADY,
output [1:0] S_AXI_BRESP,
// Read Address Channel
input [31:0] S_AXI_ARADDR,
input [ 3:0] S_AXI_ARCACHE,
input [ 2:0] S_AXI_ARPROT,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
// Read Data Channel
output [31:0] S_AXI_RDATA,
output [ 1:0] S_AXI_RRESP,
output S_AXI_RVALID,
input S_AXI_RREADY,
// AXI Stream input
input TCLK,
input [31:0] S_AXIS_TDATA,
input S_AXIS_TKEEP,
input S_AXIS_TLAST,
output S_AXIS_TREADY,
input [ 3:0] S_AXIS_TSTRB,
input S_AXIS_TVALID,
// AXI Stream output
output [31:0] M_AXIS_TDATA,
output [47:0] M_AXIS_TUSER,
output M_AXIS_TKEEP,
output M_AXIS_TLAST,
input M_AXIS_TREADY,
output [ 3:0] M_AXIS_TSTRB,
output M_AXIS_TVALID
);
wire JpegDecodeRst, JpegDecodeIdle, JpegProgressive;
wire [15:0] OutWidth, OutHeight, OutPixelX, OutPixelY;
wire [7:0] OutR, OutG, OutB;
aq_axis_djpeg_ctrl u_aq_axis_djpeg_ctrl (
.ARESETN(ARESETN),
.ACLK (ACLK),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWCACHE(S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_ARADDR (S_AXI_ARADDR),
.S_AXI_ARCACHE(S_AXI_ARCACHE),
.S_AXI_ARPROT (S_AXI_ARPROT),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RDATA (S_AXI_RDATA),
.S_AXI_RRESP (S_AXI_RRESP),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
.LOGIC_RST (JpegDecodeRst),
.LOGIC_IDLE (JpegDecodeIdle),
.LOGIC_PROGRESSIVE(JpegProgressive),
.WIDTH (OutWidth[15:0]),
.HEIGHT(OutHeight[15:0]),
.PIXELX(OutPixelX[15:0]),
.PIXELY(OutPixelY[15:0])
);
wire JpegInHandshake;
assign JpegInHandshake = S_AXIS_TVALID & S_AXIS_TREADY;
aq_djpeg u_aq_djpeg (
.rst(~JpegDecodeRst),
.clk(TCLK),
// From FIFO
.DataIn (S_AXIS_TDATA[31:0]),
.DataInEnable(JpegInHandshake),
.DataInRead (),
.DataInReq (S_AXIS_TREADY),
.JpegDecodeIdle (JpegDecodeIdle),
.JpegProgressive(JpegProgressive),
.OutReady (M_AXIS_TREADY),
.OutEnable(M_AXIS_TVALID),
.OutWidth (OutWidth[15:0]),
.OutHeight(OutHeight[15:0]),
.OutPixelX(OutPixelX[15:0]),
.OutPixelY(OutPixelY[15:0]),
.OutR (OutR[7:0]),
.OutG (OutG[7:0]),
.OutB (OutB[7:0])
);
assign M_AXIS_TKEEP = 1'b0;
assign M_AXIS_TLAST = (OutPixelX == (OutWidth - 1)) && (OutPixelY == (OutHeight - 1));
assign M_AXIS_TSTRB = 4'b1111;
assign M_AXIS_TDATA[31:0] = {8'd0, OutR[7:0], OutG[7:0], OutB[7:0]};
assign M_AXIS_TUSER[47:0] = {OutWidth[15:0], OutPixelY[15:0], OutPixelX[15:0]};
endmodule
| 6.753622 |
module aq_axis_reduce (
// AXI4 Lite Interface
input ARESETN,
input ACLK,
// Write Address Channel
input [31:0] S_AXI_AWADDR,
input [ 3:0] S_AXI_AWCACHE,
input [ 2:0] S_AXI_AWPROT,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
// Write Data Channel
input [31:0] S_AXI_WDATA,
input [ 3:0] S_AXI_WSTRB,
input S_AXI_WVALID,
output S_AXI_WREADY,
// Write Response Channel
output S_AXI_BVALID,
input S_AXI_BREADY,
output [1:0] S_AXI_BRESP,
// Read Address Channel
input [31:0] S_AXI_ARADDR,
input [ 3:0] S_AXI_ARCACHE,
input [ 2:0] S_AXI_ARPROT,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
// Read Data Channel
output [31:0] S_AXI_RDATA,
output [ 1:0] S_AXI_RRESP,
output S_AXI_RVALID,
input S_AXI_RREADY,
// AXI Stream input
input S_AXIS_TCLK,
input [31:0] S_AXIS_TDATA,
input S_AXIS_TKEEP,
input S_AXIS_TLAST,
output S_AXIS_TREADY,
input [ 3:0] S_AXIS_TSTRB,
input S_AXIS_TVALID,
// AXI Stream output
output M_AXIS_TCLK,
output [31:0] M_AXIS_TDATA,
output M_AXIS_TKEEP,
output M_AXIS_TLAST,
input M_AXIS_TREADY,
output [ 3:0] M_AXIS_TSTRB,
output M_AXIS_TVALID,
input FSYNC_IN,
output FSYNC_OUT
);
wire [15:0] org_x, org_y, cnv_x, cnv_y;
aq_axils_reduce u_aq_axils_reduce (
// AXI4 Lite Interface
.ARESETN(ARESETN),
.ACLK (ACLK),
// Write Address Channel
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWCACHE(S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_AWREADY(S_AXI_AWREADY),
// Write Data Channel
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
// Write Response Channel
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_BRESP (S_AXI_BRESP),
// Read Address Channel
.S_AXI_ARADDR (S_AXI_ARADDR),
.S_AXI_ARCACHE(S_AXI_ARCACHE),
.S_AXI_ARPROT (S_AXI_ARPROT),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
// Read Data Channel
.S_AXI_RDATA (S_AXI_RDATA),
.S_AXI_RRESP (S_AXI_RRESP),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
// Local Interface
.ORG_X(org_x),
.ORG_Y(org_y),
.CNV_X(cnv_x),
.CNV_Y(cnv_y)
);
wire din_we, dout_oe;
assign din_we = (S_AXIS_TVALID & |(S_AXIS_TSTRB)) ? 1'b1 : 1'b0;
aq_reduce u_aq_reduce (
.RST_N(ARESETN),
.CLK (S_AXIS_TCLK),
.ORG_X(org_x),
.ORG_Y(org_y),
.CNV_X(cnv_x),
.CNV_Y(cnv_y),
.DIN_WE (din_we),
.DIN_FSYNC(FSYNC_IN),
.DIN (S_AXIS_TDATA),
.DOUT_OE (dout_oe),
.DOUT_FSYNC(FSYNC_OUT),
.DOUT_LAST (M_AXIS_TLAST),
.DOUT (M_AXIS_TDATA)
);
assign S_AXIS_TREADY = 1'b1;
assign M_AXIS_TCLK = S_AXIS_TCLK;
assign M_AXIS_TKEEP = 1'b0;
assign M_AXIS_TSTRB = {dout_oe, dout_oe, dout_oe, dout_oe};
assign M_AXIS_TVALID = (M_AXIS_TREADY & dout_oe) ? 1'b1 : 1'b0;
endmodule
| 7.161924 |
module aq_axis_t32f64 (
input ARESETN,
input I_AXIS_TCLK,
input [64:0] I_AXIS_TDATA,
input I_AXIS_TVALID,
output I_AXIS_TREADY,
input [ 7:0] I_AXIS_TSTRB,
input I_AXIS_TKEEP,
input I_AXIS_TLAST,
output O_AXIS_TCLK,
output [31:0] O_AXIS_TDATA,
output O_AXIS_TVALID,
input O_AXIS_TREADY,
output [ 3:0] O_AXIS_TSTRB,
output O_AXIS_TKEEP,
output O_AXIS_TLAST
);
reg odd_even;
reg [31:0] buff;
reg [ 3:0] strb;
always @(posedge I_AXIS_TCLK or negedge ARESETN) begin
if (!ARESETN) begin
odd_even <= 1'b0;
buff <= 32'd0;
strb <= 4'd0;
end else begin
if (I_AXIS_TVALID | (!I_AXIS_TVALID & O_AXIS_TREADY)) begin
odd_even <= ~odd_even;
end
if (!odd_even) begin
buff <= I_AXIS_TDATA[63:32];
strb <= I_AXIS_TSTRB[7:4];
end
end
end
assign O_AXIS_TDATA[31:0] = (odd_even) ? buff : I_AXIS_TDATA[31:0];
assign O_AXIS_TSTRB[3:0] = (odd_even) ? strb : I_AXIS_TSTRB[3:0];
assign O_AXIS_TVALID = I_AXIS_TVALID;
assign O_AXIS_TLAST = I_AXIS_TLAST;
assign O_AXIS_TKEEP = I_AXIS_TKEEP;
assign O_AXIS_TCLK = I_AXIS_TCLK;
assign I_AXIS_TREADY = O_AXIS_TREADY & ~odd_even;
endmodule
| 7.622882 |
module aq_axi_djpeg_ctl (
input RST_N,
input CLK,
input LOCAL_CS,
input LOCAL_RNW,
output LOCAL_ACK,
input [31:0] LOCAL_ADDR,
input [ 3:0] LOCAL_BE,
input [31:0] LOCAL_WDATA,
output [31:0] LOCAL_RDATA,
output LOGIC_RST,
input LOGIC_IDLE,
input [15:0] WIDTH,
input [15:0] HEIGHT,
input [15:0] PIXELX,
input [15:0] PIXELY,
output [31:0] DEBUG
);
localparam A_STATUS = 8'h00;
localparam A_SIZE = 8'h04;
localparam A_PIXEL = 8'h08;
wire wr_ena, rd_ena, wr_ack;
reg rd_ack;
reg [31:0] reg_rdata;
reg reg_rst;
assign wr_ena = (LOCAL_CS & ~LOCAL_RNW) ? 1'b1 : 1'b0;
assign rd_ena = (LOCAL_CS & LOCAL_RNW) ? 1'b1 : 1'b0;
assign wr_ack = wr_ena;
// Write Register
always @(posedge CLK or negedge RST_N) begin
if (!RST_N) begin
reg_rst <= 1'b0;
end else begin
if (wr_ena) begin
case (LOCAL_ADDR[7:0] & 8'hFC)
A_STATUS: begin
reg_rst <= LOCAL_WDATA[31];
end
A_SIZE: begin
end
A_PIXEL: begin
end
default: begin
end
endcase
end
end
end
// Read Register
always @(posedge CLK or negedge RST_N) begin
if (!RST_N) begin
reg_rdata[31:0] <= 32'd0;
rd_ack <= 1'b0;
end else begin
rd_ack <= rd_ena;
if (rd_ena) begin
case (LOCAL_ADDR[7:0] & 8'hFC)
A_STATUS: begin
reg_rdata[31:0] <= {reg_rst, 30'd0, LOGIC_IDLE};
end
A_SIZE: begin
reg_rdata[31:0] <= {HEIGHT[15:0], WIDTH[15:0]};
end
A_PIXEL: begin
reg_rdata[31:0] <= {PIXELY[15:0], PIXELX[15:0]};
end
default: begin
reg_rdata[31:0] <= 32'd0;
end
endcase
end else begin
reg_rdata[31:0] <= 32'd0;
end
end
end
assign LOGIC_RST = reg_rst;
assign LOCAL_ACK = rd_ack | wr_ack;
assign LOCAL_RDATA[31:0] = reg_rdata[31:0];
assign DEBUG[31:0] = {32'd0};
endmodule
| 8.09949 |
module aq_axi_lite_master_model (
// Reset, Clock
input ARESETN,
input ACLK,
// Write Address Channel
output reg [31:0] S_AXI_AWADDR,
output reg [ 3:0] S_AXI_AWCACHE,
output reg [ 2:0] S_AXI_AWPROT,
output reg S_AXI_AWVALID,
input S_AXI_AWREADY,
// Write Data Channel
output reg [31:0] S_AXI_WDATA,
output reg [ 3:0] S_AXI_WSTRB,
output reg S_AXI_WVALID,
input S_AXI_WREADY,
// Write Response Channel
input S_AXI_BVALID,
output reg S_AXI_BREADY,
input [1:0] S_AXI_BRESP,
// Read Address Channe
output reg [31:0] S_AXI_ARADDR,
output reg [ 3:0] S_AXI_ARCACHE,
output reg [ 2:0] S_AXI_ARPROT,
output reg S_AXI_ARVALID,
input S_AXI_ARREADY,
// Read Data Channel
input [31:0] S_AXI_RDATA,
input [ 1:0] S_AXI_RRESP,
input S_AXI_RVALID,
output reg S_AXI_RREADY
);
initial begin
S_AXI_AWADDR = 32'h0000_0000;
S_AXI_AWCACHE = 3'd0;
S_AXI_AWPROT = 2'd0;
S_AXI_AWVALID = 1'b0;
S_AXI_WDATA = 32'h0000_0000;
S_AXI_WSTRB = 4'H0;
S_AXI_WVALID = 1'b0;
S_AXI_BREADY = 1'b0;
S_AXI_ARADDR = 32'h0000_0000;
S_AXI_ARCACHE = 3'd0;
S_AXI_ARPROT = 2'd0;
S_AXI_ARVALID = 1'b0;
S_AXI_RREADY = 1'b0;
end
task wrdata;
input [31:0] adrs;
input [31:0] data;
begin
@(negedge ACLK);
S_AXI_AWADDR <= adrs;
S_AXI_AWVALID <= 1'b1;
@(negedge ACLK);
wait (S_AXI_AWREADY);
S_AXI_AWVALID <= 1'b0;
@(negedge ACLK);
S_AXI_WDATA <= data;
S_AXI_WSTRB <= 4'HF;
S_AXI_WVALID <= 1'b1;
wait (S_AXI_WREADY);
@(negedge ACLK);
S_AXI_WVALID <= 1'b0;
@(negedge ACLK);
wait (S_AXI_BVALID);
@(negedge ACLK);
S_AXI_BREADY <= 1'b1;
@(negedge ACLK);
wait (!S_AXI_BVALID);
S_AXI_BREADY <= 1'b0;
@(negedge ACLK);
end
endtask
task rddata;
input [31:0] adrs;
output [31:0] data;
begin
@(negedge ACLK);
wait (S_AXI_ARREADY);
@(negedge ACLK);
S_AXI_ARADDR <= adrs;
S_AXI_ARVALID <= 1'b1;
@(negedge ACLK);
S_AXI_ARVALID <= 1'b0;
@(negedge ACLK);
S_AXI_RREADY <= 1'b1;
wait (S_AXI_RVALID);
data = S_AXI_RDATA;
$display("AXI Lite Master Read[%08X]: %08X", adrs, S_AXI_RDATA);
@(negedge ACLK);
S_AXI_RREADY <= 1'b0;
wait (!S_AXI_RVALID);
@(negedge ACLK);
end
endtask
endmodule
| 7.096858 |
module axi_slave_model (
// Reset, Clock
input ARESETN,
input ACLK,
// Master Write Address
input [ 0:0] M_AXI_AWID,
input [31:0] M_AXI_AWADDR,
input [ 7:0] M_AXI_AWLEN, // Burst Length: 0-255
input [ 2:0] M_AXI_AWSIZE, // Burst Size: Fixed 2'b011
input [ 1:0] M_AXI_AWBURST, // Burst Type: Fixed 2'b01(Incremental Burst)
input M_AXI_AWLOCK, // Lock: Fixed 2'b00
input [ 3:0] M_AXI_AWCACHE, // Cache: Fiex 2'b0011
input [ 2:0] M_AXI_AWPROT, // Protect: Fixed 2'b000
input [ 3:0] M_AXI_AWQOS, // QoS: Fixed 2'b0000
input [ 0:0] M_AXI_AWUSER, // User: Fixed 32'd0
input M_AXI_AWVALID,
output reg M_AXI_AWREADY,
// Master Write Data
input [31:0] M_AXI_WDATA,
input [ 3:0] M_AXI_WSTRB,
input M_AXI_WLAST,
input [ 0:0] M_AXI_WUSER,
input M_AXI_WVALID,
output reg M_AXI_WREADY,
// Master Write Response
output reg [0:0] M_AXI_BID,
output reg [1:0] M_AXI_BRESP,
output reg [0:0] M_AXI_BUSER,
output M_AXI_BVALID,
input M_AXI_BREADY,
// Master Read Address
input [ 0:0] M_AXI_ARID,
input [31:0] M_AXI_ARADDR,
input [ 7:0] M_AXI_ARLEN,
input [ 2:0] M_AXI_ARSIZE,
input [ 1:0] M_AXI_ARBURST,
// input [1:0] M_AXI_ARLOCK,
input [ 0:0] M_AXI_ARLOCK,
input [ 3:0] M_AXI_ARCACHE,
input [ 2:0] M_AXI_ARPROT,
input [ 3:0] M_AXI_ARQOS,
input [ 0:0] M_AXI_ARUSER,
input M_AXI_ARVALID,
output reg M_AXI_ARREADY,
// Master Read Data
output reg [ 0:0] M_AXI_RID,
output [31:0] M_AXI_RDATA,
output reg [ 1:0] M_AXI_RRESP,
output M_AXI_RLAST,
output reg [ 0:0] M_AXI_RUSER,
output M_AXI_RVALID,
input M_AXI_RREADY
);
initial begin
M_AXI_AWREADY = 1;
M_AXI_WREADY = 1;
M_AXI_BID = 0;
M_AXI_BRESP = 0;
M_AXI_BUSER = 0;
//M_AXI_BVALID = 0;
M_AXI_ARREADY = 1;
M_AXI_RID = 0;
//M_AXI_RDATA = 0;
M_AXI_RRESP = 0;
//M_AXI_RLAST = 0;
M_AXI_RUSER = 0;
//M_AXI_RVALID = 0;
end
reg axi_rena;
reg [31:0] count, rcount;
always @(posedge ACLK or negedge ARESETN) begin
if (!ARESETN) begin
count <= 32'd0;
rcount <= 32'd0;
axi_rena <= 0;
// M_AXI_RVALID<=1'b0;
end else begin
if (M_AXI_RLAST) begin
axi_rena <= 0;
end else if (M_AXI_ARVALID) begin
axi_rena <= 1;
end
if (axi_rena) begin
count <= count + 32'd1;
end else begin
count <= 0;
end
if (M_AXI_RVALID & M_AXI_RREADY) begin
rcount <= rcount + 32'd1;
end
end
end
assign M_AXI_RDATA = {rcount, rcount};
assign M_AXI_RLAST = (axi_rena & (count == 255)) ? 1 : 0;
assign M_AXI_RVALID = axi_rena;
reg axi_wvalid;
always @(posedge ACLK or negedge ARESETN) begin
if (!ARESETN) begin
axi_wvalid <= 0;
end else begin
if (M_AXI_BREADY) begin
axi_wvalid <= 0;
end else if (M_AXI_WVALID & M_AXI_WLAST) begin
axi_wvalid <= 1;
end
end
end
assign M_AXI_BVALID = axi_wvalid;
endmodule
| 8.390609 |
module aq_axi_sdma64_fifo_ram #(
parameter DEPTH = 12,
parameter WIDTH = 32
) (
input WR_CLK,
input WR_ENA,
input [DEPTH -1:0] WR_ADRS,
input [WIDTH -1:0] WR_DATA,
input RD_CLK,
input [DEPTH -1:0] RD_ADRS,
output [WIDTH -1:0] RD_DATA
);
reg [WIDTH -1:0] ram [0:(2**DEPTH) -1];
reg [WIDTH -1:0] rd_reg;
always @(posedge WR_CLK) begin
if (WR_ENA) ram[WR_ADRS] <= WR_DATA;
end
always @(posedge RD_CLK) begin
rd_reg <= ram[RD_ADRS];
end
assign RD_DATA = rd_reg;
endmodule
| 7.418436 |
module aq_axi_sdma64_intreg (
input RST_N,
input CLKA,
input DIN,
input CLKB,
output DOUT
);
reg data_in;
reg [2:0] data_in_rst;
reg [2:0] data_out;
always @(posedge CLKA or negedge RST_N) begin
if (!RST_N) begin
data_in <= 1'b0;
data_in_rst[2:0] <= 3'd0;
end else begin
if (data_in_rst[2]) begin
data_in <= 1'b0;
end else if (DIN) begin
data_in <= 1'b1;
end
data_in_rst[2:0] <= {data_in_rst[1:0], data_out[2]};
end
end
always @(posedge CLKB or negedge RST_N) begin
if (!RST_N) begin
data_out[2:0] <= 3'd0;
end else begin
data_out[2:0] <= {data_out[1:0], data_in};
end
end
assign DOUT = (data_out[2:1] == 2'b01) ? 1'b1 : 1'b0;
endmodule
| 7.418436 |
module aq_axi_ssm2603 (
input ARESETN,
input ACLK,
// --------------------------------------------------
// AXI4 Lite Interface
// --------------------------------------------------
// Write Address Channel
input [15:0] S_AXI_AWADDR,
input [ 3:0] S_AXI_AWCACHE,
input [ 2:0] S_AXI_AWPROT,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
// Write Data Channel
input [31:0] S_AXI_WDATA,
input [ 3:0] S_AXI_WSTRB,
input S_AXI_WVALID,
output S_AXI_WREADY,
// Write Response Channel
output S_AXI_BVALID,
input S_AXI_BREADY,
output [1:0] S_AXI_BRESP,
// Read Address Channel
input [15:0] S_AXI_ARADDR,
input [ 3:0] S_AXI_ARCACHE,
input [ 2:0] S_AXI_ARPROT,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
// Read Data Channel
output [31:0] S_AXI_RDATA,
output [ 1:0] S_AXI_RRESP,
output S_AXI_RVALID,
input S_AXI_RREADY,
// SSM2603
output MUTEN,
input MCLK,
output BCLK,
output PBLRC,
output PBDAT,
output RECLRC,
input RECDAT,
input FIFO_RD_EMPTY,
output FIFO_RD_ENA,
input [31:0] FIFO_RD_DATA,
output FIFO_WR_ENA,
output [31:0] FIFO_WR_DATA
);
wire local_cs;
wire local_rnw;
wire local_ack;
wire [31:0] local_addr;
wire [ 3:0] local_be;
wire [31:0] local_wdata;
wire [31:0] local_rdata;
aq_axi_lite_slave u_aq_axi_lite_slave (
.ARESETN(ARESETN),
.ACLK(ACLK),
.S_AXI_AWADDR ({16'd0, S_AXI_AWADDR}),
.S_AXI_AWCACHE(S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_ARADDR ({16'd0, S_AXI_ARADDR}),
.S_AXI_ARCACHE(S_AXI_ARCACHE),
.S_AXI_ARPROT (S_AXI_ARPROT),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RDATA (S_AXI_RDATA),
.S_AXI_RRESP (S_AXI_RRESP),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
.LOCAL_CS(local_cs),
.LOCAL_RNW(local_rnw),
.LOCAL_ACK(local_ack),
.LOCAL_ADDR(local_addr),
.LOCAL_BE(local_be),
.LOCAL_WDATA(local_wdata),
.LOCAL_RDATA(local_rdata)
);
aq_ssm2603 u_ssm2603 (
.RST_N(ARESETN),
.CLK (ACLK),
.LOCAL_CS(local_cs),
.LOCAL_RNW(local_rnw),
.LOCAL_ACK(local_ack),
.LOCAL_ADDR(local_addr),
.LOCAL_BE(local_be),
.LOCAL_WDATA(local_wdata),
.LOCAL_RDATA(local_rdata),
.MUTEN(MUTEN),
.MCLK(MCLK),
.BCLK (BCLK),
.PBLRC (PBLRC),
.PBDAT (PBDAT),
.RECLRC(RECLRC),
.RECDAT(RECDAT),
.FIFO_RD_EMPTY(FIFO_RD_EMPTY),
.FIFO_RD_ENA (FIFO_RD_ENA),
.FIFO_RD_DATA (FIFO_RD_DATA),
.FIFO_WR_ENA (FIFO_WR_ENA),
.FIFO_WR_DATA (FIFO_WR_DATA)
);
endmodule
| 7.972768 |
module aq_dcache_data_array (
cp0_lsu_icg_en,
data_cen,
data_clk_en,
data_din,
data_dout,
data_gwen,
data_idx,
data_wen,
forever_cpuclk,
pad_yy_icg_scan_en
);
// &Ports; @21
input cp0_lsu_icg_en;
input data_cen;
input data_clk_en;
input [63:0] data_din;
input data_gwen;
input [13:0] data_idx;
input [63:0] data_wen;
input forever_cpuclk;
input pad_yy_icg_scan_en;
output [63:0] data_dout;
// &Regs; @22
// &Wires; @23
wire cp0_lsu_icg_en;
wire data_cen;
wire data_clk;
wire data_clk_en;
wire [63:0] data_din;
wire [63:0] data_dout;
wire data_gwen;
wire [13:0] data_idx;
wire [63:0] data_wen;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
// &Force("bus", "data_idx",13,0); @25
//==========================================================
// Instance of Gated Cell
//==========================================================
// &Instance("gated_clk_cell", "x_dcache_data_gated_clk"); @30
gated_clk_cell x_dcache_data_gated_clk (
.clk_in (forever_cpuclk),
.clk_out (data_clk),
.external_en (1'b0),
.global_en (1'b1),
.local_en (data_clk_en),
.module_en (cp0_lsu_icg_en),
.pad_yy_icg_scan_en(pad_yy_icg_scan_en)
);
// &Connect( @31
// .clk_in (forever_cpuclk ), @32
// .clk_out (data_clk ), @33
// .external_en (1'b0 ), @34
// .global_en (1'b1 ), @35
// .local_en (data_clk_en ), @36
// .module_en (cp0_lsu_icg_en ) @37
// ); @38
//==========================================================
// Instance dcache array
//==========================================================
// &Instance("aq_spsram_128x64", "x_aq_spsram_128x64"); @45
// &Instance("aq_spsram_256x64", "x_aq_spsram_256x64"); @48
// &Instance("aq_spsram_512x64", "x_aq_spsram_512x64"); @51
// &Instance("aq_spsram_1024x64", "x_aq_spsram_1024x64"); @54
// &Connect( @56
// .A (data_idx[`D_DATA_INDEX_WIDTH+2:4]), @57
// .CEN (data_cen ), @58
// .CLK (data_clk ), @59
// .GWEN (data_gwen ), @60
// .D (data_din ), @61
// .Q (data_dout ), @62
// .WEN (data_wen ) @63
// ); @64
// &Instance("aq_spsram_256x64", "x_aq_spsram_256x64"); @67
// &Instance("aq_spsram_512x64", "x_aq_spsram_512x64"); @70
// &Instance("aq_spsram_1024x64", "x_aq_spsram_1024x64"); @73
aq_spsram_1024x64 x_aq_spsram_1024x64 (
.A (data_idx[12:3]),
.CEN (data_cen),
.CLK (data_clk),
.D (data_din),
.GWEN(data_gwen),
.Q (data_dout),
.WEN (data_wen)
);
// &Instance("aq_spsram_2048x64", "x_aq_spsram_2048x64"); @76
// &Connect( @78
// .A (data_idx[`D_DATA_INDEX_WIDTH+2:3]), @79
// .CEN (data_cen ), @80
// .CLK (data_clk ), @81
// .GWEN (data_gwen ), @82
// .D (data_din ), @83
// .Q (data_dout ), @84
// .WEN (data_wen ) @85
// ); @86
// &ModuleEnd; @89
endmodule
| 6.642888 |
module aq_djpeg_dht (
input rst,
input clk,
input DataInEnable,
input [1:0] DataInColor,
input [7:0] DataInCount,
input [7:0] DataIn,
input [1:0] ColorNumber,
input [7:0] TableNumber,
output [3:0] ZeroTable,
output [3:0] WidhtTable
);
// RAM
reg [7:0] DHT_Ydc [0:15];
reg [7:0] DHT_Yac [0:255];
reg [7:0] DHT_Cdc [0:15];
reg [7:0] DHT_Cac [0:255];
reg [7:0] ReadDataYdc;
reg [7:0] ReadDataYac;
reg [7:0] ReadDataCdc;
reg [7:0] ReadDataCac;
wire [7:0] ReadData;
// RAM
always @(posedge clk) begin
if ((DataInEnable == 1'b1) & (DataInColor == 2'b00)) begin
DHT_Ydc[DataInCount[3:0]] <= DataIn;
end
if (DataInEnable == 1'b1 & DataInColor == 2'b01) begin
DHT_Yac[DataInCount] <= DataIn;
end
if (DataInEnable == 1'b1 & DataInColor == 2'b10) begin
DHT_Cdc[DataInCount[3:0]] <= DataIn;
end
if (DataInEnable == 1'b1 & DataInColor == 2'b11) begin
DHT_Cac[DataInCount] <= DataIn;
end
end
always @(posedge clk) begin
ReadDataYdc[7:0] <= DHT_Ydc[TableNumber[3:0]];
ReadDataYac[7:0] <= DHT_Yac[TableNumber];
ReadDataCdc[7:0] <= DHT_Cdc[TableNumber[3:0]];
ReadDataCac[7:0] <= DHT_Cac[TableNumber];
end
// Selector
function [7:0] ReadDataSel;
input [1:0] ColorNumber;
input [7:0] ReadDataYdc;
input [7:0] ReadDataYac;
input [7:0] ReadDataCdc;
input [7:0] ReadDataCac;
begin
case (ColorNumber[1:0])
2'b00: ReadDataSel[7:0] = ReadDataYdc[7:0];
2'b01: ReadDataSel[7:0] = ReadDataYac[7:0];
2'b10: ReadDataSel[7:0] = ReadDataCdc[7:0];
2'b11: ReadDataSel[7:0] = ReadDataCac[7:0];
endcase
end
endfunction
assign ReadData = ReadDataSel(ColorNumber, ReadDataYdc, ReadDataYac, ReadDataCdc, ReadDataCac);
assign ZeroTable = ReadData[7:4];
assign WidhtTable = ReadData[3:0];
endmodule
| 6.707844 |
module aq_dtu_cdc_pulse (
dst_clk,
dst_pulse,
dst_rstn,
src_clk,
src_pulse,
src_rstn
);
// &Ports; @21
input dst_clk;
input dst_rstn;
input src_clk;
input src_pulse;
input src_rstn;
output dst_pulse;
// &Regs; @22
reg dst_sync1;
reg dst_sync2;
reg dst_sync3;
reg dst_sync4;
reg src_lvl;
reg src_sync1;
reg src_sync2;
reg src_sync3;
reg src_sync4;
// &Wires; @23
wire clear_src_lvl;
wire dst_clk;
wire dst_pulse;
wire dst_rstn;
wire src_clk;
wire src_pulse;
wire src_rstn;
always @(posedge src_clk or negedge src_rstn) begin
if (!src_rstn) src_lvl <= 1'b0;
else if (src_pulse) src_lvl <= 1'b1;
else if (clear_src_lvl) src_lvl <= 1'b0;
end
always @(posedge dst_clk or negedge dst_rstn) begin
if (!dst_rstn) begin
dst_sync1 <= 1'b0;
dst_sync2 <= 1'b0;
dst_sync3 <= 1'b0;
dst_sync4 <= 1'b0;
end else begin
dst_sync1 <= src_lvl;
dst_sync2 <= dst_sync1;
dst_sync3 <= dst_sync2;
dst_sync4 <= dst_sync3;
end
end
always @(posedge src_clk or negedge src_rstn) begin
if (!src_rstn) begin
src_sync1 <= 1'b0;
src_sync2 <= 1'b0;
src_sync3 <= 1'b0;
src_sync4 <= 1'b0;
end else begin
src_sync1 <= dst_sync3;
src_sync2 <= src_sync1;
src_sync3 <= src_sync2;
src_sync4 <= src_sync3;
end
end
assign clear_src_lvl = src_sync3 && !src_sync4;
assign dst_pulse = dst_sync3 && !dst_sync4;
// &ModuleEnd; @74
endmodule
| 7.127057 |
module aq_fdsu_right_shift (
frac_num_in,
frac_shift_cnt,
frac_shift_num
);
// &Ports; @23
input [15:0] frac_num_in;
input [2 : 0] frac_shift_cnt;
output [15:0] frac_shift_num;
// &Regs; @24
reg [ 15:0] frac_shift_num;
// &Wires; @25
wire [ 15:0] frac_num_in;
wire [2 : 0] frac_shift_cnt;
// &Force("bus","frac_num_in",15,0); @26
// &CombBeg; @27
always @(frac_num_in[15:1] or frac_shift_cnt[2:0]) begin
casez (frac_shift_cnt[2:0])
3'b111: frac_shift_num[15:0] = {1'b0, frac_num_in[15:1]};
3'b110: frac_shift_num[15:0] = {2'b0, frac_num_in[15:2]};
3'b101: frac_shift_num[15:0] = {3'b0, frac_num_in[15:3]};
3'b100: frac_shift_num[15:0] = {4'b0, frac_num_in[15:4]};
3'b011: frac_shift_num[15:0] = {5'b0, frac_num_in[15:5]};
3'b010: frac_shift_num[15:0] = {6'b0, frac_num_in[15:6]};
3'b001: frac_shift_num[15:0] = {7'b0, frac_num_in[15:7]};
3'b000: frac_shift_num[15:0] = {8'b0, frac_num_in[15:8]};
default: frac_shift_num[15:0] = {16{1'b0}};
endcase
// &CombEnd; @39
end
// &ModuleEnd; @41
endmodule
| 7.016554 |
module fifo_ram #(
parameter DEPTH = 12,
parameter WIDTH = 32
) (
input WR_CLK,
input WR_ENA,
input [DEPTH -1:0] WR_ADRS,
input [WIDTH -1:0] WR_DATA,
input RD_CLK,
input [DEPTH -1:0] RD_ADRS,
output [WIDTH -1:0] RD_DATA
);
reg [WIDTH -1:0] ram[0:(2**DEPTH) -1];
reg [WIDTH -1:0] rd_reg;
always @(posedge WR_CLK) begin
if (WR_ENA) ram[WR_ADRS] <= WR_DATA;
end
always @(posedge RD_CLK) begin
rd_reg <= ram[RD_ADRS];
end
assign RD_DATA = rd_reg;
endmodule
| 7.798104 |
module aq_fifo6432 (
input RST,
input WR_CLK,
input WR_IN_EMPTY,
output WR_IN_RE,
input [63:0] WR_IN_DATA,
input WR_OUT_RE,
output [31:0] WR_OUT_DO,
output WR_OUT_EMPTY,
input RD_CLK,
input RD_OUT_FULL,
output RD_OUT_WE,
output [63:0] RD_OUT_DATA,
input RD_IN_WE,
input [31:0] RD_IN_DI,
output RD_IN_FULL,
output [31:0] DEBUG
);
reg [31:0] wr_buf;
reg wr_state, wr_ena;
// FIFO 64bit -> 32bit
always @(posedge WR_CLK or posedge RST) begin
if (RST) begin
wr_buf[31:0] <= 32'd0;
wr_state <= 1'b0;
wr_ena <= 1'b0;
end else begin
if (!wr_state) begin
if (!WR_IN_EMPTY) begin
wr_buf[31:0] <= WR_IN_DATA[63:32];
wr_ena <= 1'b1;
if (WR_OUT_RE) begin
wr_state <= 1'b1;
end
end
end else begin
if (WR_OUT_RE) begin
wr_state <= 1'b0;
wr_ena <= 1'b0;
end
end
end
end
assign WR_OUT_EMPTY = ((!wr_state & !WR_IN_EMPTY) | (wr_state & wr_ena)) ? 1'b0 : 1'b1;
assign WR_OUT_DO[31:0] = (!wr_state) ? WR_IN_DATA[31:0] : wr_buf[31:0];
assign WR_IN_RE = wr_state & WR_OUT_RE;
reg [31:0] rd_buf;
reg rd_ena;
// fifo 32bit -> 64bit
always @(posedge RD_CLK or posedge RST) begin
if (RST) begin
rd_buf[31:0] <= 32'd0;
rd_ena <= 1'b0;
end else begin
if (RD_IN_WE & !RD_OUT_FULL) begin
if (!rd_ena) begin
rd_buf[31:0] <= RD_IN_DI[31:0];
rd_ena <= 1'b1;
end else begin
rd_ena <= 1'b0;
end
end
end
end
assign RD_OUT_DATA[63:0] = {RD_IN_DI[31:0], rd_buf[31:0]};
assign RD_OUT_WE = RD_IN_WE & rd_ena;
assign RD_IN_FULL = RD_OUT_FULL;
endmodule
| 6.993496 |
module aq_f_spsram_1024x16 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 10;
parameter DATA_WIDTH = 16;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_WIDTH-1:0] Q;
reg [ADDR_WIDTH-1:0] addr_holding;
wire [ADDR_WIDTH-1:0] A;
wire CEN;
wire CLK;
wire [DATA_WIDTH-1:0] D;
wire GWEN;
wire [DATA_WIDTH-1:0] WEN;
wire [DATA_WIDTH-1:0] Q;
wire [ADDR_WIDTH-1:0] addr;
always @(posedge CLK) begin
if (!CEN) begin
addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
end
end
assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0] : A[ADDR_WIDTH-1:0];
wire [DATA_WIDTH-1:0] ram_wen_vec;
genvar i;
generate
for (i = 0; i < DATA_WIDTH; i = i + 1) begin : RAM_DIN_VEC
assign ram_wen_vec[i] = !CEN & !WEN[i] & !GWEN;
fpga_ram #(WRAP_SIZE, ADDR_WIDTH) ram_instance (
.PortAClk(CLK),
.PortAAddr(addr),
.PortADataIn(D[i]),
.PortAWriteEnable(ram_wen_vec[i]),
.PortADataOut(Q[i])
);
end
endgenerate
endmodule
| 7.588008 |
module aq_f_spsram_1024x64 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 10;
parameter DATA_WIDTH = 64;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_WIDTH-1:0] Q;
reg [ADDR_WIDTH-1:0] addr_holding;
wire [ADDR_WIDTH-1:0] A;
wire CEN;
wire CLK;
wire [DATA_WIDTH-1:0] D;
wire GWEN;
wire [DATA_WIDTH-1:0] WEN;
wire [DATA_WIDTH-1:0] Q;
wire [ADDR_WIDTH-1:0] addr;
always @(posedge CLK) begin
if (!CEN) begin
addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
end
end
assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0] : A[ADDR_WIDTH-1:0];
wire [DATA_WIDTH-1:0] ram_wen_vec;
genvar i;
generate
for (i = 0; i < DATA_WIDTH; i = i + 1) begin : RAM_DIN_VEC
assign ram_wen_vec[i] = !CEN & !WEN[i] & !GWEN;
fpga_ram #(WRAP_SIZE, ADDR_WIDTH) ram_instance (
.PortAClk(CLK),
.PortAAddr(addr),
.PortADataIn(D[i]),
.PortAWriteEnable(ram_wen_vec[i]),
.PortADataOut(Q[i])
);
end
endgenerate
endmodule
| 7.588008 |
module aq_f_spsram_128x8 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 7;
parameter DATA_WIDTH = 8;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_WIDTH-1:0] Q;
reg [ADDR_WIDTH-1:0] addr_holding;
wire [ADDR_WIDTH-1:0] A;
wire CEN;
wire CLK;
wire [DATA_WIDTH-1:0] D;
wire GWEN;
wire [DATA_WIDTH-1:0] WEN;
wire [DATA_WIDTH-1:0] Q;
wire [ADDR_WIDTH-1:0] addr;
always @(posedge CLK) begin
if (!CEN) begin
addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
end
end
assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0] : A[ADDR_WIDTH-1:0];
wire [DATA_WIDTH-1:0] ram_wen_vec;
genvar i;
generate
for (i = 0; i < DATA_WIDTH; i = i + 1) begin : RAM_DIN_VEC
assign ram_wen_vec[i] = !CEN & !WEN[i] & !GWEN;
fpga_ram #(WRAP_SIZE, ADDR_WIDTH) ram_instance (
.PortAClk(CLK),
.PortAAddr(addr),
.PortADataIn(D[i]),
.PortAWriteEnable(ram_wen_vec[i]),
.PortADataOut(Q[i])
);
end
endgenerate
endmodule
| 7.588008 |
module aq_gemac_flow_ctrl (
input RST_N,
input CLK, // Clock from Tx Clock
// From CPU
input TX_PAUSE_ENABLE,
// Rx MAC
input [15:0] PAUSE_QUANTA,
input PAUSE_QUANTA_VALID,
output PAUSE_QUANTA_COMPLETE,
// Tx MAC
output PAUSE_APPLY,
input PAUSE_QUANTA_SUB
);
reg PauseQuantaValidDl1, PauseQuantaValidDl2;
reg [15:0] PauseQuanta, PauseQuantaCount;
reg PauseApply;
always @(posedge CLK or negedge RST_N) begin
if (!RST_N) begin
end else begin
PauseQuantaValidDl1 <= PAUSE_QUANTA_VALID;
PauseQuantaValidDl2 <= PauseQuantaValidDl1;
PauseQuanta <= PAUSE_QUANTA;
end
end
always @(posedge CLK or negedge RST_N) begin
if (!RST_N) PauseQuantaCount <= 16'd0;
else if (!PauseQuantaValidDl2 && PauseQuantaValidDl1) PauseQuantaCount <= PauseQuanta;
else if (PAUSE_QUANTA_SUB && PauseQuantaCount != 0)
PauseQuantaCount <= PauseQuantaCount - 16'd1;
end
always @(posedge CLK or negedge RST_N) begin
if (!RST_N) PauseApply <= 1'b0;
else if (PauseQuantaCount == 0) PauseApply <= 1'b0;
else if (TX_PAUSE_ENABLE) PauseApply <= 1'b1;
end
assign PAUSE_QUANTA_COMPLETE = PauseQuantaValidDl1 & PauseQuantaValidDl2;
assign PAUSE_APPLY = PauseApply;
endmodule
| 7.678619 |
module aq_hpcp_event (
cp0_hpcp_icg_en,
cpurst_b,
eventx_clk_en,
eventx_value,
eventx_wen,
forever_cpuclk,
hpcp_wdata,
pad_yy_icg_scan_en
);
// &Ports; @17
input cp0_hpcp_icg_en;
input cpurst_b;
input eventx_clk_en;
input eventx_wen;
input forever_cpuclk;
input [63:0] hpcp_wdata;
input pad_yy_icg_scan_en;
output [63:0] eventx_value;
// &Regs; @18
reg [5 : 0] value;
// &Wires @19
wire cp0_hpcp_icg_en;
wire cpurst_b;
wire eventx_clk;
wire eventx_clk_en;
wire [ 63:0] eventx_value;
wire eventx_wen;
wire forever_cpuclk;
wire [ 63:0] hpcp_wdata;
wire pad_yy_icg_scan_en;
wire value_mask;
//define total counter num
parameter HPMCNT_NUM = 42;
parameter HPMEVT_WIDTH = 6;
// &Force("bus","hpcp_wdata",63,0); @25
//==========================================================
// Instance of Gated Cell
//==========================================================
// &Instance("gated_clk_cell", "x_gated_clk"); @29
gated_clk_cell x_gated_clk (
.clk_in (forever_cpuclk),
.clk_out (eventx_clk),
.external_en (1'b0),
.global_en (1'b1),
.local_en (eventx_clk_en),
.module_en (cp0_hpcp_icg_en),
.pad_yy_icg_scan_en(pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @30
// .external_en (1'b0), @31
// .global_en (1'b1), @32
// .module_en (cp0_hpcp_icg_en), @33
// .local_en (eventx_clk_en), @34
// .clk_out (eventx_clk)); @35
//==========================================================
// Implementation of counter
//==========================================================
always @(posedge eventx_clk or negedge cpurst_b) begin
if (!cpurst_b) value[HPMEVT_WIDTH-1:0] <= {HPMEVT_WIDTH{1'b0}};
else if (eventx_wen)
value[HPMEVT_WIDTH-1:0] <= hpcp_wdata[HPMEVT_WIDTH-1:0] & {HPMEVT_WIDTH{value_mask}};
else value[HPMEVT_WIDTH-1:0] <= value[HPMEVT_WIDTH-1:0];
end
assign value_mask = (!(|hpcp_wdata[63:HPMEVT_WIDTH]))
&& (hpcp_wdata[HPMEVT_WIDTH-1:0] <= HPMCNT_NUM);
//output
assign eventx_value[63:0] = {{64 - HPMEVT_WIDTH{1'b0}}, value[HPMEVT_WIDTH-1:0]};
// &ModuleEnd; @56
endmodule
| 6.525449 |
module aq_idu_expand_32 (
x_num,
x_num_expand
);
// &Ports; @25
input [4 : 0] x_num;
output [31:0] x_num_expand;
// &Regs; @26
// &Wires; @27
wire [4 : 0] x_num;
wire [ 31:0] x_num_expand;
//==========================================================
// expand 5 bits number to 32 bits one-hot number
//==========================================================
assign x_num_expand[0] = (x_num[4:0] == 5'd0);
assign x_num_expand[1] = (x_num[4:0] == 5'd1);
assign x_num_expand[2] = (x_num[4:0] == 5'd2);
assign x_num_expand[3] = (x_num[4:0] == 5'd3);
assign x_num_expand[4] = (x_num[4:0] == 5'd4);
assign x_num_expand[5] = (x_num[4:0] == 5'd5);
assign x_num_expand[6] = (x_num[4:0] == 5'd6);
assign x_num_expand[7] = (x_num[4:0] == 5'd7);
assign x_num_expand[8] = (x_num[4:0] == 5'd8);
assign x_num_expand[9] = (x_num[4:0] == 5'd9);
assign x_num_expand[10] = (x_num[4:0] == 5'd10);
assign x_num_expand[11] = (x_num[4:0] == 5'd11);
assign x_num_expand[12] = (x_num[4:0] == 5'd12);
assign x_num_expand[13] = (x_num[4:0] == 5'd13);
assign x_num_expand[14] = (x_num[4:0] == 5'd14);
assign x_num_expand[15] = (x_num[4:0] == 5'd15);
assign x_num_expand[16] = (x_num[4:0] == 5'd16);
assign x_num_expand[17] = (x_num[4:0] == 5'd17);
assign x_num_expand[18] = (x_num[4:0] == 5'd18);
assign x_num_expand[19] = (x_num[4:0] == 5'd19);
assign x_num_expand[20] = (x_num[4:0] == 5'd20);
assign x_num_expand[21] = (x_num[4:0] == 5'd21);
assign x_num_expand[22] = (x_num[4:0] == 5'd22);
assign x_num_expand[23] = (x_num[4:0] == 5'd23);
assign x_num_expand[24] = (x_num[4:0] == 5'd24);
assign x_num_expand[25] = (x_num[4:0] == 5'd25);
assign x_num_expand[26] = (x_num[4:0] == 5'd26);
assign x_num_expand[27] = (x_num[4:0] == 5'd27);
assign x_num_expand[28] = (x_num[4:0] == 5'd28);
assign x_num_expand[29] = (x_num[4:0] == 5'd29);
assign x_num_expand[30] = (x_num[4:0] == 5'd30);
assign x_num_expand[31] = (x_num[4:0] == 5'd31);
// &ModuleEnd; @65
endmodule
| 7.391258 |
module aq_ifu_ctrl (
cp0_ifu_in_lpmd,
cp0_ifu_lpmd_req,
ctrl_btb_chgflw_vld,
ctrl_btb_inst_fetch,
ctrl_btb_stall,
ctrl_ibuf_pop_en,
ctrl_icache_abort,
ctrl_icache_req_vld,
ctrl_ipack_cancel,
ibuf_ctrl_inst_fetch,
icache_ctrl_stall,
idu_ifu_id_stall,
pcgen_ctrl_chgflw_vld,
pred_ctrl_stall,
rtu_ifu_dbg_mask,
rtu_ifu_flush_fe,
vec_ctrl_reset_mask
);
// &Ports; @24
input cp0_ifu_in_lpmd;
input cp0_ifu_lpmd_req;
input ibuf_ctrl_inst_fetch;
input icache_ctrl_stall;
input idu_ifu_id_stall;
input pcgen_ctrl_chgflw_vld;
input pred_ctrl_stall;
input rtu_ifu_dbg_mask;
input rtu_ifu_flush_fe;
input vec_ctrl_reset_mask;
output ctrl_btb_chgflw_vld;
output ctrl_btb_inst_fetch;
output ctrl_btb_stall;
output ctrl_ibuf_pop_en;
output ctrl_icache_abort;
output ctrl_icache_req_vld;
output ctrl_ipack_cancel;
// &Regs; @25
// &Wires; @26
wire cp0_ifu_in_lpmd;
wire cp0_ifu_lpmd_req;
wire ctrl_btb_chgflw_vld;
wire ctrl_btb_inst_fetch;
wire ctrl_btb_stall;
wire ctrl_ibuf_pop_en;
wire ctrl_icache_abort;
wire ctrl_icache_req_vld;
wire ctrl_if_cancel;
wire ctrl_if_stall;
wire ctrl_inst_fetch;
wire ctrl_ipack_cancel;
wire ibuf_ctrl_inst_fetch;
wire icache_ctrl_stall;
wire idu_ifu_id_stall;
wire pcgen_ctrl_chgflw_vld;
wire pred_ctrl_stall;
wire rtu_ifu_dbg_mask;
wire rtu_ifu_flush_fe;
wire vec_ctrl_reset_mask;
//==========================================================
// IFU Control Module
// 1. Inst Fetch Requet Valid Signal
// 2. Inst Fetch Stage Stall Signal
// 3. Flush Signal for IFU modules
//==========================================================
//------------------------------------------------
// 1. Inst Fetch Requet Valid Signal
// a. Fetch inst when chgflw or I-buf fetch
// b. Not fetch when lpmd or debug on
//------------------------------------------------
assign ctrl_inst_fetch = ibuf_ctrl_inst_fetch
&& !(cp0_ifu_in_lpmd || cp0_ifu_lpmd_req)
&& !rtu_ifu_dbg_mask
&& !vec_ctrl_reset_mask;
//------------------------------------------------
// 2. Inst Fetch Stage Stall Signal
//------------------------------------------------
assign ctrl_if_stall = pred_ctrl_stall || icache_ctrl_stall;
//------------------------------------------------
// 3. Flush Signal for IFU modules
//------------------------------------------------
assign ctrl_if_cancel = rtu_ifu_flush_fe || pcgen_ctrl_chgflw_vld;
//==========================================================
// Rename for Output
//==========================================================
// Output to I-Buf
assign ctrl_ibuf_pop_en = !idu_ifu_id_stall;
//assign ctrl_ibuf_chgflw_vld = ctrl_if_cancel;
// Output to ICache
assign ctrl_icache_req_vld = ctrl_inst_fetch;
assign ctrl_icache_abort = ctrl_if_cancel;
// Output to IPack
assign ctrl_ipack_cancel = ctrl_if_cancel;
// Output to pcgen
//assign ctrl_pcgen_stall = ctrl_if_stall;
// Output to BTB
assign ctrl_btb_stall = ctrl_if_stall;
assign ctrl_btb_inst_fetch = ctrl_inst_fetch;
assign ctrl_btb_chgflw_vld = ctrl_if_cancel;
// &ModuleEnd; @78
endmodule
| 6.708749 |
module aq_ifu_ras_entry (
cp0_ifu_icg_en,
cp0_yy_clk_en,
cpurst_b,
forever_cpuclk,
pad_yy_icg_scan_en,
ras_entry_pc,
ras_entry_upd,
ras_upd_pc
);
// &Ports; @24
input cp0_ifu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input ras_entry_upd;
input [23:0] ras_upd_pc;
output [23:0] ras_entry_pc;
// &Regs; @25
reg [23:0] entry_pc;
// &Wires; @26
wire cp0_ifu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire entry_clk;
wire entry_clk_en;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
wire [23:0] ras_entry_pc;
wire ras_entry_upd;
wire [23:0] ras_upd_pc;
//==========================================================
// IFU Ras Entry Module
// 1. Instance ICG Cell
// 2. Entry PC
//==========================================================
//------------------------------------------------
// 1. Instance ICG Cell
//------------------------------------------------
assign entry_clk_en = ras_entry_upd;
// &Instance("gated_clk_cell", "x_ras_entry_icg_cell"); @38
gated_clk_cell x_ras_entry_icg_cell (
.clk_in (forever_cpuclk),
.clk_out (entry_clk),
.external_en (1'b0),
.global_en (cp0_yy_clk_en),
.local_en (entry_clk_en),
.module_en (cp0_ifu_icg_en),
.pad_yy_icg_scan_en(pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @39
// .external_en (1'b0), @40
// .global_en (cp0_yy_clk_en), @41
// .module_en ( cp0_ifu_icg_en), @42
// .local_en (entry_clk_en), @43
// .clk_out (entry_clk) @44
// ); @45
//------------------------------------------------
// 2. Entry PC
//------------------------------------------------
always @(posedge entry_clk or negedge cpurst_b) begin
if (!cpurst_b) begin
entry_pc[23:0] <= 24'b0;
end else if (ras_entry_upd) begin
entry_pc[23:0] <= ras_upd_pc[23:0];
end else begin
entry_pc[23:0] <= entry_pc[23:0];
end
end
//==========================================================
// Rename for Output
//==========================================================
assign ras_entry_pc[23:0] = entry_pc[23:0];
// &ModuleEnd; @73
endmodule
| 7.336363 |
module aq_intreg (
input RST_N,
input CLKA,
input DIN,
input CLKB,
output INT
);
reg data_in;
reg [2:0] data_in_rst;
reg [2:0] data_out;
always @(posedge CLKA or negedge RST_N) begin
if (!RST_N) begin
data_in <= 1'b0;
data_in_rst[2:0] <= 3'd0;
end else begin
if (data_in_rst[2]) begin
data_in <= 1'b0;
end else begin
data_in <= DIN;
end
data_in_rst[2:0] <= {data_in_rst[1:0], data_out[2]};
end
end
always @(posedge CLKB or negedge RST_N) begin
if (!RST_N) begin
data_out[2:0] <= 3'd0;
end else begin
data_out[2:0] <= {data_out[1:0], data_in};
end
end
assign INT = (data_out[2:1] == 2'b01) ? 1'b1 : 1'b0;
endmodule
| 6.979513 |
module aq_iu_addr_gen (
ag_bju_pc,
bju_ag_cur_pc,
bju_ag_offset,
bju_ag_offset_sel,
bju_ag_use_pc,
idu_bju_ex1_gateclk_sel,
idu_iu_ex1_src0,
idu_iu_ex1_src2,
mmu_xx_mmu_en
);
// &Ports; @24
input [39:0] bju_ag_cur_pc;
input [63:0] bju_ag_offset;
input bju_ag_offset_sel;
input bju_ag_use_pc;
input idu_bju_ex1_gateclk_sel;
input [63:0] idu_iu_ex1_src0;
input [63:0] idu_iu_ex1_src2;
input mmu_xx_mmu_en;
output [63:0] ag_bju_pc;
// &Regs; @25
// &Wires; @26
wire [63:0] ag_adder_res;
wire [63:0] ag_adder_rs1;
wire [63:0] ag_adder_rs1_raw;
wire [63:0] ag_adder_rs2;
wire [63:0] ag_bju_pc;
wire ag_rs1_use_pc;
wire ag_src_operand_mux;
wire [39:0] bju_ag_cur_pc;
wire [63:0] bju_ag_offset;
wire bju_ag_offset_sel;
wire bju_ag_use_pc;
wire idu_bju_ex1_gateclk_sel;
wire [63:0] idu_iu_ex1_src0;
wire [63:0] idu_iu_ex1_src2;
wire mmu_xx_mmu_en;
// &Force("bus", "bju_ag_cur_pc", 39, 0); @28
//==========================================================
// Address Generator
//==========================================================
// Address Generator generate address for:
// 1. jump, branch inst;
// 2. auipc inst;
//----------------------------------------------------------
// BJU Address Generator
//----------------------------------------------------------
//----------- Oper Prepare -------------
// branch inst, auipc inst use pc as rs1.
assign ag_src_operand_mux = idu_bju_ex1_gateclk_sel;
assign ag_rs1_use_pc = bju_ag_use_pc;
assign ag_adder_rs1_raw[63:0] = {64{ag_src_operand_mux}} & idu_iu_ex1_src0[63:0];
assign ag_adder_rs1[63:0] = ag_rs1_use_pc ? {{24{mmu_xx_mmu_en & bju_ag_cur_pc[39]}}, bju_ag_cur_pc[39:1], 1'b0}
: ag_adder_rs1_raw[63:0];
// bju entry inst, calculate tar pc
assign ag_adder_rs2[63:0] = bju_ag_offset_sel ? bju_ag_offset[63:0] : {64{ag_src_operand_mux}} & idu_iu_ex1_src2[63:0];
//-------------- Adder -----------------
assign ag_adder_res[63:0] = ag_adder_rs2[63:0] + ag_adder_rs1[63:0];
//---------- Rename for output ---------
assign ag_bju_pc[63:0] = ag_adder_res[63:0];
// &ModuleEnd; @59
endmodule
| 6.84147 |
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