code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module AppleIIePAL (
input clk_14M,
output reg clk_7M,
output clk_3_58M,
output reg clk_q3,
output clk_phi_0,
// RAM address strobes
input clk_phi_1,
input ramen_n,
output reg pcas_n,
output reg pras_n,
input vid7,
input gr,
input eighty_vid_n,
input entmg,
... | 7.748564 |
module apple_rom (
addr,
rd_data,
clk,
rst
);
localparam ADDR_WIDTH = 11; // @IPC int 9,20
localparam DATA_WIDTH = 8; // @IPC int 1,1152
localparam OUTPUT_REG = 0; // @IPC bool
localparam RD_OCE_EN = 0; // @IPC bool
localparam CLK_OR_POL_INV = 0; // @IPC bool
localparam RESET_TY... | 6.977502 |
module font_apple (
input wire clk,
input wire video_on,
input wire [9:0] pixel_x,
pixel_y,
output reg [2:0] rgb_apple
);
// signal declaration
wire [10:0] rom_addr;
reg [ 6:0] char_addr;
reg [6:0] char_addr_a, char_addr_p, char_addr_p2, char_addr_l, char_addr_e;
reg [3:0] row_addr;
wi... | 7.721663 |
module ApplySimpleCases(
// Input
input wire `TYPE_DEF typeIn,
input wire `INDEX_DEF f,
input wire `INDEX_DEF g,
input wire `VAR_DEF top,
input wire `VAR_DEF cubeLastVar,
// Abstract transform result
output reg `TYPE_DEF outType,
output reg `INDEX_DEF outF,
output reg `INDEX_DEF outG,
// Simpl... | 6.839091 |
module ApplySimpleCasesNoVar(
// Input
input wire `TYPE_DEF typeIn,
input wire `INDEX_DEF f,
input wire `INDEX_DEF g,
output reg `TYPE_DEF outType,
output reg `INDEX_DEF outF,
output reg `INDEX_DEF outG,
// Simple cases
output reg hit,
output reg `INDEX_DEF result
);
wire equal_f_one,equal_f_g,e... | 6.839091 |
module ApplyStage #(
parameter MEMORY_HALFADDRESS_BITS = 10,
parameter INSTRUCTION_HALFADDRESS_BITS = 32
) (
input wire CLK,
input wire RST_X,
output wire MemoryStallRequest,
input wire MemOp, //Whether to access memory
input wire MemRw, //Whether to read (0) or write (1) memory
inp... | 9.353955 |
module clock_approximator #(
parameter actual_frequency = 50e6,
parameter desired_frequency = 16e6
) (
input clock_original,
output reg clock_generated
);
// Skip every other HF clock period to achieve the LF clock
localparam skip_clocks = desired_frequency / actual_frequency;
reg [$clog2(skip_c... | 7.150452 |
module approx_8x8 (
input [7:0] A,
input [7:0] B,
output [15:0] P
);
wire [15:0] P_1;
mult_8x8_1111 M (
.A(A),
.B(B),
.R(P)
); //change this module name
endmodule
| 6.860685 |
module approx_fp_div (
a,
b,
q,
clk
);
input [31:0] a, b;
input clk;
output [31:0] q;
reg a_sign, b_sign, q_sign;
reg [7:0] a_exp, b_exp, q_exp;
reg [22:0] a_frac, q_frac;
reg [5:0] b_frac /*synthesis keep*/;
//input, output interface
always @(posedge clk) begin
a_sign <= a[31]... | 7.014474 |
module approx_fp_div_lut (
in,
out
);
input [5:0] in;
output [6:0] out;
reg [6:0] out;
always @(in) begin
case (in)
6'h0: out <= 7'h7c;
6'h1: out <= 7'h78;
6'h2: out <= 7'h74;
6'h3: out <= 7'h70;
6'h4: out <= 7'h6d;
6'h5: out <= 7'h6a;
6'h6: out <= 7... | 7.014474 |
module approx_fp_div_tb ();
////////////////////////
// define the latency here
////////////////////////
parameter LATENCY = 5;
wire [31:0] q;
reg clk = 0;
reg [31:0] nf, df;
reg [31:0] qf[LATENCY:0];
////////////////////////
// test unit
////////////////////////
approx_fp_div dut (
.... | 7.014474 |
module approx_fp_invsqrt (
clk,
in,
out
);
parameter CORRECTION_ROUND = 1'b1;
input clk;
input [31:0] in;
output [31:0] out;
wire [31:0] out;
// Magic courtesy of Quake 3 / Well known Internet trick
// first order approximation of 1 / sqrt(in)
//
reg [31:0] app;
always @(posedge cl... | 7.178777 |
module approx_fp_invsqrt_tb ();
// number of stimuli in table
parameter NUM_STIM = 50000;
// 1st order approximation only v.s. additional Newton refinement round
parameter CORRECTION_ROUND = 1'b1;
// the correction round increases the pipeline latency
parameter LAG = CORRECTION_ROUND ? 6 : 1;
reg [32*NUM_STIM*7-1:0... | 7.178777 |
module appro_42 (
input a,
b,
c,
d,
output carry,
sum
);
assign carry = (a & b) | (c & d);
assign sum = (a ^ b) | (c ^ d) | (a & b & c & d);
endmodule
| 7.731284 |
module appro_fulladder (
input a,
b,
c,
output carry,
sum
);
assign carry = (a & c) | (b & c);
assign sum = (a | b) ^ c;
endmodule
| 6.890692 |
module appr_cordic #(
parameter width_in = 18, //data width_in
parameter width_out = 16 //data width_out
) (
input signed [ width_in-1:0] x_in,
input signed [ width_in-1:0] y_in,
input start,
input clk,
input rst_n... | 7.036113 |
module Appr_Mag #(
parameter WIDTH = 16
) (
input clk,
rst,
ena,
input [WIDTH-1:0] real_in,
imag_in,
output [ WIDTH:0] mag,
output val
);
reg [WIDTH-1:0] real_abs, imag_abs;
reg ena_abs;
always @(posedge clk) begin
if (rst) begin
ena_abs <= 1... | 7.85363 |
module app_aes_end_s_table_0_0_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distrib... | 6.994657 |
module app_aes_end_s_table_0_0_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - ... | 6.994657 |
module app_aes_process_0_mux_42_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
i... | 8.416717 |
module app_aes_process_0_s_table_0_0_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "d... | 8.416717 |
module app_aes_process_0_s_table_0_0_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWi... | 8.416717 |
module app_aes_process_1_mux_42_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
i... | 8.416717 |
module app_aes_process_1_s_table_0_0_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "d... | 8.416717 |
module app_aes_process_1_s_table_0_0_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWi... | 8.416717 |
module app_aes_process_2_mux_42_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
i... | 8.416717 |
module app_aes_process_2_s_table_0_0_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "d... | 8.416717 |
module app_aes_process_2_s_table_0_0_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWi... | 8.416717 |
module app_aes_process_3_mux_42_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
i... | 8.416717 |
module app_aes_process_3_s_table_0_0_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "d... | 8.416717 |
module app_aes_process_3_s_table_0_0_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWi... | 8.416717 |
module app_aes_process_4_mux_42_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
i... | 8.416717 |
module app_aes_process_4_s_table_0_0_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "d... | 8.416717 |
module app_aes_process_4_s_table_0_0_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWi... | 8.416717 |
module app_aes_process_5_mux_42_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
i... | 8.416717 |
module app_aes_process_5_s_table_0_0_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "d... | 8.416717 |
module app_aes_process_5_s_table_0_0_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWi... | 8.416717 |
module app_aes_process_6_mux_42_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
i... | 8.416717 |
module app_aes_process_6_s_table_0_0_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "d... | 8.416717 |
module app_aes_process_6_s_table_0_0_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWi... | 8.416717 |
module app_aes_process_7_mux_42_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
i... | 8.416717 |
module app_aes_process_7_s_table_0_0_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "d... | 8.416717 |
module app_aes_process_7_s_table_0_0_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWi... | 8.416717 |
module app_aes_process_8_mux_42_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
i... | 8.416717 |
module app_aes_process_8_s_table_0_0_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "d... | 8.416717 |
module app_aes_process_8_s_table_0_0_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWi... | 8.416717 |
module App_DataControl (
input in_rst,
input in_clk,
input in_clk_200M,
input in_clk_10M,
input in_clk_1k,
input in_trigger_n,
input [9:0] in_addata,
input in_request_n,
input [1:0] in_sample_rate_select,
//uart接口
output out_uart_txd... | 7.188806 |
module App_FSK (
input in_clr
, input in_clk
, input [9:0] in_ADFIFO
, input in_rdFIFOempty
, input [4:0] DS18B20_Input
, output reg out_rdFIFOclk
, output reg out_rdFIFOreq
, output reg fsk_data
, output out_FSK
);
/* 寄存器配置 -------------------------*/
reg fsk_signal; //fsk_s... | 6.654899 |
module app_gzip_mux_83_32_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
... | 6.755936 |
module app_stencil_mux_164_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32... | 7.001465 |
module app_stencil_mux_32_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
input [7 : 0] din1,
input [7 : 0... | 7.001465 |
module app_stencil_rows_buffer_0_0_red_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] ... | 6.805174 |
module app_stencil_rows_buffer_0_0_red (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
... | 6.805174 |
module app_sw_mux_32_16_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
dout_WIDTH = 32
) (
input [15 : 0] din0,
input [15 : 0] din1,
input [15 : 0]... | 6.584762 |
module app_tb;
// 156.25 MHz clock for Ethernet PHY
reg clk_156;
initial begin
clk_156 = 0;
end
always #8 clk_156 = ~clk_156;
// reset
reg sys_rst;
initial begin
sys_rst = 1;
#100 sys_rst = 0;
end
// top
wire [63:0] xgmii_txd;
wire [ 7:0] xgmii_txc;
reg [ 3:0] dipsw;
wire [ 7... | 6.553104 |
module mux #(
parameter WIDTH = 8,
CHANNELS = 4,
SEL_WIDTH = 3
) // arg! this should be $clog2(CHANNELS) but Quartus does not accept that in a port declaration;
(
// input [$clog2(CHANNELS)-1:0] sel,
input [SEL_WIDTH-1:0] sel,
input [(CHANNELS*WIDTH)-1:0] in_bus,
... | 8.575874 |
module debug (
input wire clk_in, // main tick
input wire clk_tx_in, // uart transmitter tick
input new_cycle_in, // assrted when we have to send the info
input wire [95:0] debug_data_in,
output wire uart_tx_o
);
reg [95:0] data;
reg [ 8:0] state;
reg [ 7:0] uart_data;
reg transmit, tra... | 6.504557 |
module uart_tx (
input wire clk_in,
input wire [7:0] data_in,
input wire en_in,
output wire tx_o
);
reg [3:0] state;
reg [7:0] data;
assign tx_o = (state == 1) ? 1'b1 : state[3] ? data[0] : 1'b0;
always @(posedge clk_in) begin
case (state)
0: if (en_in) state <= 4'h1;
1: begin
... | 6.884683 |
module apb_tx_tb ();
/* ---------------
INPUT of apb_tx
--------------- */
reg clk;
reg rstn; // active LOW to reset
reg sel; // activate apb_tx module
reg set; // set DUTY & PERIOD. enable PWM
reg mode; // switch between 8 bit & 10 bit tx
reg [9:0] din; // input data for transmission... | 9.311727 |
module TriangleChan (
input clk,
input ce,
input reset,
input [1:0] Addr,
input [7:0] DIN,
input MW,
input LenCtr_Clock,
input LinCtr_Clock,
input Enabled,
input [7:0] LenCtr_In,
output [3:0] Sample,
output IsNonZero
);
//
reg [10:0] Period, TimerCtr;
reg [4:0] SeqP... | 7.276593 |
module NoiseChan (
input clk,
input ce,
input reset,
input [1:0] Addr,
input [7:0] DIN,
input MW,
input LenCtr_Clock,
input Env_Clock,
input Enabled,
input [7:0] LenCtr_In,
output [3:0] Sample,
output IsNonZero
);
//
// Envelope volume
reg EnvLoop, EnvDisable, EnvDo... | 6.570767 |
module apu_div #(
parameter PERIOD_BITS = 16
) (
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire pulse_in, // input pulse
input wire reload_in, // reset counter to period_in... | 7.631895 |
module apu_envelope_generator (
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire eg_pulse_in, // 1 clk pulse for every env gen update
input wire [5:0] env_in, // envelope value (e.g., via $4000)
input wire env_wr_... | 7.106507 |
module NES_WRAM (
M2,
RnW,
n_RES,
Addr,
Data
);
input M2;
input RnW;
input n_RES;
input [15:0] Addr;
inout [7:0] Data;
wire wram_sel;
assign wram_sel = ~|Addr[15:11];
assign Data = (wram_sel & RnW) ? 8'b0 : 8'bz;
endmodule
| 6.556247 |
module apu_triangle (
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire en_in, // enable (via $4015)
input wire cpu_cycle_pulse_in, // 1 clk pulse on every cpu cycle
input wire lc_pulse_... | 6.831666 |
module ApvDataFifo_1024x12 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw
);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
output ... | 7.338939 |
module ApvDataFifo_1024x12 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw
);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
output ... | 7.338939 |
module ApvDataFifo_1024x13 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw
);
input aclr;
input [12:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [12:0] q;
output rdempty;
output ... | 7.338939 |
module ApvDataFifo_1024x13 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw
);
input aclr;
input [12:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [12:0] q;
output rdempty;
output ... | 7.338939 |
module ApvDataFifo_2048x12 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw
);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
output ... | 6.903746 |
module ApvDataFifo_2048x12 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw
);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
output ... | 6.903746 |
module ap_adder (
input [15:0] y,
output [31:0] s
);
wire [3:0] cout;
assign s[0] = y[0];
genvar i;
generate
for (i = 1; i < 5; i = i + 1) begin
if (i == 1)
ap_adder_u ap_adder_unit (
.y2 (y[i*2]),
.y1 (y[i*2-1]),
.y0 (y[i*2-2]),
.cin... | 7.087331 |
module ap_adder_u (
input y2,
input y1,
input y0,
input cin,
output s1,
output s2,
output cout
);
assign cout = y1;
assign s2 = y2;
assign s1 = cin ^ y1 ^ y0;
endmodule
| 8.009772 |
module ap_comp (
input wire x1,
x2,
x3,
x4,
output wire s,
c
);
assign c = (x1 & x2) || (x1 & x3) || (x1 & x4) || (x2 & x3) || (x2 & x4);
assign s = (x1 ^ x2) ^ (x3 || x4);
endmodule
| 6.890932 |
module aq_axi4ls (
input RST_N,
input CLK,
// AXI4 Lite Interface
input ARESETN,
input ACLK,
// Write Address Channel
input [31:0] AWADDR,
input [3:0] AWCACHE, // 4'b0011
input [2:0] AWPROT, // 3'b000
input AWVALID,
output AWREADY,
// Write Data Channel
input [31... | 8.442275 |
module aq_axis_djpeg (
// --------------------------------------------------
// AXI4 Lite Interface
// --------------------------------------------------
input ARESETN,
input ACLK,
// Write Address Channel
input [31:0] S_AXI_AWADDR,
input [ 3:0] S_AXI_AWCACHE,
input [ 2:0] S_AXI_... | 6.753622 |
module aq_axis_reduce (
// AXI4 Lite Interface
input ARESETN,
input ACLK,
// Write Address Channel
input [31:0] S_AXI_AWADDR,
input [ 3:0] S_AXI_AWCACHE,
input [ 2:0] S_AXI_AWPROT,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
// Write Data Channel
input [31... | 7.161924 |
module aq_axis_t32f64 (
input ARESETN,
input I_AXIS_TCLK,
input [64:0] I_AXIS_TDATA,
input I_AXIS_TVALID,
output I_AXIS_TREADY,
input [ 7:0] I_AXIS_TSTRB,
input I_AXIS_TKEEP,
input I_AXIS_TLAST,
output O_AXIS_TCLK,
output [31:0] O... | 7.622882 |
module aq_axi_djpeg_ctl (
input RST_N,
input CLK,
input LOCAL_CS,
input LOCAL_RNW,
output LOCAL_ACK,
input [31:0] LOCAL_ADDR,
input [ 3:0] LOCAL_BE,
input [31:0] LOCAL_WDATA,
output [31:0] LOCAL_RDATA,
output LOGIC_RST,
input LOGIC_IDLE,
inpu... | 8.09949 |
module aq_axi_lite_master_model (
// Reset, Clock
input ARESETN,
input ACLK,
// Write Address Channel
output reg [31:0] S_AXI_AWADDR,
output reg [ 3:0] S_AXI_AWCACHE,
output reg [ 2:0] S_AXI_AWPROT,
output reg S_AXI_AWVALID,
input S_AXI_AWREADY,
// Write Data... | 7.096858 |
module axi_slave_model (
// Reset, Clock
input ARESETN,
input ACLK,
// Master Write Address
input [ 0:0] M_AXI_AWID,
input [31:0] M_AXI_AWADDR,
input [ 7:0] M_AXI_AWLEN, // Burst Length: 0-255
input [ 2:0] M_AXI_AWSIZE, // Burst Size: Fixed 2'b011
input ... | 8.390609 |
module aq_axi_sdma64_fifo_ram #(
parameter DEPTH = 12,
parameter WIDTH = 32
) (
input WR_CLK,
input WR_ENA,
input [DEPTH -1:0] WR_ADRS,
input [WIDTH -1:0] WR_DATA,
input RD_CLK,
input [DEPTH -1:0] RD_ADRS,
output [WIDTH -1:0] RD_DATA
);
reg... | 7.418436 |
module aq_axi_sdma64_intreg (
input RST_N,
input CLKA,
input DIN,
input CLKB,
output DOUT
);
reg data_in;
reg [2:0] data_in_rst;
reg [2:0] data_out;
always @(posedge CLKA or negedge RST_N) begin
if (!RST_N) begin
data_in <= 1'b0;
data_in_rst[2:0] <= 3'd0;
end else... | 7.418436 |
module aq_axi_ssm2603 (
input ARESETN,
input ACLK,
// --------------------------------------------------
// AXI4 Lite Interface
// --------------------------------------------------
// Write Address Channel
input [15:0] S_AXI_AWADDR,
input [ 3:0] S_AXI_AWCACHE,
input [ 2:0] S_AXI... | 7.972768 |
module aq_dcache_data_array (
cp0_lsu_icg_en,
data_cen,
data_clk_en,
data_din,
data_dout,
data_gwen,
data_idx,
data_wen,
forever_cpuclk,
pad_yy_icg_scan_en
);
// &Ports; @21
input cp0_lsu_icg_en;
input data_cen;
input data_clk_en;
input [63:0] data_din;
input data_gw... | 6.642888 |
module aq_djpeg_dht (
input rst,
input clk,
input DataInEnable,
input [1:0] DataInColor,
input [7:0] DataInCount,
input [7:0] DataIn,
input [1:0] ColorNumber,
input [7:0] TableNumber,
output [3:0] ZeroTable,
output [3:0] WidhtTable
);
// RAM
reg [7:0] DHT_Ydc [0:15];
... | 6.707844 |
module aq_dtu_cdc_pulse (
dst_clk,
dst_pulse,
dst_rstn,
src_clk,
src_pulse,
src_rstn
);
// &Ports; @21
input dst_clk;
input dst_rstn;
input src_clk;
input src_pulse;
input src_rstn;
output dst_pulse;
// &Regs; @22
reg dst_sync1;
reg dst_sync2;
reg dst_sync3;
reg dst... | 7.127057 |
module aq_fdsu_right_shift (
frac_num_in,
frac_shift_cnt,
frac_shift_num
);
// &Ports; @23
input [15:0] frac_num_in;
input [2 : 0] frac_shift_cnt;
output [15:0] frac_shift_num;
// &Regs; @24
reg [ 15:0] frac_shift_num;
// &Wires; @25
wire [ 15:0] frac_num_in;
wire [2 : 0] frac_shift_cn... | 7.016554 |
module fifo_ram #(
parameter DEPTH = 12,
parameter WIDTH = 32
) (
input WR_CLK,
input WR_ENA,
input [DEPTH -1:0] WR_ADRS,
input [WIDTH -1:0] WR_DATA,
input RD_CLK,
input [DEPTH -1:0] RD_ADRS,
output [WIDTH -1:0] RD_DATA
);
reg [WIDTH -1:0] ... | 7.798104 |
module aq_fifo6432 (
input RST,
input WR_CLK,
input WR_IN_EMPTY,
output WR_IN_RE,
input [63:0] WR_IN_DATA,
input WR_OUT_RE,
output [31:0] WR_OUT_DO,
output WR_OUT_EMPTY,
input RD_CLK,
input RD_OUT_FULL,
output RD_OUT_WE,
output [63:0] RD_OUT_DATA,
input RD_IN_WE,
... | 6.993496 |
module aq_f_spsram_1024x16 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 10;
parameter DATA_WIDTH = 16;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_WID... | 7.588008 |
module aq_f_spsram_1024x64 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 10;
parameter DATA_WIDTH = 64;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_WID... | 7.588008 |
module aq_f_spsram_128x8 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 7;
parameter DATA_WIDTH = 8;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_WIDTH-1... | 7.588008 |
module aq_gemac_flow_ctrl (
input RST_N,
input CLK, // Clock from Tx Clock
// From CPU
input TX_PAUSE_ENABLE,
// Rx MAC
input [15:0] PAUSE_QUANTA,
input PAUSE_QUANTA_VALID,
output PAUSE_QUANTA_COMPLETE,
// Tx MAC
output PAUSE_APPLY,
input PAUSE_QUANTA_SUB
);
reg Pau... | 7.678619 |
module aq_hpcp_event (
cp0_hpcp_icg_en,
cpurst_b,
eventx_clk_en,
eventx_value,
eventx_wen,
forever_cpuclk,
hpcp_wdata,
pad_yy_icg_scan_en
);
// &Ports; @17
input cp0_hpcp_icg_en;
input cpurst_b;
input eventx_clk_en;
input eventx_wen;
input forever_cpuclk;
input [63:0] hpcp... | 6.525449 |
module aq_idu_expand_32 (
x_num,
x_num_expand
);
// &Ports; @25
input [4 : 0] x_num;
output [31:0] x_num_expand;
// &Regs; @26
// &Wires; @27
wire [4 : 0] x_num;
wire [ 31:0] x_num_expand;
//==========================================================
// expand 5 bits number to 32 bit... | 7.391258 |
module aq_ifu_ctrl (
cp0_ifu_in_lpmd,
cp0_ifu_lpmd_req,
ctrl_btb_chgflw_vld,
ctrl_btb_inst_fetch,
ctrl_btb_stall,
ctrl_ibuf_pop_en,
ctrl_icache_abort,
ctrl_icache_req_vld,
ctrl_ipack_cancel,
ibuf_ctrl_inst_fetch,
icache_ctrl_stall,
idu_ifu_id_stall,
pcgen_ctrl_chgflw_... | 6.708749 |
module aq_ifu_ras_entry (
cp0_ifu_icg_en,
cp0_yy_clk_en,
cpurst_b,
forever_cpuclk,
pad_yy_icg_scan_en,
ras_entry_pc,
ras_entry_upd,
ras_upd_pc
);
// &Ports; @24
input cp0_ifu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input... | 7.336363 |
module aq_intreg (
input RST_N,
input CLKA,
input DIN,
input CLKB,
output INT
);
reg data_in;
reg [2:0] data_in_rst;
reg [2:0] data_out;
always @(posedge CLKA or negedge RST_N) begin
if (!RST_N) begin
data_in <= 1'b0;
data_in_rst[2:0] <= 3'd0;
end else begin
if... | 6.979513 |
module aq_iu_addr_gen (
ag_bju_pc,
bju_ag_cur_pc,
bju_ag_offset,
bju_ag_offset_sel,
bju_ag_use_pc,
idu_bju_ex1_gateclk_sel,
idu_iu_ex1_src0,
idu_iu_ex1_src2,
mmu_xx_mmu_en
);
// &Ports; @24
input [39:0] bju_ag_cur_pc;
input [63:0] bju_ag_offset;
input bju_ag_offset_sel;
in... | 6.84147 |
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