code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module fifo_v2_DEPTH1_ALM_EMPTY_TH0_ALM_FULL_TH0 (
clk_i,
rst_ni,
flush_i,
testmode_i,
full_o,
empty_o,
alm_full_o,
alm_empty_o,
data_i,
push_i,
data_o,
pop_i
);
input [133:0] data_i;
output [133:0] data_o;
input clk_i;
input rst_ni;
input flush_i;
input test... | 7.120907 |
module amo_buffer (
clk_i,
rst_ni,
flush_i,
valid_i,
ready_o,
amo_op_i,
paddr_i,
data_i,
data_size_i,
amo_req_o,
amo_resp_i,
amo_valid_commit_i,
no_st_pending_i
);
input [3:0] amo_op_i;
input [63:0] paddr_i;
input [63:0] data_i;
input [1:0] data_size_i;
out... | 7.823248 |
module lzc_00000004 (
in_i,
cnt_o,
empty_o
);
input [3:0] in_i;
output [1:0] cnt_o;
output empty_o;
wire [1:0] cnt_o;
wire empty_o, N0, index_nodes_2__0_, index_nodes_1__0_, N1;
wire [2:0] sel_nodes;
assign cnt_o[1] = ~sel_nodes[1];
assign cnt_o[0] = (N0) ? index_nodes_1__0_ : (N1) ? index_... | 6.51737 |
module ARINC429 (
input wire [1 : 0] nvel,
input wire [7 : 0] adr,
input wire [22 : 0] dat,
input wire GCLK,
output wire TXD0,
output wire TXD1,
input wire RXD0,
input wire RXD1,
input wire st,
output reg [7:0] sr_adr,
output reg [22:0] sr_dat,
output reg ce_wr,
input... | 7.107397 |
module AritgmeticLogicUnit (
input [63:0] A,
input [63:0] B,
input [2:0] aluOp,
output reg [63:0] addres,
output reg zeroCU
);
always @(aluOp, A, B) begin
case (aluOp)
3'b000: begin
addres <= A + B;
if ((A + B) == 0) zeroCU <= 1;
else zeroCU <= 0;
end
... | 6.800323 |
module Arith (
a,
b,
cin,
s,
out
);
input [1:0] a;
input [1:0] b;
input cin;
input [1:0] s;
output [3:0] out;
reg [3:0] oreg;
wire [3:0] w1;
wire [3:0] w2;
wire [3:0] w3;
wire [3:0] w4;
fullfull ful (
a,
b,
cin,
w3,
cin
);
Multiply m (
... | 7.328877 |
module arith (
input [7:0] a,
input [7:0] b,
output [7:0] usum,
output [7:0] ssum,
output [7:0] usub,
output [7:0] ssub,
output [7:0] umul,
output [7:0] smul,
output [7:0] udiv,
output [7:0] sdiv,
output [7:0] umod,
output [7:0] smod,
output [7:0] upow,
output [... | 6.902759 |
module arithAdd (
a,
b,
y
);
input [7:0] a;
input [7:0] b;
output [7:0] y;
reg [7:0] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 6.717422 |
module arithbox (
arithop,
calc_sz,
ci,
co,
af,
ai,
sa,
sb,
opa,
opb,
resa,
cmp
);
input [3:0] arithop;
input [3:0] calc_sz;
input [31:0] opa, opb;
output reg [31:0] resa;
input ci, ai;
output reg co, af, sa, sb, cmp;
wire [4:0] af2, af3, af4, af5;
assi... | 6.724017 |
module arithm (
op_a,
op_b,
arithm_opsel,
result,
ovf,
cf
);
input [2:0] arithm_opsel;
input [`REG_WIDTH-1:0] op_a;
input [`REG_WIDTH-1:0] op_b;
output reg [`REG_WIDTH-1:0] result;
output reg ovf = 0;
output reg cf = 0;
wire [`REG_WIDTH-1:0] op_b_inv;
wire [`REG_WIDTH+1:0] add... | 7.295609 |
module vc_Adder #(
parameter p_nbits = 1
) (
input logic [p_nbits-1:0] in0,
input logic [p_nbits-1:0] in1,
input logic cin,
output logic [p_nbits-1:0] out,
output logic cout
);
// We need to convert cin into a 32-bit value to
// avoid verilator warnings
ass... | 7.622412 |
module vc_SimpleAdder #(
parameter p_nbits = 1
) (
input logic [p_nbits-1:0] in0,
input logic [p_nbits-1:0] in1,
output logic [p_nbits-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.112602 |
module vc_Subtractor #(
parameter p_nbits = 1
) (
input logic [p_nbits-1:0] in0,
input logic [p_nbits-1:0] in1,
output logic [p_nbits-1:0] out
);
assign out = in0 - in1;
endmodule
| 7.776575 |
module vc_Incrementer #(
parameter p_nbits = 1,
parameter p_inc_value = 1
) (
input logic [p_nbits-1:0] in,
output logic [p_nbits-1:0] out
);
assign out = in + p_inc_value;
endmodule
| 8.657353 |
module vc_ZeroExtender #(
parameter p_in_nbits = 1,
parameter p_out_nbits = 8
) (
input logic [ p_in_nbits-1:0] in,
output logic [p_out_nbits-1:0] out
);
assign out = {{(p_out_nbits - p_in_nbits) {1'b0}}, in};
endmodule
| 8.062945 |
module vc_SignExtender #(
parameter p_in_nbits = 1,
parameter p_out_nbits = 8
) (
input logic [ p_in_nbits-1:0] in,
output logic [p_out_nbits-1:0] out
);
assign out = {{(p_out_nbits - p_in_nbits) {in[p_in_nbits-1]}}, in};
endmodule
| 8.543095 |
module vc_ZeroComparator #(
parameter p_nbits = 1
) (
input logic [p_nbits-1:0] in,
output logic out
);
assign out = (in == {p_nbits{1'b0}});
endmodule
| 8.972309 |
module vc_EqComparator #(
parameter p_nbits = 1
) (
input logic [p_nbits-1:0] in0,
input logic [p_nbits-1:0] in1,
output logic out
);
assign out = (in0 == in1);
endmodule
| 8.385225 |
module vc_LtComparator #(
parameter p_nbits = 1
) (
input logic [p_nbits-1:0] in0,
input logic [p_nbits-1:0] in1,
output logic out
);
assign out = (in0 < in1);
endmodule
| 8.571994 |
module vc_GtComparator #(
parameter p_nbits = 1
) (
input logic [p_nbits-1:0] in0,
input logic [p_nbits-1:0] in1,
output logic out
);
assign out = (in0 > in1);
endmodule
| 8.065152 |
module vc_LeftLogicalShifter #(
parameter p_nbits = 1,
parameter p_shamt_nbits = 1
) (
input logic [ p_nbits-1:0] in,
input logic [p_shamt_nbits-1:0] shamt,
output logic [ p_nbits-1:0] out
);
assign out = (in << shamt);
endmodule
| 8.380756 |
module vc_RightLogicalShifter #(
parameter p_nbits = 1,
parameter p_shamt_nbits = 1
) (
input logic [ p_nbits-1:0] in,
input logic [p_shamt_nbits-1:0] shamt,
output logic [ p_nbits-1:0] out
);
assign out = (in >> shamt);
endmodule
| 8.285177 |
module arithmeticlogicunit (
input [31:0] A,
B, //Inputs
input [ 3:0] OP, //Operation selector
output reg [31:0] OUT, //Result of the operation
output wire zero //Checks if the operation result is 0
);
assign zero = (OUT == 0); //If the result of the op is 0, the flag is... | 8.012123 |
module half_adder (
a,
b,
h,
l
);
input wire a, b;
output wire h, l;
and_gate u0 (
.a(a),
.b(b),
.and_s(h)
);
xor_gate u1 (
.a(a),
.b(b),
.xor_s(l)
);
endmodule
| 6.966406 |
module add_16 (
a,
b,
c,
s,
c_out
);
input wire [15:0] a, b;
input wire c;
output [15:0] s;
output c_out;
assign {c_out, s} = a + b + c;
endmodule
| 6.977906 |
module subt_16 (
a,
b,
out
);
input wire [15:0] a, b;
output [15:0] out;
assign out = a - b;
endmodule
| 7.466112 |
module switch (
s,
d,
c1,
c0
);
input wire s, d;
output c1, c0;
wire temp;
inv_gate u0 (
.a(s),
.inv_s(temp)
);
and_gate u1 (
.a(temp),
.b(d),
.and_s(c0)
);
and_gate u2 (
.a(s),
.b(d),
.and_s(c1)
);
endmodule
| 6.864438 |
module ArithmeticUnit (
A,
B,
B15to0,
AandB,
AorB,
notB,
shlB,
shrB,
AaddB,
AsubB,
AmulB,
AcmpB,
aluout,
cin,
zout,
cout
);
input [15:0] A, B;
input B15to0, AandB, AorB, notB, shlB, shrB, AaddB, AsubB, AmulB, AcmpB;
input cin;
output [15:0] aluout;... | 6.524404 |
module ArithmeticUnit_Testbench #(
parameter WIDTH = 32
) (); // Ԫλ
// ʹõļĴ
reg OP = 1'b0; // 1λԪ룬0Ϊӷ1Ϊ
reg [WIDTH - 1 : 0] A; // (WIDTH)λ/A
reg [WIDTH - 1 : 0] B; // (WIDTH)λ/ B
wire [WIDTH - 1 : 0] Y; // (WIDTH)λY
wire SF; // 1λYλ
wire CF; ... | 6.524404 |
module HA (
(* dont_touch="true" *) input x,
(* dont_touch="true" *) input y,
(* dont_touch="true" *) output cout,
(* dont_touch="true" *) output s
);
assign cout = x & y;
assign s = x ^ y;
endmodule
| 7.380652 |
module FA (
(* dont_touch="true" *) input x,
(* dont_touch="true" *) input y,
(* dont_touch="true" *) input ci,
(* dont_touch="true" *) output cout,
(* dont_touch="true" *) output s
);
(* dont_touch="true" *)wire wr1;
(* dont_touch="true" *)wire wr2;
(* dont_touch="true" *)wire wr3;
HA h... | 7.514487 |
module RCA (
(* dont_touch="true" *) input [3:0] x,
(* dont_touch="true" *) input [3:0] y,
(* dont_touch="true" *) input ci,
(* dont_touch="true" *) output cout,
(* dont_touch="true" *) output [3:0] s
);
(* dont_touch="true" *)wire wr4;
(* dont_touch="true" *)wire wr5;
(* dont_touch="true" *)w... | 7.975596 |
module parametric_RCA #(
parameter SIZE = 8
) (
(* dont_touch="true" *) input [SIZE-1:0] x,
(* dont_touch="true" *) input [SIZE-1:0] y,
(* dont_touch="true" *) input ci,
(* dont_touch="true" *) output cout,
(* dont_touch="true" *) output [SIZE-1:0] s
);
(* dont_touch="true" *) wire temp[SIZE:0... | 7.912871 |
module Arithmetic_logic (
A,
B,
Cin,
Omultiply,
OaddSub
);
input [1:0] A;
input [1:0] B;
input Cin;
output [3:0] Omultiply;
output [3:0] OaddSub;
multiplier multiplier1 (
A,
B,
Omultiply
);
Add_Sub Add_Sub1 (
A,
B,
Cin,
OaddSub
);
endmodule... | 7.420924 |
module arithmetic_logic_system (
input [15:0] A,
input [15:0] B,
input [15:0] Imm,
input ALUsrc,
input [2:0] ALUop,
input clk,
output AltB,
output [15:0] ALUout
);
wire [15:0] mux_out, alu_out;
wire a_ltb;
reg [15:0] ALUout_reg;
reg AltB_reg;
alu_16_bit alu (
.A(A),
... | 6.612484 |
module inv16 (
a,
inv16_s
);
input wire [15:0] a;
output wire [15:0] inv16_s;
assign inv16_s = ~a;
endmodule
| 7.602931 |
module xor16 (
a,
b,
xor16_s
);
input wire [15:0] a, b;
output [15:0] xor16_s;
assign xor16_s = a ^ b;
endmodule
| 8.069681 |
module or16 (
a,
b,
or16_s
);
input [15:0] a, b;
output [15:0] or16_s;
assign or16_s = a | b;
endmodule
| 7.233483 |
module and16 (
a,
b,
and16_s
);
input [15:0] a, b;
output [15:0] and16_s;
assign and16_s = a & b;
endmodule
| 7.566975 |
module select16 (
s,
d1,
d0,
out
);
input s;
input [15:0] d1, d0;
output [15:0] out;
assign out = s ? d1 : d0;
endmodule
| 7.241005 |
module sub16 (
a,
b,
sub16_s
);
input [15:0] a, b;
output [15:0] sub16_s;
assign sub16_s = a - b;
endmodule
| 7.317719 |
module add16 (
a,
b,
add16_s
);
input [15:0] a, b;
output [15:0] add16_s;
assign add16_s = a + b;
endmodule
| 6.87555 |
module Logic_unit (
op1,
op0,
X,
Y,
out
);
input wire op0, op1;
input wire [15:0] X, Y;
output wire [15:0] out;
wire [15:0] tempi, tempxor, tempor, tempa, sel1, sel0;
inv16 u0 (
.a(X),
.inv16_s(tempi)
);
xor16 u1 (
.a(X),
.b(Y),
.xor16_s(tempxor)
);
o... | 6.91066 |
module ALU (
u,
op0,
op1,
zx,
sw,
X,
Y,
out
);
input [15:0] X, Y;
input u, op0, op1, zx, sw;
output [15:0] out;
wire zero;
wire [15:0] sel0, sel1, sel2, sel3, au, lu;
assign zero = 1'b0;
arithmetic_unit u0 (
.op1(op1),
.op0(op0),
.X (sel2),
.Y (... | 6.707544 |
module Arithmetic_logic_unity #(
parameter DATA_WIDTH = 32,
parameter OP_WIDTH = 5
) (
input [(OP_WIDTH-1):0] op,
shamt,
input [(DATA_WIDTH-1):0] data_1,
data_2,
output reg [(DATA_WIDTH-1):0] result,
output zero
);
wire [(DATA_WIDTH-1):0] n_zero;
assign n_zero = (data_2 == 0) ? 1... | 7.420924 |
module arithmetic_logic_unit_test;
reg [15:0] x;
reg [15:0] y;
reg nx, ny, zx, zy, f, no;
wire [15:0] out;
wire zr, ng;
arithmetic_logic_unit alu (
.x (x),
.y (y),
.zx (zx),
.nx (nx),
.zy (zy),
.ny (ny),
.f (f),
.no (no),
.out(out),
.zr (zr),
... | 6.612484 |
module shift_left(enable, in, out);
// module that shifts the input left when the enable input is 1
parameter n = 8;
input enable;
input [n:0] in;
output [n:0] out;
integer i;
always @(shift)
begin
for (i = 0; i < n; i = i+1)
begin
out[i+1] <= in[i]
end
end
endmodule
| 7.68256 |
module divider_restore ();
endmodule
| 7.308109 |
module divider_nonrestore (
quotient,
remainder,
numerator,
denominator
);
parameter n = 8;
input [n:0] numerator;
input [n+1:0] denominator;
output [n+1:0] remainder;
output [n:0] quotient;
always @(remainder) begin
if (remainder < 0) begin
remainder = remainder + denominator;
... | 7.831156 |
module arithmetic_operators ();
initial begin
$display(" 5 + 10 = %d", 5 + 10);
$display(" 5 - 10 = %d", 5 - 10);
$display(" 10 - 5 = %d", 10 - 5);
$display(" 10 * 5 = %d", 10 * 5);
$display(" 10 / 5 = %d", 10 / 5);
$display(" 10 / -5 = %d", 10 / -5);
$display(" 10 %s 3 = %d"... | 7.467791 |
module arithmetic_operators_tb ();
// 1) Declare local reg and wire identifiers
parameter n = 4;
reg [n - 1:0] x, y;
wire [n - 1:0] s;
wire cout, overflow;
// 2) Instantiate the unit under test
arithmetic_operators uut0 (
.x(x),
.y(y),
.s(s),
.cout(cout),
.overflow(overflow)... | 7.467791 |
module arithmetic_shift (
output reg [3:0] out,
input [3:0] in,
input direction
);
always @* begin
if (direction == 1) out = {in[2:0], 1'b0};
else out = {in[3], in[3:1]};
end
endmodule
| 7.423881 |
module arithmetic_shifter (
dataIn,
amount,
dir,
dataOut
);
function integer log2;
input integer value;
begin
value = value - 1;
for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1;
end
endfunction
parameter data_width_in = 8;
parameter shiftAmount = 16;
loc... | 7.423881 |
module Arithmetic_unit #(
parameter A_WIDTH = 8,
B_WIDTH = 8,
OUT_WIDTH = 16,
ALU_FUN_WIDTH = 2
) (
input wire [ A_WIDTH-1:0] A,
input wire [ B_WIDTH-1:0] B,
input wire [ALU_FUN_WIDTH-1:0] ALU_FUN,
input wire Arith_Enable,
input wire ... | 7.292905 |
module arithmod (
Out,
V,
N,
Z,
A,
B,
Sel,
Mem
);
input [15:0] A, B;
input [1:0] Sel;
input Mem;
output [15:0] Out;
output V, N, Z;
wire cout;
wire [15:0] adder_out, paddsb_out, adder_result, B_nor, sel_nor;
wire sign;
always @(Out) begin
//$display("adder_result=... | 6.744183 |
module arithShiftRight (
output reg [31:0] out,
input [31:0] inA,
inB
);
wire [31:0] rightOut0, leftOut, rightOut1;
always @(inA or inB) begin
out = (inA >> inB) | (((inA >> 31) << (inB + 1)) - 1) ^ 32'hffffffff;
end
endmodule
| 6.575718 |
module shiftRightTest;
reg [31:0] TinA, TinB;
wire [31:0] Tout;
initial begin
$dumpfile("shiftRightTest.vcd");
$dumpvars(0, shiftRightTest);
$monitorh($time,, Tout,, TinA,, TinB);
TinA = 32'hf0;
TinB = 32'd2;
#1000;
TinA = 32'hfffffff0;
#1000;
TinB = 32'd4;
#1000;
end
... | 6.804859 |
module describes a Arithmatic unit of ALU. /////
/// This will have two inputs of 16 bits each. /////
/// It has to provide either Arithmatic operation ////
////////////////////////////////////////////////////////////////////////////
module arith(a,b,opcode,outau);
input [15:0] a;
input [15:0] b;
input [2:0] opc... | 7.463649 |
module \$alu (
A,
B,
CI,
BI,
X,
Y,
CO
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
parameter _TECHMAP_CONSTMSK_CI_ = 0;
parameter _TECHMAP_CONSTVAL_CI_ = 0;
(* force_downto *)
input [A_WIDTH-1:0] ... | 8.218654 |
module _80_quicklogic_alu (
A,
B,
CI,
BI,
X,
Y,
CO
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 2;
parameter B_WIDTH = 2;
parameter Y_WIDTH = 2;
parameter _TECHMAP_CONSTVAL_CI_ = 0;
parameter _TECHMAP_CONSTMSK_CI_ = 0;
(* force_downto *)
input [A_... | 7.806042 |
module Arith_SR_16bit (
F,
A
);
input signed [15:0] A;
output reg signed [15:0] F;
always @(A) begin
F = A >>> 1;
end
endmodule
| 7.020633 |
module: arith
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module arith_tb;
// Inputs
reg [7:0] a;
reg [7:0] b;
// Outputs
wire [7:0] out;
// Instantiate the Unit Under Test (UU... | 6.625688 |
module arith_unit (
i_mode,
i_op,
i_A,
i_B,
i_C,
i_D,
o_out1,
o_out2
);
input i_mode; // 1'b0 - simple arithmetics, 1'b1 - complex arithmetics.
input [2:0] i_op; // 7 possible operations.
input [15:0] i_A, i_B, i_C, i_D; // input data.
output reg [15:0] o_out1, o_out2; // o... | 7.021101 |
module aritmeticos ();
initial $display("Circuitos aritméticos");
endmodule
| 7.02379 |
module arit_ckt #(
parameter SIZE = 16
) (
input [SIZE-1:0] SRC,
DST,
input BW,
input [ 1:0] S,
input Cin,
output [SIZE-1:0] ARIT_OUT,
output Cout_arit,
V
);
wire [SIZE-1:0] DST_BAR;
assign DST_BAR = ~DST;
// Outputs from first level o... | 8.630208 |
module ari_shifter_right (
in,
out,
shiftAmount
);
parameter data_WIDTH = 32;
parameter shift_WIDTH = 5;
input [data_WIDTH-1:0] in;
input [shift_WIDTH-1:0] shiftAmount;
output [data_WIDTH-1:0] out;
assign out = in >>> shiftAmount;
endmodule
| 8.378395 |
module Arkanoid (
input iCLK_50,
input btn_W,
btn_E,
btn_N,
btn_S,
input [3:0] iSW,
input iROT_A,
iROT_B,
output oVGA_R,
oVGA_G,
oVGA_B,
oHS,
oVS,
output [7:0] oLED
);
localparam BALL_NUM = 2;
localparam SHOT_NUM = 2;
reg clk_25;
wire middle, b_dis;
wir... | 6.742823 |
module ARKLED (
ROW,
COL_RED,
COL_GREEN,
CLK
);
output wire [7:0] ROW, COL_RED, COL_GREEN;
input CLK;
//Counter 用于计数，实现模8计数功能
wire [2:0] Counter;
/*
initial begin
SetLEDState m1(CLK);
end
*/
Mod8Counter m2 (
Counter,
CLK
);
ARKPrinter m3 (
ROW,
COL_RED,
... | 6.660117 |
module ARKLEDWithSwitchAndKeys (
ROW,
COL_RED,
COL_GREEN,
CLK,
Switch,
Key
);
output wire [7:0] ROW, COL_RED, COL_GREEN;
input CLK;
//开关用于切换低中高音和自动演奏
input [3:0] Switch;
//按键用于发声控制
input [6:0] Key;
//消抖后信号输出
wire [7:0] KeyState;
//Counter 用于计数，实现模8计数功能
wire [2:0] Counter;
... | 7.223807 |
module arlet_6502 (
input clk, // clock signal
input enable, // clock enable strobe
input rst_n, // active high reset signal
output reg [15:0] ab, // address bus
input [ 7:0] dbi, // 8-bit data bus (input)
output reg [ 7:0] ... | 7.039329 |
module ALU (
clk,
op,
right,
AI,
BI,
CI,
CO,
BCD,
OUT,
V,
Z,
N,
HC,
RDY
);
input clk;
input right;
input [3:0] op; // operation
input [7:0] AI;
input [7:0] BI;
input CI;
input BCD; // BCD style carry
output [7:0] OUT;
output CO;
output V;
o... | 6.737201 |
module armleocpu_alu (
input is_op,
input is_op_imm,
input [4:0] shamt,
input [6:0] funct7,
input [2:0] funct3,
input [31:0] rs1,
input [31:0] rs2,
input [31:0] simm12,
output reg [31:0] result,
output reg illegal_instruction
);
wire is_addi = is_op_imm && ... | 8.424951 |
module armleocpu_brcond(
output reg branch_taken,
output reg incorrect_instruction,
input [2:0] funct3,
input [31:0] rs1,
input [31:0] rs2
);
always @* begin
incorrect_instruction = 0;
case(funct3)
3'b000: //beq
branch_taken = rs1 == rs2;
3'b001: //bne
branch_taken = rs1 != rs2;
3'b100: //bl... | 6.968745 |
module armleocpu_loadgen (
input [1:0] inwordOffset,
input [2:0] loadType,
input [31:0] LoadGenDataIn,
output reg [31:0] LoadGenDataOut,
output reg LoadMissaligned,
output reg LoadUnknownType
);
wire [ 4:0] roffset = {inwordOffset, 3'b000};
wire [31:0] rshift = LoadGenDataIn >> roffset;
... | 6.853292 |
module armleocpu_multiplier (
input wire clk,
input wire rst_n,
input wire valid,
input wire [31:0] factor0,
input wire [31:0] factor1,
output reg ready,
output wire [63:0] result
);
assign result = accumulator;
/*
multiply two 32b numbers
a = a_up << 16 + a_down;
b = b_up <... | 6.503524 |
module armleocpu_regfile (
input clk,
input rst_n,
input [ 4:0] rs1_addr,
output [31:0] rs1_rdata,
input [ 4:0] rs2_addr,
output [31:0] rs2_rdata,
input [4:0] rd_addr,
input [31:0] rd_wdata,
input rd_write
);
reg [31:0] regs[31:0];
integer i = 0;
always @(posedge clk)... | 7.172743 |
module armleocpu_storegen (
input [1:0] inwordOffset,
input [1:0] storegenType,
input [31:0] storegenDataIn,
output wire [31:0] storegenDataOut,
output wire [ 3:0] storegenDataMask,
output wire storegenMissAligned,
output wire storegenUnknownType
);
`include "armleocpu_def... | 7.06965 |
module armleocpu_tlb (
clk,
rst_n,
command,
virtual_address,
hit,
accesstag_r,
phys_r,
virtual_address_w,
accesstag_w,
phys_w,
invalidate_set_index
);
parameter ENTRIES_W = 4;
parameter WAYS_W = 2;
localparam WAYS = 2 ** WAYS_W;
parameter disable_debug = 0;
inpu... | 6.777066 |
module armleocpu_unsigned_divider (
input wire clk,
input wire rst_n,
input wire fetch,
input wire [31:0] dividend,
input wire [31:0] divisor,
output reg ready,
output reg division_by_zero,
output reg [31:0] quotient,
output reg [31:0] remainder
);
reg [31:0] r_di... | 7.370739 |
module armleo_gpio (
`ifdef USE_POWER_PINS
inout vddio,
inout vssio,
inout vdd,
inout vss,
`endif
inout pad,
input med_enable,
input strong_enable,
input out_l,
input oe_l,
output in
);
endmodule
| 7.389926 |
module armleo_gpio (
`ifdef USE_POWER_PINS
inout vddio,
inout vssio,
inout vdd,
inout vss,
`endif
inout pad,
input med_enable,
input strong_enable,
input out_l,
input oe_l,
output in
);
assign pad = oe_l ? out_l : 1'bZ;
assign in = pad;
endmodule
| 7.389926 |
module single_port_ram_21_8 (
clk,
data,
we,
addr,
out
);
`define ADDR_WIDTH_21_8 8
`define DATA_WIDTH_21_8 21
input clk;
input [`DATA_WIDTH_21_8-1:0] data;
input we;
input [`ADDR_WIDTH_21_8-1:0] addr;
output [`DATA_WIDTH_21_8-1:0] out;
reg [`DATA_WIDTH_21_8-1:0] out;
reg [`DAT... | 8.023817 |
module single_port_ram_128_8 (
clk,
data,
we,
addr,
out
);
`define ADDR_WIDTH_128_8 8
`define DATA_WIDTH_128_8 128
input clk;
input [`DATA_WIDTH_128_8-1:0] data;
input we;
input [`ADDR_WIDTH_128_8-1:0] addr;
output [`DATA_WIDTH_128_8-1:0] out;
reg [`DATA_WIDTH_128_8-1:0] out;
r... | 8.023817 |
module a25_barrel_shift (
i_clk,
i_in,
i_carry_in,
i_shift_amount,
i_shift_imm_zero,
i_function,
o_out,
o_carry_out,
o_stall
);
/************************* IO Declarations *********************/
input i_clk;
input [31:0] i_in;
input i_carry_in;
input [7:0] i_shift_amount... | 7.686943 |
module a25_multiply (
i_clk,
i_core_stall,
i_a_in,
i_b_in,
i_function,
i_execute,
o_out,
o_flags,
o_done
);
input i_clk;
input i_core_stall;
input [31:0] i_a_in; // Rds
input [31:0] i_b_in; // Rm
input [1:0] i_function;
input i_execute;
output [31:0] o_out;
out... | 7.219736 |
module a25_write_back(
i_clk,
i_mem_stall,
i_mem_read_data,
i_mem_read_data_valid,
i_mem_load_rd,
o_wb_read_data,
o_wb_read_data_valid,
o_wb_load_rd,
i_daddress,
// i_daddress_valid
);
input ... | 6.942168 |
module HazardDetection (
input EX_memRead_in,
input [4:0] EX_write_reg,
input [63:0] ID_PC,
input [31:0] ID_IC,
output reg IFID_write_out,
output reg PC_Write_out,
output reg Control_mux_out
);
always @(*) begin
if (EX_memRead_in == 1'b1 && ((EX_write_reg === ID_IC[9:5]) || (EX_write_r... | 6.580064 |
module IFID (
input CLOCK,
input [63:0] PC_in,
input [31:0] IC_in,
input Hazard_in,
output reg [63:0] PC_out,
output reg [31:0] IC_out
);
always @(negedge CLOCK) begin
if (Hazard_in !== 1'b1) begin
PC_out <= PC_in;
IC_out <= IC_in;
end
end
endmodule
| 8.166279 |
module IDEX (
input CLOCK,
input [1:0] aluop_in,
input alusrc_in,
input isZeroBranch_in,
input isUnconBranch_in,
input memRead_in,
input memwrite_in,
input regwrite_in,
input mem2reg_in,
input [63:0] PC_in,
input [63:0] regdata1_in,
input [63:0] regdata2_in,
input [63... | 7.449647 |
module EXMEM (
input CLOCK,
input isZeroBranch_in, // M Stage
input isUnconBranch_in, // M Stage
input memRead_in, // M Stage
input memwrite_in, // M Stage
input regwrite_in, // WB Stage
input mem2reg_in, // WB Stage
input [63:0] shifted_PC_in,
input alu_zero_in,
input [63:... | 6.633817 |
module MEMWB (
input CLOCK,
input [63:0] mem_address_in,
input [63:0] mem_data_in,
input [4:0] write_reg_in,
input regwrite_in,
input mem2reg_in,
output reg [63:0] mem_address_out,
output reg [63:0] mem_data_out,
output reg [4:0] write_reg_out,
output reg regwrite_out,
output... | 6.910178 |
module Registers (
input CLOCK,
input [4:0] read1,
input [4:0] read2,
input [4:0] writeReg,
input [63:0] writeData,
input CONTROL_REGWRITE,
output reg [63:0] data1,
output reg [63:0] data2
);
reg [63:0] Data[31:0];
integer initCount;
initial begin
for (initCount = 0; initCount... | 7.405039 |
module Data_Memory (
input [63:0] inputAddress,
input [63:0] inputData,
input CONTROL_MemWrite,
input CONTROL_MemRead,
output reg [63:0] outputData
);
reg [63:0] Data[31:0];
integer initCount;
initial begin
for (initCount = 0; initCount < 32; initCount = initCount + 1) begin
Data[in... | 7.239913 |
module ALU (
input [63:0] A,
input [63:0] B,
input [4:0] CONTROL,
output reg [63:0] RESULT,
output reg ZEROFLAG
);
always @(*) begin
case (CONTROL)
5'b00000: RESULT = A & B;
5'b00001: RESULT = A | B;
5'b00010: RESULT = A + B;
5'b00110: RESULT = A - B;
5'b00111: RE... | 7.960621 |
module Forward_ALU_Mux (
input [63:0] reg_ex_in,
input [63:0] reg_wb_in,
input [63:0] reg_mem_in,
input [1:0] forward_control_in,
output reg [63:0] reg_out
);
always @(*) begin
case (forward_control_in)
2'b01: reg_out <= reg_wb_in;
2'b10: reg_out <= reg_mem_in;
default: r... | 7.604902 |
module ALU_Mux (
input [63:0] input1,
input [63:0] input2,
input CONTROL_ALUSRC,
output reg [63:0] out
);
always @(input1, input2, CONTROL_ALUSRC, out) begin
if (CONTROL_ALUSRC === 0) begin
out <= input1;
end else begin
out <= input2;
end
end
endmodule
| 7.331368 |
module ID_Mux (
input [4:0] read1_in,
input [4:0] read2_in,
input reg2loc_in,
output reg [4:0] reg_out
);
always @(read1_in, read2_in, reg2loc_in) begin
case (reg2loc_in)
1'b0: begin
reg_out <= read1_in;
end
1'b1: begin
reg_out <= read2_in;
end
default... | 7.509663 |
module WB_Mux (
input [63:0] input1,
input [63:0] input2,
input mem2reg_control,
output reg [63:0] out
);
always @(*) begin
if (mem2reg_control == 0) begin
out <= input1;
end else begin
out <= input2;
end
end
endmodule
| 7.226496 |
module SignExtend (
input [31:0] inputInstruction,
output reg [63:0] outImmediate
);
always @(inputInstruction) begin
if (inputInstruction[31:26] == 6'b000101) begin // B
outImmediate[25:0] = inputInstruction[25:0];
outImmediate[63:26] = {64{outImmediate[25]}};
end else if (inputInstruc... | 7.619369 |
module SL2 (
input [`DATA_WIDTH-1:0] in,
output [`DATA_WIDTH-1:0] out
);
assign out = {in[29:0], 2'b00};
endmodule
| 6.690903 |
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