code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module fifo_v2_DEPTH1_ALM_EMPTY_TH0_ALM_FULL_TH0 (
clk_i,
rst_ni,
flush_i,
testmode_i,
full_o,
empty_o,
alm_full_o,
alm_empty_o,
data_i,
push_i,
data_o,
pop_i
);
input [133:0] data_i;
output [133:0] data_o;
input clk_i;
input rst_ni;
input flush_i;
input testmode_i;
input push_i;
input pop_i;
output full_o;
output empty_o;
output alm_full_o;
output alm_empty_o;
wire [133:0] data_o;
wire full_o, empty_o, alm_full_o, alm_empty_o, N0, N1, N2, N3;
wire [0:0] usage;
assign N0 = N1 & 1'b0;
assign alm_full_o = ~N0;
assign N1 = ~usage[0];
assign N2 = usage[0] & N3;
assign alm_empty_o = ~N2;
assign N3 = ~1'b0;
fifo_v3_0_00000020_00000001 i_fifo_v3 (
.clk_i(clk_i),
.rst_ni(rst_ni),
.flush_i(flush_i),
.testmode_i(testmode_i),
.full_o(full_o),
.empty_o(empty_o),
.usage_o(usage[0]),
.data_i(data_i),
.push_i(push_i),
.data_o(data_o),
.pop_i(pop_i)
);
endmodule
| 7.120907 |
module amo_buffer (
clk_i,
rst_ni,
flush_i,
valid_i,
ready_o,
amo_op_i,
paddr_i,
data_i,
data_size_i,
amo_req_o,
amo_resp_i,
amo_valid_commit_i,
no_st_pending_i
);
input [3:0] amo_op_i;
input [63:0] paddr_i;
input [63:0] data_i;
input [1:0] data_size_i;
output [134:0] amo_req_o;
input [64:0] amo_resp_i;
input clk_i;
input rst_ni;
input flush_i;
input valid_i;
input amo_valid_commit_i;
input no_st_pending_i;
output ready_o;
wire [134:0] amo_req_o;
wire ready_o, amo_valid, flush_amo_buffer, N0, N1;
fifo_v2_DEPTH1_ALM_EMPTY_TH0_ALM_FULL_TH0 i_amo_fifo (
.clk_i(clk_i),
.rst_ni(rst_ni),
.flush_i(flush_amo_buffer),
.testmode_i(1'b0),
.full_o(amo_valid),
.empty_o(ready_o),
.data_i({amo_op_i, paddr_i, data_i, data_size_i}),
.push_i(valid_i),
.data_o({amo_req_o[133:130], amo_req_o[127:0], amo_req_o[129:128]}),
.pop_i(amo_resp_i[64])
);
assign amo_req_o[134] = N0 & amo_valid;
assign N0 = no_st_pending_i & amo_valid_commit_i;
assign flush_amo_buffer = flush_i & N1;
assign N1 = ~amo_valid_commit_i;
endmodule
| 7.823248 |
module lzc_00000004 (
in_i,
cnt_o,
empty_o
);
input [3:0] in_i;
output [1:0] cnt_o;
output empty_o;
wire [1:0] cnt_o;
wire empty_o, N0, index_nodes_2__0_, index_nodes_1__0_, N1;
wire [2:0] sel_nodes;
assign cnt_o[1] = ~sel_nodes[1];
assign cnt_o[0] = (N0) ? index_nodes_1__0_ : (N1) ? index_nodes_2__0_ : 1'b0;
assign N0 = sel_nodes[1];
assign index_nodes_1__0_ = ~in_i[0];
assign index_nodes_2__0_ = ~in_i[2];
assign sel_nodes[0] = sel_nodes[1] | sel_nodes[2];
assign N1 = ~sel_nodes[1];
assign sel_nodes[1] = in_i[0] | in_i[1];
assign sel_nodes[2] = in_i[2] | in_i[3];
assign empty_o = ~sel_nodes[0];
endmodule
| 6.51737 |
module ARINC429 (
input wire [1 : 0] nvel,
input wire [7 : 0] adr,
input wire [22 : 0] dat,
input wire GCLK,
output wire TXD0,
output wire TXD1,
input wire RXD0,
input wire RXD1,
input wire st,
output reg [7:0] sr_adr,
output reg [22:0] sr_dat,
output reg ce_wr,
input wire rec_disp, // reciever dispatcher
input wire reset
);
AR_TXD TX (
.clk(GCLK),
.Nvel(nvel),
.ADR(adr),
.DAT(dat),
.st(st),
.TXD0(TXD0),
.TXD1(TXD1),
.reset(reset)
);
wire [7:0] sr_adr_1;
wire [22:0] sr_dat_1;
wire ce_wr_1;
AR_RXD RX (
.clk(GCLK),
.in0(RXD0),
.in1(RXD1),
.sr_dat(sr_dat_1),
.sr_adr(sr_adr_1),
.ce_wr(ce_wr_1)
);
wire [7:0] sr_adr_2;
wire [22:0] sr_dat_2;
wire ce_wr_2;
AR_RXD_2 RX_2 (
.clk(GCLK),
.in0(RXD0),
.in1(RXD1),
.sr_dat(sr_dat_2),
.sr_adr(sr_adr_2),
.ce_wr(ce_wr_2)
);
always @(posedge GCLK) begin
sr_dat <= rec_disp ? sr_dat_1 : sr_dat_2;
sr_adr <= rec_disp ? sr_adr_1 : sr_adr_2;
ce_wr <= rec_disp ? ce_wr_1 : ce_wr_2;
end
endmodule
| 7.107397 |
module AritgmeticLogicUnit (
input [63:0] A,
input [63:0] B,
input [2:0] aluOp,
output reg [63:0] addres,
output reg zeroCU
);
always @(aluOp, A, B) begin
case (aluOp)
3'b000: begin
addres <= A + B;
if ((A + B) == 0) zeroCU <= 1;
else zeroCU <= 0;
end
3'b001: begin
addres <= A - B;
if ((A - B) == 0) zeroCU <= 1;
else zeroCU <= 0;
end
3'b010: begin
addres <= A & B;
if ((A & B) == 0) zeroCU <= 1;
else zeroCU <= 0;
end
3'b011: begin
addres <= A | B;
if ((A || B) == 0) zeroCU <= 1;
else zeroCU <= 0;
end
3'b100: begin
addres <= B;
if (B == 0) zeroCU <= 1;
else zeroCU <= 0;
end
endcase
end
endmodule
| 6.800323 |
module Arith (
a,
b,
cin,
s,
out
);
input [1:0] a;
input [1:0] b;
input cin;
input [1:0] s;
output [3:0] out;
reg [3:0] oreg;
wire [3:0] w1;
wire [3:0] w2;
wire [3:0] w3;
wire [3:0] w4;
fullfull ful (
a,
b,
cin,
w3,
cin
);
Multiply m (
a,
b,
w4
);
assign w1[0] = a[0];
assign w1[1] = a[1];
assign w1[2] = 1'b0;
assign w1[3] = 1'b0;
nand g1 (w2[0], a[0], b[0]);
nand g2 (w2[1], a[1], b[1]);
assign w2[2] = 1'b0;
assign w2[3] = 1'b0;
always @s begin
case (s)
2'b00: oreg = w1;
2'b01: oreg = w2;
2'b10: oreg = w3;
2'b11: oreg = w4;
endcase
end
assign out = oreg;
endmodule
| 7.328877 |
module arith (
input [7:0] a,
input [7:0] b,
output [7:0] usum,
output [7:0] ssum,
output [7:0] usub,
output [7:0] ssub,
output [7:0] umul,
output [7:0] smul,
output [7:0] udiv,
output [7:0] sdiv,
output [7:0] umod,
output [7:0] smod,
output [7:0] upow,
output [7:0] spow
);
assign usum = a + b;
assign ssum = $signed(a) + $signed(b);
assign usub = a - b;
assign ssub = $signed(a) - $signed(b);
assign umul = a * b;
assign smul = $signed(a) * $signed(b);
assign udiv = a / b;
assign sdiv = $signed(a) / $signed(b);
assign umod = a % b;
assign smod = $signed(a) % $signed(b);
// assign upow = a **b;
// assign spow = $signed(a) **$signed(b);
endmodule
| 6.902759 |
module arithAdd (
a,
b,
y
);
input [7:0] a;
input [7:0] b;
output [7:0] y;
reg [7:0] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 6.717422 |
module arithbox (
arithop,
calc_sz,
ci,
co,
af,
ai,
sa,
sb,
opa,
opb,
resa,
cmp
);
input [3:0] arithop;
input [3:0] calc_sz;
input [31:0] opa, opb;
output reg [31:0] resa;
input ci, ai;
output reg co, af, sa, sb, cmp;
wire [4:0] af2, af3, af4, af5;
assign af2 = opa[3:0] + opb[3:0];
assign af3 = opa[3:0] + opb[3:0] + ci;
assign af4 = opa[3:0] - opb[3:0];
assign af5 = opa[3:0] - opb[3:0] - ci;
always @(*)
case (arithop)
4'b0000:
if (calc_sz == 4) begin
{co, resa[31:0]} <= opa[31:0] + opb[31:0];
sa <= opa[31];
sb <= opb[31];
af <= af2[4];
cmp <= 0;
end else if (calc_sz == 2) begin
{co, resa[15:0]} <= opa[15:0] + opb[15:0];
sa <= opa[15];
sb <= opb[15];
af <= af2[4];
resa[31:16] <= opa[31:16];
cmp <= 0;
end else begin
{co, resa[7:0]} <= opa[7:0] + opb[7:0];
sa <= opa[7];
sb <= opb[7];
af <= af2[4];
resa[31:8] <= opa[31:8];
cmp <= 0;
end // add
4'b0001: begin
resa[31:0] <= opa[31:0] | opb[31:0];
sa <= 1;
sb <= 0;
af <= ai;
co <= 0;
cmp <= 0;
end // or
4'b0010:
if (calc_sz == 4) begin
{co, resa[31:0]} <= opa[31:0] + opb[31:0] + ci;
sa <= opa[31];
sb <= opb[31];
af <= af3[4];
cmp <= 0;
end else if (calc_sz == 2) begin
{co, resa[15:0]} <= opa[15:0] + opb[15:0] + ci;
sa <= opa[15];
sb <= opb[15];
af <= af3[4];
resa[31:16] <= opa[31:16];
cmp <= 0;
end else begin
{co, resa[7:0]} <= opa[7:0] + opb[7:0] + ci;
sa <= opa[7];
sb <= opb[7];
af <= af3[4];
resa[31:8] <= opa[31:8];
cmp <= 0;
end // adc
4'b0011:
if (calc_sz == 4) begin
{co, resa[31:0]} <= opa[31:0] - opb[31:0] - ci;
sa <= opa[31];
sb <= ~opb[31];
af <= af5[4];
cmp <= 0;
end else if (calc_sz == 2) begin
{co, resa[15:0]} <= opa[15:0] - opb[15:0] - ci;
sa <= opa[15];
sb <= ~opb[15];
af <= af5[4];
resa[31:16] <= opa[31:16];
cmp <= 0;
end else begin
{co, resa[7:0]} <= opa[7:0] - opb[7:0] - ci;
sa <= opa[7];
sb <= ~opb[7];
af <= af5[4];
resa[31:8] <= opa[31:8];
cmp <= 0;
end // sbc & cmp
4'b0100: begin
resa[31:0] <= opa[31:0] & opb[31:0];
sa <= 1;
sb <= 0;
af <= ai;
co <= 0;
cmp <= 0;
end // and
4'b0111: begin
if (calc_sz == 4) begin
{co, resa[31:0]} <= opa[31:0] - opb[31:0];
sa <= opa[31];
sb <= ~opb[31];
af <= af4[4];
cmp <= 1;
end else if (calc_sz == 2) begin
{co, resa[15:0]} <= opa[15:0] - opb[15:0];
sa <= opa[15];
sb <= ~opb[15];
af <= af4[4];
cmp <= 1;
resa[31:16] <= opa[31:16];
end else begin
{co, resa[7:0]} <= opa[7:0] - opb[7:0];
sa <= opa[7];
sb <= ~opb[7];
af <= af4[4];
cmp <= 1;
resa[31:8] <= opa[31:8];
end // sub
end
4'b0101:
if (calc_sz == 4) begin
{co, resa[31:0]} <= opa[31:0] - opb[31:0];
sa <= opa[31];
sb <= ~opb[31];
af <= af4[4];
cmp <= 0;
end else if (calc_sz == 2) begin
{co, resa[15:0]} <= opa[15:0] - opb[15:0];
sa <= opa[15];
sb <= ~opb[15];
af <= af4[4];
cmp <= 0;
resa[31:16] <= opa[31:16];
end else begin
{co, resa[7:0]} <= opa[7:0] - opb[7:0];
sa <= opa[7];
sb <= ~opb[7];
af <= af4[4];
cmp <= 0;
resa[31:8] <= opa[31:8];
end // sub
4'b0110: begin
resa[31:0] <= opa[31:0] ^ opb[31:0];
sa <= 1;
sb <= 0;
af <= ai;
co <= 0;
cmp <= 0;
end // xor
default: begin
resa[31:0] <= opa[31:0];
sa <= 0;
sb <= 0;
af <= ai;
co <= ci;
cmp <= 1;
end
endcase
endmodule
| 6.724017 |
module arithm (
op_a,
op_b,
arithm_opsel,
result,
ovf,
cf
);
input [2:0] arithm_opsel;
input [`REG_WIDTH-1:0] op_a;
input [`REG_WIDTH-1:0] op_b;
output reg [`REG_WIDTH-1:0] result;
output reg ovf = 0;
output reg cf = 0;
wire [`REG_WIDTH-1:0] op_b_inv;
wire [`REG_WIDTH+1:0] addsub_temp;
wire signed [`REG_WIDTH*2-1:0] mul_temp;
wire signed [`REG_WIDTH-1:0] div_temp;
assign op_b_inv = op_b ^ {`REG_WIDTH{arithm_opsel[0]}};
assign addsub_temp = {op_a, arithm_opsel[0]} + {op_b_inv, arithm_opsel[0]};
assign mul_temp = op_a * op_b;
assign div_temp = op_a / op_b;
always @* begin
casez (arithm_opsel)
`ALU_ADDSUB: begin
{cf, result} = addsub_temp[`REG_WIDTH+1:1];
ovf = (op_b_inv[`REG_WIDTH-1] ^ op_a[`REG_WIDTH-1]) ^ cf;
end
`ALU_MUL_L: begin
result = mul_temp[`REG_WIDTH-1:0];
cf = 0;
ovf = 0;
end
`ALU_MUL_H: begin
result = mul_temp[`REG_WIDTH*2-1:`REG_WIDTH];
cf = 0;
ovf = 0;
end
`ALU_DIV: begin
result = div_temp;
cf = 0;
ovf = 0;
end
`ALU_REM: begin
result = op_a % op_b;
cf = 0;
ovf = 0;
end
default: begin
result = 0;
cf = 0;
ovf = 0;
end
endcase
end
endmodule
| 7.295609 |
module vc_Adder #(
parameter p_nbits = 1
) (
input logic [p_nbits-1:0] in0,
input logic [p_nbits-1:0] in1,
input logic cin,
output logic [p_nbits-1:0] out,
output logic cout
);
// We need to convert cin into a 32-bit value to
// avoid verilator warnings
assign {cout, out} = in0 + in1 + {{(p_nbits - 1) {1'b0}}, cin};
endmodule
| 7.622412 |
module vc_SimpleAdder #(
parameter p_nbits = 1
) (
input logic [p_nbits-1:0] in0,
input logic [p_nbits-1:0] in1,
output logic [p_nbits-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.112602 |
module vc_Subtractor #(
parameter p_nbits = 1
) (
input logic [p_nbits-1:0] in0,
input logic [p_nbits-1:0] in1,
output logic [p_nbits-1:0] out
);
assign out = in0 - in1;
endmodule
| 7.776575 |
module vc_Incrementer #(
parameter p_nbits = 1,
parameter p_inc_value = 1
) (
input logic [p_nbits-1:0] in,
output logic [p_nbits-1:0] out
);
assign out = in + p_inc_value;
endmodule
| 8.657353 |
module vc_ZeroExtender #(
parameter p_in_nbits = 1,
parameter p_out_nbits = 8
) (
input logic [ p_in_nbits-1:0] in,
output logic [p_out_nbits-1:0] out
);
assign out = {{(p_out_nbits - p_in_nbits) {1'b0}}, in};
endmodule
| 8.062945 |
module vc_SignExtender #(
parameter p_in_nbits = 1,
parameter p_out_nbits = 8
) (
input logic [ p_in_nbits-1:0] in,
output logic [p_out_nbits-1:0] out
);
assign out = {{(p_out_nbits - p_in_nbits) {in[p_in_nbits-1]}}, in};
endmodule
| 8.543095 |
module vc_ZeroComparator #(
parameter p_nbits = 1
) (
input logic [p_nbits-1:0] in,
output logic out
);
assign out = (in == {p_nbits{1'b0}});
endmodule
| 8.972309 |
module vc_EqComparator #(
parameter p_nbits = 1
) (
input logic [p_nbits-1:0] in0,
input logic [p_nbits-1:0] in1,
output logic out
);
assign out = (in0 == in1);
endmodule
| 8.385225 |
module vc_LtComparator #(
parameter p_nbits = 1
) (
input logic [p_nbits-1:0] in0,
input logic [p_nbits-1:0] in1,
output logic out
);
assign out = (in0 < in1);
endmodule
| 8.571994 |
module vc_GtComparator #(
parameter p_nbits = 1
) (
input logic [p_nbits-1:0] in0,
input logic [p_nbits-1:0] in1,
output logic out
);
assign out = (in0 > in1);
endmodule
| 8.065152 |
module vc_LeftLogicalShifter #(
parameter p_nbits = 1,
parameter p_shamt_nbits = 1
) (
input logic [ p_nbits-1:0] in,
input logic [p_shamt_nbits-1:0] shamt,
output logic [ p_nbits-1:0] out
);
assign out = (in << shamt);
endmodule
| 8.380756 |
module vc_RightLogicalShifter #(
parameter p_nbits = 1,
parameter p_shamt_nbits = 1
) (
input logic [ p_nbits-1:0] in,
input logic [p_shamt_nbits-1:0] shamt,
output logic [ p_nbits-1:0] out
);
assign out = (in >> shamt);
endmodule
| 8.285177 |
module arithmeticlogicunit (
input [31:0] A,
B, //Inputs
input [ 3:0] OP, //Operation selector
output reg [31:0] OUT, //Result of the operation
output wire zero //Checks if the operation result is 0
);
assign zero = (OUT == 0); //If the result of the op is 0, the flag is set to 1
always @(A, B, OP) begin
case (OP)
0: OUT = A & B;
1: OUT = A | B;
2: OUT = A + B;
6: OUT = A - B;
7: OUT = A < B;
default: ;
endcase
end
endmodule
| 8.012123 |
module half_adder (
a,
b,
h,
l
);
input wire a, b;
output wire h, l;
and_gate u0 (
.a(a),
.b(b),
.and_s(h)
);
xor_gate u1 (
.a(a),
.b(b),
.xor_s(l)
);
endmodule
| 6.966406 |
module add_16 (
a,
b,
c,
s,
c_out
);
input wire [15:0] a, b;
input wire c;
output [15:0] s;
output c_out;
assign {c_out, s} = a + b + c;
endmodule
| 6.977906 |
module subt_16 (
a,
b,
out
);
input wire [15:0] a, b;
output [15:0] out;
assign out = a - b;
endmodule
| 7.466112 |
module switch (
s,
d,
c1,
c0
);
input wire s, d;
output c1, c0;
wire temp;
inv_gate u0 (
.a(s),
.inv_s(temp)
);
and_gate u1 (
.a(temp),
.b(d),
.and_s(c0)
);
and_gate u2 (
.a(s),
.b(d),
.and_s(c1)
);
endmodule
| 6.864438 |
module ArithmeticUnit (
A,
B,
B15to0,
AandB,
AorB,
notB,
shlB,
shrB,
AaddB,
AsubB,
AmulB,
AcmpB,
aluout,
cin,
zout,
cout
);
input [15:0] A, B;
input B15to0, AandB, AorB, notB, shlB, shrB, AaddB, AsubB, AmulB, AcmpB;
input cin;
output [15:0] aluout;
output zout, cout;
reg [15:0] aluout;
reg zout, cout;
always @(
A or B or B15to0 or AandB or AorB or notB or shlB or shrB or AaddB or AsubB or AmulB or AcmpB or cin
)
begin
zout = 0;
cout = 0;
aluout = 0;
case ({
B15to0, AandB, AorB, notB, shlB, shrB, AaddB, AsubB, AmulB, AcmpB
})
`B15to0H: aluout = B;
`AandBH: aluout = A & B;
`AorBH: aluout = A | B;
`notBH: aluout = ~B;
`shlBH: aluout = {B[15:0], B[0]};
`shrBH: aluout = {B[15], B[15:1]};
`AaddBH: {cout, aluout} = A + B + cin;
`AsubBH: {cout, aluout} = A - B - cin;
`AmulBH: aluout = A[7:0] * B[7:0];
`AcmpBH: begin
aluout = A;
if (A > B) cout = 1;
else cout = 0;
if (A == B) zout = 1;
else zout = 0;
end
default: aluout = 0;
endcase
if (aluout == 0) zout = 1'b1;
end
endmodule
| 6.524404 |
module ArithmeticUnit_Testbench #(
parameter WIDTH = 32
) (); // Ԫλ
// ʹõļĴ
reg OP = 1'b0; // 1λԪ룬0Ϊӷ1Ϊ
reg [WIDTH - 1 : 0] A; // (WIDTH)λ/A
reg [WIDTH - 1 : 0] B; // (WIDTH)λ/ B
wire [WIDTH - 1 : 0] Y; // (WIDTH)λY
wire SF; // 1λYλ
wire CF; // Ϊʱ1λY0δ1Ϊ
wire OF; // Ϊзʱ1λY0δ1Ϊ
ArithmeticUnit #(
.WIDTH(WIDTH)
) Unit (
.OP(OP),
.A (A),
.B (B),
.Y (Y),
.SF(SF),
.CF(CF),
.OF(OF)
);
// ÿ10nsһ, ֱԼӷͼ˹
always begin
A <= $random();
B <= $random();
#5 OP <= 1'b1;
#5 OP <= 1'b0;
end
// 趨ʱΪ10ms
initial begin
#10000000 $stop;
end
endmodule
| 6.524404 |
module HA (
(* dont_touch="true" *) input x,
(* dont_touch="true" *) input y,
(* dont_touch="true" *) output cout,
(* dont_touch="true" *) output s
);
assign cout = x & y;
assign s = x ^ y;
endmodule
| 7.380652 |
module FA (
(* dont_touch="true" *) input x,
(* dont_touch="true" *) input y,
(* dont_touch="true" *) input ci,
(* dont_touch="true" *) output cout,
(* dont_touch="true" *) output s
);
(* dont_touch="true" *)wire wr1;
(* dont_touch="true" *)wire wr2;
(* dont_touch="true" *)wire wr3;
HA ha0 (
x,
y,
wr1,
wr2
);
HA ha1 (
wr2,
ci,
wr3,
s
);
assign cout = wr1 | wr3;
endmodule
| 7.514487 |
module RCA (
(* dont_touch="true" *) input [3:0] x,
(* dont_touch="true" *) input [3:0] y,
(* dont_touch="true" *) input ci,
(* dont_touch="true" *) output cout,
(* dont_touch="true" *) output [3:0] s
);
(* dont_touch="true" *)wire wr4;
(* dont_touch="true" *)wire wr5;
(* dont_touch="true" *)wire wr6;
FA fa0 (
x[0],
y[0],
ci,
wr4,
s[0]
);
FA fa1 (
x[1],
y[1],
wr4,
wr5,
s[1]
);
FA fa2 (
x[2],
y[2],
wr5,
wr6,
s[2]
);
FA fa3 (
x[3],
y[3],
wr6,
cout,
s[3]
);
endmodule
| 7.975596 |
module parametric_RCA #(
parameter SIZE = 8
) (
(* dont_touch="true" *) input [SIZE-1:0] x,
(* dont_touch="true" *) input [SIZE-1:0] y,
(* dont_touch="true" *) input ci,
(* dont_touch="true" *) output cout,
(* dont_touch="true" *) output [SIZE-1:0] s
);
(* dont_touch="true" *) wire temp[SIZE:0];
assign temp[0] = ci;
genvar i;
generate
for (i = 0; i < SIZE; i = i + 1) begin
FA fa_param (
x[i],
y[i],
temp[i],
temp[i+1],
s[i]
);
end
endgenerate
assign cout = temp[SIZE];
endmodule
| 7.912871 |
module Arithmetic_logic (
A,
B,
Cin,
Omultiply,
OaddSub
);
input [1:0] A;
input [1:0] B;
input Cin;
output [3:0] Omultiply;
output [3:0] OaddSub;
multiplier multiplier1 (
A,
B,
Omultiply
);
Add_Sub Add_Sub1 (
A,
B,
Cin,
OaddSub
);
endmodule
| 7.420924 |
module arithmetic_logic_system (
input [15:0] A,
input [15:0] B,
input [15:0] Imm,
input ALUsrc,
input [2:0] ALUop,
input clk,
output AltB,
output [15:0] ALUout
);
wire [15:0] mux_out, alu_out;
wire a_ltb;
reg [15:0] ALUout_reg;
reg AltB_reg;
alu_16_bit alu (
.A(A),
.B(mux_out),
.op(ALUop),
.R(alu_out),
.AltB(a_ltb)
);
mux_1_bit alu_mux (
.A(Imm),
.B(B),
.S(ALUsrc),
.R(mux_out)
);
assign ALUout = ALUout_reg;
assign AltB = AltB_reg;
always @(posedge clk) begin
ALUout_reg = alu_out;
AltB_reg = a_ltb;
end
endmodule
| 6.612484 |
module inv16 (
a,
inv16_s
);
input wire [15:0] a;
output wire [15:0] inv16_s;
assign inv16_s = ~a;
endmodule
| 7.602931 |
module xor16 (
a,
b,
xor16_s
);
input wire [15:0] a, b;
output [15:0] xor16_s;
assign xor16_s = a ^ b;
endmodule
| 8.069681 |
module or16 (
a,
b,
or16_s
);
input [15:0] a, b;
output [15:0] or16_s;
assign or16_s = a | b;
endmodule
| 7.233483 |
module and16 (
a,
b,
and16_s
);
input [15:0] a, b;
output [15:0] and16_s;
assign and16_s = a & b;
endmodule
| 7.566975 |
module select16 (
s,
d1,
d0,
out
);
input s;
input [15:0] d1, d0;
output [15:0] out;
assign out = s ? d1 : d0;
endmodule
| 7.241005 |
module sub16 (
a,
b,
sub16_s
);
input [15:0] a, b;
output [15:0] sub16_s;
assign sub16_s = a - b;
endmodule
| 7.317719 |
module add16 (
a,
b,
add16_s
);
input [15:0] a, b;
output [15:0] add16_s;
assign add16_s = a + b;
endmodule
| 6.87555 |
module Logic_unit (
op1,
op0,
X,
Y,
out
);
input wire op0, op1;
input wire [15:0] X, Y;
output wire [15:0] out;
wire [15:0] tempi, tempxor, tempor, tempa, sel1, sel0;
inv16 u0 (
.a(X),
.inv16_s(tempi)
);
xor16 u1 (
.a(X),
.b(Y),
.xor16_s(tempxor)
);
or16 u2 (
.a(X),
.b(Y),
.or16_s(tempor)
);
and16 u3 (
.a(X),
.b(Y),
.and16_s(tempa)
);
select16 u4 (
.s (op0),
.d1 (tempor),
.d0 (tempa),
.out(sel0)
);
select16 u5 (
.s (op0),
.d1 (tempi),
.d0 (tempxor),
.out(sel1)
);
select16 u6 (
.s (op1),
.d1 (sel1),
.d0 (sel0),
.out(out)
);
endmodule
| 6.91066 |
module ALU (
u,
op0,
op1,
zx,
sw,
X,
Y,
out
);
input [15:0] X, Y;
input u, op0, op1, zx, sw;
output [15:0] out;
wire zero;
wire [15:0] sel0, sel1, sel2, sel3, au, lu;
assign zero = 1'b0;
arithmetic_unit u0 (
.op1(op1),
.op0(op0),
.X (sel2),
.Y (sel0),
.out(au)
);
logic_unit u1 (
.op1(op1),
.op0(op0),
.X (sel2),
.Y (sel0),
.out(lu)
);
select16 u2 (
.s (sw),
.d1 (X),
.d0 (Y),
.out(sel0)
);
select16 u3 (
.s (sw),
.d1 (Y),
.d0 (X),
.out(sel1)
);
select16 u4 (
.s (zx),
.d1 (zero),
.d0 (sel1),
.out(sel2)
);
select16 u5 (
.s (u),
.d1 (au),
.d0 (lu),
.out(out)
);
endmodule
| 6.707544 |
module Arithmetic_logic_unity #(
parameter DATA_WIDTH = 32,
parameter OP_WIDTH = 5
) (
input [(OP_WIDTH-1):0] op,
shamt,
input [(DATA_WIDTH-1):0] data_1,
data_2,
output reg [(DATA_WIDTH-1):0] result,
output zero
);
wire [(DATA_WIDTH-1):0] n_zero;
assign n_zero = (data_2 == 0) ? 1 : data_2;
always @(*) begin
case (op)
5'b00000: result = data_1 + data_2;
5'b00001: result = data_1 - data_2;
5'b00010: result = data_1 + 1;
5'b00011: result = data_1 - 1;
5'b00100: result = data_1 < data_2 ? 1 : 0; // set on less than
5'b00101: result = data_1[15:0] * data_2[15:0];
5'b00110: result = data_1 / n_zero;
5'b00111: result = data_1 << shamt;
5'b01000: result = data_1 >> shamt;
5'b01001: result = ~data_1;
5'b01010: result = data_1 & data_2;
5'b01011: result = data_1 | data_2;
5'b01100: result = data_1 ^ data_2;
5'b01101: result = data_1 <= data_2 ? 1 : 0; // set on less or equal than - slet
5'b01110: result = data_1 == data_2 ? 1 : 0; // set on equal - seq
5'b01111: result = data_1 != data_2 ? 1 : 0; // set on not equal - sneq
5'b10000: result = {data_1[15:0], data_2[15:0]}; // concatenation
default: result = 0;
endcase
end
assign zero = (result == 0);
endmodule
| 7.420924 |
module arithmetic_logic_unit_test;
reg [15:0] x;
reg [15:0] y;
reg nx, ny, zx, zy, f, no;
wire [15:0] out;
wire zr, ng;
arithmetic_logic_unit alu (
.x (x),
.y (y),
.zx (zx),
.nx (nx),
.zy (zy),
.ny (ny),
.f (f),
.no (no),
.out(out),
.zr (zr),
.ng (ng)
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
$display("Identity on x...");
x = 16'h0abc;
y = 16'h0444;
zx = 0;
nx = 0;
zy = 1;
ny = 0;
f = 1;
no = 0;
display;
$display("Identity on y...");
x = 16'h0abc;
y = 16'h0444;
zx = 1;
nx = 0;
zy = 0;
ny = 0;
f = 1;
no = 0;
display;
$display("Negative of x... (should output ffff)");
x = 16'h0001;
y = 16'h0444;
zx = 0;
nx = 0;
zy = 1;
ny = 1;
f = 1;
no = 1;
display;
$display("Negative of y... (should output ffe0)");
x = 16'h0001;
y = 16'h0020;
zx = 1;
nx = 1;
zy = 0;
ny = 0;
f = 1;
no = 1;
display;
$display("x - y... (should output ffe1)");
x = 16'h0001;
y = 16'h0020;
zx = 0;
nx = 1;
zy = 0;
ny = 0;
f = 1;
no = 1;
display;
$display("x + y... (should output 0021)");
x = 16'h0001;
y = 16'h0020;
zx = 0;
nx = 0;
zy = 0;
ny = 0;
f = 1;
no = 0;
display;
$display("x & y... (should output 0020)");
x = 16'h0031;
y = 16'h0020;
zx = 0;
nx = 0;
zy = 0;
ny = 0;
f = 0;
no = 0;
display;
$display("x | y... (should output 0031)");
x = 16'h0031;
y = 16'h0020;
zx = 0;
nx = 1;
zy = 0;
ny = 1;
f = 0;
no = 1;
display;
end
task display;
#1
$display(
"x: %4h\ty:%4h\nzx: %1b, nx: %1b, zy: %1b, ny: %1b, f: %1b\nout: %4h\tzr: %1b\tng: %1b\n",
x,
y,
zx,
nx,
zy,
ny,
f,
out,
zr,
ng
);
endtask
endmodule
| 6.612484 |
module shift_left(enable, in, out);
// module that shifts the input left when the enable input is 1
parameter n = 8;
input enable;
input [n:0] in;
output [n:0] out;
integer i;
always @(shift)
begin
for (i = 0; i < n; i = i+1)
begin
out[i+1] <= in[i]
end
end
endmodule
| 7.68256 |
module divider_restore ();
endmodule
| 7.308109 |
module divider_nonrestore (
quotient,
remainder,
numerator,
denominator
);
parameter n = 8;
input [n:0] numerator;
input [n+1:0] denominator;
output [n+1:0] remainder;
output [n:0] quotient;
always @(remainder) begin
if (remainder < 0) begin
remainder = remainder + denominator;
end else begin
//shift rem||a
remainder = remainder - denominator;
end
end
endmodule
| 7.831156 |
module arithmetic_operators ();
initial begin
$display(" 5 + 10 = %d", 5 + 10);
$display(" 5 - 10 = %d", 5 - 10);
$display(" 10 - 5 = %d", 10 - 5);
$display(" 10 * 5 = %d", 10 * 5);
$display(" 10 / 5 = %d", 10 / 5);
$display(" 10 / -5 = %d", 10 / -5);
$display(" 10 %s 3 = %d", "%", 10 % 3);
$display(" +5 = %d", +5);
$display(" -5 = %d", -5);
#10 $finish;
end
endmodule
| 7.467791 |
module arithmetic_operators_tb ();
// 1) Declare local reg and wire identifiers
parameter n = 4;
reg [n - 1:0] x, y;
wire [n - 1:0] s;
wire cout, overflow;
// 2) Instantiate the unit under test
arithmetic_operators uut0 (
.x(x),
.y(y),
.s(s),
.cout(cout),
.overflow(overflow)
);
// 3) Specify a stopwatch to stop the simulation
initial #40 $finish;
// 4) Generate stimuli, using initial and always
initial begin
x = 4'd6;
y = 4'd3;
#10 x = -4'd6;
y = 4'd3;
#10 x = 4'd6;
y = -4'd3;
#10 x = -4'd6;
y = -4'd3;
#10;
end
// 5) Display the output response (text or graphics (or both))
endmodule
| 7.467791 |
module arithmetic_shift (
output reg [3:0] out,
input [3:0] in,
input direction
);
always @* begin
if (direction == 1) out = {in[2:0], 1'b0};
else out = {in[3], in[3:1]};
end
endmodule
| 7.423881 |
module arithmetic_shifter (
dataIn,
amount,
dir,
dataOut
);
function integer log2;
input integer value;
begin
value = value - 1;
for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1;
end
endfunction
parameter data_width_in = 8;
parameter shiftAmount = 16;
localparam shiftBits = log2(shiftAmount);
parameter data_width_out = shiftAmount + data_width_in;
input dir;
input signed [data_width_in-1:0] dataIn;
input [shiftBits-1:0] amount;
output signed [data_width_out-1:0] dataOut;
assign dataOut = (dir) ? (dataIn <<< amount) : (dataIn >>> amount); //1 - left shift 0 - right shift
endmodule
| 7.423881 |
module Arithmetic_unit #(
parameter A_WIDTH = 8,
B_WIDTH = 8,
OUT_WIDTH = 16,
ALU_FUN_WIDTH = 2
) (
input wire [ A_WIDTH-1:0] A,
input wire [ B_WIDTH-1:0] B,
input wire [ALU_FUN_WIDTH-1:0] ALU_FUN,
input wire Arith_Enable,
input wire CLK,
input wire RST,
output reg [OUT_WIDTH-1:0] Arith_OUT,
output reg OUT_VALID
);
reg [OUT_WIDTH-1:0] Arith_Result;
reg VALID;
/********************************************************************************************/
/********************************************************************************************/
always @(posedge CLK or negedge RST) begin
if (!RST) begin
Arith_OUT <= 'b0;
OUT_VALID <= 'b0;
end else begin
Arith_OUT <= Arith_Result;
OUT_VALID <= VALID;
end
end
/********************************************************************************************/
/********************************************************************************************/
always @(*) begin
VALID = 1'b0;
if (Arith_Enable) begin
case (ALU_FUN)
'b00: Arith_Result = A + B;
'b01: Arith_Result = A - B;
'b10: Arith_Result = A * B;
'b11: Arith_Result = A / B;
default: Arith_Result = 'b0;
endcase
VALID = 'b1;
end else begin
Arith_Result = 'b0;
VALID = 'b0;
end
end
endmodule
| 7.292905 |
module arithmod (
Out,
V,
N,
Z,
A,
B,
Sel,
Mem
);
input [15:0] A, B;
input [1:0] Sel;
input Mem;
output [15:0] Out;
output V, N, Z;
wire cout;
wire [15:0] adder_out, paddsb_out, adder_result, B_nor, sel_nor;
wire sign;
always @(Out) begin
//$display("adder_result=%b, Z=%b, adder_out=%b, Sel=%b", adder_result, Z, adder_out, Sel);
end
split16 splitSel (
sel_nor,
Sel[1]
);
assign B_nor = (sel_nor ^ B);
paddsb ps (
paddsb_out,
A,
B
);
add16bit Adder (
cout,
adder_out,
A,
B_nor,
Sel[1]
);
overflow check (
V,
sign,
A[15],
B[15],
adder_out[15],
Sel[1]
);
assign adder_result = (V) ? ((sign) ? 16'h8000 : 16'h7FFF) : adder_out;
assign Out = (Mem || !Sel[0]) ? adder_result : paddsb_out;
assign N = (adder_result[15]);
assign Z = (adder_result == 16'h0000 && (Sel[0] == 1'b0));
endmodule
| 6.744183 |
module arithShiftRight (
output reg [31:0] out,
input [31:0] inA,
inB
);
wire [31:0] rightOut0, leftOut, rightOut1;
always @(inA or inB) begin
out = (inA >> inB) | (((inA >> 31) << (inB + 1)) - 1) ^ 32'hffffffff;
end
endmodule
| 6.575718 |
module shiftRightTest;
reg [31:0] TinA, TinB;
wire [31:0] Tout;
initial begin
$dumpfile("shiftRightTest.vcd");
$dumpvars(0, shiftRightTest);
$monitorh($time,, Tout,, TinA,, TinB);
TinA = 32'hf0;
TinB = 32'd2;
#1000;
TinA = 32'hfffffff0;
#1000;
TinB = 32'd4;
#1000;
end
arithShiftRight arithShiftRightTester (
Tout,
TinA,
TinB
);
endmodule
| 6.804859 |
module describes a Arithmatic unit of ALU. /////
/// This will have two inputs of 16 bits each. /////
/// It has to provide either Arithmatic operation ////
////////////////////////////////////////////////////////////////////////////
module arith(a,b,opcode,outau);
input [15:0] a;
input [15:0] b;
input [2:0] opcode;
output [31:0] outau;
reg [31:0] outau;
always@(a,b,opcode)
begin
case(opcode)
3'b000: outau = {16'h0000, a+b};
3'b001: outau = a * b;
3'b010: if (a > b) begin
outau = a - b;
end
else begin
outau = b - a;
end
3'b011: if (a > b) begin
outau = a / b;
end
else begin
outau = b /a;
end
default outau = 32'h00000000;
endcase
end
endmodule
| 7.463649 |
module \$alu (
A,
B,
CI,
BI,
X,
Y,
CO
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
parameter _TECHMAP_CONSTMSK_CI_ = 0;
parameter _TECHMAP_CONSTVAL_CI_ = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y, CO;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(
.A_SIGNED(A_SIGNED),
.A_WIDTH (A_WIDTH),
.Y_WIDTH (Y_WIDTH)
) A_conv (
.A(A),
.Y(A_buf)
);
\$pos #(
.A_SIGNED(B_SIGNED),
.A_WIDTH (B_WIDTH),
.Y_WIDTH (Y_WIDTH)
) B_conv (
.A(B),
.Y(B_buf)
);
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BX = B_buf;
wire [ Y_WIDTH:0] ALM_CARRY;
// Start of carry chain
generate
if (_TECHMAP_CONSTMSK_CI_ == 1) begin
assign ALM_CARRY[0] = _TECHMAP_CONSTVAL_CI_;
end else begin
MISTRAL_ALUT_ARITH #(
.LUT0(16'b1010_1010_1010_1010), // Q = A
.LUT1(16'b0000_0000_0000_0000), // Q = 0 (LUT1's input to the adder is inverted)
) alm_start (
.A (CI),
.B (1'b1),
.C (1'b1),
.D0(1'b1),
.D1(1'b1),
.CI(1'b0),
.CO(ALM_CARRY[0])
);
end
endgenerate
// Carry chain
genvar i;
generate
for (i = 0; i < Y_WIDTH; i = i + 1) begin : slice
// TODO: mwk suggests that a pass could merge pre-adder logic into this.
MISTRAL_ALUT_ARITH #(
.LUT0(16'b1010_1010_1010_1010), // Q = A
.LUT1(16'b1100_0011_1100_0011), // Q = C ? B : ~B (LUT1's input to the adder is inverted)
) alm_i (
.A (AA[i]),
.B (BX[i]),
.C (BI),
.D0(1'b1),
.D1(1'b1),
.CI(ALM_CARRY[i]),
.SO(Y[i]),
.CO(ALM_CARRY[i+1])
);
// ALM carry chain is not directly accessible, so calculate the carry through soft logic if really needed.
assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));
end
endgenerate
assign X = AA ^ BB;
endmodule
| 8.218654 |
module _80_quicklogic_alu (
A,
B,
CI,
BI,
X,
Y,
CO
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 2;
parameter B_WIDTH = 2;
parameter Y_WIDTH = 2;
parameter _TECHMAP_CONSTVAL_CI_ = 0;
parameter _TECHMAP_CONSTMSK_CI_ = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(
.A_SIGNED(A_SIGNED),
.A_WIDTH (A_WIDTH),
.Y_WIDTH (Y_WIDTH)
) A_conv (
.A(A),
.Y(A_buf)
);
\$pos #(
.A_SIGNED(B_SIGNED),
.A_WIDTH (B_WIDTH),
.Y_WIDTH (Y_WIDTH)
) B_conv (
.A(B),
.Y(B_buf)
);
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
genvar i;
wire co;
(* force_downto *)
//wire [Y_WIDTH-1:0] C = {CO, CI};
wire [Y_WIDTH:0] C;
(* force_downto *)
wire [Y_WIDTH-1:0] S = {AA ^ BB};
assign CO[Y_WIDTH-1:0] = C[Y_WIDTH:1];
//assign CO[Y_WIDTH-1] = co;
generate
adder_carry intermediate_adder (
.cin (),
.cout (C[0]),
.p (1'b0),
.g (CI),
.sumout()
);
endgenerate
genvar i;
generate
if (Y_WIDTH > 2) begin
for (i = 0; i < Y_WIDTH - 2; i = i + 1) begin : slice
adder_carry my_adder (
.cin(C[i]),
.g(AA[i]),
.p(S[i]),
.cout(C[i+1]),
.sumout(Y[i])
);
end
end
endgenerate
generate
adder_carry final_adder (
.cin (C[Y_WIDTH-2]),
.cout (),
.p (1'b0),
.g (1'b0),
.sumout(co)
);
endgenerate
assign Y[Y_WIDTH-2] = S[Y_WIDTH-2] ^ co;
assign C[Y_WIDTH-1] = S[Y_WIDTH-2] ? co : AA[Y_WIDTH-2];
assign Y[Y_WIDTH-1] = S[Y_WIDTH-1] ^ C[Y_WIDTH-1];
assign C[Y_WIDTH] = S[Y_WIDTH-1] ? C[Y_WIDTH-1] : AA[Y_WIDTH-1];
assign X = S;
endmodule
| 7.806042 |
module Arith_SR_16bit (
F,
A
);
input signed [15:0] A;
output reg signed [15:0] F;
always @(A) begin
F = A >>> 1;
end
endmodule
| 7.020633 |
module: arith
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module arith_tb;
// Inputs
reg [7:0] a;
reg [7:0] b;
// Outputs
wire [7:0] out;
// Instantiate the Unit Under Test (UUT)
arith uut (
.a(a),
.b(b),
.out(out)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
// Wait 100 ns for global reset to finish
#10;
// Add stimulus here
$display ("%d\n", out);
end
endmodule
| 6.625688 |
module arith_unit (
i_mode,
i_op,
i_A,
i_B,
i_C,
i_D,
o_out1,
o_out2
);
input i_mode; // 1'b0 - simple arithmetics, 1'b1 - complex arithmetics.
input [2:0] i_op; // 7 possible operations.
input [15:0] i_A, i_B, i_C, i_D; // input data.
output reg [15:0] o_out1, o_out2; // output result data - o_out1 is X, o_out2 is Y: [Z = X + iY = Re + i*Im = o_out1 + i*o_out2]
/*
** i_op - possible operations:
** 000 "+" Add
** 001 "-" Subtract
** 010 "<<" Shift Left Logical
** 011 ">>" Shift Right Logical
** 100 ">>>" Shift Right Arithmetic
** 101 "<--" Shift Cyclic Left
** 110 "-->" Shift Cyclic Right
*/
// Complex arithmetic
wire [15:0] Re_Z1, Im_Z1, Re_Z2, Im_Z2;
assign Re_Z1 = i_A; // Real part of [Z1 = Re + i*Im]
assign Im_Z1 = i_B; // Imaginary part of [Z1 = Re + i*Im]
assign Re_Z2 = i_C;
assign Im_Z2 = i_D;
parameter [2:0] ADD = 3'd0, SUB = 3'd1, SLL = 3'd2, SRL = 3'd3, SRA = 3'd4, SCL = 3'd5, SCR = 3'd6;
// Shifter implementation
wire [31:0] sll_A, sll_C, srl_A, srl_C;
assign sll_A = {i_A, i_A} << i_B[3:0]; // i_A << i_B[3:0], first 4 digits (LSB) of input data i_B - are the "Shift amount" value
assign sll_C = {i_C, i_C} << i_D[3:0];
assign srl_A = {i_A, i_A} >> i_B[3:0];
assign srl_C = {i_C, i_C} >> i_D[3:0];
always @(*) begin
case (i_op)
ADD: begin
// Z1 + Z2 = (X1 + i*Y1) + (X2 + i*Y2) = (X1 + X2) + i*(Y1 + Y2) = o_out1 + i*o_out2
o_out1 = (i_mode) ? (Re_Z1 + Re_Z2) : (i_A + i_B); // [Re] or [A+B]
o_out2 = (i_mode) ? (Im_Z1 + Im_Z2) : (i_C + i_D); // [Im] or [C+D]
end
SUB: begin
// Z1 - Z2 = (X1 + i*Y1) - (X2 + i*Y2) = (X1 - X2) + i*(Y1 - Y2) = o_out1 + i*o_out2
o_out1 = (i_mode) ? (Re_Z1 - Re_Z2) : (i_A - i_B); // [Re] or [A-B]
o_out2 = (i_mode) ? (Im_Z1 - Im_Z2) : (i_C - i_D); // [Im] or [C-D]
end
SLL: begin
o_out1 = sll_A[15:0]; // Shift left logical
o_out2 = sll_C[15:0];
end
SRL: begin
o_out1 = srl_A[31:16]; // Shift right logical
o_out2 = srl_C[31:16];
end
SRA: begin
o_out1 = $signed(i_A) >>> i_B[3:0]; // Arithmetic right
o_out2 = $signed(i_C) >>> i_D[3:0];
end
SCL: begin
o_out1 = sll_A[31:16]; // Cyclic left
o_out2 = sll_C[31:16];
end
SCR: begin
o_out1 = srl_A[15:0]; // Cyclic right
o_out1 = srl_C[15:0];
end
default: // Maybe, MUL or DIV - but we have the multiplexer in alu.v.
begin
o_out1 = {16{1'b0}};
o_out2 = {16{1'b0}};
end
endcase
end
/*
function [15:0] SLL;
input [15:0] data;
input [3:0] shift_amount;
reg [31:0] l_shifted;
begin
l_shifted = {data, data} << shift_amount;
SLL = l_shifted[15:0];
end
endfunction
*/
endmodule
| 7.021101 |
module aritmeticos ();
initial $display("Circuitos aritméticos");
endmodule
| 7.02379 |
module arit_ckt #(
parameter SIZE = 16
) (
input [SIZE-1:0] SRC,
DST,
input BW,
input [ 1:0] S,
input Cin,
output [SIZE-1:0] ARIT_OUT,
output Cout_arit,
V
);
wire [SIZE-1:0] DST_BAR;
assign DST_BAR = ~DST;
// Outputs from first level of logic
wire [SIZE-1:0] Y;
wire [SIZE-1:0] ARIT_OUT_TMP;
// Ripple carry bits
wire [SIZE-1:0] Cout_arit_full;
// First level of logic
wire [SIZE-1:0] S0;
wire [SIZE-1:0] S1;
// Make a data bus of same width as input so the bitwise operation
// works and doesn't need to be assigned to each individual bit
assign S1 = {SIZE{S[1]}};
assign S0 = {SIZE{S[0]}};
assign Y = (DST & S0) | (DST_BAR & S1);
// Do all the ripple carries in one shot
assign {Cout_arit_full, ARIT_OUT} = SRC + Y + Cin;
// LSB of carry out bus is the final carry out
assign Cout_arit = Cout_arit_full[0];
// If we're ADDING, and both inputs have the same sign and output has opposite sign, OVERFLOW.
// If we're SUBTRACTING, and the inputs sign bit do NOT match, and output sign matches B sign, OVERFLOW.
assign V = ((!S[1]) & ~(SRC[SIZE-1] ^ DST[SIZE-1]) & (SRC[SIZE-1] ^ ARIT_OUT[SIZE-1])) ? 1 :
((S[1]) & (SRC[SIZE-1] ^ DST[SIZE-1]) & ~(DST[SIZE-1] ^ ARIT_OUT[SIZE-1])) ? 1 : 0;
endmodule
| 8.630208 |
module ari_shifter_right (
in,
out,
shiftAmount
);
parameter data_WIDTH = 32;
parameter shift_WIDTH = 5;
input [data_WIDTH-1:0] in;
input [shift_WIDTH-1:0] shiftAmount;
output [data_WIDTH-1:0] out;
assign out = in >>> shiftAmount;
endmodule
| 8.378395 |
module Arkanoid (
input iCLK_50,
input btn_W,
btn_E,
btn_N,
btn_S,
input [3:0] iSW,
input iROT_A,
iROT_B,
output oVGA_R,
oVGA_G,
oVGA_B,
oHS,
oVS,
output [7:0] oLED
);
localparam BALL_NUM = 2;
localparam SHOT_NUM = 2;
reg clk_25;
wire middle, b_dis;
wire [4:0] p_speed;
wire [9:0] p_x, p_y, g_x, g_y;
wire reset, start, btn_r, btn_l;
wire rotary_event, rotary_right;
wire [5:0] b_radius, p_radius;
wire [1:0] b_active;
wire [2:0] g_kind;
wire g_active;
wire [BALL_NUM*10-1:0] b_x, b_y;
wire [10:0] vcounter; // 0~479
wire [11:0] hcounter; // 0~639
wire [3:0] out_back, out_paddle, out_block, out_ball, out_bmem, bm_block, out_gift;
wire [4:0] out_row, out_col, bm_row, bm_col;
wire [1:0] bm_stage, bm_func;
wire bm_ready, bm_enable;
wire st_init, st_dead;
// generate a 25Mhz clock
always @(posedge iCLK_50) clk_25 = ~clk_25;
// Buttons
syn_edge_detect sed1 (
iCLK_50,
reset,
btn_E,
btn_r
);
syn_edge_detect sed2 (
iCLK_50,
reset,
btn_W,
btn_l
);
syn_edge_detect sed3 (
iCLK_50,
reset,
btn_S,
start
);
// Rotation detection
Rotation_direction r_dir (
.CLK(iCLK_50),
.ROT_A(iROT_A),
.ROT_B(iROT_B),
.rotary_event(rotary_event),
.rotary_right(rotary_right)
);
// Game control
// Paddle control
paddle_control pd_control (
.clock(iCLK_50),
.reset(reset),
.enable(1'b1),
.rotary_event(rotary_event),
.rotary_right(rotary_right),
.speed(p_speed),
.radius(p_radius),
.middle(middle),
.paddle_x(p_x),
.paddle_y(p_y)
);
state_control s_control (
.clock(iCLK_50),
.reset(reset),
.start(start),
.btn_l(btn_l),
.btn_r(btn_r),
.iSW(iSW),
.bm_ready(bm_ready),
.bm_block(bm_block),
.p_x(p_x),
.p_y(p_y),
.p_radius(p_radius),
.b_active(b_active),
.b_radius(b_radius),
.o_bx(b_x),
.o_by(b_y),
.bm_enable(bm_enable),
.bm_row(bm_row),
.bm_col(bm_col),
.bm_func(bm_func),
.bm_stage(bm_stage),
.g_x(g_x),
.g_y(g_y),
.g_kind(g_kind),
.g_active(g_active),
.middle(middle),
.p_speed(p_speed),
.b_dis(b_dis),
.hp(oLED[7:2]),
.dead(st_dead),
.init(st_init),
.win(st_win)
);
block_memory b_mem (
.clock (iCLK_50),
.reset (reset),
.enable(bm_enable),
.row1 (bm_row),
.row2 (out_row),
.col1 (bm_col),
.col2 (out_col),
.func (bm_func),
.stage (bm_stage),
.block1(bm_block),
.block2(out_bmem),
.ready (bm_ready)
);
// Game display
draw_game d_game (
.clock(clk_25),
.reset(reset),
.visible(visible),
.dead(st_dead),
.init(st_init),
.win(st_win),
.in_ball(out_ball),
.in_gift(out_gift),
.in_block(out_block),
.in_paddle(out_paddle),
.in_back(out_back),
.oRGB({oVGA_R, oVGA_G, oVGA_B})
);
draw_back d_back (
.out(out_back),
.vcounter(vcounter),
.hcounter(hcounter),
.dead(st_dead),
.init(st_init),
.win(st_win)
);
draw_block d_block (
.clock(clk_25),
.vcounter(vcounter),
.hcounter(hcounter),
.block(out_bmem),
.sel_row(out_row),
.sel_col(out_col),
.out(out_block)
);
draw_ball d_ball (
.out(out_ball),
.vcounter(vcounter),
.hcounter(hcounter),
.visible(b_dis),
.xs(b_x),
.ys(b_y),
.active(b_active),
.radius(b_radius)
);
draw_ball d_shot (
.out(out_shot),
.vcounter(vcounter),
.hcounter(hcounter),
.xs(s_x),
.ys(s_y),
.active(s_active),
.radius(4)
);
draw_paddle d_paddle (
.vcounter(vcounter),
.hcounter(hcounter),
.x(p_x),
.y(p_y),
.radius(p_radius),
.out(out_paddle)
);
draw_gift d_gift (
.vcounter(vcounter),
.hcounter(hcounter),
.x(g_x),
.y(g_y),
.kind(g_kind),
.active(g_active),
.out(out_gift)
);
VGA_control vga_c (
.CLK(clk_25),
.reset(reset),
.vcounter(vcounter),
.hcounter(hcounter),
.visible(visible),
.oHS(oHS),
.oVS(oVS)
);
assign reset = btn_N;
assign oLED[1:0] = st_win ? 2'b11 : (st_dead ? 2'b01 : 2'b00);
endmodule
| 6.742823 |
module ARKLED (
ROW,
COL_RED,
COL_GREEN,
CLK
);
output wire [7:0] ROW, COL_RED, COL_GREEN;
input CLK;
//Counter 用于计数，实现模8计数功能
wire [2:0] Counter;
/*
initial begin
SetLEDState m1(CLK);
end
*/
Mod8Counter m2 (
Counter,
CLK
);
ARKPrinter m3 (
ROW,
COL_RED,
COL_GREEN,
Counter
);
endmodule
| 6.660117 |
module ARKLEDWithSwitchAndKeys (
ROW,
COL_RED,
COL_GREEN,
CLK,
Switch,
Key
);
output wire [7:0] ROW, COL_RED, COL_GREEN;
input CLK;
//开关用于切换低中高音和自动演奏
input [3:0] Switch;
//按键用于发声控制
input [6:0] Key;
//消抖后信号输出
wire [7:0] KeyState;
//Counter 用于计数，实现模8计数功能
wire [2:0] Counter;
Debounce m1 (
CLK,
Key,
KeyState
);
Mod8Counter m2 (
Counter,
CLK
);
ARKPrinter m3 (
ROW,
COL_RED,
COL_GREEN,
Counter,
Switch,
KeyState
);
endmodule
| 7.223807 |
module arlet_6502 (
input clk, // clock signal
input enable, // clock enable strobe
input rst_n, // active high reset signal
output reg [15:0] ab, // address bus
input [ 7:0] dbi, // 8-bit data bus (input)
output reg [ 7:0] dbo, // 8-bit data bus (output)
output reg we, // active high write enable strobe
input irq_n, // active low interrupt request
input nmi_n, // active low non-maskable interrupt
input ready, // CPU updates when ready = 1
output [15:0] pc_monitor // program counter monitor signal for debugging
);
wire [7:0] dbo_c;
wire [15:0] ab_c;
wire we_c;
wire rst = ~rst_n;
wire nmi = ~nmi_n;
wire irq = ~irq_n;
cpu arlet_cpu (
.clk(clk),
.reset(rst),
.AB(ab_c),
.DI(dbi),
.DO(dbo_c),
.WE(we_c),
.IRQ(irq),
.NMI(nmi),
.RDY(ready),
.PC_MONITOR(pc_monitor)
);
always @(posedge clk or posedge rst) begin
if (rst) begin
ab <= 16'd0;
dbo <= 8'd0;
we <= 1'b1;
end else if (enable) begin
ab <= ab_c;
dbo <= dbo_c;
we <= ~we_c;
end
end
endmodule
| 7.039329 |
module ALU (
clk,
op,
right,
AI,
BI,
CI,
CO,
BCD,
OUT,
V,
Z,
N,
HC,
RDY
);
input clk;
input right;
input [3:0] op; // operation
input [7:0] AI;
input [7:0] BI;
input CI;
input BCD; // BCD style carry
output [7:0] OUT;
output CO;
output V;
output Z;
output N;
output HC;
input RDY;
reg [7:0] OUT;
reg CO;
wire V;
wire Z;
reg N;
reg HC;
reg AI7;
reg BI7;
reg [8:0] temp_logic;
reg [7:0] temp_BI;
reg [4:0] temp_l;
reg [4:0] temp_h;
wire [8:0] temp = {temp_h, temp_l[3:0]};
wire adder_CI = (right | (op[3:2] == 2'b11)) ? 0 : CI;
// calculate the logic operations. The 'case' can be done in 1 LUT per
// bit. The 'right' shift is a simple mux that can be implemented by
// F5MUX.
always @* begin
case (op[1:0])
2'b00: temp_logic = AI | BI;
2'b01: temp_logic = AI & BI;
2'b10: temp_logic = AI ^ BI;
2'b11: temp_logic = AI;
endcase
if (right) temp_logic = {AI[0], CI, AI[7:1]};
end
// Add logic result to BI input. This only makes sense when logic = AI.
// This stage can be done in 1 LUT per bit, using carry chain logic.
always @* begin
case (op[3:2])
2'b00: temp_BI = BI; // A+B
2'b01: temp_BI = ~BI; // A-B
2'b10: temp_BI = temp_logic; // A+A
2'b11: temp_BI = 0; // A+0
endcase
end
// HC9 is the half carry bit when doing BCD add
wire HC9 = BCD & (temp_l[3:1] >= 3'd5);
// CO9 is the carry-out bit when doing BCD add
wire CO9 = BCD & (temp_h[3:1] >= 3'd5);
// combined half carry bit
wire temp_HC = temp_l[4] | HC9;
// perform the addition as 2 separate nibble, so we get
// access to the half carry flag
always @* begin
temp_l = temp_logic[3:0] + temp_BI[3:0] + adder_CI;
temp_h = temp_logic[8:4] + temp_BI[7:4] + temp_HC;
end
// calculate the flags
always @(posedge clk)
if (RDY) begin
AI7 <= AI[7];
BI7 <= temp_BI[7];
OUT <= temp[7:0];
CO <= temp[8] | CO9;
N <= temp[7];
HC <= temp_HC;
end
assign V = AI7 ^ BI7 ^ CO ^ N;
assign Z = ~|OUT;
endmodule
| 6.737201 |
module armleocpu_alu (
input is_op,
input is_op_imm,
input [4:0] shamt,
input [6:0] funct7,
input [2:0] funct3,
input [31:0] rs1,
input [31:0] rs2,
input [31:0] simm12,
output reg [31:0] result,
output reg illegal_instruction
);
wire is_addi = is_op_imm && (funct3 == 3'b000);
wire is_slti = is_op_imm && (funct3 == 3'b010);
wire is_sltiu = is_op_imm && (funct3 == 3'b011);
wire is_xori = is_op_imm && (funct3 == 3'b100);
wire is_ori = is_op_imm && (funct3 == 3'b110);
wire is_andi = is_op_imm && (funct3 == 3'b111);
wire is_slli = is_op_imm && (funct3 == 3'b001) && (funct7 == 7'b0000_000);
wire is_srli = is_op_imm && (funct3 == 3'b101) && (funct7 == 7'b0000_000);
wire is_srai = is_op_imm && (funct3 == 3'b101) && (funct7 == 7'b0100_000);
wire is_add = is_op && (funct3 == 3'b000) && (funct7 == 7'b0000_000);
wire is_sub = is_op && (funct3 == 3'b000) && (funct7 == 7'b0100_000);
wire is_slt = is_op && (funct3 == 3'b010) && (funct7 == 7'b0000_000);
wire is_sltu = is_op && (funct3 == 3'b011) && (funct7 == 7'b0000_000);
wire is_xor = is_op && (funct3 == 3'b100) && (funct7 == 7'b0000_000);
wire is_or = is_op && (funct3 == 3'b110) && (funct7 == 7'b0000_000);
wire is_and = is_op && (funct3 == 3'b111) && (funct7 == 7'b0000_000);
wire is_sll = is_op && (funct3 == 3'b001) && (funct7 == 7'b0000_000);
wire is_srl = is_op && (funct3 == 3'b101) && (funct7 == 7'b0000_000);
wire is_sra = is_op && (funct3 == 3'b101) && (funct7 == 7'b0100_000);
wire [31:0] internal_op2 = is_op ? rs2 : simm12;
/* verilator lint_off WIDTH */
wire [ 4:0] internal_shamt = is_op_imm ? shamt : rs2[4:0];
/* verilator lint_on WIDTH */
always @* begin
illegal_instruction = 0;
case (1)
is_addi, is_add: result = rs1 + internal_op2;
is_sub: result = rs1 - rs2;
/* verilator lint_off WIDTH */
is_slt, is_slti: result = ($signed(rs1) < $signed(internal_op2));
is_sltu, is_sltiu: result = ($unsigned(rs1) < $unsigned(internal_op2));
/* verilator lint_on WIDTH */
is_sll, is_slli: result = rs1 << internal_shamt;
/* verilator lint_off WIDTH */
is_sra, is_srai: result = {{32{rs1[31]}}, rs1} >> internal_shamt;
/* verilator lint_on WIDTH */
is_srl, is_srli: result = rs1 >> internal_shamt;
is_xor, is_xori: result = rs1 ^ internal_op2;
is_or, is_ori: result = rs1 | internal_op2;
is_and, is_andi: result = rs1 & internal_op2;
default: begin
illegal_instruction = 1;
result = rs1 + internal_op2;
end
endcase
end
endmodule
| 8.424951 |
module armleocpu_brcond(
output reg branch_taken,
output reg incorrect_instruction,
input [2:0] funct3,
input [31:0] rs1,
input [31:0] rs2
);
always @* begin
incorrect_instruction = 0;
case(funct3)
3'b000: //beq
branch_taken = rs1 == rs2;
3'b001: //bne
branch_taken = rs1 != rs2;
3'b100: //blt
branch_taken = $signed(rs1) < $signed(rs2);
3'b101: //bge
branch_taken = $signed(rs1) >= $signed(rs2);
3'b110: // bltu
branch_taken = $unsigned(rs1) < $unsigned(rs2);
3'b111: //bgeu
branch_taken = $unsigned(rs1) >= $unsigned(rs2);
default: begin
branch_taken = 0;
incorrect_instruction = 1;
end
endcase
end
endmodule
| 6.968745 |
module armleocpu_loadgen (
input [1:0] inwordOffset,
input [2:0] loadType,
input [31:0] LoadGenDataIn,
output reg [31:0] LoadGenDataOut,
output reg LoadMissaligned,
output reg LoadUnknownType
);
wire [ 4:0] roffset = {inwordOffset, 3'b000};
wire [31:0] rshift = LoadGenDataIn >> roffset;
always @* begin
case (loadType)
// Word
`LOAD_WORD: LoadGenDataOut = rshift;
`LOAD_HALF_UNSIGNED: LoadGenDataOut = {16'h0, rshift[15:0]};
`LOAD_HALF: LoadGenDataOut = {{16{rshift[15]}}, $signed(rshift[15:0])};
`LOAD_BYTE_UNSIGNED: LoadGenDataOut = {{24{1'b0}}, rshift[7:0]};
`LOAD_BYTE: LoadGenDataOut = {{24{rshift[7]}}, rshift[7:0]};
default: LoadGenDataOut = rshift;
endcase
end
always @* begin
LoadUnknownType = 0;
LoadMissaligned = 0;
case (loadType)
`LOAD_WORD: LoadMissaligned = (|inwordOffset);
`LOAD_HALF_UNSIGNED, `LOAD_HALF: LoadMissaligned = inwordOffset[0];
`LOAD_BYTE_UNSIGNED, `LOAD_BYTE: LoadMissaligned = 0;
default: LoadUnknownType = 1;
endcase
end
endmodule
| 6.853292 |
module armleocpu_multiplier (
input wire clk,
input wire rst_n,
input wire valid,
input wire [31:0] factor0,
input wire [31:0] factor1,
output reg ready,
output wire [63:0] result
);
assign result = accumulator;
/*
multiply two 32b numbers
a = a_up << 16 + a_down;
b = b_up << 16 + b_down;
a * b = (a_up * 2**16 + a_down) * (b_up * 2**16 + b_down) =
= (a_down * b_up * 2**16) + b_down * a_down + (b_down * a_up * 2**16) + (a_up * b_up * 2**32) =
= (b_down * a_down) + (b_up * a_down * 2**16) + (b_down * a_up * 2**16) + (a_up * b_up * 2**32)
=>
ready <= 0;
cycle register ->
intermediate_result <= 0
accumulator <= 0
cycle 0 ->
accumulator <= accumulator + intermediate_result
intermediate_result <= (b_down * a_down)
cycle 1 ->
accumulator <= accumulator + intermediate_result
intermediate_result <= (b_down * a_up) << 16
cycle 2 ->
accumulator <= accumulator + intermediate_result
intermediate_result <= (b_up * a_down) << 16
cycle 3->
accumulator <= accumulator + intermediate_result
intermediate_result <= (b_up * a_up) << 32
cycle 4->
accumulator <= accumulator + intermediate_result
intermediate_result <= (b_down * a_down);// does not matter
ready <= 1;
*/
localparam STATE_IDLE = 1'd0;
localparam STATE_OP = 1'd1;
reg state = STATE_IDLE;
reg [63:0] accumulator;
reg [63:0] intermediate_result;
reg [2:0] cycle;
reg [15:0] a_down;
reg [15:0] b_down;
reg [15:0] a_up;
reg [15:0] b_up;
reg [31:0] mult_in0;
reg [31:0] mult_in1;
wire [31:0] mult_out = mult_in0 * mult_in1;
reg [5:0] shift_count;
always @* begin
shift_count = 0;
mult_in0 = b_down;
mult_in1 = a_down;
case (cycle)
0: begin
mult_in0 = b_down;
mult_in1 = a_down;
end
1: begin
mult_in0 = b_down;
mult_in1 = a_up;
shift_count = 16;
end
2: begin
mult_in0 = b_up;
mult_in1 = a_down;
shift_count = 16;
end
3: begin
mult_in0 = b_up;
mult_in1 = a_up;
shift_count = 32;
end
default: begin
shift_count = 0;
mult_in0 = b_down;
mult_in1 = a_down;
end
endcase
end
always @(posedge clk) begin
if (!rst_n) begin
state <= STATE_IDLE;
ready <= 0;
end else begin
case (state)
STATE_IDLE: begin
ready <= 0;
intermediate_result <= 0;
accumulator <= 0;
cycle <= 0;
a_down <= factor0[15:0];
b_down <= factor1[15:0];
a_up <= factor0[31:16];
b_up <= factor1[31:16];
if (valid) begin
state <= STATE_OP;
end
end
STATE_OP: begin
ready <= 0;
intermediate_result <= 0;
accumulator <= accumulator + intermediate_result;
cycle <= cycle + 1;
case (cycle)
0, 1, 2, 3: begin
intermediate_result <= mult_out << shift_count;
end
4: begin
ready <= 1;
state <= STATE_IDLE;
end
endcase
end
endcase
end
end
/*
`ifdef FORMAL
reg [63:0] saved_result;
reg reseted = 0;
reg checked_at_least_one = 0;
always @(posedge clk) begin
if(valid) begin
saved_result <= {32'b0, factor0} * {32'b0, factor1};
checked_at_least_one <= 1;
end
if(!rst_n) begin
reseted <= 1;
end
if($past(valid) && !ready)
assume ($stable(factor0) && $stable(factor1) && $stable(valid));
// Verify all cases is impossible, but at least we can verify for (-100, +100)
assume((factor0 < 100 && $signed(factor0) > -100) && (factor1 < 100 && $signed(factor1) > -100));
assume(checked_at_least_one || valid || $past(valid));
cover (reseted);
cover (ready);
end
always @(negedge clk)
if(ready && rst_n && reseted)
assert(saved_result == result);
`endif
*/
endmodule
| 6.503524 |
module armleocpu_regfile (
input clk,
input rst_n,
input [ 4:0] rs1_addr,
output [31:0] rs1_rdata,
input [ 4:0] rs2_addr,
output [31:0] rs2_rdata,
input [4:0] rd_addr,
input [31:0] rd_wdata,
input rd_write
);
reg [31:0] regs[31:0];
integer i = 0;
always @(posedge clk) begin : regfile_clk
if (!rst_n) begin : rst_block
for (i = 0; i < 32; i = i + 1) regs[i] <= 0;
end else if (clk) begin
if (rd_write && (rd_addr != 5'd0)) regs[rd_addr] <= rd_wdata;
end
end
assign rs1_rdata = regs[rs1_addr];
assign rs2_rdata = regs[rs2_addr];
endmodule
| 7.172743 |
module armleocpu_storegen (
input [1:0] inwordOffset,
input [1:0] storegenType,
input [31:0] storegenDataIn,
output wire [31:0] storegenDataOut,
output wire [ 3:0] storegenDataMask,
output wire storegenMissAligned,
output wire storegenUnknownType
);
`include "armleocpu_defines.vh"
assign storegenDataMask =
storegenType == `STORE_WORD ? 4'b1111 : (
storegenType == `STORE_HALF ? (4'b11 << inwordOffset) : (
storegenType == `STORE_BYTE ? (4'b1 << inwordOffset) : 4'b0000
));
wire [4:0] woffset = {inwordOffset, 3'b000};
assign storegenDataOut = storegenDataIn << woffset;
assign storegenMissAligned = (
((storegenType == `STORE_WORD) && (|inwordOffset)) ||
((storegenType == `STORE_HALF) && (inwordOffset[0]))
);
assign storegenUnknownType = storegenType == 2'b11;
endmodule
| 7.06965 |
module armleocpu_tlb (
clk,
rst_n,
command,
virtual_address,
hit,
accesstag_r,
phys_r,
virtual_address_w,
accesstag_w,
phys_w,
invalidate_set_index
);
parameter ENTRIES_W = 4;
parameter WAYS_W = 2;
localparam WAYS = 2 ** WAYS_W;
parameter disable_debug = 0;
input clk;
input rst_n;
// commands
input [1:0] command;
// read port
input [19:0] virtual_address;
output reg hit;
output reg [7:0] accesstag_r;
output reg [21:0] phys_r;
// write port
input [19:0] virtual_address_w;
input [7:0] accesstag_w;
input [21:0] phys_w;
// invalidate port
input [ENTRIES_W-1:0] invalidate_set_index;
reg [WAYS_W-1:0] victim_way;
always @(posedge clk) begin
if (!rst_n) begin
victim_way <= 0;
end else begin
if (command == `TLB_CMD_WRITE) victim_way <= victim_way + 1;
end
end
/*
for resolve request resolve for all tlb ways
for write, write to tlb[victim_way]
for invalidate, write 0 to valid to all ways
*/
reg [WAYS_W-1:0] hit_waynum;
reg [ 1:0] tlbway_command [WAYS-1:0];
wire [ WAYS-1:0] tlbway_hit;
wire [ 21:0] tlbway_phys_r [WAYS-1:0];
wire [ 7:0] tlbway_accesstag_r[WAYS-1:0];
integer i;
always @* begin
hit_waynum = 0;
hit = tlbway_hit[0];
phys_r = tlbway_phys_r[0];
accesstag_r = tlbway_accesstag_r[0];
for (i = 0; i < WAYS; i = i + 1) begin
if (tlbway_hit[i]) begin
/* verilator lint_off WIDTH */
hit_waynum = i;
/* verilator lint_on WIDTH */
hit = tlbway_hit[hit_waynum];
phys_r = tlbway_phys_r[hit_waynum];
accesstag_r = tlbway_accesstag_r[hit_waynum];
end
end
end
genvar way_num;
generate
for (way_num = 0; way_num < WAYS; way_num = way_num + 1) begin : mem_generate_for
armleocpu_tlb_way #(ENTRIES_W, disable_debug) u_tlb_way (
.clk (clk),
.rst_n(rst_n),
.command(tlbway_command[way_num]),
.virtual_address(virtual_address),
.hit(tlbway_hit[way_num]),
.accesstag_r(tlbway_accesstag_r[way_num]),
.phys_r(tlbway_phys_r[way_num]),
.virtual_address_w(virtual_address_w),
.accesstag_w(accesstag_w),
.phys_w(phys_w),
.invalidate_set_index(invalidate_set_index)
);
always @* begin
tlbway_command[way_num] = command;
if (command == `TLB_CMD_RESOLVE) begin
tlbway_command[way_num] = command;
end else if (command == `TLB_CMD_WRITE) begin
if (way_num == victim_way) begin
tlbway_command[way_num] = command;
end else begin
tlbway_command[way_num] = `TLB_CMD_NONE;
end
end
end
end
endgenerate
endmodule
| 6.777066 |
module armleocpu_unsigned_divider (
input wire clk,
input wire rst_n,
input wire fetch,
input wire [31:0] dividend,
input wire [31:0] divisor,
output reg ready,
output reg division_by_zero,
output reg [31:0] quotient,
output reg [31:0] remainder
);
reg [31:0] r_dividend;
reg [5:0] counter;
wire [31:0] difference = remainder - divisor;
wire positive = remainder >= divisor;
reg state;
localparam STATE_IDLE = 1'b0;
localparam STATE_OP = 1'b1;
always @(posedge clk) begin
if (!rst_n) begin
state <= STATE_IDLE;
ready <= 0;
division_by_zero <= 1'b0;
end else begin
case (state)
STATE_IDLE: begin
ready <= 0;
division_by_zero <= 1'b0;
counter <= 0;
remainder <= 0;
if (fetch) begin
if (divisor != 0) begin
r_dividend <= dividend;
state <= STATE_OP;
end else begin
ready <= 1'b1;
division_by_zero <= 1'b1;
end
end
end
STATE_OP: begin
r_dividend <= {r_dividend[30:0], 1'b0};
quotient <= {quotient[30:0], positive};
if (positive) begin // add 1 to quotient, substract from dividend
remainder <= {difference[30:0], r_dividend[31]};
end else begin // add 0 to quotient,
remainder <= {remainder[30:0], r_dividend[31]};
end
if (counter != 32) begin
counter <= counter + 6'b1;
end else begin
if (positive) remainder <= difference;
else remainder <= remainder;
ready <= 1'b1;
state <= STATE_IDLE;
end
end
endcase
end
end
endmodule
| 7.370739 |
module armleo_gpio (
`ifdef USE_POWER_PINS
inout vddio,
inout vssio,
inout vdd,
inout vss,
`endif
inout pad,
input med_enable,
input strong_enable,
input out_l,
input oe_l,
output in
);
endmodule
| 7.389926 |
module armleo_gpio (
`ifdef USE_POWER_PINS
inout vddio,
inout vssio,
inout vdd,
inout vss,
`endif
inout pad,
input med_enable,
input strong_enable,
input out_l,
input oe_l,
output in
);
assign pad = oe_l ? out_l : 1'bZ;
assign in = pad;
endmodule
| 7.389926 |
module single_port_ram_21_8 (
clk,
data,
we,
addr,
out
);
`define ADDR_WIDTH_21_8 8
`define DATA_WIDTH_21_8 21
input clk;
input [`DATA_WIDTH_21_8-1:0] data;
input we;
input [`ADDR_WIDTH_21_8-1:0] addr;
output [`DATA_WIDTH_21_8-1:0] out;
reg [`DATA_WIDTH_21_8-1:0] out;
reg [`DATA_WIDTH_21_8-1:0] RAM [255:0];
always @(posedge clk) begin
if (we) begin
RAM[addr] <= data;
out <= RAM[addr];
end
end
endmodule
| 8.023817 |
module single_port_ram_128_8 (
clk,
data,
we,
addr,
out
);
`define ADDR_WIDTH_128_8 8
`define DATA_WIDTH_128_8 128
input clk;
input [`DATA_WIDTH_128_8-1:0] data;
input we;
input [`ADDR_WIDTH_128_8-1:0] addr;
output [`DATA_WIDTH_128_8-1:0] out;
reg [`DATA_WIDTH_128_8-1:0] out;
reg [`DATA_WIDTH_128_8-1:0] RAM [255:0];
always @(posedge clk) begin
if (we) begin
RAM[addr] <= data;
out <= RAM[addr];
end
end
endmodule
| 8.023817 |
module a25_barrel_shift (
i_clk,
i_in,
i_carry_in,
i_shift_amount,
i_shift_imm_zero,
i_function,
o_out,
o_carry_out,
o_stall
);
/************************* IO Declarations *********************/
input i_clk;
input [31:0] i_in;
input i_carry_in;
input [7:0] i_shift_amount; // uses 8 LSBs of Rs, or a 5 bit immediate constant
input i_shift_imm_zero; // high when immediate shift value of zero selected
input [1:0] i_function;
output [31:0] o_out;
output o_carry_out;
output o_stall;
/************************* IO Declarations *********************/
wire [31:0] quick_out;
wire quick_carry_out;
wire [31:0] full_out;
wire full_carry_out;
reg [31:0] full_out_r = 32'd0;
reg full_carry_out_r = 1'd0;
reg use_quick_r = 1'd1;
assign o_stall = (|i_shift_amount[7:2]) & use_quick_r;
assign o_out = use_quick_r ? quick_out : full_out_r;
assign o_carry_out = use_quick_r ? quick_carry_out : full_carry_out_r;
// Capture the result from the full barrel shifter in case the
// quick shifter gives the wrong value
always @(posedge i_clk) begin
full_out_r <= full_out;
full_carry_out_r <= full_carry_out;
use_quick_r <= !o_stall;
end
// Full barrel shifter
a25_shifter_full u_shifter_full (
.i_in (i_in),
.i_carry_in (i_carry_in),
.i_shift_amount (i_shift_amount),
.i_shift_imm_zero(i_shift_imm_zero),
.i_function (i_function),
.o_out (full_out),
.o_carry_out (full_carry_out)
);
// Quick barrel shifter
a25_shifter_quick u_shifter_quick (
.i_in (i_in),
.i_carry_in (i_carry_in),
.i_shift_amount (i_shift_amount),
.i_shift_imm_zero(i_shift_imm_zero),
.i_function (i_function),
.o_out (quick_out),
.o_carry_out (quick_carry_out)
);
endmodule
| 7.686943 |
module a25_multiply (
i_clk,
i_core_stall,
i_a_in,
i_b_in,
i_function,
i_execute,
o_out,
o_flags,
o_done
);
input i_clk;
input i_core_stall;
input [31:0] i_a_in; // Rds
input [31:0] i_b_in; // Rm
input [1:0] i_function;
input i_execute;
output [31:0] o_out;
output [1:0] o_flags; // [1] = N, [0] = Z
output o_done; // goes high 2 cycles before completion
reg o_done = 1'd0;
wire enable;
wire accumulate;
wire [33:0] multiplier;
wire [33:0] multiplier_bar;
wire [33:0] sum;
wire [33:0] sum34_b;
reg [ 5:0] count = 6'd0;
reg [ 5:0] count_nxt;
reg [67:0] product = 68'd0;
reg [67:0] product_nxt;
reg [ 1:0] flags_nxt;
wire [32:0] sum_acc1; // the MSB is the carry out for the upper 32 bit addition
assign enable = i_function[0];
assign accumulate = i_function[1];
assign multiplier = {2'd0, i_a_in};
assign multiplier_bar = ~{2'd0, i_a_in} + 34'd1;
assign sum34_b = product[1:0] == 2'b01 ? multiplier :
product[1:0] == 2'b10 ? multiplier_bar :
34'd0 ;
// -----------------------------------
// 34-bit adder - booth multiplication
// -----------------------------------
assign sum = product[67:34] + sum34_b;
// ------------------------------------
// 33-bit adder - accumulate operations
// ------------------------------------
assign sum_acc1 = {1'd0, product[32:1]} + {1'd0, i_a_in};
// assign count_nxt = count;
always @* begin
// update Negative and Zero flags
// Use registered value of product so this adds an extra cycle
// but this avoids having the 64-bit zero comparator on the
// main adder path
flags_nxt = {product[32], product[32:1] == 32'd0};
if (count == 6'd0) product_nxt = {33'd0, 1'd0, i_b_in, 1'd0};
else if (count <= 6'd33) product_nxt = {sum[33], sum, product[33:1]};
else if (count == 6'd34 && accumulate) begin
// Note that bit 0 is not part of the product. It is used during the booth
// multiplication algorithm
product_nxt = {product[64:33], sum_acc1[31:0], 1'd0}; // Accumulate
end else product_nxt = product;
// Multiplication state counter
if (count == 6'd0) // start
count_nxt = enable ? 6'd1 : 6'd0;
else if ((count == 6'd34 && !accumulate) || // MUL
(count == 6'd35 && accumulate)) // MLA
count_nxt = 6'd0;
else count_nxt = count + 1'd1;
end
always @(posedge i_clk)
if (!i_core_stall) begin
count <= i_execute ? count_nxt : count;
product <= i_execute ? product_nxt : product;
o_done <= i_execute ? count == 6'd31 : o_done;
end
// Outputs
assign o_out = product[32:1];
assign o_flags = flags_nxt;
endmodule
| 7.219736 |
module a25_write_back(
i_clk,
i_mem_stall,
i_mem_read_data,
i_mem_read_data_valid,
i_mem_load_rd,
o_wb_read_data,
o_wb_read_data_valid,
o_wb_load_rd,
i_daddress,
// i_daddress_valid
);
input i_clk;
input i_mem_stall; // Mem stage asserting stall
input [31:0] i_mem_read_data; // data reads
input i_mem_read_data_valid; // read data is valid
input [10:0] i_mem_load_rd; // Rd for data reads
output [31:0] o_wb_read_data; // data reads
output o_wb_read_data_valid; // read data is valid
output [10:0] o_wb_load_rd; // Rd for data reads
input [31:0] i_daddress;
//input i_daddress_valid;
reg [31:0] mem_read_data_r = 32'd0; // Register read data from Data Cache
reg mem_read_data_valid_r = 1'd0; // Register read data from Data Cache
reg [10:0] mem_load_rd_r = 11'd0; // Register the Rd value for loads
assign o_wb_read_data = mem_read_data_r;
assign o_wb_read_data_valid = mem_read_data_valid_r;
assign o_wb_load_rd = mem_load_rd_r;
always @( posedge i_clk )
if ( !i_mem_stall )
begin
mem_read_data_r <= i_mem_read_data;
mem_read_data_valid_r <= i_mem_read_data_valid;
mem_load_rd_r <= i_mem_load_rd;
end
// Used by a25_decompile.v, so simulation only
//synopsys translate_off
reg [31:0] daddress_r = 32'd0; // Register read data from Data Cache
always @( posedge i_clk )
if ( !i_mem_stall )
daddress_r <= i_daddress;
//synopsys translate_on
endmodule
| 6.942168 |
module HazardDetection (
input EX_memRead_in,
input [4:0] EX_write_reg,
input [63:0] ID_PC,
input [31:0] ID_IC,
output reg IFID_write_out,
output reg PC_Write_out,
output reg Control_mux_out
);
always @(*) begin
if (EX_memRead_in == 1'b1 && ((EX_write_reg === ID_IC[9:5]) || (EX_write_reg === ID_IC[20:16]))) begin
IFID_write_out <= 1'b1;
PC_Write_out <= 1'b1;
Control_mux_out <= 1'b1;
end else begin
IFID_write_out <= 1'b0;
PC_Write_out <= 1'b0;
Control_mux_out <= 1'b0;
end
end
endmodule
| 6.580064 |
module IFID (
input CLOCK,
input [63:0] PC_in,
input [31:0] IC_in,
input Hazard_in,
output reg [63:0] PC_out,
output reg [31:0] IC_out
);
always @(negedge CLOCK) begin
if (Hazard_in !== 1'b1) begin
PC_out <= PC_in;
IC_out <= IC_in;
end
end
endmodule
| 8.166279 |
module IDEX (
input CLOCK,
input [1:0] aluop_in,
input alusrc_in,
input isZeroBranch_in,
input isUnconBranch_in,
input memRead_in,
input memwrite_in,
input regwrite_in,
input mem2reg_in,
input [63:0] PC_in,
input [63:0] regdata1_in,
input [63:0] regdata2_in,
input [63:0] sign_extend_in,
input [10:0] alu_control_in,
input [4:0] write_reg_in,
input [4:0] forward_reg_1_in, // Forwarding
input [4:0] forward_reg_2_in, // Forwarding
output reg [1:0] aluop_out,
output reg alusrc_out,
output reg isZeroBranch_out,
output reg isUnconBranch_out,
output reg memRead_out,
output reg memwrite_out,
output reg regwrite_out,
output reg mem2reg_out,
output reg [63:0] PC_out,
output reg [63:0] regdata1_out,
output reg [63:0] regdata2_out,
output reg [63:0] sign_extend_out,
output reg [10:0] alu_control_out,
output reg [4:0] write_reg_out,
output reg [4:0] forward_reg_1_out, // Forwarding
output reg [4:0] forward_reg_2_out // Forwarding
);
always @(negedge CLOCK) begin
/* Values for EX */
aluop_out <= aluop_in;
alusrc_out <= alusrc_in;
/* Values for M */
isZeroBranch_out <= isZeroBranch_in;
isUnconBranch_out <= isUnconBranch_in;
memRead_out <= memRead_in;
memwrite_out <= memwrite_in;
/* Values for WB */
regwrite_out <= regwrite_in;
mem2reg_out <= mem2reg_in;
/* Values for all Stages */
PC_out <= PC_in;
regdata1_out <= regdata1_in;
regdata2_out <= regdata2_in;
/* Values for variable stages */
sign_extend_out <= sign_extend_in;
alu_control_out <= alu_control_in;
write_reg_out <= write_reg_in;
forward_reg_1_out <= forward_reg_1_in;
forward_reg_2_out <= forward_reg_2_in;
end
endmodule
| 7.449647 |
module EXMEM (
input CLOCK,
input isZeroBranch_in, // M Stage
input isUnconBranch_in, // M Stage
input memRead_in, // M Stage
input memwrite_in, // M Stage
input regwrite_in, // WB Stage
input mem2reg_in, // WB Stage
input [63:0] shifted_PC_in,
input alu_zero_in,
input [63:0] alu_result_in,
input [63:0] write_data_mem_in,
input [4:0] write_reg_in,
output reg isZeroBranch_out, // M Stage
output reg isUnconBranch_out, // M Stage
output reg memRead_out, // M Stage
output reg memwrite_out, // M Stage
output reg regwrite_out, // WB Stage
output reg mem2reg_out, // WB Stage
output reg [63:0] shifted_PC_out,
output reg alu_zero_out,
output reg [63:0] alu_result_out,
output reg [63:0] write_data_mem_out,
output reg [4:0] write_reg_out
);
always @(negedge CLOCK) begin
/* Values for M */
isZeroBranch_out <= isZeroBranch_in;
isUnconBranch_out <= isUnconBranch_in;
memRead_out <= memRead_in;
memwrite_out <= memwrite_in;
/* Values for WB */
regwrite_out <= regwrite_in;
mem2reg_out <= mem2reg_in;
/* Values for all Stages */
shifted_PC_out <= shifted_PC_in;
alu_zero_out <= alu_zero_in;
alu_result_out <= alu_result_in;
write_data_mem_out <= write_data_mem_in;
write_reg_out <= write_reg_in;
end
endmodule
| 6.633817 |
module MEMWB (
input CLOCK,
input [63:0] mem_address_in,
input [63:0] mem_data_in,
input [4:0] write_reg_in,
input regwrite_in,
input mem2reg_in,
output reg [63:0] mem_address_out,
output reg [63:0] mem_data_out,
output reg [4:0] write_reg_out,
output reg regwrite_out,
output reg mem2reg_out
);
always @(negedge CLOCK) begin
regwrite_out <= regwrite_in;
mem2reg_out <= mem2reg_in;
mem_address_out <= mem_address_in;
mem_data_out <= mem_data_in;
write_reg_out <= write_reg_in;
end
endmodule
| 6.910178 |
module Registers (
input CLOCK,
input [4:0] read1,
input [4:0] read2,
input [4:0] writeReg,
input [63:0] writeData,
input CONTROL_REGWRITE,
output reg [63:0] data1,
output reg [63:0] data2
);
reg [63:0] Data[31:0];
integer initCount;
initial begin
for (initCount = 0; initCount < 31; initCount = initCount + 1) begin
Data[initCount] = initCount;
end
Data[31] = 64'h00000000;
end
always @(posedge CLOCK) begin
if (CONTROL_REGWRITE == 1'b1) begin
Data[writeReg] = writeData;
end
data1 = Data[read1];
data2 = Data[read2];
// Debug use only
for (initCount = 0; initCount < 32; initCount = initCount + 1) begin
$display("REGISTER[%0d] = %0d", initCount, Data[initCount]);
end
end
endmodule
| 7.405039 |
module Data_Memory (
input [63:0] inputAddress,
input [63:0] inputData,
input CONTROL_MemWrite,
input CONTROL_MemRead,
output reg [63:0] outputData
);
reg [63:0] Data[31:0];
integer initCount;
initial begin
for (initCount = 0; initCount < 32; initCount = initCount + 1) begin
Data[initCount] = initCount * 5;
end
end
always @(*) begin
if (CONTROL_MemWrite == 1'b1) begin
Data[inputAddress] = inputData;
end else if (CONTROL_MemRead == 1'b1) begin
outputData = Data[inputAddress];
end else begin
outputData = 64'hxxxxxxxx;
end
// Debug use only
for (initCount = 0; initCount < 32; initCount = initCount + 1) begin
$display("RAM[%0d] = %0d", initCount, Data[initCount]);
end
end
endmodule
| 7.239913 |
module ALU (
input [63:0] A,
input [63:0] B,
input [4:0] CONTROL,
output reg [63:0] RESULT,
output reg ZEROFLAG
);
always @(*) begin
case (CONTROL)
5'b00000: RESULT = A & B;
5'b00001: RESULT = A | B;
5'b00010: RESULT = A + B;
5'b00110: RESULT = A - B;
5'b00111: RESULT = B;
5'b01100: RESULT = ~(A | B);
5'b01101: RESULT = A ^ B;
5'b01111: RESULT = A >>> B;
5'b10000: RESULT = A << B;
5'b10010: RESULT = !B;
default: RESULT = 64'hxxxxxxxx;
endcase
if (RESULT == 0) begin
ZEROFLAG = 1'b1;
end else if (RESULT != 0) begin
ZEROFLAG = 1'b0;
end else begin
ZEROFLAG = 1'bx;
end
end
endmodule
| 7.960621 |
module Forward_ALU_Mux (
input [63:0] reg_ex_in,
input [63:0] reg_wb_in,
input [63:0] reg_mem_in,
input [1:0] forward_control_in,
output reg [63:0] reg_out
);
always @(*) begin
case (forward_control_in)
2'b01: reg_out <= reg_wb_in;
2'b10: reg_out <= reg_mem_in;
default: reg_out <= reg_ex_in;
endcase
end
endmodule
| 7.604902 |
module ALU_Mux (
input [63:0] input1,
input [63:0] input2,
input CONTROL_ALUSRC,
output reg [63:0] out
);
always @(input1, input2, CONTROL_ALUSRC, out) begin
if (CONTROL_ALUSRC === 0) begin
out <= input1;
end else begin
out <= input2;
end
end
endmodule
| 7.331368 |
module ID_Mux (
input [4:0] read1_in,
input [4:0] read2_in,
input reg2loc_in,
output reg [4:0] reg_out
);
always @(read1_in, read2_in, reg2loc_in) begin
case (reg2loc_in)
1'b0: begin
reg_out <= read1_in;
end
1'b1: begin
reg_out <= read2_in;
end
default: begin
reg_out <= 1'bx;
end
endcase
end
endmodule
| 7.509663 |
module WB_Mux (
input [63:0] input1,
input [63:0] input2,
input mem2reg_control,
output reg [63:0] out
);
always @(*) begin
if (mem2reg_control == 0) begin
out <= input1;
end else begin
out <= input2;
end
end
endmodule
| 7.226496 |
module SignExtend (
input [31:0] inputInstruction,
output reg [63:0] outImmediate
);
always @(inputInstruction) begin
if (inputInstruction[31:26] == 6'b000101) begin // B
outImmediate[25:0] = inputInstruction[25:0];
outImmediate[63:26] = {64{outImmediate[25]}};
end else if (inputInstruction[31:24] == 8'b10110100) begin // CBZ
outImmediate[18:0] = inputInstruction[23:5];
outImmediate[63:19] = {64{outImmediate[18]}};
end else if (inputInstruction[31:24] == 8'b10110101) begin // CBNZ
outImmediate[18:0] = inputInstruction[23:5];
outImmediate[63:19] = {64{outImmediate[18]}};
end else if (inputInstruction[26:22] == 5'b00100 || inputInstruction[26:22] == 5'b01000) begin // I Type
outImmediate[12:0] = inputInstruction[21:10];
end else if (inputInstruction[31:21] == 11'b11010011010) begin // R Type
outImmediate[6:0] = inputInstruction[15:10];
end else if (inputInstruction[31:21] == 11'b11010011011) begin // R Type
outImmediate[6:0] = inputInstruction[15:10];
end else begin // D Type, ignored if R type
outImmediate[9:0] = inputInstruction[20:12];
outImmediate[63:10] = {64{outImmediate[9]}};
end
end
endmodule
| 7.619369 |
module SL2 (
input [`DATA_WIDTH-1:0] in,
output [`DATA_WIDTH-1:0] out
);
assign out = {in[29:0], 2'b00};
endmodule
| 6.690903 |
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