code
stringlengths
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score
float64
6.5
11.5
module Add_full_894 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1788 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1787 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.644602
module Add_full_895 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1790 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1789 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.363508
module Add_full_881 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1762 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1761 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.535208
module Add_full_882 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1764 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1763 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.836907
module Add_full_885 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1770 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1769 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
6.990463
module Add_full_886 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1772 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1771 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.082415
module Add_full_889 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1778 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1777 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.189553
module Add_full_890 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1780 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1779 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.389887
module Add_full_833 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1666 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1665 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.641416
module Add_full_834 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1668 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1667 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
8.140189
module Add_full_835 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1670 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1669 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.282933
module Add_full_837 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1674 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1673 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.368171
module Add_full_838 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1676 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1675 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.322744
module Add_full_841 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1682 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1681 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
8.005395
module Add_full_842 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1684 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1683 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.719628
module Add_full_845 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1690 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1689 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
8.347259
module Add_full_846 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1692 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1691 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.668627
module Add_full_849 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1698 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1697 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.67283
module Add_full_850 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1700 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1699 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.0709
module Add_full_853 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1706 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1705 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.328953
module Add_full_854 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1708 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1707 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.564817
module Add_full_857 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1714 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1713 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.450317
module Add_full_858 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1716 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1715 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.762597
module Add_full_861 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1722 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1721 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.617367
module Add_full_862 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1724 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1723 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.533447
module Add_full_873 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1746 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1745 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.60832
module Add_full_874 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1748 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1747 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
8.030243
module Add_full_877 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1754 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1753 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.401512
module Add_full_878 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1756 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1755 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w3), .B(w2), .Z(c_out) ); endmodule
7.528799
module Add_full_769 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1538 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1537 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.260338
module Add_full_770 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1540 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1539 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.62449
module Add_full_771 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1542 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1541 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.373641
module Add_full_772 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1544 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1543 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.468892
module Add_full_773 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1546 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1545 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.744008
module Add_full_774 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1548 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1547 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.576326
module Add_full_775 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1550 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1549 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.158634
module Add_full_776 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1552 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1551 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.548073
module Add_full_777 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1554 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1553 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.346736
module Add_full_778 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1556 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1555 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.413215
module Add_full_779 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1558 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1557 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.28637
module Add_full_780 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1560 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1559 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.518336
module Add_full_781 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1562 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1561 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.724848
module Add_full_782 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1564 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1563 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.953071
module Add_full_783 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1566 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1565 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.48479
module Add_full_784 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1568 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1567 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
8.146533
module Add_full_785 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1570 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1569 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.525069
module Add_full_786 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1572 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1571 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.604485
module Add_full_787 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1574 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1573 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.934396
module Add_full_788 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1576 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1575 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.468521
module Add_full_789 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1578 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1577 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.508497
module Add_full_790 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1580 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1579 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.583531
module Add_full_791 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1582 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1581 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.493681
module Add_full_792 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1584 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1583 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.698553
module Add_full_793 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1586 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1585 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.744362
module Add_full_794 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1588 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1587 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.802128
module Add_full_795 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1590 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1589 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.602132
module Add_full_796 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1592 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1591 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.832552
module Add_full_797 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1594 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1593 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.669046
module Add_full_798 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1596 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1595 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
8.146123
module Add_full_799 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1598 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1597 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.789755
module Add_full_800 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1600 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1599 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.908048
module Add_full_801 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1602 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1601 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.791746
module Add_full_802 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1604 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1603 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
8.060559
module Add_full_803 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1606 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1605 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.590959
module Add_full_804 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1608 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1607 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.925799
module Add_full_805 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1610 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1609 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.269433
module Add_full_806 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1612 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1611 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.394736
module Add_full_807 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1614 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1613 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.539748
module Add_full_808 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1616 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1615 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.823443
module Add_full_809 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1618 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1617 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.260906
module Add_full_810 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1620 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1619 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.664579
module Add_full_813 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1626 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1625 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.635709
module Add_full_814 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1628 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1627 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.985125
module Add_full_817 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1634 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1633 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
8.112082
module Add_full_818 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1636 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1635 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
8.031108
module Add_full_819 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1638 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1637 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
8.127016
module Add_full_820 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1640 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1639 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
8.149887
module Add_full_821 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1642 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1641 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.675778
module Add_full_822 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1644 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1643 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.720831
module Add_full_823 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1646 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1645 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.579529
module Add_full_824 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1648 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1647 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
8.133468
module Add_full_825 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1650 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1649 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.740487
module Add_full_826 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1652 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1651 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.573882
module Add_full_829 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1658 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1657 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.548023
module Add_full_830 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1660 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1659 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.369655
module Add_full_1 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_2 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_1 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.393351
module Add_full_2 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_4 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_3 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.865445
module Add_full_3 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3, n1; Add_half_6 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_5 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); CND2IX1 U1 ( .B(w3), .A(n1), .Z(c_out) ); CIVX1 U2 ( .A(w2), .Z(n1) ); endmodule
7.81088
module Add_full_4 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3, n1, n2; Add_half_8 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_7 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); CIVX1 U1 ( .A(w3), .Z(n2) ); CIVX1 U2 ( .A(w2), .Z(n1) ); CND2X2 U3 ( .A(n2), .B(n1), .Z(c_out) ); endmodule
7.766813
module Add_full_5 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_10 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_9 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.112192
module Add_full_6 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_12 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_11 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); COR2X1 U1 ( .A(w2), .B(w3), .Z(c_out) ); endmodule
7.571522
module Add_full_7 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3, n1, n2; Add_half_14 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_13 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); CIVX1 U1 ( .A(w2), .Z(n1) ); CIVX2 U2 ( .A(w3), .Z(n2) ); CND2X2 U3 ( .A(n2), .B(n1), .Z(c_out) ); endmodule
7.428688
module Add_full_8 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3, n1, n2; Add_half_16 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_15 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); CND2X2 U1 ( .A(n2), .B(n1), .Z(c_out) ); CIVX2 U2 ( .A(w3), .Z(n2) ); CIVX2 U3 ( .A(w2), .Z(n1) ); endmodule
7.221736
module Add_full_9 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3, n1, n2; Add_half_18 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_17 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); CIVX2 U1 ( .A(w3), .Z(n2) ); CIVX2 U2 ( .A(w2), .Z(n1) ); CND2X2 U3 ( .A(n2), .B(n1), .Z(c_out) ); endmodule
7.055693
module Add_full_10 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3, n1, n2; Add_half_20 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_19 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); CIVX2 U1 ( .A(w3), .Z(n2) ); CIVX2 U2 ( .A(w2), .Z(n1) ); CND2X2 U3 ( .A(n2), .B(n1), .Z(c_out) ); endmodule
6.784429
module Add_full_11 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3, n1, n2; Add_half_22 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_21 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); CIVX2 U1 ( .A(w3), .Z(n2) ); CIVX2 U2 ( .A(w2), .Z(n1) ); CND2X2 U3 ( .A(n2), .B(n1), .Z(c_out) ); endmodule
6.996495
module Add_full_12 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3, n1, n2; Add_half_24 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_23 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); CIVX2 U1 ( .A(w3), .Z(n2) ); CIVX2 U2 ( .A(w2), .Z(n1) ); CND2X2 U3 ( .A(n2), .B(n1), .Z(c_out) ); endmodule
7.246159
module Add_full_13 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3, n1; Add_half_26 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_25 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); CND2IX1 U1 ( .B(w3), .A(n1), .Z(c_out) ); CIVX2 U2 ( .A(w2), .Z(n1) ); endmodule
6.86246
module Add_full_14 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3, n1; Add_half_28 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_27 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); CND2IX1 U1 ( .B(w3), .A(n1), .Z(c_out) ); CIVX2 U2 ( .A(w2), .Z(n1) ); endmodule
7.326838
module Add_full_15 ( sum, c_out, a, b, c_in ); input a, b, c_in; output sum, c_out; wire w1, w2, w3, n1, n2; Add_half_30 M1 ( .sum(w1), .c_out(w2), .a(a), .b(b) ); Add_half_29 M2 ( .sum(sum), .c_out(w3), .a(w1), .b(c_in) ); CND2X2 U1 ( .A(n1), .B(n2), .Z(c_out) ); CIVX1 U2 ( .A(w2), .Z(n2) ); CIVX2 U3 ( .A(w3), .Z(n1) ); endmodule
6.973073