code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Add_full_16 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_32 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_31 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX1 U1 (
.A(w2),
.Z(n1)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CND2X2 U3 (
.A(n2),
.B(n1),
.Z(c_out)
);
endmodule
| 7.262265 |
module Add_full_17 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_34 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_33 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.298444 |
module Add_full_18 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_36 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_35 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 6.931267 |
module Add_full_19 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_38 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_37 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX1 U1 (
.A(w2),
.Z(n1)
);
CND2X2 U2 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U3 (
.A(w3),
.Z(n2)
);
endmodule
| 7.326513 |
module Add_full_20 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_40 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_39 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX1 U1 (
.A(w2),
.Z(n1)
);
CND2X2 U2 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U3 (
.A(w3),
.Z(n2)
);
endmodule
| 7.06258 |
module Add_full_21 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_42 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_41 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 6.962926 |
module Add_full_22 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_44 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_43 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.068851 |
module Add_full_23 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_46 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_45 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX1 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.043089 |
module Add_full_24 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_48 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_47 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX1 U1 (
.A(w2),
.Z(n1)
);
CND2X2 U2 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U3 (
.A(w3),
.Z(n2)
);
endmodule
| 7.399368 |
module Add_full_25 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_50 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_49 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 6.736335 |
module Add_full_26 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_52 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_51 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 6.952263 |
module Add_full_27 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_54 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_53 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X2 U1 (
.A(n1),
.B(n2),
.Z(c_out)
);
CIVX1 U2 (
.A(w3),
.Z(n1)
);
CIVX2 U3 (
.A(w2),
.Z(n2)
);
endmodule
| 6.954563 |
module Add_full_28 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_56 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_55 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 6.75667 |
module Add_full_29 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_58 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_57 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 6.839237 |
module Add_full_30 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_60 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_59 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 6.622722 |
module Add_full_31 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_62 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_61 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 6.712343 |
module Add_full_32 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_64 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_63 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.26049 |
module Add_full_33 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_66 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_65 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 6.703846 |
module Add_full_34 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_68 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_67 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.083911 |
module Add_full_35 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_70 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_69 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX2 U1 (
.A(w3),
.Z(n2)
);
CND2X2 U2 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX1 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.079811 |
module Add_full_36 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_72 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_71 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X2 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX1 U2 (
.A(w2),
.Z(n1)
);
CIVX2 U3 (
.A(w3),
.Z(n2)
);
endmodule
| 7.250015 |
module Add_full_37 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_74 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_73 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.466217 |
module Add_full_38 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_76 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_75 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.359058 |
module Add_full_39 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_78 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_77 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX2 U1 (
.A(w3),
.Z(n2)
);
CND2X2 U2 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX1 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 6.994652 |
module Add_full_40 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_80 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_79 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX1 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.123718 |
module Add_full_41 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_82 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_81 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.122105 |
module Add_full_42 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_84 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_83 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.450762 |
module Add_full_43 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_86 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_85 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX2 U1 (
.A(w3),
.Z(n2)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
CND2X2 U3 (
.A(n2),
.B(n1),
.Z(c_out)
);
endmodule
| 7.453006 |
module Add_full_44 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_88 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_87 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX1 U1 (
.A(w3),
.Z(n2)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
CND2X2 U3 (
.A(n2),
.B(n1),
.Z(c_out)
);
endmodule
| 7.780912 |
module Add_full_45 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_90 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_89 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.385985 |
module Add_full_46 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_92 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_91 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.477874 |
module Add_full_47 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_94 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_93 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X2 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.519532 |
module Add_full_48 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_96 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_95 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX1 U1 (
.A(w3),
.Z(n2)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
CND2X2 U3 (
.A(n2),
.B(n1),
.Z(c_out)
);
endmodule
| 8.00484 |
module Add_full_49 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_98 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_97 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.36534 |
module Add_full_50 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_100 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_99 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 6.892613 |
module Add_full_51 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_102 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_101 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X2 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX1 U2 (
.A(w2),
.Z(n1)
);
CIVX2 U3 (
.A(w3),
.Z(n2)
);
endmodule
| 7.096773 |
module Add_full_52 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_104 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_103 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX1 U2 (
.A(w2),
.Z(n1)
);
CIVX2 U3 (
.A(w3),
.Z(n2)
);
endmodule
| 7.267293 |
module Add_full_53 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_106 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_105 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.237405 |
module Add_full_54 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_108 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_107 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.551716 |
module Add_full_55 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_110 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_109 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X2 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX1 U2 (
.A(w2),
.Z(n1)
);
CIVX2 U3 (
.A(w3),
.Z(n2)
);
endmodule
| 6.889263 |
module Add_full_56 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_112 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_111 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX1 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.604716 |
module Add_full_57 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_114 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_113 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.339343 |
module Add_full_58 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_116 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_115 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.160321 |
module Add_full_59 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_118 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_117 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX2 U1 (
.A(w3),
.Z(n2)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
CND2X2 U3 (
.A(n2),
.B(n1),
.Z(c_out)
);
endmodule
| 6.903887 |
module Add_full_60 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_120 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_119 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX2 U1 (
.A(w3),
.Z(n2)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
CND2X2 U3 (
.A(n2),
.B(n1),
.Z(c_out)
);
endmodule
| 7.282254 |
module Add_full_61 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_122 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_121 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.121962 |
module Add_full_62 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_124 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_123 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.517621 |
module Add_full_63 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_126 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_125 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX2 U1 (
.A(w3),
.Z(n2)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
CND2X2 U3 (
.A(n2),
.B(n1),
.Z(c_out)
);
endmodule
| 7.194667 |
module Add_full_64 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_128 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_127 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX2 U1 (
.A(w3),
.Z(n2)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
CND2X2 U3 (
.A(n2),
.B(n1),
.Z(c_out)
);
endmodule
| 8.163176 |
module Add_full_65 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_130 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_129 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.149955 |
module Add_full_66 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_132 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_131 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.018042 |
module Add_full_67 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_134 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_133 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.369276 |
module Add_full_68 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_136 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_135 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.338827 |
module Add_full_69 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_138 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_137 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.029991 |
module Add_full_70 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_140 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_139 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.073527 |
module Add_full_71 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_142 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_141 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.116999 |
module Add_full_72 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_144 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_143 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X2 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.433799 |
module Add_full_73 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_146 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_145 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.452865 |
module Add_full_74 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_148 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_147 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.823072 |
module Add_full_75 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_150 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_149 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX1 U2 (
.A(w3),
.Z(n2)
);
CIVX1 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.393869 |
module Add_full_76 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_152 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_151 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX1 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.564621 |
module Add_full_77 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_154 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_153 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.132523 |
module Add_full_78 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_156 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_155 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.424057 |
module Add_full_79 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_158 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_157 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX1 U1 (
.A(w2),
.Z(n1)
);
CND2X1 U2 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U3 (
.A(w3),
.Z(n2)
);
endmodule
| 7.271212 |
module Add_full_80 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_160 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_159 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX1 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.201595 |
module Add_full_81 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_162 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_161 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.150909 |
module Add_full_82 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_164 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_163 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.318065 |
module Add_full_83 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_166 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_165 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.252425 |
module Add_full_84 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_168 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_167 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.812065 |
module Add_full_85 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_170 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_169 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.08346 |
module Add_full_86 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_172 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_171 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.304421 |
module Add_full_87 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_174 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_173 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.428301 |
module Add_full_88 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_176 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_175 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.253977 |
module Add_full_89 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_178 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_177 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 6.931841 |
module Add_full_90 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_180 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_179 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 6.878769 |
module Add_full_91 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_182 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_181 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX1 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.076371 |
module Add_full_92 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_184 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_183 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX1 U2 (
.A(w3),
.Z(n2)
);
CIVX1 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.106879 |
module Add_full_93 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_186 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_185 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX2 U1 (
.A(w3),
.Z(n2)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
CND2X2 U3 (
.A(n2),
.B(n1),
.Z(c_out)
);
endmodule
| 7.0747 |
module Add_full_94 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_188 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_187 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX2 U1 (
.A(w3),
.Z(n2)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
CND2X2 U3 (
.A(n2),
.B(n1),
.Z(c_out)
);
endmodule
| 7.493056 |
module Add_full_95 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_190 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_189 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX1 U1 (
.A(w2),
.Z(n1)
);
CND2X1 U2 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U3 (
.A(w3),
.Z(n2)
);
endmodule
| 7.277177 |
module Add_full_96 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_192 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_191 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX1 U2 (
.A(w2),
.Z(n1)
);
CIVX2 U3 (
.A(w3),
.Z(n2)
);
endmodule
| 7.556384 |
module Add_full_97 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_194 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_193 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.339546 |
module Add_full_98 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_196 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_195 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.243341 |
module Add_full_99 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_198 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_197 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X2 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX1 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.202182 |
module Add_full_100 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_200 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_199 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 6.944675 |
module Add_full_101 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_202 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_201 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX2 U1 (
.A(w3),
.Z(n2)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
CND2X2 U3 (
.A(n2),
.B(n1),
.Z(c_out)
);
endmodule
| 7.356437 |
module Add_full_102 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_204 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_203 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.319058 |
module Add_full_103 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_206 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_205 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX2 U1 (
.A(w3),
.Z(n2)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
CND2X2 U3 (
.A(n2),
.B(n1),
.Z(c_out)
);
endmodule
| 7.320586 |
module Add_full_104 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_208 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_207 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX2 U1 (
.A(w3),
.Z(n2)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
CND2X2 U3 (
.A(n2),
.B(n1),
.Z(c_out)
);
endmodule
| 7.668271 |
module Add_full_105 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_210 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_209 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.03693 |
module Add_full_106 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_212 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_211 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.627773 |
module Add_full_107 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_214 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_213 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.587376 |
module Add_full_108 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_216 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_215 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.550903 |
module Add_full_109 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_218 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_217 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.319791 |
module Add_full_110 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_220 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_219 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 6.994766 |
module Add_full_111 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_222 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_221 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.116813 |
module Add_full_112 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_224 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_223 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.449684 |
module Add_full_113 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_226 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_225 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 6.851947 |
module Add_full_114 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_228 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_227 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.289663 |
module Add_full_115 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_230 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_229 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX1 U1 (
.A(w3),
.Z(n2)
);
CND2X2 U2 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 6.82993 |
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