code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Adder (
input wire [`DATA_WIDTH-1:0] Op1,
Op2,
output wire [`DATA_WIDTH-1:0] Out
);
assign Out = Op1 + Op2;
endmodule
| 7.642138 |
module Mux2 //2选1
#(
parameter WIDTH = 8
) (
input [WIDTH-1:0] d0,
d1,
input select,
output [WIDTH-1:0] y
);
assign y = select ? d1 : d0;
endmodule
| 8.98768 |
module Mux4 //4选1
#(
parameter WIDTH = 8
) (
input [WIDTH-1:0] d0,
d1,
d2,
d3,
input [1:0] select,
output reg [WIDTH-1:0] y
);
always @(*) begin
case ({
select[1], select[0]
})
2'b00: y = d0;
2'b01: y = d1;
2'b10: y = d2;
2'b11: y = d3;
... | 8.692438 |
module DMem (
Data_Write,
Data_Out,
Addr,
MemWrite,
MemRead,
CLK
);
parameter Addr_Width = 12; //参数化地址线宽
parameter Data_Width = `DATA_WIDTH; //参数化数据线宽
parameter SIZE = 2 ** Addr_Width; //参数化大小4K
input [Data_Width-1:0] Data_Write; // 写入的数据
output [Data_Width-1:0] Data_Out; // 读出的数据... | 8.99805 |
module IMem (
input [63:0] A, // 地址(PC)64位
output [31:0] RD
); // 指令32位
parameter IMEM_SIZE = 512; // 最多512条指令
//指令寄存器
reg [31:0] RAM[IMEM_SIZE-1:0];
initial begin
$readmemh("/home/jinstorm/IMem.txt", RAM);
end
assign RD = RAM[A>>2]; //指令输出
endmodule
| 7.299969 |
module MainDec ( //主译码器
input [10:0] Op,
output MemToReg,
MemWrite,
MemRead,
output Branch,
ALUSrc,
output Reg2Loc,
RegWrite,
//output Jump,
output [1:0] ALUOp
);
//MainDec MainDec_1(Opcode, MemToReg, MemWrite, MemRead, Branch, ALUSrc, Reg2Loc, RegWrite, ALUOp);
reg [8:0] Co... | 6.533465 |
module ALU (
F,
A,
B,
OP,
Zero
);
parameter SIZE = `DATA_WIDTH; //运算位数
input [3:0] OP; //运算操作
input [SIZE-1:0] A; //左运算数
input [SIZE-1:0] B; //右运算数
//input CLK;
output [SIZE-1:0] F; //运算结果
//output CF; //进借位标志位
output reg Zero; //0标志位
reg [SIZE-1:0] F;
reg C; //, CF;
... | 7.043664 |
module register(Q, D, OE, CLK);
// parameter N = 8;
// output reg [N-1:0] Q; // 输出Q
// input [N:1] D;
// input OE, CLK; //三态输出
// //CLK，OE边沿敏感触发
// always @ (posedge CLK or posedge OE)
// if (OE) Q <= 8'bzzzz_zzzz; // 使能无效输出高阻态
// else Q <= D; //存入和读出数据
// endmodule
| 7.419465 |
module RegIFID (
Q,
D,
IF_ID_Write,
IF_ID_flush,
CLK
);
parameter N = 96; // 64PC+32指令
output reg [N-1:0] Q; // 输出Q(96)
input [N-1:0] D; // 输入
input IF_ID_Write, IF_ID_flush;
input CLK;
//CLK边沿敏感触发
always @(posedge CLK) begin
//if (OE) Q <= 8'bzzzz_zzzz; // 使能无效输出高阻态
//else... | 7.002608 |
module RegIDEX (
RegWrite_o,
MemToReg_o,
Branch_o,
MemRead_o,
MemWrite_o,
ALUControl_o,
ALUSrc_o,
PC_o,
ReadData1_o,
ReadData2_o,
Sig_o,
Instr_o,
CLK,
RegWrite,
MemToReg,
Branch,
MemRead,
MemWrite,
ALUControl,
ALUSrc,
PC,
ReadData1,... | 8.359291 |
module RegEXMEM (
RegWrite_o,
MemToReg_o,
PCSrc,
MemRead_o,
MemWrite_o,
PC_o,
ALUResult_o,
ReadData2_o,
Instr_o,
CLK,
RegWrite,
MemToReg,
Branch,
MemRead,
MemWrite,
PC,
Zero,
ALUResult,
ReadData2,
Instr
);
// parameter N = 171; // 2+3+32+... | 7.961253 |
module RegMEMWB (
RegWrite_o,
MemToReg_o,
ALUResult_o,
ReadData_o,
Instr_o,
CLK,
RegWrite,
MemToReg,
ReadData,
ALUResult,
Instr
);
// parameter N = 135; // 2+64+64+5
// output reg [N-1:0] Q; // 输出Q
output reg RegWrite_o, MemToReg_o;
output reg [`DATA_WIDTH-1:0] ALURes... | 7.757398 |
module forwardunit (
RegWrite_MEM_WB,
RegWrite_EX_MEM,
RdAddr_MEM_WB,
RdAddr_EX_MEM,
RnAddr_ID_EX,
RmAddr_ID_EX,
ForwardA,
ForwardB
);
input RegWrite_EX_MEM, RegWrite_MEM_WB;
input [4:0] RdAddr_MEM_WB, RdAddr_EX_MEM, RnAddr_ID_EX, RmAddr_ID_EX;
output reg [1:0] ForwardA, ForwardB;... | 7.070833 |
module HazardDetectUnit (
MemRead_ID_EX,
RdAddr_ID_EX,
RnAddr_IF_ID,
RmAddr_IF_ID,
opcode,
PCWrite,
CUStall,
IF_IDWrite,
ifBranch,
resetEXMEM,
IF_ID_flush,
PCSrc
);
input [4:0] RdAddr_ID_EX, RnAddr_IF_ID, RmAddr_IF_ID;
input [10:0] opcode;
input MemRead_ID_EX, ifBra... | 7.610722 |
module CPU_ARM(
// input CLK, Reset,
// output [`ADDR_WIDTH-1:0] PC,
// input [`DATA_WIDTH-1:0] Instr, //指令
// output MemWrite, MemRead, //存储器写控制信号
// output [`ADDR_WIDTH-1:0] ALUOut, //ALU结果输出
// output [`DATA_WIDTH-1:0] WriteData, //数据写出
// input [`DATA_WIDTH-1:0] ReadData); //数据读入
// ... | 7.03022 |
module ARM_CPU_pipeline (
input CLK, //时钟信号
output wire [`DATA_WIDTH-1:0] WriteData, //数据写入
output [`DATA_WIDTH-1:0] DataAdr, //数据地址
output MemWrite,
MemRead
);
wire [`DATA_WIDTH-1:0] PC; //PC
wire [31:0] Instr; //指令
wire [`DATA_WIDTH-1:0] ReadData; //数据读出
reg [`DATA_WIDTH-1:0] PCreg,... | 6.854321 |
module CPU_ARM_IMem_DMem(
// input CLK, Reset, //时钟信号，复位信号
// output [`DATA_WIDTH-1:0] WriteData, //数据写出
// output [`DATA_WIDTH-1:0] DataAdr, //数据地址
// output MemWrite, MemRead);
// wire [`DATA_WIDTH-1:0] PC; //PC
// wire [`DATA_WIDTH-1:0] Instr; //指令
// wire [`DATA_WIDTH-1:0] ReadDa... | 6.569086 |
module is based on xge64_to_axi64 and has lesser
// functionality.
// Note that the block only works for padding 6 bytes.
//
/////////////////////////////////////////////////////////////////////
module arm_deframer (
// Clocks and Reset
input wire clk,
input wire reset,
input wire clear,
// Slave AXI Int... | 6.956676 |
module ARM_DP_tb;
reg clk;
reg rst_n;
ARM_DP uut (
.rst(rst_n),
.clk(clk)
);
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD / 2) clk = ~clk;
initial begin
#1 rst_n <= 1'bx;
clk <= 1'bx;
#(CLK_PERIOD * 3) rst_n <= 1;
#(CLK_PERIOD * 3) rst_n <= 0;
clk <= 0;
repeat (5... | 7.348153 |
module ARM_TB;
parameter clock_period = 10;
reg clk;
reg rst;
reg enableForwarding;
ARM_DP CPU (
.clk(clk),
.rst(rst)
);
initial begin
clk = 0;
forever clk = #clock_period ~clk;
end
initial begin
enableForwarding = 1;
rst = 1;
#(clock_period / 2);
rst = 0;
... | 7.078507 |
module ARM_TB;
parameter clock_period = 10;
reg clk;
reg rst;
reg enableForwarding;
ARM_DP CPU (
.clk(clk),
.rst(rst)
);
initial begin
clk = 0;
forever clk = #clock_period ~clk;
end
initial begin
enableForwarding = 1;
rst = 1;
#(clock_period / 2);
rst = 0;
... | 7.078507 |
module arm_write_ram (
input clk_50m,
input rst_n,
input WRn,
input CSn,
input [15:0] data,
input [25:0] addr,
input clk_25m, //write_ram读时钟
input arm_to_fpga,
output reg para_confi_acq_flag, //参数配置 应答标志 脉冲式信号
output reg data_upload_acq_flag, //数据上传打开关闭 应答标志 脉冲式信号
output... | 6.926003 |
module arpeggiator (
input wire CLK, // 50MHz input clock
output wire SPEAKER,
output wire [7:0] LED_G
);
reg [31:0] cnt = 0;
reg [31:0] switchcnt = 0;
reg LEDfreq1 = 1;
reg LEDfreq2 = 1;
wire [31:0] pitch = switchcnt < 10000000 ? `C3 / 2 : switchcnt < 20000000 ?
`D3
: switchcnt < 30000000 ... | 7.066251 |
module arp_recv (
input clk,
input reset,
input [7:0] arp_tdata_in,
input arp_tvalid_in,
input arp_tlast_in,
input [31:0] local_ip_addr,
input reply_ready_in,
output reg [31:0] remote_ip_addr_out,
output reg [47:0] remote_mac_addr_out,
// Send out the r... | 8.656462 |
module arp_server_ap_rst_if #(
parameter RESET_ACTIVE_LOW = 0
) (
input wire din,
output wire dout
);
assign dout = (RESET_ACTIVE_LOW == 1) ? ~din : din;
endmodule
| 8.673805 |
module arp_server_arpDataIn_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [63:0] TDATA,
input wire [ 7:0] TKEEP,
input wire [ 0:0] TLAST,
// User signals
output wire [63:0] arpD... | 7.632522 |
module arp_server_arpDataIn_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire write,... | 7.632522 |
module arp_server_arpDataIn_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0]... | 7.632522 |
module arp_server_arpDataOut_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [63:0] TDATA,
output wire [ 7:0] TKEEP,
output wire [ 0:0] TLAST,
// User signals
input wire [63:0] arp... | 7.632522 |
module arp_server_arpDataOut_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire write... | 7.632522 |
module arp_server_arpDataOut_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0... | 7.632522 |
module arp_server_macIpEncode_req_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [31:0] TDATA,
// User signals
output wire [31:0] macIpEncode_req_V_V_dout,
output wire macIpEnco... | 7.675029 |
module arp_server_macIpEncode_req_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire ... | 7.675029 |
module arp_server_macIpEncode_req_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [... | 7.675029 |
module arp_server_macIpEncode_rsp_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [55:0] TDATA,
// User signals
input wire [48:0] macIpEncode_rsp_V_din,
output wire macIpEncode_... | 7.675029 |
module arp_server_macIpEncode_rsp_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [... | 7.675029 |
module arp_server_macLookup_req_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [39:0] TDATA,
// User signals
input wire [32:0] macLookup_req_V_din,
output wire macLookup_req_V_... | 7.675029 |
module arp_server_macLookup_req_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-... | 7.675029 |
module arp_server_macLookup_resp_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [55:0] TDATA,
// User signals
output wire [48:0] macLookup_resp_V_dout,
output wire macLookup_res... | 7.675029 |
module arp_server_macLookup_resp_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N... | 7.675029 |
module arp_server_macUpdate_req_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [87:0] TDATA,
// User signals
input wire [81:0] macUpdate_req_V_din,
output wire macUpdate_req_V_... | 7.675029 |
module arp_server_macUpdate_req_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-... | 7.675029 |
module arp_server_macUpdate_resp_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [55:0] TDATA,
// User signals
output wire [49:0] macUpdate_resp_V_dout,
output wire macUpdate_res... | 7.675029 |
module arp_server_macUpdate_resp_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N... | 7.675029 |
module arp_table_arpTablbkb_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) ... | 8.342357 |
module arp_table_arpTablbkb (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0... | 8.342357 |
module arp_table_arpTablcud_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 48;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) ... | 8.342357 |
module arp_table_arpTablcud (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd48;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0... | 8.342357 |
module arp_table_arpTabldEe_ram (
addr0,
ce0,
d0,
we0,
clk
);
parameter DWIDTH = 1;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
... | 8.342357 |
module arp_table_arpTabldEe (
reset,
clk,
address0,
ce0,
we0,
d0
);
parameter DataWidth = 32'd1;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
... | 8.342357 |
module Arquitetura_buttons (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [1:0] in_port;
input reset_n;
wire clk_en;
wire [ 1:0] data_in;
wire [ 1:0] read_mux_out;
reg [31:0] rea... | 6.734548 |
module Arquitetura_dataA (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [31:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [... | 6.641472 |
module Arquitetura_data_A (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [31:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input ... | 6.641472 |
module Arquitetura_data_B (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [31:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input ... | 6.641472 |
module Arquitetura_isPrintting (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg [31:0] readd... | 6.849703 |
module Arquitetura_isPritting (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [4:0] in_port;
input reset_n;
wire clk_en;
wire [ 4:0] data_in;
wire [ 4:0] read_mux_out;
reg [31:0] ... | 6.849703 |
module Arquitetura_nios2_gen2_0_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
... | 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
... | 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)... | 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [16:0... | 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
);
output [1:0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_input_tm_cnt;
wire [2:0] s... | 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
);
output [3:0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [3:0] fifo_wrptr_inc;
always @(ge2_free or ge3_free... | 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
);
output [4:0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [4:0] fifo_cnt_inc;
always @(em... | 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_nios2_oci_pib (
// outputs:
tr_data
);
output [35:0] tr_data;
wire [35:0] tr_data;
assign tr_data = 0;
endmodule
| 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
);
output tracemem_on;
output [35:0] tracemem_trcdata;
output tracemem_tw;
... | 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_nios2_performance_monitors;
endmodule
| 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
... | 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input [7:0] address;
input [3:0] byteenable;
input clock;
input [31:0] data;
inp... | 6.913117 |
module Arquitetura_printting (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg [31:0] readdat... | 6.533684 |
module Arquitetura_screen (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg [31:0] readdata;
... | 6.997654 |
module Arquitetura_switch (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [2:0] in_port;
input reset_n;
wire clk_en;
wire [ 2:0] data_in;
wire [ 2:0] read_mux_out;
reg [31:0] read... | 6.997654 |
module Arquitetura_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1623240844 : 0;
endmodu... | 6.997654 |
module arrange_cell ( //output
arrange_out,
arrange_out_vld,
//input
stall_vld,
//halt,
cxd_c,
cxd_r,
cxd_vld_c,
cxd_vld_l,
cxd_vld_r,
clk_dwt,
pos_clk_bpc,
rst,
rst_syn
);
output [7:0] arrange_out;
output arrange_out_vld;
input stall_vld;
input [7:0] c... | 6.841236 |
module and1 (
input x,
input y,
output wire w
);
assign w = x * y;
endmodule
| 6.846927 |
module ha (
input e,
input f,
output wire g,
output wire h
);
assign g = e ^ f;
assign h = e * f;
endmodule
| 7.857591 |
module fa (
input j,
input k,
input l,
output wire m,
output wire n
);
assign m = j ^ k ^ l;
assign n = (j * k) + (k * l) + (j * l);
endmodule
| 7.001699 |
module common_2i1 (
i0,
i1,
o,
s
);
parameter WIDTH = 281 * 2;
input [WIDTH - 1:0] i0, i1;
output [WIDTH - 1:0] o;
input s;
reg [WIDTH - 1:0] o;
always @(*)
case (s)
'b1: o = i1;
`ifdef SIM
'bz,'bx:o = {WIDTH{1'bx}};
`endif
default:o = i0;
endcase
endmodule
| 7.166385 |
module common_1o2 (
i,
o1,
o0
);
parameter WIDTH = 281 * 2;
input [WIDTH - 1:0] i;
output [WIDTH - 1:0] o0, o1;
assign o0 = i;
assign o1 = i;
endmodule
| 7.109382 |
module array4c (
Z2,
X,
Y
);
input [3:0] Y;
input [3:0] X;
output [3:0] Z2;
wire [3:0] P0;
wire [3:0] carry1;
wire [3:0] sum1;
wire [3:0] P1;
wire [3:0] carry2;
wire [3:0] sum2;
wire [3:0] P2;
wire [3:0] carry3;
wire [3:0] sum3;
wire [3:0] P3;
wire [3:0] carry4;
wire [3:0] s... | 7.858865 |
module array4h (
Z,
X,
Y
);
input [3:0] Y;
input [3:0] X;
output [3:0] Z;
wire [3:0] P0;
wire [3:0] carry1;
wire [3:0] sum1;
wire [3:0] P1;
wire [3:0] carry2;
wire [3:0] sum2;
wire [3:0] P2;
wire [3:0] carry3;
wire [3:0] sum3;
wire [3:0] P3;
wire [3:0] carry4;
wire [3:0] sum... | 7.22926 |
module array4tc (
Z,
X,
Y
);
input [3:0] Y;
input [3:0] X;
output [7:0] Z;
wire [3:0] P0;
wire [3:0] carry1;
wire [3:0] sum1;
wire [3:0] P1;
wire [3:0] carry2;
wire [3:0] sum2;
wire [3:0] P2;
wire [3:0] carry3;
wire [3:0] sum3;
wire [3:0] P3;
wire [3:0] carry4;
wire [3:0] su... | 7.117492 |
module array4v (
Z,
X,
Y
);
input [3:0] Y;
input [3:0] X;
output [3:0] Z;
wire [3:0] P0;
wire [3:0] carry1;
wire [3:0] sum1;
wire [3:0] P1;
wire [3:0] carry2;
wire [3:0] sum2;
wire [3:0] P2;
wire [3:0] carry3;
wire [3:0] sum3;
wire [3:0] P3;
wire [3:0] carry4;
wire [3:0] sum... | 7.440355 |
module aoi12 (
a,
b,
c,
y
);
input a, b, c;
output y;
assign y = ~((a & b) | c);
endmodule
| 8.423832 |
module FACell (
output Cnext,
Sthis,
input xn,
am,
Cthis
);
wire t1, t2, t3;
xor (t1, am, xn);
and (t2, t1, Cthis);
and (t3, am, xn);
or (Cnext, t2, t3);
xor (Sthis, t1, Cthis);
endmodule
| 7.106661 |
module ArrayMultiplier (
product,
a,
x
);
parameter m = 4;
parameter n = 4;
output [m+n-1:0] product;
input [m-1:0] a;
input [n-1:0] x;
wire c_partial[m*n:0];
wire s_partial[m*n:0];
// first line of the multiplier
genvar i;
generate
for (i = 0; i < m; i = i + 1) begin
Cell c... | 6.87285 |
module top;
wire [31:0] p;
reg [15:0] a;
reg [15:0] x;
ArrayMultiplier #(
.m(16),
.n(16)
) am (
p,
a,
x
);
initial $monitor("a=%b,x=%b,p=%b", a, x, p);
initial begin
a = 16'b110111;
x = 16'b11111;
end
endmodule
| 6.919222 |
module array_ctrl (
input clk,
input bottom,
input [5:0] vga_x,
input reset,
input key_en,
input [7:0] key_data,
input [7:0] ran_data,
input [5:0] ran_x,
output [7:0] v_ascii,
output pause,
output reg [3:0] score_l,
output reg [3:0] score_h,
output [9:0] LEDR,
out... | 7.073986 |
module Array_Mult_Dataflow (
a,
b,
out
);
input [1:0] a, b;
output [3:0] out;
assign out[0] = a[0] & b[0];
assign out[1] = (a[0] & b[1]) ^ (a[1] & b[0]);
assign out[2] = (a[1] & b[1]) ^ ((a[0] & b[1]) & (a[1] & b[0]));
assign out[3] = (a[1] & b[1]) & ((a[0] & b[1]) & (a[1] & b[0]));
endmodule
| 7.730166 |
module array_key (
input wire clk,
input wire rst_n,
input wire [3:0] row,
output wire [3:0] col,
output wire [2:0] addr,
output wire [7:0] seg_n
);
wire clk_20K;
wire [4:0] key_val;
clk_div clk_div_inst (
.clk (clk),
.rst_n (rst_n),
.clk_20K (clk_20K)
);
... | 7.343763 |
module Array_KeyBoard #(
parameter NUM_FOR_200HZ = 60000
) (
input clk_in,
input rst_n_in,
input [3:0] col,
output reg [3:0] row,
output reg [15:0] key_out,
output [15:0] key_pulse
);
localparam STATE0 = 2'b00;
localparam STATE1 = 2'b01;
localparam STATE2 = 2'b10;
localparam... | 6.912891 |
module FACell (
output Cnext,
Sthis,
input xn,
am,
Cthis
);
wire t1, t2, t3;
xor (t1, am, xn);
and (t2, t1, Cthis);
and (t3, am, xn);
or (Cnext, t2, t3);
xor (Sthis, t1, Cthis);
endmodule
| 7.106661 |
module ArrayMultiplier (
product,
a,
x
);
parameter m = 32;
parameter n = 32;
output [m+n-1:0] product;
input [m-1:0] a;
input [n-1:0] x;
wire c_partial[m*n:0];
wire s_partial[m*n:0];
// first line of the multiplier
genvar i;
generate
for (i = 0; i < m; i = i + 1) begin
Cell... | 6.87285 |
module ADD_HALF (
output cout,
output sum,
input a,
input b
);
xor (sum, a, b);
and (cout, a, b);
endmodule
| 7.323935 |
module FACell (
output Cnext,
Sthis,
input xn,
am,
Cthis
);
wire t1, t2, t3;
xor (t1, am, xn);
and (t2, t1, Cthis);
and (t3, am, xn);
or (Cnext, t2, t3);
xor (Sthis, t1, Cthis);
endmodule
| 7.106661 |
module ArrayMultiplier (
clk,
product_reg,
a,
x
);
parameter m = 24;
parameter n = 24;
output reg [m+n-1:0] product_reg;
wire [m+n-1:0] product;
input [m-1:0] a;
input [n-1:0] x;
input clk;
wire [m*n:0] c_partial;
wire [m*n:0] s_partial;
// first line of the multiplier
genvar i;... | 6.87285 |
module array_multiplier_4_bits (
input [7:0] SW,
//a 0-3 b 4-7
output [7:0] LEDR,
output [0:6] HEX0,
HEX2,
HEX4,
HEX5
);
wire [39:0] w;
and a1 (w[0], SW[0], SW[4]);
and a2 (w[1], SW[1], SW[4]);
and a3 (w[2], SW[2], SW[4]);
and a4 (w[3], SW[3], SW[4]);
and a5 (w[4], SW[0], S... | 6.678924 |
module fulladder (
input a,
b,
c,
output s,
ca
);
assign s = (a ^ b ^ c);
assign ca = ((a & b) | (b & c) | (c & a));
endmodule
| 7.454465 |
module array_multiplier_4_bits_board (
input [7:0] SW,
output [7:0] LEDR,
output [6:0] HEX0,
HEX2,
HEX4,
HEX5
);
assign LEDR = SW;
wire [7:0] out;
array_multiplier_4_bits(
SW[7:4], SW[3:0], out
);
decoder_hex_16 A (
SW[7:4],
HEX2
);
decoder_hex_16 B (
S... | 6.678924 |
module array_multiplier_gen (
a,
b,
p
);
// inputs
input [3:0] a;
input [3:0] b;
// outputs
output [7:0] p;
wire [7:0] temp_and0;
wire [7:0] temp_and1;
wire [7:0] temp_and2;
wire [7:0] temp_and3;
// ---------------------- design implementation ------------------------------
// pro... | 6.678924 |
module Add_full_0 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_0 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1791 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X2 U1 (... | 6.995469 |
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