code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Adder (
input wire [`DATA_WIDTH-1:0] Op1,
Op2,
output wire [`DATA_WIDTH-1:0] Out
);
assign Out = Op1 + Op2;
endmodule
| 7.642138 |
module Mux2 //2选1
#(
parameter WIDTH = 8
) (
input [WIDTH-1:0] d0,
d1,
input select,
output [WIDTH-1:0] y
);
assign y = select ? d1 : d0;
endmodule
| 8.98768 |
module Mux4 //4选1
#(
parameter WIDTH = 8
) (
input [WIDTH-1:0] d0,
d1,
d2,
d3,
input [1:0] select,
output reg [WIDTH-1:0] y
);
always @(*) begin
case ({
select[1], select[0]
})
2'b00: y = d0;
2'b01: y = d1;
2'b10: y = d2;
2'b11: y = d3;
default: y = 2'bz;
endcase
end
//assign y = select ? d1 : d0;
endmodule
| 8.692438 |
module DMem (
Data_Write,
Data_Out,
Addr,
MemWrite,
MemRead,
CLK
);
parameter Addr_Width = 12; //参数化地址线宽
parameter Data_Width = `DATA_WIDTH; //参数化数据线宽
parameter SIZE = 2 ** Addr_Width; //参数化大小4K
input [Data_Width-1:0] Data_Write; // 写入的数据
output [Data_Width-1:0] Data_Out; // 读出的数据
input [`DATA_WIDTH-1:0] Addr; //地址
input MemWrite, MemRead;
//input Rst; //复位信号
//input R_W; //1读_0写信号
//input CS; //使能片选信号
input CLK; //时钟信号
reg [Data_Width-1:0] Data_Outtmp;
assign Data_Out = Data_Outtmp;
integer i; //临时变量。用于for循环
reg [Data_Width-1:0] RAM[SIZE-1:0]; //4096*32的RAM
initial begin
for (i = 0; i <= SIZE - 1; i = i + 1) RAM[i] = 64'h1111_1111_1111_1111; // 初始化
end
assign Data_Out = (MemRead) ? RAM[Addr] : 64'bz;
//assign Data = (R_W) ? Data_i:32'bz; //z是高阻态，表示32位二进制高阻态
always @(posedge CLK) begin //时钟同步
case ({
MemWrite, MemRead
})
//4'b01 : Data_Outtmp <= RAM[Addr]; //读数据
4'b10: RAM[Addr] <= Data_Write; //写数据
default: Data_Outtmp <= 64'bz; // 32
endcase
end
endmodule
| 8.99805 |
module IMem (
input [63:0] A, // 地址(PC)64位
output [31:0] RD
); // 指令32位
parameter IMEM_SIZE = 512; // 最多512条指令
//指令寄存器
reg [31:0] RAM[IMEM_SIZE-1:0];
initial begin
$readmemh("/home/jinstorm/IMem.txt", RAM);
end
assign RD = RAM[A>>2]; //指令输出
endmodule
| 7.299969 |
module MainDec ( //主译码器
input [10:0] Op,
output MemToReg,
MemWrite,
MemRead,
output Branch,
ALUSrc,
output Reg2Loc,
RegWrite,
//output Jump,
output [1:0] ALUOp
);
//MainDec MainDec_1(Opcode, MemToReg, MemWrite, MemRead, Branch, ALUSrc, Reg2Loc, RegWrite, ALUOp);
reg [8:0] Controls;
assign {Reg2Loc, ALUSrc, MemToReg, RegWrite, MemRead, MemWrite, Branch, ALUOp} = Controls;
always @(*)
casex (Op)
11'b10001010000: Controls <= 9'b000100010; //R-format //b10001010000 AND
11'b10001011000: Controls <= 9'b000100010; //R-format //b10001010000 ADD
11'b11001011000: Controls <= 9'b000100010; //R-format SUB
11'b11111000010: Controls <= 9'bx11110000; //LDUR
11'b11111000000: Controls <= 9'b11x001000; //STUR
11'b10110100xxx: Controls <= 9'b100000101; //CBZ (Branch == 1 & Zero == 1)
11'b000101xxxxx: Controls <= 9'b100000110; //B
default: Controls <= 9'bzzzzzzzzz;
endcase
endmodule
| 6.533465 |
module ALU (
F,
A,
B,
OP,
Zero
);
parameter SIZE = `DATA_WIDTH; //运算位数
input [3:0] OP; //运算操作
input [SIZE-1:0] A; //左运算数
input [SIZE-1:0] B; //右运算数
//input CLK;
output [SIZE-1:0] F; //运算结果
//output CF; //进借位标志位
output reg Zero; //0标志位
reg [SIZE-1:0] F;
reg C; //, CF;
parameter ALU_AND = 4'b0000; //opcode:10001010000
parameter ALU_OR = 4'b0001; //opcode:10101010000
parameter ALU_ADD = 4'b0010; //opcode:10001011000 xxxxxxxxxxx
parameter ALU_SUB = 4'b0110; //opcode:11001011000
parameter ALU_PASSB = 4'b0111; //opcode:xxxxxxxxxxx
parameter ALU_Zero = 4'b1110;
parameter ALU_NOR = 4'b1100; //opcode:
always @(*) begin
C = 0;
case (OP)
ALU_AND: begin
F = A & B;
end // 按位与
ALU_OR: begin
F = A | B;
end // 按位或
ALU_ADD: begin
{C, F} = A + B;
end // 加法
ALU_SUB: begin
F = A - B;
end // 减法
ALU_PASSB: begin
F = B;
end // F = B
ALU_Zero: begin
F = 64'h0000_0000_0000_0000;
Zero = 1;
end
ALU_NOR: begin
F = ~(A | B);
end // 按位或非
default: begin
F = 64'bz;
end
endcase
if (F == 64'h0000_0000_0000_0000) Zero <= 1; // 32
else Zero <= 0;
end
endmodule
| 7.043664 |
module register(Q, D, OE, CLK);
// parameter N = 8;
// output reg [N-1:0] Q; // 输出Q
// input [N:1] D;
// input OE, CLK; //三态输出
// //CLK，OE边沿敏感触发
// always @ (posedge CLK or posedge OE)
// if (OE) Q <= 8'bzzzz_zzzz; // 使能无效输出高阻态
// else Q <= D; //存入和读出数据
// endmodule
| 7.419465 |
module RegIFID (
Q,
D,
IF_ID_Write,
IF_ID_flush,
CLK
);
parameter N = 96; // 64PC+32指令
output reg [N-1:0] Q; // 输出Q(96)
input [N-1:0] D; // 输入
input IF_ID_Write, IF_ID_flush;
input CLK;
//CLK边沿敏感触发
always @(posedge CLK) begin
//if (OE) Q <= 8'bzzzz_zzzz; // 使能无效输出高阻态
//else Q <= D; //存入和读出数据
if (IF_ID_Write) Q <= D; //写入
if (IF_ID_flush) Q <= 96'b0; //清空
end
endmodule
| 7.002608 |
module RegIDEX (
RegWrite_o,
MemToReg_o,
Branch_o,
MemRead_o,
MemWrite_o,
ALUControl_o,
ALUSrc_o,
PC_o,
ReadData1_o,
ReadData2_o,
Sig_o,
Instr_o,
CLK,
RegWrite,
MemToReg,
Branch,
MemRead,
MemWrite,
ALUControl,
ALUSrc,
PC,
ReadData1,
ReadData2,
Sigimm,
Instr
);
// parameter N = 239; // 2+3+5+32+64+64+64+5
// output reg [N-1:0] Q; // 输出Q()
output reg RegWrite_o, MemToReg_o, Branch_o, MemRead_o, MemWrite_o, ALUSrc_o;
output reg [3:0] ALUControl_o;
output reg [`DATA_WIDTH-1:0] PC_o;
output reg [`DATA_WIDTH-1:0] ReadData1_o, ReadData2_o;
output reg [`DATA_WIDTH-1:0] Instr_o, Sig_o;
input CLK;
input RegWrite, MemToReg, Branch, MemRead, MemWrite, ALUSrc;
input [3:0] ALUControl;
input [`DATA_WIDTH-1:0] PC;
input [`DATA_WIDTH-1:0] ReadData1, ReadData2;
input [`DATA_WIDTH-1:0] Instr, Sigimm;
//wire [N-1:0] TmpQ;
//CLK边沿敏感触发
always @(posedge CLK) begin
RegWrite_o <= RegWrite;
MemToReg_o <= MemToReg;
Branch_o <= Branch;
MemRead_o <= MemRead;
MemWrite_o <= MemWrite;
ALUControl_o <= ALUControl;
ALUSrc_o <= ALUSrc;
PC_o <= PC;
ReadData1_o <= ReadData1;
ReadData2_o <= ReadData2;
Sig_o <= Sigimm;
Instr_o <= Instr;
end
//Q <= TmpQ;
//assign TmpQ = {RegWrite, MemToReg, Branch, MemRead, MemWrite, ALUControl, ALUSrc, PC, ReadData1, ReadData2, Instr};
endmodule
| 8.359291 |
module RegEXMEM (
RegWrite_o,
MemToReg_o,
PCSrc,
MemRead_o,
MemWrite_o,
PC_o,
ALUResult_o,
ReadData2_o,
Instr_o,
CLK,
RegWrite,
MemToReg,
Branch,
MemRead,
MemWrite,
PC,
Zero,
ALUResult,
ReadData2,
Instr
);
// parameter N = 171; // 2+3+32+1+64+64+5
// output reg [N-1:0] Q; // 输出Q
output reg RegWrite_o, MemToReg_o, PCSrc, MemRead_o, MemWrite_o; //, Zero_o;
output reg [`DATA_WIDTH-1:0] PC_o;
output reg [`DATA_WIDTH-1:0] ALUResult_o, ReadData2_o;
output reg [4:0] Instr_o;
input CLK;
input RegWrite, MemToReg, Branch, MemRead, MemWrite, Zero;
input [`DATA_WIDTH-1:0] PC;
input [`DATA_WIDTH-1:0] ALUResult, ReadData2;
input [4:0] Instr;
initial begin
PCSrc = 0;
end
//wire [N-1:0] TmpQ;
//CLK边沿敏感触发
always @(posedge CLK) begin
RegWrite_o <= RegWrite;
MemToReg_o <= MemToReg;
//Branch_o <= Branch;
if ((Branch & Zero) == 1'b1) PCSrc <= Branch & Zero;
else PCSrc <= 0;
MemRead_o <= MemRead;
MemWrite_o <= MemWrite;
//Zero_o <= Zero;
PC_o <= PC;
ALUResult_o <= ALUResult;
ReadData2_o <= ReadData2;
Instr_o <= Instr;
end
//Q <= TmpQ;
//assign TmpQ = {RegWrite, MemToReg, Branch, MemRead, MemWrite, PC, Zero, ALUResult, ReadData2, Instr};
endmodule
| 7.961253 |
module RegMEMWB (
RegWrite_o,
MemToReg_o,
ALUResult_o,
ReadData_o,
Instr_o,
CLK,
RegWrite,
MemToReg,
ReadData,
ALUResult,
Instr
);
// parameter N = 135; // 2+64+64+5
// output reg [N-1:0] Q; // 输出Q
output reg RegWrite_o, MemToReg_o;
output reg [`DATA_WIDTH-1:0] ALUResult_o, ReadData_o;
output reg [4:0] Instr_o;
input CLK;
input RegWrite, MemToReg;
input [`DATA_WIDTH-1:0] ALUResult, ReadData;
input [4:0] Instr;
//wire [N-1:0] TmpQ;
//CLK边沿敏感触发
always @(posedge CLK) begin
RegWrite_o <= RegWrite;
MemToReg_o <= MemToReg;
ALUResult_o <= ALUResult;
ReadData_o <= ReadData;
Instr_o <= Instr;
end
//Q <= TmpQ;
//assign TmpQ = {RegWrite, MemToReg, ReadData, ALUResult, Instr};
endmodule
| 7.757398 |
module forwardunit (
RegWrite_MEM_WB,
RegWrite_EX_MEM,
RdAddr_MEM_WB,
RdAddr_EX_MEM,
RnAddr_ID_EX,
RmAddr_ID_EX,
ForwardA,
ForwardB
);
input RegWrite_EX_MEM, RegWrite_MEM_WB;
input [4:0] RdAddr_MEM_WB, RdAddr_EX_MEM, RnAddr_ID_EX, RmAddr_ID_EX;
output reg [1:0] ForwardA, ForwardB;
initial begin
ForwardA <= 2'b00;
ForwardB <= 2'b00;
end
always @(*) begin
ForwardA = 2'b00;
ForwardB = 2'b00;
//EX HAZARD
if (RegWrite_EX_MEM && (RdAddr_EX_MEM != 31) && (RdAddr_EX_MEM == RnAddr_ID_EX))
ForwardA = 2'b10;
if (RegWrite_EX_MEM && (RdAddr_EX_MEM != 31) && (RdAddr_EX_MEM == RmAddr_ID_EX))
ForwardB = 2'b10;
//MEM HAZARD
if(RegWrite_MEM_WB
&& (RdAddr_MEM_WB != 31)
&& !(RegWrite_EX_MEM && (RdAddr_EX_MEM != 31)
&& (RdAddr_EX_MEM != RnAddr_ID_EX))
&& (RdAddr_MEM_WB == RnAddr_ID_EX))
ForwardA = 2'b01;
if(RegWrite_MEM_WB
&& (RdAddr_MEM_WB != 31)
&& !(RegWrite_EX_MEM && (RdAddr_EX_MEM != 31)
&& (RdAddr_EX_MEM != RmAddr_ID_EX))
&& (RdAddr_MEM_WB == RmAddr_ID_EX))
ForwardB = 2'b01;
end
endmodule
| 7.070833 |
module HazardDetectUnit (
MemRead_ID_EX,
RdAddr_ID_EX,
RnAddr_IF_ID,
RmAddr_IF_ID,
opcode,
PCWrite,
CUStall,
IF_IDWrite,
ifBranch,
resetEXMEM,
IF_ID_flush,
PCSrc
);
input [4:0] RdAddr_ID_EX, RnAddr_IF_ID, RmAddr_IF_ID;
input [10:0] opcode;
input MemRead_ID_EX, ifBranch;
output reg PCWrite, CUStall, IF_IDWrite, resetEXMEM, IF_ID_flush, PCSrc;
initial begin
PCWrite <= 1;
CUStall <= 0;
IF_IDWrite <= 1;
resetEXMEM <= 0;
IF_ID_flush <= 0;
PCSrc <= 0;
end
always @(*) begin
PCWrite = 1;
CUStall = 0;
IF_IDWrite = 1;
resetEXMEM = 0;
IF_ID_flush = 0;
PCSrc = 0;
if (MemRead_ID_EX
&& (opcode != 1986)
&& ((RdAddr_ID_EX == RnAddr_IF_ID)
|| (RdAddr_ID_EX == RmAddr_IF_ID))) begin
$display(RdAddr_ID_EX, RmAddr_IF_ID);
PCWrite <= 0;
CUStall <= 1;
IF_IDWrite <= 0;
end
if (ifBranch) begin
resetEXMEM <= 1;
CUStall <= 1;
IF_ID_flush <= 1;
PCSrc <= 1;
end
end
endmodule
| 7.610722 |
module CPU_ARM(
// input CLK, Reset,
// output [`ADDR_WIDTH-1:0] PC,
// input [`DATA_WIDTH-1:0] Instr, //指令
// output MemWrite, MemRead, //存储器写控制信号
// output [`ADDR_WIDTH-1:0] ALUOut, //ALU结果输出
// output [`DATA_WIDTH-1:0] WriteData, //数据写出
// input [`DATA_WIDTH-1:0] ReadData); //数据读入
// wire MemToReg, ALUSrc, Reg2Loc, RegWrite, PCSrc, Zero;
// wire [2:0] ALUControl;
// //控制器
// // Opcode, Zero, MemToReg, MemWrite, MemRead, PCSrc, ALUSrc, Reg2Loc, RegWrite, ALUControl
// Controller Controller_1(Instr[31:21], Zero, MemToReg, MemWrite, MemRead, PCSrc, ALUSrc, Reg2Loc, RegWrite, ALUControl);
// //数据通路
// // CLK, MemToReg, PCSrc, ALUSrc, Reg2Loc, RegWrite, ALUControl, Zero, PC, Instr, ALUOut, WriteData, ReadData
// DataPath DataPath_1(CLK, MemToReg, PCSrc, ALUSrc, Reg2Loc, RegWrite, ALUControl, Zero, PC, Instr, ALUOut, WriteData, ReadData);
// endmodule
| 7.03022 |
module ARM_CPU_pipeline (
input CLK, //时钟信号
output wire [`DATA_WIDTH-1:0] WriteData, //数据写入
output [`DATA_WIDTH-1:0] DataAdr, //数据地址
output MemWrite,
MemRead
);
wire [`DATA_WIDTH-1:0] PC; //PC
wire [31:0] Instr; //指令
wire [`DATA_WIDTH-1:0] ReadData; //数据读出
reg [`DATA_WIDTH-1:0] PCreg, PCreg2;
initial begin
PCreg <= 64'b0;
end
//assign PC = PCreg;
//assign PCtmp = PC;
//实例化存储器和存储器
//DataPath DataPath_1(CLK, MemToReg, PCSrc, ALUSrc, Reg2Loc, RegWrite, ALUControl, Zero, PC, Instr, ALUOut, WriteData, ReadData);
//DataPath(CLK, Instr, ReadData, PC, ALUResult_o, ReadData2_o, MemRead_o2, MemWrite_o2)
DataPath DataPath_1 (
CLK,
Instr,
ReadData,
PC,
DataAdr,
WriteData,
MemRead,
MemWrite
);
IMem IMem_1 (
PC,
Instr
);
DMem DMem_1 (
WriteData,
ReadData,
DataAdr,
MemWrite,
MemRead,
CLK
);
// DMem(Data_Write, Data_Out, Addr, MemWrite, MemRead, CLK);
endmodule
| 6.854321 |
module CPU_ARM_IMem_DMem(
// input CLK, Reset, //时钟信号，复位信号
// output [`DATA_WIDTH-1:0] WriteData, //数据写出
// output [`DATA_WIDTH-1:0] DataAdr, //数据地址
// output MemWrite, MemRead);
// wire [`DATA_WIDTH-1:0] PC; //PC
// wire [`DATA_WIDTH-1:0] Instr; //指令
// wire [`DATA_WIDTH-1:0] ReadData; //数据读入
// //实例化存储器和存储器
// CPU_ARM CPU_ARM_1(CLK, Reset, PC, Instr, MemWrite, MemRead, DataAdr, WriteData, ReadData);
// IMem IMem_1(PC, Instr);
// DMem DMem_1(WriteData, ReadData, DataAdr, MemWrite, MemRead, CLK);
// //DMem: Data_Write, Data_Out, Addr, MemWrite, MemRead, CLK
// endmodule
| 6.569086 |
module is based on xge64_to_axi64 and has lesser
// functionality.
// Note that the block only works for padding 6 bytes.
//
/////////////////////////////////////////////////////////////////////
module arm_deframer (
// Clocks and Reset
input wire clk,
input wire reset,
input wire clear,
// Slave AXI Interface
input wire [63:0] s_axis_tdata,
input wire [3:0] s_axis_tuser, //used as tkeep here
input wire s_axis_tlast,
input wire s_axis_tvalid,
output reg s_axis_tready,
// Master AXI Interface
output reg [63:0] m_axis_tdata,
output reg [3:0] m_axis_tuser, //used as tkeep here
output reg m_axis_tlast,
output reg m_axis_tvalid,
input wire m_axis_tready
);
// State Machine States
localparam START = 2'b00;
localparam BODY = 2'b01;
localparam EXTRA = 2'b10;
localparam PAD_BYTES = 3'b110; //6 bytes
wire new_line;
wire valid_beat;
reg [1:0] state = 2'b00, next_state=2'b00;
reg [47:0] holding_reg;
reg [2:0] holding_user;
// New line will be created by padding 6 bytes if the valid bytes on the
// last line are greater than 2 bytes(3 to 7 bytes) or all 8 bytes are valid.
assign new_line = (s_axis_tuser[2:0] > 3'b010) || (s_axis_tuser[2:0] == 3'b000);
assign valid_beat = s_axis_tvalid & m_axis_tready;
always @(posedge clk) begin
if (reset | clear) begin
state <= START;
end else begin
state <=next_state;
end
end
// holding last 48 bits from input tdata on every valid_beat.
always @(posedge clk)begin
if (s_axis_tvalid & s_axis_tready) begin
// Register the last 6 bytes of data for one cycle
holding_reg <= s_axis_tdata[63:16];
// Register the tuser in case there is a new line
// tuser should be valid for one extra cycle in that case
holding_user <= s_axis_tuser[2:0];
end
end
// Outputs
always @(*) begin
m_axis_tdata = 64'b0;
m_axis_tvalid = 1'b0;
m_axis_tlast = 1'b0;
m_axis_tuser = 4'b0;
s_axis_tready = 1'b1;
case (state)
START : begin
// Pad with 6 bytes of Zeros at the beginning of the packet
// Shift the first 2 bytes to the end
m_axis_tdata = {s_axis_tdata[15:0], 48'b0};
m_axis_tvalid = s_axis_tvalid;
m_axis_tlast = s_axis_tlast;
m_axis_tuser = 4'b0;
s_axis_tready = m_axis_tready;
if(valid_beat) next_state = BODY;
else next_state = START;
end
BODY : begin
// Shift the remaining packet by 6 bytes.
// Here we're using register version of data and tvalid.
m_axis_tdata = {s_axis_tdata[15:0], holding_reg};
m_axis_tvalid = s_axis_tvalid;
m_axis_tlast = new_line? 1'b0: s_axis_tvalid & s_axis_tlast;
// Modify the tuser according to the new packet i.e. add 6 to it.
m_axis_tuser = (new_line & s_axis_tlast) ? 4'b0: {1'b0, s_axis_tuser[2:0] + PAD_BYTES};
s_axis_tready = m_axis_tready;
if (valid_beat & s_axis_tlast) next_state = new_line ? EXTRA : START;
else next_state = BODY;
end
EXTRA : begin
m_axis_tdata = {16'b0, holding_reg};
m_axis_tvalid = 1'b1;
m_axis_tlast = 1'b1;
// Modify the tuser according to the new shifted packet i.e. add 6 to it.
m_axis_tuser = {1'b0, holding_user + PAD_BYTES};
// We need to hold off any comming upstream data i.e not ready until
// downstream done consuming this data
s_axis_tready = 1'b0;
if (m_axis_tready) next_state = START;
else next_state = EXTRA;
end
default : begin
m_axis_tdata = 64'b0;
m_axis_tvalid = 1'b0;
m_axis_tlast = 1'b0;
m_axis_tuser = 4'b0;
s_axis_tready = 1'b1;
next_state = START;
end
endcase
end
endmodule
| 6.956676 |
module ARM_DP_tb;
reg clk;
reg rst_n;
ARM_DP uut (
.rst(rst_n),
.clk(clk)
);
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD / 2) clk = ~clk;
initial begin
#1 rst_n <= 1'bx;
clk <= 1'bx;
#(CLK_PERIOD * 3) rst_n <= 1;
#(CLK_PERIOD * 3) rst_n <= 0;
clk <= 0;
repeat (5) @(posedge clk);
@(posedge clk);
repeat (2) @(posedge clk);
#1000 $stop;
end
endmodule
| 7.348153 |
module ARM_TB;
parameter clock_period = 10;
reg clk;
reg rst;
reg enableForwarding;
ARM_DP CPU (
.clk(clk),
.rst(rst)
);
initial begin
clk = 0;
forever clk = #clock_period ~clk;
end
initial begin
enableForwarding = 1;
rst = 1;
#(clock_period / 2);
rst = 0;
#(1000 * clock_period);
$stop;
end
endmodule
| 7.078507 |
module ARM_TB;
parameter clock_period = 10;
reg clk;
reg rst;
reg enableForwarding;
ARM_DP CPU (
.clk(clk),
.rst(rst)
);
initial begin
clk = 0;
forever clk = #clock_period ~clk;
end
initial begin
enableForwarding = 1;
rst = 1;
#(clock_period / 2);
rst = 0;
#(1000 * clock_period);
$stop;
end
endmodule
| 7.078507 |
module arm_write_ram (
input clk_50m,
input rst_n,
input WRn,
input CSn,
input [15:0] data,
input [25:0] addr,
input clk_25m, //write_ram读时钟
input arm_to_fpga,
output reg para_confi_acq_flag, //参数配置 应答标志 脉冲式信号
output reg data_upload_acq_flag, //数据上传打开关闭 应答标志 脉冲式信号
output reg [127:0] data_buffer /*synthesis noprune*/
);
wire wr = (CSn | WRn);
reg wr_clk;
always @(posedge clk_50m or negedge rst_n) begin
if (!rst_n) wr_clk <= 1'b1;
else wr_clk <= wr;
end
wire [15:0] q;
reg [ 4:0] rdaddr;
write_ram U1 (
.data(data),
.rdaddress(rdaddr),
.rdclock(clk_25m),
.wraddress(addr[4:0]),
.wrclock(!wr_clk),
.wren(!wr),
.q(q)
);
/******判断arm_to_fpga下降沿，读出write_ram数据，判断帧头做出相应应答********/
reg arm_to_fpga_reg;
reg arm_to_fpga_fall;
always @(posedge clk_25m) begin
arm_to_fpga_reg <= arm_to_fpga;
arm_to_fpga_fall <= arm_to_fpga_reg & (!arm_to_fpga);
end
reg [3:0] state;
reg [2:0] delay;
parameter idle=4'd0,read0=4'd1,read1=4'd2,read2=4'd3,read3=4'd4,
read4=4'd5,read5=4'd6,read6=4'd7,read7=4'd8,reco=4'd9;
always @(posedge clk_25m or negedge rst_n) begin
if (!rst_n) begin
state <= idle;
delay <= 3'd0;
para_confi_acq_flag <= 1'b0;
data_upload_acq_flag <= 1'b0;
end else
case (state)
idle: begin
para_confi_acq_flag <= 1'b0;
data_upload_acq_flag <= 1'b0;
if (arm_to_fpga_fall) state <= read0;
else state <= idle;
end
read0: begin
rdaddr <= 5'd0;
if (delay == 3'd4) begin
state <= read1;
delay <= 3'd0;
data_buffer[127:112] <= q;
end else delay <= delay + 1'b1;
end
read1: begin
rdaddr <= 5'd1;
if (delay == 3'd4) begin
state <= read2;
delay <= 3'd0;
data_buffer[111:96] <= q;
end else delay <= delay + 1'b1;
end
read2: begin
rdaddr <= 5'd2;
if (delay == 3'd4) begin
state <= read3;
delay <= 3'd0;
data_buffer[95:80] <= q;
end else delay <= delay + 1'b1;
end
read3: begin
rdaddr <= 5'd3;
if (delay == 3'd4) begin
state <= read4;
delay <= 3'd0;
data_buffer[79:64] <= q;
end else delay <= delay + 1'b1;
end
read4: begin
rdaddr <= 5'd4;
if (delay == 3'd4) begin
state <= read5;
delay <= 3'd0;
data_buffer[63:48] <= q;
end else delay <= delay + 1'b1;
end
read5: begin
rdaddr <= 5'd5;
if (delay == 3'd4) begin
state <= read6;
delay <= 3'd0;
data_buffer[47:32] <= q;
end else delay <= delay + 1'b1;
end
read6: begin
rdaddr <= 5'd6;
if (delay == 3'd4) begin
state <= read7;
delay <= 3'd0;
data_buffer[31:16] <= q;
end else delay <= delay + 1'b1;
end
read7: begin
rdaddr <= 5'd7;
if (delay == 3'd4) begin
state <= reco;
delay <= 3'd0;
data_buffer[15:0] <= q;
end else delay <= delay + 1'b1;
end
reco: begin
if(data_buffer[127:112]==16'h1111)//参数配置
begin
para_confi_acq_flag <= 1'b1;
state <= idle;
end
else if(data_buffer[127:112]==16'h7777)//数据上传打开关闭
begin
data_upload_acq_flag <= 1'b1;
state <= idle;
end else begin
para_confi_acq_flag <= 1'b0;
data_upload_acq_flag <= 1'b0;
state <= idle;
end
end
default state <= idle;
endcase
end
endmodule
| 6.926003 |
module arpeggiator (
input wire CLK, // 50MHz input clock
output wire SPEAKER,
output wire [7:0] LED_G
);
reg [31:0] cnt = 0;
reg [31:0] switchcnt = 0;
reg LEDfreq1 = 1;
reg LEDfreq2 = 1;
wire [31:0] pitch = switchcnt < 10000000 ? `C3 / 2 : switchcnt < 20000000 ?
`D3
: switchcnt < 30000000 ?
`F3
: `A3;
always @(posedge CLK) begin
if (cnt >= pitch) cnt <= 0;
else cnt <= cnt + 1;
if (switchcnt == 40000000) switchcnt <= 0;
else switchcnt <= switchcnt + 1;
end
assign SPEAKER = cnt > pitch / 2;
assign LED_G[0] = LEDfreq1;
assign LED_G[1] = LEDfreq2;
endmodule
| 7.066251 |
module arp_recv (
input clk,
input reset,
input [7:0] arp_tdata_in,
input arp_tvalid_in,
input arp_tlast_in,
input [31:0] local_ip_addr,
input reply_ready_in,
output reg [31:0] remote_ip_addr_out,
output reg [47:0] remote_mac_addr_out,
// Send out the remote ARP request
input arp_reply_ack,
output arp_reply_out
);
localparam BUF_DEPTH = 9;
localparam ARP_LENGTH = 28;
reg [7:0] data_buf [0:BUF_DEPTH-1];
reg [4:0] byte_cnt;
reg arp_reply_r;
reg arp_reply_ack_r1, arp_reply_ack_r2;
wire [31:0] des_ip;
integer k;
//Clock domain cross
always @(posedge clk) begin
arp_reply_ack_r1 <= arp_reply_ack;
arp_reply_ack_r2 <= arp_reply_ack_r1;
end
always @(posedge clk) begin
if (reset) begin
for (k = 0; k < BUF_DEPTH; k = k + 1) begin
data_buf[k] <= 'h0;
end
end else begin
if (arp_tvalid_in) begin
for (k = 0; k < (BUF_DEPTH - 1); k = k + 1) begin
data_buf[k+1] <= data_buf[k];
end
data_buf[0] <= arp_tdata_in;
end else begin
for (k = 0; k < (BUF_DEPTH - 1); k = k + 1) begin
data_buf[k] <= data_buf[k];
end
end
end
end
always @(posedge clk) begin
if (reset) begin
byte_cnt <= 'h0;
end else begin
if (arp_reply_out || byte_cnt == (ARP_LENGTH - 1)) begin
byte_cnt <= 'h0;
end else if (arp_tvalid_in && ~arp_tlast_in) begin
byte_cnt <= byte_cnt + 5'd1;
end else if (arp_tlast_in) begin
byte_cnt <= 'h0;
end else begin
byte_cnt <= byte_cnt;
end
end
end
assign des_ip = {data_buf[2], data_buf[1], data_buf[0], arp_tdata_in};
always @(posedge clk) begin
if (reset) begin
remote_mac_addr_out <= 'h0;
remote_ip_addr_out <= 'h0;
arp_reply_r <= 1'b0;
end else begin
remote_ip_addr_out <= remote_ip_addr_out;
remote_mac_addr_out <= remote_mac_addr_out;
// Register the remote IP and MAC, used in the ARP reply operation.
if (arp_tvalid_in && byte_cnt == 5'd17) begin
remote_mac_addr_out <= {
data_buf[8], data_buf[7], data_buf[6], data_buf[5], data_buf[4], data_buf[3]
};
remote_ip_addr_out <= {data_buf[2], data_buf[1], data_buf[0], arp_tdata_in};
end
if (arp_tvalid_in && (byte_cnt == 5'd27)) begin
// Filter the local_ip_address and generate ARP reply operation
if (des_ip == local_ip_addr) begin
arp_reply_r <= 1'b1;
end else begin
arp_reply_r <= 1'b0;
end
end else if (reply_ready_in && arp_reply_ack_r2) begin
arp_reply_r <= 1'b0;
end else begin
arp_reply_r <= arp_reply_r;
end
end
end
assign arp_reply_out = reply_ready_in ? arp_reply_r : 1'b0;
/*
wire [0:0] arp_tvalid_ila;
wire [0:0] arp_tlast_ila;
wire [0:0] arp_reply_ila;
wire [0:0] arp_reply_ack_ila;
assign arp_tvalid_ila[0] = arp_tvalid_in;
assign arp_tlast_ila[0] = arp_tlast_in;
assign arp_reply_ila[0] = arp_reply_r;
assign arp_reply_ack_ila[0] = arp_reply_ack_r2;
ila_arp ila_arp (
.clk(clk), // input wire clk
.probe0(des_ip),
.probe1(byte_cnt),
.probe2(arp_reply_ila),
.probe3(arp_tdata_in),
.probe4(arp_tvalid_ila),
.probe5(arp_tlast_ila),
.probe6(local_ip_addr),
.probe7(arp_reply_ack_ila)
);
*/
endmodule
| 8.656462 |
module arp_server_ap_rst_if #(
parameter RESET_ACTIVE_LOW = 0
) (
input wire din,
output wire dout
);
assign dout = (RESET_ACTIVE_LOW == 1) ? ~din : din;
endmodule
| 8.673805 |
module arp_server_arpDataIn_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [63:0] TDATA,
input wire [ 7:0] TKEEP,
input wire [ 0:0] TLAST,
// User signals
output wire [63:0] arpDataIn_V_data_V_dout,
output wire arpDataIn_V_data_V_empty_n,
input wire arpDataIn_V_data_V_read,
output wire [ 7:0] arpDataIn_V_keep_V_dout,
output wire arpDataIn_V_keep_V_empty_n,
input wire arpDataIn_V_keep_V_read,
output wire [ 0:0] arpDataIn_V_last_V_dout,
output wire arpDataIn_V_last_V_empty_n,
input wire arpDataIn_V_last_V_read
);
//------------------------Local signal-------------------
// FIFO
wire [ 0:0] fifo_write;
wire [ 0:0] fifo_full_n;
wire [63:0] arpDataIn_V_data_V_din;
wire [ 0:0] arpDataIn_V_data_V_full_n;
wire [ 7:0] arpDataIn_V_keep_V_din;
wire [ 0:0] arpDataIn_V_keep_V_full_n;
wire [ 0:0] arpDataIn_V_last_V_din;
wire [ 0:0] arpDataIn_V_last_V_full_n;
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [72:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [72:0] m_data;
//------------------------Instantiation------------------
// rs
arp_server_arpDataIn_reg_slice #(
.N(73)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
// arpDataIn_V_data_V_fifo
arp_server_arpDataIn_fifo #(
.DATA_BITS (64),
.DEPTH_BITS(4)
) arpDataIn_V_data_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(arpDataIn_V_data_V_empty_n),
.full_n (arpDataIn_V_data_V_full_n),
.read (arpDataIn_V_data_V_read),
.write (fifo_write),
.dout (arpDataIn_V_data_V_dout),
.din (arpDataIn_V_data_V_din)
);
// arpDataIn_V_keep_V_fifo
arp_server_arpDataIn_fifo #(
.DATA_BITS (8),
.DEPTH_BITS(4)
) arpDataIn_V_keep_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(arpDataIn_V_keep_V_empty_n),
.full_n (arpDataIn_V_keep_V_full_n),
.read (arpDataIn_V_keep_V_read),
.write (fifo_write),
.dout (arpDataIn_V_keep_V_dout),
.din (arpDataIn_V_keep_V_din)
);
// arpDataIn_V_last_V_fifo
arp_server_arpDataIn_fifo #(
.DATA_BITS (1),
.DEPTH_BITS(4)
) arpDataIn_V_last_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(arpDataIn_V_last_V_empty_n),
.full_n (arpDataIn_V_last_V_full_n),
.read (arpDataIn_V_last_V_read),
.write (fifo_write),
.dout (arpDataIn_V_last_V_dout),
.din (arpDataIn_V_last_V_din)
);
//------------------------Body---------------------------
//++++++++++++++++++++++++AXI4-Stream++++++++++++++++++++
assign TREADY = s_ready;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++Reigister Slice++++++++++++++++
assign s_valid = TVALID;
assign m_ready = fifo_full_n;
assign s_data = {TLAST[0:0], TKEEP[7:0], TDATA[63:0]};
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++FIFO+++++++++++++++++++++++++++
assign fifo_write = fifo_full_n & m_valid;
assign arpDataIn_V_data_V_din = m_data[63:0];
assign arpDataIn_V_keep_V_din = m_data[71:64];
assign arpDataIn_V_last_V_din = m_data[72:72];
assign fifo_full_n = arpDataIn_V_data_V_full_n & arpDataIn_V_keep_V_full_n & arpDataIn_V_last_V_full_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 7.632522 |
module arp_server_arpDataIn_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire write,
output wire [DATA_BITS-1:0] dout,
input wire [DATA_BITS-1:0] din
);
//------------------------Parameter----------------------
localparam DEPTH = 1 << DEPTH_BITS;
//------------------------Local signal-------------------
reg empty;
reg full;
reg [DEPTH_BITS-1:0] index;
reg [ DATA_BITS-1:0] mem [0:DEPTH-1];
//------------------------Body---------------------------
assign empty_n = ~empty;
assign full_n = ~full;
assign dout = mem[index];
// empty
always @(posedge clk or posedge aclr) begin
if (aclr) empty <= 1'b1;
else if (empty & write & ~read) empty <= 1'b0;
else if (~empty & ~write & read & (index == 1'b0)) empty <= 1'b1;
end
// full
always @(posedge clk or posedge aclr) begin
if (aclr) full <= 1'b0;
else if (full & read & ~write) full <= 1'b0;
else if (~full & ~read & write & (index == DEPTH - 2'd2)) full <= 1'b1;
end
// index
always @(posedge clk or posedge aclr) begin
if (aclr) index <= {DEPTH_BITS{1'b1}};
else if (~empty & ~write & read) index <= index - 1'b1;
else if (~full & ~read & write) index <= index + 1'b1;
end
// mem
always @(posedge clk) begin
if (~full & write) mem[0] <= din;
end
genvar i;
generate
for (i = 1; i < DEPTH; i = i + 1) begin : gen_sr
always @(posedge clk) begin
if (~full & write) mem[i] <= mem[i-1];
end
end
endgenerate
endmodule
| 7.632522 |
module arp_server_arpDataIn_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.632522 |
module arp_server_arpDataOut_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [63:0] TDATA,
output wire [ 7:0] TKEEP,
output wire [ 0:0] TLAST,
// User signals
input wire [63:0] arpDataOut_V_data_V_din,
output wire arpDataOut_V_data_V_full_n,
input wire arpDataOut_V_data_V_write,
input wire [ 7:0] arpDataOut_V_keep_V_din,
output wire arpDataOut_V_keep_V_full_n,
input wire arpDataOut_V_keep_V_write,
input wire [ 0:0] arpDataOut_V_last_V_din,
output wire arpDataOut_V_last_V_full_n,
input wire arpDataOut_V_last_V_write
);
//------------------------Local signal-------------------
// FIFO
wire [ 0:0] fifo_read;
wire [ 0:0] fifo_empty_n;
wire [63:0] arpDataOut_V_data_V_dout;
wire [ 0:0] arpDataOut_V_data_V_empty_n;
wire [ 7:0] arpDataOut_V_keep_V_dout;
wire [ 0:0] arpDataOut_V_keep_V_empty_n;
wire [ 0:0] arpDataOut_V_last_V_dout;
wire [ 0:0] arpDataOut_V_last_V_empty_n;
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [72:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [72:0] m_data;
//------------------------Instantiation------------------
// rs
arp_server_arpDataOut_reg_slice #(
.N(73)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
// arpDataOut_V_data_V_fifo
arp_server_arpDataOut_fifo #(
.DATA_BITS (64),
.DEPTH_BITS(4)
) arpDataOut_V_data_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(arpDataOut_V_data_V_empty_n),
.full_n (arpDataOut_V_data_V_full_n),
.read (fifo_read),
.write (arpDataOut_V_data_V_write),
.dout (arpDataOut_V_data_V_dout),
.din (arpDataOut_V_data_V_din)
);
// arpDataOut_V_keep_V_fifo
arp_server_arpDataOut_fifo #(
.DATA_BITS (8),
.DEPTH_BITS(4)
) arpDataOut_V_keep_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(arpDataOut_V_keep_V_empty_n),
.full_n (arpDataOut_V_keep_V_full_n),
.read (fifo_read),
.write (arpDataOut_V_keep_V_write),
.dout (arpDataOut_V_keep_V_dout),
.din (arpDataOut_V_keep_V_din)
);
// arpDataOut_V_last_V_fifo
arp_server_arpDataOut_fifo #(
.DATA_BITS (1),
.DEPTH_BITS(4)
) arpDataOut_V_last_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(arpDataOut_V_last_V_empty_n),
.full_n (arpDataOut_V_last_V_full_n),
.read (fifo_read),
.write (arpDataOut_V_last_V_write),
.dout (arpDataOut_V_last_V_dout),
.din (arpDataOut_V_last_V_din)
);
//------------------------Body---------------------------
//++++++++++++++++++++++++AXI4-Stream++++++++++++++++++++
assign TVALID = m_valid;
assign TDATA = m_data[63:0];
assign TKEEP = m_data[71:64];
assign TLAST = m_data[72:72];
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++Reigister Slice++++++++++++++++
assign s_valid = fifo_empty_n;
assign m_ready = TREADY;
assign s_data = {arpDataOut_V_last_V_dout, arpDataOut_V_keep_V_dout, arpDataOut_V_data_V_dout};
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++FIFO+++++++++++++++++++++++++++
assign fifo_read = fifo_empty_n & s_ready;
assign fifo_empty_n = arpDataOut_V_data_V_empty_n & arpDataOut_V_keep_V_empty_n & arpDataOut_V_last_V_empty_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 7.632522 |
module arp_server_arpDataOut_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire write,
output wire [DATA_BITS-1:0] dout,
input wire [DATA_BITS-1:0] din
);
//------------------------Parameter----------------------
localparam DEPTH = 1 << DEPTH_BITS;
//------------------------Local signal-------------------
reg empty;
reg full;
reg [DEPTH_BITS-1:0] index;
reg [ DATA_BITS-1:0] mem [0:DEPTH-1];
//------------------------Body---------------------------
assign empty_n = ~empty;
assign full_n = ~full;
assign dout = mem[index];
// empty
always @(posedge clk or posedge aclr) begin
if (aclr) empty <= 1'b1;
else if (empty & write & ~read) empty <= 1'b0;
else if (~empty & ~write & read & (index == 1'b0)) empty <= 1'b1;
end
// full
always @(posedge clk or posedge aclr) begin
if (aclr) full <= 1'b0;
else if (full & read & ~write) full <= 1'b0;
else if (~full & ~read & write & (index == DEPTH - 2'd2)) full <= 1'b1;
end
// index
always @(posedge clk or posedge aclr) begin
if (aclr) index <= {DEPTH_BITS{1'b1}};
else if (~empty & ~write & read) index <= index - 1'b1;
else if (~full & ~read & write) index <= index + 1'b1;
end
// mem
always @(posedge clk) begin
if (~full & write) mem[0] <= din;
end
genvar i;
generate
for (i = 1; i < DEPTH; i = i + 1) begin : gen_sr
always @(posedge clk) begin
if (~full & write) mem[i] <= mem[i-1];
end
end
endgenerate
endmodule
| 7.632522 |
module arp_server_arpDataOut_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.632522 |
module arp_server_macIpEncode_req_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [31:0] TDATA,
// User signals
output wire [31:0] macIpEncode_req_V_V_dout,
output wire macIpEncode_req_V_V_empty_n,
input wire macIpEncode_req_V_V_read
);
//------------------------Local signal-------------------
// FIFO
wire [ 0:0] fifo_write;
wire [ 0:0] fifo_full_n;
wire [31:0] macIpEncode_req_V_V_din;
wire [ 0:0] macIpEncode_req_V_V_full_n;
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [31:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [31:0] m_data;
//------------------------Instantiation------------------
// rs
arp_server_macIpEncode_req_reg_slice #(
.N(32)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
// macIpEncode_req_V_V_fifo
arp_server_macIpEncode_req_fifo #(
.DATA_BITS (32),
.DEPTH_BITS(4)
) macIpEncode_req_V_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(macIpEncode_req_V_V_empty_n),
.full_n (macIpEncode_req_V_V_full_n),
.read (macIpEncode_req_V_V_read),
.write (fifo_write),
.dout (macIpEncode_req_V_V_dout),
.din (macIpEncode_req_V_V_din)
);
//------------------------Body---------------------------
//++++++++++++++++++++++++AXI4-Stream++++++++++++++++++++
assign TREADY = s_ready;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++Reigister Slice++++++++++++++++
assign s_valid = TVALID;
assign m_ready = fifo_full_n;
assign s_data = {TDATA[31:0]};
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++FIFO+++++++++++++++++++++++++++
assign fifo_write = fifo_full_n & m_valid;
assign macIpEncode_req_V_V_din = m_data[31:0];
assign fifo_full_n = macIpEncode_req_V_V_full_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 7.675029 |
module arp_server_macIpEncode_req_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire write,
output wire [DATA_BITS-1:0] dout,
input wire [DATA_BITS-1:0] din
);
//------------------------Parameter----------------------
localparam DEPTH = 1 << DEPTH_BITS;
//------------------------Local signal-------------------
reg empty;
reg full;
reg [DEPTH_BITS-1:0] index;
reg [ DATA_BITS-1:0] mem [0:DEPTH-1];
//------------------------Body---------------------------
assign empty_n = ~empty;
assign full_n = ~full;
assign dout = mem[index];
// empty
always @(posedge clk or posedge aclr) begin
if (aclr) empty <= 1'b1;
else if (empty & write & ~read) empty <= 1'b0;
else if (~empty & ~write & read & (index == 1'b0)) empty <= 1'b1;
end
// full
always @(posedge clk or posedge aclr) begin
if (aclr) full <= 1'b0;
else if (full & read & ~write) full <= 1'b0;
else if (~full & ~read & write & (index == DEPTH - 2'd2)) full <= 1'b1;
end
// index
always @(posedge clk or posedge aclr) begin
if (aclr) index <= {DEPTH_BITS{1'b1}};
else if (~empty & ~write & read) index <= index - 1'b1;
else if (~full & ~read & write) index <= index + 1'b1;
end
// mem
always @(posedge clk) begin
if (~full & write) mem[0] <= din;
end
genvar i;
generate
for (i = 1; i < DEPTH; i = i + 1) begin : gen_sr
always @(posedge clk) begin
if (~full & write) mem[i] <= mem[i-1];
end
end
endgenerate
endmodule
| 7.675029 |
module arp_server_macIpEncode_req_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.675029 |
module arp_server_macIpEncode_rsp_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [55:0] TDATA,
// User signals
input wire [48:0] macIpEncode_rsp_V_din,
output wire macIpEncode_rsp_V_full_n,
input wire macIpEncode_rsp_V_write
);
//------------------------Local signal-------------------
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [48:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [48:0] m_data;
//------------------------Instantiation------------------
// rs
arp_server_macIpEncode_rsp_reg_slice #(
.N(49)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
//------------------------Body---------------------------
// AXI4-Stream
assign TVALID = m_valid;
assign TDATA = m_data[48:0];
// Register Slice
assign s_valid = macIpEncode_rsp_V_write;
assign m_ready = TREADY;
assign s_data = macIpEncode_rsp_V_din;
// User Signal
assign macIpEncode_rsp_V_full_n = s_ready;
endmodule
| 7.675029 |
module arp_server_macIpEncode_rsp_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.675029 |
module arp_server_macLookup_req_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [39:0] TDATA,
// User signals
input wire [32:0] macLookup_req_V_din,
output wire macLookup_req_V_full_n,
input wire macLookup_req_V_write
);
//------------------------Local signal-------------------
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [32:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [32:0] m_data;
//------------------------Instantiation------------------
// rs
arp_server_macLookup_req_reg_slice #(
.N(33)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
//------------------------Body---------------------------
// AXI4-Stream
assign TVALID = m_valid;
assign TDATA = m_data[32:0];
// Register Slice
assign s_valid = macLookup_req_V_write;
assign m_ready = TREADY;
assign s_data = macLookup_req_V_din;
// User Signal
assign macLookup_req_V_full_n = s_ready;
endmodule
| 7.675029 |
module arp_server_macLookup_req_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.675029 |
module arp_server_macLookup_resp_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [55:0] TDATA,
// User signals
output wire [48:0] macLookup_resp_V_dout,
output wire macLookup_resp_V_empty_n,
input wire macLookup_resp_V_read
);
//------------------------Local signal-------------------
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [48:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [48:0] m_data;
//------------------------Instantiation------------------
// rs
arp_server_macLookup_resp_reg_slice #(
.N(49)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
//------------------------Body---------------------------
// AXI4-Stream
assign TREADY = s_ready;
// Register Slice
assign s_valid = TVALID;
assign m_ready = macLookup_resp_V_read;
assign s_data[48:0] = TDATA[48:0];
// User Signal
assign macLookup_resp_V_empty_n = m_valid;
assign macLookup_resp_V_dout = m_data;
endmodule
| 7.675029 |
module arp_server_macLookup_resp_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.675029 |
module arp_server_macUpdate_req_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [87:0] TDATA,
// User signals
input wire [81:0] macUpdate_req_V_din,
output wire macUpdate_req_V_full_n,
input wire macUpdate_req_V_write
);
//------------------------Local signal-------------------
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [81:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [81:0] m_data;
//------------------------Instantiation------------------
// rs
arp_server_macUpdate_req_reg_slice #(
.N(82)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
//------------------------Body---------------------------
// AXI4-Stream
assign TVALID = m_valid;
assign TDATA = m_data[81:0];
// Register Slice
assign s_valid = macUpdate_req_V_write;
assign m_ready = TREADY;
assign s_data = macUpdate_req_V_din;
// User Signal
assign macUpdate_req_V_full_n = s_ready;
endmodule
| 7.675029 |
module arp_server_macUpdate_req_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.675029 |
module arp_server_macUpdate_resp_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [55:0] TDATA,
// User signals
output wire [49:0] macUpdate_resp_V_dout,
output wire macUpdate_resp_V_empty_n,
input wire macUpdate_resp_V_read
);
//------------------------Local signal-------------------
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [49:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [49:0] m_data;
//------------------------Instantiation------------------
// rs
arp_server_macUpdate_resp_reg_slice #(
.N(50)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
//------------------------Body---------------------------
// AXI4-Stream
assign TREADY = s_ready;
// Register Slice
assign s_valid = TVALID;
assign m_ready = macUpdate_resp_V_read;
assign s_data[49:0] = TDATA[49:0];
// User Signal
assign macUpdate_resp_V_empty_n = m_valid;
assign macUpdate_resp_V_dout = m_data;
endmodule
| 7.675029 |
module arp_server_macUpdate_resp_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.675029 |
module arp_table_arpTablbkb_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./arp_table_arpTablbkb_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
q0 <= ram[addr0];
end
end
endmodule
| 8.342357 |
module arp_table_arpTablbkb (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
arp_table_arpTablbkb_ram arp_table_arpTablbkb_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.q0(q0)
);
endmodule
| 8.342357 |
module arp_table_arpTablcud_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 48;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./arp_table_arpTablcud_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
q0 <= ram[addr0];
end
end
endmodule
| 8.342357 |
module arp_table_arpTablcud (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd48;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
arp_table_arpTablcud_ram arp_table_arpTablcud_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.q0(q0)
);
endmodule
| 8.342357 |
module arp_table_arpTabldEe_ram (
addr0,
ce0,
d0,
we0,
clk
);
parameter DWIDTH = 1;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./arp_table_arpTabldEe_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
end
end
endmodule
| 8.342357 |
module arp_table_arpTabldEe (
reset,
clk,
address0,
ce0,
we0,
d0
);
parameter DataWidth = 32'd1;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
arp_table_arpTabldEe_ram arp_table_arpTabldEe_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0)
);
endmodule
| 8.342357 |
module Arquitetura_buttons (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [1:0] in_port;
input reset_n;
wire clk_en;
wire [ 1:0] data_in;
wire [ 1:0] read_mux_out;
reg [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {2{(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
| 6.734548 |
module Arquitetura_dataA (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [31:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0] writedata;
wire clk_en;
reg [31:0] data_out;
wire [31:0] out_port;
wire [31:0] read_mux_out;
wire [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {32{(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata[31 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
| 6.641472 |
module Arquitetura_data_A (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [31:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0] writedata;
wire clk_en;
reg [31:0] data_out;
wire [31:0] out_port;
wire [31:0] read_mux_out;
wire [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {32{(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata[31 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
| 6.641472 |
module Arquitetura_data_B (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [31:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0] writedata;
wire clk_en;
reg [31:0] data_out;
wire [31:0] out_port;
wire [31:0] read_mux_out;
wire [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {32{(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 1636852736;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata[31 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
| 6.641472 |
module Arquitetura_isPrintting (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1{(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
| 6.849703 |
module Arquitetura_isPritting (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [4:0] in_port;
input reset_n;
wire clk_en;
wire [ 4:0] data_in;
wire [ 4:0] read_mux_out;
reg [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {5{(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
| 6.849703 |
module Arquitetura_nios2_gen2_0_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire [31:0] q;
wire [31:0] ram_data;
wire [31:0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram (
.address_a(wraddress),
.address_b(rdaddress),
.clock0(clock),
.data_a(ram_data),
.q_b(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0", the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0, the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32, the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32, the_altsyncram.widthad_a = 5, the_altsyncram.widthad_b = 5;
endmodule
| 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire [31:0] q;
wire [31:0] ram_data;
wire [31:0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram (
.address_a(wraddress),
.address_b(rdaddress),
.clock0(clock),
.data_a(ram_data),
.q_b(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0", the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0, the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32, the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32, the_altsyncram.widthad_a = 5, the_altsyncram.widthad_b = 5;
endmodule
| 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
| 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [16:0] cpu_d_address;
input cpu_d_read;
input [31:0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [31:0] cpu_d_writedata;
input jrst_n;
input [15:0] trc_ctrl;
reg [35:0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [31:0] cpu_d_address_0_padded;
wire [31:0] cpu_d_readdata_0_padded;
wire [31:0] cpu_d_writedata_0_padded;
reg [35:0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dummy_tie_off;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3:0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//Arquitetura_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode, which is an e_instance
Arquitetura_nios2_gen2_0_cpu_nios2_oci_td_mode Arquitetura_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode
(
.ctrl (trc_ctrl[8 : 0]),
.td_mode(td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n) begin
if (jrst_n == 0) begin
atm <= 0;
dtm <= 0;
end else begin
atm <= 0;
dtm <= 0;
end
end
assign dummy_tie_off = cpu_d_wait | cpu_d_read | cpu_d_write;
endmodule
| 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
);
output [1:0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_input_tm_cnt;
wire [2:0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux) begin
case (switch_for_mux)
3'b000: begin
compute_input_tm_cnt = 0;
end // 3'b000
3'b001: begin
compute_input_tm_cnt = 1;
end // 3'b001
3'b010: begin
compute_input_tm_cnt = 1;
end // 3'b010
3'b011: begin
compute_input_tm_cnt = 2;
end // 3'b011
3'b100: begin
compute_input_tm_cnt = 1;
end // 3'b100
3'b101: begin
compute_input_tm_cnt = 2;
end // 3'b101
3'b110: begin
compute_input_tm_cnt = 2;
end // 3'b110
3'b111: begin
compute_input_tm_cnt = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
| 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
);
output [3:0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [3:0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or input_tm_cnt) begin
if (ge3_free & (input_tm_cnt == 3)) fifo_wrptr_inc = 3;
else if (ge2_free & (input_tm_cnt >= 2)) fifo_wrptr_inc = 2;
else if (input_tm_cnt >= 1) fifo_wrptr_inc = 1;
else fifo_wrptr_inc = 0;
end
endmodule
| 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
);
output [4:0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [4:0] fifo_cnt_inc;
always @(empty or ge2_free or ge3_free or input_tm_cnt) begin
if (empty) fifo_cnt_inc = input_tm_cnt[1 : 0];
else if (ge3_free & (input_tm_cnt == 3)) fifo_cnt_inc = 2;
else if (ge2_free & (input_tm_cnt >= 2)) fifo_cnt_inc = 1;
else if (input_tm_cnt >= 1) fifo_cnt_inc = 0;
else fifo_cnt_inc = {5{1'b1}};
end
endmodule
| 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_nios2_oci_pib (
// outputs:
tr_data
);
output [35:0] tr_data;
wire [35:0] tr_data;
assign tr_data = 0;
endmodule
| 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
);
output tracemem_on;
output [35:0] tracemem_trcdata;
output tracemem_tw;
output [6:0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input jrst_n;
input [15:0] trc_ctrl;
input [35:0] tw;
wire tracemem_on;
wire [35:0] tracemem_trcdata;
wire tracemem_tw;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [35:0] trc_im_data;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n) begin
if (jrst_n == 0) begin
trc_im_addr <= 0;
trc_wrap <= 0;
end else begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
end
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_trcdata = 0;
endmodule
| 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_nios2_performance_monitors;
endmodule
| 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
);
output [31:0] oci_ienable;
output [31:0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [8:0] address;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [31:0] writedata;
reg [31:0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [31:0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) oci_single_step_mode <= 1'b0;
else if (take_action_ocireg) oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) oci_ienable <= 32'b00000000000000000000000000000001;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000000000001);
end
endmodule
| 6.913117 |
module Arquitetura_nios2_gen2_0_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input [7:0] address;
input [3:0] byteenable;
input clock;
input [31:0] data;
input reset_req;
input wren;
wire clocken;
wire [31:0] q;
wire [31:0] ram_q;
assign q = ram_q;
assign clocken = ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clock),
.clocken0(clocken),
.data_a(data),
.q_a(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.init_file = lpm_file, the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 256, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 8;
endmodule
| 6.913117 |
module Arquitetura_printting (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1{(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
| 6.533684 |
module Arquitetura_screen (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1{(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
| 6.997654 |
module Arquitetura_switch (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [2:0] in_port;
input reset_n;
wire clk_en;
wire [ 2:0] data_in;
wire [ 2:0] read_mux_out;
reg [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {3{(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
| 6.997654 |
module Arquitetura_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1623240844 : 0;
endmodule
| 6.997654 |
module arrange_cell ( //output
arrange_out,
arrange_out_vld,
//input
stall_vld,
//halt,
cxd_c,
cxd_r,
cxd_vld_c,
cxd_vld_l,
cxd_vld_r,
clk_dwt,
pos_clk_bpc,
rst,
rst_syn
);
output [7:0] arrange_out;
output arrange_out_vld;
input stall_vld;
input [7:0] cxd_c;
input [7:0] cxd_r;
input cxd_vld_c;
input cxd_vld_l;
input cxd_vld_r;
input clk_dwt;
input pos_clk_bpc;
input rst;
input rst_syn;
reg [7:0] arrange_out;
reg arrange_out_vld;
always @(posedge clk_dwt or negedge rst) begin
if (!rst) begin
arrange_out <= 8'b0;
arrange_out_vld <= 1'b0;
end else if (rst_syn) begin
arrange_out <= 8'b0;
arrange_out_vld <= 1'b0;
end else if (pos_clk_bpc == 1'b1) begin
if (stall_vld == 1'b1) begin
arrange_out <= arrange_out;
arrange_out_vld <= arrange_out_vld;
end
else if(((cxd_vld_c == 1'b1)&&(cxd_vld_l == 1'b0))||((cxd_vld_c == 1'b0)&&(cxd_vld_r == 1'b0))) begin
arrange_out <= 8'b0;
arrange_out_vld <= 1'b0;
end else if ((cxd_vld_c == 1'b1) && (cxd_vld_l == 1'b1)) begin
arrange_out <= cxd_c;
arrange_out_vld <= cxd_vld_c;
end else if ((cxd_vld_c == 1'b0) && (cxd_vld_r == 1'b1)) begin
arrange_out <= cxd_r;
arrange_out_vld <= cxd_vld_r;
end
end
end
endmodule
| 6.841236 |
module and1 (
input x,
input y,
output wire w
);
assign w = x * y;
endmodule
| 6.846927 |
module ha (
input e,
input f,
output wire g,
output wire h
);
assign g = e ^ f;
assign h = e * f;
endmodule
| 7.857591 |
module fa (
input j,
input k,
input l,
output wire m,
output wire n
);
assign m = j ^ k ^ l;
assign n = (j * k) + (k * l) + (j * l);
endmodule
| 7.001699 |
module common_2i1 (
i0,
i1,
o,
s
);
parameter WIDTH = 281 * 2;
input [WIDTH - 1:0] i0, i1;
output [WIDTH - 1:0] o;
input s;
reg [WIDTH - 1:0] o;
always @(*)
case (s)
'b1: o = i1;
`ifdef SIM
'bz,'bx:o = {WIDTH{1'bx}};
`endif
default:o = i0;
endcase
endmodule
| 7.166385 |
module common_1o2 (
i,
o1,
o0
);
parameter WIDTH = 281 * 2;
input [WIDTH - 1:0] i;
output [WIDTH - 1:0] o0, o1;
assign o0 = i;
assign o1 = i;
endmodule
| 7.109382 |
module array4c (
Z2,
X,
Y
);
input [3:0] Y;
input [3:0] X;
output [3:0] Z2;
wire [3:0] P0;
wire [3:0] carry1;
wire [3:0] sum1;
wire [3:0] P1;
wire [3:0] carry2;
wire [3:0] sum2;
wire [3:0] P2;
wire [3:0] carry3;
wire [3:0] sum3;
wire [3:0] P3;
wire [3:0] carry4;
wire [3:0] sum4;
wire [4:0] carry5;
wire [5:0] Z;
// Partial Product Generation
and pp1 (P0[3], X[3], Y[0]);
and pp2 (P0[2], X[2], Y[0]);
and pp3 (sum1[3], X[3], Y[1]);
and pp4 (P1[2], X[2], Y[1]);
and pp5 (P1[1], X[1], Y[1]);
and pp6 (sum2[3], X[3], Y[2]);
and pp7 (P2[2], X[2], Y[2]);
and pp8 (P2[1], X[1], Y[2]);
and pp9 (P2[0], X[0], Y[2]);
and pp10 (sum3[3], X[3], Y[3]);
and pp11 (P3[2], X[2], Y[3]);
and pp12 (P3[1], X[1], Y[3]);
and pp13 (P3[0], X[0], Y[3]);
// Partial Product Reduction
sha SHA1 (
carry1[2],
sum1[2],
P1[2],
P0[3]
);
ha HA1 (
carry1[1],
sum1[1],
P1[1],
P0[2]
);
fa FA1 (
carry2[2],
sum2[2],
P2[2],
sum1[3],
carry1[2]
);
fa FA2 (
carry2[1],
sum2[1],
P2[1],
sum1[2],
carry1[1]
);
assign carry2[0] = P2[0] & sum1[1];
fa FA3 (
carry3[2],
sum3[2],
P3[2],
sum2[3],
carry2[2]
);
fa FA4 (
carry3[1],
sum3[1],
P3[1],
sum2[2],
carry2[1]
);
rfa RFA1 (
carry3[0],
P3[0],
sum2[1],
carry2[0]
);
// Generate lower product bits YBITS
// Final Carry Propagate Addition
// Generate higher product bits
ha CPA1 (
carry4[0],
Z2[0],
carry3[0],
sum3[1]
);
fa CPA2 (
carry4[1],
Z2[1],
carry3[1],
carry4[0],
sum3[2]
);
fa CPA3 (
Z2[3],
Z2[2],
carry3[2],
carry4[1],
sum3[3]
);
endmodule
| 7.858865 |
module array4h (
Z,
X,
Y
);
input [3:0] Y;
input [3:0] X;
output [3:0] Z;
wire [3:0] P0;
wire [3:0] carry1;
wire [3:0] sum1;
wire [3:0] P1;
wire [3:0] carry2;
wire [3:0] sum2;
wire [3:0] P2;
wire [3:0] carry3;
wire [3:0] sum3;
wire [3:0] P3;
wire [3:0] carry4;
wire [3:0] sum4;
// Partial Product Generation
and pp1 (P0[3], X[3], Y[0]);
and pp2 (sum1[3], X[3], Y[1]);
and pp3 (P1[2], X[2], Y[1]);
and pp4 (sum2[3], X[3], Y[2]);
and pp5 (P2[2], X[2], Y[2]);
and pp6 (P2[1], X[1], Y[2]);
and pp7 (sum3[3], X[3], Y[3]);
and pp8 (P3[2], X[2], Y[3]);
and pp9 (P3[1], X[1], Y[3]);
and pp10 (P3[0], X[0], Y[3]);
// Partial Product Reduction
sha SHA1 (
carry1[2],
sum1[2],
P1[2],
P0[3]
);
fa FA1 (
carry2[2],
sum2[2],
P2[2],
sum1[3],
carry1[2]
);
ha HA1 (
carry2[1],
sum2[1],
P2[1],
sum1[2]
);
fa FA2 (
carry3[2],
sum3[2],
P3[2],
sum2[3],
carry2[2]
);
fa FA3 (
carry3[1],
sum3[1],
P3[1],
sum2[2],
carry2[1]
);
assign carry3[0] = P3[0] & sum2[1];
// Generate lower product bits YBITS
// Final Carry Propagate Addition
// Generate higher product bits
ha CPA1 (
carry4[0],
Z[0],
carry3[0],
sum3[1]
);
fa CPA2 (
carry4[1],
Z[1],
carry3[1],
carry4[0],
sum3[2]
);
fa CPA3 (
Z[3],
Z[2],
carry3[2],
carry4[1],
sum3[3]
);
endmodule
| 7.22926 |
module array4tc (
Z,
X,
Y
);
input [3:0] Y;
input [3:0] X;
output [7:0] Z;
wire [3:0] P0;
wire [3:0] carry1;
wire [3:0] sum1;
wire [3:0] P1;
wire [3:0] carry2;
wire [3:0] sum2;
wire [3:0] P2;
wire [3:0] carry3;
wire [3:0] sum3;
wire [3:0] P3;
wire [3:0] carry4;
wire [3:0] sum4;
wire [6:0] carry5;
wire [7:0] Z;
// Partial Product Generation
nand pp1 (P0[3], X[3], Y[0]);
and pp2 (P0[2], X[2], Y[0]);
and pp3 (P0[1], X[1], Y[0]);
and pp4 (P0[0], X[0], Y[0]);
nand pp5 (sum1[3], X[3], Y[1]);
and pp6 (P1[2], X[2], Y[1]);
and pp7 (P1[1], X[1], Y[1]);
and pp8 (P1[0], X[0], Y[1]);
nand pp9 (sum2[3], X[3], Y[2]);
and pp10 (P2[2], X[2], Y[2]);
and pp11 (P2[1], X[1], Y[2]);
and pp12 (P2[0], X[0], Y[2]);
and pp13 (sum3[3], X[3], Y[3]);
nand pp14 (P3[2], X[2], Y[3]);
nand pp15 (P3[1], X[1], Y[3]);
nand pp16 (P3[0], X[0], Y[3]);
// Partial Product Reduction
ha HA1 (
carry1[2],
sum1[2],
P1[2],
P0[3]
);
ha HA2 (
carry1[1],
sum1[1],
P1[1],
P0[2]
);
ha HA3 (
carry1[0],
sum1[0],
P1[0],
P0[1]
);
fa FA1 (
carry2[2],
sum2[2],
P2[2],
sum1[3],
carry1[2]
);
fa FA2 (
carry2[1],
sum2[1],
P2[1],
sum1[2],
carry1[1]
);
fa FA3 (
carry2[0],
sum2[0],
P2[0],
sum1[1],
carry1[0]
);
fa FA4 (
carry3[2],
sum3[2],
P3[2],
sum2[3],
carry2[2]
);
fa FA5 (
carry3[1],
sum3[1],
P3[1],
sum2[2],
carry2[1]
);
fa FA6 (
carry3[0],
sum3[0],
P3[0],
sum2[1],
carry2[0]
);
// Generate lower product bits YBITS
buf b1 (Z[0], P0[0]);
assign Z[1] = sum1[0];
assign Z[2] = sum2[0];
assign Z[3] = sum3[0];
// Final Carry Propagate Addition (CPA)
fa CPA1 (
carry4[0],
Z[4],
carry3[0],
sum3[1],
1'b1
);
fa CPA2 (
carry4[1],
Z[5],
carry3[1],
carry4[0],
sum3[2]
);
fa CPA3 (
cout,
Z[6],
carry3[2],
carry4[1],
sum3[3]
);
not i1 (Z[7], cout);
endmodule
| 7.117492 |
module array4v (
Z,
X,
Y
);
input [3:0] Y;
input [3:0] X;
output [3:0] Z;
wire [3:0] P0;
wire [3:0] carry1;
wire [3:0] sum1;
wire [3:0] P1;
wire [3:0] carry2;
wire [3:0] sum2;
wire [3:0] P2;
wire [3:0] carry3;
wire [3:0] sum3;
wire [3:0] P3;
wire [3:0] carry4;
wire [3:0] sum4;
// Partial Product Generation
and pp1 (P0[3], X[3], Y[0]);
and pp2 (sum1[3], X[3], Y[1]);
and pp3 (P1[2], X[2], Y[1]);
and pp4 (carry1[1], X[1], Y[1]);
and pp5 (sum2[3], X[3], Y[2]);
and pp6 (P2[2], X[2], Y[2]);
and pp7 (P2[1], X[1], Y[2]);
and pp8 (carry2[0], X[0], Y[2]);
and pp9 (sum3[3], X[3], Y[3]);
and pp10 (P3[2], X[2], Y[3]);
and pp11 (P3[1], X[1], Y[3]);
and pp12 (P3[0], X[0], Y[3]);
// Partial Product Reduction
ha HA1 (
carry1[2],
sum1[2],
P1[2],
P0[3]
);
fa FA1 (
carry2[2],
sum2[2],
P2[2],
sum1[3],
carry1[2]
);
fa FA2 (
carry2[1],
sum2[1],
P2[1],
sum1[2],
carry1[1]
);
fa FA3 (
carry3[2],
sum3[2],
P3[2],
sum2[3],
carry2[2]
);
fa FA4 (
carry3[1],
sum3[1],
P3[1],
sum2[2],
carry2[1]
);
rfa RFA1 (
carry3[0],
P3[0],
sum2[1],
carry2[0]
);
// Generate lower product bits YBITS
// Final Carry Propagate Addition
// Generate higher product bits
ha CPA1 (
carry4[0],
Z[0],
carry3[0],
sum3[1]
);
fa CPA2 (
carry4[1],
Z[1],
carry3[1],
carry4[0],
sum3[2]
);
fa CPA3 (
Z[3],
Z[2],
carry3[2],
carry4[1],
sum3[3]
);
endmodule
| 7.440355 |
module aoi12 (
a,
b,
c,
y
);
input a, b, c;
output y;
assign y = ~((a & b) | c);
endmodule
| 8.423832 |
module FACell (
output Cnext,
Sthis,
input xn,
am,
Cthis
);
wire t1, t2, t3;
xor (t1, am, xn);
and (t2, t1, Cthis);
and (t3, am, xn);
or (Cnext, t2, t3);
xor (Sthis, t1, Cthis);
endmodule
| 7.106661 |
module ArrayMultiplier (
product,
a,
x
);
parameter m = 4;
parameter n = 4;
output [m+n-1:0] product;
input [m-1:0] a;
input [n-1:0] x;
wire c_partial[m*n:0];
wire s_partial[m*n:0];
// first line of the multiplier
genvar i;
generate
for (i = 0; i < m; i = i + 1) begin
Cell c_first (
.Cnext(c_partial[i]),
.Sthis(s_partial[i]),
.xn(x[0]),
.am(a[i]),
.Slast(1'b0),
.Cthis(1'b0)
);
end
endgenerate
// middle lines of the multiplier - except last column
genvar j, k;
generate
for (k = 0; k < n - 1; k = k + 1) begin
for (j = 0; j < m - 1; j = j + 1) begin
Cell c_middle (
c_partial[m*(k+1)+j],
s_partial[m*(k+1)+j],
x[k+1],
a[j],
s_partial[m*(k+1)+j-m+1],
c_partial[m*(k+1)+j-m]
);
end
end
endgenerate
// middle lines of the multiplier - only last column
genvar z;
generate
for (z = 0; z < n - 1; z = z + 1) begin
Cell c_middle_last_col (
c_partial[m*(z+1)+(m-1)],
s_partial[m*(z+1)+(m-1)],
x[z+1],
a[+(m-1)],
1'b0,
c_partial[m*(z+1)+(m-1)-m]
);
end
endgenerate
// last line of the multiplier
wire c_last_partial[m-1:0];
wire s_last_partial[m-2:0];
buf (c_last_partial[0], 0);
genvar l;
generate
for (l = 0; l < m - 1; l = l + 1) begin
FACell c_last (
c_last_partial[l+1],
s_last_partial[l],
c_partial[(n-1)*m+l],
s_partial[(n-1)*m+l+1],
c_last_partial[l]
);
end
endgenerate
// product bits from first and middle cells
generate
for (i = 0; i < n; i = i + 1) begin
buf (product[i], s_partial[m*i]);
end
endgenerate
// product bits from the last line of cells
generate
for (i = n; i < n + m - 1; i = i + 1) begin
buf (product[i], s_last_partial[i-n]);
end
endgenerate
// msb of product
buf (product[m+n-1], c_last_partial[m-2]);
endmodule
| 6.87285 |
module top;
wire [31:0] p;
reg [15:0] a;
reg [15:0] x;
ArrayMultiplier #(
.m(16),
.n(16)
) am (
p,
a,
x
);
initial $monitor("a=%b,x=%b,p=%b", a, x, p);
initial begin
a = 16'b110111;
x = 16'b11111;
end
endmodule
| 6.919222 |
module array_ctrl (
input clk,
input bottom,
input [5:0] vga_x,
input reset,
input key_en,
input [7:0] key_data,
input [7:0] ran_data,
input [5:0] ran_x,
output [7:0] v_ascii,
output pause,
output reg [3:0] score_l,
output reg [3:0] score_h,
output [9:0] LEDR,
output reg [2:0] heart
);
reg [7:0] asciiarray[63:0]; //每一列的ASCII值
reg [5:0] letter_vaddr[25:0]; //村26个字母的列信息
wire [7:0] key_tag; //键盘字符对应的下标(0到25)
wire [5:0] key_x; //
wire [7:0] ran_tag; //随机字符对应的下标(0到25)
wire p_pause;
reg p_score;
assign v_ascii = asciiarray[vga_x];
assign key_tag = key_data - 8'h41;
assign key_x = letter_vaddr[key_tag];
assign ran_tag = ran_data - 8'h41;
assign p_pause = (key_data == 8'hFF);
assign pause = p_pause | (heart == 0);
assign LEDR[0] = key_en;
assign LEDR[1] = pause;
initial begin
heart = 3;
end
always @(negedge clk) begin
if (pause == 0) begin
if (key_en) begin
if (letter_vaddr[key_tag] != 0) begin
asciiarray[key_x] = 8'h00;
letter_vaddr[key_tag] = 6'b000000;
/* 分数计算 */
if (p_score == 1'b0) begin
score_l = score_l + 1;
p_score = 1'b1;
if (score_l == 10) begin
score_l = 0;
score_h = score_h + 1;
if (score_h == 10) score_h = 0;
end
end
end
end else p_score = 1'b0;
if(letter_vaddr[ran_tag] == 0 && key_en == 0) //不存在该字母，增加
begin
asciiarray[ran_x] = ran_data;
letter_vaddr[ran_tag] = ran_x;
end
end
end
//减少生命
always @(posedge bottom) begin
heart = heart - 1;
end
endmodule
| 7.073986 |
module Array_Mult_Dataflow (
a,
b,
out
);
input [1:0] a, b;
output [3:0] out;
assign out[0] = a[0] & b[0];
assign out[1] = (a[0] & b[1]) ^ (a[1] & b[0]);
assign out[2] = (a[1] & b[1]) ^ ((a[0] & b[1]) & (a[1] & b[0]));
assign out[3] = (a[1] & b[1]) & ((a[0] & b[1]) & (a[1] & b[0]));
endmodule
| 7.730166 |
module array_key (
input wire clk,
input wire rst_n,
input wire [3:0] row,
output wire [3:0] col,
output wire [2:0] addr,
output wire [7:0] seg_n
);
wire clk_20K;
wire [4:0] key_val;
clk_div clk_div_inst (
.clk (clk),
.rst_n (rst_n),
.clk_20K (clk_20K)
);
key16_1 key16_1_inst (
.clk (clk_20K),
.rst_n (rst_n),
.row (row),
.col (col),
.key_val (key_val)
);
encoder encoder_inst (
.data (key_val),
.seg_n(seg_n)
);
assign addr = 3'd0;
endmodule
| 7.343763 |
module Array_KeyBoard #(
parameter NUM_FOR_200HZ = 60000
) (
input clk_in,
input rst_n_in,
input [3:0] col,
output reg [3:0] row,
output reg [15:0] key_out,
output [15:0] key_pulse
);
localparam STATE0 = 2'b00;
localparam STATE1 = 2'b01;
localparam STATE2 = 2'b10;
localparam STATE3 = 2'b11;
//count for clk_200hz
reg [15:0] cnt;
reg clk_200hz;
always @(posedge clk_in or negedge rst_n_in) begin
if (!rst_n_in) begin
cnt <= 16'd0;
clk_200hz <= 1'b0;
end else begin
if (cnt >= ((NUM_FOR_200HZ >> 1) - 1)) begin
cnt <= 16'd0;
clk_200hz <= ~clk_200hz;
end else begin
cnt <= cnt + 1'b1;
clk_200hz <= clk_200hz;
end
end
end
reg [1:0] c_state;
always @(posedge clk_200hz or negedge rst_n_in) begin
if (!rst_n_in) begin
c_state <= STATE0;
row <= 4'b1110;
end else begin
case (c_state)
STATE0: begin
c_state <= STATE1;
row <= 4'b1101;
end
STATE1: begin
c_state <= STATE2;
row <= 4'b1011;
end
STATE2: begin
c_state <= STATE3;
row <= 4'b0111;
end
STATE3: begin
c_state <= STATE0;
row <= 4'b1110;
end
default: begin
c_state <= STATE0;
row <= 4'b1110;
end
endcase
end
end
always @(negedge clk_200hz or negedge rst_n_in) begin
if (!rst_n_in) begin
key_out <= 16'hffff;
end else begin
case (c_state)
STATE0: key_out[3:0] <= col;
STATE1: key_out[7:4] <= col;
STATE2: key_out[11:8] <= col;
STATE3: key_out[15:12] <= col;
default: key_out <= 16'hffff;
endcase
end
end
reg [15:0] key_out_r;
//Register key_out_r, lock key_out to next clk
always @(posedge clk_in or negedge rst_n_in)
if (!rst_n_in) key_out_r <= 16'hffff;
else key_out_r <= key_out;
//wire [15:0] key_pulse;
//Detect the negedge of key_out, generate pulse
assign key_pulse = key_out_r & (~key_out);
endmodule
| 6.912891 |
module FACell (
output Cnext,
Sthis,
input xn,
am,
Cthis
);
wire t1, t2, t3;
xor (t1, am, xn);
and (t2, t1, Cthis);
and (t3, am, xn);
or (Cnext, t2, t3);
xor (Sthis, t1, Cthis);
endmodule
| 7.106661 |
module ArrayMultiplier (
product,
a,
x
);
parameter m = 32;
parameter n = 32;
output [m+n-1:0] product;
input [m-1:0] a;
input [n-1:0] x;
wire c_partial[m*n:0];
wire s_partial[m*n:0];
// first line of the multiplier
genvar i;
generate
for (i = 0; i < m; i = i + 1) begin
Cell c_first (
.Cnext(c_partial[i]),
.Sthis(s_partial[i]),
.xn(x[0]),
.am(a[i]),
.Slast(1'b0),
.Cthis(1'b0)
);
end
endgenerate
// middle lines of the multiplier - except last column
genvar j, k;
generate
for (k = 0; k < n - 1; k = k + 1) begin
for (j = 0; j < m - 1; j = j + 1) begin
Cell c_middle (
c_partial[m*(k+1)+j],
s_partial[m*(k+1)+j],
x[k+1],
a[j],
s_partial[m*(k+1)+j-m+1],
c_partial[m*(k+1)+j-m]
);
end
end
endgenerate
// middle lines of the multiplier - only last column
genvar z;
generate
for (z = 0; z < n - 1; z = z + 1) begin
Cell c_middle_last_col (
c_partial[m*(z+1)+(m-1)],
s_partial[m*(z+1)+(m-1)],
x[z+1],
a[+(m-1)],
1'b0,
c_partial[m*(z+1)+(m-1)-m]
);
end
endgenerate
// last line of the multiplier
wire c_last_partial[m-1:0];
wire s_last_partial[m-2:0];
buf (c_last_partial[0], 0);
genvar l;
generate
for (l = 0; l < m - 1; l = l + 1) begin
FACell c_last (
c_last_partial[l+1],
s_last_partial[l],
c_partial[(n-1)*m+l],
s_partial[(n-1)*m+l+1],
c_last_partial[l]
);
end
endgenerate
// product bits from first and middle cells
generate
for (i = 0; i < n; i = i + 1) begin
buf (product[i], s_partial[m*i]);
end
endgenerate
// product bits from the last line of cells
generate
for (i = n; i < n + m - 1; i = i + 1) begin
buf (product[i], s_last_partial[i-n]);
end
endgenerate
// msb of product
buf (product[m+n-1], c_last_partial[m-2]);
endmodule
| 6.87285 |
module ADD_HALF (
output cout,
output sum,
input a,
input b
);
xor (sum, a, b);
and (cout, a, b);
endmodule
| 7.323935 |
module FACell (
output Cnext,
Sthis,
input xn,
am,
Cthis
);
wire t1, t2, t3;
xor (t1, am, xn);
and (t2, t1, Cthis);
and (t3, am, xn);
or (Cnext, t2, t3);
xor (Sthis, t1, Cthis);
endmodule
| 7.106661 |
module ArrayMultiplier (
clk,
product_reg,
a,
x
);
parameter m = 24;
parameter n = 24;
output reg [m+n-1:0] product_reg;
wire [m+n-1:0] product;
input [m-1:0] a;
input [n-1:0] x;
input clk;
wire [m*n:0] c_partial;
wire [m*n:0] s_partial;
// first line of the multiplier
genvar i;
generate
for (i = 0; i < m; i = i + 1) begin
Cell c_first (
.Cnext(c_partial[i]),
.Sthis(s_partial[i]),
.xn(x[0]),
.am(a[i]),
.Slast(1'b0),
.Cthis(1'b0)
);
end
endgenerate
// middle lines of the multiplier - except last column
genvar j, k;
generate
for (k = 0; k < n - 1; k = k + 1) begin
for (j = 0; j < m - 1; j = j + 1) begin
Cell c_middle (
c_partial[m*(k+1)+j],
s_partial[m*(k+1)+j],
x[k+1],
a[j],
s_partial[m*(k+1)+j-m+1],
c_partial[m*(k+1)+j-m]
);
end
end
endgenerate
// middle lines of the multiplier - only last column
genvar z;
generate
for (z = 0; z < n - 1; z = z + 1) begin
Cell c_middle_last_col (
c_partial[m*(z+1)+(m-1)],
s_partial[m*(z+1)+(m-1)],
x[z+1],
a[+(m-1)],
1'b0,
c_partial[m*(z+1)+(m-1)-m]
);
end
endgenerate
reg [m*n:0] c_partial_reg;
reg [m*n:0] s_partial_reg;
always @(posedge clk) begin
c_partial_reg[m*n : 0] = c_partial[m*n : 0];
s_partial_reg[m*n : 0] = s_partial[m*n : 0];
end
// last line of the multiplier
wire c_last_partial[m-1:0];
wire s_last_partial[m-2:0];
buf (c_last_partial[0], 0);
genvar l1;
generate
for (l1 = 0; l1 < (m - 1); l1 = l1 + 1) begin
FACell c_last (
c_last_partial[l1+1],
s_last_partial[l1],
c_partial_reg[(n-1)*m+l1],
s_partial_reg[(n-1)*m+l1+1],
c_last_partial[l1]
);
end
endgenerate
genvar l2;
generate
for (l2 = (m + 1) / 2; l2 < m - 1; l2 = l2 + 1) begin
FACell c_last (
c_last_partial[l2+1],
s_last_partial[l2],
c_partial_reg[(n-1)*m+l2],
s_partial_reg[(n-1)*m+l2+1],
c_last_partial[l2]
);
end
endgenerate
// product bits from first and middle cells
generate
for (i = 0; i < n; i = i + 1) begin
buf (product[i], s_partial_reg[m*i]);
end
endgenerate
// product bits from the last line of cells
generate
for (i = n; i < n + m - 1; i = i + 1) begin
buf (product[i], s_last_partial[i-n]);
end
endgenerate
// msb of product
buf (product[m+n-1], c_last_partial[m-2]);
always @(posedge clk) begin
product_reg[m+n-1 : 0] = product[m+n-1 : 0];
end
endmodule
| 6.87285 |
module array_multiplier_4_bits (
input [7:0] SW,
//a 0-3 b 4-7
output [7:0] LEDR,
output [0:6] HEX0,
HEX2,
HEX4,
HEX5
);
wire [39:0] w;
and a1 (w[0], SW[0], SW[4]);
and a2 (w[1], SW[1], SW[4]);
and a3 (w[2], SW[2], SW[4]);
and a4 (w[3], SW[3], SW[4]);
and a5 (w[4], SW[0], SW[5]);
and a6 (w[5], SW[1], SW[5]);
and a7 (w[6], SW[2], SW[5]);
and a8 (w[7], SW[3], SW[5]);
and a9 (w[8], SW[0], SW[6]);
and a10 (w[9], SW[1], SW[6]);
and a11 (w[10], SW[2], SW[6]);
and a12 (w[11], SW[3], SW[6]);
and a13 (w[12], SW[0], SW[7]);
and a14 (w[13], SW[1], SW[7]);
and a15 (w[14], SW[2], SW[7]);
and a16 (w[15], SW[3], SW[7]);
assign LEDR[0] = w[0];
//full adders instatiations
fulladder a17 (
1'b0,
w[1],
w[4],
w[16],
w[17]
);
fulladder a18 (
1'b0,
w[2],
w[5],
w[18],
w[19]
);
fulladder a19 (
1'b0,
w[3],
w[6],
w[20],
w[21]
);
fulladder a20 (
w[8],
w[17],
w[18],
w[22],
w[23]
);
fulladder a21 (
w[9],
w[19],
w[20],
w[24],
w[25]
);
fulladder a22 (
w[10],
w[7],
w[21],
w[26],
w[27]
);
fulladder a23 (
w[12],
w[23],
w[24],
w[28],
w[29]
);
fulladder a24 (
w[13],
w[25],
w[26],
w[30],
w[31]
);
fulladder a25 (
w[14],
w[11],
w[27],
w[32],
w[33]
);
fulladder a26 (
1'b0,
w[29],
w[30],
w[34],
w[35]
);
fulladder a27 (
w[31],
w[32],
w[35],
w[36],
w[37]
);
fulladder a28 (
w[15],
w[33],
w[37],
w[38],
w[39]
);
assign LEDR[1] = w[16];
assign LEDR[2] = w[22];
assign LEDR[3] = w[28];
assign LEDR[4] = w[34];
assign LEDR[5] = w[36];
assign LEDR[6] = w[38];
assign LEDR[7] = w[39];
display d1 (
SW[3:0],
HEX0
);
display d2 (
SW[7:4],
HEX2
);
display d3 (
LEDR[7:0] % 16,
HEX4
);
display d4 (
LEDR[7:0] / 16,
HEX5
);
endmodule
| 6.678924 |
module fulladder (
input a,
b,
c,
output s,
ca
);
assign s = (a ^ b ^ c);
assign ca = ((a & b) | (b & c) | (c & a));
endmodule
| 7.454465 |
module array_multiplier_4_bits_board (
input [7:0] SW,
output [7:0] LEDR,
output [6:0] HEX0,
HEX2,
HEX4,
HEX5
);
assign LEDR = SW;
wire [7:0] out;
array_multiplier_4_bits(
SW[7:4], SW[3:0], out
);
decoder_hex_16 A (
SW[7:4],
HEX2
);
decoder_hex_16 B (
SW[3:0],
HEX0
);
decoder_hex_16 P0 (
out % 16,
HEX4
);
decoder_hex_16 P1 (
out / 16,
HEX5
);
endmodule
| 6.678924 |
module array_multiplier_gen (
a,
b,
p
);
// inputs
input [3:0] a;
input [3:0] b;
// outputs
output [7:0] p;
wire [7:0] temp_and0;
wire [7:0] temp_and1;
wire [7:0] temp_and2;
wire [7:0] temp_and3;
// ---------------------- design implementation ------------------------------
// produce all the summands: evaluate the AND rows
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : generate_AND0
if (i > 3) begin
assign temp_and0[i] = 1'b0;
end else begin
assign temp_and0[i] = (a[i] & b[0]);
end
end
endgenerate
genvar j;
generate
for (j = 0; j < 8; j = j + 1) begin : generate_AND1
if ((j < 1) || (j > 4)) begin
assign temp_and1[j] = 1'b0;
end else begin
assign temp_and1[j] = (a[j-1] & b[1]);
end
end
endgenerate
genvar k;
generate
for (k = 0; k < 8; k = k + 1) begin : generate_AND2
if ((k < 2) || (k > 5)) begin
assign temp_and2[k] = 1'b0;
end else begin
assign temp_and2[k] = (a[k-2] & b[2]);
end
end
endgenerate
genvar l;
generate
for (l = 0; l < 8; l = l + 1) begin : generate_AND3
if ((l < 3) || (l > 6)) begin
assign temp_and3[l] = 1'b0;
end else begin
assign temp_and3[l] = (a[l-3] & b[3]);
end
end
endgenerate
// compute the final product: sum all
assign p = temp_and0 + temp_and1 + temp_and2 + temp_and3;
endmodule
| 6.678924 |
module Add_full_0 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_0 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_1791 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X2 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX1 U2 (
.A(w2),
.Z(n1)
);
CIVX2 U3 (
.A(w3),
.Z(n2)
);
endmodule
| 6.995469 |
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