code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module aq_mp_rst_top (
ciu_rst_b,
clkgen_rst_b,
core0_rst_b,
forever_cpuclk,
pad_cpu_rst_b,
pad_yy_dft_clk_rst_b,
pad_yy_mbist_mode,
pad_yy_scan_mode,
pad_yy_scan_rst_b,
sync_sys_apb_rst_b,
sys_apb_clk,
sys_apb_rst_b
);
// &Ports; @23
input forever_cpuclk;
input pad_cpu_rst_b;
input pad_yy_dft_clk_rst_b;
input pad_yy_mbist_mode;
input pad_yy_scan_mode;
input pad_yy_scan_rst_b;
input sys_apb_clk;
input sys_apb_rst_b;
output ciu_rst_b;
output clkgen_rst_b;
output core0_rst_b;
output sync_sys_apb_rst_b;
// &Regs; @24
reg ciu_rst_ff_1st;
reg ciu_rst_ff_2nd;
reg ciu_rst_ff_3rd;
reg sys_apb_rst_ff_1st;
// &Wires; @25
wire async_apb_rst_b;
wire async_ciu_rst_b;
wire ciu_rst_b;
wire clkgen_rst_b;
wire core0_rst_b;
wire forever_cpuclk;
wire pad_cpu_rst_b;
wire pad_yy_dft_clk_rst_b;
wire pad_yy_mbist_mode;
wire pad_yy_scan_mode;
wire pad_yy_scan_rst_b;
wire sync_sys_apb_rst_b;
wire sys_apb_clk;
wire sys_apb_rst_b;
//assign ciu_rre[3:0] = 4'b1;
////cpu reset
//assign cpu0_rst_b = pad_core0_rst_b & ciu_rre[0] | pad_yy_mbist_mode;
//
//always @(posedge forever_cpuclk or negedge cpu0_rst_b)
//begin
// if(!cpu0_rst_b)
// begin
// cpu0_rst_ff_1st <= 1'b0;
// cpu0_rst_ff_2nd <= 1'b0;
// cpu0_rst_ff_3rd <= 1'b0;
// end
// else
// begin
// cpu0_rst_ff_1st <= 1'b1;
// cpu0_rst_ff_2nd <= cpu0_rst_ff_1st;
// cpu0_rst_ff_3rd <= cpu0_rst_ff_2nd;
// end
//end
//
//assign core0_rst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : cpu0_rst_ff_3rd;
//
//
//
//
assign async_ciu_rst_b = pad_cpu_rst_b & !pad_yy_mbist_mode;
always @(posedge forever_cpuclk or negedge async_ciu_rst_b) begin
if (!async_ciu_rst_b) begin
ciu_rst_ff_1st <= 1'b0;
ciu_rst_ff_2nd <= 1'b0;
ciu_rst_ff_3rd <= 1'b0;
end else begin
ciu_rst_ff_1st <= 1'b1;
ciu_rst_ff_2nd <= ciu_rst_ff_1st;
ciu_rst_ff_3rd <= ciu_rst_ff_2nd;
end
end
assign async_apb_rst_b = sys_apb_rst_b & !pad_yy_mbist_mode;
always @(posedge sys_apb_clk or negedge async_apb_rst_b) begin
if (!async_apb_rst_b) sys_apb_rst_ff_1st <= 1'b0;
else sys_apb_rst_ff_1st <= 1'b1;
end
// &Force("output","ciu_rst_b"); @149
assign ciu_rst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : ciu_rst_ff_3rd;
assign core0_rst_b = ciu_rst_b;
assign sync_sys_apb_rst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : sys_apb_rst_ff_1st;
assign clkgen_rst_b = pad_yy_scan_mode ? pad_yy_dft_clk_rst_b : ciu_rst_ff_3rd;
//assign jtg_trst_b_bf_flop = async_ciu_rst_b & pad_had_jtg_trst_b ;
//assign trst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : jtg_trst_b_bf_flop;
// &ModuleEnd; @160
endmodule
| 6.814271 |
module aq_prio (
clk,
rst_b,
valid,
clr,
sel
);
parameter NUM = 2;
input clk;
input rst_b;
input [NUM-1:0] valid;
input clr;
output [NUM-1:0] sel;
reg [NUM-1:0] prio [NUM-1:0];
reg [NUM-1:0] unused [NUM-1:0];
wire [NUM-1:0] sel;
wire [NUM-1:0] clr_bus;
assign clr_bus[NUM-1:0] = {NUM{clr}} & sel[NUM-1:0];
genvar i;
generate
for (i = 0; i < NUM; i = i + 1) begin : PRIO_MATRIX_GEN
always @(posedge clk or negedge rst_b) begin
if (!rst_b) {prio[i][NUM-1:0], unused[i][NUM-1:0]} <= {{NUM{1'b0}}, {NUM{1'b1}}} << i;
else if (|clr_bus[NUM-1:0]) begin
prio[i][NUM-1:0] <= (clr_bus[NUM-1:0] == ({{(NUM-1){1'b0}},1'b1}<<i))
? ~clr_bus[NUM-1:0]
: prio[i][NUM-1:0] &~clr_bus[NUM-1:0];
end
end
end
endgenerate
generate
for (i = 0; i < NUM; i = i + 1) begin : SEL_GEN
assign sel[i] = valid[i] && !(|(valid[NUM-1:0] & prio[i][NUM-1:0]));
end
endgenerate
endmodule
| 6.5303 |
module aq_ram19x11 (
input CLKA,
input WEA,
input [10:0] ADDRA,
input [18:0] DINA,
input CLKB,
input [10:0] ADDRB,
output [18:0] DOUTB
);
reg [18:0] array[0:2048];
always @(posedge CLKA) begin
if (WEA) begin
array[ADDRA[10:0]] = DINA[18:0];
end
end
reg [18:0] data;
always @(posedge CLKB) begin
data[18:0] = array[ADDRB[10:0]];
end
assign DOUTB[18:0] = data[18:0];
endmodule
| 6.733145 |
module aq_ram25x16 (
input CLKA,
input WEA,
input [15:0] ADDRA,
input [24:0] DINA,
input CLKB,
input [15:0] ADDRB,
output [24:0] DOUTB
);
reg [24:0] array[0:2048];
always @(posedge CLKA) begin
if (WEA) begin
array[ADDRA[10:0]] = DINA[24:0];
end
end
reg [24:0] data;
always @(posedge CLKB) begin
data[24:0] = array[ADDRB[10:0]];
end
assign DOUTB[24:0] = data[24:0];
endmodule
| 7.737306 |
module aq_rtu_int (
cp0_rtu_int_vld,
dp_int_ex2_inst_split,
dtu_rtu_int_mask,
int_retire_int_vec,
int_retire_int_vld
);
// &Ports; @25
input [14:0] cp0_rtu_int_vld;
input dp_int_ex2_inst_split;
input dtu_rtu_int_mask;
output [4 : 0] int_retire_int_vec;
output int_retire_int_vld;
// &Regs; @26
reg [4 : 0] int_vec;
// &Wires; @27
wire [ 14:0] cp0_rtu_int_vld;
wire dp_int_ex2_inst_split;
wire dtu_rtu_int_mask;
wire [4 : 0] int_retire_int_vec;
wire int_retire_int_vld;
wire int_vld;
wire [ 14:0] int_vld_raw;
//==========================================================
// Int Source
//==========================================================
assign int_vld_raw[14:0] = cp0_rtu_int_vld[14:0];
// &CombBeg; @35
always @(int_vld_raw[14:0]) begin
casez (int_vld_raw[14:0])
15'b1??????????????: int_vec[4:0] = 5'd16; // mcip
15'b01?????????????: int_vec[4:0] = 5'd18; // mhip
15'b001????????????: int_vec[4:0] = 5'd11; // meip
15'b0001???????????: int_vec[4:0] = 5'd3; // msip
15'b00001??????????: int_vec[4:0] = 5'd7; // mtip
15'b000001?????????: int_vec[4:0] = 5'd9; // seip
15'b0000001????????: int_vec[4:0] = 5'd1; // ssip
15'b00000001???????: int_vec[4:0] = 5'd5; // stip
15'b000000001??????: int_vec[4:0] = 5'd17; // moip
15'b0000000001?????: int_vec[4:0] = 5'd16; // mcip
15'b00000000001????: int_vec[4:0] = 5'd18; // mhip
15'b000000000001???: int_vec[4:0] = 5'd9; // seip
15'b0000000000001??: int_vec[4:0] = 5'd1; // ssip
15'b00000000000001?: int_vec[4:0] = 5'd5; // stip
15'b000000000000001: int_vec[4:0] = 5'd17; // moip
default: int_vec[4:0] = {5{1'bx}};
endcase
// &CombEnd; @54
end
//==========================================================
// Int Judge
//==========================================================
assign int_vld = |int_vld_raw[14:0] && !dtu_rtu_int_mask && !dp_int_ex2_inst_split;
//==========================================================
// Output
//==========================================================
assign int_retire_int_vld = int_vld;
assign int_retire_int_vec[4:0] = int_vec[4:0];
// &ModuleEnd; @69
endmodule
| 7.774232 |
module aq_serdes_n_to_1 (
input ioclk,
input gclk,
input reset,
input [9:0] datain,
output iob_data_out
);
wire cascade_di;
wire cascade_ti;
wire cascade_do;
wire cascade_to;
reg toggle;
reg [4:0] datain_d;
reg rst_inst;
always @(posedge gclk or posedge reset) begin
if (reset) begin
rst_inst <= 1'b1;
end else begin
rst_inst <= 1'b0;
end
end
OSERDESE2 #(
.DATA_WIDTH (10),
.TRISTATE_WIDTH(1),
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("SDR"),
.SERDES_MODE ("MASTER")
) oserdes_m (
.RST (rst_inst),
.CLK (ioclk),
.CLKDIV(gclk),
.OQ (iob_data_out),
.D8 (datain[7]),
.D7 (datain[6]),
.D6 (datain[5]),
.D5 (datain[4]),
.D4 (datain[3]),
.D3 (datain[2]),
.D2 (datain[1]),
.D1 (datain[0]),
.OCE(1'b1),
.TQ (),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TCE(1'b0),
.TBYTEIN (1'b0),
.TBYTEOUT (),
.TFB (),
.SHIFTIN1 (cascade_di),
.SHIFTIN2 (cascade_ti),
.SHIFTOUT1(),
.SHIFTOUT2()
);
OSERDESE2 #(
.DATA_WIDTH (10),
.TRISTATE_WIDTH(1),
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("SDR"),
.SERDES_MODE ("SLAVE")
) oserdes_s (
.RST (rst_inst),
.CLK (ioclk),
.CLKDIV(gclk),
.D8 (1'b0),
.D7 (1'b0),
.D6 (1'b0),
.D5 (1'b0),
.D4 (datain[9]),
.D3 (datain[8]),
.D2 (1'b0),
.D1 (1'b0),
.OCE(1'b1),
.TQ (),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TCE(1'b0),
.TBYTEIN (1'b0),
.TBYTEOUT (),
.TFB (),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.SHIFTOUT1(cascade_di),
.SHIFTOUT2(cascade_ti)
);
endmodule
| 7.158293 |
module aq_sigcap (
// --------------------------------------------------
// AXI4 Lite Interface
// --------------------------------------------------
// Reset, Clock
input S_AXI_ARESETN,
input S_AXI_ACLK,
// Write Address Channel
input [15:0] S_AXI_AWADDR,
input [ 3:0] S_AXI_AWCACHE, // 4'b0011
input [ 2:0] S_AXI_AWPROT, // 3'b000
input S_AXI_AWVALID,
output S_AXI_AWREADY,
// Write Data Channel
input [31:0] S_AXI_WDATA,
input [ 3:0] S_AXI_WSTRB,
input S_AXI_WVALID,
output S_AXI_WREADY,
// Write Response Channel
output S_AXI_BVALID,
input S_AXI_BREADY,
output [1:0] S_AXI_BRESP,
// Read Address Channel
input [15:0] S_AXI_ARADDR,
input [ 3:0] S_AXI_ARCACHE, // 4'b0011
input [ 2:0] S_AXI_ARPROT, // 3'b000
input S_AXI_ARVALID,
output S_AXI_ARREADY,
// Read Data Channel
output [31:0] S_AXI_RDATA,
output [ 1:0] S_AXI_RRESP,
output S_AXI_RVALID,
input S_AXI_RREADY,
input CAP_CLK,
input [31:0] CAP_DATA
);
wire A_CLK;
wire [ 9:0] A_ADDR;
wire [ 3:0] A_WE;
wire [31:0] A_DO;
wire B_CLK;
wire [ 9:0] B_ADDR;
wire [31:0] B_DI;
// AXI Lite Slave Interface
aq_sigcap_ctl u_aq_sigcap_ctl (
// AXI4 Lite Interface
.ARESETN(S_AXI_ARESETN),
.ACLK (S_AXI_ACLK),
// Write Address Channel
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWCACHE(S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_AWREADY(S_AXI_AWREADY),
// Write Data Channel
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
// Write Response Channel
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_BRESP (S_AXI_BRESP),
// Read Address Channel
.S_AXI_ARADDR (S_AXI_ARADDR),
.S_AXI_ARCACHE(S_AXI_ARCACHE),
.S_AXI_ARPROT (S_AXI_ARPROT),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
// Read Data Channel
.S_AXI_RDATA (S_AXI_RDATA),
.S_AXI_RRESP (S_AXI_RRESP),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
// Local Interface
.CAP_CLK (CAP_CLK),
.CAP_DATA(CAP_DATA[31:0]),
.A_CLK (A_CLK),
.A_ADDR(A_ADDR[9:0]),
.A_WE (A_WE[3:0]),
.A_DO (A_DO[31:0]),
.B_CLK (B_CLK),
.B_ADDR(B_ADDR[9:0]),
.B_DI (B_DI[31:0])
);
aq_sigcap_mem u_aq_sigcap_mem (
.RST(~S_AXI_ARESETN),
.A_CLK (A_CLK),
.A_ADDR(A_ADDR[9:0]),
.A_WE (A_WE[3:0]),
.A_DI (A_DO[31:0]),
.A_DO (),
.B_CLK (B_CLK),
.B_ADDR(B_ADDR[9:0]),
.B_WE (4'd0),
.B_DI (32'd0),
.B_DO (B_DI[31:0])
);
endmodule
| 6.886592 |
module aq_spsram_1024x16 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [9 : 0] A;
input CEN;
input CLK;
input [15:0] D;
input GWEN;
input [15:0] WEN;
output [15:0] Q;
// &Regs; @24
// &Wires; @25
wire [9 : 0] A;
wire CEN;
wire CLK;
wire [ 15:0] D;
wire GWEN;
wire [ 15:0] Q;
wire [ 15:0] WEN;
//**********************************************************
// Parameter Definition
//**********************************************************
parameter ADDR_WIDTH = 10;
parameter DATA_WIDTH = 16;
parameter WE_WIDTH = 16;
// &Force("bus","Q",DATA_WIDTH-1,0); @34
// &Force("bus","WEN",WE_WIDTH-1,0); @35
// &Force("bus","A",ADDR_WIDTH-1,0); @36
// &Force("bus","D",DATA_WIDTH-1,0); @37
//********************************************************
//* FPGA memory *
//********************************************************
// &Instance("aq_f_spsram_1024x16"); @43
aq_f_spsram_1024x16 x_aq_f_spsram_1024x16 (
.A (A),
.CEN (CEN),
.CLK (CLK),
.D (D),
.GWEN(GWEN),
.Q (Q),
.WEN (WEN)
);
// &Instance("aq_tsmc_spsram_1024x16"); @49
// &Instance("aq_umc_spsram_1024x16"); @61
// &ModuleEnd; @65
endmodule
| 7.605262 |
module aq_spsram_1024x64 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [9 : 0] A;
input CEN;
input CLK;
input [63:0] D;
input GWEN;
input [63:0] WEN;
output [63:0] Q;
// &Regs; @24
// &Wires; @25
wire [9 : 0] A;
wire CEN;
wire CLK;
wire [ 63:0] D;
wire GWEN;
wire [ 63:0] Q;
wire [ 63:0] WEN;
//**********************************************************
// Parameter Definition
//**********************************************************
parameter ADDR_WIDTH = 10;
parameter DATA_WIDTH = 64;
parameter WE_WIDTH = 64;
// &Force("bus","Q",DATA_WIDTH-1,0); @34
// &Force("bus","WEN",WE_WIDTH-1,0); @35
// &Force("bus","A",ADDR_WIDTH-1,0); @36
// &Force("bus","D",DATA_WIDTH-1,0); @37
// //********************************************************
// //* FPGA memory *
// //********************************************************
// &Instance("aq_f_spsram_1024x64"); @43
aq_f_spsram_1024x64 x_aq_f_spsram_1024x64 (
.A (A),
.CEN (CEN),
.CLK (CLK),
.D (D),
.GWEN(GWEN),
.Q (Q),
.WEN (WEN)
);
// &Instance("aq_umc_spsram_1024x64"); @49
// &Instance("aq_tsmc_spsram_1024x64"); @55
// &ModuleEnd; @58
endmodule
| 7.605262 |
module aq_spsram_128x8 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [6:0] A;
input CEN;
input CLK;
input [7:0] D;
input GWEN;
input [7:0] WEN;
output [7:0] Q;
// &Regs; @24
// &Wires; @25
wire [6:0] A;
wire CEN;
wire CLK;
wire [7:0] D;
wire GWEN;
wire [7:0] Q;
wire [7:0] WEN;
//**********************************************************
// Parameter Definition
//**********************************************************
parameter ADDR_WIDTH = 7;
parameter DATA_WIDTH = 8;
parameter WE_WIDTH = 8;
// &Force("bus","Q",DATA_WIDTH-1,0); @34
// &Force("bus","WEN",WE_WIDTH-1,0); @35
// &Force("bus","A",ADDR_WIDTH-1,0); @36
// &Force("bus","D",DATA_WIDTH-1,0); @37
// //********************************************************
// //* FPGA memory *
// //********************************************************
// &Instance("aq_f_spsram_128x8"); @43
aq_f_spsram_128x8 x_aq_f_spsram_128x8 (
.A (A),
.CEN (CEN),
.CLK (CLK),
.D (D),
.GWEN(GWEN),
.Q (Q),
.WEN (WEN)
);
// &Instance("aq_umc_spsram_128x8"); @49
// &Instance("aq_tsmc_spsram_128x8"); @55
// &ModuleEnd; @58
endmodule
| 8.40252 |
module aq_spsram_2048x32 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [10:0] A;
input CEN;
input CLK;
input [31:0] D;
input GWEN;
input [31:0] WEN;
output [31:0] Q;
// &Regs; @24
// &Wires; @25
wire [10:0] A;
wire CEN;
wire CLK;
wire [31:0] D;
wire GWEN;
wire [31:0] Q;
wire [31:0] WEN;
//**********************************************************
// Parameter Definition
//**********************************************************
parameter ADDR_WIDTH = 11;
parameter DATA_WIDTH = 32;
parameter WE_WIDTH = 32;
// &Force("bus","Q",DATA_WIDTH-1,0); @34
// &Force("bus","WEN",WE_WIDTH-1,0); @35
// &Force("bus","A",ADDR_WIDTH-1,0); @36
// &Force("bus","D",DATA_WIDTH-1,0); @37
//********************************************************
//* FPGA memory *
//********************************************************
// &Instance("aq_f_spsram_2048x32"); @43
aq_f_spsram_2048x32 x_aq_f_spsram_2048x32 (
.A (A),
.CEN (CEN),
.CLK (CLK),
.D (D),
.GWEN(GWEN),
.Q (Q),
.WEN (WEN)
);
// &Instance("aq_tsmc_spsram_2048x32"); @49
// &Instance("aq_umc_spsram_2048x32"); @61
// &ModuleEnd; @65
endmodule
| 8.19862 |
module aq_spsram_256x59 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [7 : 0] A;
input CEN;
input CLK;
input [58:0] D;
input GWEN;
input [58:0] WEN;
output [58:0] Q;
// &Regs; @24
// &Wires; @25
wire [7 : 0] A;
wire CEN;
wire CLK;
wire [ 58:0] D;
wire GWEN;
wire [ 58:0] Q;
wire [ 58:0] WEN;
//**********************************************************
// Parameter Definition
//**********************************************************
parameter ADDR_WIDTH = 8;
parameter DATA_WIDTH = 59;
parameter WE_WIDTH = 59;
// &Force("bus","Q",DATA_WIDTH-1,0); @34
// &Force("bus","WEN",WE_WIDTH-1,0); @35
// &Force("bus","A",ADDR_WIDTH-1,0); @36
// &Force("bus","D",DATA_WIDTH-1,0); @37
//********************************************************
//* FPGA memory *
//********************************************************
// &Instance("aq_f_spsram_256x59"); @43
aq_f_spsram_256x59 x_aq_f_spsram_256x59 (
.A (A),
.CEN (CEN),
.CLK (CLK),
.D (D),
.GWEN(GWEN),
.Q (Q),
.WEN (WEN)
);
// &Instance("aq_tsmc_spsram_256x59"); @49
// &Instance("aq_umc_spsram_256x59"); @61
// &ModuleEnd; @65
endmodule
| 7.115472 |
module aq_spsram_64x58 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [5 : 0] A;
input CEN;
input CLK;
input [57:0] D;
input GWEN;
input [57:0] WEN;
output [57:0] Q;
// &Regs; @24
// &Wires; @25
wire [5 : 0] A;
wire CEN;
wire CLK;
wire [ 57:0] D;
wire GWEN;
wire [ 57:0] Q;
wire [ 57:0] WEN;
//**********************************************************
// Parameter Definition
//**********************************************************
parameter ADDR_WIDTH = 6;
parameter DATA_WIDTH = 58;
parameter WE_WIDTH = 58;
// &Force("bus","Q",DATA_WIDTH-1,0); @34
// &Force("bus","WEN",WE_WIDTH-1,0); @35
// &Force("bus","A",ADDR_WIDTH-1,0); @36
// &Force("bus","D",DATA_WIDTH-1,0); @37
// //********************************************************
// //* FPGA memory *
// //********************************************************
// &Instance("aq_f_spsram_64x58"); @43
aq_f_spsram_64x58 x_aq_f_spsram_64x58 (
.A (A),
.CEN (CEN),
.CLK (CLK),
.D (D),
.GWEN(GWEN),
.Q (Q),
.WEN (WEN)
);
// &Instance("aq_umc_spsram_64x58"); @49
// &Instance("aq_tsmc_spsram_64x58"); @55
// &ModuleEnd; @58
endmodule
| 7.947531 |
module aq_spsram_64x88 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [5 : 0] A;
input CEN;
input CLK;
input [87:0] D;
input GWEN;
input [87:0] WEN;
output [87:0] Q;
// &Regs; @24
// &Wires; @25
wire [5 : 0] A;
wire CEN;
wire CLK;
wire [ 87:0] D;
wire GWEN;
wire [ 87:0] Q;
wire [ 87:0] WEN;
//**********************************************************
// Parameter Definition
//**********************************************************
parameter ADDR_WIDTH = 6;
parameter DATA_WIDTH = 88;
parameter WE_WIDTH = 88;
// &Force("bus","Q",DATA_WIDTH-1,0); @34
// &Force("bus","WEN",WE_WIDTH-1,0); @35
// &Force("bus","A",ADDR_WIDTH-1,0); @36
// &Force("bus","D",DATA_WIDTH-1,0); @37
//********************************************************
//* FPGA memory *
//********************************************************
//{WEN[135:132],WEN[131:99],WEN[98:66],WEN[65:33],WEN[32:0]}
// &Instance("aq_f_spsram_64x88"); @44
aq_f_spsram_64x88 x_aq_f_spsram_64x88 (
.A (A),
.CEN (CEN),
.CLK (CLK),
.D (D),
.GWEN(GWEN),
.Q (Q),
.WEN (WEN)
);
// &Instance("aq_tsmc_spsram_64x88"); @50
// &Instance("aq_umc_spsram_64x88"); @62
// &ModuleEnd; @66
endmodule
| 7.947531 |
module aq_spsram_64x98 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [5 : 0] A;
input CEN;
input CLK;
input [97:0] D;
input GWEN;
input [97:0] WEN;
output [97:0] Q;
// &Regs; @24
// &Wires; @25
wire [5 : 0] A;
wire CEN;
wire CLK;
wire [ 97:0] D;
wire GWEN;
wire [ 97:0] Q;
wire [ 97:0] WEN;
//**********************************************************
// Parameter Definition
//**********************************************************
parameter ADDR_WIDTH = 6;
parameter DATA_WIDTH = 98;
parameter WE_WIDTH = 98;
// &Force("bus","Q",DATA_WIDTH-1,0); @34
// &Force("bus","WEN",WE_WIDTH-1,0); @35
// &Force("bus","A",ADDR_WIDTH-1,0); @36
// &Force("bus","D",DATA_WIDTH-1,0); @37
//********************************************************
//* FPGA memory *
//********************************************************
//{WEN[111:56],WEN[55:0]}
// &Instance("aq_f_spsram_64x98"); @44
aq_f_spsram_64x98 x_aq_f_spsram_64x98 (
.A (A),
.CEN (CEN),
.CLK (CLK),
.D (D),
.GWEN(GWEN),
.Q (Q),
.WEN (WEN)
);
// &Instance("aq_tsmc_spsram_64x98"); @50
// &Instance("aq_umc_spsram_64x98"); @62
// &ModuleEnd; @66
endmodule
| 7.947531 |
module aq_vdsp_8_bit_ff1 (
out,
rem,
src,
zero
);
// &Ports; @18
input [7:0] src;
output [4:0] out;
output rem;
output zero;
// &Regs; @19
reg rem_1;
reg [4:0] result;
// &Wires; @20
wire [4:0] out;
wire rem;
wire [7:0] src;
wire zero;
// &CombBeg; @22
always @(src[7:0]) begin
casez (src[7:0])
8'b1???_????: begin
rem_1 = &src[6:0];
result[4:0] = 5'b11111;
end
8'b01??_????: begin
rem_1 = &src[5:0];
result[4:0] = 5'b00000;
end
8'b001?_????: begin
rem_1 = &src[4:0];
result[4:0] = 5'b00001;
end
8'b0001_????: begin
rem_1 = &src[3:0];
result[4:0] = 5'b00010;
end
8'b0000_1???: begin
rem_1 = &src[2:0];
result[4:0] = 5'b00011;
end
8'b0000_01??: begin
rem_1 = &src[1:0];
result[4:0] = 5'b00100;
end
8'b0000_001?: begin
rem_1 = src[0];
result[4:0] = 5'b00101;
end
8'b0000_0001: begin
rem_1 = 1'b1;
result[4:0] = 5'b00110;
end
8'b0000_0000: begin
rem_1 = 1'b1;
result[4:0] = 5'b00111;
end
default: begin
rem_1 = 1'bx;
result[4:0] = {5{1'bx}};
end
endcase
// &CombEnd; @35
end
assign out[4:0] = result[4:0];
assign rem = rem_1;
assign zero = (src[7:0] == 8'b0000_0000);
// &ModuleEnd; @41
endmodule
| 7.782013 |
module aq_vlsu_rot_data (
data_in,
data_out,
rot_sel
);
// &Ports; @24
input [63:0] data_in;
input [7 : 0] rot_sel;
output [63:0] data_out;
// &Regs; @25
reg [ 63:0] data_settle;
// &Wires; @26
wire [ 63:0] data;
wire [ 63:0] data_in;
wire [ 63:0] data_out;
wire [ 63:0] data_rot0;
wire [ 63:0] data_rot1;
wire [ 63:0] data_rot2;
wire [ 63:0] data_rot3;
wire [ 63:0] data_rot4;
wire [ 63:0] data_rot5;
wire [ 63:0] data_rot6;
wire [ 63:0] data_rot7;
wire [7 : 0] rot_sel;
//================================================
// input interface
//================================================
assign data[`LSU_DATAW-1:0] = data_in[`LSU_DATAW-1:0];
//================================================
// rot_sel
//================================================
assign data_rot0[`LSU_DATAW-1:0] = data[`LSU_DATAW-1:0];
assign data_rot1[`LSU_DATAW-1:0] = {data[`LSU_DATAW-9:0], data[`LSU_DATAW-1:`LSU_DATAW-8]};
assign data_rot2[`LSU_DATAW-1:0] = {data[`LSU_DATAW-17:0], data[`LSU_DATAW-1:`LSU_DATAW-16]};
assign data_rot3[`LSU_DATAW-1:0] = {data[`LSU_DATAW-25:0], data[`LSU_DATAW-1:`LSU_DATAW-24]};
assign data_rot4[`LSU_DATAW-1:0] = {data[`LSU_DATAW-33:0], data[`LSU_DATAW-1:`LSU_DATAW-32]};
assign data_rot5[`LSU_DATAW-1:0] = {data[`LSU_DATAW-41:0], data[`LSU_DATAW-1:`LSU_DATAW-40]};
assign data_rot6[`LSU_DATAW-1:0] = {data[`LSU_DATAW-49:0], data[`LSU_DATAW-1:`LSU_DATAW-48]};
assign data_rot7[`LSU_DATAW-1:0] = {data[`LSU_DATAW-57:0], data[`LSU_DATAW-1:`LSU_DATAW-56]};
// &CombBeg; @56
// &CombEnd; @76
// &CombBeg; @79
always @( data_rot5[63:0]
or rot_sel[7:0]
or data_rot0[63:0]
or data_rot3[63:0]
or data_rot6[63:0]
or data_rot4[63:0]
or data_rot1[63:0]
or data_rot7[63:0]
or data_rot2[63:0])
begin
case (rot_sel[7:0])
8'h01: data_settle[`LSU_DATAW-1:0] = data_rot0[`LSU_DATAW-1:0];
8'h02: data_settle[`LSU_DATAW-1:0] = data_rot1[`LSU_DATAW-1:0];
8'h04: data_settle[`LSU_DATAW-1:0] = data_rot2[`LSU_DATAW-1:0];
8'h08: data_settle[`LSU_DATAW-1:0] = data_rot3[`LSU_DATAW-1:0];
8'h10: data_settle[`LSU_DATAW-1:0] = data_rot4[`LSU_DATAW-1:0];
8'h20: data_settle[`LSU_DATAW-1:0] = data_rot5[`LSU_DATAW-1:0];
8'h40: data_settle[`LSU_DATAW-1:0] = data_rot6[`LSU_DATAW-1:0];
8'h80: data_settle[`LSU_DATAW-1:0] = data_rot7[`LSU_DATAW-1:0];
default: data_settle[`LSU_DATAW-1:0] = {`LSU_DATAW{1'bx}};
endcase
// &CombEnd; @91
end
//================================================
// output interface
//================================================
assign data_out[`LSU_DATAW-1:0] = data_settle[`LSU_DATAW-1:0];
// &ModuleEnd; @98
endmodule
| 6.820042 |
module aq_zybo_vga (
input RST_N,
input CLK,
input [31:0] DIN,
input ACTIVE,
input HIN,
input VIN,
output HSYNC,
output VSYNC,
output [4:0] DOUT_R,
output [5:0] DOUT_G,
output [4:0] DOUT_B
);
reg HSYNC;
reg VSYNC;
reg [4:0] DOUT_R;
reg [5:0] DOUT_G;
reg [4:0] DOUT_B;
always @(posedge CLK or negedge RST_N) begin
if (!RST_N) begin
HSYNC <= 1'b0;
VSYNC <= 1'b0;
DOUT_R[4:0] <= 5'd0;
DOUT_G[5:0] <= 6'd0;
DOUT_B[4:0] <= 5'd0;
end else begin
HSYNC <= HIN;
VSYNC <= VIN;
DOUT_R[4:0] <= (ACTIVE) ? DIN[23:19] : 5'd0;
DOUT_G[5:0] <= (ACTIVE) ? DIN[15:10] : 6'd0;
DOUT_B[4:0] <= (ACTIVE) ? DIN[7:3] : 5'd0;
end
end
endmodule
| 6.880747 |
module ar (
din,
clk,
rst,
arload,
arinc,
dout
);
input [15:0] din;
input clk, rst, arload, arinc;
output [15:0] dout;
reg [15:0] dout;
always @(posedge clk or negedge rst)
if (!rst) dout <= 0;
else if (arload) dout <= din;
else if (arinc) dout <= dout + 1;
endmodule
| 6.957779 |
module aram8x16 (
input wr_in,
rd_in,
input [2:0] addr_in,
addr_out,
input [15:0] data_wr,
output [15:0] data_rd
);
reg [ 7:0] out;
reg [15:0] mem [7:0];
always @(*) begin
if (wr_in) mem[addr_in] = data_wr;
if (rd_in) out = (rd_in) ? mem[addr_out] : 16'hzz;
end
assign data_rd = out;
endmodule
| 8.522772 |
module ArbDynamicPriority (
clk,
rst_n,
req,
priorityLevel,
grant
);
parameter REQ_NUM = 4;
parameter PRI_WIDTH = clog2(REQ_NUM);
parameter PRI_TOTALW = REQ_NUM * PRI_WIDTH;
//
input clk;
input rst_n;
input [REQ_NUM-1:0] req;
input [PRI_TOTALW-1:0] priorityLevel;
output reg [REQ_NUM-1:0] grant;
//
wire [REQ_NUM*REQ_NUM-1:0] compResult;
wire noGrant;
wire [REQ_NUM-1:0] orPriorityResult;
wire [REQ_NUM-1:0] reqEn;
wire [REQ_NUM*REQ_NUM-1:0] newGrant;
wire [REQ_NUM-1:0] setGrant;
wire [REQ_NUM-1:0] setPriorityGrant;
//Priority comparator
generate
genvar i0;
genvar i1;
//--------------------------------------
//(1) Priority selection
//--------------------------------------
for (i0 = 0; i0 < REQ_NUM; i0 = i0 + 1) begin : uComp
for (i1 = 0; i1 < REQ_NUM; i1 = i1 + 1) begin : bitComp
assign compResult[i1+i0*REQ_NUM] = req[i0] & (priorityLevel[PRI_WIDTH*(i0+1)-1:PRI_WIDTH*i0] == i1);
end
end
//--------------------------------------
//(2) Asserted request check based on the priority level
//--------------------------------------
for (i0 = 0; i0 < REQ_NUM; i0 = i0 + 1) begin : AChk
assign orPriorityResult[i0] = orOut(compResult[REQ_NUM*REQ_NUM-1:0], i0);
end
//--------------------------------------
//(3) Request enable
//--------------------------------------
assign reqEn[0] = orPriorityResult[0];
for (i0 = 1; i0 < REQ_NUM; i0 = i0 + 1) begin : ReqEnable
assign reqEn[i0] = orPriorityResult[i0] & ~|orPriorityResult[i0-1:0];
end
//--------------------------------------
//(4) Request mask
//--------------------------------------
for (i0 = 0; i0 < REQ_NUM; i0 = i0 + 1) begin : ReqMask
for (i1 = 0; i1 < REQ_NUM; i1 = i1 + 1) begin : BitMask
assign newGrant[i1+i0*REQ_NUM] = compResult[i1+i0*REQ_NUM] & reqEn[i1];
end
end
//--------------------------------------
//(5) Grant set
//--------------------------------------
for (i0 = 0; i0 < REQ_NUM; i0 = i0 + 1) begin : uSetGrant
assign setGrant[i0] = |newGrant[REQ_NUM*(i0+1)-1:i0*REQ_NUM];
end
//--------------------------------------
//(6) Same priority filter
//--------------------------------------
assign setPriorityGrant[0] = setGrant[0];
for (i0 = 1; i0 < REQ_NUM; i0 = i0 + 1) begin : uSetPriGrant
assign setPriorityGrant[i0] = setGrant[i0] & ~|setGrant[i0-1:0];
end
//
endgenerate
//--------------------------------------
//(7) Grant
//--------------------------------------
generate
genvar j;
//
for (j = 0; j < REQ_NUM; j = j + 1) begin : uGrant
always @(posedge clk, negedge rst_n) begin
if (~rst_n) grant[j] <= 1'b0;
else if (noGrant) grant[j] <= setPriorityGrant[j];
else grant[j] <= grant[j] & req[j];
end
end //for loop
endgenerate
assign noGrant = ~|grant[REQ_NUM-1:0];
//-----------------------------------------------------------
//OR function - Can synthesize
//-----------------------------------------------------------
function reg orOut;
input [REQ_NUM*REQ_NUM-1:0] orIn;
input integer id;
integer i;
begin
orOut = 1'b0;
for (i = 0; i < REQ_NUM; i = i + 1) begin
orOut = orOut | orIn[id+i*REQ_NUM];
end
end
endfunction
//-----------------------------------------------------------
//log2 function - Not for synthesizing
//Only use to calculate the parameter value
//-----------------------------------------------------------
function integer clog2;
input integer value;
integer i;
begin
clog2 = 0;
for (i = 0; 2 ** i < value; i = i + 1) clog2 = i + 1;
end
endfunction
endmodule
| 7.747255 |
module arbel (
input X,
input Y,
input C,
output W,
output Z
);
wire W1, W2;
wire Z1, Z2;
mux2x1 M1 (
X,
Y,
C,
W1
);
mux2x1 M2 (
Y,
X,
C,
Z1
);
not N1 (W2, W1);
not N2 (W, W2);
not N7 (Z2, Z1);
not N8 (Z, Z2);
endmodule
| 8.13877 |
module arbit (
input wire sclk,
input wire rst,
input wire rd_req,
input wire wr_req,
input wire rd_end,
input wire wr_end,
output wire rd_cmd_start,
output wire wr_cmd_start
);
parameter IDLE = 4'b0001;
parameter ARBIT = 4'b0010;
parameter WR = 4'b0100;
parameter RD = 4'b1000;
reg [3:0] state;
reg wr_flag, rd_flag;
reg wr_start, rd_start;
assign wr_cmd_start = wr_start;
assign rd_cmd_start = rd_start;
always @(posedge sclk) begin
if (rst == 1'b1) begin
state <= IDLE;
end else begin
case (state)
IDLE: begin
state <= ARBIT;
end
ARBIT: begin
if (wr_req == 1'b1) begin
state <= WR;
end else if (rd_req == 1'b1) begin
state <= RD;
end
end
WR: begin
if (wr_end == 1'b1) begin
state <= ARBIT;
end
end
RD: begin
if (rd_end == 1'b1) begin
state <= ARBIT;
end
end
default: state <= IDLE;
endcase
end
end
always @(posedge sclk) begin
if (rst == 1'b1) begin
wr_flag <= 1'b0;
end else if (state == WR) begin //&& wr_flag == 1'b1 ) begin
wr_flag <= 1'b0;
end else if (wr_req == 1'b1) begin
wr_flag <= 1'b1;
end
end
always @(posedge sclk) begin
if (rst == 1'b1) begin
wr_start <= 1'b0;
end else if (state == WR && wr_flag == 1'b1) begin
wr_start <= 1'b1;
end else begin
wr_start <= 1'b0;
end
end
always @(posedge sclk) begin
if (rst == 1'b1) begin
rd_flag <= 1'b0;
end else if (state == RD) begin //&& rd_flag == 1'b1) begin
rd_flag <= 1'b0;
end else if (rd_req == 1'b1) begin
rd_flag <= 1'b1;
end
end
always @(posedge sclk) begin
if (rst == 1'b1) begin
rd_start <= 1'b0;
end else if (state == RD && rd_flag == 1'b1) begin
rd_start <= 1'b1;
end else begin
rd_start <= 1'b0;
end
end
endmodule
| 7.672948 |
module arbiter3 (
input wire clk,
input wire rst_n,
input wire [2:0] grant,
output wire [2:0] arbitration
);
reg prio2_1;
reg prio2_0;
reg prio1_0;
assign arbitration[2] = grant[2] & (~grant[1] | prio2_1) & (~grant[0] | prio2_0);
assign arbitration[1] = grant[1] & (~grant[2] | ~prio2_1) & (~grant[0] | prio1_0);
assign arbitration[0] = grant[0] & (~grant[2] | ~prio2_0) & (~grant[1] | ~prio1_0);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
//initial priority is 43210;
prio2_1 <= 1;
prio2_0 <= 1;
prio1_0 <= 1;
end else begin
case (arbitration)
3'b100: begin
prio2_1 <= 0;
prio2_0 <= 0;
prio1_0 <= prio1_0;
end
3'b010: begin
prio2_1 <= 1;
prio2_0 <= prio2_0;
prio1_0 <= 0;
end
3'b001: begin
prio2_1 <= prio2_1;
prio2_0 <= 1;
prio1_0 <= 1;
end
default: begin
prio2_1 <= prio2_1;
prio2_0 <= prio2_0;
prio1_0 <= prio1_0;
end
endcase
end
end
endmodule
| 8.317171 |
module arbiter4 (
input wire clk,
input wire rst_n,
input wire [3:0] grant,
output wire [3:0] arbitration
);
reg prio3_2;
reg prio3_1;
reg prio3_0;
reg prio2_1;
reg prio2_0;
reg prio1_0;
assign arbitration[3] = grant[3]& (~grant[2] | prio3_2) &(~grant[1] | prio3_1)& (~grant[0] | prio3_0);
assign arbitration[2] = grant[2]& (~grant[3] | ~prio3_2) &(~grant[1] | prio2_1)& (~grant[0] | prio2_0);
assign arbitration[1] = grant[1]& (~grant[3] | ~prio3_1) &(~grant[2] | ~prio2_1)& (~grant[0] | prio1_0);
assign arbitration[0] = grant[0]& (~grant[3] | ~prio3_0) &(~grant[2] | ~prio2_0)& (~grant[1] | ~prio1_0);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
//initial priority is 43210;
prio3_2 <= 1;
prio3_1 <= 1;
prio3_0 <= 1;
prio2_1 <= 1;
prio2_0 <= 1;
prio1_0 <= 1;
end else begin
case (arbitration)
4'b1000: begin
prio3_2 <= 0;
prio3_1 <= 0;
prio3_0 <= 0;
prio2_1 <= prio2_1;
prio2_0 <= prio2_0;
prio1_0 <= prio1_0;
end
4'b0100: begin
prio3_2 <= 1;
prio3_1 <= prio3_1;
prio3_0 <= prio3_0;
prio2_1 <= 0;
prio2_0 <= 0;
prio1_0 <= prio1_0;
end
4'b0010: begin
prio3_2 <= prio3_2;
prio3_1 <= 1;
prio3_0 <= prio3_0;
prio2_1 <= 1;
prio2_0 <= prio2_0;
prio1_0 <= 0;
end
4'b0001: begin
prio3_2 <= prio3_2;
prio3_1 <= prio3_1;
prio3_0 <= 1;
prio2_1 <= prio2_1;
prio2_0 <= 1;
prio1_0 <= 1;
end
default: begin
prio3_2 <= prio3_2;
prio3_1 <= prio3_1;
prio3_0 <= prio3_0;
prio2_1 <= prio2_1;
prio2_0 <= prio2_0;
prio1_0 <= prio1_0;
end
endcase
end
end
endmodule
| 7.886769 |
module arbiter5 (
input wire clk,
input wire rst_n,
input wire [4:0] grant,
output wire [4:0] arbitration
);
reg prio4_3;
reg prio4_2;
reg prio4_1;
reg prio4_0;
reg prio3_2;
reg prio3_1;
reg prio3_0;
reg prio2_1;
reg prio2_0;
reg prio1_0;
assign arbitration[4] = grant[4]& (~grant[3] | prio4_3) & (~grant[2] | prio4_2) &(~grant[1] | prio4_1)& (~grant[0] | prio4_0);
assign arbitration[3] = grant[3]& (~grant[4] | ~prio4_3) & (~grant[2] | prio3_2) &(~grant[1] | prio3_1)& (~grant[0] | prio3_0);
assign arbitration[2] = grant[2]& (~grant[4] | ~prio4_2) & (~grant[3] | ~prio3_2) &(~grant[1] | prio2_1)& (~grant[0] | prio2_0);
assign arbitration[1] = grant[1]& (~grant[4] | ~prio4_1) & (~grant[3] | ~prio3_1) &(~grant[2] | ~prio2_1)& (~grant[0] | prio1_0);
assign arbitration[0] = grant[0]& (~grant[4] | ~prio4_0) & (~grant[3] | ~prio3_0) &(~grant[2] | ~prio2_0)& (~grant[1] | ~prio1_0);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
//initial priority is 43210;
prio4_3 <= 1;
prio4_2 <= 1;
prio4_1 <= 1;
prio4_0 <= 1;
prio3_2 <= 1;
prio3_1 <= 1;
prio3_0 <= 1;
prio2_1 <= 1;
prio2_0 <= 1;
prio1_0 <= 1;
end else begin
case (arbitration)
5'b10000: begin
prio4_3 <= 0;
prio4_2 <= 0;
prio4_1 <= 0;
prio4_0 <= 0;
prio3_2 <= prio3_2;
prio3_1 <= prio3_1;
prio3_0 <= prio3_0;
prio2_1 <= prio2_1;
prio2_0 <= prio2_0;
prio1_0 <= prio1_0;
end
5'b01000: begin
prio4_3 <= 1;
prio4_2 <= prio4_2;
prio4_1 <= prio4_1;
prio4_0 <= prio4_0;
prio3_2 <= 0;
prio3_1 <= 0;
prio3_0 <= 0;
prio2_1 <= prio2_1;
prio2_0 <= prio2_0;
prio1_0 <= prio1_0;
end
5'b00100: begin
prio4_3 <= prio4_3;
prio4_2 <= 1;
prio4_1 <= prio4_1;
prio4_0 <= prio4_0;
prio3_2 <= 1;
prio3_1 <= prio3_1;
prio3_0 <= prio3_0;
prio2_1 <= 0;
prio2_0 <= 0;
prio1_0 <= prio1_0;
end
5'b00010: begin
prio4_3 <= prio4_3;
prio4_2 <= prio4_2;
prio4_1 <= 1;
prio4_0 <= prio4_0;
prio3_2 <= prio3_2;
prio3_1 <= 1;
prio3_0 <= prio3_0;
prio2_1 <= 1;
prio2_0 <= prio2_0;
prio1_0 <= 0;
end
5'b00001: begin
prio4_3 <= prio4_3;
prio4_2 <= prio4_2;
prio4_1 <= prio4_1;
prio4_0 <= 1;
prio3_2 <= prio3_2;
prio3_1 <= prio3_1;
prio3_0 <= 1;
prio2_1 <= prio2_1;
prio2_0 <= 1;
prio1_0 <= 1;
end
default: begin
prio4_3 <= prio4_3;
prio4_2 <= prio4_2;
prio4_1 <= prio4_1;
prio4_0 <= prio4_0;
prio3_2 <= prio3_2;
prio3_1 <= prio3_1;
prio3_0 <= prio3_0;
prio2_1 <= prio2_1;
prio2_0 <= prio2_0;
prio1_0 <= prio1_0;
end
endcase
end
end
endmodule
| 7.226772 |
module vc_FixedArbChain #(
parameter p_num_reqs = 2
) (
input logic kin, // kill in
input logic [p_num_reqs-1:0] reqs, // 1 = making a req, 0 = no req
output logic [p_num_reqs-1:0] grants, // (one-hot) 1 indicates req won grant
output logic kout // kill out
);
// The internal kills signals essentially form a kill chain from the
// highest priority to the lowest priority requester. The highest
// priority requster (say requester i) which is actually making a
// request sets the kill signal for the next requester to one (ie
// kills[i+1]) and then this kill signal is propagated to all lower
// priority requesters.
logic [p_num_reqs:0] kills;
assign kills[0] = 1'b0;
// The per requester logic first computes the grant signal and then
// computes the kill signal for the next requester.
logic [p_num_reqs-1:0] grants_int;
genvar i;
generate
for (i = 0; i < p_num_reqs; i = i + 1) begin : per_req_logic
// Grant is true if this requester is not killed and it is actually
// making a req.
assign grants_int[i] = !kills[i] && reqs[i];
// Kill is true if this requester was either killed or it received
// the grant.
assign kills[i+1] = kills[i] || grants_int[i];
end
endgenerate
// We AND kin into the grant and kout signals afterwards so that we can
// begin doing the arbitration before we know kin. This also allows us
// to build hybrid tree-ripple arbiters out of vc_FixedArbChain
// components.
assign grants = grants_int & {p_num_reqs{~kin}};
assign kout = kills[p_num_reqs] || kin;
endmodule
| 8.484232 |
module vc_VariableArbChain #(
parameter p_num_reqs = 2
) (
input logic kin, // kill in
input logic [p_num_reqs-1:0] priority_, // (one-hot) 1 is req w/ highest pri
input logic [p_num_reqs-1:0] reqs, // 1 = making a req, 0 = no req
output logic [p_num_reqs-1:0] grants, // (one-hot) 1 is req won grant
output logic kout // kill out
);
// The internal kills signals essentially form a kill chain from the
// highest priority to the lowest priority requester. Unliked the fixed
// arb, the priority input is used to determine which request has the
// highest priority. We could use a circular kill chain, but static
// timing analyzers would probably consider it a combinational loop
// (which it is) and choke. Instead we replicate the kill chain. See
// Principles and Practices of Interconnection Networks, Dally +
// Towles, p354 for more info.
logic [2*p_num_reqs:0] kills;
assign kills[0] = 1'b1;
logic [2*p_num_reqs-1:0] priority_int;
assign priority_int = {{p_num_reqs{1'b0}}, priority_};
logic [2*p_num_reqs-1:0] reqs_int;
assign reqs_int = {reqs, reqs};
logic [2*p_num_reqs-1:0] grants_int;
// The per requester logic first computes the grant signal and then
// computes the kill signal for the next requester.
localparam p_num_reqs_x2 = (p_num_reqs << 1);
genvar i;
generate
for (i = 0; i < 2 * p_num_reqs; i = i + 1) begin : per_req_logic
// If this is the highest priority requester, then we ignore the
// input kill signal, otherwise grant is true if this requester is
// not killed and it is actually making a req.
assign grants_int[i] = priority_int[i] ? reqs_int[i] : (!kills[i] && reqs_int[i]);
// If this is the highest priority requester, then we ignore the
// input kill signal, otherwise kill is true if this requester was
// either killed or it received the grant.
assign kills[i+1] = priority_int[i] ? grants_int[i] : (kills[i] || grants_int[i]);
end
endgenerate
// To calculate final grants we OR the two grants from the replicated
// kill chain. We also AND in the global kin signal.
assign grants
= (grants_int[p_num_reqs-1:0] | grants_int[2*p_num_reqs-1:p_num_reqs])
& {p_num_reqs{~kin}};
assign kout = kills[2*p_num_reqs] || kin;
endmodule
| 7.922999 |
module vc_VariableArb #(
parameter p_num_reqs = 2
) (
input logic [p_num_reqs-1:0] priority_, // (one-hot) 1 is req w/ highest pri
input logic [p_num_reqs-1:0] reqs, // 1 = making a req, 0 = no req
output logic [p_num_reqs-1:0] grants // (one-hot) 1 is req won grant
);
logic dummy_kout;
vc_VariableArbChain #(p_num_reqs) variable_arb_chain (
.kin (1'b0),
.priority_(priority_),
.reqs (reqs),
.grants (grants),
.kout (dummy_kout)
);
endmodule
| 7.922999 |
module arbiter_1m_2s #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32
) (
/* Master wishbone */
input [ADDR_WIDTH-1:0] m_addr_i,
input [DATA_WIDTH-1:0] m_data_i,
output [DATA_WIDTH-1:0] m_data_o,
input m_cyc_i,
input [ 3:0] m_sel_i,
input m_stb_i,
input m_we_i,
output m_ack_o,
output m_err_o,
output m_rty_o,
/* slave one */
output [ADDR_WIDTH-2:0] s0_addr_o,
output [DATA_WIDTH-1:0] s0_data_o,
input [DATA_WIDTH-1:0] s0_data_i,
output s0_cyc_o,
output [ 3:0] s0_sel_o,
output s0_stb_o,
output s0_we_o,
input s0_ack_i,
input s0_err_i,
input s0_rty_i,
/* slave two */
output [ADDR_WIDTH-2:0] s1_addr_o,
output [DATA_WIDTH-1:0] s1_data_o,
input [DATA_WIDTH-1:0] s1_data_i,
output s1_cyc_o,
output [ 3:0] s1_sel_o,
output s1_stb_o,
output s1_we_o,
input s1_ack_i,
input s1_err_i,
input s1_rty_i
);
wire cs = m_addr_i[24];
assign s0_stb_o = ~cs & m_stb_i;
assign s1_stb_o = cs & m_stb_i;
assign s0_addr_o = {8'b0, m_addr_i[ADDR_WIDTH-9:0]};
assign s1_addr_o = {8'b0, m_addr_i[ADDR_WIDTH-9:0]};
assign s0_data_o = m_data_i;
assign s1_data_o = m_data_i;
assign m_data_o = cs ? s1_data_i : s0_data_i;
assign s0_cyc_o = m_cyc_i;
assign s1_cyc_o = m_cyc_i;
assign s0_sel_o = m_sel_i;
assign s1_sel_o = m_sel_i;
assign s0_we_o = m_we_i;
assign s1_we_o = m_we_i;
assign m_ack_o = cs ? s1_ack_i : s0_ack_i;
assign m_err_o = cs ? s1_err_i : s0_err_i;
assign m_rty_o = cs ? s1_rty_i : s0_rty_i;
endmodule
| 6.968401 |
module arbiter_tb ();
// Request bundles are composed by:
// * request_bundle[2] :: hit_x
// * request_bundle[1] :: hit_y
// * request_bundle[0] :: request
reg [2:0] pe_request_bundle;
reg [2:0] north_request_bundle;
reg [2:0] east_request_bundle;
// Configuration bundles are composed by:
// * cfg_bundle[2] :: mux_ctrl[1]
// * cfg_bundle[1] :: mux_ctrl[0]
// * cfg_bundle[0] :: toggle
wire [1:0] pe_cfg_bundle;
wire [2:0] south_cfg_bundle;
wire [2:0] west_cfg_bundle;
// ACK that a request from the PE has been accepted
wire r2pe_ack;
// localparam
localparam MUX_EAST = 3'b011;
localparam MUX_NORTH = 3'b001;
localparam MUX_PE = 3'b101;
localparam MUX_NULL = 3'b000;
localparam WEST = 3'b011;
localparam SOUTH = 3'b101;
localparam PE = 3'b111;
localparam NULL = 3'b000;
arbitro UUT (
// Request bundles are composed by:
// * request_bundle[2] :: hit_x
// * request_bundle[1] :: hit_y
// * request_bundle[0] :: request
.pe_request_bundle (pe_request_bundle),
.north_request_bundle(north_request_bundle),
.east_request_bundle (east_request_bundle),
// Configuration bundles are composed by:
// * cfg_bundle[2] :: mux_ctrl[1]
// * cfg_bundle[1] :: mux_ctrl[0]
// * cfg_bundle[0] :: toggle
.pe_cfg_bundle (pe_cfg_bundle),
.south_cfg_bundle(south_cfg_bundle),
.west_cfg_bundle (west_cfg_bundle),
// ACK that a request from the PE has been accepted
.r2pe_ack(r2pe_ack)
);
// stimuli
initial begin
// initial values
pe_request_bundle = 0;
north_request_bundle = 0;
east_request_bundle = 0;
// stimuli
#(30);
// out of stability period
north_request_bundle = WEST;
#(20);
north_request_bundle = NULL;
#(20);
north_request_bundle = SOUTH;
#(20);
north_request_bundle = PE;
#(20);
north_request_bundle = NULL;
// Done with North
// Start PE request
pe_request_bundle = WEST;
#(20);
pe_request_bundle = SOUTH;
#(20);
pe_request_bundle = SOUTH | WEST;
#(20);
pe_request_bundle = NULL;
#(20)
// Done with PE
// Start South request
east_request_bundle = WEST;
#(20);
east_request_bundle = SOUTH;
#(20);
east_request_bundle = PE;
#(20);
east_request_bundle = NULL;
#(20);
// Done with South
// Multiple Petition
north_request_bundle = WEST;
east_request_bundle = SOUTH;
#(20);
north_request_bundle = NULL;
east_request_bundle = NULL;
#(20);
north_request_bundle = WEST;
east_request_bundle = WEST;
#(20);
north_request_bundle = NULL;
east_request_bundle = NULL;
#(20);
north_request_bundle = SOUTH;
east_request_bundle = SOUTH;
pe_request_bundle = WEST;
#(20);
north_request_bundle = SOUTH;
east_request_bundle = WEST;
pe_request_bundle = WEST;
#(20);
north_request_bundle = PE;
east_request_bundle = WEST;
pe_request_bundle = WEST;
#(20);
north_request_bundle = SOUTH;
east_request_bundle = PE;
pe_request_bundle = WEST;
#(20);
north_request_bundle = NULL;
east_request_bundle = NULL;
pe_request_bundle = NULL;
#(20);
// Done with Multiple
#(200);
$finish;
end
endmodule
| 7.933876 |
module prior_arb #(
parameter WIDTH = 16
) (
input [WIDTH-1:0] req,
output [WIDTH-1:0] gnt
);
wire [WIDTH-1:0] var;
assign var = req - 1'b1;
assign gnt = req & ~var;
endmodule
| 7.84627 |
module function:because there are three kinds of accesses to mem ,
/// we need to determine which will be allowed to access mem finally.
module arbiter_for_mem(//input
clk,
rst,
v_mem_download,
v_d_m_areg,
v_i_m_areg,
mem_access_done,
//output
ack_m_download,
ack_d_m_areg,
ack_i_m_areg,
v_m_download_m,
v_d_m_areg_m,
v_i_m_areg_m
);
//input
input clk;
input rst;
input v_mem_download;
input v_d_m_areg;
input v_i_m_areg;
input mem_access_done;
//output
output ack_m_download;
output ack_d_m_areg;
output ack_i_m_areg;
output v_m_download_m;
output v_d_m_areg_m;
output v_i_m_areg_m;
/// parameter for fsm state
parameter arbiter_idle=2'b00;
parameter i_m_areg_busy=2'b01;
parameter d_m_areg_busy=2'b10;
parameter m_download_busy=2'b11;
reg [1:0] nstate;
reg [1:0] state;
// wire [2:0] v_vector;
// assign v_vector={v_i_m_areg,v_d_m_areg,v_mem_download};
wire [2:0] seled_v;
reg ack_m_download;
reg ack_d_m_areg;
reg ack_i_m_areg;
reg v_m_download_m;
reg v_d_m_areg_m;
reg v_i_m_areg_m;
assign seled_v=(v_i_m_areg==1'b1)?3'b100:(v_d_m_areg==1'b1)?3'b010:(v_mem_download==1'b1)?3'b001:3'b000;
always@(*)
begin
//default values
{ack_i_m_areg,ack_d_m_areg,ack_m_download}=3'b000;
{v_i_m_areg_m,v_d_m_areg_m,v_m_download_m}=3'b000;
nstate=state;
case(state)
arbiter_idle:
begin
{ack_i_m_areg,ack_d_m_areg,ack_m_download}=seled_v;
{v_i_m_areg_m,v_d_m_areg_m,v_m_download_m}=seled_v;
if(seled_v==3'b100)
nstate=i_m_areg_busy;
else
if(seled_v==3'b010)
nstate=d_m_areg_busy;
else
if(seled_v==3'b001)
nstate=m_download_busy;
end
i_m_areg_busy:
begin
if(mem_access_done)
begin
nstate=arbiter_idle;
end
{ack_i_m_areg,ack_d_m_areg,ack_m_download}=3'b100;
{v_i_m_areg_m,v_d_m_areg_m,v_m_download_m}=3'b100;
end
d_m_areg_busy:
begin
if(mem_access_done)
begin
nstate=arbiter_idle;
end
{ack_i_m_areg,ack_d_m_areg,ack_m_download}=3'b010;
{v_i_m_areg_m,v_d_m_areg_m,v_m_download_m}=3'b010;
end
m_download_busy:
begin
if(mem_access_done)
begin
nstate=arbiter_idle;
end
{ack_i_m_areg,ack_d_m_areg,ack_m_download}=3'b001;
{v_i_m_areg_m,v_d_m_areg_m,v_m_download_m}=3'b001;
end
endcase
end
/// state reg
always@(posedge clk)
begin
if(rst)
state<=2'b00;
else
state<=nstate;
end
endmodule
| 6.680089 |
module function:because there are two kinds of uploadregs to
/// OUT_rep: inst_cache ,data_cache and memory, so we need to determine which can be writed into OUT_rep.
module arbiter_for_OUT_rep(//input
clk,
rst,
OUT_rep_rdy,
v_dc_rep,
v_mem_rep,
dc_rep_flit,
mem_rep_flit,
dc_rep_ctrl,
mem_rep_ctrl,
//output
ack_OUT_rep,
ack_dc_rep,
ack_mem_rep,
select // select 1/2
);
//input
input clk;
input rst;
input OUT_rep_rdy;
input v_dc_rep;
input v_mem_rep;
input [15:0] dc_rep_flit;
input [15:0] mem_rep_flit;
input [1:0] dc_rep_ctrl;
input [1:0] mem_rep_ctrl;
//output
output ack_OUT_rep;
output ack_dc_rep;
output ack_mem_rep;
output [1:0] select; // select 1/2
//parameter for fsm state
parameter arbiter_idle=3'b001;
parameter dc_uploading=3'b010;
parameter mem_uploading=3'b100;
//parameter of cmd
parameter nackrep_cmd=5'b10101;
parameter SCflurep_cmd=5'b11100;
reg [2:0] nstate;
reg [2:0] state;
reg priority1;
reg ack_OUT_rep;
reg ack_dc_rep;
reg ack_mem_rep;
reg update_priority;
reg [1:0] select;
/// nstate and output function
always@(*)
begin
nstate=state;
ack_OUT_rep=1'b0;
ack_dc_rep=1'b0;
ack_mem_rep=1'b0;
update_priority=1'b0;
select=2'b00;
case(state)
arbiter_idle:
begin
if({v_dc_rep,v_mem_rep}==2'b11)
begin
update_priority=1'b1;
if(priority1)
begin
nstate=dc_uploading;
end
else
begin
nstate=mem_uploading;
end
end
else if({v_dc_rep,v_mem_rep}==2'b01)
begin
nstate=mem_uploading;
end
else if({v_dc_rep,v_mem_rep}==2'b10)
begin
nstate=dc_uploading;
end
end
dc_uploading:
begin
if(OUT_rep_rdy)
begin
ack_OUT_rep=1'b1;
ack_dc_rep=1'b1;
select=2'b01;
if(dc_rep_ctrl==2'b11||dc_rep_ctrl==2'b01&&(dc_rep_flit[9:5]==SCflurep_cmd||dc_rep_flit[9:5]==nackrep_cmd))
begin
nstate=arbiter_idle;
end
end
end
mem_uploading:
begin
if(OUT_rep_rdy)
begin
ack_OUT_rep=1'b1;
ack_mem_rep=1'b1;
select=2'b10;
if(mem_rep_ctrl==2'b11||mem_rep_ctrl==2'b01&&(mem_rep_flit[9:5]==SCflurep_cmd||mem_rep_flit[9:5]==nackrep_cmd))
begin
nstate=arbiter_idle;
end
end
end
endcase
end
// fsm state reg
always@(posedge clk)
begin
if(rst)
state<=3'b001;
else
state<=nstate;
end
always@(posedge clk)
begin
if(rst)
priority1<=1'b0;
else if(update_priority)
priority1<=~priority1;
end
endmodule
| 6.680089 |
module arbiter_LRU4 (
grant_vector,
req_vector,
enable,
CLK,
RST
);
input [3:0] req_vector;
input CLK;
input RST;
input enable;
output [3:0] grant_vector;
reg [1:0] lru[3:0];
reg [3:0] grant_vector;
reg [3:0] grant_vector_1d;
reg [3:0] grant_vector_pre;
reg [1:0] equal_sloc;
reg [3:0] update_sloc;
wire grant_ind;
reg cnt;
integer i;
// initialize lru
always @(posedge CLK) begin
if (RST) begin
lru[0] <= 2'd0;
lru[1] <= 2'd1;
lru[2] <= 2'd2;
lru[3] <= 2'd3;
grant_vector <= 4'b0;
// for(i=0; i<4; i=i+1) begin
// lru[i] <= i;
// grant_vector[i] <= 1'b0;
// end
end // update lru
else if ((enable == 1'b1) && (cnt == 1'b1)) begin
if (equal_sloc == 2'b0) begin
lru[3] <= lru[0];
lru[2] <= lru[3];
lru[1] <= lru[2];
lru[0] <= lru[1];
end else if (equal_sloc == 2'b1) begin
lru[3] <= lru[1];
lru[2] <= lru[3];
lru[1] <= lru[2];
end else if (equal_sloc == 2'b10) begin
lru[3] <= lru[2];
lru[2] <= lru[3];
end
end
end
// determin which block in lru is recently used
always @(*) begin
for (i = 0; i < 4; i = i + 1) begin
if (grant_vector[lru[i]] == 1'b1) begin
equal_sloc = i;
end
end
end
//give grant
always @(*) begin
grant_vector_pre <= 4'b0;
if (RST) grant_vector_pre = 4'b0;
else if (!enable) grant_vector_pre = 4'b0;
else if (cnt == 1'b1) // neglect in the second clk of a grant since grant last for two clk
grant_vector_pre = 4'b0;
else if (req_vector[lru[0]]) grant_vector_pre[lru[0]] = req_vector[lru[0]];
else if (req_vector[lru[1]]) grant_vector_pre[lru[1]] = req_vector[lru[1]];
else if (req_vector[lru[2]]) grant_vector_pre[lru[2]] = req_vector[lru[2]];
else if (req_vector[lru[3]]) grant_vector_pre[lru[3]] = req_vector[lru[3]];
else grant_vector_pre = 4'b0;
end
always @(posedge CLK) begin
if (RST) grant_vector_1d <= 4'b0;
else if (!enable) grant_vector_1d <= 4'b0;
else grant_vector_1d <= grant_vector_pre;
end
always @(*) begin
grant_vector = grant_vector_1d | grant_vector_pre;
end
assign grant_ind = |grant_vector;
always @(posedge CLK) begin
if (RST) cnt <= 1'b0;
else if (grant_ind) cnt <= cnt + 1;
end
endmodule
| 7.01686 |
module tb ();
reg [3:0] req;
wire [3:0] grant;
reg RST;
reg enable;
reg CLK;
integer i;
parameter DUTY = 1;
always #DUTY CLK = ~CLK;
initial begin
CLK = 1;
RST = 1;
enable = 0;
req = 4'b0;
//repeat(5) @(posedge CLK)
#4 RST = 0;
//@(posedge CLK)
enable = 1;
req = 4'd15;
#20 req = $urandom % 4'hf;
#16 req = $urandom % 4'hf;
#16 req = $urandom % 4'hf;
#12 enable = 0;
req = $urandom % 4'hf;
#2 enable = 1;
#12 $stop;
end
arbiter_LRU4 u_arbiter_LRU4 (
.grant_vector(grant),
.req_vector(req),
.enable(enable),
.CLK(CLK),
.RST(RST)
);
always @(posedge CLK) begin
for (i = 0; i < 4; i = i + 1) begin
if (grant[i] == 1'b1) req[i] = 1'b0;
end
end
endmodule
| 7.002324 |
module arbiter #(
parameter NUM_PORTS = 6
) (
input clk,
input rst,
input [NUM_PORTS-1:0] request,
output reg [NUM_PORTS-1:0] grant,
output reg active
);
/**
* Local parameters
*/
localparam WRAP_LENGTH = 2 * NUM_PORTS;
`ifdef VERBOSE
initial $display("Bus arbiter with %d units", NUM_PORTS);
`endif
/**
* Internal signals
*/
wire next;
wire [ NUM_PORTS-1:0] order;
wire [ NUM_PORTS-1:0] order_right;
wire [ NUM_PORTS-1:0] gate;
reg [ NUM_PORTS-1:0] token;
wire [ NUM_PORTS-1:0] token_nx;
wire [ NUM_PORTS-1:0] token_lookahead[NUM_PORTS-1:0];
wire [WRAP_LENGTH-1:0] token_wrap;
wire [ NUM_PORTS-1:0] token_gated [0:NUM_PORTS-1];
wire [ NUM_PORTS-1:0] invert [0:NUM_PORTS-1];
/**
* Implementation
*/
assign token_wrap = {token, token};
assign next = ~|(token & request);
assign order_right = (order_right >> 1) | order;
assign gate = (order_right >> 1) ^ order_right;
always @(posedge clk) grant <= token & request;
always @(posedge clk) active <= |(token & request);
always @(posedge clk)
if (rst) token <= 'b1;
else if (next & |(gate)) token <= token_nx;
genvar xx;
genvar zz;
generate
for (xx = 0; xx < NUM_PORTS; xx = xx + 1) begin : ORDER_
assign token_lookahead[xx] = token_wrap[xx+:NUM_PORTS];
assign order[xx] = |(token_lookahead[xx] & request);
assign token_gated[xx] = gate[xx] ? token_lookahead[xx] : {NUM_PORTS{1'b0}};
assign token_nx[xx] = |(invert[xx]);
for (zz = 0; zz < NUM_PORTS; zz = zz + 1) begin : INVERT_
assign invert[xx][zz] = token_gated[zz][xx];
end
end
endgenerate
endmodule
| 7.470414 |
module implements an arbiter, giving priority to the highest index
module arbiter_priority
#(
parameter NUM_ENTRIES = 8,
parameter NUM_ENTRIES_LOG = $clog2(NUM_ENTRIES)
)
(
// client side
input logic [NUM_ENTRIES-1:0] client_valid,
input logic [NUM_ENTRIES_LOG-1:0] top_client,
output logic [NUM_ENTRIES-1:0] client_ready,
output logic [NUM_ENTRIES_LOG-1:0] winner,
// destination side
output logic valid,
input logic ready
);
assign winner = (client_valid[top_client]) ? top_client :
prio_encoder(client_valid);
always_comb
begin
client_ready = {NUM_ENTRIES{1'b0}};
client_ready[winner] = ready;
end
assign valid = |client_valid;
function automatic [NUM_ENTRIES_LOG-1:0] prio_encoder;
input [NUM_ENTRIES - 1:0] v;
begin
prio_encoder = { (NUM_ENTRIES_LOG) {1'b0}};
for(int i=1;i<NUM_ENTRIES;i++) begin
if (v[i]) prio_encoder = i[NUM_ENTRIES_LOG-1:0];
end
end
endfunction
endmodule
| 6.667836 |
module testbench;
logic a_req, b_req, reset, clock, a_res, b_res;
arbiter arb (
.a_req(a_req),
.b_req(b_req),
.reset(reset),
.clock(clock),
.a_res(a_res),
.b_res(b_res)
);
// Clock
always begin
#5;
clock = ~clock;
end
initial begin
$monitor("Time:%4.0f clock:%b a_req:%b b_req:%b reset:%b a_res:%b b_res:%b", $time, clock,
a_req, b_req, reset, a_res, b_res);
clock = 1'b0;
reset = 1'b1;
a_req = 1'b0;
b_req = 1'b0;
@(negedge clock);
@(negedge clock);
reset = 1'b0;
// Start testing
@(negedge clock);
@(negedge clock);
@(negedge clock);
// Switch to A
a_req = 1'b1;
@(negedge clock);
@(negedge clock);
@(negedge clock);
// Back to Neither
a_req = 1'b0;
@(negedge clock);
@(negedge clock);
@(negedge clock);
@(negedge clock);
// Switch to A
a_req = 1'b1;
b_req = 1'b1;
@(negedge clock);
@(negedge clock);
@(negedge clock);
// Back to neither, then to B
a_req = 1'b0;
@(negedge clock);
@(negedge clock);
@(negedge clock);
@(negedge clock);
// Back to neither
b_req = 1'b0;
@(negedge clock);
@(negedge clock);
@(negedge clock);
@(negedge clock);
$finish;
end
endmodule
| 7.015571 |
module testbench_rx ();
localparam DURATION = 500; // duration of simulation (time units)
initial begin
#DURATION $finish;
end
wire clk, reset;
generator u1 (
clk,
reset
);
wire [4:0] reqs_in;
wire [4:0] acks_in;
wire [2:0] selected;
wire [7:0] datas_in [4:0];
localparam P = 5;
random_emitter #(
.PERC_ACTIVE(P),
.ID(0)
) s1 (
clk,
reset,
reqs_in[0],
acks_in[0],
datas_in[0]
);
random_emitter #(
.PERC_ACTIVE(P),
.ID(1)
) s2 (
clk,
reset,
reqs_in[1],
acks_in[1],
datas_in[1]
);
random_emitter #(
.PERC_ACTIVE(P),
.ID(2)
) s3 (
clk,
reset,
reqs_in[2],
acks_in[2],
datas_in[2]
);
random_emitter #(
.PERC_ACTIVE(P),
.ID(3)
) s4 (
clk,
reset,
reqs_in[3],
acks_in[3],
datas_in[3]
);
random_emitter #(
.PERC_ACTIVE(P),
.ID(4)
) s5 (
clk,
reset,
reqs_in[4],
acks_in[4],
datas_in[4]
);
random_consumer c1 (
clk,
reset,
req_out,
ack_out,
datas_in[selected]
);
arbiter a1 (
clk,
reset,
reqs_in,
acks_in,
req_out,
ack_out,
selected
);
endmodule
| 6.984192 |
module arbiter_top (
PCLK,
PRESETn,
PADDR,
PWRITE,
PSEL,
PENABLE,
PWDATA,
PRDATA,
PREADY,
APB_BYPASS,
APB_REQ,
APB_ARB_TYPE,
REQ,
GNT
);
// APB interface
input PCLK;
input PRESETn;
input PWRITE;
input PSEL;
input PENABLE;
input [7:0] PADDR;
input [7:0] PWDATA;
output [7:0] PRDATA;
output PREADY;
// APB registers
output APB_BYPASS;
output [3:0] APB_REQ;
output [2:0] APB_ARB_TYPE;
// Arbiter ports
input [3:0] REQ;
output [3:0] GNT;
// APB slave: APB registers
apb_slave u_apb_slave (
.PCLK(PCLK),
.PRESETn(PRESETn),
.PADDR(PADDR),
.PWRITE(PWRITE),
.PSEL(PSEL),
.PENABLE(PENABLE),
.PWDATA(PWDATA),
.PRDATA(PRDATA),
.PREADY(PREADY),
.APB_BYPASS(APB_BYPASS),
.APB_REQ(APB_REQ),
.APB_ARB_TYPE(APB_ARB_TYPE)
);
// Multi-mode arbiter
arbiter u_arbiter (
.clk(PCLK),
.rst_n(PRESETn),
.req(APB_BYPASS ? APB_REQ : REQ),
.arb_type(APB_ARB_TYPE),
.gnt(GNT)
);
endmodule
| 8.392315 |
module arbiter_URAM #(
parameter NUM_WR = 8,
parameter NUM_MUL = 4,
parameter DATA_WIDTH = 64,
parameter KEY_WIDTH = 32
) (
input [NUM_MUL*NUM_WR*DATA_WIDTH-1:0] rd_BRAM_out,
input [KEY_WIDTH-1:0] key_rd,
input [NUM_MUL-1:0] opt_rd,
output [NUM_MUL-1:0] arbiter_result
);
//key_rd, the key of write. opt_rd, the opt of rd_BRAM_out.
// key and opt can be gave by DFU.
// opt_rd only 1 bit, because we only need to care it is write/del.
wire [DATA_WIDTH-1:0] rd_xor_result[NUM_MUL-1:0];
wire [NUM_MUL-1:0] compare_result;
wire [NUM_MUL-1:0] rd_valid;
reg [NUM_MUL-1:0] write_only_arbiter;
//--------------------------xor NUM_WR elements, NUL_MUL results--------------------------//
genvar i;
generate
for (i = 0; i < NUM_MUL; i = i + 1) begin
xor_all_URAM #(NUM_WR, DATA_WIDTH) xor_all_u0 (
rd_BRAM_out[NUM_WR*DATA_WIDTH*i+:NUM_WR*DATA_WIDTH],
rd_xor_result[i]
);
end
endgenerate
//---------------------------generate the compare results--------------------------//
generate
for (i = 0; i < NUM_MUL; i = i + 1) begin
assign compare_result[i] = (rd_xor_result[i][KEY_WIDTH-1:0] == key_rd)&&(rd_valid[i] == 1'b1);
end
endgenerate
//---------------------------rd valid-------------------------------------------//
generate
for (i = 0; i < NUM_MUL; i = i + 1) begin
assign rd_valid[i] = rd_xor_result[i][DATA_WIDTH-1];
end
endgenerate
//---------------------------if opt is write, which place to write----------------------//
integer j;
always @(*) begin
write_only_arbiter = 0;
for (j = 0; j < NUM_MUL; j = j + 1) begin
if (rd_valid[j] == 1'b0) begin // if this place is empty, we could write here.
write_only_arbiter = 0;
write_only_arbiter[j] = 1'b1;
end
end
end
//------------------------------arbiter_result--------------------------------------//
assign arbiter_result = (opt_rd || compare_result) ? compare_result : write_only_arbiter;
//if opt_rd == 1(del), arbiter_result = compare_result. else, it is write. if compare_result == 0, it means, this is write. else, this is update.
endmodule
| 7.974177 |
module arb_counter (
out,
count,
init,
set,
reset,
clk
);
input set, reset, clk;
input [3:0] init;
output [3:0] count;
output out;
reg [3:0] count;
reg out;
always @(negedge clk or negedge set or negedge reset) begin
if (!set) begin
count = init;
out = 0;
end else if (!reset) begin
count = 4'b0011;
out = 0;
end else begin
case (count)
4'b0011: begin
count = 4'b0000;
out = 0;
end
4'b0000: begin
count = 4'b0001;
out = 0;
end
4'b0001: begin
count = 4'b0101;
out = 0;
end
4'b0101: begin
count = 4'b0010;
out = 0;
end
4'b0010: begin
count = 4'b0111;
out = 0;
end
4'b0111: begin
count = 4'b0110;
out = 0;
end
4'b0110: begin
count = 4'b0100;
out = 0;
end
4'b0100: begin
count = 4'b1001;
out = 0;
end
4'b1001: begin
count = 4'b1100;
out = 0;
end
4'b1100: begin
count = 4'b0011;
out = 1;
end
default: begin
count = 4'b0101;
out = 0;
end
endcase
end
end
endmodule
| 6.64194 |
module arb_counter_tb;
reg set, reset, clk;
reg [3:0] init;
wire [3:0] count;
wire out;
reg [3:0] count_p, count_c;
reg out_p, out_c;
arb_counter SA (
out,
count,
init,
set,
reset,
clk
);
parameter STDIN = 32'h8000_0000;
integer testid;
integer ret;
initial begin
clk = 1'b1;
forever #10 clk = ~clk;
end
//3 -> 0 -> 1 -> 5 -> 2 -> 7 -> 6 -> 4 -> 9 -> 12
initial begin
ret = $fscanf(STDIN, "%d", testid);
case (testid)
0: begin //reset the counter
#2 set = 1'b1;
reset = 1'b0;
#5 count_p = count;
out_p = out;
reset = 1'b1;
//#20 $display("%d", count);
#60 count_c = count;
out_c = out;
end
1: begin //set the counter
#2 set = 1'b0;
reset = 1'b1;
init = 4'b0110;
#5 count_p = count;
out_p = out;
set = 1'b1;
#80 count_c = count;
out_c = out;
end
2: begin //set the counter
#2 set = 1'b0;
reset = 1'b1;
init = 4'b1111;
#5 count_p = count;
out_p = out;
set = 1'b1;
#20 count_c = count;
out_c = out;
end
3: begin //set the counter
#2 set = 1'b1;
reset = 1'b0;
#5 count_p = count;
out_p = out;
reset = 1'b1;
#200 count_c = count;
out_c = out;
end
4: begin //set the counter
#2 set = 1'b0;
reset = 1'b1;
init = 4'b0110;
#5 count_p = count;
out_p = out;
set = 1'b1;
#200 count_c = count;
out_c = out;
end
5: begin //set the counter
#2 set = 1'b0;
reset = 1'b1;
init = 4'b0111;
#5 count_p = count;
out_p = out;
set = 1'b1;
#100 count_c = count;
out_c = out;
end
6: begin //set the counter
#2 set = 1'b0;
reset = 1'b1;
init = 4'b1001;
#5 count_p = count;
out_p = out;
set = 1'b1;
#20 count_c = count;
out_c = out;
end
7: begin //set the counter
#2 set = 1'b0;
reset = 1'b1;
init = 4'b1100;
#5 count_p = count;
out_p = out;
set = 1'b1;
#20 count_c = count;
out_c = out;
end
default: begin
$display("Bad testcase id %d", testid);
$finish();
end
endcase
if ( (testid == 0 & count_c == 5 & out_c == 0 & count_p == 3 & out_p == 0) ||
(testid == 1 & count_c == 3 & out_c == 1 & count_p == 6 & out_p == 0) ||
(testid == 2 & count_c == 5 & out_c == 0 & count_p == 15 & out_p == 0)||
(testid == 3 & count_c == 3 & out_c == 1 & count_p == 3 & out_p == 0) ||
(testid == 4 & count_c == 6 & out_c == 0 & count_p == 6 & out_p == 0) ||
(testid == 5 & count_c == 3 & out_c == 1 & count_p == 7 & out_p == 0) ||
(testid == 6 & count_c == 12 & out_c == 0 & count_p == 9 & out_p == 0) ||
(testid == 7 & count_c == 3 & out_c == 1 & count_p == 12 & out_p == 0))
pass();
else fail();
end
task fail;
begin
$display(
"Fail: for init(count,out)=(%d, %b), after period =%2d arb_counter(count, out)=(%d, %b) is WRONG",
count_p, out_p, $time / 20, count_c, out_c);
$finish();
end
endtask
task pass;
begin
$display(
"Pass: for init(count,out)=(%d, %b), after period =%2d arb_counter(count, out)=(%d, %b)",
count_p, out_p, $time / 20, count_c, out_c);
$finish();
end
endtask
endmodule
| 6.554006 |
module is used to pick which component gets to output to the val/rdy SPI wrapper if multiple components can send a valid message.
// The arbitrator puts an address header on the outgoing packet so that downstream components can tell which component sent the response
// The nbits parameter is the length of the message.
// The num_inputs parameter is the number of input components that the Arbitrator is selecting from. MUST be >= 2
// Author : Dilan Lakhani
// Date : Dec 19, 2021
module SPI_v3_components_ArbitratorVRTL
#(
parameter nbits = 4,
parameter num_inputs = 2,
parameter addr_nbits = $clog2(num_inputs)
)
(
input logic clk,
input logic reset,
// Receive Interface - need recv signals for each component connected to arbitrator
input logic recv_val [0:num_inputs-1],
output logic recv_rdy [0:num_inputs-1],
input logic [nbits-1:0] recv_msg [0:num_inputs-1],
// Send Interface
output logic send_val,
input logic send_rdy,
output logic [addr_nbits+nbits-1:0] send_msg
);
logic [addr_nbits-1:0] grants_index; // which input is granted access to send to SPI
logic [addr_nbits-1:0] old_grants_index;
logic [addr_nbits-1:0] encoder_out;
logic [nbits-1:0] send_msg_data;
logic [addr_nbits-1:0] send_msg_addr;
assign send_msg_data = recv_msg[grants_index];
assign send_msg_addr = grants_index;
assign send_val = recv_val[grants_index] & recv_rdy[grants_index];
assign send_msg = {send_msg_addr, send_msg_data}; // append component address to the beginning of the message
always_comb begin
// change grants_index if the last cycle's grant index is 0 (that component has finished sending its message)
if (!recv_val[old_grants_index]) begin
grants_index = encoder_out;
end else begin
grants_index = grants_index;
end
end
always_comb begin
for (integer j=0; j<num_inputs;j++) begin
// Only tell one input that the arbitrator is ready for it
if(grants_index == j) begin
recv_rdy[j] = send_rdy;
end else begin
recv_rdy[j] = 1'b0;
end
end
end
always_comb begin
// priority encoder that gives highest priority to the LSB and lowest to MSB
encoder_out = 0;
for(integer i=0; i<num_inputs; i++) begin
if (recv_val[num_inputs-1-i]) begin
encoder_out = num_inputs-1-i;
end
end
end
// One issue arises with having multiple Disassemblers. Since the SPI width is normally less than the size of a response,
// a PacketDisassembler component needs multiple cycles to fully send a message to the arbitrator. Thus, we do not want to
// change which Disassembler is allowed to send to the Arbitrator in the middle of a message.
// Fix this by holding a trailing value of the grants_index.
// We need to be able to check the recv_val of the old grants_index to make sure that it is not 1, then we can allow a different
// Disassembler to send a message
always_ff @(posedge clk) begin
if (reset) begin
old_grants_index <= 0;
end
else begin
old_grants_index <= grants_index;
end
end
endmodule
| 9.583561 |
module arbitrator_2_masters (
clk,
rst,
//master ports
m0_we_i,
m0_cyc_i,
m0_stb_i,
m0_sel_i,
m0_ack_o,
m0_dat_i,
m0_dat_o,
m0_adr_i,
m0_int_o,
m1_we_i,
m1_cyc_i,
m1_stb_i,
m1_sel_i,
m1_ack_o,
m1_dat_i,
m1_dat_o,
m1_adr_i,
m1_int_o,
//slave port
s_we_o,
s_cyc_o,
s_stb_o,
s_sel_o,
s_ack_i,
s_dat_o,
s_dat_i,
s_adr_o,
s_int_i
);
//control signals
input clk;
input rst;
//wishbone slave signals
output reg s_we_o;
output reg s_stb_o;
output reg s_cyc_o;
output reg [3:0] s_sel_o;
output reg [31:0] s_adr_o;
output reg [31:0] s_dat_o;
input [31:0] s_dat_i;
input s_ack_i;
input s_int_i;
//wishbone master signals
input m0_we_i;
input m0_cyc_i;
input m0_stb_i;
input [3:0] m0_sel_i;
input [31:0] m0_adr_i;
input [31:0] m0_dat_i;
output [31:0] m0_dat_o;
output m0_ack_o;
output m0_int_o;
input m1_we_i;
input m1_cyc_i;
input m1_stb_i;
input [3:0] m1_sel_i;
input [31:0] m1_adr_i;
input [31:0] m1_dat_i;
output [31:0] m1_dat_o;
output m1_ack_o;
output m1_int_o;
//this should be parameterized
reg [7:0] master_select;
//master select block
parameter MASTER_NO_SEL = 8'hFF;
parameter MASTER_0 = 0;
parameter MASTER_1 = 1;
always @(rst or master_select or m0_stb_i or m1_stb_i) begin
if (rst) begin
master_select <= MASTER_NO_SEL;
end else begin
case (master_select)
MASTER_0: begin
if (~m0_stb_i) begin
master_select <= MASTER_NO_SEL;
end
end
MASTER_1: begin
if (~m1_stb_i) begin
master_select <= MASTER_NO_SEL;
end
end
default: begin
//nothing selected
if (m0_stb_i) begin
master_select <= MASTER_0;
end else if (m1_stb_i) begin
master_select <= MASTER_1;
end
end
endcase
end
end
//write select block
always @(master_select or m0_we_i or m1_we_i) begin
case (master_select)
MASTER_0: begin
s_we_o <= m0_we_i;
end
MASTER_1: begin
s_we_o <= m1_we_i;
end
default: begin
s_we_o <= 1'h0;
end
endcase
end
//strobe select block
always @(master_select or m0_we_i or m1_we_i) begin
case (master_select)
MASTER_0: begin
s_stb_o <= m0_stb_i;
end
MASTER_1: begin
s_stb_o <= m1_stb_i;
end
default: begin
s_stb_o <= 1'h0;
end
endcase
end
//cycle select block
always @(master_select or m0_cyc_i or m1_cyc_i) begin
case (master_select)
MASTER_0: begin
s_cyc_o <= m0_cyc_i;
end
MASTER_1: begin
s_cyc_o <= m1_cyc_i;
end
default: begin
s_cyc_o <= 1'h0;
end
endcase
end
//select select block
always @(master_select or m0_sel_i or m1_sel_i) begin
case (master_select)
MASTER_0: begin
s_sel_o <= m0_sel_i;
end
MASTER_1: begin
s_sel_o <= m1_sel_i;
end
default: begin
s_sel_o <= 4'h0;
end
endcase
end
//address seelct block
always @(master_select or m0_adr_i or m1_adr_i) begin
case (master_select)
MASTER_0: begin
s_adr_o <= m0_adr_i;
end
MASTER_1: begin
s_adr_o <= m1_adr_i;
end
default: begin
s_adr_o <= 32'h00000000;
end
endcase
end
//data select block
always @(master_select or m0_dat_i or m1_dat_i) begin
case (master_select)
MASTER_0: begin
s_dat_o <= m0_dat_i;
end
MASTER_1: begin
s_dat_o <= m1_dat_i;
end
default: begin
s_dat_o <= 32'h00000000;
end
endcase
end
//assign block
assign m0_ack_o = (master_select == MASTER_0) ? s_ack_i : 0;
assign m0_dat_o = (master_select == MASTER_0) ? s_dat_i : 0;
assign m0_int_o = (master_select == MASTER_0) ? s_int_i : 0;
assign m1_ack_o = (master_select == MASTER_1) ? s_ack_i : 0;
assign m1_dat_o = (master_select == MASTER_1) ? s_dat_i : 0;
assign m1_int_o = (master_select == MASTER_1) ? s_int_i : 0;
endmodule
| 8.041478 |
module arbitrer_r1_2ph ( /*AUTOARG*/
// Outputs
a1,
a2,
g1,
g2,
// Inputs
r1,
r2,
d1,
d2,
rstn
);
input r1;
output a1;
input r2;
output a2;
output g1;
input d1;
output g2;
input d2;
input rstn;
wire mutex_r1, mutex_r2;
wire toogle_in1, toggle_in2;
wire cm1, cm2;
wire g1_released, g2_released;
muller2 U_MULLER_1 (
.a(!g1_released),
.b(r1),
.rstn(rstn),
.z(cm1)
);
muller2 U_MULLER_2 (
.a(!g2_released),
.b(r2),
.rstn(rstn),
.z(cm2)
);
xor2 U_XOR2_1 (
.a(cm1),
.b(d1),
.z(mutex_r1)
);
xor2 U_XOR2_2 (
.a(cm2),
.b(d2),
.z(mutex_r2)
);
mutex U_MUTEX (
.r1(mutex_r1),
.r2(mutex_r2),
.g1(toggle_in1),
.g2(toggle_in2)
);
`ifndef USE_TOGGLE_SIMPLE
toggle U_TOGGLE_1 (
.in(toggle_in1),
.dot(g1),
.blank(g1_released),
.rstn(rstn)
);
toggle U_TOGGLE_2 (
.in(toggle_in2),
.dot(g2),
.blank(g2_released),
.rstn(rstn)
);
`else
toggle_simple U_TOGGLE_1 (
.in(toggle_in1),
.dot(g1),
.blank(g1_released),
.rstn(rstn)
);
toggle_simple U_TOGGLE_2 (
.in(toggle_in2),
.dot(g2),
.blank(g2_released),
.rstn(rstn)
);
`endif
// ack feedback on input ports
muller2 U_MULLER_ACK1 (
.a(r1),
.b(d1),
.rstn(rstn),
.z(a1)
);
muller2 U_MULLER_ACK2 (
.a(r2),
.b(d2),
.rstn(rstn),
.z(a2)
);
`ifdef DEBUG
assign input_port1_ongoing_req = r1 ^ a1;
assign input_port2_ongoing_req = r2 ^ a2;
assign output_port1_unstable = g1 ^ d1;
assign output_port2_unstable = g2 ^ d2;
assign error = output_port1_unstable & output_port2_unstable;
initial begin
#1;
@(posedge error);
$display("-E arbitrer_r1_2ph : error found in protocol");
#100;
$finish;
end
`endif
endmodule
| 6.736451 |
module arbitrer_r1_2ph ( /*AUTOARG*/
// Outputs
a1,
a2,
g1,
g2,
// Inputs
r1,
r2,
d1,
d2,
rstn
);
input r1;
output a1;
input r2;
output a2;
output g1;
input d1;
output g2;
input d2;
input rstn;
wire mutex_r1, mutex_r2;
wire latch_en1, latch_en2;
xor2 U_XOR2_1 (
.a(r1),
.b(d1),
.z(mutex_r1)
);
xor2 U_XOR2_2 (
.a(r2),
.b(d2),
.z(mutex_r2)
);
mutex U_MUTEX (
.r1(mutex_r1),
.r2(mutex_r2),
.g1(latch_en1),
.g2(latch_en2)
);
latch U_LATCH_1 (
.i(r1),
.q(g1),
.en(latch_en1),
.rstn(rstn)
);
latch U_LATCH_2 (
.i(r2),
.q(g2),
.en(latch_en2),
.rstn(rstn)
);
// ack feedback on input ports
muller2 U_MULLER_1 (
.a(r1),
.b(d1),
.rstn(rstn),
.z(a1)
);
muller2 U_MULLER_2 (
.a(r2),
.b(d2),
.rstn(rstn),
.z(a2)
);
endmodule
| 6.736451 |
module arbitro (
input clk,
input almost_full0,
input almost_full1,
input almost_full2,
input almost_full3,
input [3:0] state,
input empty0_naranja,
input empty1_naranja,
input empty2_naranja,
input empty3_naranja,
input empty0_morado,
input empty1_morado,
input empty2_morado,
input empty3_morado,
output reg push,
// output reg push1,
// output reg push2,
// output reg push3,
output reg pop0,
output reg pop1,
output reg pop2,
output reg pop3,
output reg [7:0] empties
);
always @(posedge clk) begin
if (state == 4'b0001) begin
push <= 0;
end else begin
push <= 1;
end
end
//Lógica de prioridades
always @(*) begin
if (state == 4'b0001) begin
pop0 = 0;
pop1 = 0;
pop2 = 0;
pop3 = 0;
// push=1;
// push1=1;
// push2=1;
// push3=1;
end else begin
if (almost_full0 | almost_full1 | almost_full2 | almost_full3) begin
pop0 = 0;
pop1 = 0;
pop2 = 0;
pop3 = 0;
end else begin
// push=1;
//logica de cambio de fifo
//logica del pop por los siglos de los siglos
if (empty0_naranja == 0) begin //if logica pops naranjas
pop0 = 1;
pop1 = 0;
pop2 = 0;
pop3 = 0;
end else begin
if (empty1_naranja == 0) begin //if logica pops naranjas
pop0 = 0;
pop1 = 1;
pop2 = 0;
pop3 = 0;
end else begin
if (empty2_naranja == 0) begin //if logica pops naranjas
pop0 = 0;
pop1 = 0;
pop2 = 1;
pop3 = 0;
end else begin
if (empty3_naranja == 0) begin //if logica pops naranjas
pop0 = 0;
pop1 = 0;
pop2 = 0;
pop3 = 1;
end else begin
pop0 = 0;
pop1 = 0;
pop2 = 0;
pop3 = 0;
end
end
end
end
// end
//logica de fifos morados
// if(almost_full0 | almost_full1 | almost_full2 | almost_full3)begin
// // push=0;
// // push1=0;
// // push2=0;
// // push3=0;
// end
// else begin
// push=1;
// push1=1;
// push2=1;
// push3=1;
end
end
end
//encapsulamiento de los empties para eventual entrada de FSM
always @(*) begin
if (state == 4'b0001) begin
empties <= 8'b00000000;
end else begin
empties[0] = empty0_naranja;
empties[1] = empty1_naranja;
empties[2] = empty2_naranja;
empties[3] = empty3_naranja;
empties[4] = empty0_morado;
empties[5] = empty1_morado;
empties[6] = empty2_morado;
empties[7] = empty3_morado;
end
end
endmodule
| 6.71338 |
module arbitro2 #(
// Tamaño de cada celda de memoria, [11:10] clase [9:8] destino [7:0] datos
parameter WORD_SIZE = 12
) (
input clk,
input reset,
input [WORD_SIZE-1:0] data_in_arb,
input fifo_empty,
input [3:0] fifos_almost_full,
output reg [WORD_SIZE-1:0] data_out_arb,
output reg pop,
output reg [3:0] push
);
reg [1:0] class;
always @(posedge clk) begin
if (!reset) begin
pop <= 0;
push <= 0;
data_out_arb <= 0;
end
else begin
if (fifo_empty) begin
pop <= 0;
push <= 0;
data_out_arb <= 0;
end
else begin
if (fifos_almost_full[3] | fifos_almost_full[2] | fifos_almost_full[1] | fifos_almost_full[0]) begin
pop <= 0;
push <= 0;
data_out_arb <= 0;
end
else begin
if (fifo_empty) pop <= 0;
else pop <= 1;
push <= 0;
end
end
if (pop) begin
case (class)
2'b00: begin
push[0] <= 1;
data_out_arb <= data_in_arb;
end
2'b01: begin
push[1] <= 1;
data_out_arb <= data_in_arb;
end
2'b10: begin
push[2] <= 1;
data_out_arb <= data_in_arb;
end
2'b11: begin
push[3] <= 1;
data_out_arb <= data_in_arb;
end
endcase
end
else data_out_arb <= 0;
end
end
always @(*) begin
class = data_in_arb[WORD_SIZE-1:WORD_SIZE-2];
end
endmodule
| 7.13765 |
module arbitro_demux (
input [5:0] mux_arbitro_1,
input reset_L,
destiny,
output reg [5:0] D0_out,
D1_out
);
always @(*) begin
if (~reset_L) begin
D0_out = 0;
D1_out = 0;
end else begin
if (destiny == 0) D0_out = mux_arbitro_1;
else if (destiny == 1) D1_out = mux_arbitro_1;
end
end
endmodule
| 6.72883 |
module logica_pops_synth (
VC0_empty,
VC1_empty,
D0_pause,
D1_pause,
clk,
reset_L,
VC0_pop_synth,
VC1_pop_synth,
pop_delay_VC0,
pop_delay_VC1
);
(* src = "./arbitro_mux_synthes/logica_pops_synth.v:4" *)
wire _00_;
(* src = "./arbitro_mux_synthes/logica_pops_synth.v:4" *)
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
(* src = "./arbitro_mux_synthes/logica_pops_synth.v:1" *)
input D0_pause;
(* src = "./arbitro_mux_synthes/logica_pops_synth.v:1" *)
input D1_pause;
(* src = "./arbitro_mux_synthes/logica_pops_synth.v:1" *)
input VC0_empty;
(* src = "./arbitro_mux_synthes/logica_pops_synth.v:2" *)
output VC0_pop_synth;
(* src = "./arbitro_mux_synthes/logica_pops_synth.v:1" *)
input VC1_empty;
(* src = "./arbitro_mux_synthes/logica_pops_synth.v:2" *)
output VC1_pop_synth;
(* src = "./arbitro_mux_synthes/logica_pops_synth.v:1" *)
input clk;
(* src = "./arbitro_mux_synthes/logica_pops_synth.v:2" *)
output pop_delay_VC0;
(* src = "./arbitro_mux_synthes/logica_pops_synth.v:2" *)
output pop_delay_VC1;
(* src = "./arbitro_mux_synthes/logica_pops_synth.v:1" *)
input reset_L;
NOT _08_ (
.A(reset_L),
.Y(_02_)
);
NOT _09_ (
.A(VC1_empty),
.Y(_03_)
);
NOT _10_ (
.A(D1_pause),
.Y(_04_)
);
NOR _11_ (
.A(_02_),
.B(D0_pause),
.Y(_05_)
);
NAND _12_ (
.A(_04_),
.B(_05_),
.Y(_06_)
);
NAND _13_ (
.A(VC0_empty),
.B(_03_),
.Y(_07_)
);
NOR _14_ (
.A(_06_),
.B(_07_),
.Y(VC1_pop_synth)
);
NOR _15_ (
.A(VC0_empty),
.B(_06_),
.Y(VC0_pop_synth)
);
NOR _16_ (
.A(_06_),
.B(_07_),
.Y(_01_)
);
NOR _17_ (
.A(VC0_empty),
.B(_06_),
.Y(_00_)
);
(* src = "./arbitro_mux_synthes/logica_pops_synth.v:4" *)
DFF _18_ (
.C(clk),
.D(_00_),
.Q(pop_delay_VC0)
);
(* src = "./arbitro_mux_synthes/logica_pops_synth.v:4" *)
DFF _19_ (
.C(clk),
.D(_01_),
.Q(pop_delay_VC1)
);
endmodule
| 6.842325 |
module arbitro_mux (
input reset_L,
clk,
input [5:0] VC0,
input [5:0] VC1,
input pop_delay_VC0,
pop_delay_VC1,
input VC0_empty,
VC1_empty,
output reg [5:0] arbitro_D0_out,
arbitro_D1_out,
output reg D0_push,
D1_push
);
always @(posedge clk) begin
if (~reset_L) begin
arbitro_D0_out <= 0;
arbitro_D1_out <= 0;
D0_push <= 0;
D1_push <= 0;
end else begin
if (~VC0_empty) begin
if (pop_delay_VC0) begin
if (VC0[4] == 0) begin
arbitro_D0_out <= VC0;
arbitro_D1_out <= 0;
D0_push <= 1;
D1_push <= 0;
end else begin
arbitro_D1_out <= VC0;
arbitro_D0_out <= 0;
D1_push <= 1;
D0_push <= 0;
end
end else begin
arbitro_D0_out <= 0;
arbitro_D1_out <= 0;
D0_push <= 0;
D1_push <= 0;
end
end else if (~VC1_empty) begin
if (pop_delay_VC1) begin
if (VC1[4] == 0) begin
arbitro_D0_out <= VC1;
arbitro_D1_out <= 0;
D0_push <= 1;
D1_push <= 0;
end else begin
arbitro_D1_out <= VC1;
arbitro_D0_out <= 0;
D0_push <= 0;
D1_push <= 1;
end
end else begin
arbitro_D0_out <= 0;
arbitro_D1_out <= 0;
D0_push <= 0;
D1_push <= 0;
end
end else begin
arbitro_D0_out <= 0;
arbitro_D1_out <= 0;
D0_push <= 0;
D1_push <= 0;
end
end
end
endmodule
| 6.514522 |
module ArbPriorityRR (
clk,
rst_n,
req,
grant
);
parameter REQ_NUM = 4;
parameter COUNTER_W = clog2(REQ_NUM);
//
input clk;
input rst_n;
input [REQ_NUM-1:0] req;
output reg [REQ_NUM-1:0] grant;
//
reg [COUNTER_W-1:0] rrCounter;
wire incCounter;
wire [REQ_NUM-1:0] prioritySel;
wire [REQ_NUM*REQ_NUM-1:0] reqOut;
wire [REQ_NUM*REQ_NUM-1:0] reqOutVector;
wire noGrant;
wire [REQ_NUM-1:0] nextGrant;
//
assign noGrant = ~|grant[REQ_NUM-1:0];
//Increase counter if no request or END of current request
assign incCounter = (~|req[REQ_NUM-1:0]) | |(~req[REQ_NUM-1:0] & grant[REQ_NUM-1:0]);
//
always @(posedge clk, negedge rst_n) begin
if (~rst_n) rrCounter[COUNTER_W-1:0] <= {COUNTER_W{1'b0}};
else if (incCounter) begin
if (rrCounter[COUNTER_W-1:0] == REQ_NUM - 1) rrCounter[COUNTER_W-1:0] <= {COUNTER_W{1'b0}};
else rrCounter[COUNTER_W-1:0] <= rrCounter[COUNTER_W-1:0] + 1'b1;
end
end
//
//Select priority logic
//
generate
genvar i;
//
for (i = 0; i < REQ_NUM; i = i + 1) begin : uPrioritySel
assign prioritySel[i] = (rrCounter[COUNTER_W-1:0] == i);
end //for loop
endgenerate
//
//Connect inputs to priority logic
//
//for req[0]
priorityLogic #(
.REQ_NUM(REQ_NUM)
) priorityLogic0 (
.Sel(prioritySel[0]),
.reqIn(req[REQ_NUM-1:0]),
.reqOut(reqOut[REQ_NUM-1:0])
);
generate
genvar j;
for (j = 1; j < REQ_NUM; j = j + 1) begin : uPResult
//Note: Can NOT declare instance array priorityLogic[j] -> Can NOT synthesize
//Must declare priorityLogic[j:j]
priorityLogic #(
.REQ_NUM(REQ_NUM)
) priorityLogic (
.Sel(prioritySel[j]),
.reqIn({req[j-1:0], req[REQ_NUM-1:j]}),
.reqOut(reqOut[REQ_NUM*(j+1)-1:j*REQ_NUM])
);
end //for loop
endgenerate
//
//Shift the output result
//
generate
genvar x;
assign reqOutVector[REQ_NUM-1:0] = reqOut[REQ_NUM-1:0];
for (x = 1; x < REQ_NUM; x = x + 1) begin : reOrderBit
//Case REQ_NUM = 4
//x=1 [7:4] = [6:4][7:7]
//x=2 [11:8] = [9:8][11:10]
//x=3 [15:12] = [12:12][15:13]
assign reqOutVector[REQ_NUM*(x+1)-1:x*REQ_NUM] = {
reqOut[REQ_NUM*(x+1)-1-x:x*REQ_NUM], reqOut[REQ_NUM*(x+1)-1:REQ_NUM*(x+1)-x]
};
end
endgenerate
//
//Create grant
//
generate
genvar y;
for (y = 0; y < REQ_NUM; y = y + 1) begin : nextGrantGen
assign nextGrant[y] = orOut(reqOutVector[REQ_NUM*REQ_NUM-1:0], y);
end
endgenerate
//
always @(posedge clk, negedge rst_n) begin
if (~rst_n) grant[REQ_NUM-1:0] <= {REQ_NUM{1'b0}};
else if (noGrant) grant[REQ_NUM-1:0] <= nextGrant[REQ_NUM-1:0];
else grant[REQ_NUM-1:0] <= nextGrant[REQ_NUM-1:0] & grant[REQ_NUM-1:0];
end
//
//For synthesis
//
function orOut;
input [REQ_NUM*REQ_NUM-1:0] orIn;
input integer index;
integer i1;
begin
orOut = 1'b0;
for (i1 = 0; i1 < REQ_NUM; i1 = i1 + 1) begin
orOut = orOut | orIn[index+i1*REQ_NUM];
end
end
endfunction
//
//Not for sunthesis, Only use to calculate the parameter
//
function integer clog2;
input integer value;
integer ii;
begin
clog2 = 0;
for (ii = 0; 2 ** ii < value; ii = ii + 1) begin
clog2 = ii + 1;
end
end
endfunction
//
endmodule
| 6.772825 |
module priorityLogic (
Sel,
reqIn,
reqOut
);
parameter REQ_NUM = 2;
//
input Sel;
input [REQ_NUM-1:0] reqIn;
output wire [REQ_NUM-1:0] reqOut;
//
assign reqOut[0] = Sel ? reqIn[0] : 1'b0;
generate
genvar k;
for (k = 1; k < REQ_NUM; k = k + 1) begin : uPLogic
assign reqOut[k] = Sel ? (reqIn[k] & ~|reqIn[k-1:0]) : 1'b0;
end
endgenerate
endmodule
| 6.502438 |
module arb_decoder (
bus_addr,
rd_wr_in,
rd_wr_out,
en,
dma_en,
mem_en,
io_en
);
parameter DMA_FRAME = 20'h00001;
parameter DISK_FRAME = 20'h00003;
parameter BUSADDRW = 32;
input [BUSADDRW-1:0] bus_addr;
input rd_wr_in;
output rd_wr_out;
input en;
output dma_en;
output mem_en;
output io_en;
assign rd_wr_out = rd_wr_in;
// TODO implement
wire dma_sel;
wire disk_sel;
wire mem_sel;
wire [19:0] phys_frame = bus_addr[19:0];
compare#(
.WIDTH(20)
) (
phys_frame, DMA_FRAME, dma_sel
); compare#(
.WIDTH(20)
) (
phys_frame, DISK_FRAME, disk_sel
);
nor2$ mem_nor (
mem_sel,
dma_sel,
disk_sel
);
wire dma_en;
wire disk_en;
wire mem_en;
and2$ dma_and (
dma_en,
en,
dma_sel
);
and2$ disk_and (
io_en,
en,
disk_sel
);
and2$ mem_and (
mem_en,
en,
mem_sel
);
endmodule
| 7.007837 |
module arb_pattern_type_muxes (
Arb_WhichPort, // I [C_ARB_PORT_ENCODING_WIDTH-1:0]
PI_ArbPatternType_I, // I [C_NUM_PORTS*C_ARB_PATTERN_TYPE_WIDTH-1:0]
PI_ArbPatternType_O // O [C_ARB_PATTERN_TYPE_WIDTH-1:0]
);
parameter C_NUM_PORTS = 8; // Allowed Values: 1-8
parameter C_ARB_PORT_ENCODING_WIDTH = 3; // Allowed Values: 1-3
parameter C_ARB_PATTERN_TYPE_WIDTH = 4; // Allowed Values: 4
input [C_ARB_PORT_ENCODING_WIDTH-1:0] Arb_WhichPort;
input [C_NUM_PORTS*C_ARB_PATTERN_TYPE_WIDTH-1:0] PI_ArbPatternType_I;
output [C_ARB_PATTERN_TYPE_WIDTH-1:0] PI_ArbPatternType_O;
reg [ C_ARB_PATTERN_TYPE_WIDTH-1:0] PI_ArbPatternType_O = 0;
wire [8*C_ARB_PATTERN_TYPE_WIDTH-1:0] PI_ArbPatternType_I_i;
assign PI_ArbPatternType_I_i = PI_ArbPatternType_I;
generate
if (C_NUM_PORTS == 1) begin : instantiate_Arb_PatternType_O_1port
always @(PI_ArbPatternType_I_i) begin
PI_ArbPatternType_O = PI_ArbPatternType_I_i[1*C_ARB_PATTERN_TYPE_WIDTH-1:0*C_ARB_PATTERN_TYPE_WIDTH];
end
end else begin : instantiate_Arb_PatternType_O_2to8ports
always @(Arb_WhichPort or PI_ArbPatternType_I_i)
case (Arb_WhichPort)
0:
PI_ArbPatternType_O = PI_ArbPatternType_I_i[1*C_ARB_PATTERN_TYPE_WIDTH-1:0*C_ARB_PATTERN_TYPE_WIDTH];
1:
if (C_NUM_PORTS > 1)
PI_ArbPatternType_O = PI_ArbPatternType_I_i[2*C_ARB_PATTERN_TYPE_WIDTH-1:1*C_ARB_PATTERN_TYPE_WIDTH];
else PI_ArbPatternType_O = 0;
2:
if (C_NUM_PORTS > 2)
PI_ArbPatternType_O = PI_ArbPatternType_I_i[3*C_ARB_PATTERN_TYPE_WIDTH-1:2*C_ARB_PATTERN_TYPE_WIDTH];
else PI_ArbPatternType_O = 0;
3:
if (C_NUM_PORTS > 3)
PI_ArbPatternType_O = PI_ArbPatternType_I_i[4*C_ARB_PATTERN_TYPE_WIDTH-1:3*C_ARB_PATTERN_TYPE_WIDTH];
else PI_ArbPatternType_O = 0;
4:
if (C_NUM_PORTS > 4)
PI_ArbPatternType_O = PI_ArbPatternType_I_i[5*C_ARB_PATTERN_TYPE_WIDTH-1:4*C_ARB_PATTERN_TYPE_WIDTH];
else PI_ArbPatternType_O = 0;
5:
if (C_NUM_PORTS > 5)
PI_ArbPatternType_O = PI_ArbPatternType_I_i[6*C_ARB_PATTERN_TYPE_WIDTH-1:5*C_ARB_PATTERN_TYPE_WIDTH];
else PI_ArbPatternType_O = 0;
6:
if (C_NUM_PORTS > 6)
PI_ArbPatternType_O = PI_ArbPatternType_I_i[7*C_ARB_PATTERN_TYPE_WIDTH-1:6*C_ARB_PATTERN_TYPE_WIDTH];
else PI_ArbPatternType_O = 0;
7:
if (C_NUM_PORTS > 7)
PI_ArbPatternType_O = PI_ArbPatternType_I_i[8*C_ARB_PATTERN_TYPE_WIDTH-1:7*C_ARB_PATTERN_TYPE_WIDTH];
else PI_ArbPatternType_O = 0;
endcase
end
endgenerate
endmodule
| 7.374951 |
module forms the qualification engine for a single master as
// part of a larger arbitration engine for a slave. It would typically
// be instantiated from arb_select_master.v to form a complete arbitor solution.
//
module arb_qualify_master
#(
parameter WIDTH=16 // Bit width of destination field.
)
(
input clk,
input reset,
input clear,
// Header signals
input [WIDTH-1:0] header,
input header_valid,
// Slave Confg Signals
input [WIDTH-1:0] slave_addr,
input [WIDTH-1:0] slave_mask,
input slave_valid,
// Arbitration flags
output reg master_valid,
input master_ack
);
localparam WAIT_HEADER_VALID = 0;
localparam MATCH = 1;
localparam WAIT_HEADER_NOT_VALID = 2;
reg [1:0] state, next_state;
// Does masked slave address match header field for dest from master?
assign header_match = ((header & slave_mask) == (slave_addr & slave_mask)) && slave_valid;
always @(posedge clk)
if (reset | clear) begin
state <= WAIT_HEADER_VALID;
master_valid <= 0;
end else
begin
case(state)
//
// Wait here until Masters FIFO presents a valid header word.
//
WAIT_HEADER_VALID: begin
if (header_valid)
if (header_match) begin
state <= MATCH;
master_valid <= 1;
end else
next_state <= WAIT_HEADER_NOT_VALID;
end
//
// There should only ever be one match across various arbitors
// if they are configured correctly and since the backing FIFO in the
// master should not start to drain until the arbitration is won
// by that master, master_ack should always preceed de-assertion of
// header_valid so we don't check for the other order of deassertion.
//
MATCH: begin
if (master_ack) begin
master_valid <= 0;
state <= WAIT_HEADER_NOT_VALID;
end
end
//
// Wait here until this master starts to drain this packet from his FIFO.
//
WAIT_HEADER_NOT_VALID: begin
if (!header_valid) begin
state <= WAIT_HEADER_VALID;
end
end
endcase // case(state)
end // else: !if(reset | clear)
endmodule
| 8.218298 |
module arb_req_pending_muxes (
Arb_ReqPending, // I [C_NUM_PORTS-1:0]
Arb_PortNum, // I [C_ARB_PORT_ENCODING_WIDTH-1:0]
Arb_PatternEnable // O
);
parameter C_NUM_PORTS = 8; // Allowed Values: 1-8
parameter C_ARB_PORT_ENCODING_WIDTH = 3; // Allowed Values: 1-3
input [C_NUM_PORTS-1:0] Arb_ReqPending;
input [C_ARB_PORT_ENCODING_WIDTH-1:0] Arb_PortNum;
output Arb_PatternEnable;
reg Arb_PatternEnable = 0;
wire [2:0] arb_portnum_i;
wire [7:0] arb_reqpending_i;
// Instantiate Enable Mux
assign arb_portnum_i = Arb_PortNum;
assign arb_reqpending_i = Arb_ReqPending;
always @(arb_portnum_i or arb_reqpending_i)
case (arb_portnum_i)
0: Arb_PatternEnable <= arb_reqpending_i[0];
1: Arb_PatternEnable <= arb_reqpending_i[1];
2: Arb_PatternEnable <= arb_reqpending_i[2];
3: Arb_PatternEnable <= arb_reqpending_i[3];
4: Arb_PatternEnable <= arb_reqpending_i[4];
5: Arb_PatternEnable <= arb_reqpending_i[5];
6: Arb_PatternEnable <= arb_reqpending_i[6];
7: Arb_PatternEnable <= arb_reqpending_i[7];
endcase // case(arb_portnum_i)
endmodule
| 6.856042 |
module implements an high speed round robin arbiter
module arb_rr #(parameter NUM_REQS=4) (
input logic clock,
input logic reset,
output logic [NUM_REQS-1:0] grants,
input logic pop,
input logic [NUM_REQS-1:0] reqs
);
logic [NUM_REQS-1:0] mask_code;
logic [NUM_REQS-1:0] masked_reqs = mask_code & reqs;
logic [NUM_REQS-1:0] reqs_code;
logic [NUM_REQS-1:0] masked_reqs_code;
genvar bn;
generate
for (bn = 0; bn < NUM_REQS; bn = bn + 1)
begin : reqs_code_gen_block
assign reqs_code[bn] = |( reqs[0 +: (bn + 1)]);
assign masked_reqs_code[bn] = |(masked_reqs[0 +: (bn + 1)]);
end
endgenerate
logic any_masked_req = |masked_reqs;
logic [NUM_REQS-1:0] muxed_reqs_code = any_masked_req ? masked_reqs_code : reqs_code;
logic [NUM_REQS-1:0] mask_code_next;
generate
// Check corner case of only one master
if (NUM_REQS == 1)
assign mask_code_next = 1'b0;
else
assign mask_code_next = {muxed_reqs_code[0 +: (NUM_REQS-1)], 1'b0}; // shift muxed_reqs_code left by one-bit
endgenerate
assign grants = muxed_reqs_code ^ mask_code_next; // grant is simple xor to find one-hot location of selected reqs code
// mask_code
logic req_valid;
assign req_valid = (|reqs) && pop; //if there are requests and asked for a pop
// CLK RST EN DOUT DIN DEF
`RST_EN_FF(clock, reset, req_valid, mask_code, mask_code_next, '0)
endmodule
| 6.667836 |
module arb_test ();
reg clk, reset_n, wreq, fifo_full;
reg [7:0] memadrs, memdata;
wire [7:0] synth_ctrl, synth_data;
reg [7:0] test_state;
reg [7:0] wait_cnt;
synth_arb arb1 (
.clk(clk),
.reset_n(reset_n),
.memadrs(memadrs),
.memdata(memdata),
.wreq(wreq),
.synth_ctrl(synth_ctrl),
.synth_data(synth_data),
.fifo_full(fifo_full)
);
parameter CLOCK = 10;
initial clk <= 0;
always #(CLOCK / 2) clk <= ~clk;
initial test_state <= 0;
initial reset_n <= 1;
initial wreq <= 0;
initial fifo_full <= 0;
initial memadrs <= 0;
initial memdata <= 0;
initial wait_cnt <= 0;
always @(posedge clk) begin
case (test_state)
8'D0: test_state <= test_state + 1;
8'D1: begin
test_state <= test_state + 1;
reset_n <= 0;
end
8'D2: begin
test_state <= test_state + 1;
reset_n <= 1;
end
8'D3: begin //Normal Operation
if (wait_cnt != 8'b11111111) begin
wait_cnt <= wait_cnt + 1;
end else begin
wait_cnt <= 0;
test_state <= test_state + 1;
end
end
8'D4: begin //FIFO Full Operation Test
if (wait_cnt != 8'b00001111) begin
wait_cnt <= wait_cnt + 1;
fifo_full <= 1;
end else begin
wait_cnt <= 0;
fifo_full <= 0;
test_state <= test_state + 1;
end
end
8'D5: begin //Frequency Register Write Operation 1
if (wait_cnt != 8'b00001111) begin
memadrs <= 8'h01;
memdata <= 8'h08;
wreq <= 1;
wait_cnt <= wait_cnt + 1;
test_state <= test_state;
end else begin
memadrs <= 8'h00;
memdata <= 8'h00;
wreq <= 0;
test_state <= test_state + 1;
wait_cnt <= 0;
end
end
8'D6: begin
wreq <= 0;
test_state <= test_state + 1;
end
8'D7: begin //Frequency Register Write Operation 2
if (wait_cnt != 8'b00001111) begin
memadrs <= 8'h11;
memdata <= 8'h0A;
wreq <= 1;
wait_cnt <= wait_cnt + 1;
test_state <= test_state;
end else begin
memadrs <= 8'h00;
memdata <= 8'h00;
wreq <= 0;
test_state <= test_state + 1;
wait_cnt <= 0;
end
end
8'D8: begin
wreq <= 0;
test_state <= test_state + 1;
end
8'D9: test_state <= test_state;
default: test_state <= 0;
endcase
end
endmodule
| 6.90103 |
module arb_v (
reset,
clk,
dma_breq,
dma_grant,
tdsp_breq,
tdsp_grant
);
input reset, clk, dma_breq, tdsp_breq;
output reg dma_grant, tdsp_grant;
// include state encodings defined in arb.h
`include "arb.h"
// STATE REGISTERS
reg [2:0] state; // current state
reg [2:0] next_state;
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= `IDLE;
end else state <= next_state;
end
// Compute next state based on present state: combinational logic
always @(state or tdsp_breq or dma_breq) begin
case (state)
`IDLE: begin
if (tdsp_breq) next_state = `GRANT_TDSP;
else if (dma_breq) next_state = `GRANT_DMA;
else next_state = `IDLE;
end
`GRANT_TDSP: begin
if (tdsp_breq == 1'b0) next_state = `CLEAR;
else next_state = `GRANT_TDSP;
end
`GRANT_DMA: begin
if (dma_breq == 1'b0) next_state = `CLEAR;
else next_state = `GRANT_DMA;
end
`DMA_PRI: begin
if (tdsp_breq) next_state = `GRANT_TDSP;
else if (dma_breq) next_state = `GRANT_DMA;
else if (!tdsp_breq && !dma_breq) next_state = `IDLE;
else next_state = `DMA_PRI;
end
`CLEAR: begin
if (tdsp_breq == 1'b1) next_state = `GRANT_TDSP;
else if (dma_breq) next_state = `DMA_PRI;
else next_state = `CLEAR;
end
default: next_state = `IDLE;
endcase
end
// output at clock edge based on next state: Registered output, glitch free
always @(posedge clk or posedge reset) begin
if (reset) begin
dma_grant <= 1'b0;
tdsp_grant <= 1'b0;
end else begin
case (next_state) // based on next state assign the output
`IDLE: begin
dma_grant = 1'b0;
tdsp_grant = 1'b0;
end
`GRANT_TDSP: begin
dma_grant = 1'b0;
tdsp_grant = 1'b1;
end
`GRANT_DMA: begin
dma_grant = 1'b1;
tdsp_grant = 1'b0;
end
`DMA_PRI: begin
dma_grant = 1'b0;
tdsp_grant = 1'b0;
end
`CLEAR: begin
dma_grant = 1'b0;
tdsp_grant = 1'b1;
end
default: begin
dma_grant = 1'b0;
tdsp_grant = 1'b0;
end
endcase
end
end
endmodule
| 8.59133 |
module arb_wavegen #(
parameter OUTPUT_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire enable_pulse, // Acts as a clock divider
input wire [11:0] step, // Acts as a clock multiplier
input wire [11:0] range,
input wire [11:0] wr_addr,
input wire [OUTPUT_WIDTH-1:0] wr_data,
input wire wr_enable,
output wire [OUTPUT_WIDTH-1:0] wave_out
);
reg [15:0] wave_ram [0:2047];
reg [11:0] rd_addr;
reg [15:0] out_value;
assign wave_out = out_value;
// Pseudo-dual port RAM (as in ice40)
// TODO: Implement range checking
always @(posedge clk) begin
if (wr_enable) begin
wave_ram[wr_addr] <= wr_data;
end
if (enable_pulse) begin
rd_addr <= rd_addr + step;
out_value <= wave_ram[rd_addr];
end
if (reset) begin
rd_addr <= 12'b0;
out_value <= {OUTPUT_WIDTH - 1{1'b0}};
end
end
endmodule
| 7.314566 |
module control_rotator (
input [3:0] joystick, //UDLR
input [3:0] keyboard,
input rotate,
input [1:0] orientation,
output [3:0] out
);
assign out = {m_up, m_down, m_left, m_right};
wire m_up = ~(orientation[0] ^ rotate) ? keyboard[3] | joystick[3] : ((orientation[1] ^ orientation[0]) ? keyboard[0] | joystick[0] : keyboard[1] | joystick[1]);
wire m_down = ~(orientation[0] ^ rotate) ? keyboard[2] | joystick[2] : ((orientation[1] ^ orientation[0]) ? keyboard[1] | joystick[1] : keyboard[0] | joystick[0]);
wire m_left = ~(orientation[0] ^ rotate) ? keyboard[1] | joystick[1] : ((orientation[1] ^ orientation[0]) ? keyboard[3] | joystick[3] : keyboard[2] | joystick[2]);
wire m_right = ~(orientation[0] ^ rotate) ? keyboard[0] | joystick[0] : ((orientation[1] ^ orientation[0]) ? keyboard[2] | joystick[2] : keyboard[3] | joystick[3]);
endmodule
| 8.033793 |
module input_toggle (
input clk,
input reset,
input btn,
output reg state
);
reg btn_old;
always @(posedge clk) begin
btn_old <= btn;
if (reset) state <= 0;
else if (~btn_old & btn) state <= ~state;
end
endmodule
| 7.20813 |
module arcade_video #(
parameter WIDTH = 320,
DW = 8,
GAMMA = 1
) (
input clk_video,
input ce_pix,
input [DW-1:0] RGB_in,
input HBlank,
input VBlank,
input HSync,
input VSync,
output CLK_VIDEO,
output CE_PIXEL,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE,
output [1:0] VGA_SL,
input [ 2:0] fx,
input forced_scandoubler,
inout [21:0] gamma_bus
);
assign CLK_VIDEO = clk_video;
wire hs_fix, vs_fix;
sync_fix sync_v (
CLK_VIDEO,
HSync,
hs_fix
);
sync_fix sync_h (
CLK_VIDEO,
VSync,
vs_fix
);
reg [DW-1:0] RGB_fix;
reg CE, HS, VS, HBL, VBL;
always @(posedge CLK_VIDEO) begin
reg old_ce;
old_ce <= ce_pix;
CE <= 0;
if (~old_ce & ce_pix) begin
CE <= 1;
HS <= hs_fix;
if (~HS & hs_fix) VS <= vs_fix;
RGB_fix <= RGB_in;
HBL <= HBlank;
if (HBL & ~HBlank) VBL <= VBlank;
end
end
wire [7:0] R, G, B;
generate
if (DW == 6) begin
assign R = {RGB_fix[5:4], RGB_fix[5:4], RGB_fix[5:4], RGB_fix[5:4]};
assign G = {RGB_fix[3:2], RGB_fix[3:2], RGB_fix[3:2], RGB_fix[3:2]};
assign B = {RGB_fix[1:0], RGB_fix[1:0], RGB_fix[1:0], RGB_fix[1:0]};
end else if (DW == 8) begin
assign R = {RGB_fix[7:5], RGB_fix[7:5], RGB_fix[7:6]};
assign G = {RGB_fix[4:2], RGB_fix[4:2], RGB_fix[4:3]};
assign B = {RGB_fix[1:0], RGB_fix[1:0], RGB_fix[1:0], RGB_fix[1:0]};
end else if (DW == 9) begin
assign R = {RGB_fix[8:6], RGB_fix[8:6], RGB_fix[8:7]};
assign G = {RGB_fix[5:3], RGB_fix[5:3], RGB_fix[5:4]};
assign B = {RGB_fix[2:0], RGB_fix[2:0], RGB_fix[2:1]};
end else if (DW == 12) begin
assign R = {RGB_fix[11:8], RGB_fix[11:8]};
assign G = {RGB_fix[7:4], RGB_fix[7:4]};
assign B = {RGB_fix[3:0], RGB_fix[3:0]};
end else begin // 24
assign R = RGB_fix[23:16];
assign G = RGB_fix[15:8];
assign B = RGB_fix[7:0];
end
endgenerate
assign VGA_SL = sl[1:0];
wire [2:0] sl = fx ? fx - 1'd1 : 3'd0;
wire scandoubler = fx || forced_scandoubler;
video_mixer #(
.LINE_LENGTH(WIDTH + 4),
.HALF_DEPTH(DW != 24),
.GAMMA(GAMMA)
) video_mixer (
.CLK_VIDEO(CLK_VIDEO),
.ce_pix(CE),
.CE_PIXEL(CE_PIXEL),
.scandoubler(scandoubler),
.hq2x(fx == 1),
.gamma_bus(gamma_bus),
.R((DW != 24) ? R[7:4] : R),
.G((DW != 24) ? G[7:4] : G),
.B((DW != 24) ? B[7:4] : B),
.HSync (HS),
.VSync (VS),
.HBlank(HBL),
.VBlank(VBL),
.VGA_R (VGA_R),
.VGA_G (VGA_G),
.VGA_B (VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.VGA_DE(VGA_DE)
);
endmodule
| 6.828318 |
module screen_rotate (
input CLK_VIDEO,
input CE_PIXEL,
input [7:0] VGA_R,
input [7:0] VGA_G,
input [7:0] VGA_B,
input VGA_HS,
input VGA_VS,
input VGA_DE,
input rotate_ccw,
input no_rotate,
input flip,
output video_rotated,
output FB_EN,
output [ 4:0] FB_FORMAT,
output reg [11:0] FB_WIDTH,
output reg [11:0] FB_HEIGHT,
output [31:0] FB_BASE,
output [13:0] FB_STRIDE,
input FB_VBL,
input FB_LL,
output DDRAM_CLK,
input DDRAM_BUSY,
output [ 7:0] DDRAM_BURSTCNT,
output [28:0] DDRAM_ADDR,
output [63:0] DDRAM_DIN,
output [ 7:0] DDRAM_BE,
output DDRAM_WE,
output DDRAM_RD
);
parameter MEM_BASE = 7'b0010010; // buffer at 0x24000000, 3x8MB
reg do_flip;
assign DDRAM_CLK = CLK_VIDEO;
assign DDRAM_BURSTCNT = 1;
assign DDRAM_ADDR = {MEM_BASE, i_fb, ram_addr[22:3]};
assign DDRAM_BE = ram_addr[2] ? 8'hF0 : 8'h0F;
assign DDRAM_DIN = {ram_data, ram_data};
assign DDRAM_WE = ram_wr;
assign DDRAM_RD = 0;
assign FB_EN = fb_en[2];
assign FB_FORMAT = 5'b00110;
assign FB_BASE = {MEM_BASE, o_fb, 23'd0};
assign FB_STRIDE = stride;
function [1:0] buf_next;
input [1:0] a, b;
begin
buf_next = 1;
if ((a == 0 && b == 1) || (a == 1 && b == 0)) buf_next = 2;
if ((a == 1 && b == 2) || (a == 2 && b == 1)) buf_next = 0;
end
endfunction
assign video_rotated = ~no_rotate;
always @(posedge CLK_VIDEO) begin
do_flip <= no_rotate && flip;
if (do_flip) begin
FB_WIDTH <= hsz;
FB_HEIGHT <= vsz;
end else begin
FB_WIDTH <= vsz;
FB_HEIGHT <= hsz;
end
end
reg [1:0] i_fb, o_fb;
always @(posedge CLK_VIDEO) begin
reg old_vbl, old_vs;
old_vbl <= FB_VBL;
old_vs <= VGA_VS;
if (FB_LL) begin
if (~old_vbl & FB_VBL) o_fb <= {1'b0, ~i_fb[0]};
if (~old_vs & VGA_VS) i_fb <= {1'b0, ~i_fb[0]};
end else begin
if (~old_vbl & FB_VBL) o_fb <= buf_next(o_fb, i_fb);
if (~old_vs & VGA_VS) i_fb <= buf_next(i_fb, o_fb);
end
end
initial begin
fb_en = 0;
end
reg [2:0] fb_en = 0;
reg [11:0] hsz = 320, vsz = 240;
reg [11:0] bwidth;
reg [22:0] bufsize;
always @(posedge CLK_VIDEO) begin
reg [11:0] hcnt = 0, vcnt = 0;
reg old_vs, old_de;
if (CE_PIXEL) begin
old_vs <= VGA_VS;
old_de <= VGA_DE;
hcnt <= hcnt + 1'd1;
if (~old_de & VGA_DE) begin
hcnt <= 1;
vcnt <= vcnt + 1'd1;
end
if (old_de & ~VGA_DE) begin
hsz <= hcnt;
if (do_flip) bwidth <= hcnt + 2'd3;
end
if (~old_vs & VGA_VS) begin
vsz <= vcnt;
if (!do_flip) bwidth <= vcnt + 2'd3;
vcnt <= 0;
fb_en <= {fb_en[1:0], ~no_rotate | flip};
end
if (old_vs & ~VGA_VS) bufsize <= (do_flip ? vsz : hsz) * stride;
end
end
wire [13:0] stride = {bwidth[11:2], 4'd0};
reg [22:0] ram_addr, next_addr;
reg [31:0] ram_data;
reg ram_wr;
always @(posedge CLK_VIDEO) begin
reg [13:0] hcnt = 0;
reg old_vs, old_de;
ram_wr <= 0;
if (CE_PIXEL && FB_EN) begin
old_vs <= VGA_VS;
old_de <= VGA_DE;
if (~old_vs & VGA_VS) begin
next_addr <=
do_flip ? bufsize-3'd4 :
rotate_ccw ? (bufsize - stride) : {vsz-1'd1, 2'b00};
hcnt <= rotate_ccw ? 3'd4 : {vsz - 2'd2, 2'b00};
end
if (VGA_DE) begin
ram_wr <= 1;
ram_data <= {8'd0, VGA_B, VGA_G, VGA_R};
ram_addr <= next_addr;
next_addr <=
do_flip ? next_addr-3'd4 :
rotate_ccw ? (next_addr - stride) : (next_addr + stride);
end
if (old_de & ~VGA_DE & ~do_flip) begin
next_addr <= rotate_ccw ? (bufsize - stride + hcnt) : hcnt;
hcnt <= rotate_ccw ? (hcnt + 3'd4) : (hcnt - 3'd4);
end
end
end
endmodule
| 7.258265 |
module arcade_wrapper (
input _2LFT,
input _2S3,
input _2DN,
input _2S2,
input _2UP,
input _2S1,
input _START,
input _2RGT,
input _1LFT,
input _1S3,
input _1DN,
input _1S2,
input _1UP,
input _1S1,
input _START1,
input _1RGT
//input sw[7:0], //select switch for board-level debugging
//output [7:0] Led
);
// Uncomment the line below to debug the JAMMA interface at the board
// level. You should see the 8 LEDs on the Nexys3 board light up and turn
// off upon activating a switch
//assign Led = sw[0] ? {_2LFT, _2S3, _2DN, _2S2, _2UP, _2S1, _START, _2RGT} : {_1LFT, _1S3, _1DN, _1S2, _1UP, _1S1, _START1, _1RGT};
endmodule
| 6.97422 |
module Arch_Map (
input logic en, clock, reset,
input logic [`NUM_SUPER-1:0] retire_en, // retire signal from ROB
`ifndef DEBUG
input ROB_ARCH_MAP_OUT_t ROB_Arch_Map_out
`else
input ROB_ARCH_MAP_OUT_t ROB_Arch_Map_out,
output logic [31:0][$clog2(`NUM_PR)-1:0] next_arch_map,
`endif
output ARCH_MAP_MAP_TABLE_OUT_t ARCH_MAP_MAP_Table_out
);
logic [31:0][$clog2(`NUM_PR)-1:0] arch_map;
`ifndef DEBUG
logic [31:0][$clog2(`NUM_PR)-1:0] next_arch_map;
`endif
assign ARCH_MAP_MAP_Table_out.arch_map = arch_map;
always_comb begin
next_arch_map = arch_map;
for(int i = 0; i < `NUM_SUPER; i++) begin
if (retire_en[i]) begin
next_arch_map[ROB_Arch_Map_out.dest_idx[i]] = ROB_Arch_Map_out.T_idx[i];
end
end
end // always
// synopsys sync_set_reset "reset"
always_ff @(posedge clock) begin
if(reset) begin
arch_map <= `SD `ARCH_MAP_RESET;
end else if(en) begin
arch_map <= `SD next_arch_map;
end // if (en)
end // always
endmodule
| 6.856361 |
modules
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// License: MIT
// Copyright (c) 2021 Dmitry Matyunin
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
//////////////////////////////////////////////////////////////////////////////////
//
// CDC Array
//
module arch_cdc_array #(
parameter FPGA_VENDOR = "xilinx",
parameter FPGA_FAMILY = "7series",
parameter WIDTH = 2
)
(
input wire src_clk,
input wire [WIDTH-1:0]src_data,
input wire dst_clk,
output wire [WIDTH-1:0]dst_data
);
generate if ((FPGA_VENDOR == "xilinx") && (FPGA_FAMILY == "7series")) begin
xpm_cdc_array_single #(
.DEST_SYNC_FF(3),
.INIT_SYNC_FF(0),
.SIM_ASSERT_CHK(0),
.SRC_INPUT_REG(1),
.WIDTH(WIDTH)
) xpm_cdc_array_single_inst (
.dest_out(dst_data),
.dest_clk(dst_clk),
.src_clk(src_clk),
.src_in(src_data)
);
end else begin
initial $error("Unsupported FPGA Vendor or Family!");
end endgenerate
endmodule
| 6.704136 |
module arch_fifo_axis #(
parameter FPGA_VENDOR = "xilinx",
parameter FPGA_FAMILY = "7series",
parameter CLOCK_MODE = "ASYNC",
parameter FIFO_PACKET = 0,
parameter FIFO_DEPTH = 1024,
parameter DATA_WIDTH = 8,
parameter PROG_FULL_THRESHOLD = 64
) (
input wire s_aclk,
input wire s_aresetn,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire [7:0] s_axis_tdata,
input wire s_axis_tlast,
input wire m_aclk,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire [7:0] m_axis_tdata,
output wire m_axis_tlast,
output wire axis_prog_full
);
generate
if ((FPGA_VENDOR == "xilinx") && (FPGA_FAMILY == "7series")) begin
localparam CLOCKING_MODE = (CLOCK_MODE == "ASYNC") ? "independent_clock" : "common_clock";
localparam PACKET_FIFO = (FIFO_PACKET == 0) ? "false" : "true";
localparam USE_ADV_FEATURES = (PROG_FULL_THRESHOLD != 0) ? "1002" : "1000";
xpm_fifo_axis #(
.CDC_SYNC_STAGES(2),
.CLOCKING_MODE(CLOCKING_MODE),
.ECC_MODE("no_ecc"),
.FIFO_DEPTH(FIFO_DEPTH),
.FIFO_MEMORY_TYPE("auto"),
.PACKET_FIFO(PACKET_FIFO),
.PROG_EMPTY_THRESH(10),
.PROG_FULL_THRESH(PROG_FULL_THRESHOLD),
.RD_DATA_COUNT_WIDTH(1),
.RELATED_CLOCKS(0),
.TDATA_WIDTH(DATA_WIDTH),
.TDEST_WIDTH(1),
.TID_WIDTH(1),
.TUSER_WIDTH(1),
.USE_ADV_FEATURES(USE_ADV_FEATURES),
.WR_DATA_COUNT_WIDTH(1)
) xpm_fifo_axis_inst (
.almost_empty_axis(),
.almost_full_axis(),
.dbiterr_axis(),
.m_axis_tdata(m_axis_tdata),
.m_axis_tdest(),
.m_axis_tid(),
.m_axis_tkeep(),
.m_axis_tlast(m_axis_tlast),
.m_axis_tstrb(),
.m_axis_tuser(),
.m_axis_tvalid(m_axis_tvalid),
.prog_empty_axis(),
.prog_full_axis(axis_prog_full),
.rd_data_count_axis(),
.s_axis_tready(s_axis_tready),
.sbiterr_axis(),
.wr_data_count_axis(),
.injectdbiterr_axis(),
.injectsbiterr_axis(),
.m_aclk(m_aclk),
.m_axis_tready(m_axis_tready),
.s_aclk(s_aclk),
.s_aresetn(s_aresetn),
.s_axis_tdata(s_axis_tdata),
.s_axis_tdest(),
.s_axis_tid(),
.s_axis_tkeep(),
.s_axis_tlast(s_axis_tlast),
.s_axis_tstrb(),
.s_axis_tuser(),
.s_axis_tvalid(s_axis_tvalid)
);
end else begin
initial $error("Unsupported FPGA Vendor or Family!");
end
endgenerate
endmodule
| 6.916777 |
module arch_fifo_async #(
parameter FPGA_VENDOR = "xilinx",
parameter FPGA_FAMILY = "7series",
parameter RD_DATA_WIDTH = 8,
parameter WR_DATA_WIDTH = 8
) (
output wire [RD_DATA_WIDTH-1:0] dout,
output wire empty,
output wire full,
output wire rd_rst_busy,
output wire wr_rst_busy,
input wire [WR_DATA_WIDTH-1:0] din,
input wire rd_clk,
input wire rd_en,
input wire rst,
input wire wr_clk,
input wire wr_en
);
generate
if ((FPGA_VENDOR == "xilinx") && (FPGA_FAMILY == "7series")) begin
xpm_fifo_async #(
.CDC_SYNC_STAGES(4),
.DOUT_RESET_VALUE("0"),
.ECC_MODE("no_ecc"),
.FIFO_MEMORY_TYPE("distributed"),
.FIFO_READ_LATENCY(0),
.FIFO_WRITE_DEPTH(16 * 4),
.FULL_RESET_VALUE(0),
.PROG_EMPTY_THRESH(),
.PROG_FULL_THRESH(),
.RD_DATA_COUNT_WIDTH(1),
.READ_DATA_WIDTH(RD_DATA_WIDTH),
.READ_MODE("fwft"),
.RELATED_CLOCKS(0),
.USE_ADV_FEATURES("0000"),
.WAKEUP_TIME(0),
.WRITE_DATA_WIDTH(WR_DATA_WIDTH),
.WR_DATA_COUNT_WIDTH(1)
) xpm_fifo_async_inst (
.almost_empty(),
.almost_full(),
.data_valid(),
.dbiterr(),
.dout(dout),
.empty(empty),
.full(full),
.overflow(),
.prog_empty(),
.prog_full(),
.rd_data_count(),
.rd_rst_busy(rd_rst_busy),
.sbiterr(),
.underflow(),
.wr_ack(),
.wr_data_count(),
.wr_rst_busy(wr_rst_busy),
.din(din),
.injectdbiterr(),
.injectsbiterr(),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.sleep(1'b0),
.wr_clk(wr_clk),
.wr_en(wr_en)
);
end else begin
initial $error("Unsupported FPGA Vendor or Family!");
end
endgenerate
endmodule
| 6.526387 |
module arduino_adc (
adc_ltc2308_conduit_end_CONVST,
adc_ltc2308_conduit_end_SCK,
adc_ltc2308_conduit_end_SDI,
adc_ltc2308_conduit_end_SDO,
clk_clk,
motor_export,
pll_sys_locked_export,
reset_reset_n,
uart_rxd,
uart_txd
);
output adc_ltc2308_conduit_end_CONVST;
output adc_ltc2308_conduit_end_SCK;
output adc_ltc2308_conduit_end_SDI;
input adc_ltc2308_conduit_end_SDO;
input clk_clk;
output [3:0] motor_export;
output pll_sys_locked_export;
input reset_reset_n;
input uart_rxd;
output uart_txd;
endmodule
| 6.595463 |
module arduino_adc_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk) begin
if (fifo_wr) $write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 7.019349 |
module arduino_adc_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear;
input [7:0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
arduino_adc_jtag_uart_sim_scfifo_w the_arduino_adc_jtag_uart_sim_scfifo_w (
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty(wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 7.019349 |
module arduino_adc_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [31:0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7:0] fifo_rdata;
wire new_rom;
wire [31:0] num_bytes;
wire [ 6:0] rfifo_entries;
wire rfifo_full;
wire [ 5:0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n) begin
if (rst_n == 0) begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end else begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d) bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom) bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 7.019349 |
module arduino_adc_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [7:0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [7:0] fifo_rdata;
wire rfifo_full;
wire [5:0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
arduino_adc_jtag_uart_sim_scfifo_r the_arduino_adc_jtag_uart_sim_scfifo_r (
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata(fifo_rdata),
.rfifo_full(rfifo_full),
.rfifo_used(rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 7.019349 |
module arduino_adc_onchip_memory2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "arduino_adc_onchip_memory2.hex";
output [31:0] readdata;
input [15:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input freeze;
input reset;
input reset_req;
input write;
input [31:0] writedata;
wire clocken0;
wire [31:0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clk),
.clocken0(clocken0),
.data_a(writedata),
.q_a(readdata),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram", the_altsyncram.maximum_depth = 40000,
the_altsyncram.numwords_a = 40000, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 16;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 7.108928 |
module arduino_adc_pll_sys (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(2),
.output_clock_frequency0("100.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("40.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst(rst),
.outclk({outclk_1, outclk_0}),
.locked(locked),
.fboutclk(),
.fbclk(1'b0),
.refclk(refclk)
);
endmodule
| 6.506893 |
module arduino_adc_sw (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
);
output irq;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input [3:0] in_port;
input reset_n;
input write_n;
input [31:0] writedata;
wire clk_en;
reg [ 3:0] d1_data_in;
reg [ 3:0] d2_data_in;
wire [ 3:0] data_in;
reg [ 3:0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 3:0] edge_detect;
wire irq;
reg [ 3:0] irq_mask;
wire [ 3:0] read_mux_out;
reg [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 2)}} & irq_mask) |
({4 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2)) irq_mask <= writedata[3 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe) edge_capture[0] <= 0;
else if (edge_detect[0]) edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe) edge_capture[1] <= 0;
else if (edge_detect[1]) edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe) edge_capture[2] <= 0;
else if (edge_detect[2]) edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe) edge_capture[3] <= 0;
else if (edge_detect[3]) edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) begin
d1_data_in <= 0;
d2_data_in <= 0;
end else if (clk_en) begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in ^ d2_data_in;
endmodule
| 7.41614 |
module arduino_adc_sysid_qsys (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1568128486 : 35;
endmodule
| 7.41614 |
module arduino_shield (
input wire UART,
input wire I2C,
input wire SPI,
inout wire [15:0] SH_IO,
output wire I2C_OE
);
wire [15:0] gpio;
wire uart_rx;
wire uart_tx;
wire i2c_scl;
wire i2c_sda;
wire i2c_scl_int;
wire i2c_sda_int;
wire i2c_oe_int;
wire spi_sck;
wire spi_ss;
wire spi_mosi;
wire spi_miso;
wire sh_io_int14;
// Intentionally unused signals
wire unused;
//---------------------UART / GPIO Mux---------------------------------------------
assign SH_IO[0] = UART ? uart_rx : gpio[0];
assign uart_tx = UART ? SH_IO[1] : 1'bz;
//---------------------------------------------------------------------------------
//---------------------I2C / GPIO Mux----------------------------------------------
pullup (i2c_scl); // pullup scl line
pullup (i2c_sda); // pullup sda line
assign i2c_scl_int = I2C ? SH_IO[15] : 1'bz;
assign i2c_scl = i2c_scl_int ? 1'bz : 1'b0;
assign sh_io_int14 = I2C_OE ? i2c_sda : 1'bz; // I2C_SDA <=> SH_IO[14]
assign SH_IO[14] = I2C ? sh_io_int14 : gpio[14];
assign i2c_sda_int = (~SH_IO[14] & ~i2c_oe_int) ? 1'b0 : 1'bz;
assign i2c_sda = I2C ? i2c_sda_int : 1'bz;
assign I2C_OE = I2C ? i2c_oe_int : 1'bz;
I2C_SRAM u_i2c_sram (
.power_cycle(1'b1),
.A0 (1'b0),
.A1 (1'b0),
.A2 (1'b0),
.WP (1'b0),
.SDA (i2c_sda),
.SCL (i2c_scl),
.SDA_OE (i2c_oe_int),
.HSB_bar (),
.INT ()
);
//---------------------------------------------------------------------------------
//---------------------SPI / GPIO Mux----------------------------------------------
assign spi_sck = SPI ? SH_IO[13] : 1'bz;
assign spi_ss = SPI ? SH_IO[10] : 1'bz;
assign spi_mosi = SPI ? SH_IO[11] : 1'bz;
assign SH_IO[12] = SPI ? spi_miso : gpio[12];
assign gpio[13] = SPI ? 1'bz : SH_IO[13];
assign gpio[10] = SPI ? 1'bz : SH_IO[10];
assign SH_IO[11] = SPI ? 1'bz : gpio[11];
SPI_EEPROM u_spi_eeprom (
.SI (spi_mosi),
.SCK (spi_sck),
.CS_N (spi_ss),
.WP_N (1'b1),
.HOLD_N(1'b1),
.RESET (1'b0),
.SO (spi_miso)
);
//---------------------------------------------------------------------------------
assign unused = |{gpio[10], gpio[13], uart_tx};
endmodule
| 6.848058 |
module area_1 (
input pixelclk,
input rst_n,
input en,
input i_binary,
input i_hs,
input i_vs,
input i_de,
//input [23:0] i_rgb_1,
//
//output [23:0] o_rgb_1_6,
output wire hs_r,
output wire vs_r,
output wire de_r,
output wire post_frame_vsync,
output wire post_frame_href,
output wire post_frame_clken,
output wire post_img_Bit
);
assign hs_r = i_hs;
assign vs_r =i_vs;
assign de_r = i_de;
assign post_frame_vsync=i_vs ;
assign post_frame_href =i_hs ;
assign post_frame_clken=i_de ;
assign post_img_Bit =i_binary ;
endmodule
| 7.014839 |
module area_BMR #(
parameter N = 8
) (
input [6*N-1:0] p_input, //A, B, C: 2*N
output o
);
wire signed [N-1:0] xA, yA, xB, yB, xC, yC;
assign xA = p_input[6*N-1:5*N];
assign yA = p_input[5*N-1:4*N];
assign xB = p_input[4*N-1:3*N];
assign yB = p_input[3*N-1:2*N];
assign xC = p_input[2*N-1:1*N];
assign yC = p_input[1*N-1:0*N];
area #(
.N(N)
) A (
.xA (xA),
.yA (yA),
.xB (xB),
.yB (yB),
.xC (xC),
.yC (yC),
.pass(o)
);
endmodule
| 6.953901 |
module area_cnt (
input pixelclk,
input reset_n,
input i_vsync_pos,
input wb,
input [11:0] hcount,
input [11:0] vcount,
input [11:0] hcount_l,
input [11:0] hcount_r,
input [11:0] vcount_l,
input [11:0] vcount_r,
output [11:0] area
);
reg [11:0] area_r;
assign area = area_r;
always @(posedge pixelclk or negedge reset_n) begin
if (!reset_n) area_r <= 12'd0;
else if (i_vsync_pos == 1'b1) area_r <= 12'd0;
else if ((vcount > vcount_l && vcount < vcount_r && hcount > hcount_l && hcount < hcount_r))
if (wb == 1'b0) area_r <= area_r + 1;
else area_r <= area_r;
end
endmodule
| 6.697345 |
module areg (
output reg DALtx,
// The QBUS signals as seen by the FPGA
inout [21:0] DAL, // bidirectional to save FPGA pins
input RDOUT,
output reg TDOUT,
input RRPLY,
output reg TRPLY,
input RDIN,
output reg TDIN,
input RSYNC,
output reg TSYNC,
input RIRQ4,
output reg TIRQ4,
input RIRQ5,
output reg TIRQ5,
input RIRQ6,
output reg TIRQ6,
input RIRQ7,
output reg TIRQ7,
input RWTBT,
output reg TWTBT, // option 1, allow byte write DMA cycles
input RREF, // option for DMA burst mode when acting as memory
output reg TREF, // option for DMA burst mode
input RINIT,
input RDCOK,
input RPOK,
input RBS7,
input RIAKI,
input RDMGI,
output reg TDMR,
output reg TSACK,
output reg TIAKO,
output reg TDMGO
);
parameter addr = 'o777777;
reg [15:0] reg_data = 'o123456; // the actual register
reg [12:0] io_addr = 0;
reg io_page = 0;
wire addr_match = RSYNC && (io_addr == addr) && io_page;
reg drive_DAL; // this is the same as DALtx but it exists only in this
// module, it doesn't leak out
// Drive the DAL lines with the register contents when DALtx, otherwise tri-state
assign DAL = drive_DAL ? {6'b0, reg_data} : 22'bZ;
// Latch the address whenever it comes along
always @(posedge RSYNC) begin
io_page <= RBS7;
io_addr <= DAL[12:0];
end
// Latch the data
always @(posedge RDOUT) if (RSYNC && addr_match) reg_data <= DAL[15:0];
// Look for read and write operations
always @(*) begin
drive_DAL <= 0;
DALtx <= 0;
TDOUT <= 0;
TRPLY <= 0;
TDIN <= 0;
TSYNC <= 0;
TIRQ4 <= 0;
TIRQ5 <= 0;
TIRQ6 <= 0;
TIRQ7 <= 0;
TWTBT <= 0;
TREF <= 0;
TDMR <= 0;
TSACK <= 0;
TIAKO <= 0;
TDMGO <= 0;
if (addr_match) begin
if (RDIN) begin
DALtx <= 1;
drive_DAL <= 1;
TRPLY <= 1;
end else if (RDOUT) begin
TRPLY <= 1;
end
end
end
endmodule
| 6.809406 |
module aregc01_3v3 ( OUT, VIN3, GNDO, EN, GNDR, VDDO, VDDR, VDD, ENB );
input VDD;
input VDDO;
input GNDO;
input VDDR;
input GNDR;
input EN;
output OUT;
input ENB;
input VIN3;
wire real VDDR;
reg real OUT;
wire EN;
real NaN;
initial begin
NaN = 0.0 / 0.0;
OUT <= 0.0;
end
always @(VDDR or EN) begin
if (EN == 1'b1) begin
if (VDDR > 1.8) begin
OUT <= 1.8;
end else begin
OUT <= VDDR;
end
end else if (EN == 1'b0) begin
OUT <= 0.0;
end else begin
OUT <= NaN;
end
end
endmodule
| 6.547788 |
module aReg (
clk,
alu_dataOut_1,
aReg_out
);
input clk;
input [31:0] alu_dataOut_1;
output reg [31:0] aReg_out;
always @(posedge clk) begin
aReg_out <= alu_dataOut_1;
end
endmodule
| 6.864059 |
module select_vector (
input wire [`SPECTAG_LEN-1:0] spectag,
input wire [ `REG_NUM-1:0] dat0,
input wire [ `REG_NUM-1:0] dat1,
input wire [ `REG_NUM-1:0] dat2,
input wire [ `REG_NUM-1:0] dat3,
input wire [ `REG_NUM-1:0] dat4,
output reg [ `REG_NUM-1:0] out
);
always @(*) begin
out = 0;
case (spectag)
5'b00001: out = dat1;
5'b00010: out = dat2;
5'b00100: out = dat3;
5'b01000: out = dat4;
5'b10000: out = dat0;
default: out = 0;
endcase // case (spectag)
end
endmodule
| 6.539981 |
module argmax_cell #(
parameter DATA_WIDTH = 8,
parameter RESULT_WIDTH = 16,
parameter INDEX_WIDTH = 10,
parameter CELL_AMOUNT = 4
) (
input wire clk,
input wire [INDEX_WIDTH-1:0] input_index,
input wire [DATA_WIDTH-1:0] input_value,
input wire input_enable,
output reg [RESULT_WIDTH:0] output_result
);
reg [DATA_WIDTH-1:0] best_value;
reg [DATA_WIDTH-1:0] best_index;
initial begin
best_value = 0;
best_index = 0;
end
always @(posedge clk) begin
#1
if (input_enable)
if (input_index == CELL_AMOUNT - 1) begin
output_result[RESULT_WIDTH] = 1'b1;
if (best_value <= input_value) output_result[RESULT_WIDTH-1:0] <= input_index;
else output_result[RESULT_WIDTH-1:0] <= best_index;
best_value <= 0;
best_index <= 0;
end else begin
output_result[RESULT_WIDTH] <= 1'b0;
if (input_index == 0 || best_value <= input_value) begin
best_value <= input_value;
best_index <= input_index;
end
end
else output_result <= 0;
end
endmodule
| 6.610927 |
module.
//////////////////////////////////////////////////////////////////////////////////
module argmax_simulator();
event error;
always @ (error) begin
$display("ERROR at time %t", $time);
#`CLOCK $stop;
end
task check_output(input [`DATA_WIDTH*2:0] result, input [`DATA_WIDTH*2:0] golden);
begin
if (result!==golden) begin
$display("Output is %0d which should be %0d instead!", result[`DATA_WIDTH*2-1:0], golden[`DATA_WIDTH*2-1:0]);
->error;
end
end
endtask
reg clk;
reg [`DATA_WIDTH+1:0] input_index;
reg [`DATA_WIDTH-1:0] input_value;
reg input_enable;
wire [`DATA_WIDTH*2:0] output_result;
argmax_cell #(
.DATA_WIDTH(`DATA_WIDTH),
.RESULT_WIDTH(`DATA_WIDTH*2),
.INDEX_WIDTH(`DATA_WIDTH+2),
.CELL_AMOUNT(2)
) uut (
.clk(clk),
.input_index(input_index),
.input_value(input_value),
.input_enable(input_enable),
.output_result(output_result)
);
initial begin
clk = 1;
forever #(`CLOCK/2) clk = !clk;
end
initial begin
input_index = 0;
input_value = 0;
input_enable = 0;
end
initial begin
#2;
#(`CLOCK*2);
input_value = 1;
#`CLOCK;
input_value = 0;
input_index = 1;
#`CLOCK;
check_output(output_result, 0);
input_index = 0;
input_value = 2;
input_enable = 1;
#`CLOCK;
check_output(output_result, 0);
input_index = 1;
input_value = 1;
input_enable = 1;
#`CLOCK;
check_output(output_result, {1'b1, 16'd0});
input_index = 0;
input_value = 3;
input_enable = 1;
#`CLOCK;
check_output(output_result, 0);
input_index = 1;
input_value = 6;
input_enable = 0;
#`CLOCK;
check_output(output_result, 0);
#`CLOCK;
$display("SUCCESSFUL TEST!");
$stop;
end
endmodule
| 6.641851 |
module returns a one hot vector where the high bit corresponds to
the location of the minimum number in the input vector
Note that there is only clk, reset, and enable for control signals.
This module is to be used in parallel with pipeline train.
This module always takes ceil(log2(BLOCKLENGTH)) time steps.
This is relied on in other modules and is what allows the simpler input/output contract.
No input registering.
The functioning of the module is pretty simple.
Each implementation kind of mimics a recursive implementation.
Basically, its a min tree.
At the first layer we just compare values beside eachother.
The output of that layer is a vector half the size with the minimum values.
Also, a BLOCKLENGTH length vector is passed on indicating which positions the mins came from.
The next layer than cuts the vector of mins in half again and turns off relevant bits in the indicator vector.
This is done until the indicator vector is one-hot.
The one-hot vector is the output.
*/
`include "2dArrayMacros.v"
module ArgMin #
(
parameter BLOCKLENGTH = 1,
parameter DATA_WIDTH = 8
)
(
input clk,
input reset,
input enable,
input [DATA_WIDTH*BLOCKLENGTH-1:0] data_in,
output [0:BLOCKLENGTH-1] arg
);
//instantiate different circuits depending on blocklength
//There might be a nice recursive declaration of this module
//but I was having trouble guaranteeing the pipeline depth
//when the two recursive calls would have different depths.
generate
if( 1 == BLOCKLENGTH ) begin
assign arg[0] = 1'b1;
end else if( 2 == BLOCKLENGTH) begin
am2 #( .BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) amin(clk, reset, enable, data_in, arg);
end else if( 3 == BLOCKLENGTH) begin
am3 #( .BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) amin(clk, reset, enable, data_in, arg);
end else if( 4 == BLOCKLENGTH) begin
am4 #( .BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) amin(clk, reset, enable, data_in, arg);
end else if( 5 == BLOCKLENGTH) begin
am5 #( .BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) amin(clk, reset, enable, data_in, arg);
end else if( 6 == BLOCKLENGTH) begin
am6 #( .BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) amin(clk, reset, enable, data_in, arg);
end else if( 7 == BLOCKLENGTH) begin
am7 #( .BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) amin(clk, reset, enable, data_in, arg);
end else if( 8 == BLOCKLENGTH) begin
am8 #( .BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) amin(clk, reset, enable, data_in, arg);
end else if( 14 == BLOCKLENGTH) begin
am14 #( .BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) amin(clk, reset, enable, data_in, arg);
end else if( 15 == BLOCKLENGTH) begin
am15 #( .BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) amin(clk, reset, enable, data_in, arg);
end else if( 16 == BLOCKLENGTH) begin
am16 #( .BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) amin(clk, reset, enable, data_in, arg);
end
endgenerate
endmodule
| 7.878483 |
module am2 #(
parameter BLOCKLENGTH = 2,
parameter DATA_WIDTH = 8
) (
input clk,
input reset,
input enable,
input [DATA_WIDTH*BLOCKLENGTH-1:0] data_in,
output [0:BLOCKLENGTH-1] arg
);
wire [DATA_WIDTH-1:0] in[0:BLOCKLENGTH-1];
`UNPACK_ARRAY(DATA_WIDTH, BLOCKLENGTH, in, data_in)
reg [0:BLOCKLENGTH-1] out;
wire leq;
assign leq = in[0] <= in[1];
always @(posedge clk, posedge reset) begin
if (1'b1 == reset) begin
out <= 0;
end else if (1'b1 == enable) begin
out[0] <= leq;
out[1] <= ~leq;
end
end
assign arg = out;
endmodule
| 6.990385 |
module am3 #(
parameter BLOCKLENGTH = 3,
parameter DATA_WIDTH = 8
) (
input clk,
input reset,
input enable,
input [DATA_WIDTH*BLOCKLENGTH-1:0] data_in,
output [0:BLOCKLENGTH-1] arg
);
wire [DATA_WIDTH-1:0] in[0:BLOCKLENGTH-1];
`UNPACK_ARRAY(DATA_WIDTH, BLOCKLENGTH, in, data_in)
//first layer of comparison
reg [0:BLOCKLENGTH-1] arg1;
reg [DATA_WIDTH-1:0] min1[0:1];
wire leq1;
assign leq1 = in[0] <= in[1];
always @(posedge clk, posedge reset) begin
if (1'b1 == reset) begin
min1[0] <= 0;
min1[1] <= 0;
arg1 <= 0;
end else if (1'b1 == enable) begin
arg1[0] <= leq1;
arg1[1] <= ~leq1;
arg1[2] <= 1'b1;
min1[0] <= leq1 ? in[0] : in[1];
min1[1] <= in[2];
end
end
//second layer of comparison
reg [0:BLOCKLENGTH-1] arg2;
wire leq2;
assign leq2 = min1[0] <= min1[1];
always @(posedge clk, posedge reset) begin
if (1'b1 == reset) begin
arg2 <= 0;
end else if (1'b1 == enable) begin
//mask off the arg vectors from previous clock cycle
arg2[0] <= arg1[0] & leq2;
arg2[1] <= arg1[1] & leq2;
arg2[2] <= arg1[2] & ~leq2;
end
end
//assign output
assign arg = arg2;
endmodule
| 6.762173 |
module am4 #(
parameter BLOCKLENGTH = 4,
parameter DATA_WIDTH = 8
) (
input clk,
input reset,
input enable,
input [DATA_WIDTH*BLOCKLENGTH-1:0] data_in,
output [0:BLOCKLENGTH-1] arg
);
wire [DATA_WIDTH-1:0] in[0:BLOCKLENGTH-1];
`UNPACK_ARRAY(DATA_WIDTH, BLOCKLENGTH, in, data_in)
//first layer of comparison
reg [0:BLOCKLENGTH-1] arg1;
reg [DATA_WIDTH-1:0] min1[0:1];
wire [0:1] leq1;
assign leq1[0] = in[0] <= in[1];
assign leq1[1] = in[2] <= in[3];
always @(posedge clk, posedge reset) begin
if (1'b1 == reset) begin
min1[0] <= 0;
min1[1] <= 0;
arg1 <= 0;
end else if (1'b1 == enable) begin
arg1[0] <= leq1[0];
arg1[1] <= ~leq1[0];
arg1[2] <= leq1[1];
arg1[3] <= ~leq1[1];
min1[0] <= leq1[0] ? in[0] : in[1];
min1[1] <= leq1[1] ? in[2] : in[3];
end
end
//second layer of comparison
reg [0:BLOCKLENGTH-1] arg2;
wire leq2;
assign leq2 = min1[0] <= min1[1];
always @(posedge clk, posedge reset) begin
if (1'b1 == reset) begin
arg2 <= 0;
end else if (1'b1 == enable) begin
//mask off the arg vectors from previous clock cycle
arg2[0] <= arg1[0] & leq2;
arg2[1] <= arg1[1] & leq2;
arg2[2] <= arg1[2] & ~leq2;
arg2[3] <= arg1[3] & ~leq2;
end
end
//assign output
assign arg = arg2;
endmodule
| 6.918724 |
module argmin_helper #(
parameter WIDTH = 1,
parameter ADDR_WIDTH = 1,
parameter NUM_INP = 2,
parameter NUM_OUTP = 1,
parameter STAGE = 1
) (
input wire clk,
input wire rst,
input wire [WIDTH*NUM_INP-1:0] inp,
input wire [ADDR_WIDTH*NUM_INP-1:0] inp_addr,
output wire [WIDTH*NUM_OUTP-1:0] outp,
output wire [ADDR_WIDTH*NUM_OUTP-1:0] outp_addr
);
localparam INP_WIDTH = WIDTH * NUM_INP;
localparam INP_A_WIDTH = ADDR_WIDTH * NUM_INP;
// Unpack the input words
wire [WIDTH-1:0] inp_word[NUM_INP];
wire [ADDR_WIDTH-1:0] inp_addr_word[NUM_INP];
genvar i;
generate
for (i = 0; i < NUM_INP; i++) begin
assign inp_word[i] = inp[(INP_WIDTH-WIDTH*i-1):(INP_WIDTH-WIDTH*(i+1))];
assign inp_addr_word[i] = inp_addr[(INP_A_WIDTH-ADDR_WIDTH*i-1):
(INP_A_WIDTH-ADDR_WIDTH*(i+1))];
end
endgenerate
localparam OUTP_WIDTH = WIDTH * NUM_OUTP;
localparam OUTP_A_WIDTH = ADDR_WIDTH * NUM_OUTP;
// Pack the output words
wire [WIDTH-1:0] outp_word[NUM_OUTP];
wire [ADDR_WIDTH-1:0] outp_addr_word[NUM_OUTP];
genvar j;
generate
for (j = 0; j < NUM_OUTP; j++) begin
assign outp[(OUTP_WIDTH-WIDTH*j-1):(OUTP_WIDTH-WIDTH*(j+1))] = outp_word[j];
assign outp_addr[(OUTP_A_WIDTH-ADDR_WIDTH*j-1):
(OUTP_A_WIDTH-ADDR_WIDTH*(j+1))] = outp_addr_word[j];
end
endgenerate
// Create the different argmin stages.
genvar k;
generate
for (k = 0; k < NUM_INP; k += 2) begin : node
if (k + 2 > NUM_INP) begin
// This will be satisfied iff NUM_INP is odd, and we are at the end of the
// list. If that's the case, generate pass-through flip-flops instead of
// the argmin stage.
dff #(
.WIDTH(WIDTH)
) val (
clk,
rst,
inp_word[k],
outp_word[k/2]
);
dff #(
.WIDTH(ADDR_WIDTH)
) addr (
clk,
rst,
inp_addr_word[k],
outp_addr_word[k/2]
);
end else begin
// Otherwise, generate an argmin_stage that reduces two inputs to a single
// output.
argmin_stage #(
.WIDTH(WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.STAGE(STAGE)
) as (
clk,
rst,
inp_word[k],
inp_addr_word[k],
inp_word[k+1],
inp_addr_word[k+1],
outp_word[k/2],
outp_addr_word[k/2]
);
end
end
endgenerate
endmodule
| 8.658206 |
module argmin_stage #(
parameter WIDTH = 1,
parameter ADDR_WIDTH = 1,
parameter STAGE = 1
) (
input wire clk,
input wire rst,
input wire [WIDTH-1:0] left_val,
// One bit of the address input will go unused
/* verilator lint_off UNUSED */
input wire [ADDR_WIDTH-1:0] left_addr,
/* verilator lint_on UNUSED */
input wire [WIDTH-1:0] right_val,
/* verilator lint_off UNUSED */
input wire [ADDR_WIDTH-1:0] right_addr,
/* verilator lint_on UNUSED */
output wire [WIDTH-1:0] outp,
output wire [ADDR_WIDTH-1:0] outp_addr
);
wire left_lte;
wire [WIDTH-1:0] outp_next;
wire [ADDR_WIDTH-1:0] outp_addr_next;
dff #(
.WIDTH(WIDTH)
) out_ff (
clk,
rst,
outp_next,
outp
);
dff #(
.WIDTH(ADDR_WIDTH)
) out_addr_ff (
clk,
rst,
outp_addr_next,
outp_addr
);
assign left_lte = left_val <= right_val;
assign outp_next = left_lte ? left_val : right_val;
genvar i;
generate
for (i = 0; i < ADDR_WIDTH; i++) begin
if (i == STAGE) begin
assign outp_addr_next[i] = !left_lte;
end else begin
assign outp_addr_next[i] = left_lte ? left_addr[i] : right_addr[i];
end
end
endgenerate
endmodule
| 8.183015 |
module argmin_test (
input clk,
input rst,
input wire [10*32-1:0] inp,
output wire [31:0] outp,
output wire [3:0] outp_addr
);
argmin_10 #(
.WIDTH(32)
) am (
clk,
rst,
inp,
outp,
outp_addr
);
endmodule
| 6.698899 |
module argmax_tb();
reg clk;
reg signed [{{i_bits - 1}}:0] xi;
reg signed [{{q_bits - 1}}:0] xq;
integer arg_max_input;
reg m_axis_tvalid;
wire s_axis_tready;
reg m_axis_tready;
wire [{{ out_max_bits - 1}}:0] out_max;
wire [{{ index_bits }}:0] index;
wire s_axis_tvalid;
initial begin
clk = 1'b0;
m_axis_tready = 1'b1;
m_axis_tvalid = 1'b0;
arg_max_input = $fopen("{{ arg_max_input }}", "r");
if (arg_max_input == `NULL) begin
$display("arg_max_input handle was NULL");
$finish;
end
@(posedge s_axis_tvalid);
@(posedge clk) begin
m_axis_tready = 1'b0;
end // UNMATCHED !!
@(posedge clk);
@(posedge clk);
$finish;
end
always begin
#10 clk = ~clk;
end
{% include "arg_max_inst.v" %}
always @(posedge clk) begin
$fscanf(arg_max_input, "%d,%d\n", xi, xq);
m_axis_tvalid = 1'b1;
if ($feof(arg_max_input)) begin
m_axis_tvalid = 1'b0;
end
end
endmodule
| 6.614633 |
module fifo_v2_DEPTH8 (
clk_i,
rst_ni,
flush_i,
testmode_i,
full_o,
empty_o,
alm_full_o,
alm_empty_o,
data_i,
push_i,
data_o,
pop_i
);
input [166:0] data_i;
output [166:0] data_o;
input clk_i;
input rst_ni;
input flush_i;
input testmode_i;
input push_i;
input pop_i;
output full_o;
output empty_o;
output alm_full_o;
output alm_empty_o;
wire [166:0] data_o;
wire full_o, empty_o, alm_full_o, alm_empty_o, N0;
wire [2:0] usage;
assign alm_empty_o = usage <= 1'b1;
fifo_v3_0_00000020_00000008 i_fifo_v3 (
.clk_i(clk_i),
.rst_ni(rst_ni),
.flush_i(flush_i),
.testmode_i(testmode_i),
.full_o(full_o),
.empty_o(empty_o),
.usage_o(usage),
.data_i(data_i),
.push_i(push_i),
.data_o(data_o),
.pop_i(pop_i)
);
assign alm_full_o = N0 | usage[0];
assign N0 = usage[2] | usage[1];
endmodule
| 7.120907 |
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