code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Add_full_116 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_232 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_231 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X2 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX1 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 6.958658 |
module Add_full_117 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_234 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_233 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX2 U1 (
.A(w3),
.Z(n2)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
CND2X2 U3 (
.A(n2),
.B(n1),
.Z(c_out)
);
endmodule
| 7.399211 |
module Add_full_118 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_236 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_235 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX2 U1 (
.A(w3),
.Z(n2)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
CND2X2 U3 (
.A(n2),
.B(n1),
.Z(c_out)
);
endmodule
| 7.194705 |
module Add_full_119 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_238 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_237 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.137518 |
module Add_full_120 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_240 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_239 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.64962 |
module Add_full_121 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_242 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_241 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.438156 |
module Add_full_122 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_244 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_243 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.529526 |
module Add_full_123 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_246 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_245 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.274231 |
module Add_full_124 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_248 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_247 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 8.177129 |
module Add_full_125 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_250 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_249 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.528671 |
module Add_full_126 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_252 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_251 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.616958 |
module Add_full_127 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_254 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_253 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.651848 |
module Add_full_128 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_256 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_255 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 8.090451 |
module Add_full_129 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_258 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_257 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.265673 |
module Add_full_130 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_260 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_259 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.314594 |
module Add_full_131 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_262 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_261 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.128257 |
module Add_full_132 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_264 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_263 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.36681 |
module Add_full_133 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_266 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_265 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.117053 |
module Add_full_134 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_268 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_267 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.399883 |
module Add_full_135 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_270 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_269 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.378352 |
module Add_full_136 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_272 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_271 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CNR2X1 U1 (
.A(w3),
.B(w2),
.Z(n1)
);
CIVXL U2 (
.A(n1),
.Z(c_out)
);
endmodule
| 7.472425 |
module Add_full_137 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_274 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_273 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.443198 |
module Add_full_138 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_276 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_275 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.147347 |
module Add_full_139 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_278 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_277 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.083309 |
module Add_full_140 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_280 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_279 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X2 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.429093 |
module Add_full_141 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_282 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_281 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.296295 |
module Add_full_142 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_284 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_283 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.3382 |
module Add_full_143 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_286 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_285 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.079757 |
module Add_full_144 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_288 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_287 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 8.088049 |
module Add_full_145 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_290 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_289 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.521083 |
module Add_full_146 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_292 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_291 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.424887 |
module Add_full_147 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_294 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_293 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CNR2X1 U1 (
.A(w3),
.B(w2),
.Z(n1)
);
CIVXL U2 (
.A(n1),
.Z(c_out)
);
endmodule
| 7.541129 |
module Add_full_148 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_296 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_295 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.937416 |
module Add_full_149 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_298 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_297 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.475361 |
module Add_full_150 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_300 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_299 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
endmodule
| 7.350708 |
module Add_full_151 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_302 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_301 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.384741 |
module Add_full_152 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_304 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_303 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CNR2X1 U1 (
.A(w3),
.B(w2),
.Z(n1)
);
CIVXL U2 (
.A(n1),
.Z(c_out)
);
endmodule
| 7.929491 |
module Add_full_153 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_306 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_305 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.26956 |
module Add_full_154 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_308 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_307 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.609777 |
module Add_full_155 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_310 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_309 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.898728 |
module Add_full_156 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_312 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_311 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.859966 |
module Add_full_157 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_314 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_313 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.667532 |
module Add_full_158 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_316 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_315 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.702666 |
module Add_full_159 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_318 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_317 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.313746 |
module Add_full_160 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_320 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_319 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.763915 |
module Add_full_161 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_322 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_321 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.422227 |
module Add_full_162 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_324 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_323 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.536228 |
module Add_full_163 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_326 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_325 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX1 U1 (
.A(w3),
.Z(n2)
);
CND2X1 U2 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.209208 |
module Add_full_164 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_328 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_327 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.838165 |
module Add_full_165 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_330 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_329 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.728889 |
module Add_full_166 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_332 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_331 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.459843 |
module Add_full_167 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_334 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_333 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.899759 |
module Add_full_168 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_336 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_335 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.572476 |
module Add_full_169 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_338 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_337 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.481078 |
module Add_full_170 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_340 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_339 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.431352 |
module Add_full_171 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_342 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_341 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.48979 |
module Add_full_172 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_344 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_343 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.496899 |
module Add_full_173 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_346 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_345 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.50908 |
module Add_full_174 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_348 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_347 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 8.061177 |
module Add_full_175 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_350 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_349 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X2 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.559948 |
module Add_full_176 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_352 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_351 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X2 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.575032 |
module Add_full_177 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_354 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_353 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.548047 |
module Add_full_178 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_356 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_355 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.563947 |
module Add_full_179 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_358 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_357 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.442043 |
module Add_full_180 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_360 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_359 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.661626 |
module Add_full_181 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_362 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_361 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.200891 |
module Add_full_182 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_364 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_363 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.352912 |
module Add_full_183 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_366 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_365 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X2 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.547288 |
module Add_full_184 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_368 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_367 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X2 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.858248 |
module Add_full_185 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_370 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_369 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.595972 |
module Add_full_186 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_372 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_371 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.845959 |
module Add_full_187 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_374 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_373 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X2 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX1 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.835958 |
module Add_full_188 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_376 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_375 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX1 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.595987 |
module Add_full_189 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_378 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_377 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.783108 |
module Add_full_190 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_380 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_379 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.934214 |
module Add_full_191 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_382 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_381 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X2 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.655399 |
module Add_full_192 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_384 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_383 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X2 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.699036 |
module Add_full_193 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_386 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_385 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.625956 |
module Add_full_194 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_388 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_387 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.809436 |
module Add_full_195 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_390 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_389 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX2 U1 (
.A(w3),
.Z(n2)
);
CND2X1 U2 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.864535 |
module Add_full_196 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_392 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_391 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX2 U1 (
.A(w3),
.Z(n2)
);
CND2X1 U2 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.962438 |
module Add_full_197 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_394 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_393 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.686572 |
module Add_full_198 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_396 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_395 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.44333 |
module Add_full_199 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_398 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_397 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.771962 |
module Add_full_200 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_400 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_399 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X2 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.558101 |
module Add_full_201 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_402 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_401 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX2 U1 (
.A(w3),
.Z(n2)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
CND2X2 U3 (
.A(n2),
.B(n1),
.Z(c_out)
);
endmodule
| 7.701044 |
module Add_full_202 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_404 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_403 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX2 U1 (
.A(w3),
.Z(n2)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
CND2X2 U3 (
.A(n2),
.B(n1),
.Z(c_out)
);
endmodule
| 7.90518 |
module Add_full_203 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_406 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_405 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.56697 |
module Add_full_204 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_408 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_407 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 8.087496 |
module Add_full_205 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_410 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_409 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX2 U1 (
.A(w3),
.Z(n2)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
CND2X2 U3 (
.A(n2),
.B(n1),
.Z(c_out)
);
endmodule
| 7.426992 |
module Add_full_206 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_412 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_411 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX2 U1 (
.A(w3),
.Z(n2)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
CND2X2 U3 (
.A(n2),
.B(n1),
.Z(c_out)
);
endmodule
| 7.90542 |
module Add_full_207 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_414 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_413 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.755393 |
module Add_full_208 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_416 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_415 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2X1 U1 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w3),
.Z(n2)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.724563 |
module Add_full_209 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_418 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_417 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CNR2X1 U1 (
.A(w3),
.B(w2),
.Z(n1)
);
CIVX2 U2 (
.A(n1),
.Z(c_out)
);
endmodule
| 7.422798 |
module Add_full_210 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_420 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_419 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.367978 |
module Add_full_211 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_422 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_421 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.387143 |
module Add_full_212 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1;
Add_half_424 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_423 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CND2IX1 U1 (
.B(w3),
.A(n1),
.Z(c_out)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
endmodule
| 7.784916 |
module Add_full_213 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_426 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_425 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX1 U1 (
.A(w3),
.Z(n2)
);
CIVX2 U2 (
.A(w2),
.Z(n1)
);
CND2X2 U3 (
.A(n2),
.B(n1),
.Z(c_out)
);
endmodule
| 7.430061 |
module Add_full_214 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half_428 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_427 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
COR2X1 U1 (
.A(w3),
.B(w2),
.Z(c_out)
);
endmodule
| 7.865573 |
module Add_full_215 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3, n1, n2;
Add_half_430 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_429 M2 (
.sum(sum),
.c_out(w3),
.a(w1),
.b(c_in)
);
CIVX1 U1 (
.A(w3),
.Z(n2)
);
CND2X1 U2 (
.A(n2),
.B(n1),
.Z(c_out)
);
CIVX2 U3 (
.A(w2),
.Z(n1)
);
endmodule
| 7.466378 |
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