code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_delays;
reg clk;
reg rst;
reg d;
initial begin // <- Initial construct are evaluated at t = 0.
// Here, t = 0.
clk = 1'b0;
rst = 1'b1;
d = 1'b0;
#3;
// Here, t = 3;
rst = 1'b0;
#2;
// Here, t = 5.
d = 1'b1;
#2;
// Here, t = 7.
d = 1'b0;
... | 6.522164 |
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output done
); //
parameter BYTE1 = 0, BYTE2 = 1, BYTE3 = 2, DONE = 3;
reg [1:0] cstate, nstate;
always @(posedge clk) begin
if (reset) begin
cstate <= BYTE1;
end else begin
cstate <= nstate;
... | 7.203305 |
module top_module (
input clk,
input [7:0] in,
output [7:0] anyedge
);
reg [7:0] intermediate;
always @(posedge clk) begin
intermediate <= in;
anyedge <= intermediate ^ in;
end
endmodule
| 7.203305 |
module top_module (
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different
);
assign out_both = in[2:0] & in[3:1]; //here bits of input vector is shifted right
//and bitwise and is performed to obtain the required output
assign out_any = in[3:1] | in... | 7.203305 |
module approx_fa (
output sum,
cout,
input x,
y,
cin
);
wire s1, c1, c2;
or o1 (s1, x, y);
xor x1 (sum, s1, cin);
and a1 (cout, s1, cin);
endmodule
| 7.10387 |
module XOR4 (
output f,
input a,
input b,
input c,
input d,
input e
);
assign f = a ^ b ^ c ^ d ^ e; // ^ is the XOR operator
endmodule
| 7.338253 |
module ksa4 (
input [2:0] a,
input [2:0] s,
input cin,
output [3:0] B,
output carryout
);
wire [3:0] p, g, cp, cg, ccg, ccp, c;
//initial processing
assign p = a ^ s;
assign g = a & s;
//production of carry
assign cg[0] = (g[0]);
assign cp[0] = (p[0]);
assign cg[1] = (p[1] & g[0]) ... | 7.621387 |
module top_module (
input clk,
input [7:0] in,
output [7:0] anyedge
);
reg [7:0] q;
always @(posedge clk) begin
q <= in;
anyedge <= q ^ in;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output [23:0] out_bytes,
output done
); //
// FSM from fsm_ps2
parameter A = 0, B = 1, C = 2, D = 3;
reg [1:0] state, nextstate;
reg [23:0] data;
// State transition logic (combinational)
always @(*) begi... | 7.203305 |
module top_module (
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different
);
assign out_both = {in[2] & in[3], in[1] & in[2], in[0] & in[1]};
assign out_any = {in[3] | in[2], in[2] | in[1], in[1] | in[0]};
assign out_different = {in[3] ^ in[0], in[2] ^ in[3], in... | 7.203305 |
module top_module (
input [4:0] a,
b,
c,
d,
e,
f,
output [7:0] w,
x,
y,
z
); //
// assign { ... } = { ... };
assign {w, x, y, z} = {a, b, c, d, e, f, 2'b11};
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
output out
); //
wire out_tmp;
assign out = ~out_tmp;
andgate inst1 (
out_tmp,
a,
b,
c,
1,
1
);
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
output out
); //
// andgate inst1 ( a, b, c, out );
wire and_out;
andgate inst1 (
.out(and_out),
.a (a),
.b (b),
.c (c),
.d (1'b1),
.e (1'b1)
);
assign out = ~and_out;
endmodule
| 7.203305 |
module top_module (
input [1:0] sel,
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output [7:0] out
); //
wire [7:0] mux0;
wire [7:0] mux1;
mux2 u_mux2_1 (
sel[0],
a,
b,
mux0
);
mux2 u_mux2_2 (
sel[0],
c,
d,
mux1
)... | 7.203305 |
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output [7:0] out
);
assign out = sel ? a : b;
endmodule
| 7.203305 |
module top_module (
input [1:0] sel,
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output [7:0] out
); //
// wire mux0, mux1;
// mux2 mux0 ( sel[0], a, b, mux0 );
// mux2 mux1 ( sel[1], c, d, mux1 );
// mux2 mux2 ( sel[1], mux0, mux1, out );
wire [7:0... | 7.203305 |
module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
); //
always @(*) begin
case (do_sub)
0: out = a + b;
1: out = a - b;
endcase
if (out == 0) result_is_zero = 1;
else result_is_zero = 0;
end
endmodule
| 7.203305 |
module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
); //
always @(*) begin
case (do_sub)
0: out = a + b;
1: out = a - b;
endcase
result_is_zero = ~(|out);
end
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
output out
); //
wire out_temp;
andgate inst1 (
.out(out_temp),
.a (a),
.b (b),
.c (c),
.d (1'b1),
.e (1'b1)
);
assign out = ~out_temp;
endmodule
| 7.203305 |
module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid
); //
always @(*) begin
out = 0;
valid = 1;
case (code)
8'h45: out = 0;
8'h16: out = 1;
8'h1e: out = 2;
8'h26: out = 3;
8'h25: out = 4;
8'h2e: out = 5;
8'h36: ... | 7.203305 |
module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid
); //
always @(*)
case (code)
8'h45: begin
out = 0;
valid = 1;
end
8'h16: begin
out = 1;
valid = 1;
end
8'h1e: begin
out = 2;
valid = 1;
... | 7.203305 |
module top_module (
input [1:0] sel,
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output [7:0] out
); //
wire [7:0] mux_out_0;
wire [7:0] mux_out_1;
mux2 mux0 (
sel[1],
a,
c,
mux_out_0
);
mux2 mux1 (
sel[1],
b,
d,
mu... | 7.203305 |
module top_module (
input a,
input b,
output q
); //
assign q = a & b;
endmodule
| 7.203305 |
module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
); //
always @(*) begin
case (do_sub)
1'b0: out = a + b;
1'b1: out = a - b;
endcase
if (out == 8'b0000_0000) result_is_zero = 1'b1;
else result_is_zero = 1... | 7.203305 |
module top_module (
input a,
input b,
output q
); //
assign q = a & b;
endmodule
| 7.203305 |
module razhas_top_level (
input [7:0] io_in,
output [7:0] io_out
);
wire w_clk = io_in[0];
wire w_rst = io_in[1];
wire [3:0] w_duty = io_in[5:2]; // selects pwm signal duty cycle: 0% to 100% in increments of 10%. Values of 11-15 treated as 100%.
wire [1:0] w_freq = io_in[7:6]; // selects pwm signal ... | 7.293351 |
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = (a + b + c + d == 0 | a + b + c + d == 2 | a + b + c + d == 4);
//you can also try to use Karnaugh map to find the logic.
endmodule
| 7.203305 |
module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid
); //
always @(*)
case (code)
8'h45: begin
out = 4'b0000;
valid = 1'b1;
end
8'h16: begin
out = 4'b0001;
valid = 1'b1;
end
8'h1e: begin
out = 4'b001... | 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output q
); //
always @(*) begin
case ({
a, b, c, d
})
4'd0: q = 1;
4'd1: q = 0;
4'd2: q = 0;
4'd3: q = 1;
4'd4: q = 0;
4'd5: q = 1;
4'd6: q = 1;
4'd7: q = 0;
4... | 7.203305 |
module c_BIN_EDGE_DETECTOR (
input [0:0] in_0,
output [0:0] out_0
);
wire net_0 = in_0;
wire net_1 = net_0;
wire net_2;
wire net_3;
wire net_4;
wire net_5;
assign out_0 = net_5;
f_K00 LogicGate_0 (
.in_1 (net_0),
.in_0 (net_4),
.out_0(net_5)
);
f_2 LogicGate_1 (
... | 6.553472 |
module c_BIN_NAND_DLATCH (
input [0:0] in_0,
input [0:0] in_1,
output [0:0] out_0,
output [0:0] out_1
);
wire net_0 = in_0;
wire net_1 = net_0;
wire net_2 = in_1;
wire net_3 = net_2;
wire net_4;
wire net_5;
wire net_6;
wire net_7;
wire net_8;
assign out_0 = net_7;
assign out_1... | 6.60502 |
module c_BIN_NAND_SR_LATCH (
input [0:0] in_0,
input [0:0] in_1,
output [0:0] out_0,
output [0:0] out_1
);
wire net_0 = in_0;
wire net_1 = in_1;
wire net_2;
wire net_3;
wire net_4 = net_2;
wire net_5 = net_3;
assign out_0 = net_4;
assign out_1 = net_5;
f_22Z LogicGate_0 (
.... | 6.860786 |
module c_BIN_ZOOK_DLATCH (
input [0:0] in_0,
input [0:0] in_1,
output [0:0] out_0
);
wire net_0 = in_0;
wire net_1 = in_1;
wire net_2;
wire net_3 = net_2;
assign out_0 = net_3;
f_Z00K00KKK LogicGate_0 (
.in_2 (net_0),
.in_0 (net_2),
.in_1 (net_1),
.out_0(net_2)
);... | 6.781969 |
module f_2 (
input wire in_0,
output wire out_0
);
assign out_0 = (in_0 == 0);
endmodule
| 7.388176 |
module f_K00 (
input wire in_0,
input wire in_1,
output wire out_0
);
assign out_0 = (in_0 == 1 & in_1 == 1);
endmodule
| 6.889262 |
module f_Z00K00KKK (
input wire in_0,
input wire in_1,
input wire in_2,
output wire out_0
);
assign out_0 = (in_0 == 0 & in_1 == 1 & in_2 == 0) | (in_0 == 1 & in_1 == 1 & in_2 == 0) | (in_0 == 1 & in_1 == 0 & in_2 == 1) | (in_0 == 1 & in_1 == 1 & in_2 == 1);
endmodule
| 6.599243 |
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = (b & d) | (b & c) | (a & d) | (a & c);
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output q
); //
always @(*) begin
case ({
a, b, c, d
})
4'd0: q = 0;
4'd1: q = 0;
4'd2: q = 0;
4'd3: q = 0;
4'd4: q = 0;
4'd5: q = 1;
4'd6: q = 1;
4'd7: q = 1;
4... | 7.203305 |
module top_module (
input a,
input b,
output q
); //
assign q = a & b; // Fix me
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = b | c;
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output q
); //
always @(*) begin
case ({
a, b, c, d
})
4'd0: q = 0;
4'd1: q = 0;
4'd2: q = 1;
4'd3: q = 1;
4'd4: q = 1;
4'd5: q = 1;
4'd6: q = 1;
4'd7: q = 1;
4... | 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = (~a)&(~b)&(~c)&(~d) | (~a)&(~b)&(c)&(d) | (~a)&(b)&(~c)&(d) | (~a)&(b)&(c)&(~d) |
(a)&(b)&(~c)&(~d) |(a)&(b)&(c)&(d) | (a)&(~b)&(~c)&(d) | (a)&(~b)&(c)&(~d); // Fix me
endmodule
| 7.203305 |
module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output [3:0] q
);
always @(*) begin
case (c)
0: q = b;
1: q = e;
2: q = a;
3: q = d;
default: q = 4'hf;
endcase
end
endmodule
| 7.203305 |
module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output [3:0] q
);
always @(*) begin
case (c)
4'h0: q = b;
4'h1: q = e;
4'h2: q = a;
4'h3: q = d;
default: q = 4'hf;
endcase
end
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = (a | b) & (c | d); // Fix me
endmodule
| 7.203305 |
module top_module (
input [2:0] a,
output reg [15:0] q
);
always @(*) begin
case (a)
0: q = 16'h1232;
1: q = 16'haee0;
2: q = 16'h27d4;
3: q = 16'h5a0e;
4: q = 16'h2066;
5: q = 16'h64ce;
6: q = 16'hc526;
7: q = 16'h2f19;
endcase
end
endmodule
| 7.203305 |
module top_module (
input [ 2:0] a,
output [15:0] q
);
always @(*) begin
case (a)
3'd0: q = 16'h1232;
3'd1: q = 16'haee0;
3'd2: q = 16'h27d4;
3'd3: q = 16'h5a0e;
3'd4: q = 16'h2066;
3'd5: q = 16'h64ce;
3'd6: q = 16'hc526;
3'd7: q = 16'h2f19;
endcase
... | 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = b | ((~b) & c); // Fix me
endmodule
| 7.203305 |
module shift_ff (
input wire clk,
reset,
shift,
prev_dff,
d_in,
output wire q
);
mux2 m (
d_in,
prev_dff,
shift,
in
); // To select between shift and load operations
dfrl ff (
clk,
reset,
1'b1,
in,
q
);
endmodule
| 6.666654 |
module shift_register (
input wire clk,
reset,
load,
input wire [15:0] in,
output wire out_bit,
output wire [15:0] contents
);
// This is a module for one shift register, i.e a collection of 16 D-Flip Flops
// Loads data parallely and on each clock cycle shifts the data by one bit
// load ... | 6.854847 |
module shift_resgister_out (
input wire clk,
reset,
in1,
output wire [15:0] sum
);
// This register is used to store the sum output
// in1 is the input bit received from the sum output of the fulladder
wire intermediate[14:0];
dfrl d1 (
clk,
reset,
1'b1,
in1,
interm... | 6.776277 |
module shift_adder (
input wire clk,
reset,
load,
input wire [15:0] a,
b,
output wire [15:0] contents_a,
contents_b,
op,
output wire carry
);
// This is the serial shift adder module
// It takes two 16 bit numbers a and b as input and loads them to the shift registers a and b
... | 7.572689 |
module Bit16Adder (
a,
b,
cin,
sum,
cout
);
input [16:1] a, b;
input cin;
output [16:1] sum;
output cout;
wire w1, w2, w3;
Bit4Adder B4A_0 (
a[4:1],
b[4:1],
cin,
sum[4:1],
w1
);
Bit4Adder B4A_1 (
a[8:5],
b[8:5],
w1,
sum[8:5],
... | 6.99225 |
module invert (
output ib,
input b
);
assign ib = ~b;
endmodule
| 7.953624 |
module and2 (
input wire i0,
i1,
output wire o
);
assign o = i0 & i1;
endmodule
| 8.35921 |
module or2 (
input wire i0,
i1,
output wire o
);
assign o = i0 | i1;
endmodule
| 8.541431 |
module xor2 (
input wire i0,
i1,
output wire o
);
assign o = i0 ^ i1;
endmodule
| 8.782532 |
module nand2 (
input wire i0,
i1,
output wire o
);
wire t;
and2 and2_0 (
i0,
i1,
t
);
invert invert_0 (
t,
o
);
endmodule
| 7.360689 |
module nor2 (
input wire i0,
i1,
output wire o
);
wire t;
or2 or2_0 (
i0,
i1,
t
);
invert invert_0 (
t,
o
);
endmodule
| 7.781479 |
module xnor2 (
input wire i0,
i1,
output wire o
);
wire t;
xor2 xor2_0 (
i0,
i1,
t
);
invert invert_0 (
t,
o
);
endmodule
| 7.523861 |
module and3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
and2 and2_0 (
i0,
i1,
t
);
and2 and2_1 (
i2,
t,
o
);
endmodule
| 7.185291 |
module or3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
or2 or2_0 (
i0,
i1,
t
);
or2 or2_1 (
i2,
t,
o
);
endmodule
| 7.924047 |
module nor3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
or2 or2_0 (
i0,
i1,
t
);
nor2 nor2_0 (
i2,
t,
o
);
endmodule
| 7.838557 |
module nand3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
and2 and2_0 (
i0,
i1,
t
);
nand2 nand2_1 (
i2,
t,
o
);
endmodule
| 7.036906 |
module xor3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
xor2 xor2_0 (
i0,
i1,
t
);
xor2 xor2_1 (
i2,
t,
o
);
endmodule
| 8.362259 |
module xnor3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
xor2 xor2_0 (
i0,
i1,
t
);
xnor2 xnor2_0 (
i2,
t,
o
);
endmodule
| 7.872322 |
module fa (
input wire i0,
i1,
cin,
output wire sum,
cout
);
wire t0, t1, t2;
xor3 _i0 (
i0,
i1,
cin,
sum
);
and2 _i1 (
i0,
i1,
t0
);
and2 _i2 (
i1,
cin,
t1
);
and2 _i3 (
cin,
i0,
t2
);
or3 _i4 (
... | 7.001699 |
module Adder (
a,
b,
sum
);
input [15:0] a, b;
output [15:0] sum;
wire cout;
wire [15:0] q;
fa fa1 (
a[0],
b[0],
1'b0,
sum[0],
q[0]
);
fa fa2 (
a[1],
b[1],
q[0],
sum[1],
q[1]
);
fa fa3 (
a[2],
b[2],
q[1],
s... | 6.808429 |
module booth_substep (
input wire signed [15:0] a,
Q,
input wire signed q0,
input wire signed [15:0] m,
output reg signed [15:0] f8,
output reg signed [15:0] l8,
output reg cq0
);
wire [15:0] addam, subam;
Adder myadd (
a,
m,
addam
);
subtractor mysub (
a,
... | 6.761271 |
module mul16_unsigned (
input signed [15:0] A,
B,
input clk,
output signed [31:0] P
);
mul16_signed(
A, B, clk, P
);
endmodule
| 6.602435 |
module dff (
q,
d,
clk
);
input d, clk;
output q;
reg q;
always @(negedge clk) q <= d;
endmodule
| 8.035763 |
module shiftreg_tb;
reg [15:0] din;
reg sin, ld, mode, clk;
wire [15:0] dout;
shiftreg SR1 (
sin,
din,
dout,
ld,
mode,
clk
);
parameter STDIN = 32'h8000_0000;
integer testid;
integer ret;
initial begin
clk = 1'b1;
forever #50 clk = ~clk;
end
initial... | 6.713753 |
module bit16_4way_mux (
out,
i0,
i1,
i2,
i3,
s0,
s1
);
input [15:0] i0, i1, i2, i3;
input s0, s1;
output [15:0] out;
wire [15:0] x, y;
wire inv;
not_gate not_1 (
inv,
s0,
s0
); //complement of s0
//not_gate not_2(inv1,s1,s1); //complement of s1
mu... | 7.474265 |
module mux_8way (
out,
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
s0,
s1,
s2
);
output [15:0] out;
input [15:0] in0, in1, in2, in3, in4, in5, in6, in7;
input s0, s1, s2;
wire [15:0] x, y;
bit16_4way_mux mux_8way_1 (
x,
in0,
in1,
in2,
... | 6.70825 |
module adder_4bit (
a,
b,
cin,
sum,
carry
);
output [3:0] sum;
output carry;
input [3:0] a;
input [3:0] b;
input cin;
wire [2:0] s;
Full_Adder u0 (
a[0],
b[0],
1'b0,
sum[0],
s[0]
);
Full_Adder u1 (
a[1],
b[1],
s[0],
sum[1],
... | 9.041993 |
module adder_16bit (
a,
b,
sum,
carry
);
input [15:0] a;
input [15:0] b;
output [15:0] sum;
output carry;
wire [2:0] s;
adder_4bit u0 (
a[3:0],
b[3:0],
1'b0,
sum[3:0],
s[0]
);
adder_4bit u1 (
a[7:4],
b[7:4],
s[0],
sum[7:4],
s... | 7.133988 |
module mux4x1 (
in,
sel,
out
);
input [3:0] in;
input [1:0] sel;
output out;
wire [1:0] sel_bar;
wire in0s0, in1s1, in2s2, in3s3;
not n1 (sel_bar[0], sel[0]);
not n1 (sel_bar[1], sel[1]);
and a1 (in0s0, in[0], sel_bar[1], sel_bar[0]);
and a2 (in1s1, in[1], sel_bar[1], sel[0]);
and a3 ... | 6.791623 |
module gf2m #(
parameter DIGITAL = 16,
parameter DATA_WIDTH = 163
) (
input wire rst,
input wire clk,
input wire start,
input wire [DATA_WIDTH - 1 : 0] a,
input wire [DATA_WIDTH - 1 : 0] g,
input wire [DIGITAL - 1:0] b,
output reg [DATA_WIDTH - 1 : 0] t_i_j,
output reg done
);
... | 7.196913 |
module flop_16bit (
rst_n,
x,
y,
clk,
stall
);
input rst_n, clk, stall;
input [15:0] x;
output reg [15:0] y;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) y <= 0;
else if (stall) y <= y;
else y <= x;
end
endmodule
| 8.140276 |
module PGU (
a,
b,
p,
g
);
input [15:0] a, b;
output [15:0] p, g;
assign p = a ^ b;
assign g = a & b;
endmodule
| 7.368717 |
module BCLU (
p,
g,
cin,
ps,
gs,
c
);
input [3:0] p, g;
input cin;
output ps, gs;
output [2:0] c;
assign ps = p[3] & p[2] & p[1] & p[0];
assign gs = g[3] | p[3] & g[2] | p[3] & p[2] & g[1] | p[3] & p[2] & p[1] & g[0];
assign c[0] = g[0] | p[0] & cin;
assign c[1] = g[1] | p[... | 7.053402 |
module CLU (
ps,
gs,
cin,
c
);
input ps, gs, cin;
output c;
assign c = gs | ps & cin;
endmodule
| 7.105785 |
module SU (
p,
cin,
c,
s
);
input [15:0] p;
input cin;
input [14:0] c;
output [15:0] s;
assign s = p ^ {c, cin};
endmodule
| 7.057463 |
module D1_3bit (
in,
clk,
out
);
input [2:0] in;
input clk;
output reg [2:0] out;
always @(posedge clk) begin
out <= in;
end
endmodule
| 6.884111 |
module D1_4bit (
in,
clk,
out
);
input [3:0] in;
input clk;
output reg [3:0] out;
always @(posedge clk) begin
out <= in;
end
endmodule
| 7.122843 |
module D1_16bit (
in,
clk,
out
);
input [15:0] in;
input clk;
output reg [15:0] out;
always @(posedge clk) begin
out <= in;
end
endmodule
| 6.605137 |
module DD2 (
in,
clk,
out
);
input in, clk;
output reg out;
reg r_data;
always @(posedge clk) begin
r_data <= in;
out <= r_data;
end
endmodule
| 6.600992 |
module DD4 (
in,
clk,
out
);
input in, clk;
output reg out;
reg [2:0] r_data;
always @(posedge clk) begin
r_data[0] <= in;
r_data[1] <= r_data[0];
r_data[2] <= r_data[1];
out <= r_data[2];
end
endmodule
| 6.511385 |
module DD2_4bit (
in,
clk,
out
);
input [3:0] in;
input clk;
output reg [3:0] out;
reg [3:0] r_data;
always @(posedge clk) begin
r_data <= in;
out <= r_data;
end
endmodule
| 7.031347 |
module DD3_4bit (
in,
clk,
out
);
input [3:0] in;
input clk;
output reg [3:0] out;
reg [3:0] r_data[0:1];
always @(posedge clk) begin
r_data[0] <= in;
r_data[1] <= r_data[0];
out <= r_data[1];
end
endmodule
| 6.638852 |
module DD2_3bit (
in,
clk,
out
);
input [2:0] in;
input clk;
output reg [2:0] out;
reg [2:0] r_data;
always @(posedge clk) begin
r_data <= in;
out <= r_data;
end
endmodule
| 6.963781 |
module DD3_3bit (
in,
clk,
out
);
input [2:0] in;
input clk;
output reg [2:0] out;
reg [2:0] r_data[0:1];
always @(posedge clk) begin
r_data[0] <= in;
r_data[1] <= r_data[0];
out <= r_data[1];
end
endmodule
| 6.61913 |
module DD4_3bit (
in,
clk,
out
);
input [2:0] in;
input clk;
output reg [2:0] out;
reg [2:0] r_data[0:2];
always @(posedge clk) begin
r_data[0] <= in;
r_data[1] <= r_data[0];
r_data[2] <= r_data[1];
out <= r_data[2];
end
endmodule
| 6.941144 |
module DD4_16bit (
in,
clk,
out
);
input [15:0] in;
input clk;
output reg [15:0] out;
reg [15:0] r_data[0:2];
always @(posedge clk) begin
r_data[0] <= in;
r_data[1] <= r_data[0];
r_data[2] <= r_data[1];
out <= r_data[2];
end
endmodule
| 7.075333 |
module Pip16CLA (
a,
b,
cin,
clk,
s,
cout
);
input [15:0] a, b;
input cin;
input clk;
output [15:0] s;
output cout;
wire cin2;
wire cin22;
wire [15:0] a2, b2, p, g, p2, g2, p22; //pccc
wire [11:0] p222, g222; //pcc, gcc
wire [14:0] c;
wire [ 2:0] c2;
wire [15:0] c22;
... | 6.942108 |
module fulladder (
a,
b,
cin,
s,
cout
);
input a, b, cin;
output s, cout;
assign s = (a ^ b) ^ cin;
assign cout = ((a & b) | ((a ^ b) & cin));
endmodule
| 7.454465 |
module DD2 (
in,
clk,
out
);
input in, clk;
output reg out;
reg r_data;
always @(posedge clk) begin
r_data <= in;
out <= r_data;
end
endmodule
| 6.600992 |
module DD4 (
in,
clk,
out
);
input in, clk;
output reg out;
reg [2:0] r_data;
always @(posedge clk) begin
r_data[0] <= in;
r_data[1] <= r_data[0];
r_data[2] <= r_data[1];
out <= r_data[2];
end
endmodule
| 6.511385 |
module Pip4RCA (
a,
b,
cin,
clk,
s,
cout
);
input [3:0] a, b;
input cin;
input clk;
output [3:0] s;
output cout;
wire [2:0] c;
wire [2:0] c2;
wire [3:0] b2;
wire [3:0] a2;
wire [3:0] out;
wire cin2;
//FA0? ??? ? ?? s0, c0
DD1 D1 (
a[0],
clk,
a2[0]
... | 6.853022 |
module DD1_16 (
in,
clk,
out
);
input [15:0] in;
input clk;
output reg [15:0] out;
always @(posedge clk) begin
out <= in;
end
endmodule
| 6.966147 |
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