code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module DD5 (
in,
clk,
out
);
input [3:0] in;
input clk;
output reg [3:0] out;
reg [3:0] r_data[0:3];
always @(posedge clk) begin
r_data[0] <= in;
r_data[1] <= r_data[0];
r_data[2] <= r_data[1];
r_data[3] <= r_data[2];
out <= r_data[3];
end
endmodule
| 6.77203 |
module DD10 (
in,
clk,
out
);
input [3:0] in;
input clk;
output reg [3:0] out;
reg [3:0] r_data[0:8];
always @(posedge clk) begin
r_data[0] <= in;
r_data[1] <= r_data[0];
r_data[2] <= r_data[1];
r_data[3] <= r_data[2];
r_data[4] <= r_data[3];
r_data[5] <= r_data[4];
r_... | 6.671791 |
module DD15 (
in,
clk,
out
);
input [3:0] in;
input clk;
output reg [3:0] out;
reg [3:0] r_data[0:13];
always @(posedge clk) begin
r_data[0] <= in;
r_data[1] <= r_data[0];
r_data[2] <= r_data[1];
r_data[3] <= r_data[2];
r_data[4] <= r_data[3];
r_data[5] <= r_data[4];
... | 7.147228 |
module Pip16RCA (
a,
b,
cin,
clk,
s,
cout
);
input [15:0] a, b;
input cin;
input clk;
output [15:0] s;
output cout;
wire cin2;
wire [15:0] a2, b2;
wire [11:0] a22, b22;
wire [15:0] s2;
wire [ 2:0] c;
wire [ 2:0] c2;
//RCA0
DD1 D111 (
cin,
clk,
cin2
... | 6.568046 |
module tb_Pip16RCA ();
reg clk = 0;
reg [15:0] a, b;
reg cin;
wire [15:0] s;
wire cout;
Pip16RCA Pip16RCA0 (
a,
b,
cin,
clk,
s,
cout
);
always #5 clk = ~clk;
initial begin
a = 16'b0110_1111_0111_0111;
b = 16'b0111_0001_0111_1000;
cin = 0;
#15... | 7.030769 |
module sequence_generator (
clock,
Yt,
Yt1
);
input clock;
output [3:0] Yt, Yt1;
reg [3:0] Yt, Yt1;
initial begin
Yt = 3'b101;
end
always @(negedge clock) begin
case (Yt)
3'b000: begin
Yt = 3'b001;
end
3'b001: begin
Yt = 3'b010;
end
3'b010: ... | 7.628189 |
module complement (
a,
b,
c,
d,
w,
x,
y,
z
);
input a, b, c, d;
output reg w, x, y, z;
always @(a, b, c, d) begin
assign w = (~a) & (~b) & (~c);
assign x = b ^ c;
assign y = c;
assign z = ~d;
end
endmodule
| 7.736521 |
module dflipflop (
d,
clock,
qn,
q
);
input d, clock;
output q, qn;
reg q, qn;
always @(posedge clock) begin
q <= d;
qn <= ~d;
end
endmodule
| 7.751981 |
module sequence_generator (
Yt,
Yt1,
clock
);
input clock;
output [3:0] Yt, Yt1;
reg [3:0] Yt, Yt1;
initial begin
Yt = 4'b0010;
end
always @(posedge clock) begin
case (Yt)
4'b0000: begin
Yt1 = 4'b1000;
end
4'b1000: begin
Yt1 = 4'b0101;
end
4... | 7.628189 |
module pipo (
data,
dataout,
clock,
reset
);
output reg [3:0] dataout;
input [3:0] data;
input clock;
input reset;
always @(negedge clock) begin
if (reset) dataout <= 4'b0000;
else dataout <= data;
end
endmodule
| 6.891143 |
module complement (
a,
b,
c,
d,
w,
x,
y,
z
);
input a, b, c, d;
output w, x, y, z;
wire w1, w2, w3, w4;
assign w1 = ~a;
assign w2 = ~b;
assign w3 = w1 & w2;
assign w4 = ~c;
assign w = w3 & w4;
assign x = b ^ c;
assign y = c;
assign z = ~d;
endmodule
| 7.736521 |
module dflipflop (
D,
Clock,
Q,
Qn
);
output Q, Qn;
input Clock, D;
wire Cn;
wire Cnn;
wire DQ;
wire DQn;
assign Cn = ~Clock;
assign Cnn = ~Cn;
d_latch dl (
DQ,
DQn,
Cn,
D
);
sr_latch_gated sr (
Q,
Qn,
Cnn,
DQ,
DQn
);
endmod... | 7.751981 |
module d_latch (
Q,
Qn,
G,
D
);
output Q, Qn;
input G, D;
wire Dn, D1, Dn1;
assign Dn = ~D;
assign D1 = G & D;
assign Dn1 = G & Dn;
assign Qn = ~(D1 | Q);
assign Q = ~(Dn1 | Qn);
endmodule
| 6.881555 |
module sequence_generator (
Yt,
Yt1,
clock
);
input clock;
output [3:0] Yt, Yt1;
output w0, w1, w2, w3;
tflipflop a3 (
.Yt(w3),
.Yt1(Yt[3]),
.clock(clock)
);
tflipflop a2 (
.Yt(w2),
.Yt1(Yt[2]),
.clock(clock)
);
tflipflop a1 (
.Yt(w1),
.Yt1(Yt... | 7.628189 |
module tflipflop (
Yt,
Yt1,
clock
);
input Yt;
input clock;
output Yt1;
reg Yt1, Yt1c;
initial begin
Yt1 = 0;
Yt1c = 1;
end
always @(posedge clock) begin
if (Yt == 1'b1) begin
Yt1 = (~Yt1);
Yt1c = (~Yt1c);
end else if (Yt == 1'b0) begin
Yt1 = Yt1;
Yt1... | 6.576555 |
module pipo (
data,
dataout,
clock,
reset
);
input reset, clock;
input [3:0] data;
output [3:0] dataout;
d_flip_flop o1 (
data[0],
clock,
reset,
dataout[0]
);
d_flip_flop o2 (
data[1],
clock,
reset,
dataout[1]
);
d_flip_flop o3 (
dat... | 6.891143 |
module d_flip_flop (
d,
clock,
reset,
q
);
output q;
input d, clock, reset;
wire w1, w2, w3, w4, w1n, w2n, w3n, w4n;
assign w1 = ~(d & clock);
assign w1n = ~(~d & clock);
assign w2 = ~(w1 & w2n);
assign w2n = ~(~reset & w1n & w2);
assign w3 = ~(~clock & w2);
assign w3n = ~(~clock &... | 7.497066 |
module complement (
a,
b,
c,
d,
w,
x,
y,
z
);
input a, b, c, d;
output w, x, y, z;
wire w1, w2, w3, w4;
not (w1, a); // w1 = a`
not (w2, b); // w2 = b`
not (w4, c); // w4 = c`
and (w3, w1, w2); // w3 = w1.w2 = (a`.b`)
and (w, w3, w4); // w = w3.w4 = (a`.b`.c`)
xo... | 7.736521 |
module dflipflop (
D,
Clock,
Q,
Qn
);
output Q, Qn;
input Clock, D;
wire Cn;
wire Cnn;
wire DQ;
wire DQn;
not (Cn, Clock);
not (Cnn, Cn);
d_latch dl (
DQ,
DQn,
Cn,
D
);
sr_latch_gated sr (
Q,
Qn,
Cnn,
DQ,
DQn
);
endmodule
| 7.751981 |
module d_latch (
Q,
Qn,
G,
D
);
output Q, Qn;
input G, D;
wire Dn, D1, Dn1;
not (Dn, D);
and (D1, G, D);
and (Dn1, G, Dn);
nor (Qn, D1, Q);
nor (Q, Dn1, Qn);
endmodule
| 6.881555 |
module sequence_generator (
Yt,
Yt1,
clock
);
input clock;
output [3:0] Yt, Yt1;
wire w1, w2, w3, w4;
tflipflop a3 (
w3,
Yt[3],
clock
);
tflipflop a2 (
w2,
Yt[2],
clock
);
tflipflop a1 (
w1,
Yt[1],
clock
);
tflipflop a0 (
w0,
... | 7.628189 |
module tflipflop (
Yt,
Yt1,
clock
);
input Yt;
input clock;
output Yt1;
reg Yt1, Yt1c;
initial begin
Yt1 = 0;
Yt1c = 1;
end
always @(posedge clock) begin
if (Yt == 1'b1) begin
Yt1 = (~Yt1);
Yt1c = (~Yt1c);
end else if (Yt == 1'b0) begin
Yt1 = Yt1;
Yt1... | 6.576555 |
module pipo (
data,
dataout,
clock,
reset
);
input reset, clock;
input [3:0] data;
output [3:0] dataout;
d_flip_flop o0 (
data[0],
clock,
reset,
dataout[0]
);
d_flip_flop o1 (
data[1],
clock,
reset,
dataout[1]
);
d_flip_flop o2 (
dat... | 6.891143 |
module d_flip_flop (
d,
clock,
reset,
q
);
output q;
input d, clock, reset;
wire dn, resetn, clockn, w1, w2, w3, w4, w1n, w2n, w3n, w4n;
nand (w1, d, clock);
not (dn, d);
nand (w1n, dn, clock);
not (resetn, reset);
nand (w2, w1, w2n);
nand (w2n, resetn, w1n, w2);
not (clockn, clock)... | 7.497066 |
module fpga_gf2m #(
parameter DIGITAL = 16,
parameter DATA_WIDTH = 163
) (
input clk, // Clock
input rst, // Asynchronous reset active low
input wire start,
input wire [DATA_WIDTH - 1 : 0] a,
input wire [DATA_WIDTH - 1 : 0] g,
input wire [BWIDTH - 1:0] b,
output reg [DATA_WIDTH - 1... | 6.91314 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0]... | 6.504296 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0]... | 6.504296 |
module booth_array (
input [15:0] multiplier,
output [ 7:0] zero,
output [ 7:0] double,
output [ 7:0] negation
);
booth_radix4 booth_radix4_0 (
{multiplier[1:0], 1'b0},
zero[0],
double[0],
negation[0]
);
booth_radix4 booth_radix4_1 (
multiplier[3:1],
zero[1],... | 6.70532 |
module half_adder (
input A,
input B,
output S,
output carry
);
assign S = A ^ B;
assign carry = A & B;
endmodule
| 6.966406 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0]... | 6.504296 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module used to convert binary code to gray code
//author:WangFW
//date:2020-5-25
module bin_to_gray(bin_code,gray_code);
//input clk;
//input rst_n;
input [7:0] bin_code;
output [7:0] gray_code;
/*always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
gray_code<=8'd0;
else
gray_code<=(bin_code>>... | 7.274583 |
module bin_to_gray_tb ();
//reg clk;
//reg rst_n;
reg [7:0] bin_code;
wire [7:0] gray_code;
initial begin
//clk=0;
//rst_n=1;
bin_code <= 8'd0;
repeat (256) #2 bin_code = bin_code + 1'b1;
//#10 rst_n=0;
//#10 rst_n=1;
end
//always #2 clk<=~clk;
//always @(posedge clk)
//bin... | 6.686182 |
module ALU16 (
A,
B,
opcode,
out
);
//4 bit input signals
input [3:0] A, B;
//4 bit opcode input
input [3:0] opcode;
//output after operation
output reg [3:0] out;
always @(*) begin
case (opcode)
//addition
4'b0000: out = A + B;
//subtraction
4'b0001: out = A... | 6.816861 |
module up_down_counter (
input [15:0] begpoint,
input clk,
load,
reset,
up_down,
output [15:0] counter
);
reg [15:0] counter_up_down;
always @(posedge clk or posedge reset) begin
if (~reset) counter_up_down <= begpoint;
else if (~load) begin
if (up_down) counter_up_down <= coun... | 7.520907 |
module ST_Bit_MUX (
Load,
Image,
Layer,
AddressInDecompressed,
AddressInFile,
AddressInCNN,
AddressLayerInput,
AddressToRAM
);
input Load, Image, Layer;
input [15:0] AddressInDecompressed, AddressInFile, AddressInCNN, AddressLayerInput;
reg [15:0] Temp, TempIn;
output [15:0] Add... | 7.808518 |
module RAM (
d_in,
d_out,
adr,
WE,
CE,
clk,
OE
);
input [7:0] d_in;
output [7:0] d_out;
input CE, WE, clk, OE;
input [4:0] adr;
reg [7:0] d_mem[15:0]; //array of sixteen 8bit registers
always @(posedge clk) begin
if (CE) begin
if (WE) begin
d_mem[adr] <= d_in... | 6.742331 |
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output [23:0] out_bytes,
output done
); //
// FSM from fsm_ps2
parameter BYTE1 = 0, BYTE2 = 1, BYTE3 = 2, DONE = 3;
reg [1:0] cstate, nstate;
reg [23:0] o_bytes;
reg [ 7:0] r_bytes;
assign out_bytes = o_b... | 7.203305 |
module tb_delays;
reg clk;
reg rst;
reg d;
initial begin
$dumpfile("test.vcd");
$dumpvars;
end
initial begin // <- Initial construct are evaluated at t = 0.
// Here, t = 0.
clk = 1'b0;
rst = 1'b1;
d = 1'b0;
#3;
// Here, t = 3;
rst = 1'b0;
#2;
// Here, t... | 6.522164 |
module top_module (
input clk,
input d,
output q
);
reg q1, q2;
always @(posedge clk) begin
q1 <= q2 ^ d;
end
always @(negedge clk) begin
q2 <= q1 ^ d;
end
assign q = q1 ^ q2;
endmodule
| 7.203305 |
module top_module (
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different
);
assign out_both = in[98:0] & in[99:1]; //here bits of input vector is shifted right
//and bitwise and is performed to obtain the required output
assign out_any = in[99:... | 7.203305 |
module top_module (
input clk,
input reset,
input [31:0] in,
output [31:0] out
);
reg [31:0] q;
always @(posedge clk) begin
q <= in;
if (reset) out <= 0;
else out <= out | q & ~in;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output done
);
parameter start=0, bit1=1, bit2=2, bit3=3, bit4=4, bit5=5, bit6=6, bit7=7, bit8=8, stop=9, idle=10, WAIT=11;
reg [3:0] state, nextstate;
always @(*) begin
case (state)
start: nextstate = bit1;... | 7.203305 |
module top_module (
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different
);
assign out_both = {in[98:0] & in[99:1]};
assign out_any = {in[99:1] | in[98:0]};
assign out_different = {in[99:0] ^ {in[0], in[99:1]}};
endmodule
| 7.203305 |
module top_module (
input [7:0] in,
output [7:0] out
);
assign out = {in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7]};
endmodule
| 7.203305 |
module top_module (
input [7:0] in,
output [7:0] out
);
assign out = {in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7]};
endmodule
| 7.203305 |
module top_module (
input clk,
input a,
output q
);
always @(posedge clk) begin
q <= ~a;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input a,
output q
);
always @(posedge clk) begin
q <= (~a);
end
endmodule
| 7.203305 |
module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output reg [3:0] q
);
// 4 to 1 multiplexer
always @(*) begin
case (c)
4'b0000: q = b;
4'b0001: q = e;
4'b0010: q = a;
4'b0011: q = d;
default: q <= 4'b1111;
... | 7.203305 |
module top_module (
input clock,
input a,
output p,
output q
);
always @(*) begin
if (clock) p = a;
end
always @(negedge clock) begin
q <= p;
end
endmodule
| 7.203305 |
module top_module (
input clock,
input a,
output reg p,
output q
);
always @(*) begin
if (clock) p = a;
end
always @(negedge clock) begin
q <= a;
end
endmodule
| 7.203305 |
module top_module (
input [2:0] a,
output reg [15:0] q
);
always @(a) begin
case (a)
3'b000: q = 16'h1232;
3'b001: q = 16'haee0;
3'b010: q = 16'h27d4;
3'b011: q = 16'h5a0e;
3'b100: q = 16'h2066;
3'b101: q = 16'h64ce;
3'b110: q = 16'hc526;
3'b111: q ... | 7.203305 |
module top_module (
input clk,
input a,
output [3:0] q
);
always @(posedge clk) begin
if (a) q <= 4;
else begin
if (q < 6) q <= q + 1;
else q <= 0;
end
end
endmodule
| 7.203305 |
module top_module (
input clk,
input a,
output [3:0] q
);
always @(posedge clk) begin
if (a) q <= 4;
else if (q == 6) q <= 0;
else q <= q + 1;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input a,
output reg q
);
always @(posedge clk) begin
q <= ~a;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input a,
input b,
output q,
output state
);
always @(posedge clk) begin
if (a == b) state <= a;
else state <= state;
end
assign q = (a == b) ? state : (~state);
endmodule
| 7.203305 |
module top_module (
input clk,
input a,
input b,
output q,
output state
);
always @(posedge clk) begin
state <= (a == b) ? a : state;
end
assign q = (a == b) ? state : ~state;
endmodule
| 7.203305 |
module top_module (
input clock,
input a,
output p,
output reg q
);
// q
initial begin
q = 1'b1;
end
always @(negedge clock) begin
if (a) q <= 1'b1;
else q <= 1'b0;
end
assign p = (clock & a & (~q)) | ((~clock) & (~a) & q) | ((~clock) & a & q) | (clock & a & q);
endmodule
| 7.203305 |
module top_module ();
parameter time_period = 10;
reg clk;
initial clk = 0;
always begin
#(time_period / 2) clk = ~clk;
end
dut u_dut (.clk(clk));
endmodule
| 6.627149 |
module top_module ();
reg clk;
always #5 clk = ~clk;
initial begin
`probe_start
clk = 0;
end
dut dut_u0 (.clk(clk));
endmodule
| 6.627149 |
module top_module (
input clk,
input a,
output [3:0] q
);
parameter A = 3'b100;
parameter B = 3'b101;
parameter C = 3'b110;
parameter D = 3'b000;
parameter E = 3'b001;
parameter F = 3'b010;
parameter G = 3'b011;
reg [2:0] state;
reg [2:0] next_state;
// sequential logic
always @(pos... | 7.203305 |
module top_module (
output reg A,
output reg B
); //
// generate input patterns here
initial begin
A = 0;
B = 0;
#10;
A = 1;
B = 0;
#5;
A = 1;
B = 1;
#5;
A = 0;
B = 1;
#20;
A = 0;
B = 0;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input a,
input b,
output q,
output reg state
);
parameter Idle = 1'b0;
parameter Start = 1'b1;
reg next_state;
// sequential logic reset
always @(posedge clk) begin
if ((a == 1'b0) && (b == 1'b0)) state <= Idle;
else state <= next_state;
end
/... | 7.203305 |
module top_module (
output reg A,
output reg B
); //
// generate input patterns here
initial begin
A = 0;
B = 0;
#10;
A = 1;
#5;
B = 1;
#5;
A = 0;
#20;
B = 0;
#20;
B = 0;
#15;
// $finish;
end
endmodule
| 7.203305 |
module top_module ();
reg [1:0] in;
wire out;
initial begin
in = 2'b00;
#10;
in = 2'b01;
#10;
in = 2'b10;
#10;
in = 2'b11;
end
andgate u_andgate (
.in (in),
.out(out)
);
endmodule
| 6.627149 |
module top_module ();
reg [1:0] in;
andgate andgate_u0 (.in(in));
initial begin
in = 0;
#10;
in = 1;
#10;
in = 2;
#10;
in = 3;
#10;
end
endmodule
| 6.627149 |
module top_module ();
reg clk;
parameter PERIOD = 10;
initial begin
clk = 1'b0;
end
always #(PERIOD / 2) clk = ~clk;
dut u_dut (clk);
endmodule
| 6.627149 |
module top_module ();
reg clk;
reg in;
reg [2:0] s;
wire out;
initial begin
clk = 0;
in = 0;
s = 2;
#10;
s = 6;
#10;
s = 2;
in = 1;
#10;
s = 7;
in = 0;
#10;
in = 1;
s = 0;
#30;
in = 0;
end
always begin
#5 clk = ~clk;
end
q7 ... | 6.627149 |
module top_module (
output reg A,
output reg B
); //
// generate input patterns here
initial begin
A = 1'b0;
B = 1'B0;
#10 A = 1'b1;
#5 B = 1'b1;
#5 A = 1'b0;
#20 B = 1'b0;
end
endmodule
| 7.203305 |
module top_module ();
reg clk;
reg in;
reg [2:0] s;
q7 q7_u0 (
.clk(clk),
.in (in),
.s (s)
);
always #5 clk = ~clk;
initial begin
clk = 0;
in = 0;
s = 2;
repeat (1) @(negedge clk);
s = 6;
repeat (1) @(negedge clk);
in = 1;
s = 2;
repeat (1)... | 6.627149 |
module top_module ();
reg clk;
reg reset;
reg t;
wire q;
tff u_tff (
.clk (clk),
.reset(reset),
.t (t),
.q (q)
);
initial begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial begin
reset = 1'b0;
#3;
reset = 1'b1;
#10;
reset = 1'b0;
end... | 6.627149 |
module top_module ();
reg [1:0] in;
wire out;
initial begin
in = 2'b00;
#10 in = 2'b01;
#10 in = 2'b10;
#10 in = 2'b11;
end
andgate u_andgate (
.in (in),
.out(out)
);
endmodule
| 6.627149 |
module top_module ();
reg clk;
reg reset;
reg t;
always #5 clk = ~clk;
initial begin
clk = 0;
reset = 0;
t = 0;
end
initial begin
repeat (3) @(posedge clk);
reset = 1;
repeat (1) @(posedge clk);
reset = 0;
t = 1;
repeat (1) @(posedge clk);
end
tff tff_u0 (
... | 6.627149 |
module top_module (
input clk,
input load,
input [9:0] data,
output tc
);
reg [9:0] counter;
always @(posedge clk) begin
if (load == 1) begin
counter <= data;
end
if (load == 0) begin
if (counter != 0) begin
counter <= counter - 1;
end
end
end
assign tc ... | 7.203305 |
module top_module ();
reg clk;
reg in;
reg [2:0] s;
wire out;
parameter PERIOD = 10;
initial begin
clk = 1'b0;
in = 1'b0;
s = 3'b010;
end
always #(PERIOD / 2) clk = ~clk;
initial begin
#20 in = 1'b1;
#10 in = 1'b0;
#10 in = 1'b1;
#30 in = 1'b0;
end
initial beg... | 6.627149 |
module top_module (
input clk,
input load,
input [9:0] data,
output tc
);
reg [9:0] counter;
always @(posedge clk) begin
if (load) counter <= data;
else if (counter != 0) counter <= counter - 1;
end
assign tc = (counter == 0);
endmodule
| 7.203305 |
module 17var_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, valid);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q;
output valid;
wire [8:0] min_value = 9'd120;
wire [8:0] max_weight = 9'd60;
wire [8:0] max_volume = 9'd60;
wire [8:0] total_value =
A * 9'd4
+ B * ... | 6.95954 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module example_cases (
in,
out
);
input [2:0] in;
output reg [1:0] out;
always @(*) begin
case (in)
3'b000: begin
out = 2'b10;
end
3'b101: begin
out = 2'b11;
end
default: begin
out = 2'b00;
end
endcase
end
endmodule
| 6.872934 |
module used to find a special number
//author:WangFW
//date:2020-5-26
module finder(clk,rst_n,wr,din,find,dfind,full,is,location);
input clk;
input rst_n;
input wr;
input [7:0] din;
input find;
input [7:0] dfind;
output reg full;
output reg is;
output reg [5:0] location;
reg [7:0] mem [63:0];
reg [5:0] po... | 6.968102 |
module finder_tb ();
reg clk;
reg rst_n;
reg wr;
reg [7:0] din;
reg find;
reg [7:0] dfind;
wire full;
wire is;
wire [5:0] location;
initial begin
clk = 0;
rst_n = 1;
wr = 0;
din = 8'd0;
find = 0;
dfind = 8'd0;
#10 rst_n = 0;
#10 rst_n = 1;
wr = 1;
repeat (63)... | 6.596117 |
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output done
);
parameter IDLE = 5'b00001;
parameter START = 5'b00010;
parameter DATA = 5'b00100;
parameter WAIT = 5'b01000;
parameter STOP = 5'b10000;
reg [4:0] cstate;
reg [4:0] nstate;
reg [3:0] data_cnt;
... | 7.203305 |
module top_module (
input clk,
input d,
output q
);
reg [1:0] m;
always @(posedge clk) begin
m[0] <= d;
end
always @(negedge clk) begin
m[1] <= d;
end
assign q = clk ? m[0] : m[1];
endmodule
| 7.203305 |
module top_module (
input clk,
input d,
output q
);
reg p, n;
// A positive-edge triggered flip-flop
always @(posedge clk) p <= d ^ n;
// A negative-edge triggered flip-flop
always @(negedge clk) n <= d ^ p;
// Why does this work?
// After posedge clk, p changes to d^n. Thus q = (p^n) =... | 7.203305 |
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
// Use FSM from Fsm_serial
parameter start=0, bit1=1, bit2=2, bit3=3, bit4=4, bit5=5, bit6=6, bit7=7, bit8=8, stop=9, idle=10, WAIT=11;
reg [3:0] state, nextstate;
reg [7:... | 7.203305 |
module top_module (
input [ 7:0] in,
output [31:0] out
); //
// assign out = { replicate-sign-bit , the-input };
assign out = {{24{in[7]}}, in};
endmodule
| 7.203305 |
module top_module (
input clk,
input areset,
input train_valid,
input train_taken,
output [1:0] state
);
reg [1:0] next_state;
always @(posedge clk, posedge areset) begin
if (areset) state <= 2'b01;
else state <= next_state;
end
always @(*) begin
if (train_valid) begin
if (... | 7.203305 |
module top_module (
input clk,
input areset,
input train_valid,
input train_taken,
output reg [1:0] state
);
parameter SNT = 2'b00, WNT = 2'b01, WT = 2'b10, ST = 2'b11;
reg [1:0] n_state;
always @(*) begin
if (train_valid) begin
case (state)
SNT: n_state = (train_taken) ? W... | 7.203305 |
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