code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module top_module ();
// input
reg clk;
reg reset;
reg t;
// output
wire q;
// parameter
parameter PERIOD = 10;
initial begin
clk = 1'b0;
reset = 1'b0;
t = 1'b0;
end
// clk
always #(PERIOD / 2) clk = ~clk;
// reset
initial begin
#10 reset = 1;
#10 reset = 0;
en... | 6.627149 |
module top_module (
input clk,
input areset,
input predict_valid,
input predict_taken,
output [31:0] predict_history,
input train_mispredicted,
input train_taken,
input [31:0] train_history
);
reg [31:0] predict_history_reg;
always @(posedge clk, posedge areset) begin
if (arese... | 7.203305 |
module top_module (
input clk,
input areset,
input predict_valid,
input predict_taken,
output [31:0] predict_history,
input train_mispredicted,
input train_taken,
input [31:0] train_history
);
reg [31:0] n_predict_history;
always @(*) begin
if (train_mispredicted) n_predict_h... | 7.203305 |
module top_module (
input clk,
input areset,
input predict_valid,
input [6:0] predict_pc,
output predict_taken,
output [6:0] predict_history,
input train_valid,
input train_taken,
input train_mispredicted,
input [6:0] train_history,
input [6:0] train_pc
);
reg [1:0] PHT[1... | 7.203305 |
module top_module (
input clk,
input areset,
input predict_valid,
input [(N-1):0] predict_pc,
output predict_taken,
output [(N-1):0] predict_history,
input train_valid,
input train_taken,
input train_mispredicted,
input [(N-1):0] train_history,
input [(N-1):0] train_pc
);
... | 7.203305 |
module counter_2bc #(
parameter SNT = 2'b00,
WNT = 2'b01,
WT = 2'b10,
ST = 2'b11
) (
input clk,
input areset,
input train_valid,
input train_taken,
output reg [1:0] state
);
reg [1:0] n_state;
always @(*) begin
if (train_valid) begin
case (state)
SNT: n_state =... | 6.553139 |
module history_shift #(
parameter N = 7
) (
input clk,
input areset,
input predict_valid,
input predict_taken,
output [(N-1):0] predict_history,
input train_valid,
input train_mispredicted,
input train_taken,
input [(N-1):0] train_history
);
reg [(N-1):0] n_predict_history;
... | 6.629959 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module pre_adder (
mode,
dir,
a,
b,
c
);
input mode;
input dir;
input [18 : 0] a;
input [17 : 0] b;
input [18 : 0] c;
assign c = mode ? (dir ? a - b : a + b) : a;
endmodule
| 6.718407 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module HA (
input a,
b,
output c_out,
s
);
assign s = a ^ b;
assign c_out = a & b;
endmodule
| 9.138493 |
module FA (
input a,
b,
c_in,
output c_out,
s
);
wire wire_1;
wire wire_2;
wire wire_3;
assign wire_1 = a ^ b;
assign wire_2 = wire_1 & c_in;
assign wire_3 = a & b;
assign c_out = wire_2 | wire_3;
assign s = wire_1 ^ c_in;
endmodule
| 8.362615 |
module Adder_2_bits (
input [1:0] a,
b,
input c_in,
output [1:0] s,
output c_out
);
FA fa_00 (
a[0],
b[0],
c_in,
c0,
s[0]
);
FA fa_01 (
a[1],
b[1],
c0,
c_out,
s[1]
);
endmodule
| 7.402012 |
module fsm (
clk,
rst,
in1,
in2,
out1,
out2
);
input clk;
input rst;
input in1, in2;
output reg out1, out2;
reg [1:0] state, next_state; // Register that holds the current state.
// State encodings
localparam STATE_S0 = 2'd0;
localparam STATE_S1 = 2'd1;
localparam STATE_S2 ... | 7.213172 |
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
// Use FSM from Fsm_serial
parameter IDLE = 5'b00001;
parameter START = 5'b00010;
parameter DATA = 5'b00100;
parameter WAIT = 5'b01000;
parameter STOP = 5'b10000;
r... | 7.203305 |
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
// Modify FSM and datapath from Fsm_serialdata
parameter start=0, bit1=1, bit2=2, bit3=3, bit4=4, bit5=5, bit6=6, bit7=7, bit8=8, stop=9, idle=10, WAIT=11, bit9=12;
reg [3:0... | 7.203305 |
module top_module (
input a,
b,
c,
d,
e,
output [24:0] out
); //
// The output is XNOR of two vectors created by
// concatenating and replicating the five inputs.
// assign out = ~{ ... } ^ { ... };
assign out = {{5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}}} ~^ {5{a, b, c, d, e}};
endmodul... | 7.203305 |
module top_module (
input a,
b,
c,
d,
e,
output [24:0] out
); //
// The output is XNOR of two vectors created by
// concatenating and replicating the five inputs.
// assign out = ~{ ... } ^ { ... };
wire [24:0] top, bottom;
assign top = {{5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}}};
as... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module DMUX_tb ();
reg clk;
reg rst_n;
reg [3:0] din;
wire dout;
initial begin
clk = 0;
rst_n = 1;
din = 4'b1010;
#10 rst_n = 0;
#10 rst_n = 1;
end
always #2 clk <= ~clk;
initial $monitor("din=%b,dout=%b", din, dout);
DMUX dut (
.clk (clk),
.rst_n(rst_n),
... | 6.622306 |
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
// Modify FSM and datapath from Fsm_serialdata
parameter IDLE = 6'b000001;
parameter START = 6'b000010;
parameter DATA = 6'b000100;
parameter CHECK = 6'b001000;
parame... | 7.203305 |
module FAS (
M,
A,
B,
Cin,
D,
Cout
);
input M;
input A;
input B;
input Cin;
output D;
output Cout;
wire W4;
xor2 X3 (
B,
M,
W4
);
FA d (
A,
W4,
Cin,
D,
Cout
);
endmodule
| 7.492846 |
module aha_full_adder_subtractor (
A,
B,
Sel,
Cin,
Cout,
S
);
input A, B, Cin, Sel;
output Cout, S;
wire Bs, t1, t2, t3;
assign Bs = B ^ Sel;
assign t1 = Bs ^ A;
assign S = t1 ^ Cin;
assign t2 = A & Bs;
assign t3 = t1 & Cin;
assign Cout = t2 | t3;
endmodule
| 7.24041 |
module single_counter (
out,
clock,
reset
);
input clock, reset;
output out;
reg out;
always @(reset) if (reset == 1) out = 0;
always @(posedge clock) if (reset == 0) out = ~out;
endmodule
| 6.64582 |
module FADDER (
sum,
carry,
x,
y,
z
);
input x, y, z;
output sum, carry;
wire [0:7] d;
DECODER dec (
d,
x,
y,
z
);
assign sum = d[1] | d[2] | d[4] | d[7], carry = d[3] | d[5] | d[6] | d[7];
endmodule
| 6.577998 |
module ror4 (
input [3:0] in,
input [1:0] s,
output [3:0] out
);
assign out = in >> s;
endmodule
| 7.537229 |
module add_1bit (
input a,
input b,
input c0,
output s,
output c1
);
wire s;
wire c1;
assign s = (a ^ b) ^ c0;
assign c1 = (a & b) | (b & c0) | (c0 & a);
endmodule
| 7.224096 |
module one_bit_comp (
input A,
B,
output reg EQ
);
always @(A, B) begin
if (A == B) EQ = 1;
else EQ = 0;
end
endmodule
| 7.149439 |
module flop_1bit (
x,
y,
clk,
rst_n
);
input rst_n, clk;
input x;
output reg y;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) y <= 0;
else y <= x;
end
endmodule
| 7.349013 |
module flop_1bit_with_stall (
clk,
x,
y,
rst_n,
stall
);
input clk, x, rst_n, stall;
output reg y;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) y <= 0;
else if (stall) y <= y;
else y <= x;
end
endmodule
| 7.411333 |
module OneBitFullAdder (
in1,
in2,
out,
cout
);
input wire in1;
input wire in2;
output wire out;
output wire cout;
assign {cout, out} = in1 + in2;
endmodule
| 8.425088 |
module FullAdder (
a,
b,
cin,
s,
cout
);
// 3C7 LabD 2010
// a and b are the bits to add
// cin is carry in
input wire a, b, cin;
// s is the sum of a and b. cout is any carry out bit
// wires since just using assign here
output wire s, cout;
// logic for sum and carry
assign s =... | 7.610141 |
module fullsubtractor1 (
output diff,
bout,
input a,
b,
bin
);
//methodology: data flow modeling
assign diff = a ^ b ^ bin;
assign bout = ~a & (b ^ bin) | b & bin;
endmodule
| 6.741456 |
module fullsubtractor1_tb;
wire diff, bout;
reg a, b, bin;
fullsubtractor1 Instance0 (
diff,
bout,
a,
b,
bin
);
initial begin
a = 0;
b = 0;
bin = 0;
#20 a = 0;
b = 0;
bin = 1;
#20 a = 0;
b = 1;
bin = 0;
#20 a = 0;
b = 1;
... | 6.741456 |
module fullsubtractor1 (
output diff,
bout,
input a,
b,
bin
);
xor a1 (diff, a, b, bin);
and a2 (w1, ~a, b);
and a3 (w2, ~a, bin);
and a4 (w3, b, bin);
or a5 (bout, w1, w2, w3);
endmodule
| 6.741456 |
module fullsubtractor1_tb ();
wire diff;
wire bout;
reg a, b;
reg bin;
fullsubtractor1 m1 (
diff,
bout,
a,
b,
bin
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
a = 0;
b = 0;
bin = 0;
#20 a = 0;
b = 0;
bin = 1;
#20 a = 0... | 6.741456 |
module xnor_gate
// I/O ports
(
input wire i0,
i1,
output wire op
);
// signal declaration
wire p0, p1;
// body
// sum of two product terms
assign op = p0 | p1;
// product terms
assign p0 = ~i0 & ~i1;
assign p1 = i0 & i1;
endmodule
| 7.843367 |
module clk_div3 (
clk,
reset,
clk_out
);
input clk;
input reset;
output clk_out;
reg [1:0] pos_count, neg_count;
wire [1:0] r_nxt;
always @(posedge clk)
if (reset) pos_count <= 0;
else if (pos_count == 2) pos_count <= 0;
else pos_count <= pos_count + 1;
always @(negedge clk)
... | 6.961143 |
module clk_divn #(
parameter WIDTH = 3,
parameter N = 5
) (
clk,
reset,
clk_out
);
input clk;
input reset;
output clk_out;
reg [WIDTH-1:0] pos_count, neg_count;
wire [WIDTH-1:0] r_nxt;
always @(posedge clk)
if (reset) pos_count <= 0;
else if (pos_count == N - 1) pos_count <= 0... | 7.317272 |
module time_adv_half #(
parameter M = 2,
WIDTH = 7 //3.5*2
) (
input clk,
input rst,
output reg clk_out
);
wire clk_cnt;
assign clk_cnt = (clk_vld) ? !clk : clk;
reg [WIDTH : 0] counter;
always @(posedge clk_cnt or posedge rst) begin
if (rst) begin
// reset
counter <= 0;
... | 6.726844 |
module butterfly (
input clock,
input signed [15:0] x1,
input signed [15:0] y1,
input signed [15:0] x2,
input signed [15:0] y2,
input signed [31:0] zangle,
output signed [15:0] xout1,
output signed [15:0] yout1,
output signed [15:0] xout2,
output signed [15:0] yout2
);
// Temp... | 7.77208 |
module cordic (
input clock,
input signed [15:0] xstart,
input signed [15:0] ystart,
input signed [31:0] zangle,
output signed [15:0] xout,
output signed [15:0] yout,
output reg done
);
reg znext;
wire signed [31:0] atan_table[0:15];
assign atan_table[00] = 'b0010000000000000000000... | 6.912729 |
module fa_1 (
A,
B,
C,
S,
Cout
);
input [3:0] A;
input [3:0] B;
input C;
output [3:0] S, Cout;
reg S;
reg Cout;
always @(A or B or C) begin
{Cout, S} = A + B + C;
end
endmodule
| 7.561253 |
module fa_1 (
A,
B,
C,
S,
Cout
);
input A, B, C;
output S, Cout;
reg S, Cout;
always @(A or B or C) begin
if ((A == B && B != C && A == 1'b1) ||
(A == C && C != B && A == 1'b1) ||
(B == C && A != B && B == 1'b1))
begin
S = 0;
Cout = 1;
end
e... | 7.561253 |
module t1 (N1,N2,N3,N4,N5,N6,N7,N19,N21,N23);
input N1,N2,N3,N4,N5,N6,N7;
output N19,N21,N23;
N16 = NAND(N1, N2)
N19 = NOR(N16, N3)
N21 = NAND(N4, N5)
N23 = NOR(N6, N7)
endmodule
| 7.526928 |
module tri_mode_ethernet_mac_0_reset_sync #(
parameter INITIALISE = 1'b1,
parameter DEPTH = 5
) (
input reset_in,
input clk,
input enable,
output reset_out
);
wire reset_sync_reg0;
wire reset_sync_reg1;
wire reset_sync_reg2;
wire reset_sync_reg3;
wire reset_sync_reg4;
(* ASYNC_... | 6.950534 |
module tri_mode_ethernet_mac_0_sync_block #(
parameter INITIALISE = 1'b0,
parameter DEPTH = 5
) (
input clk, // clock to be sync'ed to
input data_in, // Data to be 'synced'
output data_out // synced data
);
// Internal Signals
wire data_sync0;
wire data_sync1;
wire data_sync2;
wi... | 6.950534 |
module first_register (
input clk,
input rst,
input StallD,
input FlushD,
input [31:0] instruction,
input [31:0] PCF,
input [31:0] PCPlus4F,
output reg [31:0] instrD,
output reg [31:0] PCD,
output reg [31:0] PCPlus4D
... | 7.889146 |
module Mem_1por2 (
output [1:0] saida,
input [1:0] entrada,
input clk,
input addr,
input rw,
input clr
);
Mem_1por1 MEM1 (
saida[0],
entrada[0],
clk,
addr,
rw,
clr
);
Mem_1por1 MEM2 (
saida[1],
entrada[1],
clk,
addr,
rw,
... | 6.819471 |
module Mem_1por4 (
output [3:0] saida,
input [3:0] entrada,
input clk,
input addr,
input rw,
input clr
);
Mem_1por2 MEM1 (
saida[1:0],
entrada[1:0],
clk,
addr,
rw,
clr
);
Mem_1por2 MEM2 (
saida[3:2],
entrada[3:2],
clk,
addr,
... | 6.891837 |
module test_Mem_1por4;
// ------------------------- definir dados
reg [3:0] entrada;
reg clk;
reg addr;
reg rw;
reg clr;
wire [3:0] saida;
// ------------------------- instancia
Mem_1por4 modulo (
saida,
entrada,
clk,
addr,
rw,
clr
);
// -----------------... | 7.603961 |
module teste1por8;
reg entrada[0:7], clk, rw, addr, clear;
wire saida[0:7], q[0:7], qnot[0:7], clk_s;
and and0 (clk_s, clk, rw, addr);
jkff jk1 (
q[0],
qnot[0],
entrada[0],
entrada[0],
clk_s
);
jkff jk2 (
q[1],
qnot[0],
entrada[1],
entrada[1],
cl... | 6.520574 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = (~{full[4:1], full[5]});
always @(posedge clk) begin
if (rst) full <= 'b010000;
els... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = '0;
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = '1;
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[... | 6.868788 |
module onebitALU (
y,
z,
a,
b,
cin,
c0,
c1
);
output y, z;
input a, b, cin, c0, c1;
wire y1, y2, y3;
wire cout, z1, z2;
wire w1, w2, w3;
fullAdder f1 (
y1,
cout,
a,
b,
cin
);
and a1 (y2, a, b);
not n1 (y3, a);
xor x1 (w1, a, b);
and a2 (w2... | 8.545363 |
module is scalable and suitable for
// expansion.
//
// Licence: These project have been published for
// academic use only under GPLv3 License.
// Copyright 2018
// All Rights Reserved
///////////////////////////////////////////////////////... | 6.736964 |
module BitonicPosStage1 #(
parameter W = 16
) (
//INPUT
//input clk, rst,
input direction,
input [(2*W)-1:0] IN,
//OUTPUT
output [(2*W)-1:0] OUT
);
Comparator #(W) COM_1 (
//.clk(clk), .rst(rst),
.direction(direction),
.IN1(IN[W-1:0]),
.IN2(IN[2*W-1:W]),
.OU... | 6.628381 |
module.
//
// Licence: These project have been published for
// academic use only under GPLv3 License.
// Copyright 2018
// All Rights Reserved
///////////////////////////////////////////////////////////
module BitonicPosStage2 #( parameter W = 16)(
//INP... | 7.081424 |
module.
//
// Licence: These project have been published for
// academic use only under GPLv3 License.
// Copyright 2018
// All Rights Reserved
///////////////////////////////////////////////////////////
module BitonicPosStage3 #( parameter W = 16)(
//INP... | 7.081424 |
module BitonicPreStage #(
parameter NUM = 16,
W = 16
) (
//INPUT
//input clk, rst,
input direction,
input [(NUM*W)-1 : 0] IN,
//OUTPUT
output [(NUM*W)-1 : 0] OUT
);
genvar i;
generate
for (i = 0; i < NUM / 2; i = i + 1) begin : PreStage_
Comparator #(W) COM_ (
/... | 6.509421 |
module one_bit_full_adder (
a,
b,
cin,
opcode,
sum,
carry
);
input a;
input b;
input cin;
input opcode;
output wire sum;
output wire carry;
assign sum = cin ^ (a ^ (b ^ opcode));
assign carry = ((a & (b ^ opcode)) | ((b ^ opcode) & cin) | (cin & a));
endmodule
| 6.938543 |
module fulladder1 (
output sum,
cout,
input a,
b,
cin
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | ((a ^ b) & cin);
endmodule
| 6.715059 |
module fulladder1_tb ();
reg a, b;
reg cin;
wire sum;
wire cout;
fulladder1 instance0 (
sum,
cout,
a,
b,
cin
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
a = 0;
b = 0;
cin = 0;
#20 a = 0;
b = 0;
cin = 1;
#20 a = 0;
... | 7.232581 |
module fulladder1 (
output sum,
cout,
input a,
b,
cin
);
xor a1 (sum, a, b, cin);
and a2 (w1, a, b);
and a3 (w2, b, cin);
and a4 (w3, a, cin);
or a5 (cout, w1, w2, w3);
endmodule
| 6.715059 |
module fulladder1_tb ();
wire sum;
wire cout;
reg a, b;
reg cin;
fulladder1 m1 (
sum,
cout,
a,
b,
cin
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
a = 0;
b = 0;
cin = 0;
#20 a = 0;
b = 0;
cin = 1;
#20 a = 0;
b = ... | 7.232581 |
module halfadder1 (
output sum,
carry,
input a,
b
);
assign sum = a ^ b;
assign carry = a & b;
endmodule
| 6.995975 |
module halfadder1_tb ();
reg a, b;
wire sum;
wire carry;
halfadder1 m1 (
sum,
carry,
a,
b
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
a = 0;
b = 0;
#20 a = 1;
b = 0;
#20 a = 0;
b = 1;
#20 a = 1;
b = 1;
#30 $stop;
end
end... | 6.803674 |
module halfadder1 (
output sum,
carry,
input a,
b
);
xor a1 (sum, a, b);
and a2 (carry, a, b);
endmodule
| 6.995975 |
module halfadder1_tb ();
wire sum;
wire carry;
reg a, b;
halfadder1 m1 (
sum,
carry,
a,
b
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
a = 0;
b = 0;
#20 a = 1;
b = 0;
#20 a = 0;
b = 1;
#20 a = 1;
b = 1;
#30 $stop;
end
end... | 6.803674 |
module of RTHS design, you can find description about this module from paper below.
// ("RTHS: A Low-Cost High-Performance Real-Time Hardware Sorter, Using
// a Multidimensional Sorting Algorithm", doi: 10.1109/TVLSI.2019.2912554)
//
// Licence: These project have been publis... | 8.47808 |
module multiplier_8x2 (
input [1:0] W, // signed or unsigned
input [7:0] A, // signed
input mode, // if 1, regards w as signed, else unsigned
output [9:0] Result
);
wire [7:0] W_01A, notA, temp, W_10A;
assign W_01A = {8{W[0]}} & A;
assign notA = ~A;
genvar i;
for (i = 0... | 7.064293 |
module MUX_2 (
input A,
B,
sel,
output O
);
wire asp, bs, notsel;
not (notsel, sel);
nand (asp, A, notsel);
nand (bs, B, sel);
nand (O, asp, bs);
endmodule
| 6.660624 |
module signExtender (
I,
O
); // size bit 신호 I를 extsize bit 신호 O로 sign extension
parameter size = 10;
parameter extsize = 12;
input [size-1:0] I;
output [extsize-1:0] O;
assign O = {{(extsize - size) {I[size-1]}}, {I}};
endmodule
| 7.592923 |
module ADDER (
op1,
op2,
cin,
res
); // without carry out
parameter size = 12;
input [size-1:0] op1, op2;
input cin;
output [size-1:0] res;
wire [size:0] C;
genvar i;
assign C[0] = cin;
generate
for (i = 0; i < size; i = i + 1) begin
fullAdder FAwoc (
.A (op1[i]),
... | 7.255631 |
module ADDERc (
op1,
op2,
cin,
res,
cout
); // with carry out
parameter size = 12;
input [size-1:0] op1, op2;
input cin;
output [size-1:0] res;
output cout;
wire [size:0] C;
genvar i;
assign C[0] = cin;
assign cout = C[size];
generate
for (i = 0; i < size; i = i + 1) begin... | 6.952629 |
module Insertion_block #(
parameter W = 41,
N = 64
) (
input clk,
rst,
input subtract,
input rd,
input wr,
input [W-2:0] data_in,
input repair_period,
output [W-2:0] data_out,
output empty,
output [W-2:0] data_fail,
output fail
);
integer RP_rd = 0;
wire [N:0]... | 6.929352 |
module Insertion_cell #(
parameter W = 41
) (
input clk,
rst,
input subtract,
input wr,
input rd,
input [W-2:0] data_in,
input [W-1:0] data_in_pre, // data from previous cell
output reg [W-1:0] data_reg,
output reg [W-2:0] data_out, // replacement with oldest data_reg or send ... | 6.692141 |
module gates (
a,
b,
not_op,
and_op,
nand_op,
or_op,
nor_op,
xor_op,
xnor_op
);
input a, b;
output not_op, and_op, nand_op, or_op, nor_op, xor_op, xnor_op;
assign not_op = ~(a);
assign and_op = a & b;
assign nand_op = ~(a & b);
assign or_op = a | b;
assign nor_op ... | 7.748371 |
module test;
wire not_op, and_op, nand_op, or_op, nor_op, xor_op, xnor_op;
reg a = 1'b0, b = 1'b0;
gates g1 (
a,
b,
not_op,
and_op,
nand_op,
or_op,
nor_op,
xor_op,
xnor_op
);
initial begin
$dumpfile("1_logicgates_test.vcd");
$dumpvars(0, test);
... | 6.964054 |
module m1 (
A,
B,
C,
D,
E,
F,
G,
H,
I
);
input A, B;
output C, D, E, F, G, H, I;
assign C = A & B;
assign D = A | B;
assign E = A ^ B;
assign F = ~(A & B);
assign G = ~(A | B);
assign H = ~(A ^ B);
assign I = ~A;
endmodule
| 6.520877 |
module top_module (
input [99:0] a,
b,
input sel,
output [99:0] out
);
assign out = sel ? b : a;
endmodule
| 7.203305 |
module top_module (
input clk,
input [7:0] d,
output [7:0] q
);
always @(posedge clk) begin
q <= d;
end
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
//connect module by position
mod_a inst_1 (
out1,
out2,
a,
b,
c,
d
);
endmodule
| 7.203305 |
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 4'd0;
else if (q == 4'd9) q <= 4'd0;
else q <= q + 4'd1;
end
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = (c | !d | !b) & (!a | !b | c) & (a | b | !c | !d) & (!a | !c | d);
endmodule
| 7.203305 |
module top_module (
input a,
b,
cin,
output cout,
sum
);
assign cout = a & b | b & cin | a & cin;
assign sum = a ^ b ^ cin;
endmodule
| 7.203305 |
module top_module (
output out
);
assign out = 1'b0;
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
output out
); //
wire con;
andgate inst1 (
con,
a,
b,
c,
1'b1,
1'b1
);
assign out = ~con;
endmodule
| 7.203305 |
module top_module (
input [7:0] in,
output parity
);
//even parity is calculated by XOR ing all the data bits
assign parity = ^in;
endmodule
| 7.203305 |
module top_module (
input wire [15:0] in,
output wire [ 7:0] out_hi,
output wire [ 7:0] out_lo
);
//The unpacked dimensions are declared after the name. They are generally used to declare memory arrays.
//reg [7:0] mem [255:0]; // 256 unpacked elements, each of which is a 8-bit packed vector of reg.... | 7.203305 |
module bldc_motorDriver_2ch (
clk,
en_ch1,
en_ch2,
freq_adj_ch1,
freq_adj_ch2,
out_p1_ch1,
out_p1_inv_ch1,
out_p2_ch1,
out_p2_inv_ch1,
out_p3_ch1,
out_p3_inv_ch1,
out_p1_ch2,
out_p1_inv_ch2,
out_p2_ch2,
out_p2_inv_ch2,
out_p3_ch2,
out_p3_inv_ch2
);
... | 7.354324 |
module Three_phase_sin (
clk,
en,
out_p1,
out_p1_inv,
out_p2,
out_p2_inv,
out_p3,
out_p3_inv,
freq_adj
);
input clk, en;
input [3:0] freq_adj;
output out_p1, out_p1_inv, out_p2, out_p2_inv, out_p3, out_p3_inv;
wire [7:0] duty_cycle_1;
wire [7:0] duty_cycle_2;
wire [7:0] ... | 7.248268 |
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