code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_Pip20CLA ();
reg clk = 0;
reg [19:0] a, b;
reg cin;
wire [19:0] s;
wire cout;
Pip20CLA Pip20CLA0 (
a,
b,
cin,
clk,
s,
cout
);
always #5 clk = ~clk;
initial begin
a = 20'b0000_0110_1111_0111_0111;
b = 20'b0000_0111_0001_0111_1000;
cin = 0... | 6.647245 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module used to extend the width of the pulse
//author:WangFW
//date:2020-5-29
module extend(clk,rst_n,din,dout);
input clk;
input rst_n;
input din;
output reg dout;
reg d1;
reg d2;
reg d3;
reg d4;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
d1<=1'b0;
d2<=1'b0;
d3<=1... | 6.976744 |
module top_module (
input clk,
input reset, // Synchronous reset
input in,
output disc,
output flag,
output err
);
parameter NONE = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4;
parameter S5 = 5, S6 = 6, DISCARD = 7, FLAG = 8, ERROR = 9;
reg [3:0] cstate, nstate;
always @(posedge clk) begin
... | 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a(
out1, out2, a, b, c, d
);
endmodule
| 7.203305 |
module part_2147 (
A0,
A1,
A2,
A3,
A4,
A5,
A6,
A7,
A8,
A9,
A10,
A11,
CE_N,
WE_N,
DI,
DO
);
input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11;
input CE_N, WE_N, DI;
output DO;
reg memory[0:4096];
initial begin
memory[0] <= 0;
end
... | 7.37652 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module drink_machine (
clk,
rst_n,
coin,
drink,
back
);
input clk;
input rst_n;
input [1:0] coin;
output reg drink;
output reg [1:0] back;
parameter init = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100;
parameter coin_5 = 2'b01, coin_10 = 2'b10;
reg [2:0] state;
reg... | 6.79605 |
module drink_machine_tb ();
reg clk;
reg rst_n;
//reg load;
reg [1:0] coin;
wire drink;
wire [1:0] back;
initial begin
clk = 0;
rst_n = 1;
coin = 2'b00;
#10 rst_n = 0;
#10 rst_n = 1;
//init---s2---s3
#5 coin = 2'b01;
#5 coin = 2'b00;
#5 coin = 2'b01;
#5 coin = ... | 6.79605 |
module top_module (
input clk,
input aresetn, // Asynchronous active-low reset
input x,
output z
);
parameter S0 = 0, S1 = 1, S2 = 2;
reg [1:0] cstate, nstate;
always @(posedge clk or negedge aresetn) begin
if (!aresetn) begin
cstate <= S0;
end else begin
cstate <= nstate... | 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a(
.out1(out1), .out2(out2), .in1(a), .in2(b), .in3(c), .in4(d)
);
endmodule
| 7.203305 |
module lpm_constant (
result // Value specified by the argument to LPM_CVALUE. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the result[] port. (Required)
parameter lpm_cvalue = 0; // Constant value to be driven out on the
// result[] port... | 6.780056 |
module lpm_and (
data, // Data input to the AND gate. (Required)
result // Result of the AND operators. (Required)
);
// GLOBAL PARAMETER DECLARATION
// Width of the data[][] and result[] ports. Number of AND gates. (Required)
parameter lpm_width = 1;
// Number of inputs to each AND gate. Number of i... | 7.013581 |
module lpm_or (
data, // Data input to the OR gates. (Required)
result // Result of OR operators. (Required)
);
// GLOBAL PARAMETER DECLARATION
// Width of the data[] and result[] ports. Number of OR gates. (Required)
parameter lpm_width = 1;
// Number of inputs to each OR gate. Number of input buses... | 6.857827 |
module lpm_bustri (
tridata, // Bidirectional bus signal. (Required)
data, // Data input to the tridata[] bus. (Required)
enabletr, // If high, enables tridata[] onto the result bus.
enabledt, // If high, enables data onto the tridata[] bus.
result // Output from the tridata[] bus.
);
// GLO... | 8.412317 |
module lpm_decode (
data, // Data input. Treated as an unsigned binary encoded number. (Required)
enable, // Enable. All outputs low when not active.
clock, // Clock for pipelined usage.
aclr, // Asynchronous clear for pipelined usage.
clken, // Clock enable for pipelined usage.
eq // Deco... | 7.18043 |
module lpm_latch (
data, // Data input to the latch.
gate, // Latch enable input. High = flow-through, low = latch. (Required)
aclr, // Asynchronous clear input.
aset, // Asynchronous set input.
aconst,
q // Data output from the latch.
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_w... | 7.559436 |
module lpm_fifo_dc_dffpipe (
d,
clock,
aclr,
q
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_delay = 1;
parameter lpm_width = 64;
// INPUT PORT DECLARATION
input [lpm_width-1:0] d;
input clock;
input aclr;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
// INTERNAL REGIST... | 7.553269 |
module lpm_fifo_dc (
data,
rdclock,
wrclock,
aclr,
rdreq,
wrreq,
rdfull,
wrfull,
rdempty,
wrempty,
rdusedw,
wrusedw,
q
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_widthu = 1;
parameter lpm_numwords = 2;
parameter lpm_showahead ... | 7.282858 |
module lpm_outpad (
data,
pad
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_type = "lpm_outpad";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] pad;
// INTERNAL REGISTER/S... | 6.730452 |
module count4 (
q,
data,
clock,
clk_en,
cnt_en,
updown,
sset,
sclr,
sload
);
parameter lpm_width = 4;
output [lpm_width-1:0] q;
input [lpm_width-1:0] data;
input clock, clk_en, cnt_en, updown;
input sset, sclr, sload;
lpm_counter U1 (
.q(q),
.data(data),
... | 7.148055 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module div_odd (
clk,
rst_n,
clkout
);
input clk;
input rst_n;
output clkout;
reg pos_clk;
reg neg_clk;
reg [2:0] count1;
reg [2:0] count2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
count1 <= 3'd0;
pos_clk <= 1'b0;
end else begin
if (count1 ... | 6.538557 |
module div_odd_tb ();
reg clk;
reg rst_n;
wire clkout;
initial begin
clk = 0;
rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;
end
always #2 clk <= ~clk;
div_odd test (
.clk(clk),
.rst_n(rst_n),
.clkout(clkout)
);
endmodule
| 7.170528 |
module top_module (
input clk,
input areset,
input x,
output z
);
parameter IDLE = 0, S0 = 1, S1 = 2, S2 = 3;
reg [1:0] cstate, nstate;
always @(posedge clk or posedge areset) begin
if (areset) begin
cstate <= IDLE;
end else begin
cstate <= nstate;
end
end
always ... | 7.203305 |
module top_module (
input clk,
input d,
output q
);
wire q_1;
wire q_2;
my_dff u_my_dff_1 (
.clk(clk),
.d (d),
.q (q_1)
);
my_dff u_my_dff_2 (
.clk(clk),
.d (q_1),
.q (q_2)
);
my_dff u_my_dff_3 (
.clk(clk),
.d (q_2),
.q (q)
);
e... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input areset,
input x,
output z
);
parameter A = 0, B = 1;
reg [1:0] cstate, nstate;
always @(posedge clk or posedge areset) begin
if (areset) begin
cstate <= A;
end else begin
cstate <= nstate;
end
end
always @(*) begin
case (cs... | 7.203305 |
module seqdet (
clk,
rst_n,
x,
flag
);
input clk;
input rst_n;
input x;
output reg flag;
parameter idle=3'b000,s1=3'b001,s2=3'b010,s3=3'b011,s4=3'b100,s5=3'b101,s6=3'b110;
reg [2:0] state;
reg [2:0] next_state;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
s... | 7.387939 |
module seqdet_tb ();
reg clk, rst_n;
reg [23:0] data;
wire flag, x;
assign x = data[23];
initial begin
clk = 0;
rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;
data = 24'b1011_0101_1011_0101_0100_0101;
end
always #2 clk = ~clk;
always @(posedge clk) begin
data = {data[22:0], data[23]}... | 6.662055 |
module top_module (
input clk,
input [7:0] d,
input [1:0] sel,
output [7:0] q
);
wire [7:0] q1;
wire [7:0] q2;
wire [7:0] q3;
my_dff8 u_my_dff8_1 (
.clk(clk),
.d (d),
.q (q1)
);
my_dff8 u_my_dff8_2 (
.clk(clk),
.d (q1),
.q (q2)
);
my_dff8 u_my_dff... | 7.203305 |
module scorecounter (
clock,
resetwire,
HEX0,
HEX1,
HEX2,
scorecount
);
input resetwire, clock;
output [6:0] HEX0, HEX1, HEX2;
reg [3:0] hexconvert0, hexconvert1, hexconvert2;
input [9:0] scorecount;
initial begin
hexconvert0 = 0;
hexconvert1 = 0;
hexconvert2 = 0;
end
... | 6.690009 |
module enablercount (
CLOCK_50,
reset,
enable,
divider,
enabledelay1,
enabledelay2,
enabledelay3,
enabledelay4,
enabledelay5
);
input CLOCK_50, reset;
input [2:0] divider;
output reg enable;
output reg enabledelay1;
output reg enabledelay2;
output reg enabledelay3;
outp... | 6.922756 |
module modulox (
xpositionW,
is0,
enable,
CLOCK_50
);
input [7:0] xpositionW;
input CLOCK_50;
input enable;
output reg is0;
always @(CLOCK_50)
if (enable == 1'b1)
if (xpositionW % 10 == 0) is0 = 1;
else is0 = 0;
endmodule
| 6.994745 |
module PS2_Demo (
// Inputs
CLOCK_50,
KEY,
// Bidirectionals
PS2_CLK,
PS2_DAT,
// Outputs
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7
);
/*****************************************************************************
* Paramet... | 8.682108 |
module mux (
a,
b,
s,
o
);
input a;
input b;
input s;
output o;
assign o = (s == 0) ? b : a;
endmodule
| 8.268895 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input reset, // Synchronous reset
input s,
input w,
output z
);
parameter A = 0, B = 1;
reg cstate, nstate;
reg [1:0] cnt;
reg cnt_end;
reg [1:0] w_cnt;
assign z = cnt_end;
always @(posedge clk) begin
if (reset) begin
cstate <= A;
en... | 7.203305 |
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire cout_lo;
wire [15:0] sum_lo;
wire [15:0] sum_hi;
wire cout;
wire cin_lo;
add16 add16_lo (
.a({a[15:0]}),
.b({b[15:0]}),
.cin(cin_lo),
.sum(sum_lo),
.cout(cout_lo)
);
add16 add16_hi ... | 7.203305 |
module top_module (
input [1023:0] in,
input [7:0] sel,
output [3:0] out
);
// We can't part-select multiple bits without an error, but we can select one bit at a time,
// four times, then concatenate them together.
assign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]};
endmodule
| 7.203305 |
module top_module (
input [1023:0] in,
input [7:0] sel,
output [3:0] out
);
assign out = in[4*sel+:4];
endmodule
| 7.203305 |
module top_module (
input [255:0] in,
input [7:0] sel,
output out
);
assign out = in[sel];
endmodule
| 7.203305 |
module SRAM (
dat_in,
addr_in,
w_en,
clk,
read_d
);
input wire [3:0] dat_in;
input wire [7:0] addr_in;
input wire w_en, clk;
output wire [3:0] read_d;
/* Declare the RAM variable */
reg [3:0] ram[255:0];
/* Variable to hold the registered read address */
reg [7:0] addr_reg = 8'b0000... | 7.472043 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input reset, // Synchronous reset
input x,
output z
);
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
reg [2:0] cstate, nstate;
always @(posedge clk) begin
if (reset) begin
c... | 7.203305 |
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
); //
wire cin1, cout1, cout2;
wire [15:0] sum1, sum2;
assign cin1 = 0;
add16 u_add16_0 (
.a(a[15:0]),
.b(b[15:0]),
.cin(cin1),
.sum(sum1),
.cout(cout1)
);
add16 u_add16_1 (
.a(a[31:16... | 7.203305 |
module add1 (
input a,
input b,
input cin,
output sum,
output cout
);
// Full adder module here
assign sum = a ^ b ^ cin;
assign cout = a & b | (a ^ b) & cin;
endmodule
| 6.640243 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module a_s_reset (
clk,
rst_n,
din,
dout
);
input clk;
input rst_n;
input [7:0] din;
output reg [7:0] dout;
reg reg1, reg2;
wire reset;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
reg1 <= 1'b0;
reg2 <= 1'b0;
end else begin
reg1 <= rst_n;
... | 6.77581 |
module a_s_reset_tb ();
reg clk;
reg rst_n;
reg [7:0] din;
wire [7:0] dout;
initial begin
clk = 0;
rst_n = 1;
din = 8'b1010_1010;
#10 rst_n = 0;
#10 rst_n = 1;
end
always #2 clk <= ~clk;
a_s_reset dut (
.clk (clk),
.rst_n(rst_n),
.din (din),
.dout (do... | 6.887683 |
module top_module (
input clk,
input [2:0] y,
input x,
output Y0,
output z
);
always @(*) begin
case (y)
3'b000, 3'b010: Y0 = x;
default: Y0 = ~x;
endcase
end
assign z = (y == 3'b011 || y == 3'b100);
endmodule
| 7.203305 |
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire cin;
wire [15:0] sum1;
wire [15:0] sum2_0;
wire [15:0] sum2_1;
wire cout1, cout1_0, cout1_1;
wire cout2_0, cout2_1;
assign cin = 0;
assign cout1_0 = 0;
assign cout1_1 = 1;
add16 u_add16_1 (
.a(a[15:0... | 7.203305 |
module ALU (
sum,
cout,
a,
b,
cin,
ov
);
input [7:0] a;
input [7:0] b;
input cin;
output [7:0] sum;
output cout, ov;
wire cin7;
reg [7:0] d;
RCA_8 n1_inst (
sum,
cout,
a,
d,
cin,
cin7
);
assign ov = cout ^ cin7;
always @(*) begin
if ... | 6.859596 |
module RCA_8 (
sum,
cout,
a,
b,
cin,
cin7
);
output [7:0] sum;
output cout, cin7;
input [7:0] a, b;
input cin;
wire cin1, cin2, cin3, cin4, cin5, cin6;
add_full U1 (
sum[0],
cin1,
a[0],
b[0],
cin
);
add_full U2 (
sum[1],
cin2,
a[1],... | 6.550225 |
module add_full (
sum,
cout,
a,
b,
cin
);
input a, b, cin;
output cout, sum;
wire w1, w2, w3;
add_half U1 (
w1,
w2,
a,
b
);
add_half U2 (
sum,
w3,
cin,
w1
);
assign cout = w2 | w3;
endmodule
| 7.057721 |
module add_half (
sum,
cout,
a,
b
);
input a, b;
output cout, sum;
assign sum = a ^ b;
assign cout = a & b;
endmodule
| 7.260022 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module pre_adder (
mode,
dir,
a,
b,
c
);
input mode;
input dir;
input [26 : 0] a;
input [25 : 0] b;
input [26 : 0] c;
assign c = mode ? (dir ? a - b : a + b) : a;
endmodule
| 6.718407 |
module number_list (
clk,
rst_n,
dout
);
input clk;
input rst_n;
output dout;
reg [9:0] init;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) init <= 10'b0010_1101_11;
else init <= {init[8:0], init[9]};
end
assign dout = init[9];
endmodule
| 6.686257 |
module number_list_tb ();
reg clk;
reg rst_n;
wire dout;
initial begin
clk = 0;
rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;
end
always #2 clk <= ~clk;
number_list dut (
.clk (clk),
.rst_n(rst_n),
.dout (dout)
);
endmodule
| 6.831512 |
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