code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module top_module (
input [3:1] y,
input w,
output Y2
);
always @(*) begin
case (y)
3'b010, 3'b100: Y2 = w;
3'b000, 3'b011: Y2 = 0;
default: Y2 = 1;
endcase
end
endmodule
| 7.203305 |
module top_module (
input [31:0] a,
input [31:0] b,
input sub,
output [31:0] sum
);
wire cout1, cout2;
wire [15:0] b_lo;
wire [15:0] b_hi;
wire [15:0] sum_lo;
wire [15:0] sum_hi;
always @(a or b or sub) begin
if (sub == 0) begin
b_lo = b[15:0];
b_hi = b[31:16];
end else... | 7.203305 |
module CFIqueryModule (); //, isCFI);
//input isCFI;
reg [`BYTE_range] CFIarray[0:`CFI_dim];
reg error;
reg [8*30:1] CFI_file;
integer i;
initial begin
`ifdef x128P30T
CFI_file = "CFImemory_top.mem";
`elsif x128P30B
CFI_file = "CFImemory_bottom.mem";
`elsif x64P30T
CFI_file = "CFImemor... | 6.718754 |
module Erase
// *********************
//
// Memory Manager :
// the memory array
//
// *********************
module MemoryModule(Info);
input Info;
reg [`WORD_range] memory [0:(`MEMORY_dim) - 1]; // the Memory: word organization
parameter FILENAME_MEM="";
initial begin
LoadMemory;
end
task L... | 7.196549 |
module OutputBufferModule (
DataInput,
DataInputBurst,
DataOutput,
OutputEnable
);
input [`WORD_range] DataInput;
input [`WORD_range] DataInputBurst;
output [`WORD_range] DataOutput;
input OutputEnable;
reg [`WORD_range] DataOutput;
time timeDataV, timeDataX, timeDataZ;
initial begin
... | 6.818094 |
module ReadModule (
dataOutput,
address,
voltOK,
Info
);
output [`WORD_range] dataOutput;
input [`ADDRBUS_range] address;
input voltOK;
input Info;
reg [`WORD_range] dataOutput, regRead;
reg [1:0] Mode, oldMode;
reg [`BYTE_range] Status;
integer i;
initial begin
regRead = 0;
... | 6.789247 |
module BlankCheckModule(address, data, progVoltOK, progHighVoltOK,Info);
input [`WORD_range] data;
input [`ADDRBUS_range] address;
input progVoltOK, progHighVoltOK;
input Info;
event ErrorCheckEvent, CompleteEvent;
reg [`BYTE_range] Status;
reg [`ADDRBUS_range] hold_address;
reg [`BLOCKADDR_range] ... | 6.629661 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input [6:1] y,
input w,
output Y2,
output Y4
);
assign Y2 = y[1] && (~w);
assign Y4 = (y[2] || y[3] || y[5] || y[6]) && w;
endmodule
| 7.203305 |
module top_module (
input a,
input b,
output wire out_assign,
output reg out_alwaysblock
);
assign out_assign = a & b;
always @(*) begin
out_alwaysblock = a & b;
end
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module key_scan (
clk,
rst_n,
col,
row,
key_out
);
input clk; //10KHz
input rst_n;
input [3:0] col;
output reg [3:0] row;
output reg [15:0] key_out;
parameter s1 = 2'b00, s2 = 2'b01, s3 = 2'b10, s4 = 2'b11;
reg [1:0] state;
reg clk_200hz;
reg [4:0] cnt;
always @(posedge clk o... | 6.821826 |
module top_module (
input clk,
input reset, // synchronous reset
input w,
output z
);
parameter A = 3'b000;
parameter B = 3'b001;
parameter C = 3'b010;
parameter D = 3'b011;
parameter E = 3'b100;
parameter F = 3'b101;
reg [2:0] cstate, nstate;
always @(posedge clk) begin
if (r... | 7.203305 |
module decoder (
a,
y
);
input [1:0] a;
output [3:0] y;
reg [3:0] y = 4'b1111;
always @(a)
case (a)
2'b00: y = 4'b1110;
2'b01: y = 4'b1101;
2'b10: y = 4'b1011;
2'b11: y = 4'b0111;
endcase
endmodule
| 7.018254 |
module test;
wire [3:0] y;
reg [1:0] a = 2'b00;
decoder d1 (
a,
y
);
initial begin
$dumpfile("2a_decoder_test.vcd");
$dumpvars(0, test);
#5 a = 2'b01;
#5 a = 2'b10;
#5 a = 2'b11;
#5 $finish;
end
always @(a) $strobe("At time = (%0t) a = (%b),y = (%b)", $time, a, y);
... | 6.964054 |
module AND (
a,
b,
y
);
input a, b;
output y;
assign y = a & b;
endmodule
| 7.053445 |
module OR (
a,
b,
y
);
input a, b;
output y;
assign y = a | b;
endmodule
| 7.086775 |
module NOR (
a,
b,
y
);
input a, b;
output y;
assign y = ~(a | b);
endmodule
| 7.611112 |
module XOR (
a,
b,
y
);
input a, b;
output y;
assign y = (a ^ b);
endmodule
| 7.915029 |
module NOT (
a,
b
);
output b;
input a;
assign b = !a;
endmodule
| 7.483426 |
module comp (
input [6:0] A,
input [6:0] B,
output reg Q
);
wire [6:0] temp1;
wire [6:0] temp2;
//XOR x1(.A(A[7]),.B(B[7]),.Q(temp));
assign temp1[0] = A[0];
assign temp1[1] = A[1];
assign temp1[2] = A[2];
assign temp1[3] = A[3];
assign temp1[4] = A[4];
assign temp1[5] = A[5];
assign te... | 6.601597 |
module p_node (
input [7:0] LLR_C,
input [7:0] LLR_D,
input frozen1,
input frozen2,
output u2i_1,
output u2i
);
wire h, i, j, k, l, m, n, comp, o, p, q, r, s, t, u;
signum S1 (
.A(LLR_C),
.Q(h)
);
signum S2 (
.A(LLR_D),
.Q(i)
);
XOR X1 (
.a(h),
.b... | 7.849494 |
module Half_adder (
input p,
input q,
output S,
output C
);
assign C = p & q;
assign S = p ^ q;
endmodule
| 7.033118 |
module Full_adder (
input IN,
input IN2,
input Cin,
output R,
output Cout
);
wire x1;
wire y1;
wire z;
Half_adder Ha1 (
.p(IN),
.q(IN2),
.S(x1),
.C(y1)
);
Half_adder Ha2 (
.p(x1),
.q(Cin),
.S(R),
.C(z)
);
assign Cout = y1 | z;
endmod... | 7.225676 |
module Adder (
input [7:0] A,
input [7:0] B,
output [9:0] Q
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
Full_adder Fa0 (
.IN(A[0]),
.IN2(B[0]),
.Cin(0),
.R(Q[0]),
.Cout(w0)
);
Full_adder Fa1 (
.IN(A[1]),
.IN2(B[1]),
... | 7.642138 |
module Subtracter (
input [7:0] A,
input [7:0] B,
output [9:0] Q
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
Full_adder Fa0 (
.IN(A[0]),
.IN2(~B[0]),
.Cin(1),
.R(Q[0]),
.Cout(w0)
);
Full_adder Fa1 (
.IN(A[1]),
... | 6.986633 |
module FA_2 (
input [1:0] A,
input [1:0] B,
output [2:0] O
);
wire [2:0] Cout;
wire [1:0] S;
assign Cout[0] = 1'b0;
FA FA1 (
.A(A[0]),
.B(B[0]),
.Cin(Cout[0]),
.S(S[0]),
.Cout(Cout[1])
);
FA FA2 (
.A(A[1]),
.B(B[1]),
.Cin(Cout[1]),
.S(S... | 7.130943 |
module gr (
input wire [1:0] num0,
num1,
output wire gr
);
// signal declaration
wire p0, p1, p2;
// body - includes the logical expressions used and the final SOP form to achieve the desired result
assign gr = p0 | p1 | p2; // gr = p0 + p1 + p2
// = (A1.~B1) + (A0... | 7.314663 |
module bit2_less_than (
input wire [1:0] a,
b, // a and b are the two 2-bit numbers to compare
output wire alessb
);
wire aeqb;
wire agrb;
// body
// instantiate the result from the SOP of both
// 2 bit greater than comparator and
// 2 bit equality comparator
// and OR them to get the fina... | 6.705786 |
module encoder_8to3 (
a,
y
);
input [7:0] a;
output [2:0] y;
reg [2:0] y;
always @(a) begin
if (a == 8'b00000001) y = 3'b000;
else if (a == 8'b00000010) y = 3'b001;
else if (a == 8'b00000100) y = 3'b010;
else if (a == 8'b00001000) y = 3'b011;
else if (a == 8'b00010000) y = 3'b100;
... | 7.526774 |
module test;
wire [2:0] y;
reg [7:0] a;
encoder_8to3 e1 (
a,
y
);
initial begin
$dumpfile("2b_encoder_8to3_test.vcd");
$dumpvars(0, test);
#5 a = 8'b00000001;
#5 a = 8'b00000010;
#5 a = 8'b00000100;
#5 a = 8'b00001000;
#5 a = 8'b00010000;
#5 a = 8'b00100000;
... | 6.964054 |
module fulladder (
a,
b,
c,
carry,
sum
);
input a, b, c;
output carry, sum;
assign carry = a & b | a & c | b & c;
assign sum = a ^ b ^ c;
endmodule
| 7.454465 |
module encoder_8to3 (
a,
y
);
input [7:0] a;
output [2:0] y;
reg [2:0] y;
always @(a) begin
case (a)
8'b00000001: y = 3'b000;
8'b0000001x: y = 3'b001;
8'b000001xx: y = 3'b010;
8'b00001xxx: y = 3'b011;
8'b0001xxxx: y = 3'b100;
8'b001xxxxx: y = 3'b101;
8'b01x... | 7.526774 |
module test;
wire [2:0] y;
reg [7:0] a;
encoder_8to3 e1 (
a,
y
);
initial begin
$dumpfile("2c_priorityencoder_8to3_test.vcd");
$dumpvars(0, test);
#5 a = 8'b00000001;
#5 a = 8'b0000001x;
#5 a = 8'b000001xx;
#5 a = 8'b00001xxx;
#5 a = 8'b0001xxxx;
#5 a = 8'b001xx... | 6.964054 |
module test;
wire a;
reg [7:0] y = 8'd82;
reg [2:0] sel;
multiplexer_8to1 m1 (
a,
sel,
y
);
initial begin
$dumpfile("2d_multiplexer_8to1_test.vcd");
$dumpvars(0, test);
#5 sel = 3'b000;
#5 sel = 3'b001;
#5 sel = 3'b010;
#5 sel = 3'b011;
#5 sel = 3'b100;
#... | 6.964054 |
module test;
wire [3:0] y;
reg [3:0] a;
bintograyconv4bit bg1 (
a,
y
);
initial begin
$dumpfile("2e_4bit_binarytograyconverter.vcd");
$dumpvars(0, test);
#5 a = 4'd0;
#5 a = 4'd1;
#5 a = 4'd2;
#5 a = 4'd3;
#5 a = 4'd4;
#5 a = 4'd5;
#5 a = 4'd6;
#5 a = 4'... | 6.964054 |
module test;
wire [7:0] y;
reg a = 1'b1;
reg [2:0] sel;
demultiplexer1to8 d1 (
a,
sel,
y
);
initial begin
$dumpfile("2f_demultiplexer_1to8.vcd");
$dumpvars(0, test);
#5 sel = 3'd0;
#5 sel = 3'd1;
#5 sel = 3'd2;
#5 sel = 3'd3;
#5 sel = 3'd4;
#5 sel = 3'd5;... | 6.964054 |
module test;
wire l, e, g;
reg [3:0] a;
reg [3:0] b;
comparator c1 (
a,
b,
l,
e,
g
);
initial begin
$dumpfile("2g_comparator.vcd");
$dumpvars(0, test);
#5 begin
a = 4'b1111;
b = 4'b1100;
end
#5 begin
a = 4'b1111;
b = 4'b1111;
... | 6.964054 |
module mux2 (
in0,
in1,
select,
out
);
input in0, in1, select;
output out;
wire s0, w0, w1;
not n1 (s0, select);
and a1 (w0, s0, in0);
and a2 (w1, select, in1);
or g3 (out, w0, w1);
endmodule
| 7.816424 |
module tb_mux;
// Declaring Inputs
reg Data_in_0;
reg Data_in_1;
reg sel;
// Declaring Outputs
wire Data_out;
// Instantiate the Unit Under Test (UUT)
mux2 uut (
.in0(Data_in_0),
.in1(Data_in_1),
.select(sel),
.out(Data_out)
);
initial begin
//for creating vcd wav... | 7.600974 |
module mux1_2_4 (
A,
B,
sel,
Y
);
input [3:0] A;
input [3:0] B;
input sel;
output reg [3:0] Y;
always @(A, B, sel) begin
Y <= sel ? A : B;
end
endmodule
| 6.8861 |
module Second_register (
input [31:0] PCD,
input [31:0] ImmExtD,
input [31:0] PCPlus4D,
input [31:0] RD1,
input [31:0] RD2,
input [ 4:0] RdD,
input [ 4:0] Rs1D,
input [ 4:0] Rs2D,
input [ 2:0] funct3,
input rst,
input ... | 7.65325 |
module iob_2p_mem_tiled #(
parameter DATA_W = 32, // data width
parameter N_WORDS = 8192, // number of words (each word has 'DATA_W/8' bytes)
parameter ADDR_W = $clog2(N_WORDS * DATA_W / 8.0), // address width
parameter TILE_ADDR_W = 11, // log2 of block size
parameter USE_RAM = 0
) (
// Inp... | 6.757707 |
module decN #(
parameter N_OUTPUTS = 16
) (
input [$clog2(N_OUTPUTS)-1:0] dec_in,
output reg [N_OUTPUTS-1:0] dec_out
);
always @* begin
dec_out = 0;
dec_out[dec_in] = 1'b1;
end
endmodule
| 6.877415 |
module muxN #(
parameter N_INPUTS = 4, // number of inputs
parameter INPUT_W = 8, // input bit width
parameter S = $clog2(N_INPUTS), // number of select lines
parameter W = N_INPUTS * INPUT_W // total data width
) (
// Inputs
input [INPUT_W-1:0] data_in[N_INPUTS-1:0], // input port
inpu... | 8.176797 |
module iob_2p_mem_tiled_tb;
// Inputs
reg clk;
reg w_en;
reg r_en;
reg [`DATA_W-1:0] data_in;
reg [`ADDR_W-1:0] addr;
// Outputs
wire [`DATA_W-1:0] data_out;
integer i, seq_ini;
integer test, base_block;
parameter clk_per = 10; // clk period = 10 timeticks
// Instantiate the Unit Under Tes... | 6.757707 |
module comp (
input [31:0] inp,
output [31:0] out
);
wire [31:0] o1;
wire carry;
assign o1[31:0] = ~(inp[31:0]);
thirtytwoBitAdder a1 (
o1,
32'd1,
1'b0,
out,
carry
);
endmodule
| 6.601597 |
module pipe_2stage_data (
out,
in,
clk
);
input [29:0] in;
input clk;
output reg [29:0] out;
reg [29:0] pipe1, pipe2, pipe3, pipe4;
always @(posedge clk) begin
pipe1 <= in;
pipe2 <= pipe1;
pipe3 <= pipe2;
pipe4 <= pipe3;
out <= pipe4;
end
endmodule
| 6.738391 |
module simon2share (
clk,
data_ina,
data_inb,
data_rdy,
cipher_out,
Done,
Trig
);
input clk;
input data_ina, data_inb;
input [1:0] data_rdy;
output [127:0] cipher_out;
output reg Done, Trig;
reg [7:0] counter;
wire [63:0] keya, keyb;
always @(posedge clk) begin
if (dat... | 6.990502 |
module data_share2 (
clk,
data_rdy,
counter,
data_in,
key_in,
X_out,
Y_out,
Y_in
);
input clk, counter, data_in;
input [63:0] key_in;
input [1:0] data_rdy;
input [63:0] Y_in;
output [63:0] X_out, Y_out;
reg [63:0] X, Y;
wire [63:0] XL1_1, XL2_1, XL8_1;
assign XL1_1 = {X... | 7.29868 |
module quick_mux_128 (
in1,
in2,
out,
sel
);
input [127:0] in1, in2;
input sel;
output [127:0] out;
assign out = sel ? (in1) : in2;
endmodule
| 7.428361 |
module p_keysch10 (
clk,
counter,
data_in,
data_rdy,
key_out
);
input clk, data_in;
input [1:0] data_rdy;
input [7:0] counter;
output [63:0] key_out;
reg [63:0] KX, KY;
reg [0:67] Z = 68'b10101111011100000011010010011000101000010001111110010110110011101011;
reg [63:0] c = 64'hffffffff... | 6.723774 |
module p_keysch11 (
clk,
counter,
data_in,
data_rdy,
key_out
);
input clk, data_in;
input [1:0] data_rdy;
input [7:0] counter;
output [63:0] key_out;
reg [63:0] KX, KY;
always @(posedge clk) begin
if (data_rdy == 2) begin
{KX, KY} <= {data_in, KX, KY[63:1]};
end else if (... | 6.688182 |
module and4 (
a1,
a2,
andout
);
input [3:0] a1, a2;
output [3:0] andout;
assign andout = a1 & a2;
endmodule
| 7.593419 |
module MUX2to1 (
In0,
In1,
Sel,
Out
);
input In0, In1, Sel;
output Out;
assign Out = (Sel) ? In1 : In0;
endmodule
| 7.21075 |
module toMod (
output [7:0] Pos,
input [7:0] A
);
assign Pos = (A[7] ? ~A + 1 : A);
endmodule
| 6.963467 |
module TwoXOneMUX (
input A,
B,
S,
output reg C
);
always @(*) begin
C = (A & ~S) | (S & B);
end
endmodule
| 7.48674 |
module 2x1(input a,b,s, output y);
wire r,w1,w2;
not(r,s);
and(w1,b,s);
and(w2,a,r);
or(y,w1,w2);
endmodule
| 6.775103 |
module adder (
a,
b,
s,
co
);
input a, b;
output s, co;
and (co, a, b);
xor (s, a, b);
endmodule
| 7.4694 |
module Mux (
output saida,
input entrada0,
input entrada1,
input chave
);
wire [1:0] s;
wire saida_not;
not NOT0 (saida_not, chave);
and AND0 (s[0], entrada0, saida_not);
and AND1 (s[1], entrada1, chave);
or OR0 (saida, s[0], s[1]);
endmodule
| 7.736456 |
module Demux (
output saida0,
output saida1,
input chave
);
wire saida_not;
not NOT0 (saida_not, chave);
and AND0 (saida0, 1, saida_not);
and AND1 (saida1, 1, chave);
endmodule
| 7.090619 |
module Mem_2por4 (
output [3:0] OUT0,
input [3:0] entrada,
input clk,
input addr,
input rw,
input clr
);
wire [1:0] s;
wire [3:0] saida0;
wire [3:0] saida1;
Demux demux0 (
s[0],
s[1],
addr
);
Mem_1por4 MEM1 (
saida0,
entrada,
clk,
s[0],
... | 6.523387 |
module test_Mem_2por4;
// ------------------------- definir dados
reg [3:0] entrada;
reg clk;
reg addr;
reg rw;
reg clr;
wire [3:0] saida;
// ------------------------- instancia
Mem_2por4 modulo (
saida,
entrada,
clk,
addr,
rw,
clr
);
// -----------------... | 7.504431 |
module 2x4decoder(input a,b output s,d,f,g);
assign s = ~a&~b;
assign d = ~a& b;
assign f = a&~b;
assign g = a& b;
endmodule
| 6.855172 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {(~full[4:1]), full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
els... | 6.868788 |
module mux2to1 (
out,
in1,
in2,
sel
);
input in1, in2, sel;
output out;
assign out = sel ? in2 : in1;
endmodule
| 7.107199 |
module MUX (
i,
s,
y
);
input [1:0] i;
input s;
output y;
reg y;
always @(s or i) begin
case (s)
1'b0: y = i[00];
1'b1: y = i[01];
default: y = 0;
endcase
end
endmodule
| 6.699278 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], (~full[5])};
always @(posedge clk) begin
if (rst) full <= 'b010000;
els... | 6.868788 |
module decoder (
en,
a,
b,
y
);
// input port
input en, a, b;
// use reg to store the output value
output reg [3:0] y;
// always is used in design block
// only in Behavioural modeling.
always @(en, a, b) begin
// using condition if statement
// implement the 2:4 truth table
... | 7.018254 |
module Arbiter_cell #(
parameter W = 4
) (
input clk,
input rst,
input [1:0] req,
input [2*(W-1)-1:0] grant,
output req_out,
output [W-1:0] grant_out
);
wire [1:0] op1, op2;
reg priority_;
assign op1[0] = ~priority_ | ~req[1];
assign op1[1] = priority_ | ~req[0];
assign op2[0] =... | 6.97395 |
module of RTHS design, you can find description about this module from paper below.
// ("RTHS: A Low-Cost High-Performance Real-Time Hardware Sorter, Using
// a Multidimensional Sorting Algorithm", doi: 10.1109/TVLSI.2019.2912554)
// In this module, one dimentional in... | 8.47808 |
module MAC_Unit (
input [7:0] Activation,
weight,
input clk,
rstn,
en,
input [1:0] ReducePrecLevel,
output reg [2:0] count,
output reg [15:0] PRODUCT,
output reg [19:0] RESULT
);
// counter part
always @(posedge clk, negedge rstn) begin
if (rstn == 0) count = 0;
else if ... | 6.805864 |
module MUX_2 (
input A,
B,
sel,
output O
);
wire asp, bs, notsel;
not (notsel, sel);
nand (asp, A, notsel);
nand (bs, B, sel);
nand (O, asp, bs);
endmodule
| 6.660624 |
module ADDERc (
op1,
op2,
cin,
res,
cout
); // with carry out
parameter size = 12;
input [size-1:0] op1, op2;
input cin;
output [size-1:0] res;
output cout;
wire [size:0] C;
genvar i;
assign C[0] = cin;
assign cout = C[size];
generate
for (i = 0; i < size; i = i + 1) begin... | 6.952629 |
module ADDER (
op1,
op2,
cin,
res
); // without carry out
parameter size = 12;
input [size-1:0] op1, op2;
input cin;
output [size-1:0] res;
wire [size:0] C;
genvar i;
assign C[0] = cin;
generate
for (i = 0; i < size; i = i + 1) begin
fullAdder FAwoc (
.A (op1[i]),
... | 7.255631 |
module two_bit_adder (
sum,
carryout,
S0,
A0,
B0,
A1,
B1
);
input A0, B0, A1, B1;
output sum, carryout, S0;
HA HA1 (
S0,
C1,
A0,
B0
);
FA FA1 (
sum,
carryout,
A1,
B1,
C1
);
endmodule
| 6.650749 |
module tb_comparator;
reg [1:0] A, B;
wire gt, eq, lt;
integer i;
comp_2_bit dut (
A,
B,
gt,
eq,
lt
);
initial begin
$dumpfile("2 bit comp.vcd");
$dumpvars(0, tb_comparator);
for (i = 0; i < 4; i = i + 1) begin
A = i;
B = i + 1;
#20;
end
fo... | 6.843472 |
module fulladder (
input x,
input y,
input cin,
output A,
output cout
);
assign {cout, A} = cin + y + x;
endmodule
| 7.454465 |
module nand2 (
Y,
A,
B
);
output Y;
input A, B;
supply0 GND;
supply1 PWR;
pmos (Y, PWR, A);
pmos (Y, PWR, B);
nmos (Y, w1, A);
nmos (w1, GND, B);
endmodule
| 9.113032 |
module mux2 (
input a,
b,
s,
output x
);
assign x = s ? b : a;
endmodule
| 7.816424 |
module TriState_TB ();
reg aa = 0, enable = 0;
wire yy;
integer i;
Tri_State UUT (
aa,
enable,
yy
);
initial begin
//examing To 1 worst case senario:
#20 enable = 1;
#20 aa = 1;
#20 aa = 0;
#20 enable = 0;
#25 $stop;
end
endmodule
| 6.982755 |
module top_module (
input [2:0] a,
b,
input cin,
output [2:0] cout,
output [2:0] sum
);
FA FA1 (
a[0],
b[0],
cin,
cout[0],
sum[0]
);
FA FA2 (
a[1],
b[1],
cout[0],
cout[1],
sum[1]
);
FA FA3 (
a[2],
b[2],
cout[1],... | 7.203305 |
module FA (
input a,
b,
cin,
output cout,
sum
);
assign cout = a & b | b & cin | a & cin;
assign sum = a ^ b ^ cin;
endmodule
| 8.362615 |
module top_module (
input [1:0] sel,
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output [7:0] out
);
wire [7:0] mux_con_0, mux_con_1;
mux2 mux_inst_0 (
sel[0],
a,
b,
mux_con_0
);
mux2 mux_inst_1 (
sel[0],
c,
d,
mux_con... | 7.203305 |
module top_module (
input [15:0] a,
b,
c,
d,
e,
f,
g,
h,
i,
input [ 3:0] sel,
output [15:0] out
);
always @* begin
case (sel)
4'b0000: out = a;
4'b0001: out = b;
4'b0010: out = c;
4'b0011: out = d;
4'b0100: out = e;
4'b0101: out =... | 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
//connect ports by name
mod_a inst_1 (
.in1 (a),
.in2 (b),
.in3 (c),
.in4 (d),
.out1(out1),
.out2(out2)
);
endmodule
| 7.203305 |
module top_module (
input clk,
input reset,
output [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 4'd1;
else if (q == 4'd10) q <= 4'd1;
else q <= q + 4'd1;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk) begin
//this is an active high synchronous reset
if (reset) q <= 8'b0;
else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = a | (~a & ~b & c);
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always
);
assign out_assign = (sel_b1 == 1'b1 && sel_b2 == 1'b1) ? b : a;
always @(*) begin
if (sel_b1 == 1'b1 && sel_b2 == 1'b1) begin
out_always = b;
end else begin
... | 7.203305 |
module top_module (
input in1,
input in2,
output out
);
assign out = ~(in1 | in2);
endmodule
| 7.203305 |
module top_module (
input [99:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = ∈
assign out_or = |in;
assign out_xor = ^in;
endmodule
| 7.203305 |
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