code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module top_module (
input clk,
input areset,
input load,
input ena,
input [3:0] data,
output reg [3:0] q
);
// Asynchronous reset: Notice the sensitivity list.
// The shift register has four modes:
// reset
// load
// enable shift
// idle -- preserve q (i.e., DFFs)
always ... | 7.203305 |
module top_module (
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q
);
// This rotator has 4 modes:
// load
// rotate left
// rotate right
// do nothing
// I used vector part-select and concatenation to express a rotation.
// Edge-sensitive alway... | 7.203305 |
module top_module (
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q
);
always @(posedge clk) begin
if (load) q <= data;
else if (ena) begin
case (amount)
2'b00: q <= {q[62:0], 1'b0};
2'b01: q <= {q[55:0], 8'b0};
... | 7.203305 |
module top_module (
input clk,
input reset, // Active-high synchronous reset to 5'h1
output [4:0] q
);
always @(posedge clk) begin
if (reset) q <= 5'h1;
else q <= {q[0], q[4], q[3] ^ q[0], q[2], q[1]};
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset,
output reg [4:0] q
);
reg [4:0] q_next; // q_next is not a register
// Convenience: Create a combinational block of logic that computes
// what the next value should be. For shorter code, I first shift
// all of the values and then override the two bit ... | 7.203305 |
module top_module (
input [2:0] SW, // R
input [1:0] KEY, // L and clk
output reg [2:0] LEDR
); // Q
wire clk = KEY[0];
wire L = KEY[1];
wire [2:0] d = (L) ? SW : {LEDR[1] ^ LEDR[2], LEDR[0], LEDR[2]};
always @(posedge clk) begin
LEDR <= d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset, // Active-high synchronous reset to 32'h1
output [31:0] q
);
reg [31:0] q_next;
always @(*) begin
q_next = q[31:1]; // Shift all the bits. This is incorrect for q_next[4] and q_next[2]
q_next[31] = q[0]; // Give q_next[4] and q_next[2] their correc... | 7.203305 |
module top_module (
input clk,
input resetn, // synchronous reset
input in,
output out
);
reg [3:0] Q;
assign out = Q[0];
always @(posedge clk) begin
if (~resetn) Q <= 4'd0;
else Q <= {in, Q[3:1]};
end
endmodule
| 7.203305 |
module top_module (
input [3:0] SW,
input [3:0] KEY,
output [3:0] LEDR
); //
wire [3:0] w_input = {KEY[3], LEDR[3], LEDR[2], LEDR[1]};
generate
genvar i;
for (i = 0; i < 4; i = i + 1) begin : muxdff
MUXDFF(
.clk(KEY[0]), .w(w_input[i]), .R(SW[i]), .E(KEY[1]), .L(KEY[2]), .Q(L... | 7.203305 |
module top_module (
input clk,
input enable,
input S,
input A,
B,
C,
output reg Z
);
reg [7:0] q;
// The final circuit is a shift register attached to a 8-to-1 mux.
// Create a 8-to-1 mux that chooses one of the bits of q based on the three-bit number {A,B,C}:
// There are many... | 7.203305 |
module top_module (
input clk,
input load,
input [511:0] data,
output reg [511:0] q
);
always @(posedge clk) begin
if (load) q <= data; // Load the DFFs with a value.
else begin
// At each clock, the DFF storing each bit position becomes the XOR of its left neighbour
// and its r... | 7.203305 |
module top_module (
input clk,
input load,
input [511:0] data,
output [511:0] q
);
always @(posedge clk) begin
if (load) q <= data;
else q <= q ^ {q[510:0], 1'b0} | q & ~{1'b0, q[511:1]};
end
endmodule
| 7.203305 |
module top_module (
input clk,
input load,
input [255:0] data,
output [255:0] q
);
reg [255:0] temp;
wire [287:0] map = {temp[15:0], temp, temp[255:240]};
int count;
always @(posedge clk) begin
if (load) begin
q <= data;
end else begin
for (int i = 16; i < 272; i = i + 1) b... | 7.203305 |
module top_module (
input clk,
input in,
input areset,
output out
);
// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
// It doesn't really matter what assignment is used, as long as they're unique.
parameter A = 0, B = 1;
reg state; // Ensure state and next a... | 7.203305 |
module top_module (
input clk,
input areset,
input bump_left,
input bump_right,
output walk_left,
output walk_right
);
// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
// It doesn't really matter what assignment is used, as long as they're unique.
param... | 7.203305 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah
);
parameter L = 0, R = 1, LF = 2, RF = 3;
reg [1:0] state, next_state;
always @(*) begin
... | 7.203305 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter L = 0, R = 1, LF = 2, RF = 3, LD = 4, RD = 5;
re... | 7.203305 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter L = 0, R = 1, LF = 2, RF = 3, LD = 4, RD = 5, SP =... | 7.203305 |
module top_module (
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2
);
always @(*) begin
next_state[0] = (state[0] | state[1] | state[2] | state[3] | state[4] | state[7] | state[8] | state[9]) & ~in;
next_state[1] = (state[8] | state[9] | state[0]) & in;
... | 7.203305 |
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output done
); //
parameter init = 0, read = 1, d = 2;
reg [1:0] state, next;
int cnt;
// State transition logic (combinational)
always @(*) begin
case (state)
init: next = (in[3]) ? read : init;
... | 7.203305 |
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output [23:0] out_bytes,
output done
); //
parameter B1 = 0, B2 = 1, B3 = 2, d = 3;
reg [1:0] state, next;
// FSM from fsm_ps2
always @(*) begin
case (state)
B1: next = (in[3]) ? B2 : B1;
B2:... | 7.203305 |
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output done
);
parameter i = 0, r = 1, d = 2, e = 3;
reg [1:0] state, next;
int cnt;
always @(*) begin
case (state)
i: next = (~in) ? r : i;
r: next = (cnt == 9 && in) ? d : (cnt == 9 && ~in) ? e : r;... | 7.203305 |
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
parameter i = 0, r = 1, d = 2, e = 3;
reg [1:0] state, next;
int cnt;
always @(*) begin
case (state)
i: next = (~in) ? r : i;
r: next = (cnt == 9 && in) ? d... | 7.203305 |
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
parameter i = 0, r = 1, d = 2, e = 3, dp = 4;
reg [2:0] state, next;
reg odd;
parity p_check (
clk,
~(state == r),
in,
odd
);
int cnt;
alway... | 7.203305 |
module declaration syntax here:
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
reg out;
// Fill in state name declarations
parameter A=0, B=1;
reg present_state, next_state;
always @(posedge clk) begin
... | 6.89453 |
module top_module (
input clk,
input reset, // Synchronous reset
input in,
output disc,
output flag,
output err
);
parameter i = 0, one = 1, two = 2, thr = 3, four = 4, fiv = 5, six = 6, er = 7, ds = 8, flg = 9;
reg [3:0] state, next;
always @(*) begin
case (state)
i: next ... | 7.203305 |
module top_module (
input clk,
input aresetn, // Asynchronous active-low reset
input x,
output z
);
parameter a = 0, b = 1, c = 2;
reg [1:0] state, next;
always @(*) begin
case (state)
a: next = (x) ? b : a;
b: next = (x) ? b : c;
c: next = (x) ? b : a;
endcase
en... | 7.203305 |
module top_module (
input clk,
input aresetn,
input x,
output reg z
);
// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
// It doesn't really matter what assignment is used, as long as they're unique.
parameter S = 0, S1 = 1, S10 = 2;
reg [1:0] state, next; // Ma... | 7.203305 |
module top_module (
input clk,
input areset,
input x,
output z
);
parameter a = 0, b = 1, c = 2;
reg [1:0] state, next;
always @(*) begin
case (state)
a: next = (x) ? b : a;
b: next = (x) ? c : b;
c: next = (x) ? c : b;
endcase
end
always @(posedge clk or posedg... | 7.203305 |
module top_module (
input clk,
input areset,
input x,
output z
);
parameter a = 0, b = 1;
reg state, next;
always @(*) begin
case (state)
a: next = (x) ? b : a;
b: next = b;
endcase
end
always @(posedge clk or posedge areset) begin
if (areset) state <= a;
else ... | 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
input s,
input w,
output z
);
parameter a = 0, b = 1;
reg state, next;
always @(*) begin
case (state)
a: next = (s) ? b : a;
b: next = b;
endcase
end
always @(posedge clk) begin
if (reset) state... | 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
input x,
output z
);
parameter A = 0, B = 1, C = 2, D = 3, E = 4;
reg [2:0] state, next;
always @(*) begin
case (state)
A: next = (~x) ? A : B;
B: next = (~x) ? B : E;
C: next = (~x) ? C : B;
D: next... | 7.203305 |
module top_module (
input clk,
input [2:0] y,
input x,
output Y0,
output z
);
reg [2:0] state, next;
parameter A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100;
always @(*) begin
case (y)
A: next = (~x) ? A : B;
B: next = (~x) ? B : E;
C: next = (~x) ? C : B;
... | 7.203305 |
module top_module (
input [3:1] y,
input w,
output Y2
);
parameter E = 3'b100, F = 3'b101, D = 3'b011, C = 3'b010, B = 3'b001;
assign Y2 = (y == B) || (y == F) || (y == C && w) || (y == E && w);
endmodule
| 7.203305 |
module top_module (
input [6:1] y,
input w,
output Y2,
output Y4
);
assign Y2 = y[1] && ~w;
assign Y4 = (y[2] | y[3] | y[5] | y[6]) && w;
endmodule
| 7.203305 |
module top_module (
input clk,
input reset, // synchronous reset
input w,
output z
);
parameter A = 0, B = 1, C = 2, D = 3, E = 4, F = 5;
reg [3:0] state, next;
always @(*) begin
case (state)
A: next = (w) ? A : B;
B: next = (w) ? D : C;
C: next = (w) ? D : E;
D: ... | 7.203305 |
module top_module (
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out
); //
parameter OFF = 0, ON = 1;
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
OFF: next_state = (j) ? ON : OFF;
ON: next_stat... | 7.203305 |
module top_module (
input clk,
input reset, // synchronous reset
input w,
output z
);
parameter A = 0, B = 1, C = 2, D = 3, E = 4, F = 5;
reg [3:0] state, next;
always @(*) begin
case (state)
A: next = (~w) ? A : B;
B: next = (~w) ? D : C;
C: next = (~w) ? D : E;
... | 7.203305 |
module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
assign Y1 = (y[0]) & w;
assign Y3 = (y[1] | y[2] | y[4] | y[5]) & ~w;
endmodule
| 7.203305 |
module top_module (
input clk,
input resetn, // active-low synchronous reset
input [3:1] r, // request
output [3:1] g // grant
);
wire r1, r2, r3, g1, g2, g3;
assign {r3, r2, r1} = r;
assign g = {g3, g2, g1};
parameter A = 0, B = 1, C = 2, D = 3;
reg [1:0] state, next;
always @(*) begin... | 7.203305 |
module logic_gates(oY, iA, iB, iC);
output oY;
input iA,iB,iC;
...
endmodule
| 7.336286 |
module top_module (
input clk,
input reset,
output reg [9:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else if (q == 10'd999) q <= 0;
else q <= q + 1;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input shift_ena,
input count_ena,
input data,
output [3:0] q
);
always @(posedge clk) begin
if (shift_ena) begin
q <= {q[2:0], data};
end else if (count_ena) begin
q <= q - 1'b1;
end
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output start_shifting
);
parameter A = 0, B = 1, C = 2, D = 3, E = 4;
reg [2:0] state, next;
always @(*) begin
case (state)
A: next = (data) ? B : A;
B: next = (data) ? C : A;
C: next =... | 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
output shift_ena
);
parameter A = 0, B = 1, C = 2, D = 3, E = 4;
reg [2:0] state, next;
always @(*) begin
case (state)
A: next = (reset) ? B : A;
B: next = (reset) ? B : C;
C: next = (reset) ? B : D;
D... | 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output shift_ena,
output counting,
input done_counting,
output done,
input ack
);
parameter S = 0, S1 = 1, S11 = 2, S110 = 3, B0 = 4, B1 = 5, B2 = 6, B3 = 7, cnt = 8, hold = 9;
reg [3:0] state... | 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output [3:0] count,
output counting,
output done,
input ack
);
parameter S=0,S1=1,S11=2,S110=3, B0=4, B1=5, B2=6, B3=7, cnt=8, delay_cnt=9, last_cnt=10, hold=11;
reg ... | 7.203305 |
module top_module (
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
); //
// You may use t... | 7.203305 |
module dff2 (
clock,
reset,
d,
q
);
input clock, reset, d;
output q;
reg q;
always @(posedge clock or negedge reset) begin
if (!reset) q <= 0;
else q <= d;
end
endmodule
| 6.764726 |
module logic_gates(oY, iA, iB, iC);
output oY;
inputiA,iB,iC;
wire andl, and2 //连接线
and(and1, iA, iB);
and(and2, iA, iC);
or(oY, andl, and2)
endmodule
| 7.336286 |
module logic_gates(oY, iA, iB, iC);
output oY;
inputiA,iB,iC;
assign oY=(iA&iB)|(iA&iC);
endmodule
| 7.336286 |
module fsm_eg_mult_seg
(
input wire clk, reset,
input wire a, b,
output wire y0, y1
);
//符号状态声明
localparam [1: 0] s0=2'b00,
s1=2'b01,
s2=2'b10;
//信号声明
reg [1: 0] state_reg, state_next;
//状态寄存器
always@ (posedge clk, posedge reset)
begin
if (reset)
state_reg <= s0;
else
state_reg <= state_next;
end
//下一状态逻辑
alw... | 7.419378 |
module fsm_eg_2_seg
{
input wire clk, reset,
input wire a, b ,
output reg y0, yi
};
//符号状态声明
localparam [1: 0] s0 =2'b00,
s1=2'b01,
s2=2'b10;
//信号声明
reg [1: 0] state_reg, state_next;//状态寄存器
always @(posedge clk, posedge reset)begin
if (reset)
state_reg<= s0;
else
state_reg<=state_next;
end
//下ー状态逻辑和输出逻辑
al... | 8.234733 |
module edge_detect_moore
{
input wire clk, reset,
input wire level,
output reg tick
}
//符号状态声明
localparam [1: 0]
zero =2'b00,
eda=2'b01,
one =2'b10;//信号声明
reg [1: 0] state_reg, state_next;//状态寄存器
always@(posedge clk, posedge reset)
begin
if (reset)state_reg <= zero;
else
state_reg <=state_next;
end
//下一状态逻辑和... | 8.503577 |
module edge_detect_mealy
{
input wire clk, reset,
input wire level,
output reg tick
}
//符号状态声明
local param zero=1'b0,
one=1'b1;
reg state_reg, state_next;//状态寄存器
always@(posedge clk, posedge reset)
begin
if (reset)state_reg <= zero;
else
state_reg <=state_next;
end
//下一状态逻辑和输出逻辑
always@*
begin
state_next=s... | 8.503577 |
module edge_detect_gate (
input wire clk,
reset,
input wire level,
output wire tick
);
reg delay_reg;
always @(posedge clk, posedge reset) begin
if (reset) delay_reg <= 1'b0;
else delay_reg <= level;
end
assign tick = ~delay_reg & level;
endmodule
| 7.357013 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output reg walk_left,
output reg walk_right,
output reg aaah,
output reg digging
);
reg walk_temp[1:0];
initial begin
walk_... | 7.203305 |
module top_module (
input clk,
input a,
input b,
output wire out_assign,
output reg out_always_comb,
output reg out_always_ff
);
assign out_assign = a ^ b;
always @(*) begin
out_always_comb = a ^ b;
end
always @(posedge clk) begin
out_always_ff <= a ^ b;
end
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input reset, // Synchronous active-high reset
input w,
output z
);
parameter A = 3'b000;
parameter B = 3'b001;
parameter C = 3'b010;
parameter D = 3'b011;
parameter E = 3'b100;
parameter F = 3'b101;
reg [2:0] cstate, nstate;
always @(posedge clk) beg... | 7.203305 |
module top_module (
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always
);
assign out_assign = ({sel_b2, sel_b1} == 2'b11) ? b : a;
always @(*) begin
if ({sel_b2, sel_b1} == 2'b11) out_always = b;
else out_always = a;
end
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
assign Y1 = w && y[0];
assign Y3 = (~w) && (y[1] || y[2] || y[4] || y[5]);
endmodule
| 7.203305 |
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving
); //
always @(*) begin
if (cpu_overheated) shut_off_computer = 1;
else begin
shut_off_computer = 0;
end
end
always @(*) begi... | 7.203305 |
module CLA2 (
input [1:0] iG,
input [1:0] iP,
input iC,
output oG,
output oP,
output [2:0] oC
);
assign oC[0] = iC;
assign oC[1] = iG[0] | (iP[0] & oC[0]);
assign oG = iG[1] | (iP[1] & iG[0]);
assign oP = iP[1] & iP[0];
assign oC[2] = oG | (oP & oC[0]);
endmodule
| 7.086682 |
module CLA4 (
input [3:0] iG,
input [3:0] iP,
input iC,
output oG,
output oP,
output [4:0] oC
);
assign oC[0] = iC;
assign oC[1] = iG[0] | (iP[0] & oC[0]);
assign oC[2] = iG[1] | (iP[1] & iG[0]) | (iP[1] & iP[0] & oC[0]);
assign oC[3] = iG[2] | (iP[2] & iG[1]) | (iP[2] & iP[1] & iG[0]) ... | 7.783567 |
module Adder4 (
input [3:0] iA,
input [3:0] iB,
input iC,
output [3:0] oS,
output oG,
output oP,
output oC
);
wire [3:0] G = iA & iB;
wire [3:0] P = iA | iB;
wire [3:0] C;
CLA4 cla (
.iG(G),
.iP(P),
.iC(iC),
.oG(oG),
.oP(oP),
.oC({oC, C})
);
... | 7.84746 |
module Adder8 (
input [7:0] iA,
input [7:0] iB,
input iC,
output [7:0] oS,
output oG,
output oP,
output oC
);
wire [1:0] G;
wire [1:0] P;
wire [1:0] C;
Adder4 adder0 (
.iA(iA[3:0]),
.iB(iB[3:0]),
.iC(C[0]),
.oS(oS[3:0]),
.oG(G[0]),
.oP(P[0])
);... | 8.497707 |
module Adder16 (
input [15:0] iA,
input [15:0] iB,
input iC,
output [15:0] oS,
output oG,
output oP,
output oC
);
wire [3:0] G;
wire [3:0] P;
wire [3:0] C;
Adder4 adder0 (
.iA(iA[3:0]),
.iB(iB[3:0]),
.iC(C[0]),
.oS(oS[3:0]),
.oG(G[0]),
.oP(P[0])
... | 8.053466 |
module Adder32 (
input [31:0] iA,
input [31:0] iB,
input iC,
output [31:0] oS,
output oG,
output oP,
output oC
);
wire [1:0] G;
wire [1:0] P;
wire [1:0] C;
Adder16 adder0 (
.iA(iA[15:0]),
.iB(iB[15:0]),
.iC(C[0]),
.oS(oS[15:0]),
.oG(G[0]),
.oP(P[... | 7.953506 |
module alu (
a,
b,
opcode,
c
);
output signed [31:0] c;
//output zero;
//output overflow;
//output neg;
input signed [31:0] a, b;
input [2:0] opcode;
reg [32:0] reg_C;
//reg zf;
//reg nf;
reg [31:0] reg_A, reg_B;
parameter sla = 3'b000, srai = 3'b001;
always @(a, b, opcode... | 6.634214 |
module mux4x1 (
input [31:0] a,
input [31:0] b,
input [31:0] c,
input [31:0] d,
input [1:0] sel,
output reg [31:0] y
);
always @(sel or a or b or c or d) begin
begin : mux4x1
case (sel)
2'b00: y = a;
2'b01: y = b;
2'b10: y = c;
2'b11: y = d;
endc... | 6.791623 |
module adder1b (
input a,
input b,
input c,
output s,
output cout
);
assign s = a ^ b ^ c;
assign cout = (a & b) | (b & c) | (c & a);
endmodule
| 8.20245 |
module zeroextend (
input a,
output [31:0] b
);
assign b[0] = a;
assign b[31:1] = 31'd0;
endmodule
| 8.72426 |
module main (
input [31:0] a,
input [31:0] b,
input [2:0] f,
output cout,
output [31:0] y,
output of,
output reg zf
);
wire [31:0] bout;
wire [31:0] orgate;
wire [31:0] andgate;
wire [31:0] temp;
wire [31:0] s;
mux2x1 mx (
b,
~b,
f[2],
bout
);
assign ... | 7.081372 |
module Adder32bit (
A,
B,
Sum
);
input [31:0] A, B;
output reg [31:0] Sum;
always @(*) begin
Sum <= A + B;
end
endmodule
| 8.498695 |
module decoder (
fetchoutput,
destination,
operationnumber,
source_1,
source_2,
unsigned_1,
unsigned_2,
unsigned_3,
unsigned_4,
unsigned_5,
signed_1,
signed_2,
signed_3,
flush,
super_duper_a,
super_duper_b
);
// Inputs & Putputs //
output [05:00] des... | 7.018254 |
module testbench_32BFA;
reg [31:0] A, B;
reg CarryIn;
wire [31:0] Sum;
wire Carry;
integer i, j;
FADDER32 mod (
Sum,
Carry,
A,
B,
CarryIn
);
initial begin
$monitor($time, " A = %b, B = %b, Carry In = %b, Carry = %b, Sum = %b.", A, B, CarryIn, Carry,
Sum);
... | 6.607722 |
module a_32bitRegester_tb;
wire q;
reg c, l, r;
reg [31:0] d;
bit32_regester b (
q,
c,
l,
d,
r
);
initial begin
#5 d = 'h00000000;
r = 'b1;
l = 'b0;
#5 c = 'b0;
#5 c = 'b1;
#5 golden(q, 'h00000000, l, d, r);
#5;
#5 d = 'h00000001;
r = 'b0;
... | 6.679986 |
module fulladdr_1_bit (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
xor (w1, a, b);
xor (sum, w1, c_in);
and (w2, a, b);
and (w3, w1, c_in);
or (c_out, w2, w3);
endmodule
| 7.174501 |
module fulladdr_4_bit (
sum,
c_out,
a,
b,
c_in
);
input [3:0] a, b;
input c_in;
output [3:0] sum;
output c_out;
wire w1, w2, w3;
fulladdr_1_bit fa0 (
sum[0],
w1,
a[0],
b[0],
c_in
);
fulladdr_1_bit fa1 (
sum[1],
w2,
a[1],
b[1],
... | 7.111335 |
module fulladdr_16_bit (
sum,
c_out,
a,
b,
c_in
);
input [15:0] a, b;
input c_in;
output [15:0] sum;
output c_out;
wire w1, w2, w3;
fulladdr_4_bit fa4_0 (
sum[3:0],
w1,
a[3:0],
b[3:0],
c_in
);
fulladdr_4_bit fa4_1 (
sum[7:4],
w2,
a[7... | 6.986683 |
module fulladdr_32_bit (
sum,
c_out,
a,
b,
c_in
);
input [31:0] a, b;
input c_in;
output [31:0] sum;
output c_out;
wire w1;
fulladdr_16_bit fa16_0 (
sum[15:0],
w1,
a[15:0],
b[15:0],
c_in
);
fulladdr_16_bit fa16_1 (
sum[31:16],
c_out,
... | 7.255391 |
module mux8x1 (
input in0,
input in1,
input in2,
input in3,
input in4,
input in5,
input [2:0] sel,
output reg muxOut
);
always @(sel, in0, in1, in2, in3, in4, in5)
case (sel)
3'b000: muxOut = in0;
3'b001: muxOut = in1;
3'b010: muxOut = in2;
3'b011: muxOut = ... | 7.340408 |
module Adder32Bit (
input1,
input2,
out,
overflowBit
);
input [31:0] input1, input2;
output [31:0] out;
reg [31:0] out;
output overflowBit;
reg overflowBit;
always @(input1 or input2) begin
{overflowBit, out} = input1 + input2;
end
endmodule
| 7.363356 |
module ripple_carry_adder #(
parameter WIDTH = 32
) (
input [WIDTH-1:0] input_a,
input [WIDTH-1:0] input_b,
input carry_in,
output [WIDTH-1:0] final_sum,
output carry_out
);
wire [ WIDTH:0] carry;
wire [WIDTH-1:0] incr_sum;
// First full-adder has cin as logic 0
assign carry_in = 1'b0... | 7.682509 |
module CLA_32_4 (
input [31:0] a_inp,
input [31:0] b_inp,
output reg [31:0] s_out,
output reg c_out,
input clock,
input reset
);
wire Cin_1, Cin_2, Cin_3, Cin_4, Cin_5, Cin_6, Cin_7, Cin_8;
wire Cout_1, Cout_2, Cout_3, Cout_4, Cout_5, Cout_6, Cout_7,... | 7.993192 |
module CLA_32_4_tb ();
reg [31:0] A = 0, B = 0;
wire [31:0] Sum;
wire Cout;
reg reset, clock;
initial begin : A_TB
A = 0;
#10 A = 32'h00FF_00FF;
#30 A = 32'h0000_0000; // Making input = 0 so that next transition can be noted
#30 A = 32'h8080_8080;
#30 A = 32'h0000_0000; // Making inp... | 7.828759 |
module gf2m #(
parameter DIGITAL = 32,
parameter DATA_WIDTH = 163
) (
input wire rst,
input wire clk,
input wire start,
input wire [DATA_WIDTH - 1 : 0] a,
input wire [DATA_WIDTH - 1 : 0] g,
input wire [DIGITAL - 1:0] b,
output reg [DATA_WIDTH - 1 : 0] t_i_j,
output reg done
);
... | 7.196913 |
module top_module (
input clk,
input reset, // Active-high synchronous reset to 32'h1
output [31:0] q
);
reg [31:0] d;
assign d[31:0] = {q[0], q[31:23], q[22] ^ q[0], q[21:3], q[2] ^ q[0], q[1] ^ q[0]};
always @(posedge clk) begin
if (reset) q <= 32'h1;
else q <= d;
end
endmodule
| 7.203305 |
module DataReg(Q,D,Le,Clk);
// BUS width
parameter DATA_WIDTH = 32;
// Outputs
output reg [DATA_WIDTH-1:0]Q;
// Inputs
input[DATA_WIDTH-1:0]D;
input Le,Clr,Clk;
always @ (posedge Clk,)
if (Le) Q <= D;
endmodule
| 7.028105 |
module kpg_init (
output reg out1,
out0,
input a,
b,
clk
);
always @(posedge clk)
case ({
a, b
})
2'b00: begin
out0 = 1'b0;
out1 = 1'b0;
end
2'b11: begin
out0 = 1'b1;
out1 = 1'b1;
end
default: begin
out0 = 1'b0;
... | 6.603491 |
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