code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tbRegFile32;
reg Clock, Reset, RegWrite;
reg [4:0] ReadReg1, ReadReg2, WriteRegNo;
reg [31:0] WriteData;
wire [31:0] ReadData1, ReadData2;
RegFile_32 rgf (
ReadData1,
ReadData2,
Clock,
Reset,
RegWrite,
ReadReg1,
ReadReg2,
WriteRegNo,
WriteData
);
... | 6.672416 |
module fpga_gf2m #(
parameter DIGITAL = 32,
parameter DATA_WIDTH = 163
) (
input clk, // Clock
input rst, // Asynchronous reset active low
input wire start,
input wire [DATA_WIDTH - 1 : 0] a,
input wire [DATA_WIDTH - 1 : 0] g,
input wire [BWIDTH - 1:0] b,
output reg [DATA_WIDTH - 1... | 6.91314 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0]... | 6.504296 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0]... | 6.504296 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module encoder_32_5 (
output reg [4:0] S,
input wire [31:0] i,
input wire [15:0] RegIn,
input wire inport1Enable,
input wire clk
);
reg [31:0] comboSig;
always @(clk) begin
comboSig[15:0] <= RegIn;
comboSig[25:16] <= i[25:16];
comboSig[26] <= inport1Enable;
comboSig[31:27] <= 0;
... | 7.61766 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module adder32 (
result,
a,
b
);
input [31:0] a;
input [31:0] b;
output [31:0] result;
wire [32:0] sum = {1'b0, a} + {1'b0, b};
assign result = sum[32] ? sum[32:1] : sum[31:0];
endmodule
| 8.194085 |
module top_module (
input clk,
input resetn, // active-low synchronous reset
input [3:1] r, // request
output [3:1] g // grant
);
parameter A = 0, B = 1, C = 2, D = 3;
reg [1:0] cstate, nstate;
always @(posedge clk) begin
if (!resetn) begin
cstate <= A;
end else begin
csta... | 7.203305 |
module test_seq_tb ();
reg clk;
reg rst_n;
wire din;
wire dout;
reg [23:0] data;
assign din = data[23];
initial begin
clk = 0;
rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;
data = 24'b1010_0101_1001_0101_0100_1001;
end
always #2 clk = ~clk;
always @(posedge clk) begin
data = {... | 7.106176 |
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
); //
always @(*) begin // This is a combinational circuit
case (sel)
3'b000: out = data0;
3'b... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input resetn, // active-low synchronous reset
input x,
input y,
output f,
output g
);
parameter IDLE = 0, F0 = 1, F1 = 2;
parameter X0 = 3, X1 = 4, X2 = 5;
parameter Y0 = 6, Y1 = 7;
parameter Y00 = 8, Y01 = 9;
reg [3:0] cstate, nstate;
always @(... | 7.203305 |
module test_mod3 (
clk,
rst_n,
din,
dout
);
input clk;
input rst_n;
input din;
output reg dout;
reg [1:0] state, next_state;
parameter idle = 2'b00, s1 = 2'b01, s2 = 2'b10, s3 = 2'b11;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) state <= idle;
else state <= next_stat... | 6.709397 |
module top_module (
input [3:0] in,
output reg [1:0] pos
);
always @(*) begin
case (in)
4'b0000: pos = 2'b00;
4'b0001: pos = 2'b00;
4'b0010: pos = 2'b01;
4'b0011: pos = 2'b00;
4'b0100: pos = 2'b10;
4'b0101: pos = 2'b00;
4'b0110: pos = 2'b01;
4'b0111: pos = ... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module test_level_pluse (
clk,
rst_n,
din,
dout
);
input clk;
input rst_n;
input din;
output dout;
reg d1, d2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
d1 <= 1'b0;
d2 <= 1'b0;
end else begin
d1 <= din;
d2 <= d1;
end
end
assign ... | 6.881229 |
module test_level_pluse_tb ();
reg clk;
reg rst_n;
reg din;
wire dout;
initial begin
clk = 0;
rst_n = 1;
din = 0;
#10 rst_n = 0;
#10 rst_n = 1;
#20 din = 0;
#20 din = 1;
#20 din = 0;
#20 din = 1;
#20 $stop;
end
always #2 clk <= ~clk;
test_level_pluse dut... | 6.881229 |
module top_module (
input [7:0] in,
output reg [2:0] pos
);
always @(*) begin
casez (in)
8'bzzzzzzz1: pos = 0;
8'bzzzzzz1z: pos = 1;
8'bzzzzz1zz: pos = 2;
8'bzzzz1zzz: pos = 3;
8'bzzz1zzzz: pos = 4;
8'bzz1zzzzz: pos = 5;
8'bz1zzzzzz: pos = 6;
8'b1zzzzzzz: p... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
always @(*) begin
left = 0;
down = 0;
right = 0;
up = 0;
case (scancode)
16'he06b: left = 1;
16'he072: down = 1;
16'he074: right = 1;
16'he07... | 7.203305 |
module Bit36Adder (
a,
b,
cin,
sum,
cout
);
input [36:1] a, b;
input cin;
output [36:1] sum;
output cout;
wire w1, w2;
Bit16Adder B16A_0 (
a[16:1],
b[16:1],
cin,
sum[16:1],
w1
);
Bit16Adder B16A_1 (
a[32:17],
b[32:17],
w1,
sum[3... | 6.866082 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module test_div3 (
clkin,
rst_n,
clkout
);
input clkin;
input rst_n;
output clkout;
reg [1:0] count1, count2;
reg pos, neg;
always @(posedge clkin or negedge rst_n) begin
if (!rst_n) begin
count1 <= 2'd0;
pos <= 1'b0;
end else begin
case (count1)
2'd0: begin
... | 6.747281 |
module top_module (
input [7:0] a,
b,
c,
d,
output [7:0] min
); //
wire [7:0] min_temp1;
wire [7:0] min_temp2;
// assign intermediate_result1 = compare? true: false;
assign min_temp1 = (a <= b) ? a : b;
assign min_temp2 = (c <= d) ? c : d;
assign min = (min_temp1 <= min_temp2) ? min_t... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module test_div3_v2 (
clkin,
rst_n,
clkout
);
input clkin;
input rst_n;
output clkout;
reg pos, neg;
reg [1:0] cnt1, cnt2;
always @(posedge clkin or negedge rst_n) begin
if (!rst_n) cnt1 <= 2'd0;
else begin
if (cnt1 < 2'd2) cnt1 <= cnt1 + 1'b1;
else cnt1 <= 2'd0;
end
... | 7.144119 |
module test_div3_v2_tb ();
reg clkin;
reg rst_n;
wire clkout;
initial begin
clkin = 0;
rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;
end
always #2 clkin <= ~clkin;
test_div3_v2 dut (
.clkin (clkin),
.rst_n (rst_n),
.clkout(clkout)
);
endmodule
| 6.511095 |
module top_module (
input [7:0] in,
output parity
);
assign parity = ^in;
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module test_div5 (
clkin,
rst_n,
clkout
);
input clkin;
input rst_n;
output clkout;
reg pos, neg;
reg [2:0] cnt1, cnt2;
always @(posedge clkin or negedge rst_n) begin
if (!rst_n) cnt1 <= 3'd0;
else begin
if (cnt1 < 3'd4) cnt1 <= cnt1 + 1'b1;
else cnt1 <= 3'd0;
end
end... | 7.459377 |
module test_div5_tb ();
reg clkin;
reg rst_n;
wire clkout;
initial begin
clkin = 0;
rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;
end
always #2 clkin <= ~clkin;
test_div5 dut (
.clkin (clkin),
.rst_n (rst_n),
.clkout(clkout)
);
endmodule
| 6.959045 |
module top_module (
input [99:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = ∈
assign out_or = |in;
assign out_xor = ^in;
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module fulladder (
a,
b,
c,
sum,
carry
);
input a, b, c;
output sum, carry;
assign sum = a ^ b ^ c;
assign carry = (a & b) | (b & c) | (c & a);
endmodule
| 7.454465 |
module test;
wire sum, carry;
reg a, b, c;
fulladder f1 (
a,
b,
c,
sum,
carry
);
initial begin
$dumpfile("3a_full_adder.vcd");
$dumpvars(0, test);
#5 begin
a = 0;
b = 0;
c = 0;
end
#5 begin
a = 0;
b = 0;
c = 1;
end
... | 6.964054 |
module top_module (
input [2:0] a,
b,
input cin,
output [2:0] cout,
output [2:0] sum
);
FA FA1 (
a[0],
b[0],
cin,
cout[0],
sum[0]
);
FA FA2 (
a[1],
b[1],
cout[0],
cout[1],
sum[1]
);
FA FA3 (
a[2],
b[2],
cout[1],... | 7.203305 |
module FA (
input a,
b,
cin,
output cout,
sum
);
wire w1, w2, w3, w4;
xor (w1, a, b);
xor (sum, cin, w1);
and (w2, a, b);
and (w3, b, cin);
and (w4, a, cin);
or (cout, w2, w3, w4);
endmodule
| 8.362615 |
module fulladder (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S;
output Cout;
assign S = A ^ B ^ Cin;
assign Cout = A & B + Cin & (A ^ B);
endmodule
| 7.454465 |
module adder_3bits (
input [2:0] a,
b,
input cin,
output [2:0] sum,
output co
);
wire w1, w2, w3;
full_adder x (
.a (a[0]),
.b (b[0]),
.ci(cin),
.s (sum[0]),
.co(w1)
);
full_adder y (
.a (a[1]),
.b (b[1]),
.ci(w1),
.s (sum[1]),
.... | 7.015374 |
module top_module (
input [2:0] SW, // R
input [1:0] KEY, // L and clk
output [2:0] LEDR
); // Q
reg [2:0] d;
assign d = {
KEY[1] ? SW[2] : LEDR[1] ^ LEDR[2], KEY[1] ? SW[1] : LEDR[0], KEY[1] ? SW[0] : LEDR[2]
};
always @(posedge KEY[0]) LEDR <= d;
endmodule
| 7.203305 |
module S3MUX (
flush,
stall,
x,
y
);
input flush, stall;
input [2:0] x;
output [2:0] y;
assign y = ((flush || stall) == 1) ? 0 : x;
endmodule
| 7.124145 |
module three_b_bc_tb;
wire y_out;
reg x_in, clock, reset;
three_b_bc dut (.*);
initial #200 $finish;
initial begin
reset = 0;
clock = 0;
#5 reset = 1;
repeat (32) #5 clock = ~clock;
end
initial begin
x_in = 0;
#15 x_in = 1;
repeat (16) #10 x_in = ~x_in;
end
endmodule
| 6.776646 |
module fullsubtractor (
x,
y,
z,
d,
b
);
input x, y, z;
output d, b;
assign d = x ^ y ^ z;
assign b = ~x & z | ~x & y | y & z;
endmodule
| 6.741456 |
module ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ///... | 8.238592 |
module top_module (
input clk,
input enable,
input S,
input A,
B,
C,
output Z
);
reg [7:0] q;
wire [2:0] n;
assign n = {A, B, C};
always @(posedge clk) begin
if (enable) q <= {q[6:0], S};
else q <= q;
end
assign Z = q[n];
endmodule
| 7.203305 |
module MAC3 (
//numbers
input wire [7:0] W1,
input wire [7:0] I1,
input wire [7:0] W2,
input wire [7:0] I2,
input wire [7:0] W3,
input wire [7:0] I3,
output reg [7:0] OUTPUT,
//control
input wire CLK,
input wire EN,
input wire RST
);
wire mul1out;
wire mul2ou... | 8.045542 |
module baudgen (
input wire clk,
output wire ser_clk
);
localparam lim = (`CLKFREQ / `BAUD) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk) counter <= ser_clk ? 0 : (counter + 1);
endmodule
| 7.298257 |
module baudgen2 (
input wire clk,
input wire restart,
output wire ser_clk
);
localparam lim = (`CLKFREQ / (2 * `BAUD)) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk)
if (restart) counter <= 0;
... | 7.26565 |
module uart (
input wire clk,
input wire resetq,
output wire uart_busy, // High means UART is transmitting
output reg uart_tx, // UART transmit wire
input wire uart_wr_i, // Raise to transmit byte
input wire [7:0] uart_dat_i
);
reg [3:0] bitcount; // 0 means idle, so this is a 1... | 7.01014 |
module rxuart (
input wire clk,
input wire resetq,
input wire uart_rx, // UART recv wire
input wire rd, // read strobe
output wire valid, // has data
output wire [7:0] data
); // data
reg [4:0] bitcount;
reg [7:0] shifter;
// bitcount == 11111... | 6.632783 |
module buart (
input wire clk,
input wire resetq,
input wire rx, // recv wire
output wire tx, // xmit wire
input wire rd, // read strobe
input wire wr, // write strobe
output wire valid, // has recv data
output wi... | 8.065655 |
module outpin (
input clk,
output pin,
input we,
input wd,
output rd
);
SB_IO #(
.PIN_TYPE(6'b0101_01)
) _io (
.PACKAGE_PIN(pin),
.CLOCK_ENABLE(we),
.OUTPUT_CLK(clk),
.D_OUT_0(wd),
.D_IN_0(rd)
);
endmodule
| 7.044247 |
module third_register (
input [31:0] WriteDataE,
input [31:0] ALUResult,
input [31:0] PCPlus4E,
input [ 4:0] RdE,
input clk,
input rst,
input RegWriteE,
input MemWriteE,
input [ 1:0] ResultSrcE,
output reg [... | 7.344693 |
module pipe_3stage (
out,
in,
clk
);
input in, clk;
output reg out;
reg pipe1, pipe2, pipe3, pipe4;
always @(posedge clk) begin
pipe1 <= in;
pipe2 <= pipe1;
pipe3 <= pipe2;
pipe4 <= pipe3;
out <= pipe4;
end
endmodule
| 6.580929 |
module pipe_3stage_address (
out,
in,
clk
);
input [7:0] in;
input clk;
output reg [7:0] out;
reg [7:0] pipe1, pipe2, pipe3, pipe4;
always @(posedge clk) begin
pipe1 <= in;
pipe2 <= pipe1;
pipe3 <= pipe2;
pipe4 <= pipe3;
out <= pipe4;
end
endmodule
| 7.1017 |
module pipe_3stage_data (
out,
in,
clk
);
input [29:0] in;
input clk;
output reg [29:0] out;
reg [29:0] pipe1, pipe2, pipe3;
always @(posedge clk) begin
pipe1 <= in;
//pipe2<=pipe1;
//pipe3<=pipe2;
out <= pipe1;
end
endmodule
| 6.781458 |
module testbench;
wire [63:0] producto;
wire [31:0] a, b, c;
tester test (
clk,
reset,
a,
b,
c,
ack,
Done_Flag,
producto,
valid_data
);
multiplicador3 imul (
producto,
Done_Flag,
a,
b,
c,
clk,
reset,
valid_... | 7.015571 |
module simon_parallel (
clk,
data_ina,
data_inb,
data_inc,
data_rdy,
cipher_outa,
cipher_outb,
cipher_outc,
Trig,
Done
);
input clk, data_ina, data_inb, data_inc;
input [1:0] data_rdy;
output cipher_outa, cipher_outb, cipher_outc;
output reg Trig, Done;
wire keya, key... | 7.587745 |
module sasebo_simon (
Din,
Dout,
Drdy,
Dvld,
EN,
BSY,
CLK,
RSTn,
Trig
);
//------------------------------------------------
input [(128*6)-1:0] Din; // Data input
output [127:0] Dout; // Data output
input Drdy; // Data input ready
output Dvld; // Data output valid
i... | 8.20872 |
module TopModule_tb;
// Inputs
reg [767:0] Din;
reg Drdy;
reg EN;
reg CLK;
reg RSTn;
// Outputs
wire [127:0] Dout;
wire Dvld;
wire BSY;
wire Trig;
// Instantiate the Unit Under Test (UUT)
sasebo_simon uut (
.Din (Din),
.Dout(Dout),
.Drdy(Drdy),
.Dvld(Dvld),
.EN... | 8.900291 |
module put each share into isolated modules
// such that no two shares are mixed into the same slice
// to cause leakage.
//////////////////////////////////////////////////////////////////////////////////
module bitSpeck128_128_hierarchy_carry_sharing(
input clk,
input data_ina, data_inb, data_inc,
input k_da... | 7.604776 |
module share (
input clk,
we,
Start,
EN,
input share_in,
input shiftlessthan8,
shiftlessthan3,
rndlessthan32,
rnd0,
input keybit,
input Xbit_else,
Ybit_else,
carry_else,
carry_init,
output wire Xbit_mine,
Ybit_mine,
carry_mine,
output wire share_ou... | 6.598089 |
module share_roundTI (
input clk,
EN,
input keybit,
Xbit,
Ybit1,
Ybit2,
input Xbit_else,
Ybit_else,
carry_else,
carry_init,
output X_out,
Y_out,
output reg carry
);
assign X_out = carry ^ Xbit ^ Ybit1 ^ keybit;
assign Y_out = X_out ^ Ybit2;
always @(posedge cl... | 7.613275 |
module key_share (
input clk,
we,
Start,
EN,
input share_in,
input shiftlessthan8,
shiftlessthan3,
rndlessthan32,
rnd0,
input keybit,
input Xbit_else,
Ybit_else,
carry_else,
output wire Xbit_mine,
Ybit_mine,
carry_mine
);
wire X_out, Y_out;
wire X_carr... | 7.071314 |
module key_share_roundTI (
input clk,
EN,
input keybit,
Xbit,
Ybit1,
Ybit2,
input Xbit_else,
Ybit_else,
carry_else,
output X_out,
Y_out,
output reg carry
);
assign X_out = carry ^ Xbit ^ Ybit1 ^ keybit;
assign Y_out = X_out ^ Ybit2;
always @(posedge clk) begin
... | 8.325179 |
module decoder_3to8(
input reg [2:0] in,
//Control inputs
output wire [7:0] out
);
//Going to do this naively with case statement for now, see how it synthesizes
always @ *
case(in)
3b'000: begin
out[0]=1b'1; out[1:7]=7'b0;
end
5b'001: begin
out[0]=1'b0; out[1]=1b'1; out[2:7]=6'b0;
end
5b'0... | 7.578914 |
module Reg8_1 (
out,
in,
clk,
ctrl
);
input ctrl;
output [7:0] out;
input [7:0] in;
reg [7:0] Regs;
input clk;
assign out[0] = Regs[0];
assign out[1] = Regs[1];
assign out[2] = Regs[2];
assign out[3] = Regs[3];
assign out[4] = Regs[4];
assign out[5] = Regs[5];
assign out[6] = Reg... | 6.75854 |
module Reg8_2 (
out,
in,
clk
);
output [7:0] out;
input [7:0] in;
reg [7:0] Regs;
input clk;
assign out[0] = Regs[0];
assign out[1] = Regs[1];
assign out[2] = Regs[2];
assign out[3] = Regs[3];
assign out[4] = Regs[4];
assign out[5] = Regs[5];
assign out[6] = Regs[6];
assign out[7] = ... | 6.827413 |
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